Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109930081

1

T1

149091

T2

460501

T3

2816

auto[1]

1418857

1

T1

495

T2

7261

T3

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109936520

1

T1

149091

T2

460998

T3

2618

auto[1]

1412418

1

T1

495

T2

6764

T3

495

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7753410	1			T1	6418		T2	45653		T3	766
auto[IdleSt]	22445251	1			T1	72419		T2	20357		T3	752
auto[ClkMuxSt]	36223	1			T1	68		T2	18		T3	8
auto[CntIncrSt]	35977	1			T1	68		T2	18		T3	8
auto[CntProgSt]	1765846	1			T1	3028		T2	264		T3	16
auto[TransCheckSt]	28036	1			T1	51		T2	18		T10	99
auto[TokenHashSt]	44811165	1			T1	3530		T2	199030		T10	2038
auto[FlashRmaSt]	29249	1			T1	18		T2	18		T11	46
auto[TokenCheck0St]	13026	1			T1	18		T2	18		T11	32
auto[TokenCheck1St]	9638	1			T1	13		T2	18		T11	11
auto[TransProgSt]	486272	1			T1	592		T2	245		T13	578
auto[PostTransSt]	13480625	1			T1	59065		T2	3577		T3	500
auto[ScrapSt]	352219	1			T14	3		T4	641		T23	723
auto[EscalateSt]	7296721	1			T1	4298		T2	50492		T3	1063
auto[InvalidSt]	12803289	1			T2	148024		T13	1631		T15	7634

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1991	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12803289	1			T2	148024		T13	1631		T15	7634
EscalateSt	7296721	1			T1	4298		T2	50492		T3	1063
ScrapSt	352219	1			T14	3		T4	641		T23	723
PostTransSt	13480625	1			T1	59065		T2	3577		T3	500
TransProgSt	486272	1			T1	592		T2	245		T13	578
TokenCheck1St	9638	1			T1	13		T2	18		T11	11
TokenCheck0St	13026	1			T1	18		T2	18		T11	32
FlashRmaSt	29249	1			T1	18		T2	18		T11	46
TokenHashSt	44811165	1			T1	3530		T2	199030		T10	2038
TransCheckSt	28036	1			T1	51		T2	18		T10	99
CntProgSt	1765846	1			T1	3028		T2	264		T3	16
CntIncrSt	35977	1			T1	68		T2	18		T3	8
ClkMuxSt	36223	1			T1	68		T2	18		T3	8
IdleSt	22445251	1			T1	72419		T2	20357		T3	752
ResetSt	7753410	1			T1	6418		T2	45653		T3	766
arcs[ResetSt=>IdleSt]	55437	1			T1	69		T2	187		T3	9
arcs[IdleSt=>ScrapSt]	319	1			T14	1		T4	1		T23	1
arcs[IdleSt=>ClkMuxSt]	36046	1			T1	68		T2	18		T3	8
arcs[ClkMuxSt=>CntIncrSt]	35977	1			T1	68		T2	18		T3	8
arcs[CntIncrSt=>PostTransSt]	1905	1			T1	7		T17	7		T18	13
arcs[CntIncrSt=>CntProgSt]	34019	1			T1	61		T2	18		T3	8
arcs[CntProgSt=>PostTransSt]	4929	1			T1	10		T3	8		T13	26
arcs[CntProgSt=>TransCheckSt]	28036	1			T1	51		T2	18		T10	99
arcs[TransCheckSt=>PostTransSt]	3751	1			T1	8		T11	36		T17	5
arcs[TransCheckSt=>TokenHashSt]	24167	1			T1	43		T2	18		T10	99
arcs[TokenHashSt=>PostTransSt]	10384	1			T1	25		T10	99		T11	14
arcs[TokenHashSt=>FlashRmaSt]	13119	1			T1	18		T2	18		T11	32
arcs[FlashRmaSt=>TokenCheck0St]	13026	1			T1	18		T2	18		T11	32
arcs[TokenCheck0St=>PostTransSt]	3359	1			T1	5		T11	21		T13	15
arcs[TokenCheck0St=>TokenCheck1St]	9638	1			T1	13		T2	18		T11	11
arcs[TokenCheck1St=>PostTransSt]	655	1			T1	1		T11	11		T39	6
arcs[TransProgSt=>PostTransSt]	8121	1			T1	12		T2	18		T13	25
arcs[IdleSt=>EscalateSt]	203	1			T14	3		T50	7		T48	6
arcs[ClkMuxSt=>EscalateSt]	69	1			T14	1		T48	2		T49	3
arcs[CntIncrSt=>EscalateSt]	53	1			T14	1		T50	1		T48	1
arcs[CntProgSt=>EscalateSt]	1054	1			T14	19		T50	12		T48	27
arcs[TransCheckSt=>EscalateSt]	118	1			T50	4		T48	1		T54	4
arcs[TokenHashSt=>EscalateSt]	664	1			T14	4		T50	21		T48	6
arcs[FlashRmaSt=>EscalateSt]	93	1			T14	1		T50	1		T48	2
arcs[TokenCheck0St=>EscalateSt]	29	1			T14	2		T50	1		T48	1
arcs[TokenCheck1St=>EscalateSt]	128	1			T14	2		T50	6		T48	4
arcs[TransProgSt=>EscalateSt]	734	1			T14	11		T50	9		T48	21
arcs[PostTransSt=>EscalateSt]	5158	1			T1	10		T3	8		T13	26
arcs[InvalidSt=>EscalateSt]	14498	1			T2	143		T13	21		T15	55

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7753249	1			T1	6418		T2	45653		T3	766
auto[0]	auto[IdleSt]	22445116	1			T1	72419		T2	20357		T3	752
auto[0]	auto[ClkMuxSt]	36174	1			T1	68		T2	18		T3	8
auto[0]	auto[CntIncrSt]	35948	1			T1	68		T2	18		T3	8
auto[0]	auto[CntProgSt]	1765137	1			T1	3028		T2	264		T3	16
auto[0]	auto[TransCheckSt]	27956	1			T1	51		T2	18		T10	99
auto[0]	auto[TokenHashSt]	44810734	1			T1	3530		T2	199030		T10	2038
auto[0]	auto[FlashRmaSt]	29193	1			T1	18		T2	18		T11	46
auto[0]	auto[TokenCheck0St]	13004	1			T1	18		T2	18		T11	32
auto[0]	auto[TokenCheck1St]	9549	1			T1	13		T2	18		T11	11
auto[0]	auto[TransProgSt]	485762	1			T1	592		T2	245		T13	578
auto[0]	auto[PostTransSt]	13478006	1			T1	59060		T2	3577		T3	497
auto[0]	auto[ScrapSt]	352189	1			T14	2		T4	641		T23	723
auto[0]	auto[EscalateSt]	5890040	1			T1	3808		T2	43305		T3	769
auto[0]	auto[InvalidSt]	12796033	1			T2	147950		T13	1617		T15	7610
auto[1]	auto[ResetSt]	161	1			T14	2		T50	4		T48	5
auto[1]	auto[IdleSt]	135	1			T14	1		T50	5		T48	2
auto[1]	auto[ClkMuxSt]	49	1			T14	1		T48	2		T49	2
auto[1]	auto[CntIncrSt]	29	1			T14	1		T49	1		T109	1
auto[1]	auto[CntProgSt]	709	1			T14	14		T50	7		T48	20
auto[1]	auto[TransCheckSt]	80	1			T50	2		T48	1		T54	2
auto[1]	auto[TokenHashSt]	431	1			T14	3		T50	12		T48	5
auto[1]	auto[FlashRmaSt]	56	1			T50	1		T48	1		T109	1
auto[1]	auto[TokenCheck0St]	22	1			T50	1		T48	1		T49	1
auto[1]	auto[TokenCheck1St]	89	1			T14	1		T50	3		T48	2
auto[1]	auto[TransProgSt]	510	1			T14	8		T50	6		T48	16
auto[1]	auto[PostTransSt]	2619	1			T1	5		T3	3		T13	14
auto[1]	auto[ScrapSt]	30	1			T14	1		T50	1		T49	1
auto[1]	auto[EscalateSt]	1406681	1			T1	490		T2	7187		T3	294
auto[1]	auto[InvalidSt]	7256	1			T2	74		T13	14		T15	24

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7753235	1			T1	6418		T2	45653		T3	766
auto[0]	auto[IdleSt]	22445116	1			T1	72419		T2	20357		T3	752
auto[0]	auto[ClkMuxSt]	36182	1			T1	68		T2	18		T3	8
auto[0]	auto[CntIncrSt]	35937	1			T1	68		T2	18		T3	8
auto[0]	auto[CntProgSt]	1765136	1			T1	3028		T2	264		T3	16
auto[0]	auto[TransCheckSt]	27957	1			T1	51		T2	18		T10	99
auto[0]	auto[TokenHashSt]	44810713	1			T1	3530		T2	199030		T10	2038
auto[0]	auto[FlashRmaSt]	29189	1			T1	18		T2	18		T11	46
auto[0]	auto[TokenCheck0St]	13009	1			T1	18		T2	18		T11	32
auto[0]	auto[TokenCheck1St]	9563	1			T1	13		T2	18		T11	11
auto[0]	auto[TransProgSt]	485796	1			T1	592		T2	245		T13	578
auto[0]	auto[PostTransSt]	13478031	1			T1	59060		T2	3577		T3	495
auto[0]	auto[ScrapSt]	352185	1			T14	3		T4	641		T23	723
auto[0]	auto[EscalateSt]	5896433	1			T1	3808		T2	43797		T3	573
auto[0]	auto[InvalidSt]	12796047	1			T2	147955		T13	1624		T15	7603
auto[1]	auto[ResetSt]	175	1			T14	4		T50	3		T48	5
auto[1]	auto[IdleSt]	135	1			T14	3		T50	4		T48	5
auto[1]	auto[ClkMuxSt]	41	1			T14	1		T49	3		T109	1
auto[1]	auto[CntIncrSt]	40	1			T14	1		T50	1		T48	1
auto[1]	auto[CntProgSt]	710	1			T14	10		T50	6		T48	14
auto[1]	auto[TransCheckSt]	79	1			T50	2		T48	1		T54	3
auto[1]	auto[TokenHashSt]	452	1			T14	3		T50	16		T48	4
auto[1]	auto[FlashRmaSt]	60	1			T14	1		T48	1		T109	1
auto[1]	auto[TokenCheck0St]	17	1			T14	2		T50	1		T110	1
auto[1]	auto[TokenCheck1St]	75	1			T14	1		T50	6		T48	3
auto[1]	auto[TransProgSt]	476	1			T14	6		T50	6		T48	13
auto[1]	auto[PostTransSt]	2594	1			T1	5		T3	5		T13	12
auto[1]	auto[ScrapSt]	34	1			T50	1		T48	2		T49	2
auto[1]	auto[EscalateSt]	1400288	1			T1	490		T2	6695		T3	490
auto[1]	auto[InvalidSt]	7242	1			T2	69		T13	7		T15	31