| T166 |
/workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.1871834957 |
|
|
Apr 30 02:17:18 PM PDT 24 |
Apr 30 02:43:01 PM PDT 24 |
163236658226 ps |
| T809 |
/workspace/coverage/default/18.lc_ctrl_state_failure.787761715 |
|
|
Apr 30 02:16:15 PM PDT 24 |
Apr 30 02:16:42 PM PDT 24 |
201357316 ps |
| T810 |
/workspace/coverage/default/34.lc_ctrl_errors.2591021762 |
|
|
Apr 30 02:17:10 PM PDT 24 |
Apr 30 02:17:24 PM PDT 24 |
437501730 ps |
| T811 |
/workspace/coverage/default/4.lc_ctrl_sec_mubi.2702374175 |
|
|
Apr 30 02:15:55 PM PDT 24 |
Apr 30 02:16:06 PM PDT 24 |
742424154 ps |
| T812 |
/workspace/coverage/default/35.lc_ctrl_stress_all.2771709140 |
|
|
Apr 30 02:16:59 PM PDT 24 |
Apr 30 02:18:04 PM PDT 24 |
3118015504 ps |
| T813 |
/workspace/coverage/default/14.lc_ctrl_stress_all.1014205945 |
|
|
Apr 30 02:16:08 PM PDT 24 |
Apr 30 02:18:13 PM PDT 24 |
17217677650 ps |
| T814 |
/workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2578005577 |
|
|
Apr 30 02:15:56 PM PDT 24 |
Apr 30 02:15:57 PM PDT 24 |
17096269 ps |
| T211 |
/workspace/coverage/default/5.lc_ctrl_claim_transition_if.1230329974 |
|
|
Apr 30 02:15:40 PM PDT 24 |
Apr 30 02:15:41 PM PDT 24 |
13535967 ps |
| T815 |
/workspace/coverage/default/27.lc_ctrl_jtag_access.466382006 |
|
|
Apr 30 02:16:50 PM PDT 24 |
Apr 30 02:16:56 PM PDT 24 |
325339185 ps |
| T816 |
/workspace/coverage/default/0.lc_ctrl_errors.2693128297 |
|
|
Apr 30 02:15:39 PM PDT 24 |
Apr 30 02:15:53 PM PDT 24 |
1236775720 ps |
| T817 |
/workspace/coverage/default/28.lc_ctrl_smoke.1340387615 |
|
|
Apr 30 02:16:57 PM PDT 24 |
Apr 30 02:17:01 PM PDT 24 |
99288580 ps |
| T818 |
/workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.212389939 |
|
|
Apr 30 02:16:25 PM PDT 24 |
Apr 30 02:16:27 PM PDT 24 |
40143357 ps |
| T167 |
/workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.1479061368 |
|
|
Apr 30 02:16:00 PM PDT 24 |
Apr 30 02:25:16 PM PDT 24 |
26979666353 ps |
| T819 |
/workspace/coverage/default/19.lc_ctrl_security_escalation.1162222573 |
|
|
Apr 30 02:16:31 PM PDT 24 |
Apr 30 02:16:40 PM PDT 24 |
174649919 ps |
| T820 |
/workspace/coverage/default/15.lc_ctrl_jtag_errors.1330264143 |
|
|
Apr 30 02:16:26 PM PDT 24 |
Apr 30 02:17:17 PM PDT 24 |
1544559269 ps |
| T821 |
/workspace/coverage/default/13.lc_ctrl_jtag_errors.2625770024 |
|
|
Apr 30 02:16:26 PM PDT 24 |
Apr 30 02:16:56 PM PDT 24 |
27622436989 ps |
| T822 |
/workspace/coverage/default/45.lc_ctrl_stress_all.4005280667 |
|
|
Apr 30 02:17:23 PM PDT 24 |
Apr 30 02:19:14 PM PDT 24 |
2646656209 ps |
| T823 |
/workspace/coverage/default/4.lc_ctrl_security_escalation.2456396318 |
|
|
Apr 30 02:15:45 PM PDT 24 |
Apr 30 02:15:54 PM PDT 24 |
1991375674 ps |
| T824 |
/workspace/coverage/default/42.lc_ctrl_security_escalation.3416475966 |
|
|
Apr 30 02:17:29 PM PDT 24 |
Apr 30 02:17:37 PM PDT 24 |
337218681 ps |
| T825 |
/workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.918303418 |
|
|
Apr 30 02:17:21 PM PDT 24 |
Apr 30 02:17:22 PM PDT 24 |
14945539 ps |
| T826 |
/workspace/coverage/default/21.lc_ctrl_prog_failure.1106398012 |
|
|
Apr 30 02:16:29 PM PDT 24 |
Apr 30 02:16:33 PM PDT 24 |
58651815 ps |
| T827 |
/workspace/coverage/default/16.lc_ctrl_state_post_trans.662062932 |
|
|
Apr 30 02:16:12 PM PDT 24 |
Apr 30 02:16:18 PM PDT 24 |
96096031 ps |
| T828 |
/workspace/coverage/default/3.lc_ctrl_sec_token_mux.2585574303 |
|
|
Apr 30 02:15:47 PM PDT 24 |
Apr 30 02:15:58 PM PDT 24 |
769782290 ps |
| T829 |
/workspace/coverage/default/47.lc_ctrl_state_failure.2408927030 |
|
|
Apr 30 02:17:18 PM PDT 24 |
Apr 30 02:17:40 PM PDT 24 |
202583414 ps |
| T830 |
/workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1915488741 |
|
|
Apr 30 02:16:10 PM PDT 24 |
Apr 30 02:16:13 PM PDT 24 |
249981970 ps |
| T831 |
/workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.4136921085 |
|
|
Apr 30 02:15:42 PM PDT 24 |
Apr 30 02:16:06 PM PDT 24 |
844337982 ps |
| T832 |
/workspace/coverage/default/6.lc_ctrl_stress_all.702008886 |
|
|
Apr 30 02:15:54 PM PDT 24 |
Apr 30 02:17:19 PM PDT 24 |
19235536466 ps |
| T833 |
/workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3608107678 |
|
|
Apr 30 02:16:04 PM PDT 24 |
Apr 30 02:16:13 PM PDT 24 |
960257435 ps |
| T834 |
/workspace/coverage/default/17.lc_ctrl_security_escalation.3900007942 |
|
|
Apr 30 02:16:29 PM PDT 24 |
Apr 30 02:16:38 PM PDT 24 |
623806387 ps |
| T835 |
/workspace/coverage/default/0.lc_ctrl_claim_transition_if.317123160 |
|
|
Apr 30 02:17:05 PM PDT 24 |
Apr 30 02:17:06 PM PDT 24 |
14159615 ps |
| T836 |
/workspace/coverage/default/8.lc_ctrl_sec_token_digest.1643137839 |
|
|
Apr 30 02:15:55 PM PDT 24 |
Apr 30 02:16:09 PM PDT 24 |
2041044458 ps |
| T837 |
/workspace/coverage/default/14.lc_ctrl_prog_failure.6018586 |
|
|
Apr 30 02:15:56 PM PDT 24 |
Apr 30 02:16:01 PM PDT 24 |
382812515 ps |
| T838 |
/workspace/coverage/default/23.lc_ctrl_sec_token_digest.3922783713 |
|
|
Apr 30 02:16:33 PM PDT 24 |
Apr 30 02:16:43 PM PDT 24 |
1181337814 ps |
| T839 |
/workspace/coverage/default/47.lc_ctrl_errors.3342968037 |
|
|
Apr 30 02:17:28 PM PDT 24 |
Apr 30 02:17:43 PM PDT 24 |
454292825 ps |
| T840 |
/workspace/coverage/default/38.lc_ctrl_sec_token_mux.602002589 |
|
|
Apr 30 02:17:10 PM PDT 24 |
Apr 30 02:17:19 PM PDT 24 |
294193537 ps |
| T841 |
/workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3469804110 |
|
|
Apr 30 02:15:37 PM PDT 24 |
Apr 30 02:16:36 PM PDT 24 |
3161760167 ps |
| T842 |
/workspace/coverage/default/6.lc_ctrl_prog_failure.3751257016 |
|
|
Apr 30 02:16:06 PM PDT 24 |
Apr 30 02:16:08 PM PDT 24 |
89345571 ps |
| T843 |
/workspace/coverage/default/15.lc_ctrl_smoke.3441031120 |
|
|
Apr 30 02:16:30 PM PDT 24 |
Apr 30 02:16:34 PM PDT 24 |
127343219 ps |
| T844 |
/workspace/coverage/default/33.lc_ctrl_state_post_trans.4197085244 |
|
|
Apr 30 02:17:03 PM PDT 24 |
Apr 30 02:17:07 PM PDT 24 |
57789028 ps |
| T845 |
/workspace/coverage/default/3.lc_ctrl_jtag_smoke.339490008 |
|
|
Apr 30 02:15:40 PM PDT 24 |
Apr 30 02:15:42 PM PDT 24 |
362773826 ps |
| T846 |
/workspace/coverage/default/1.lc_ctrl_state_post_trans.382573451 |
|
|
Apr 30 02:15:40 PM PDT 24 |
Apr 30 02:15:53 PM PDT 24 |
232763990 ps |
| T847 |
/workspace/coverage/default/22.lc_ctrl_state_post_trans.615428164 |
|
|
Apr 30 02:16:23 PM PDT 24 |
Apr 30 02:16:32 PM PDT 24 |
94693550 ps |
| T848 |
/workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1770045344 |
|
|
Apr 30 02:16:57 PM PDT 24 |
Apr 30 02:17:00 PM PDT 24 |
20987483 ps |
| T849 |
/workspace/coverage/default/46.lc_ctrl_state_failure.2432899163 |
|
|
Apr 30 02:17:20 PM PDT 24 |
Apr 30 02:17:44 PM PDT 24 |
217901403 ps |
| T850 |
/workspace/coverage/default/25.lc_ctrl_errors.2196692898 |
|
|
Apr 30 02:16:49 PM PDT 24 |
Apr 30 02:17:00 PM PDT 24 |
189671042 ps |
| T851 |
/workspace/coverage/default/28.lc_ctrl_sec_token_mux.4142735524 |
|
|
Apr 30 02:17:00 PM PDT 24 |
Apr 30 02:17:07 PM PDT 24 |
558457303 ps |
| T852 |
/workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1724880797 |
|
|
Apr 30 02:16:52 PM PDT 24 |
Apr 30 02:16:55 PM PDT 24 |
13681706 ps |
| T853 |
/workspace/coverage/default/24.lc_ctrl_security_escalation.2754317516 |
|
|
Apr 30 02:16:47 PM PDT 24 |
Apr 30 02:16:56 PM PDT 24 |
288733662 ps |
| T854 |
/workspace/coverage/default/20.lc_ctrl_sec_token_mux.2406430687 |
|
|
Apr 30 02:16:44 PM PDT 24 |
Apr 30 02:16:55 PM PDT 24 |
316773554 ps |
| T855 |
/workspace/coverage/default/47.lc_ctrl_stress_all.1194633607 |
|
|
Apr 30 02:17:16 PM PDT 24 |
Apr 30 02:19:46 PM PDT 24 |
18259953397 ps |
| T856 |
/workspace/coverage/default/44.lc_ctrl_state_failure.2647272173 |
|
|
Apr 30 02:17:24 PM PDT 24 |
Apr 30 02:17:45 PM PDT 24 |
246812960 ps |
| T857 |
/workspace/coverage/default/8.lc_ctrl_state_post_trans.4265858020 |
|
|
Apr 30 02:16:06 PM PDT 24 |
Apr 30 02:16:14 PM PDT 24 |
100275247 ps |
| T858 |
/workspace/coverage/default/21.lc_ctrl_sec_token_mux.92275069 |
|
|
Apr 30 02:16:45 PM PDT 24 |
Apr 30 02:16:58 PM PDT 24 |
513376665 ps |
| T859 |
/workspace/coverage/default/27.lc_ctrl_security_escalation.2260030362 |
|
|
Apr 30 02:16:48 PM PDT 24 |
Apr 30 02:16:59 PM PDT 24 |
5235259937 ps |
| T860 |
/workspace/coverage/default/25.lc_ctrl_smoke.1386383161 |
|
|
Apr 30 02:16:47 PM PDT 24 |
Apr 30 02:16:52 PM PDT 24 |
1668497843 ps |
| T861 |
/workspace/coverage/default/42.lc_ctrl_sec_mubi.2839855190 |
|
|
Apr 30 02:17:21 PM PDT 24 |
Apr 30 02:17:35 PM PDT 24 |
695022594 ps |
| T862 |
/workspace/coverage/default/22.lc_ctrl_sec_mubi.2882116592 |
|
|
Apr 30 02:16:36 PM PDT 24 |
Apr 30 02:16:50 PM PDT 24 |
884002003 ps |
| T863 |
/workspace/coverage/default/31.lc_ctrl_sec_token_mux.3557996085 |
|
|
Apr 30 02:17:08 PM PDT 24 |
Apr 30 02:17:19 PM PDT 24 |
960805133 ps |
| T864 |
/workspace/coverage/default/26.lc_ctrl_security_escalation.1150710786 |
|
|
Apr 30 02:16:42 PM PDT 24 |
Apr 30 02:16:57 PM PDT 24 |
410179107 ps |
| T865 |
/workspace/coverage/default/5.lc_ctrl_jtag_priority.1289485285 |
|
|
Apr 30 02:15:38 PM PDT 24 |
Apr 30 02:15:57 PM PDT 24 |
791611111 ps |
| T866 |
/workspace/coverage/default/34.lc_ctrl_stress_all.2252952673 |
|
|
Apr 30 02:17:02 PM PDT 24 |
Apr 30 02:17:52 PM PDT 24 |
2366053683 ps |
| T76 |
/workspace/coverage/default/9.lc_ctrl_jtag_smoke.2562888854 |
|
|
Apr 30 02:15:59 PM PDT 24 |
Apr 30 02:16:01 PM PDT 24 |
477962424 ps |
| T867 |
/workspace/coverage/default/45.lc_ctrl_state_failure.238507974 |
|
|
Apr 30 02:17:19 PM PDT 24 |
Apr 30 02:18:01 PM PDT 24 |
719424289 ps |
| T868 |
/workspace/coverage/default/37.lc_ctrl_smoke.3723185775 |
|
|
Apr 30 02:17:04 PM PDT 24 |
Apr 30 02:17:06 PM PDT 24 |
382742575 ps |
| T869 |
/workspace/coverage/default/3.lc_ctrl_sec_mubi.3092028704 |
|
|
Apr 30 02:15:54 PM PDT 24 |
Apr 30 02:16:02 PM PDT 24 |
1212605251 ps |
| T870 |
/workspace/coverage/default/37.lc_ctrl_state_failure.1136600020 |
|
|
Apr 30 02:17:07 PM PDT 24 |
Apr 30 02:17:39 PM PDT 24 |
1027234050 ps |
| T128 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2305450605 |
|
|
Apr 30 03:01:21 PM PDT 24 |
Apr 30 03:01:23 PM PDT 24 |
36137613 ps |
| T136 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2455197573 |
|
|
Apr 30 03:01:17 PM PDT 24 |
Apr 30 03:01:19 PM PDT 24 |
436397771 ps |
| T197 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3628696722 |
|
|
Apr 30 03:01:38 PM PDT 24 |
Apr 30 03:01:40 PM PDT 24 |
44781298 ps |
| T122 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4017435893 |
|
|
Apr 30 03:01:23 PM PDT 24 |
Apr 30 03:01:27 PM PDT 24 |
288774741 ps |
| T129 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.694317088 |
|
|
Apr 30 03:01:26 PM PDT 24 |
Apr 30 03:01:30 PM PDT 24 |
3937226908 ps |
| T871 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1024882887 |
|
|
Apr 30 03:01:14 PM PDT 24 |
Apr 30 03:01:17 PM PDT 24 |
88776313 ps |
| T123 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.854063196 |
|
|
Apr 30 03:01:30 PM PDT 24 |
Apr 30 03:01:32 PM PDT 24 |
18244497 ps |
| T153 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2186244931 |
|
|
Apr 30 03:01:25 PM PDT 24 |
Apr 30 03:01:32 PM PDT 24 |
25954571 ps |
| T154 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3541323372 |
|
|
Apr 30 03:01:24 PM PDT 24 |
Apr 30 03:01:26 PM PDT 24 |
40141270 ps |
| T130 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3507622832 |
|
|
Apr 30 03:01:28 PM PDT 24 |
Apr 30 03:01:31 PM PDT 24 |
88462065 ps |
| T189 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3144725757 |
|
|
Apr 30 03:01:31 PM PDT 24 |
Apr 30 03:01:33 PM PDT 24 |
32098437 ps |
| T872 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3590501165 |
|
|
Apr 30 03:01:15 PM PDT 24 |
Apr 30 03:01:16 PM PDT 24 |
13931694 ps |
| T198 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1205104884 |
|
|
Apr 30 03:01:30 PM PDT 24 |
Apr 30 03:01:32 PM PDT 24 |
53318755 ps |
| T873 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3177261414 |
|
|
Apr 30 03:01:09 PM PDT 24 |
Apr 30 03:01:11 PM PDT 24 |
1093717538 ps |
| T168 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3333273781 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:24 PM PDT 24 |
169478202 ps |
| T874 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1679928667 |
|
|
Apr 30 03:01:16 PM PDT 24 |
Apr 30 03:01:18 PM PDT 24 |
35623594 ps |
| T169 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.671773572 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:24 PM PDT 24 |
183010503 ps |
| T875 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3554340800 |
|
|
Apr 30 03:01:30 PM PDT 24 |
Apr 30 03:01:32 PM PDT 24 |
23623198 ps |
| T876 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3729700754 |
|
|
Apr 30 03:01:16 PM PDT 24 |
Apr 30 03:01:17 PM PDT 24 |
66790332 ps |
| T877 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3051683381 |
|
|
Apr 30 03:01:14 PM PDT 24 |
Apr 30 03:01:25 PM PDT 24 |
344783972 ps |
| T170 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2804115302 |
|
|
Apr 30 03:01:23 PM PDT 24 |
Apr 30 03:01:25 PM PDT 24 |
63218220 ps |
| T152 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3108600590 |
|
|
Apr 30 03:01:17 PM PDT 24 |
Apr 30 03:01:33 PM PDT 24 |
1287434954 ps |
| T878 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2181962478 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:25 PM PDT 24 |
160259066 ps |
| T199 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3879487025 |
|
|
Apr 30 03:01:25 PM PDT 24 |
Apr 30 03:01:27 PM PDT 24 |
24195796 ps |
| T120 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2440597358 |
|
|
Apr 30 03:01:34 PM PDT 24 |
Apr 30 03:01:37 PM PDT 24 |
45407366 ps |
| T879 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1923283416 |
|
|
Apr 30 03:01:17 PM PDT 24 |
Apr 30 03:01:30 PM PDT 24 |
541390607 ps |
| T176 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1576730882 |
|
|
Apr 30 03:01:32 PM PDT 24 |
Apr 30 03:01:34 PM PDT 24 |
93832530 ps |
| T121 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3717616523 |
|
|
Apr 30 03:01:15 PM PDT 24 |
Apr 30 03:01:19 PM PDT 24 |
60527438 ps |
| T124 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2325654253 |
|
|
Apr 30 03:01:29 PM PDT 24 |
Apr 30 03:01:32 PM PDT 24 |
185103858 ps |
| T880 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3660650669 |
|
|
Apr 30 03:01:14 PM PDT 24 |
Apr 30 03:01:35 PM PDT 24 |
1275087119 ps |
| T126 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1157153668 |
|
|
Apr 30 03:01:29 PM PDT 24 |
Apr 30 03:01:33 PM PDT 24 |
317080035 ps |
| T125 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2730791021 |
|
|
Apr 30 03:01:32 PM PDT 24 |
Apr 30 03:01:37 PM PDT 24 |
440811458 ps |
| T200 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3485501526 |
|
|
Apr 30 03:01:40 PM PDT 24 |
Apr 30 03:01:42 PM PDT 24 |
26318319 ps |
| T881 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.4175211324 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:39 PM PDT 24 |
2958921056 ps |
| T882 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.372205923 |
|
|
Apr 30 03:01:21 PM PDT 24 |
Apr 30 03:01:22 PM PDT 24 |
743155553 ps |
| T883 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3473712838 |
|
|
Apr 30 03:01:29 PM PDT 24 |
Apr 30 03:01:46 PM PDT 24 |
7344501877 ps |
| T884 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3054137252 |
|
|
Apr 30 03:01:21 PM PDT 24 |
Apr 30 03:01:23 PM PDT 24 |
48432679 ps |
| T885 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1444804526 |
|
|
Apr 30 03:01:25 PM PDT 24 |
Apr 30 03:01:31 PM PDT 24 |
17492990 ps |
| T886 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1370246761 |
|
|
Apr 30 03:01:29 PM PDT 24 |
Apr 30 03:01:31 PM PDT 24 |
30047646 ps |
| T131 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.3857766113 |
|
|
Apr 30 03:01:24 PM PDT 24 |
Apr 30 03:01:26 PM PDT 24 |
51947817 ps |
| T145 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.495983965 |
|
|
Apr 30 03:01:17 PM PDT 24 |
Apr 30 03:01:20 PM PDT 24 |
79051048 ps |
| T201 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3444638137 |
|
|
Apr 30 03:01:30 PM PDT 24 |
Apr 30 03:01:31 PM PDT 24 |
37962164 ps |
| T887 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1831357740 |
|
|
Apr 30 03:01:14 PM PDT 24 |
Apr 30 03:01:15 PM PDT 24 |
14987577 ps |
| T888 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3246197868 |
|
|
Apr 30 03:01:16 PM PDT 24 |
Apr 30 03:01:18 PM PDT 24 |
79415014 ps |
| T889 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3576463520 |
|
|
Apr 30 03:01:17 PM PDT 24 |
Apr 30 03:01:18 PM PDT 24 |
18005449 ps |
| T147 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2624163494 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:27 PM PDT 24 |
228256892 ps |
| T890 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1909499826 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:37 PM PDT 24 |
815443780 ps |
| T891 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.741222316 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:24 PM PDT 24 |
123775597 ps |
| T202 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1721038330 |
|
|
Apr 30 03:01:32 PM PDT 24 |
Apr 30 03:01:34 PM PDT 24 |
17602916 ps |
| T892 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.78234988 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:24 PM PDT 24 |
41895095 ps |
| T135 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3820364581 |
|
|
Apr 30 03:01:29 PM PDT 24 |
Apr 30 03:01:32 PM PDT 24 |
36780654 ps |
| T893 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2634416633 |
|
|
Apr 30 03:01:31 PM PDT 24 |
Apr 30 03:01:33 PM PDT 24 |
51365669 ps |
| T894 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3953924540 |
|
|
Apr 30 03:01:16 PM PDT 24 |
Apr 30 03:01:18 PM PDT 24 |
83586663 ps |
| T203 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3545480281 |
|
|
Apr 30 03:01:24 PM PDT 24 |
Apr 30 03:01:26 PM PDT 24 |
30767350 ps |
| T190 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1463403619 |
|
|
Apr 30 03:01:18 PM PDT 24 |
Apr 30 03:01:20 PM PDT 24 |
25862568 ps |
| T895 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.268350813 |
|
|
Apr 30 03:01:24 PM PDT 24 |
Apr 30 03:01:26 PM PDT 24 |
20981299 ps |
| T204 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.270773920 |
|
|
Apr 30 03:01:32 PM PDT 24 |
Apr 30 03:01:33 PM PDT 24 |
40459097 ps |
| T896 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.71547858 |
|
|
Apr 30 03:01:26 PM PDT 24 |
Apr 30 03:01:31 PM PDT 24 |
119600553 ps |
| T137 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.57737105 |
|
|
Apr 30 03:01:33 PM PDT 24 |
Apr 30 03:01:38 PM PDT 24 |
116650740 ps |
| T897 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1921235634 |
|
|
Apr 30 03:01:23 PM PDT 24 |
Apr 30 03:01:44 PM PDT 24 |
811630717 ps |
| T898 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3170500805 |
|
|
Apr 30 03:01:15 PM PDT 24 |
Apr 30 03:01:17 PM PDT 24 |
53489857 ps |
| T132 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2842566225 |
|
|
Apr 30 03:01:30 PM PDT 24 |
Apr 30 03:01:33 PM PDT 24 |
239802612 ps |
| T899 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.4216371799 |
|
|
Apr 30 03:01:29 PM PDT 24 |
Apr 30 03:01:31 PM PDT 24 |
22632490 ps |
| T900 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3358753839 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:26 PM PDT 24 |
417635530 ps |
| T901 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1582672081 |
|
|
Apr 30 03:01:24 PM PDT 24 |
Apr 30 03:01:27 PM PDT 24 |
616849975 ps |
| T902 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1671461724 |
|
|
Apr 30 03:01:31 PM PDT 24 |
Apr 30 03:01:33 PM PDT 24 |
14389344 ps |
| T139 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1713979775 |
|
|
Apr 30 03:01:19 PM PDT 24 |
Apr 30 03:01:23 PM PDT 24 |
49736575 ps |
| T140 |
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2849747139 |
|
|
Apr 30 03:01:29 PM PDT 24 |
Apr 30 03:01:32 PM PDT 24 |
25228102 ps |
| T903 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3616148629 |
|
|
Apr 30 03:01:17 PM PDT 24 |
Apr 30 03:01:20 PM PDT 24 |
201809599 ps |
| T904 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1357613652 |
|
|
Apr 30 03:01:21 PM PDT 24 |
Apr 30 03:01:22 PM PDT 24 |
47634388 ps |
| T905 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2258945375 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:25 PM PDT 24 |
183100857 ps |
| T906 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3134179570 |
|
|
Apr 30 03:01:20 PM PDT 24 |
Apr 30 03:01:22 PM PDT 24 |
354057292 ps |
| T141 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1692733951 |
|
|
Apr 30 03:01:32 PM PDT 24 |
Apr 30 03:01:34 PM PDT 24 |
43225947 ps |
| T907 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1868926197 |
|
|
Apr 30 03:01:13 PM PDT 24 |
Apr 30 03:01:15 PM PDT 24 |
246290294 ps |
| T908 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1079012603 |
|
|
Apr 30 03:01:21 PM PDT 24 |
Apr 30 03:01:22 PM PDT 24 |
31010686 ps |
| T909 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.435810372 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:26 PM PDT 24 |
337225165 ps |
| T910 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1123806292 |
|
|
Apr 30 03:01:14 PM PDT 24 |
Apr 30 03:01:21 PM PDT 24 |
293525681 ps |
| T143 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3189241278 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:26 PM PDT 24 |
250093265 ps |
| T911 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3916039243 |
|
|
Apr 30 03:01:17 PM PDT 24 |
Apr 30 03:01:24 PM PDT 24 |
1629763037 ps |
| T912 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3857040372 |
|
|
Apr 30 03:01:16 PM PDT 24 |
Apr 30 03:01:19 PM PDT 24 |
93510807 ps |
| T913 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.77392501 |
|
|
Apr 30 03:01:14 PM PDT 24 |
Apr 30 03:01:15 PM PDT 24 |
98749142 ps |
| T914 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2531574418 |
|
|
Apr 30 03:01:25 PM PDT 24 |
Apr 30 03:01:29 PM PDT 24 |
646165884 ps |
| T915 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1827261399 |
|
|
Apr 30 03:01:25 PM PDT 24 |
Apr 30 03:01:28 PM PDT 24 |
69823575 ps |
| T916 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3763966232 |
|
|
Apr 30 03:01:25 PM PDT 24 |
Apr 30 03:01:28 PM PDT 24 |
477936010 ps |
| T917 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1690927075 |
|
|
Apr 30 03:01:17 PM PDT 24 |
Apr 30 03:01:19 PM PDT 24 |
31059274 ps |
| T918 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1524620387 |
|
|
Apr 30 03:01:29 PM PDT 24 |
Apr 30 03:01:30 PM PDT 24 |
14621527 ps |
| T133 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1618914882 |
|
|
Apr 30 03:01:24 PM PDT 24 |
Apr 30 03:01:28 PM PDT 24 |
404642673 ps |
| T191 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3957667037 |
|
|
Apr 30 03:01:21 PM PDT 24 |
Apr 30 03:01:23 PM PDT 24 |
33066373 ps |
| T919 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3197538304 |
|
|
Apr 30 03:01:23 PM PDT 24 |
Apr 30 03:01:26 PM PDT 24 |
42959359 ps |
| T151 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1208355556 |
|
|
Apr 30 03:01:15 PM PDT 24 |
Apr 30 03:01:20 PM PDT 24 |
121480355 ps |
| T920 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4259900403 |
|
|
Apr 30 03:01:13 PM PDT 24 |
Apr 30 03:01:17 PM PDT 24 |
418052662 ps |
| T921 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3133767489 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:25 PM PDT 24 |
155377022 ps |
| T138 |
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3132173024 |
|
|
Apr 30 03:01:44 PM PDT 24 |
Apr 30 03:01:48 PM PDT 24 |
152950901 ps |
| T922 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.64701415 |
|
|
Apr 30 03:01:19 PM PDT 24 |
Apr 30 03:01:21 PM PDT 24 |
200614495 ps |
| T923 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2038589635 |
|
|
Apr 30 03:01:29 PM PDT 24 |
Apr 30 03:01:30 PM PDT 24 |
66977602 ps |
| T924 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2997197155 |
|
|
Apr 30 03:01:15 PM PDT 24 |
Apr 30 03:01:18 PM PDT 24 |
1096686203 ps |
| T925 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3862441388 |
|
|
Apr 30 03:01:25 PM PDT 24 |
Apr 30 03:01:28 PM PDT 24 |
353349385 ps |
| T926 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3489873163 |
|
|
Apr 30 03:01:28 PM PDT 24 |
Apr 30 03:01:30 PM PDT 24 |
39419890 ps |
| T927 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.469088189 |
|
|
Apr 30 03:01:26 PM PDT 24 |
Apr 30 03:01:39 PM PDT 24 |
1910067318 ps |
| T928 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.443634272 |
|
|
Apr 30 03:01:23 PM PDT 24 |
Apr 30 03:01:32 PM PDT 24 |
1590381250 ps |
| T929 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2321328570 |
|
|
Apr 30 03:01:20 PM PDT 24 |
Apr 30 03:01:22 PM PDT 24 |
21145936 ps |
| T930 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.457748033 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:24 PM PDT 24 |
20991876 ps |
| T931 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1856427953 |
|
|
Apr 30 03:01:30 PM PDT 24 |
Apr 30 03:01:31 PM PDT 24 |
16406961 ps |
| T932 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.753136327 |
|
|
Apr 30 03:01:28 PM PDT 24 |
Apr 30 03:01:31 PM PDT 24 |
41634647 ps |
| T933 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2648613870 |
|
|
Apr 30 03:01:31 PM PDT 24 |
Apr 30 03:01:34 PM PDT 24 |
50241927 ps |
| T934 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.572905683 |
|
|
Apr 30 03:01:34 PM PDT 24 |
Apr 30 03:01:37 PM PDT 24 |
51203867 ps |
| T935 |
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3885152658 |
|
|
Apr 30 03:01:33 PM PDT 24 |
Apr 30 03:01:35 PM PDT 24 |
118805236 ps |
| T936 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4153837919 |
|
|
Apr 30 03:01:16 PM PDT 24 |
Apr 30 03:01:19 PM PDT 24 |
145076530 ps |
| T937 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2011216996 |
|
|
Apr 30 03:01:18 PM PDT 24 |
Apr 30 03:01:21 PM PDT 24 |
119422921 ps |
| T938 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2230936543 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:24 PM PDT 24 |
798752090 ps |
| T939 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2079849222 |
|
|
Apr 30 03:01:39 PM PDT 24 |
Apr 30 03:01:42 PM PDT 24 |
31257268 ps |
| T940 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.11937596 |
|
|
Apr 30 03:01:13 PM PDT 24 |
Apr 30 03:01:15 PM PDT 24 |
150086308 ps |
| T941 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.4044306030 |
|
|
Apr 30 03:01:26 PM PDT 24 |
Apr 30 03:01:28 PM PDT 24 |
14351497 ps |
| T942 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3092378385 |
|
|
Apr 30 03:01:14 PM PDT 24 |
Apr 30 03:01:16 PM PDT 24 |
18101874 ps |
| T943 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1291978115 |
|
|
Apr 30 03:01:25 PM PDT 24 |
Apr 30 03:01:29 PM PDT 24 |
101372800 ps |
| T944 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.739280815 |
|
|
Apr 30 03:01:25 PM PDT 24 |
Apr 30 03:01:29 PM PDT 24 |
346210895 ps |
| T192 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.3808164458 |
|
|
Apr 30 03:01:17 PM PDT 24 |
Apr 30 03:01:19 PM PDT 24 |
79842843 ps |
| T945 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.447340715 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:24 PM PDT 24 |
15705405 ps |
| T946 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2147515347 |
|
|
Apr 30 03:01:21 PM PDT 24 |
Apr 30 03:01:27 PM PDT 24 |
1371695815 ps |
| T947 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4082859718 |
|
|
Apr 30 03:01:16 PM PDT 24 |
Apr 30 03:01:18 PM PDT 24 |
497346772 ps |
| T144 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2363281533 |
|
|
Apr 30 03:01:24 PM PDT 24 |
Apr 30 03:01:29 PM PDT 24 |
82478284 ps |
| T948 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1373352009 |
|
|
Apr 30 03:01:26 PM PDT 24 |
Apr 30 03:01:29 PM PDT 24 |
68555817 ps |
| T949 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.755729516 |
|
|
Apr 30 03:01:58 PM PDT 24 |
Apr 30 03:02:00 PM PDT 24 |
337698411 ps |
| T950 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3779326200 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:25 PM PDT 24 |
159918973 ps |
| T951 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1194506951 |
|
|
Apr 30 03:01:15 PM PDT 24 |
Apr 30 03:01:27 PM PDT 24 |
2311355271 ps |
| T952 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1947644130 |
|
|
Apr 30 03:01:12 PM PDT 24 |
Apr 30 03:01:24 PM PDT 24 |
2360134769 ps |
| T953 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3447177002 |
|
|
Apr 30 03:01:14 PM PDT 24 |
Apr 30 03:01:17 PM PDT 24 |
147990455 ps |
| T954 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1603162791 |
|
|
Apr 30 03:01:16 PM PDT 24 |
Apr 30 03:01:18 PM PDT 24 |
35360005 ps |
| T955 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2666601184 |
|
|
Apr 30 03:01:21 PM PDT 24 |
Apr 30 03:01:24 PM PDT 24 |
1097316009 ps |
| T956 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3597217904 |
|
|
Apr 30 03:01:24 PM PDT 24 |
Apr 30 03:01:27 PM PDT 24 |
25990618 ps |
| T957 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.903846804 |
|
|
Apr 30 03:01:32 PM PDT 24 |
Apr 30 03:01:33 PM PDT 24 |
12775992 ps |
| T958 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3225131593 |
|
|
Apr 30 03:01:30 PM PDT 24 |
Apr 30 03:01:32 PM PDT 24 |
23915002 ps |
| T959 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2950172607 |
|
|
Apr 30 03:01:23 PM PDT 24 |
Apr 30 03:01:26 PM PDT 24 |
73847710 ps |
| T960 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.991126729 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:35 PM PDT 24 |
2541974745 ps |
| T961 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4267515850 |
|
|
Apr 30 03:01:15 PM PDT 24 |
Apr 30 03:01:20 PM PDT 24 |
118214851 ps |
| T962 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2597364711 |
|
|
Apr 30 03:01:28 PM PDT 24 |
Apr 30 03:01:30 PM PDT 24 |
22771121 ps |
| T963 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.907621121 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:25 PM PDT 24 |
57068992 ps |
| T964 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3641567595 |
|
|
Apr 30 03:01:20 PM PDT 24 |
Apr 30 03:01:22 PM PDT 24 |
21969279 ps |
| T965 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.1580827915 |
|
|
Apr 30 03:01:25 PM PDT 24 |
Apr 30 03:01:27 PM PDT 24 |
83539164 ps |
| T966 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3154224454 |
|
|
Apr 30 03:01:36 PM PDT 24 |
Apr 30 03:01:38 PM PDT 24 |
49128023 ps |
| T967 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3048604792 |
|
|
Apr 30 03:01:23 PM PDT 24 |
Apr 30 03:01:25 PM PDT 24 |
138769987 ps |
| T968 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.314936130 |
|
|
Apr 30 03:01:25 PM PDT 24 |
Apr 30 03:01:28 PM PDT 24 |
83637926 ps |
| T149 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1475323548 |
|
|
Apr 30 03:01:20 PM PDT 24 |
Apr 30 03:01:25 PM PDT 24 |
179549468 ps |
| T969 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1052503380 |
|
|
Apr 30 03:01:29 PM PDT 24 |
Apr 30 03:01:31 PM PDT 24 |
78922066 ps |
| T970 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3959617255 |
|
|
Apr 30 03:01:16 PM PDT 24 |
Apr 30 03:01:45 PM PDT 24 |
1215192191 ps |
| T146 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3075443871 |
|
|
Apr 30 03:01:30 PM PDT 24 |
Apr 30 03:01:34 PM PDT 24 |
184667064 ps |
| T971 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3073549951 |
|
|
Apr 30 03:01:16 PM PDT 24 |
Apr 30 03:01:19 PM PDT 24 |
44587321 ps |
| T972 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.663860375 |
|
|
Apr 30 03:01:31 PM PDT 24 |
Apr 30 03:01:33 PM PDT 24 |
20049357 ps |
| T973 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.226922469 |
|
|
Apr 30 03:01:21 PM PDT 24 |
Apr 30 03:01:26 PM PDT 24 |
344186242 ps |
| T974 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1302124041 |
|
|
Apr 30 03:01:20 PM PDT 24 |
Apr 30 03:01:42 PM PDT 24 |
1757626760 ps |
| T975 |
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.7824202 |
|
|
Apr 30 03:01:23 PM PDT 24 |
Apr 30 03:01:25 PM PDT 24 |
67082105 ps |
| T976 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2276120158 |
|
|
Apr 30 03:01:23 PM PDT 24 |
Apr 30 03:01:27 PM PDT 24 |
125279367 ps |
| T977 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1087828642 |
|
|
Apr 30 03:01:21 PM PDT 24 |
Apr 30 03:01:23 PM PDT 24 |
17699807 ps |
| T978 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3022871151 |
|
|
Apr 30 03:01:10 PM PDT 24 |
Apr 30 03:01:14 PM PDT 24 |
1634239140 ps |
| T979 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1780291460 |
|
|
Apr 30 03:01:25 PM PDT 24 |
Apr 30 03:01:30 PM PDT 24 |
753763714 ps |
| T980 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3848499794 |
|
|
Apr 30 03:01:23 PM PDT 24 |
Apr 30 03:01:40 PM PDT 24 |
702915880 ps |
| T981 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.161845856 |
|
|
Apr 30 03:01:15 PM PDT 24 |
Apr 30 03:01:18 PM PDT 24 |
224027540 ps |
| T982 |
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.320443093 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:25 PM PDT 24 |
302594010 ps |
| T983 |
/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2599985130 |
|
|
Apr 30 03:01:34 PM PDT 24 |
Apr 30 03:01:36 PM PDT 24 |
36025946 ps |
| T193 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3545341208 |
|
|
Apr 30 03:01:17 PM PDT 24 |
Apr 30 03:01:19 PM PDT 24 |
47967781 ps |
| T984 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3057641155 |
|
|
Apr 30 03:01:17 PM PDT 24 |
Apr 30 03:01:19 PM PDT 24 |
16091819 ps |
| T985 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2276375182 |
|
|
Apr 30 03:01:25 PM PDT 24 |
Apr 30 03:01:28 PM PDT 24 |
74324499 ps |
| T986 |
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3960267716 |
|
|
Apr 30 03:01:30 PM PDT 24 |
Apr 30 03:01:35 PM PDT 24 |
195352703 ps |
| T134 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3372785036 |
|
|
Apr 30 03:01:34 PM PDT 24 |
Apr 30 03:01:39 PM PDT 24 |
123539288 ps |
| T987 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.4188680241 |
|
|
Apr 30 03:01:35 PM PDT 24 |
Apr 30 03:01:37 PM PDT 24 |
30979679 ps |
| T988 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2243077000 |
|
|
Apr 30 03:01:12 PM PDT 24 |
Apr 30 03:01:14 PM PDT 24 |
19951176 ps |
| T989 |
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1542206973 |
|
|
Apr 30 03:01:31 PM PDT 24 |
Apr 30 03:01:34 PM PDT 24 |
94633402 ps |
| T990 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1479359049 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:24 PM PDT 24 |
33589734 ps |
| T142 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2462820948 |
|
|
Apr 30 03:01:22 PM PDT 24 |
Apr 30 03:01:26 PM PDT 24 |
489349723 ps |
| T991 |
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1614526159 |
|
|
Apr 30 03:01:29 PM PDT 24 |
Apr 30 03:01:30 PM PDT 24 |
41125897 ps |
| T194 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2639435694 |
|
|
Apr 30 03:01:11 PM PDT 24 |
Apr 30 03:01:13 PM PDT 24 |
63261895 ps |
| T992 |
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3347358562 |
|
|
Apr 30 03:01:23 PM PDT 24 |
Apr 30 03:01:26 PM PDT 24 |
85692884 ps |
| T993 |
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3621710167 |
|
|
Apr 30 03:01:36 PM PDT 24 |
Apr 30 03:01:38 PM PDT 24 |
80932573 ps |
| T994 |
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.454799963 |
|
|
Apr 30 03:01:24 PM PDT 24 |
Apr 30 03:01:26 PM PDT 24 |
65770327 ps |
| T195 |
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2583783460 |
|
|
Apr 30 03:01:25 PM PDT 24 |
Apr 30 03:01:28 PM PDT 24 |
150752692 ps |
| T995 |
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2244108458 |
|
|
Apr 30 03:01:23 PM PDT 24 |
Apr 30 03:01:27 PM PDT 24 |
132354037 ps |
| T996 |
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3516670372 |
|
|
Apr 30 03:01:16 PM PDT 24 |
Apr 30 03:01:19 PM PDT 24 |
94040789 ps |
| T997 |
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3456443297 |
|
|
Apr 30 03:01:24 PM PDT 24 |
Apr 30 03:01:26 PM PDT 24 |
93002512 ps |
| T150 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1337592581 |
|
|
Apr 30 03:01:16 PM PDT 24 |
Apr 30 03:01:19 PM PDT 24 |
70589105 ps |
| T998 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1183910770 |
|
|
Apr 30 03:01:30 PM PDT 24 |
Apr 30 03:01:31 PM PDT 24 |
60501430 ps |
| T999 |
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2782256458 |
|
|
Apr 30 03:01:31 PM PDT 24 |
Apr 30 03:01:34 PM PDT 24 |
27000982 ps |
| T1000 |
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1226743835 |
|
|
Apr 30 03:01:12 PM PDT 24 |
Apr 30 03:01:14 PM PDT 24 |
41813692 ps |
| T196 |
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.911957456 |
|
|
Apr 30 03:01:25 PM PDT 24 |
Apr 30 03:01:26 PM PDT 24 |
31176657 ps |
| T1001 |
/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3355009133 |
|
|
Apr 30 03:01:16 PM PDT 24 |
Apr 30 03:01:18 PM PDT 24 |
65585320 ps |