Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109773955

1

T1

1204

T2

799994

T3

21258

auto[1]

1407477

1

T2

4810

T4

3267

T5

23672

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

109764836

1

T1

1204

T2

801566

T3

21258

auto[1]

1416596

1

T2

3238

T4

3762

T5

22697

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7423033	1			T1	84		T2	49787		T3	5929
auto[IdleSt]	23050119	1			T1	73		T2	288635		T3	2545
auto[ClkMuxSt]	36976	1			T1	1		T2	128		T3	65
auto[CntIncrSt]	36715	1			T1	1		T2	128		T3	65
auto[CntProgSt]	1879300	1			T1	95		T2	221		T3	1902
auto[TransCheckSt]	28713	1			T1	1		T2	93		T3	65
auto[TokenHashSt]	45754396	1			T1	335		T2	1701		T3	742
auto[FlashRmaSt]	29740	1			T2	85		T3	64		T5	516
auto[TokenCheck0St]	13302	1			T2	54		T3	24		T5	262
auto[TokenCheck1St]	9879	1			T2	46		T3	6		T5	217
auto[TransProgSt]	494417	1			T2	89		T5	424		T12	603
auto[PostTransSt]	14280202	1			T1	614		T2	238591		T3	9851
auto[ScrapSt]	123516	1			T5	1052		T15	3409		T18	622
auto[EscalateSt]	6775453	1			T2	74426		T4	9550		T5	185713
auto[InvalidSt]	11243582	1			T2	150813		T4	9613		T5	396103

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2089	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11243582	1			T2	150813		T4	9613		T5	396103
EscalateSt	6775453	1			T2	74426		T4	9550		T5	185713
ScrapSt	123516	1			T5	1052		T15	3409		T18	622
PostTransSt	14280202	1			T1	614		T2	238591		T3	9851
TransProgSt	494417	1			T2	89		T5	424		T12	603
TokenCheck1St	9879	1			T2	46		T3	6		T5	217
TokenCheck0St	13302	1			T2	54		T3	24		T5	262
FlashRmaSt	29740	1			T2	85		T3	64		T5	516
TokenHashSt	45754396	1			T1	335		T2	1701		T3	742
TransCheckSt	28713	1			T1	1		T2	93		T3	65
CntProgSt	1879300	1			T1	95		T2	221		T3	1902
CntIncrSt	36715	1			T1	1		T2	128		T3	65
ClkMuxSt	36976	1			T1	1		T2	128		T3	65
IdleSt	23050119	1			T1	73		T2	288635		T3	2545
ResetSt	7423033	1			T1	84		T2	49787		T3	5929
arcs[ResetSt=>IdleSt]	56049	1			T1	1		T2	203		T3	66
arcs[IdleSt=>ScrapSt]	279	1			T5	9		T15	4		T18	3
arcs[IdleSt=>ClkMuxSt]	36770	1			T1	1		T2	128		T3	65
arcs[ClkMuxSt=>CntIncrSt]	36715	1			T1	1		T2	128		T3	65
arcs[CntIncrSt=>PostTransSt]	1976	1			T2	14		T5	79		T12	6
arcs[CntIncrSt=>CntProgSt]	34682	1			T1	1		T2	114		T3	65
arcs[CntProgSt=>PostTransSt]	4947	1			T2	21		T5	136		T6	8
arcs[CntProgSt=>TransCheckSt]	28713	1			T1	1		T2	93		T3	65
arcs[TransCheckSt=>PostTransSt]	3879	1			T2	10		T3	28		T5	56
arcs[TransCheckSt=>TokenHashSt]	24683	1			T1	1		T2	83		T3	37
arcs[TokenHashSt=>PostTransSt]	10693	1			T1	1		T2	29		T3	13
arcs[TokenHashSt=>FlashRmaSt]	13386	1			T2	54		T3	24		T5	262
arcs[FlashRmaSt=>TokenCheck0St]	13302	1			T2	54		T3	24		T5	262
arcs[TokenCheck0St=>PostTransSt]	3395	1			T2	8		T3	18		T5	45
arcs[TokenCheck0St=>TokenCheck1St]	9879	1			T2	46		T3	6		T5	217
arcs[TokenCheck1St=>PostTransSt]	665	1			T2	1		T3	6		T5	3
arcs[TransProgSt=>PostTransSt]	8367	1			T2	45		T5	214		T12	13
arcs[IdleSt=>EscalateSt]	211	1			T50	7		T46	8		T47	8
arcs[ClkMuxSt=>EscalateSt]	55	1			T46	2		T47	2		T48	2
arcs[CntIncrSt=>EscalateSt]	57	1			T49	3		T50	3		T46	1
arcs[CntProgSt=>EscalateSt]	1022	1			T49	32		T50	16		T46	6
arcs[TransCheckSt=>EscalateSt]	151	1			T49	1		T50	1		T46	6
arcs[TokenHashSt=>EscalateSt]	604	1			T15	7		T49	10		T50	10
arcs[FlashRmaSt=>EscalateSt]	84	1			T50	2		T46	3		T47	3
arcs[TokenCheck0St=>EscalateSt]	28	1			T50	2		T47	3		T48	1
arcs[TokenCheck1St=>EscalateSt]	139	1			T49	4		T50	2		T46	1
arcs[TransProgSt=>EscalateSt]	708	1			T49	18		T50	15		T46	7
arcs[PostTransSt=>EscalateSt]	5178	1			T2	22		T5	140		T6	8
arcs[InvalidSt=>EscalateSt]	14556	1			T2	60		T4	71		T5	332

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7422888	1			T1	84		T2	49787		T3	5929
auto[0]	auto[IdleSt]	23049973	1			T1	73		T2	288635		T3	2545
auto[0]	auto[ClkMuxSt]	36933	1			T1	1		T2	128		T3	65
auto[0]	auto[CntIncrSt]	36676	1			T1	1		T2	128		T3	65
auto[0]	auto[CntProgSt]	1878614	1			T1	95		T2	221		T3	1902
auto[0]	auto[TransCheckSt]	28612	1			T1	1		T2	93		T3	65
auto[0]	auto[TokenHashSt]	45753999	1			T1	335		T2	1701		T3	742
auto[0]	auto[FlashRmaSt]	29689	1			T2	85		T3	64		T5	516
auto[0]	auto[TokenCheck0St]	13285	1			T2	54		T3	24		T5	262
auto[0]	auto[TokenCheck1St]	9781	1			T2	46		T3	6		T5	217
auto[0]	auto[TransProgSt]	493955	1			T2	89		T5	424		T12	603
auto[0]	auto[PostTransSt]	14277578	1			T1	614		T2	238576		T3	9851
auto[0]	auto[ScrapSt]	123473	1			T5	1052		T15	3409		T18	622
auto[0]	auto[EscalateSt]	5380055	1			T2	69665		T4	6316		T5	162282
auto[0]	auto[InvalidSt]	11236355	1			T2	150779		T4	9580		T5	395934
auto[1]	auto[ResetSt]	145	1			T49	4		T46	6		T47	4
auto[1]	auto[IdleSt]	146	1			T50	7		T46	5		T47	4
auto[1]	auto[ClkMuxSt]	43	1			T46	1		T47	2		T48	2
auto[1]	auto[CntIncrSt]	39	1			T49	3		T50	2		T46	1
auto[1]	auto[CntProgSt]	686	1			T49	24		T50	9		T46	3
auto[1]	auto[TransCheckSt]	101	1			T49	1		T50	1		T46	4
auto[1]	auto[TokenHashSt]	397	1			T15	1		T49	4		T50	10
auto[1]	auto[FlashRmaSt]	51	1			T50	1		T46	2		T47	1
auto[1]	auto[TokenCheck0St]	17	1			T50	2		T47	2		T48	1
auto[1]	auto[TokenCheck1St]	98	1			T49	2		T47	1		T203	1
auto[1]	auto[TransProgSt]	462	1			T49	12		T50	8		T46	6
auto[1]	auto[PostTransSt]	2624	1			T2	15		T5	72		T6	6
auto[1]	auto[ScrapSt]	43	1			T47	1		T203	1		T204	1
auto[1]	auto[EscalateSt]	1395398	1			T2	4761		T4	3234		T5	23431
auto[1]	auto[InvalidSt]	7227	1			T2	34		T4	33		T5	169

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7422884	1			T1	84		T2	49787		T3	5929
auto[0]	auto[IdleSt]	23049973	1			T1	73		T2	288635		T3	2545
auto[0]	auto[ClkMuxSt]	36936	1			T1	1		T2	128		T3	65
auto[0]	auto[CntIncrSt]	36678	1			T1	1		T2	128		T3	65
auto[0]	auto[CntProgSt]	1878624	1			T1	95		T2	221		T3	1902
auto[0]	auto[TransCheckSt]	28613	1			T1	1		T2	93		T3	65
auto[0]	auto[TokenHashSt]	45753999	1			T1	335		T2	1701		T3	742
auto[0]	auto[FlashRmaSt]	29681	1			T2	85		T3	64		T5	516
auto[0]	auto[TokenCheck0St]	13282	1			T2	54		T3	24		T5	262
auto[0]	auto[TokenCheck1St]	9797	1			T2	46		T3	6		T5	217
auto[0]	auto[TransProgSt]	493929	1			T2	89		T5	424		T12	603
auto[0]	auto[PostTransSt]	14277572	1			T1	614		T2	238584		T3	9851
auto[0]	auto[ScrapSt]	123479	1			T5	1052		T15	3409		T18	622
auto[0]	auto[EscalateSt]	5371047	1			T2	71221		T4	5826		T5	163247
auto[0]	auto[InvalidSt]	11236253	1			T2	150787		T4	9575		T5	395940
auto[1]	auto[ResetSt]	149	1			T49	1		T50	1		T46	2
auto[1]	auto[IdleSt]	146	1			T50	2		T46	5		T47	6
auto[1]	auto[ClkMuxSt]	40	1			T46	2		T47	1		T48	2
auto[1]	auto[CntIncrSt]	37	1			T49	2		T50	1		T203	1
auto[1]	auto[CntProgSt]	676	1			T49	18		T50	10		T46	6
auto[1]	auto[TransCheckSt]	100	1			T49	1		T46	4		T47	2
auto[1]	auto[TokenHashSt]	397	1			T15	6		T49	8		T50	6
auto[1]	auto[FlashRmaSt]	59	1			T50	2		T46	1		T47	3
auto[1]	auto[TokenCheck0St]	20	1			T50	1		T47	1		T48	1
auto[1]	auto[TokenCheck1St]	82	1			T49	4		T50	2		T46	1
auto[1]	auto[TransProgSt]	488	1			T49	11		T50	8		T46	4
auto[1]	auto[PostTransSt]	2630	1			T2	7		T5	68		T6	2
auto[1]	auto[ScrapSt]	37	1			T49	1		T47	3		T48	1
auto[1]	auto[EscalateSt]	1404406	1			T2	3205		T4	3724		T5	22466
auto[1]	auto[InvalidSt]	7329	1			T2	26		T4	38		T5	163