Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

91506560

1

T1

2155

T2

38298

T3

910

auto[1]

1361054

1

T2

2079

T5

7802

T14

396

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

91502456

1

T1

2155

T2

38793

T3

910

auto[1]

1365158

1

T2

1584

T5

5514

T14

198

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7055644	1			T1	109		T2	8213		T3	117
auto[IdleSt]	20488122	1			T1	2046		T2	9096		T3	16
auto[ClkMuxSt]	34371	1			T2	77		T3	1		T4	55
auto[CntIncrSt]	34149	1			T2	77		T3	1		T4	55
auto[CntProgSt]	1387863	1			T2	537		T3	2		T4	110
auto[TransCheckSt]	26271	1			T2	55		T3	1		T4	55
auto[TokenHashSt]	34524623	1			T2	1144		T3	13		T4	294
auto[FlashRmaSt]	27368	1			T2	83		T4	32		T5	23
auto[TokenCheck0St]	12180	1			T2	49		T4	25		T5	14
auto[TokenCheck1St]	9023	1			T2	33		T4	13		T5	14
auto[TransProgSt]	344367	1			T2	335		T5	41		T14	109
auto[PostTransSt]	11785374	1			T2	12444		T3	759		T4	8897
auto[ScrapSt]	291235	1			T5	6		T7	458		T26	1455
auto[EscalateSt]	6395821	1			T2	5427		T5	9414		T14	896
auto[InvalidSt]	10449295	1			T2	2807		T20	5254		T22	5136

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1908	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10449295	1			T2	2807		T20	5254		T22	5136
EscalateSt	6395821	1			T2	5427		T5	9414		T14	896
ScrapSt	291235	1			T5	6		T7	458		T26	1455
PostTransSt	11785374	1			T2	12444		T3	759		T4	8897
TransProgSt	344367	1			T2	335		T5	41		T14	109
TokenCheck1St	9023	1			T2	33		T4	13		T5	14
TokenCheck0St	12180	1			T2	49		T4	25		T5	14
FlashRmaSt	27368	1			T2	83		T4	32		T5	23
TokenHashSt	34524623	1			T2	1144		T3	13		T4	294
TransCheckSt	26271	1			T2	55		T3	1		T4	55
CntProgSt	1387863	1			T2	537		T3	2		T4	110
CntIncrSt	34149	1			T2	77		T3	1		T4	55
ClkMuxSt	34371	1			T2	77		T3	1		T4	55
IdleSt	20488122	1			T1	2046		T2	9096		T3	16
ResetSt	7055644	1			T1	109		T2	8213		T3	117
arcs[ResetSt=>IdleSt]	52272	1			T1	1		T2	93		T3	1
arcs[IdleSt=>ScrapSt]	267	1			T5	2		T7	4		T26	5
arcs[IdleSt=>ClkMuxSt]	34207	1			T2	77		T3	1		T4	55
arcs[ClkMuxSt=>CntIncrSt]	34149	1			T2	77		T3	1		T4	55
arcs[CntIncrSt=>PostTransSt]	1741	1			T14	7		T7	24		T8	9
arcs[CntIncrSt=>CntProgSt]	32330	1			T2	77		T3	1		T4	55
arcs[CntProgSt=>PostTransSt]	4891	1			T2	22		T14	6		T19	19
arcs[CntProgSt=>TransCheckSt]	26271	1			T2	55		T3	1		T4	55
arcs[TransCheckSt=>PostTransSt]	3489	1			T4	28		T14	9		T15	27
arcs[TransCheckSt=>TokenHashSt]	22716	1			T2	55		T3	1		T4	27
arcs[TokenHashSt=>PostTransSt]	9872	1			T2	6		T3	1		T4	2
arcs[TokenHashSt=>FlashRmaSt]	12277	1			T2	49		T4	25		T5	16
arcs[FlashRmaSt=>TokenCheck0St]	12180	1			T2	49		T4	25		T5	14
arcs[TokenCheck0St=>PostTransSt]	3133	1			T2	16		T4	12		T14	8
arcs[TokenCheck0St=>TokenCheck1St]	9023	1			T2	33		T4	13		T5	14
arcs[TokenCheck1St=>PostTransSt]	679	1			T4	13		T14	1		T15	8
arcs[TransProgSt=>PostTransSt]	7404	1			T2	33		T5	1		T14	9
arcs[IdleSt=>EscalateSt]	192	1			T5	6		T53	8		T43	7
arcs[ClkMuxSt=>EscalateSt]	58	1			T5	2		T16	1		T43	1
arcs[CntIncrSt=>EscalateSt]	78	1			T16	1		T53	1		T43	3
arcs[CntProgSt=>EscalateSt]	1168	1			T5	19		T16	36		T53	26
arcs[TransCheckSt=>EscalateSt]	66	1			T43	2		T54	10		T58	2
arcs[TokenHashSt=>EscalateSt]	567	1			T5	4		T16	9		T53	10
arcs[FlashRmaSt=>EscalateSt]	97	1			T5	2		T16	4		T53	1
arcs[TokenCheck0St=>EscalateSt]	24	1			T43	1		T54	2		T58	1
arcs[TokenCheck1St=>EscalateSt]	140	1			T5	1		T16	7		T53	3
arcs[TransProgSt=>EscalateSt]	800	1			T5	12		T16	18		T53	17
arcs[PostTransSt=>EscalateSt]	5065	1			T2	22		T5	1		T14	6
arcs[InvalidSt=>EscalateSt]	13525	1			T2	15		T20	73		T22	69

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7055481	1			T1	109		T2	8213		T3	117
auto[0]	auto[IdleSt]	20487994	1			T1	2046		T2	9096		T3	16
auto[0]	auto[ClkMuxSt]	34337	1			T2	77		T3	1		T4	55
auto[0]	auto[CntIncrSt]	34097	1			T2	77		T3	1		T4	55
auto[0]	auto[CntProgSt]	1387063	1			T2	537		T3	2		T4	110
auto[0]	auto[TransCheckSt]	26228	1			T2	55		T3	1		T4	55
auto[0]	auto[TokenHashSt]	34524244	1			T2	1144		T3	13		T4	294
auto[0]	auto[FlashRmaSt]	27302	1			T2	83		T4	32		T5	21
auto[0]	auto[TokenCheck0St]	12161	1			T2	49		T4	25		T5	14
auto[0]	auto[TokenCheck1St]	8935	1			T2	33		T4	13		T5	14
auto[0]	auto[TransProgSt]	343838	1			T2	335		T5	32		T14	109
auto[0]	auto[PostTransSt]	11782808	1			T2	12431		T3	759		T4	8897
auto[0]	auto[ScrapSt]	291192	1			T5	4		T7	458		T26	1455
auto[0]	auto[EscalateSt]	5046398	1			T2	3369		T5	1654		T14	504
auto[0]	auto[InvalidSt]	10442574	1			T2	2799		T20	5221		T22	5105
auto[1]	auto[ResetSt]	163	1			T5	2		T16	3		T53	2
auto[1]	auto[IdleSt]	128	1			T5	5		T53	5		T43	3
auto[1]	auto[ClkMuxSt]	34	1			T5	1		T200	1		T147	1
auto[1]	auto[CntIncrSt]	52	1			T53	1		T43	2		T54	2
auto[1]	auto[CntProgSt]	800	1			T5	16		T16	23		T53	21
auto[1]	auto[TransCheckSt]	43	1			T43	2		T54	7		T58	2
auto[1]	auto[TokenHashSt]	379	1			T5	4		T16	6		T53	5
auto[1]	auto[FlashRmaSt]	66	1			T5	2		T16	4		T53	1
auto[1]	auto[TokenCheck0St]	19	1			T43	1		T54	1		T201	1
auto[1]	auto[TokenCheck1St]	88	1			T16	2		T53	1		T43	5
auto[1]	auto[TransProgSt]	529	1			T5	9		T16	10		T53	15
auto[1]	auto[PostTransSt]	2566	1			T2	13		T5	1		T14	4
auto[1]	auto[ScrapSt]	43	1			T5	2		T43	1		T161	1
auto[1]	auto[EscalateSt]	1349423	1			T2	2058		T5	7760		T14	392
auto[1]	auto[InvalidSt]	6721	1			T2	8		T20	33		T22	31

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7055471	1			T1	109		T2	8213		T3	117
auto[0]	auto[IdleSt]	20487990	1			T1	2046		T2	9096		T3	16
auto[0]	auto[ClkMuxSt]	34328	1			T2	77		T3	1		T4	55
auto[0]	auto[CntIncrSt]	34103	1			T2	77		T3	1		T4	55
auto[0]	auto[CntProgSt]	1387096	1			T2	537		T3	2		T4	110
auto[0]	auto[TransCheckSt]	26225	1			T2	55		T3	1		T4	55
auto[0]	auto[TokenHashSt]	34524266	1			T2	1144		T3	13		T4	294
auto[0]	auto[FlashRmaSt]	27303	1			T2	83		T4	32		T5	23
auto[0]	auto[TokenCheck0St]	12163	1			T2	49		T4	25		T5	14
auto[0]	auto[TokenCheck1St]	8927	1			T2	33		T4	13		T5	13
auto[0]	auto[TransProgSt]	343815	1			T2	335		T5	37		T14	109
auto[0]	auto[PostTransSt]	11782833	1			T2	12435		T3	759		T4	8897
auto[0]	auto[ScrapSt]	291187	1			T5	4		T7	458		T26	1455
auto[0]	auto[EscalateSt]	5042350	1			T2	3859		T5	3930		T14	700
auto[0]	auto[InvalidSt]	10442491	1			T2	2800		T20	5214		T22	5098
auto[1]	auto[ResetSt]	173	1			T5	2		T16	3		T53	2
auto[1]	auto[IdleSt]	132	1			T5	3		T53	4		T43	6
auto[1]	auto[ClkMuxSt]	43	1			T5	2		T16	1		T43	1
auto[1]	auto[CntIncrSt]	46	1			T16	1		T43	2		T54	3
auto[1]	auto[CntProgSt]	767	1			T5	14		T16	23		T53	10
auto[1]	auto[TransCheckSt]	46	1			T43	2		T54	8		T58	1
auto[1]	auto[TokenHashSt]	357	1			T5	1		T16	5		T53	7
auto[1]	auto[FlashRmaSt]	65	1			T16	3		T53	1		T202	1
auto[1]	auto[TokenCheck0St]	17	1			T43	1		T54	1		T58	1
auto[1]	auto[TokenCheck1St]	96	1			T5	1		T16	5		T53	2
auto[1]	auto[TransProgSt]	552	1			T5	4		T16	14		T53	10
auto[1]	auto[PostTransSt]	2541	1			T2	9		T5	1		T14	2
auto[1]	auto[ScrapSt]	48	1			T5	2		T54	2		T202	1
auto[1]	auto[EscalateSt]	1353471	1			T2	1568		T5	5484		T14	196
auto[1]	auto[InvalidSt]	6804	1			T2	7		T20	40		T22	38