Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.87 97.82 96.03 93.31 97.62 98.52 98.51 96.29


Total test records in report: 1000
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T810 /workspace/coverage/default/48.lc_ctrl_security_escalation.2405104915 May 05 01:47:33 PM PDT 24 May 05 01:47:40 PM PDT 24 571897529 ps
T811 /workspace/coverage/default/18.lc_ctrl_sec_token_digest.2767034302 May 05 01:46:11 PM PDT 24 May 05 01:46:19 PM PDT 24 918871668 ps
T812 /workspace/coverage/default/26.lc_ctrl_errors.2107732616 May 05 01:46:40 PM PDT 24 May 05 01:46:58 PM PDT 24 1124545574 ps
T813 /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1478810691 May 05 01:45:56 PM PDT 24 May 05 01:45:57 PM PDT 24 11988281 ps
T814 /workspace/coverage/default/10.lc_ctrl_errors.871256567 May 05 01:45:46 PM PDT 24 May 05 01:46:02 PM PDT 24 695018518 ps
T815 /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2732436622 May 05 01:45:41 PM PDT 24 May 05 01:45:50 PM PDT 24 303891147 ps
T816 /workspace/coverage/default/45.lc_ctrl_errors.3060038239 May 05 01:47:17 PM PDT 24 May 05 01:47:29 PM PDT 24 221699517 ps
T817 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2666898301 May 05 01:47:20 PM PDT 24 May 05 01:47:21 PM PDT 24 24643542 ps
T818 /workspace/coverage/default/12.lc_ctrl_alert_test.725847605 May 05 01:45:59 PM PDT 24 May 05 01:46:00 PM PDT 24 18549469 ps
T819 /workspace/coverage/default/29.lc_ctrl_stress_all.1110893416 May 05 01:46:37 PM PDT 24 May 05 01:48:13 PM PDT 24 3784832708 ps
T820 /workspace/coverage/default/36.lc_ctrl_errors.2198010679 May 05 01:46:52 PM PDT 24 May 05 01:47:05 PM PDT 24 528060946 ps
T821 /workspace/coverage/default/2.lc_ctrl_sec_mubi.1571051858 May 05 01:45:29 PM PDT 24 May 05 01:45:37 PM PDT 24 730833209 ps
T822 /workspace/coverage/default/45.lc_ctrl_security_escalation.2187251241 May 05 01:47:24 PM PDT 24 May 05 01:47:37 PM PDT 24 1076568831 ps
T823 /workspace/coverage/default/48.lc_ctrl_alert_test.2093928884 May 05 01:47:22 PM PDT 24 May 05 01:47:23 PM PDT 24 17150148 ps
T824 /workspace/coverage/default/11.lc_ctrl_prog_failure.2730122732 May 05 01:46:04 PM PDT 24 May 05 01:46:07 PM PDT 24 89022437 ps
T825 /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3856824118 May 05 01:46:46 PM PDT 24 May 05 01:46:56 PM PDT 24 473265765 ps
T826 /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2543786725 May 05 01:46:05 PM PDT 24 May 05 01:46:10 PM PDT 24 391238985 ps
T827 /workspace/coverage/default/39.lc_ctrl_errors.3613479806 May 05 01:46:53 PM PDT 24 May 05 01:47:09 PM PDT 24 451303243 ps
T828 /workspace/coverage/default/22.lc_ctrl_state_post_trans.1439446959 May 05 01:46:27 PM PDT 24 May 05 01:46:34 PM PDT 24 256769192 ps
T829 /workspace/coverage/default/20.lc_ctrl_security_escalation.3903325768 May 05 01:46:19 PM PDT 24 May 05 01:46:32 PM PDT 24 726308900 ps
T830 /workspace/coverage/default/27.lc_ctrl_sec_token_mux.3774326010 May 05 01:46:36 PM PDT 24 May 05 01:46:48 PM PDT 24 2465440516 ps
T831 /workspace/coverage/default/10.lc_ctrl_smoke.1821392805 May 05 01:45:46 PM PDT 24 May 05 01:45:52 PM PDT 24 174644770 ps
T832 /workspace/coverage/default/23.lc_ctrl_smoke.3140647401 May 05 01:46:27 PM PDT 24 May 05 01:46:32 PM PDT 24 44216534 ps
T833 /workspace/coverage/default/26.lc_ctrl_stress_all.2129340951 May 05 01:46:39 PM PDT 24 May 05 01:46:47 PM PDT 24 339640641 ps
T834 /workspace/coverage/default/1.lc_ctrl_alert_test.4110764046 May 05 01:45:31 PM PDT 24 May 05 01:45:33 PM PDT 24 29019541 ps
T835 /workspace/coverage/default/20.lc_ctrl_sec_token_digest.927272430 May 05 01:46:27 PM PDT 24 May 05 01:46:43 PM PDT 24 470348930 ps
T836 /workspace/coverage/default/29.lc_ctrl_state_failure.2665545537 May 05 01:46:45 PM PDT 24 May 05 01:47:15 PM PDT 24 1101415356 ps
T837 /workspace/coverage/default/24.lc_ctrl_prog_failure.366442437 May 05 01:46:36 PM PDT 24 May 05 01:46:39 PM PDT 24 270717342 ps
T838 /workspace/coverage/default/46.lc_ctrl_errors.2690788233 May 05 01:47:17 PM PDT 24 May 05 01:47:28 PM PDT 24 234816213 ps
T839 /workspace/coverage/default/16.lc_ctrl_alert_test.2070297734 May 05 01:46:11 PM PDT 24 May 05 01:46:13 PM PDT 24 414068170 ps
T840 /workspace/coverage/default/6.lc_ctrl_prog_failure.1325397603 May 05 01:45:34 PM PDT 24 May 05 01:45:37 PM PDT 24 144239068 ps
T841 /workspace/coverage/default/17.lc_ctrl_security_escalation.652203440 May 05 01:46:10 PM PDT 24 May 05 01:46:18 PM PDT 24 256216635 ps
T842 /workspace/coverage/default/18.lc_ctrl_security_escalation.2361975452 May 05 01:46:15 PM PDT 24 May 05 01:46:25 PM PDT 24 1443986114 ps
T843 /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2863621268 May 05 01:46:13 PM PDT 24 May 05 01:46:29 PM PDT 24 681145794 ps
T844 /workspace/coverage/default/17.lc_ctrl_prog_failure.4151316379 May 05 01:46:08 PM PDT 24 May 05 01:46:11 PM PDT 24 51465871 ps
T845 /workspace/coverage/default/17.lc_ctrl_state_failure.1829613408 May 05 01:46:16 PM PDT 24 May 05 01:46:41 PM PDT 24 399110230 ps
T846 /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1241234518 May 05 01:46:45 PM PDT 24 May 05 01:47:04 PM PDT 24 2928019518 ps
T847 /workspace/coverage/default/30.lc_ctrl_stress_all.1062013261 May 05 01:46:43 PM PDT 24 May 05 01:49:31 PM PDT 24 18238987015 ps
T848 /workspace/coverage/default/34.lc_ctrl_state_failure.3171353969 May 05 01:46:52 PM PDT 24 May 05 01:47:26 PM PDT 24 1093315719 ps
T849 /workspace/coverage/default/25.lc_ctrl_sec_mubi.1682205094 May 05 01:46:45 PM PDT 24 May 05 01:47:00 PM PDT 24 1217291723 ps
T850 /workspace/coverage/default/36.lc_ctrl_alert_test.3800130795 May 05 01:46:52 PM PDT 24 May 05 01:46:53 PM PDT 24 19468227 ps
T851 /workspace/coverage/default/5.lc_ctrl_alert_test.2013847734 May 05 01:45:38 PM PDT 24 May 05 01:45:40 PM PDT 24 44900811 ps
T852 /workspace/coverage/default/12.lc_ctrl_sec_token_digest.473335487 May 05 01:45:47 PM PDT 24 May 05 01:46:02 PM PDT 24 2167495305 ps
T76 /workspace/coverage/default/1.lc_ctrl_claim_transition_if.850595671 May 05 01:45:24 PM PDT 24 May 05 01:45:26 PM PDT 24 30132676 ps
T853 /workspace/coverage/default/31.lc_ctrl_state_post_trans.1129312230 May 05 01:46:37 PM PDT 24 May 05 01:46:45 PM PDT 24 165154724 ps
T854 /workspace/coverage/default/46.lc_ctrl_state_failure.1311066067 May 05 01:47:19 PM PDT 24 May 05 01:47:44 PM PDT 24 392054380 ps
T855 /workspace/coverage/default/9.lc_ctrl_prog_failure.1696220862 May 05 01:45:42 PM PDT 24 May 05 01:45:46 PM PDT 24 117913470 ps
T856 /workspace/coverage/default/30.lc_ctrl_prog_failure.151991405 May 05 01:46:40 PM PDT 24 May 05 01:46:43 PM PDT 24 27280565 ps
T857 /workspace/coverage/default/35.lc_ctrl_smoke.2448037340 May 05 01:46:47 PM PDT 24 May 05 01:46:51 PM PDT 24 194276997 ps
T858 /workspace/coverage/default/16.lc_ctrl_state_post_trans.3143105551 May 05 01:46:08 PM PDT 24 May 05 01:46:12 PM PDT 24 281147489 ps
T859 /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.383486379 May 05 01:45:46 PM PDT 24 May 05 01:45:49 PM PDT 24 37230295 ps
T860 /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3895166662 May 05 01:46:38 PM PDT 24 May 05 01:46:40 PM PDT 24 28736233 ps
T861 /workspace/coverage/default/49.lc_ctrl_state_failure.3564962806 May 05 01:47:16 PM PDT 24 May 05 01:47:45 PM PDT 24 478345638 ps
T862 /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1427980337 May 05 01:46:27 PM PDT 24 May 05 01:46:34 PM PDT 24 180146885 ps
T863 /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.3322487583 May 05 01:45:57 PM PDT 24 May 05 01:47:26 PM PDT 24 17013912440 ps
T864 /workspace/coverage/default/35.lc_ctrl_stress_all.514508471 May 05 01:46:51 PM PDT 24 May 05 01:49:11 PM PDT 24 3789109841 ps
T865 /workspace/coverage/default/47.lc_ctrl_jtag_access.1488916118 May 05 01:47:25 PM PDT 24 May 05 01:47:32 PM PDT 24 461176551 ps
T866 /workspace/coverage/default/29.lc_ctrl_security_escalation.715477469 May 05 01:46:42 PM PDT 24 May 05 01:46:51 PM PDT 24 485003898 ps
T867 /workspace/coverage/default/17.lc_ctrl_state_post_trans.3654325218 May 05 01:46:08 PM PDT 24 May 05 01:46:16 PM PDT 24 120179965 ps
T868 /workspace/coverage/default/7.lc_ctrl_prog_failure.3189889882 May 05 01:45:41 PM PDT 24 May 05 01:45:46 PM PDT 24 756955446 ps
T869 /workspace/coverage/default/18.lc_ctrl_state_failure.20169091 May 05 01:46:13 PM PDT 24 May 05 01:46:32 PM PDT 24 889059873 ps
T870 /workspace/coverage/default/40.lc_ctrl_security_escalation.2092635290 May 05 01:46:56 PM PDT 24 May 05 01:47:08 PM PDT 24 276763052 ps
T871 /workspace/coverage/default/28.lc_ctrl_alert_test.3016481037 May 05 01:46:42 PM PDT 24 May 05 01:46:44 PM PDT 24 55480400 ps
T872 /workspace/coverage/default/19.lc_ctrl_stress_all.285820798 May 05 01:46:27 PM PDT 24 May 05 01:47:55 PM PDT 24 12661506036 ps
T873 /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1466643980 May 05 01:46:35 PM PDT 24 May 05 01:46:55 PM PDT 24 598270581 ps
T108 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3085179297 May 05 02:37:56 PM PDT 24 May 05 02:37:57 PM PDT 24 37373174 ps
T102 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1227031513 May 05 02:37:28 PM PDT 24 May 05 02:37:32 PM PDT 24 766068308 ps
T116 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2343677495 May 05 02:37:56 PM PDT 24 May 05 02:37:57 PM PDT 24 18251885 ps
T117 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3452868955 May 05 02:37:17 PM PDT 24 May 05 02:37:54 PM PDT 24 5521143793 ps
T109 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2541466042 May 05 02:38:03 PM PDT 24 May 05 02:38:05 PM PDT 24 284149806 ps
T110 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3615598962 May 05 02:37:23 PM PDT 24 May 05 02:37:25 PM PDT 24 67285571 ps
T142 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3511839442 May 05 02:37:27 PM PDT 24 May 05 02:37:28 PM PDT 24 24563869 ps
T193 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.431636440 May 05 02:37:33 PM PDT 24 May 05 02:37:35 PM PDT 24 143988757 ps
T103 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.743718055 May 05 02:37:18 PM PDT 24 May 05 02:37:21 PM PDT 24 1290551052 ps
T182 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1414067166 May 05 02:37:17 PM PDT 24 May 05 02:37:19 PM PDT 24 22109280 ps
T183 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3124409105 May 05 02:37:32 PM PDT 24 May 05 02:37:33 PM PDT 24 35451576 ps
T135 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3048476516 May 05 02:37:37 PM PDT 24 May 05 02:37:45 PM PDT 24 1139599131 ps
T105 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2108499181 May 05 02:37:38 PM PDT 24 May 05 02:37:40 PM PDT 24 47107346 ps
T104 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1075556393 May 05 02:38:04 PM PDT 24 May 05 02:38:08 PM PDT 24 443590211 ps
T184 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.591683207 May 05 02:38:02 PM PDT 24 May 05 02:38:04 PM PDT 24 60665386 ps
T106 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.4196785349 May 05 02:38:01 PM PDT 24 May 05 02:38:03 PM PDT 24 57286177 ps
T874 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3112746688 May 05 02:37:31 PM PDT 24 May 05 02:37:33 PM PDT 24 44930962 ps
T875 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.733155398 May 05 02:37:37 PM PDT 24 May 05 02:37:38 PM PDT 24 165530740 ps
T107 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.996488488 May 05 02:38:02 PM PDT 24 May 05 02:38:08 PM PDT 24 141847788 ps
T111 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2289751426 May 05 02:37:59 PM PDT 24 May 05 02:38:01 PM PDT 24 37393865 ps
T137 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1829324840 May 05 02:37:50 PM PDT 24 May 05 02:37:53 PM PDT 24 720464197 ps
T157 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2448309113 May 05 02:37:22 PM PDT 24 May 05 02:37:25 PM PDT 24 781549491 ps
T143 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3829139350 May 05 02:37:22 PM PDT 24 May 05 02:37:24 PM PDT 24 25090206 ps
T122 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.825768123 May 05 02:37:28 PM PDT 24 May 05 02:37:30 PM PDT 24 350148714 ps
T876 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4221445438 May 05 02:37:32 PM PDT 24 May 05 02:37:34 PM PDT 24 512437627 ps
T124 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3661498790 May 05 02:37:55 PM PDT 24 May 05 02:37:57 PM PDT 24 274696335 ps
T144 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.971012158 May 05 02:37:47 PM PDT 24 May 05 02:37:49 PM PDT 24 53467817 ps
T877 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2822974843 May 05 02:37:20 PM PDT 24 May 05 02:37:22 PM PDT 24 54893370 ps
T112 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3971677124 May 05 02:37:21 PM PDT 24 May 05 02:37:26 PM PDT 24 235055785 ps
T113 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2500632784 May 05 02:38:06 PM PDT 24 May 05 02:38:09 PM PDT 24 73911107 ps
T115 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1539078889 May 05 02:37:32 PM PDT 24 May 05 02:37:36 PM PDT 24 515537961 ps
T878 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2784840795 May 05 02:38:01 PM PDT 24 May 05 02:38:02 PM PDT 24 42170126 ps
T879 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3339849163 May 05 02:38:02 PM PDT 24 May 05 02:38:08 PM PDT 24 140222743 ps
T131 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2131601554 May 05 02:37:48 PM PDT 24 May 05 02:37:51 PM PDT 24 48657872 ps
T114 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.601644874 May 05 02:37:54 PM PDT 24 May 05 02:37:59 PM PDT 24 414157736 ps
T880 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1579549848 May 05 02:37:33 PM PDT 24 May 05 02:37:35 PM PDT 24 31421039 ps
T136 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3038419032 May 05 02:37:40 PM PDT 24 May 05 02:37:44 PM PDT 24 321816971 ps
T881 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3116143546 May 05 02:37:34 PM PDT 24 May 05 02:37:37 PM PDT 24 951217598 ps
T882 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.877420580 May 05 02:37:42 PM PDT 24 May 05 02:37:47 PM PDT 24 406721281 ps
T883 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.742863846 May 05 02:37:36 PM PDT 24 May 05 02:37:42 PM PDT 24 926233470 ps
T185 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3874853132 May 05 02:37:16 PM PDT 24 May 05 02:37:18 PM PDT 24 36465105 ps
T884 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1555164568 May 05 02:37:38 PM PDT 24 May 05 02:37:40 PM PDT 24 227138407 ps
T126 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2147521305 May 05 02:38:05 PM PDT 24 May 05 02:38:09 PM PDT 24 228380576 ps
T885 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2671057104 May 05 02:37:27 PM PDT 24 May 05 02:37:50 PM PDT 24 1207598167 ps
T186 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1661352002 May 05 02:37:35 PM PDT 24 May 05 02:37:37 PM PDT 24 184770889 ps
T187 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.495117773 May 05 02:37:42 PM PDT 24 May 05 02:37:44 PM PDT 24 178261675 ps
T886 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4053484459 May 05 02:37:48 PM PDT 24 May 05 02:37:50 PM PDT 24 46965565 ps
T887 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2856785024 May 05 02:37:33 PM PDT 24 May 05 02:37:39 PM PDT 24 409179083 ps
T888 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.376217850 May 05 02:37:31 PM PDT 24 May 05 02:37:35 PM PDT 24 235606375 ps
T889 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1756388221 May 05 02:37:20 PM PDT 24 May 05 02:37:23 PM PDT 24 37673740 ps
T890 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4186202714 May 05 02:37:21 PM PDT 24 May 05 02:37:24 PM PDT 24 1594011318 ps
T891 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1388256278 May 05 02:37:41 PM PDT 24 May 05 02:37:43 PM PDT 24 35689520 ps
T892 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2339309164 May 05 02:37:58 PM PDT 24 May 05 02:38:00 PM PDT 24 36347229 ps
T123 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1621178819 May 05 02:37:27 PM PDT 24 May 05 02:37:33 PM PDT 24 615487829 ps
T893 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.440565867 May 05 02:37:27 PM PDT 24 May 05 02:37:30 PM PDT 24 367247260 ps
T894 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2488031149 May 05 02:37:31 PM PDT 24 May 05 02:37:34 PM PDT 24 381562924 ps
T895 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2601450434 May 05 02:37:39 PM PDT 24 May 05 02:37:40 PM PDT 24 75551841 ps
T896 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1597811608 May 05 02:37:41 PM PDT 24 May 05 02:37:50 PM PDT 24 2963761103 ps
T118 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2651413221 May 05 02:37:47 PM PDT 24 May 05 02:37:51 PM PDT 24 142931387 ps
T897 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2152287000 May 05 02:37:19 PM PDT 24 May 05 02:38:02 PM PDT 24 11011161970 ps
T898 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2686339337 May 05 02:37:21 PM PDT 24 May 05 02:37:23 PM PDT 24 178223656 ps
T899 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1290518208 May 05 02:37:24 PM PDT 24 May 05 02:37:25 PM PDT 24 128669746 ps
T129 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.501399827 May 05 02:37:55 PM PDT 24 May 05 02:37:57 PM PDT 24 84168482 ps
T900 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.601758652 May 05 02:38:05 PM PDT 24 May 05 02:38:06 PM PDT 24 47730521 ps
T901 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1943359778 May 05 02:37:57 PM PDT 24 May 05 02:38:00 PM PDT 24 60295003 ps
T902 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4188486986 May 05 02:38:03 PM PDT 24 May 05 02:38:08 PM PDT 24 111400467 ps
T903 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1386809415 May 05 02:37:50 PM PDT 24 May 05 02:37:52 PM PDT 24 179488865 ps
T904 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3131536222 May 05 02:37:27 PM PDT 24 May 05 02:37:28 PM PDT 24 15868900 ps
T905 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1654517021 May 05 02:37:23 PM PDT 24 May 05 02:37:25 PM PDT 24 21166456 ps
T906 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1370184254 May 05 02:37:53 PM PDT 24 May 05 02:37:57 PM PDT 24 424795662 ps
T907 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2454314127 May 05 02:37:23 PM PDT 24 May 05 02:37:33 PM PDT 24 1501204039 ps
T908 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3732331382 May 05 02:38:04 PM PDT 24 May 05 02:38:05 PM PDT 24 60169817 ps
T909 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2407989998 May 05 02:37:33 PM PDT 24 May 05 02:37:35 PM PDT 24 57551111 ps
T910 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2809526741 May 05 02:37:21 PM PDT 24 May 05 02:37:23 PM PDT 24 31223740 ps
T911 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2924608721 May 05 02:37:27 PM PDT 24 May 05 02:37:37 PM PDT 24 3202991733 ps
T912 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.4071082275 May 05 02:37:21 PM PDT 24 May 05 02:37:22 PM PDT 24 20576422 ps
T913 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3696351126 May 05 02:37:47 PM PDT 24 May 05 02:37:48 PM PDT 24 14400791 ps
T914 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4152746476 May 05 02:37:26 PM PDT 24 May 05 02:37:28 PM PDT 24 22742594 ps
T915 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2123200315 May 05 02:37:38 PM PDT 24 May 05 02:37:41 PM PDT 24 234377960 ps
T916 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4187990628 May 05 02:37:32 PM PDT 24 May 05 02:37:42 PM PDT 24 939439878 ps
T917 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.299772958 May 05 02:37:48 PM PDT 24 May 05 02:38:00 PM PDT 24 1351305668 ps
T918 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3018355070 May 05 02:38:01 PM PDT 24 May 05 02:38:03 PM PDT 24 49842994 ps
T919 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4280796935 May 05 02:37:53 PM PDT 24 May 05 02:37:55 PM PDT 24 39412543 ps
T130 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1482251305 May 05 02:37:43 PM PDT 24 May 05 02:37:45 PM PDT 24 41999848 ps
T920 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.4026779611 May 05 02:37:33 PM PDT 24 May 05 02:37:35 PM PDT 24 68905475 ps
T921 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1826229633 May 05 02:37:40 PM PDT 24 May 05 02:37:42 PM PDT 24 15900882 ps
T922 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3136611297 May 05 02:37:34 PM PDT 24 May 05 02:37:35 PM PDT 24 53867647 ps
T923 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2488608305 May 05 02:37:38 PM PDT 24 May 05 02:37:47 PM PDT 24 1752052111 ps
T924 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2813174232 May 05 02:38:05 PM PDT 24 May 05 02:38:07 PM PDT 24 30145195 ps
T925 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1771377791 May 05 02:37:23 PM PDT 24 May 05 02:37:25 PM PDT 24 30953901 ps
T926 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2538541613 May 05 02:37:51 PM PDT 24 May 05 02:37:59 PM PDT 24 2804166221 ps
T927 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3036426861 May 05 02:38:01 PM PDT 24 May 05 02:38:02 PM PDT 24 53996976 ps
T928 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.657876618 May 05 02:37:47 PM PDT 24 May 05 02:37:49 PM PDT 24 179618964 ps
T929 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1397983066 May 05 02:37:33 PM PDT 24 May 05 02:37:37 PM PDT 24 94291398 ps
T930 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1078044463 May 05 02:37:42 PM PDT 24 May 05 02:37:44 PM PDT 24 30735714 ps
T931 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.678742554 May 05 02:37:34 PM PDT 24 May 05 02:37:37 PM PDT 24 233408284 ps
T932 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.4283285228 May 05 02:38:00 PM PDT 24 May 05 02:38:02 PM PDT 24 67325800 ps
T128 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1342133385 May 05 02:37:33 PM PDT 24 May 05 02:37:35 PM PDT 24 43998208 ps
T933 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.4139618926 May 05 02:37:20 PM PDT 24 May 05 02:37:25 PM PDT 24 270892957 ps
T934 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.4012993569 May 05 02:37:38 PM PDT 24 May 05 02:37:41 PM PDT 24 132385687 ps
T935 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1920828748 May 05 02:37:31 PM PDT 24 May 05 02:37:35 PM PDT 24 67570132 ps
T936 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3558630552 May 05 02:37:50 PM PDT 24 May 05 02:37:53 PM PDT 24 212628529 ps
T937 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2314033836 May 05 02:38:00 PM PDT 24 May 05 02:38:02 PM PDT 24 135473380 ps
T938 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.702361591 May 05 02:37:27 PM PDT 24 May 05 02:37:29 PM PDT 24 18912625 ps
T939 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2093210011 May 05 02:37:21 PM PDT 24 May 05 02:37:23 PM PDT 24 145730169 ps
T171 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1777277068 May 05 02:37:29 PM PDT 24 May 05 02:37:31 PM PDT 24 33674562 ps
T940 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1021186490 May 05 02:37:58 PM PDT 24 May 05 02:38:01 PM PDT 24 37402800 ps
T941 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3210421240 May 05 02:37:35 PM PDT 24 May 05 02:37:37 PM PDT 24 152433892 ps
T942 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2405878613 May 05 02:37:20 PM PDT 24 May 05 02:37:22 PM PDT 24 21513854 ps
T120 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.521554736 May 05 02:37:32 PM PDT 24 May 05 02:37:36 PM PDT 24 118963843 ps
T943 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2898524840 May 05 02:37:35 PM PDT 24 May 05 02:37:36 PM PDT 24 15835358 ps
T944 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.683060100 May 05 02:37:42 PM PDT 24 May 05 02:37:44 PM PDT 24 14952329 ps
T945 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.44709871 May 05 02:38:05 PM PDT 24 May 05 02:38:07 PM PDT 24 62109342 ps
T946 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1663305808 May 05 02:37:50 PM PDT 24 May 05 02:37:53 PM PDT 24 371959360 ps
T947 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.995841093 May 05 02:37:35 PM PDT 24 May 05 02:37:38 PM PDT 24 141587989 ps
T948 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3404260327 May 05 02:37:37 PM PDT 24 May 05 02:37:39 PM PDT 24 27171739 ps
T133 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2518027540 May 05 02:37:54 PM PDT 24 May 05 02:37:57 PM PDT 24 64117062 ps
T949 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3727926550 May 05 02:38:05 PM PDT 24 May 05 02:38:07 PM PDT 24 23856783 ps
T950 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1491914018 May 05 02:37:19 PM PDT 24 May 05 02:37:21 PM PDT 24 45326047 ps
T951 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1475897330 May 05 02:37:17 PM PDT 24 May 05 02:37:20 PM PDT 24 440835664 ps
T127 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.250713306 May 05 02:37:57 PM PDT 24 May 05 02:38:00 PM PDT 24 293948325 ps
T952 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3883761169 May 05 02:37:22 PM PDT 24 May 05 02:38:14 PM PDT 24 5078163054 ps
T172 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4048402710 May 05 02:37:17 PM PDT 24 May 05 02:37:18 PM PDT 24 18450520 ps
T953 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1180492320 May 05 02:37:37 PM PDT 24 May 05 02:37:39 PM PDT 24 143855803 ps
T173 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.249737021 May 05 02:37:32 PM PDT 24 May 05 02:37:34 PM PDT 24 142758125 ps
T954 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1423917795 May 05 02:37:38 PM PDT 24 May 05 02:37:41 PM PDT 24 144401512 ps
T955 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.59029344 May 05 02:37:47 PM PDT 24 May 05 02:37:49 PM PDT 24 547782820 ps
T956 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3875427357 May 05 02:37:32 PM PDT 24 May 05 02:37:34 PM PDT 24 712102610 ps
T125 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2489098408 May 05 02:37:52 PM PDT 24 May 05 02:37:55 PM PDT 24 118817202 ps
T957 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.623751377 May 05 02:38:02 PM PDT 24 May 05 02:38:05 PM PDT 24 112666397 ps
T958 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4167091279 May 05 02:37:48 PM PDT 24 May 05 02:37:50 PM PDT 24 88210766 ps
T959 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1855722092 May 05 02:38:05 PM PDT 24 May 05 02:38:07 PM PDT 24 19798209 ps
T960 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1793674311 May 05 02:38:01 PM PDT 24 May 05 02:38:03 PM PDT 24 43141261 ps
T961 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1411485988 May 05 02:37:47 PM PDT 24 May 05 02:37:51 PM PDT 24 1202802928 ps
T174 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4211148695 May 05 02:38:05 PM PDT 24 May 05 02:38:07 PM PDT 24 55832000 ps
T175 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3682492312 May 05 02:37:52 PM PDT 24 May 05 02:37:53 PM PDT 24 140696315 ps
T962 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2048931157 May 05 02:37:51 PM PDT 24 May 05 02:37:52 PM PDT 24 42974310 ps
T963 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2282266997 May 05 02:37:38 PM PDT 24 May 05 02:37:39 PM PDT 24 257844555 ps
T176 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2222983285 May 05 02:37:21 PM PDT 24 May 05 02:37:23 PM PDT 24 114313318 ps
T964 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1294878486 May 05 02:37:23 PM PDT 24 May 05 02:37:27 PM PDT 24 446463628 ps
T965 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2324066781 May 05 02:37:38 PM PDT 24 May 05 02:37:41 PM PDT 24 176567776 ps
T966 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1387123053 May 05 02:37:55 PM PDT 24 May 05 02:37:57 PM PDT 24 57272947 ps
T177 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2107306856 May 05 02:37:28 PM PDT 24 May 05 02:37:30 PM PDT 24 13336703 ps
T967 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2359057957 May 05 02:37:48 PM PDT 24 May 05 02:37:51 PM PDT 24 78640405 ps
T968 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2619077837 May 05 02:37:39 PM PDT 24 May 05 02:38:25 PM PDT 24 4579117094 ps
T178 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3241974377 May 05 02:37:33 PM PDT 24 May 05 02:37:35 PM PDT 24 15216900 ps
T969 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1442508451 May 05 02:37:20 PM PDT 24 May 05 02:37:23 PM PDT 24 278441847 ps
T970 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.493773613 May 05 02:37:28 PM PDT 24 May 05 02:37:30 PM PDT 24 23639392 ps
T971 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2376317684 May 05 02:37:47 PM PDT 24 May 05 02:37:54 PM PDT 24 2345531403 ps
T121 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.400383874 May 05 02:37:38 PM PDT 24 May 05 02:37:44 PM PDT 24 190055264 ps
T972 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2957439321 May 05 02:38:05 PM PDT 24 May 05 02:38:07 PM PDT 24 48755391 ps
T119 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2987184192 May 05 02:38:10 PM PDT 24 May 05 02:38:13 PM PDT 24 305713018 ps
T973 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2367561334 May 05 02:37:46 PM PDT 24 May 05 02:37:50 PM PDT 24 166717681 ps
T974 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.714476807 May 05 02:38:02 PM PDT 24 May 05 02:38:07 PM PDT 24 102184221 ps
T179 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3246470375 May 05 02:38:09 PM PDT 24 May 05 02:38:11 PM PDT 24 17689930 ps
T132 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1309678430 May 05 02:37:27 PM PDT 24 May 05 02:37:31 PM PDT 24 1918419447 ps
T975 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.617275298 May 05 02:37:50 PM PDT 24 May 05 02:37:53 PM PDT 24 24412228 ps
T976 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2817517451 May 05 02:37:50 PM PDT 24 May 05 02:37:55 PM PDT 24 49470925 ps
T977 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.4142795496 May 05 02:37:48 PM PDT 24 May 05 02:37:51 PM PDT 24 44220154 ps
T978 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.156118072 May 05 02:37:29 PM PDT 24 May 05 02:37:32 PM PDT 24 682749536 ps
T979 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3655407921 May 05 02:37:41 PM PDT 24 May 05 02:37:43 PM PDT 24 39456310 ps
T980 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.4243447547 May 05 02:37:52 PM PDT 24 May 05 02:37:53 PM PDT 24 57299029 ps
T981 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.193190001 May 05 02:37:18 PM PDT 24 May 05 02:37:20 PM PDT 24 203444472 ps
T982 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3343568261 May 05 02:37:49 PM PDT 24 May 05 02:37:51 PM PDT 24 89283467 ps
T983 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2642425314 May 05 02:37:58 PM PDT 24 May 05 02:38:02 PM PDT 24 32425030 ps
T984 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2382093305 May 05 02:37:37 PM PDT 24 May 05 02:37:39 PM PDT 24 74824150 ps
T985 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3218992222 May 05 02:37:51 PM PDT 24 May 05 02:37:56 PM PDT 24 1501666392 ps
T986 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2745686666 May 05 02:37:52 PM PDT 24 May 05 02:37:53 PM PDT 24 34111320 ps
T180 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2695314243 May 05 02:37:23 PM PDT 24 May 05 02:37:24 PM PDT 24 245941903 ps
T987 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2311408377 May 05 02:38:02 PM PDT 24 May 05 02:38:04 PM PDT 24 14422931 ps
T988 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3100964953 May 05 02:37:53 PM PDT 24 May 05 02:37:55 PM PDT 24 41140509 ps
T989 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2883652481 May 05 02:37:53 PM PDT 24 May 05 02:37:56 PM PDT 24 114587593 ps
T990 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1636288495 May 05 02:38:02 PM PDT 24 May 05 02:38:06 PM PDT 24 40230866 ps
T991 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4150495055 May 05 02:37:40 PM PDT 24 May 05 02:37:42 PM PDT 24 143719679 ps
T992 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3920889081 May 05 02:38:09 PM PDT 24 May 05 02:38:11 PM PDT 24 54089900 ps
T134 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2073147685 May 05 02:38:01 PM PDT 24 May 05 02:38:04 PM PDT 24 128727499 ps
T993 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2311758860 May 05 02:38:02 PM PDT 24 May 05 02:38:06 PM PDT 24 122749427 ps
T994 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3338639418 May 05 02:38:01 PM PDT 24 May 05 02:38:03 PM PDT 24 21080384 ps
T995 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1687786565 May 05 02:37:50 PM PDT 24 May 05 02:37:52 PM PDT 24 80020915 ps
T996 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2233543687 May 05 02:37:30 PM PDT 24 May 05 02:37:32 PM PDT 24 166513681 ps
T997 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.4101760285 May 05 02:38:04 PM PDT 24 May 05 02:38:06 PM PDT 24 31347230 ps
T998 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2276500833 May 05 02:37:28 PM PDT 24 May 05 02:37:30 PM PDT 24 53221156 ps
T999 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.825576854 May 05 02:37:22 PM PDT 24 May 05 02:37:25 PM PDT 24 360452689 ps
T181 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.658795927 May 05 02:38:02 PM PDT 24 May 05 02:38:04 PM PDT 24 47618255 ps
T1000 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2074030251 May 05 02:37:33 PM PDT 24 May 05 02:37:35 PM PDT 24 101074530 ps

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1935927329
Short name T16
Test name
Test status
Simulation time 1190929312 ps
CPU time 9.77 seconds
Started May 05 01:47:10 PM PDT 24
Finished May 05 01:47:20 PM PDT 24
Peak memory 218208 kb
Host smart-3bd35d4a-b267-443d-9627-6cb86049c85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935927329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1935927329
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2603702517
Short name T7
Test name
Test status
Simulation time 63663191890 ps
CPU time 376.9 seconds
Started May 05 01:45:58 PM PDT 24
Finished May 05 01:52:16 PM PDT 24
Peak memory 261964 kb
Host smart-44d229e4-4ca7-4f32-9607-95dfa7d5fe19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2603702517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.2603702517
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.392167441
Short name T2
Test name
Test status
Simulation time 939061442 ps
CPU time 17 seconds
Started May 05 01:46:16 PM PDT 24
Finished May 05 01:46:33 PM PDT 24
Peak memory 218424 kb
Host smart-d8d8acec-cdd9-42f8-b6c5-32604073eb4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392167441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.392167441
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.291115422
Short name T43
Test name
Test status
Simulation time 1480180208 ps
CPU time 9.74 seconds
Started May 05 01:46:03 PM PDT 24
Finished May 05 01:46:14 PM PDT 24
Peak memory 218144 kb
Host smart-8edef0c5-8181-4a45-bf19-0c4cf47edade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291115422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.291115422
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.743718055
Short name T103
Test name
Test status
Simulation time 1290551052 ps
CPU time 2.74 seconds
Started May 05 02:37:18 PM PDT 24
Finished May 05 02:37:21 PM PDT 24
Peak memory 222312 kb
Host smart-2ebf7b45-97cb-455a-a846-6c4a6fd85cd4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743718055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.743718055
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.540040578
Short name T55
Test name
Test status
Simulation time 1136779761 ps
CPU time 37.02 seconds
Started May 05 01:45:24 PM PDT 24
Finished May 05 01:46:02 PM PDT 24
Peak memory 270756 kb
Host smart-3d219878-7f92-4b6c-a9b1-dd81d7bbde51
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540040578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.540040578
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.1553615047
Short name T26
Test name
Test status
Simulation time 22921091377 ps
CPU time 897.4 seconds
Started May 05 01:46:53 PM PDT 24
Finished May 05 02:01:51 PM PDT 24
Peak memory 497028 kb
Host smart-0e4dd45b-0e44-455f-bcbb-985d592feac9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1553615047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.1553615047
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.182871194
Short name T10
Test name
Test status
Simulation time 372315107 ps
CPU time 5.01 seconds
Started May 05 01:46:05 PM PDT 24
Finished May 05 01:46:11 PM PDT 24
Peak memory 217252 kb
Host smart-121b340a-4fbf-4748-8dcc-b5dea0b6c7b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182871194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.182871194
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2129770676
Short name T98
Test name
Test status
Simulation time 22123028264 ps
CPU time 403.92 seconds
Started May 05 01:46:05 PM PDT 24
Finished May 05 01:52:49 PM PDT 24
Peak memory 333076 kb
Host smart-80135a34-1001-4bc9-98f7-9932fa91a67c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129770676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2129770676
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4221445438
Short name T876
Test name
Test status
Simulation time 512437627 ps
CPU time 2.04 seconds
Started May 05 02:37:32 PM PDT 24
Finished May 05 02:37:34 PM PDT 24
Peak memory 218724 kb
Host smart-afc5500b-9fcc-468e-b0f4-f3dad2fc72c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422144
5438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4221445438
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1807070413
Short name T4
Test name
Test status
Simulation time 197839201 ps
CPU time 7.82 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:45:52 PM PDT 24
Peak memory 218120 kb
Host smart-4381e0dc-a59c-4818-a8ba-2fc3a4048dc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807070413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
807070413
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3527321033
Short name T1
Test name
Test status
Simulation time 22476957 ps
CPU time 0.98 seconds
Started May 05 01:46:56 PM PDT 24
Finished May 05 01:46:58 PM PDT 24
Peak memory 209672 kb
Host smart-f6511405-4727-47d4-9296-542fbbe52919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527321033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3527321033
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.3511839442
Short name T142
Test name
Test status
Simulation time 24563869 ps
CPU time 0.88 seconds
Started May 05 02:37:27 PM PDT 24
Finished May 05 02:37:28 PM PDT 24
Peak memory 209420 kb
Host smart-6823a767-1169-4ddc-a628-835a43f46e02
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511839442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.3511839442
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1621178819
Short name T123
Test name
Test status
Simulation time 615487829 ps
CPU time 5.1 seconds
Started May 05 02:37:27 PM PDT 24
Finished May 05 02:37:33 PM PDT 24
Peak memory 217620 kb
Host smart-2790c1f9-025b-4c2d-9da5-9bfa33cf8bd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621178819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1621178819
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2488031149
Short name T894
Test name
Test status
Simulation time 381562924 ps
CPU time 2.07 seconds
Started May 05 02:37:31 PM PDT 24
Finished May 05 02:37:34 PM PDT 24
Peak memory 218576 kb
Host smart-6aacb736-7499-46b0-a6af-e7ed535d2626
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488031149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2488031149
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.1094746083
Short name T5
Test name
Test status
Simulation time 415583909 ps
CPU time 5.81 seconds
Started May 05 01:45:23 PM PDT 24
Finished May 05 01:45:29 PM PDT 24
Peak memory 218148 kb
Host smart-c267338a-6198-4324-8370-c544b01f9208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094746083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.1094746083
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.250713306
Short name T127
Test name
Test status
Simulation time 293948325 ps
CPU time 2.76 seconds
Started May 05 02:37:57 PM PDT 24
Finished May 05 02:38:00 PM PDT 24
Peak memory 222332 kb
Host smart-6b78a092-8ac2-4e95-a0eb-2e3426423be4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250713306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.250713306
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1075556393
Short name T104
Test name
Test status
Simulation time 443590211 ps
CPU time 3.08 seconds
Started May 05 02:38:04 PM PDT 24
Finished May 05 02:38:08 PM PDT 24
Peak memory 222028 kb
Host smart-4663ff80-af27-459d-bf08-7eab4c6be58b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075556393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1075556393
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2431798754
Short name T100
Test name
Test status
Simulation time 259830501 ps
CPU time 25.93 seconds
Started May 05 01:46:47 PM PDT 24
Finished May 05 01:47:13 PM PDT 24
Peak memory 250680 kb
Host smart-8c635d11-80a0-4b63-891b-820d4ba053a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431798754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2431798754
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.521554736
Short name T120
Test name
Test status
Simulation time 118963843 ps
CPU time 4.08 seconds
Started May 05 02:37:32 PM PDT 24
Finished May 05 02:37:36 PM PDT 24
Peak memory 217704 kb
Host smart-6c510c62-e015-4368-abf5-cf72462e6e88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521554736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e
rr.521554736
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2222983285
Short name T176
Test name
Test status
Simulation time 114313318 ps
CPU time 1.2 seconds
Started May 05 02:37:21 PM PDT 24
Finished May 05 02:37:23 PM PDT 24
Peak memory 209464 kb
Host smart-42f1bfd9-877e-493a-ad3b-df66858a2f06
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222983285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2222983285
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2636793218
Short name T13
Test name
Test status
Simulation time 138738888 ps
CPU time 1 seconds
Started May 05 01:46:45 PM PDT 24
Finished May 05 01:46:47 PM PDT 24
Peak memory 211792 kb
Host smart-04ee0bd5-ee33-43e2-a65c-34f997f290e6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636793218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2636793218
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.501399827
Short name T129
Test name
Test status
Simulation time 84168482 ps
CPU time 1.85 seconds
Started May 05 02:37:55 PM PDT 24
Finished May 05 02:37:57 PM PDT 24
Peak memory 221972 kb
Host smart-9075bc3d-0128-410f-bea2-3052f67a4f86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501399827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.501399827
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2651413221
Short name T118
Test name
Test status
Simulation time 142931387 ps
CPU time 3.41 seconds
Started May 05 02:37:47 PM PDT 24
Finished May 05 02:37:51 PM PDT 24
Peak memory 217624 kb
Host smart-abc70891-45dd-43ea-a35d-e8640f910669
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651413221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2651413221
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1221023472
Short name T194
Test name
Test status
Simulation time 13084416 ps
CPU time 0.81 seconds
Started May 05 01:45:28 PM PDT 24
Finished May 05 01:45:29 PM PDT 24
Peak memory 209524 kb
Host smart-691ae7e3-5bcb-4133-88ea-67ae9d9d2009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221023472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1221023472
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.850595671
Short name T76
Test name
Test status
Simulation time 30132676 ps
CPU time 0.88 seconds
Started May 05 01:45:24 PM PDT 24
Finished May 05 01:45:26 PM PDT 24
Peak memory 209604 kb
Host smart-9016a30d-f66a-4cf9-98f3-ade647a391f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850595671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.850595671
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.75194563
Short name T198
Test name
Test status
Simulation time 12699138 ps
CPU time 0.86 seconds
Started May 05 01:45:28 PM PDT 24
Finished May 05 01:45:30 PM PDT 24
Peak memory 209556 kb
Host smart-fa18f077-4150-4264-b2da-62c573a06eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75194563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.75194563
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3264738121
Short name T195
Test name
Test status
Simulation time 13330976 ps
CPU time 0.83 seconds
Started May 05 01:45:30 PM PDT 24
Finished May 05 01:45:32 PM PDT 24
Peak memory 209572 kb
Host smart-416d50c2-13b8-47e5-8296-33ca3dcf6b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264738121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3264738121
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1475897330
Short name T951
Test name
Test status
Simulation time 440835664 ps
CPU time 3.42 seconds
Started May 05 02:37:17 PM PDT 24
Finished May 05 02:37:20 PM PDT 24
Peak memory 208540 kb
Host smart-adf8c4e7-14fe-43ec-b40e-e19b27ca88c6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475897330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1475897330
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2987184192
Short name T119
Test name
Test status
Simulation time 305713018 ps
CPU time 2.8 seconds
Started May 05 02:38:10 PM PDT 24
Finished May 05 02:38:13 PM PDT 24
Peak memory 222360 kb
Host smart-6c7c6668-b097-42c9-93c5-aab225924d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987184192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2987184192
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1342133385
Short name T128
Test name
Test status
Simulation time 43998208 ps
CPU time 1.96 seconds
Started May 05 02:37:33 PM PDT 24
Finished May 05 02:37:35 PM PDT 24
Peak memory 221916 kb
Host smart-644ab926-9e59-4323-ba22-a664a3959143
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342133385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1342133385
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.400383874
Short name T121
Test name
Test status
Simulation time 190055264 ps
CPU time 5.2 seconds
Started May 05 02:37:38 PM PDT 24
Finished May 05 02:37:44 PM PDT 24
Peak memory 217592 kb
Host smart-5f9556fa-925f-4182-8497-efffb336df9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400383874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.400383874
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.601644874
Short name T114
Test name
Test status
Simulation time 414157736 ps
CPU time 4.2 seconds
Started May 05 02:37:54 PM PDT 24
Finished May 05 02:37:59 PM PDT 24
Peak memory 217596 kb
Host smart-813bbba5-bdba-4d64-9bc6-3a308239240e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601644874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.601644874
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.162993632
Short name T8
Test name
Test status
Simulation time 2476024480 ps
CPU time 40.49 seconds
Started May 05 01:45:48 PM PDT 24
Finished May 05 01:46:29 PM PDT 24
Peak memory 219116 kb
Host smart-0dbc69fc-7d83-45aa-b064-aa4499c636c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162993632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_er
rors.162993632
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1756388221
Short name T889
Test name
Test status
Simulation time 37673740 ps
CPU time 1.8 seconds
Started May 05 02:37:20 PM PDT 24
Finished May 05 02:37:23 PM PDT 24
Peak memory 209260 kb
Host smart-9a6fc7ac-6559-4c2e-ba29-33e4cd9ec743
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756388221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1756388221
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4048402710
Short name T172
Test name
Test status
Simulation time 18450520 ps
CPU time 1.02 seconds
Started May 05 02:37:17 PM PDT 24
Finished May 05 02:37:18 PM PDT 24
Peak memory 210360 kb
Host smart-49031e4e-7735-44c4-a8fe-b59f9e5f8ed5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048402710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.4048402710
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2809526741
Short name T910
Test name
Test status
Simulation time 31223740 ps
CPU time 1.31 seconds
Started May 05 02:37:21 PM PDT 24
Finished May 05 02:37:23 PM PDT 24
Peak memory 219132 kb
Host smart-a6de804d-8240-40b2-a0d7-85f1805cf2c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809526741 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2809526741
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1491914018
Short name T950
Test name
Test status
Simulation time 45326047 ps
CPU time 0.99 seconds
Started May 05 02:37:19 PM PDT 24
Finished May 05 02:37:21 PM PDT 24
Peak memory 209368 kb
Host smart-af7c0dff-77e7-43aa-a7e0-e6e3b7f841f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491914018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.1491914018
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2822974843
Short name T877
Test name
Test status
Simulation time 54893370 ps
CPU time 2.06 seconds
Started May 05 02:37:20 PM PDT 24
Finished May 05 02:37:22 PM PDT 24
Peak memory 209260 kb
Host smart-4684db8a-3694-430f-bb54-648fe3cf55e4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822974843 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2822974843
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3452868955
Short name T117
Test name
Test status
Simulation time 5521143793 ps
CPU time 36.84 seconds
Started May 05 02:37:17 PM PDT 24
Finished May 05 02:37:54 PM PDT 24
Peak memory 209384 kb
Host smart-1b554bfe-3c67-490c-a665-1ca153a5fbb4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452868955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.3452868955
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.4139618926
Short name T933
Test name
Test status
Simulation time 270892957 ps
CPU time 3.86 seconds
Started May 05 02:37:20 PM PDT 24
Finished May 05 02:37:25 PM PDT 24
Peak memory 210796 kb
Host smart-42180fb8-120a-45d2-9e1d-a949ff0f53a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139618926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.4139618926
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2093210011
Short name T939
Test name
Test status
Simulation time 145730169 ps
CPU time 2.43 seconds
Started May 05 02:37:21 PM PDT 24
Finished May 05 02:37:23 PM PDT 24
Peak memory 217896 kb
Host smart-8dfc8776-6ab7-44aa-a602-aa2ba25e638a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209321
0011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2093210011
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.193190001
Short name T981
Test name
Test status
Simulation time 203444472 ps
CPU time 1.79 seconds
Started May 05 02:37:18 PM PDT 24
Finished May 05 02:37:20 PM PDT 24
Peak memory 209308 kb
Host smart-f7289eaa-6899-45fd-b668-3b59b3e7bfda
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193190001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.193190001
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3874853132
Short name T185
Test name
Test status
Simulation time 36465105 ps
CPU time 1.29 seconds
Started May 05 02:37:16 PM PDT 24
Finished May 05 02:37:18 PM PDT 24
Peak memory 209468 kb
Host smart-fb2ca3eb-2f33-4a1a-be77-a2f6191282c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874853132 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3874853132
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1414067166
Short name T182
Test name
Test status
Simulation time 22109280 ps
CPU time 0.99 seconds
Started May 05 02:37:17 PM PDT 24
Finished May 05 02:37:19 PM PDT 24
Peak memory 209384 kb
Host smart-d6c29769-6ea3-4360-ba50-a122654b38d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414067166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1414067166
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3971677124
Short name T112
Test name
Test status
Simulation time 235055785 ps
CPU time 4.67 seconds
Started May 05 02:37:21 PM PDT 24
Finished May 05 02:37:26 PM PDT 24
Peak memory 217660 kb
Host smart-fad95a85-48de-4aac-9cc2-ff8d959a6778
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971677124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3971677124
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2695314243
Short name T180
Test name
Test status
Simulation time 245941903 ps
CPU time 1.11 seconds
Started May 05 02:37:23 PM PDT 24
Finished May 05 02:37:24 PM PDT 24
Peak memory 209380 kb
Host smart-8a3b631c-e883-4ddf-8c4a-0129b2589223
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695314243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.2695314243
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1654517021
Short name T905
Test name
Test status
Simulation time 21166456 ps
CPU time 1.2 seconds
Started May 05 02:37:23 PM PDT 24
Finished May 05 02:37:25 PM PDT 24
Peak memory 209368 kb
Host smart-56439ae3-acb7-4cda-a0fb-4ca41b1f27e5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654517021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1654517021
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.493773613
Short name T970
Test name
Test status
Simulation time 23639392 ps
CPU time 1.11 seconds
Started May 05 02:37:28 PM PDT 24
Finished May 05 02:37:30 PM PDT 24
Peak memory 209988 kb
Host smart-986cf755-f15f-447f-8df6-969c7e84ea68
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493773613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.493773613
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1771377791
Short name T925
Test name
Test status
Simulation time 30953901 ps
CPU time 1.64 seconds
Started May 05 02:37:23 PM PDT 24
Finished May 05 02:37:25 PM PDT 24
Peak memory 218400 kb
Host smart-6fcf2156-04f2-49a1-8b69-045e226730b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771377791 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1771377791
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1290518208
Short name T899
Test name
Test status
Simulation time 128669746 ps
CPU time 1.06 seconds
Started May 05 02:37:24 PM PDT 24
Finished May 05 02:37:25 PM PDT 24
Peak memory 209288 kb
Host smart-2ebc795a-965e-413a-8af1-ebb0f439fd64
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290518208 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1290518208
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2454314127
Short name T907
Test name
Test status
Simulation time 1501204039 ps
CPU time 10.22 seconds
Started May 05 02:37:23 PM PDT 24
Finished May 05 02:37:33 PM PDT 24
Peak memory 209116 kb
Host smart-f00aea14-330a-40a4-874d-67b23b6de2ef
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454314127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2454314127
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2152287000
Short name T897
Test name
Test status
Simulation time 11011161970 ps
CPU time 42.75 seconds
Started May 05 02:37:19 PM PDT 24
Finished May 05 02:38:02 PM PDT 24
Peak memory 209308 kb
Host smart-1dbc6f15-e685-4eb1-b1d7-68ff18b8f94f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152287000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2152287000
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1442508451
Short name T969
Test name
Test status
Simulation time 278441847 ps
CPU time 2.42 seconds
Started May 05 02:37:20 PM PDT 24
Finished May 05 02:37:23 PM PDT 24
Peak memory 210848 kb
Host smart-514b4304-052d-48bc-894c-9efdb2213c95
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442508451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1442508451
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2448309113
Short name T157
Test name
Test status
Simulation time 781549491 ps
CPU time 2.84 seconds
Started May 05 02:37:22 PM PDT 24
Finished May 05 02:37:25 PM PDT 24
Peak memory 222176 kb
Host smart-5aa47cac-a6f3-47ee-9d90-ce12503c9af8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244830
9113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2448309113
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2686339337
Short name T898
Test name
Test status
Simulation time 178223656 ps
CPU time 1.43 seconds
Started May 05 02:37:21 PM PDT 24
Finished May 05 02:37:23 PM PDT 24
Peak memory 209300 kb
Host smart-ef7fa4dd-550b-4dbf-bebd-e22d5c1a0fe4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686339337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2686339337
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.825576854
Short name T999
Test name
Test status
Simulation time 360452689 ps
CPU time 1.8 seconds
Started May 05 02:37:22 PM PDT 24
Finished May 05 02:37:25 PM PDT 24
Peak memory 209392 kb
Host smart-fb2ae7c9-4bdc-4dd5-8d81-629a8eab2a32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825576854 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.825576854
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3829139350
Short name T143
Test name
Test status
Simulation time 25090206 ps
CPU time 1.03 seconds
Started May 05 02:37:22 PM PDT 24
Finished May 05 02:37:24 PM PDT 24
Peak memory 209368 kb
Host smart-0446d8dd-f12d-49c8-931d-0c93fde5d6aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829139350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3829139350
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2276500833
Short name T998
Test name
Test status
Simulation time 53221156 ps
CPU time 1.79 seconds
Started May 05 02:37:28 PM PDT 24
Finished May 05 02:37:30 PM PDT 24
Peak memory 217684 kb
Host smart-f095d985-7e94-4b75-b339-470511bf7d19
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276500833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2276500833
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3661498790
Short name T124
Test name
Test status
Simulation time 274696335 ps
CPU time 1.38 seconds
Started May 05 02:37:55 PM PDT 24
Finished May 05 02:37:57 PM PDT 24
Peak memory 217660 kb
Host smart-eb028248-992d-44e3-90b5-b6206eafd634
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661498790 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3661498790
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3682492312
Short name T175
Test name
Test status
Simulation time 140696315 ps
CPU time 0.92 seconds
Started May 05 02:37:52 PM PDT 24
Finished May 05 02:37:53 PM PDT 24
Peak memory 209368 kb
Host smart-b5b7fd54-c74b-44ce-890b-eea6baa16229
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682492312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.3682492312
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.617275298
Short name T975
Test name
Test status
Simulation time 24412228 ps
CPU time 1.37 seconds
Started May 05 02:37:50 PM PDT 24
Finished May 05 02:37:53 PM PDT 24
Peak memory 209040 kb
Host smart-c350798c-415c-41d2-8b35-ee3ea7cfb7dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617275298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.617275298
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2817517451
Short name T976
Test name
Test status
Simulation time 49470925 ps
CPU time 3.38 seconds
Started May 05 02:37:50 PM PDT 24
Finished May 05 02:37:55 PM PDT 24
Peak memory 218268 kb
Host smart-6c49a445-eeb4-459a-88c6-f55557db72ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817517451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2817517451
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2489098408
Short name T125
Test name
Test status
Simulation time 118817202 ps
CPU time 2.94 seconds
Started May 05 02:37:52 PM PDT 24
Finished May 05 02:37:55 PM PDT 24
Peak memory 217612 kb
Host smart-ef970355-5c5c-46f1-ba98-3988aece489e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489098408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2489098408
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1021186490
Short name T940
Test name
Test status
Simulation time 37402800 ps
CPU time 1.63 seconds
Started May 05 02:37:58 PM PDT 24
Finished May 05 02:38:01 PM PDT 24
Peak memory 222872 kb
Host smart-e18b4a1c-62f0-4a78-b1f2-0e9b96011054
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021186490 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1021186490
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2339309164
Short name T892
Test name
Test status
Simulation time 36347229 ps
CPU time 0.8 seconds
Started May 05 02:37:58 PM PDT 24
Finished May 05 02:38:00 PM PDT 24
Peak memory 209340 kb
Host smart-cd726f41-2792-40f9-9998-5a13d27554c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339309164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2339309164
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.623751377
Short name T957
Test name
Test status
Simulation time 112666397 ps
CPU time 1.44 seconds
Started May 05 02:38:02 PM PDT 24
Finished May 05 02:38:05 PM PDT 24
Peak memory 209312 kb
Host smart-447c7692-0145-4e07-911f-55b512474d90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623751377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.623751377
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2642425314
Short name T983
Test name
Test status
Simulation time 32425030 ps
CPU time 1.94 seconds
Started May 05 02:37:58 PM PDT 24
Finished May 05 02:38:02 PM PDT 24
Peak memory 218696 kb
Host smart-a9e57df2-cb1a-4ce7-b8e5-0abffa8a7060
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642425314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2642425314
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2518027540
Short name T133
Test name
Test status
Simulation time 64117062 ps
CPU time 2.57 seconds
Started May 05 02:37:54 PM PDT 24
Finished May 05 02:37:57 PM PDT 24
Peak memory 217636 kb
Host smart-af23a34d-7028-4135-9a71-421d2b4502cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518027540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2518027540
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3727926550
Short name T949
Test name
Test status
Simulation time 23856783 ps
CPU time 1.23 seconds
Started May 05 02:38:05 PM PDT 24
Finished May 05 02:38:07 PM PDT 24
Peak memory 218728 kb
Host smart-adb1ed91-684d-460c-bf04-dd7508416028
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727926550 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3727926550
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3338639418
Short name T994
Test name
Test status
Simulation time 21080384 ps
CPU time 0.8 seconds
Started May 05 02:38:01 PM PDT 24
Finished May 05 02:38:03 PM PDT 24
Peak memory 209244 kb
Host smart-13c509a6-f1ee-425e-8ad0-8caf4c058469
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338639418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3338639418
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3085179297
Short name T108
Test name
Test status
Simulation time 37373174 ps
CPU time 1.09 seconds
Started May 05 02:37:56 PM PDT 24
Finished May 05 02:37:57 PM PDT 24
Peak memory 209372 kb
Host smart-8fa48665-b82d-4960-ba50-40dc66289a1a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085179297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3085179297
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4188486986
Short name T902
Test name
Test status
Simulation time 111400467 ps
CPU time 4.13 seconds
Started May 05 02:38:03 PM PDT 24
Finished May 05 02:38:08 PM PDT 24
Peak memory 217572 kb
Host smart-c04198cd-d75a-4856-8aa0-65d0898584a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188486986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.4188486986
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2343677495
Short name T116
Test name
Test status
Simulation time 18251885 ps
CPU time 0.97 seconds
Started May 05 02:37:56 PM PDT 24
Finished May 05 02:37:57 PM PDT 24
Peak memory 217620 kb
Host smart-7bab7b2b-2b06-4317-9602-2d86b87fd0d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343677495 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2343677495
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.658795927
Short name T181
Test name
Test status
Simulation time 47618255 ps
CPU time 0.97 seconds
Started May 05 02:38:02 PM PDT 24
Finished May 05 02:38:04 PM PDT 24
Peak memory 209312 kb
Host smart-ccae7eaa-cd7d-465e-924c-bf8e3aad1205
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658795927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.658795927
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.591683207
Short name T184
Test name
Test status
Simulation time 60665386 ps
CPU time 1.54 seconds
Started May 05 02:38:02 PM PDT 24
Finished May 05 02:38:04 PM PDT 24
Peak memory 211404 kb
Host smart-b419d081-a8cd-4196-8436-2e9156f9d556
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591683207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.591683207
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1943359778
Short name T901
Test name
Test status
Simulation time 60295003 ps
CPU time 2.63 seconds
Started May 05 02:37:57 PM PDT 24
Finished May 05 02:38:00 PM PDT 24
Peak memory 217684 kb
Host smart-0be2fd85-787f-4a4e-9c4f-67701ec0c489
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943359778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1943359778
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2314033836
Short name T937
Test name
Test status
Simulation time 135473380 ps
CPU time 1.23 seconds
Started May 05 02:38:00 PM PDT 24
Finished May 05 02:38:02 PM PDT 24
Peak memory 217628 kb
Host smart-00681c9b-fe55-4c50-917f-72e0e217e7df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314033836 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2314033836
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1793674311
Short name T960
Test name
Test status
Simulation time 43141261 ps
CPU time 0.89 seconds
Started May 05 02:38:01 PM PDT 24
Finished May 05 02:38:03 PM PDT 24
Peak memory 209348 kb
Host smart-10ef3404-0fff-44c3-9122-145b51ed3160
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793674311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1793674311
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.4283285228
Short name T932
Test name
Test status
Simulation time 67325800 ps
CPU time 1.01 seconds
Started May 05 02:38:00 PM PDT 24
Finished May 05 02:38:02 PM PDT 24
Peak memory 209376 kb
Host smart-8ed9671d-92ab-4f08-9848-798591cd6836
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283285228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.4283285228
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.996488488
Short name T107
Test name
Test status
Simulation time 141847788 ps
CPU time 4.94 seconds
Started May 05 02:38:02 PM PDT 24
Finished May 05 02:38:08 PM PDT 24
Peak memory 217572 kb
Host smart-8f695e14-9cfe-4ee8-afea-16c86872ccd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996488488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.996488488
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.4196785349
Short name T106
Test name
Test status
Simulation time 57286177 ps
CPU time 2.13 seconds
Started May 05 02:38:01 PM PDT 24
Finished May 05 02:38:03 PM PDT 24
Peak memory 221824 kb
Host smart-b59807d6-e45a-45b6-a5e4-03a376bc5116
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196785349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.4196785349
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3036426861
Short name T927
Test name
Test status
Simulation time 53996976 ps
CPU time 0.99 seconds
Started May 05 02:38:01 PM PDT 24
Finished May 05 02:38:02 PM PDT 24
Peak memory 217740 kb
Host smart-bea49771-9f21-4126-9dc6-c2049e39f964
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036426861 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3036426861
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2784840795
Short name T878
Test name
Test status
Simulation time 42170126 ps
CPU time 0.86 seconds
Started May 05 02:38:01 PM PDT 24
Finished May 05 02:38:02 PM PDT 24
Peak memory 209304 kb
Host smart-7f75d7ab-6f88-48a7-a3fe-cec8a2e99433
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784840795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2784840795
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2541466042
Short name T109
Test name
Test status
Simulation time 284149806 ps
CPU time 2.01 seconds
Started May 05 02:38:03 PM PDT 24
Finished May 05 02:38:05 PM PDT 24
Peak memory 209392 kb
Host smart-c34e43e8-57a0-4a81-bd0e-25413e473e45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541466042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2541466042
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2311758860
Short name T993
Test name
Test status
Simulation time 122749427 ps
CPU time 3.4 seconds
Started May 05 02:38:02 PM PDT 24
Finished May 05 02:38:06 PM PDT 24
Peak memory 217596 kb
Host smart-026905a1-5139-4350-af2a-48db06922401
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311758860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2311758860
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2073147685
Short name T134
Test name
Test status
Simulation time 128727499 ps
CPU time 2.52 seconds
Started May 05 02:38:01 PM PDT 24
Finished May 05 02:38:04 PM PDT 24
Peak memory 217540 kb
Host smart-171ac6f4-eefb-4766-9367-f7138a9f2b6e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073147685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2073147685
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2289751426
Short name T111
Test name
Test status
Simulation time 37393865 ps
CPU time 1.27 seconds
Started May 05 02:37:59 PM PDT 24
Finished May 05 02:38:01 PM PDT 24
Peak memory 219760 kb
Host smart-6f4b5efe-c6dd-4ccd-ab95-2472e08a2122
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289751426 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2289751426
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2311408377
Short name T987
Test name
Test status
Simulation time 14422931 ps
CPU time 0.92 seconds
Started May 05 02:38:02 PM PDT 24
Finished May 05 02:38:04 PM PDT 24
Peak memory 209384 kb
Host smart-b0b0d4ea-a201-4727-a653-37d1b65ea233
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311408377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2311408377
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3018355070
Short name T918
Test name
Test status
Simulation time 49842994 ps
CPU time 1.19 seconds
Started May 05 02:38:01 PM PDT 24
Finished May 05 02:38:03 PM PDT 24
Peak memory 209360 kb
Host smart-bce8809f-7c71-4ef8-bc91-96a6c42a0ce4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018355070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3018355070
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3339849163
Short name T879
Test name
Test status
Simulation time 140222743 ps
CPU time 5.55 seconds
Started May 05 02:38:02 PM PDT 24
Finished May 05 02:38:08 PM PDT 24
Peak memory 217712 kb
Host smart-6c1aa802-55ba-469a-9760-a29281bd9bea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339849163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3339849163
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.714476807
Short name T974
Test name
Test status
Simulation time 102184221 ps
CPU time 4 seconds
Started May 05 02:38:02 PM PDT 24
Finished May 05 02:38:07 PM PDT 24
Peak memory 217596 kb
Host smart-825b29d0-ca48-48d4-97eb-ae10a25f4b5d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714476807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.714476807
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2813174232
Short name T924
Test name
Test status
Simulation time 30145195 ps
CPU time 1.67 seconds
Started May 05 02:38:05 PM PDT 24
Finished May 05 02:38:07 PM PDT 24
Peak memory 217704 kb
Host smart-9ff373e5-0012-4fce-b409-218127cadcae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813174232 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2813174232
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4211148695
Short name T174
Test name
Test status
Simulation time 55832000 ps
CPU time 1.11 seconds
Started May 05 02:38:05 PM PDT 24
Finished May 05 02:38:07 PM PDT 24
Peak memory 209504 kb
Host smart-ec1c0810-f81e-4190-bc04-0eb5621e188a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211148695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.4211148695
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.44709871
Short name T945
Test name
Test status
Simulation time 62109342 ps
CPU time 1.13 seconds
Started May 05 02:38:05 PM PDT 24
Finished May 05 02:38:07 PM PDT 24
Peak memory 209452 kb
Host smart-ebc988d4-8704-46db-b30d-f68d18a83f99
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44709871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
same_csr_outstanding.44709871
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1636288495
Short name T990
Test name
Test status
Simulation time 40230866 ps
CPU time 2.96 seconds
Started May 05 02:38:02 PM PDT 24
Finished May 05 02:38:06 PM PDT 24
Peak memory 217752 kb
Host smart-5de0b8c1-7d7e-46d4-932f-033381c97a24
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636288495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1636288495
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.2147521305
Short name T126
Test name
Test status
Simulation time 228380576 ps
CPU time 4.09 seconds
Started May 05 02:38:05 PM PDT 24
Finished May 05 02:38:09 PM PDT 24
Peak memory 217648 kb
Host smart-98f50f34-2fb3-46c3-80e5-3a4745764a49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147521305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.2147521305
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3732331382
Short name T908
Test name
Test status
Simulation time 60169817 ps
CPU time 1.17 seconds
Started May 05 02:38:04 PM PDT 24
Finished May 05 02:38:05 PM PDT 24
Peak memory 219332 kb
Host smart-73f30172-bd97-4077-9cf9-693ac13e796d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732331382 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3732331382
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3246470375
Short name T179
Test name
Test status
Simulation time 17689930 ps
CPU time 0.96 seconds
Started May 05 02:38:09 PM PDT 24
Finished May 05 02:38:11 PM PDT 24
Peak memory 209160 kb
Host smart-d1de565c-f3e8-49f8-809d-5a064e636122
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246470375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3246470375
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1855722092
Short name T959
Test name
Test status
Simulation time 19798209 ps
CPU time 1.28 seconds
Started May 05 02:38:05 PM PDT 24
Finished May 05 02:38:07 PM PDT 24
Peak memory 217596 kb
Host smart-19ad6b1b-7ef1-4468-b082-0782ec8b54bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855722092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1855722092
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.4101760285
Short name T997
Test name
Test status
Simulation time 31347230 ps
CPU time 2.45 seconds
Started May 05 02:38:04 PM PDT 24
Finished May 05 02:38:06 PM PDT 24
Peak memory 217760 kb
Host smart-c615d2ef-c52f-40ad-acc1-ef4ab76c804b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101760285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.4101760285
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2957439321
Short name T972
Test name
Test status
Simulation time 48755391 ps
CPU time 1.48 seconds
Started May 05 02:38:05 PM PDT 24
Finished May 05 02:38:07 PM PDT 24
Peak memory 217736 kb
Host smart-243e4e50-ed51-44cc-a440-897385191364
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957439321 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2957439321
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.601758652
Short name T900
Test name
Test status
Simulation time 47730521 ps
CPU time 0.83 seconds
Started May 05 02:38:05 PM PDT 24
Finished May 05 02:38:06 PM PDT 24
Peak memory 209428 kb
Host smart-d68a1a38-a8b7-4548-92f1-390ac4b8ff77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601758652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.601758652
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3920889081
Short name T992
Test name
Test status
Simulation time 54089900 ps
CPU time 1.4 seconds
Started May 05 02:38:09 PM PDT 24
Finished May 05 02:38:11 PM PDT 24
Peak memory 209412 kb
Host smart-35f5196f-1bed-427f-a555-4d8549ea3e2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920889081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3920889081
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2500632784
Short name T113
Test name
Test status
Simulation time 73911107 ps
CPU time 2.04 seconds
Started May 05 02:38:06 PM PDT 24
Finished May 05 02:38:09 PM PDT 24
Peak memory 217676 kb
Host smart-85f37bed-a005-49a5-9f73-af99f3b00c55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500632784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2500632784
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1777277068
Short name T171
Test name
Test status
Simulation time 33674562 ps
CPU time 1.23 seconds
Started May 05 02:37:29 PM PDT 24
Finished May 05 02:37:31 PM PDT 24
Peak memory 209472 kb
Host smart-22e16379-88c7-4712-b998-f004d32ca9e1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777277068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.1777277068
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4152746476
Short name T914
Test name
Test status
Simulation time 22742594 ps
CPU time 1.17 seconds
Started May 05 02:37:26 PM PDT 24
Finished May 05 02:37:28 PM PDT 24
Peak memory 209432 kb
Host smart-849bc7fb-b1ec-4f76-81b0-126d2467fd69
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152746476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.4152746476
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2107306856
Short name T177
Test name
Test status
Simulation time 13336703 ps
CPU time 1.06 seconds
Started May 05 02:37:28 PM PDT 24
Finished May 05 02:37:30 PM PDT 24
Peak memory 209720 kb
Host smart-c369f924-e8f1-4f1c-99bc-571ea7296c12
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107306856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2107306856
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.825768123
Short name T122
Test name
Test status
Simulation time 350148714 ps
CPU time 1.5 seconds
Started May 05 02:37:28 PM PDT 24
Finished May 05 02:37:30 PM PDT 24
Peak memory 222752 kb
Host smart-3edf0ef7-6d35-4904-ba5d-70008a9acf87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825768123 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.825768123
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.702361591
Short name T938
Test name
Test status
Simulation time 18912625 ps
CPU time 0.88 seconds
Started May 05 02:37:27 PM PDT 24
Finished May 05 02:37:29 PM PDT 24
Peak memory 208828 kb
Host smart-fa12758f-c9e5-4ffa-b1e2-657643743069
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702361591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.702361591
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.4071082275
Short name T912
Test name
Test status
Simulation time 20576422 ps
CPU time 1.11 seconds
Started May 05 02:37:21 PM PDT 24
Finished May 05 02:37:22 PM PDT 24
Peak memory 209348 kb
Host smart-c52802a3-886b-4fbe-8182-583dce63050d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071082275 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.4071082275
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2924608721
Short name T911
Test name
Test status
Simulation time 3202991733 ps
CPU time 9.79 seconds
Started May 05 02:37:27 PM PDT 24
Finished May 05 02:37:37 PM PDT 24
Peak memory 208656 kb
Host smart-441ab883-1499-447a-966f-d26c1cc8318a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924608721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2924608721
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3883761169
Short name T952
Test name
Test status
Simulation time 5078163054 ps
CPU time 51.36 seconds
Started May 05 02:37:22 PM PDT 24
Finished May 05 02:38:14 PM PDT 24
Peak memory 209364 kb
Host smart-a496b875-b627-4139-b4f3-5516172e7e87
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883761169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3883761169
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.4186202714
Short name T890
Test name
Test status
Simulation time 1594011318 ps
CPU time 2.46 seconds
Started May 05 02:37:21 PM PDT 24
Finished May 05 02:37:24 PM PDT 24
Peak memory 210892 kb
Host smart-4935335b-c6ed-4139-a306-5dca6ad63427
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186202714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.4186202714
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1294878486
Short name T964
Test name
Test status
Simulation time 446463628 ps
CPU time 3.97 seconds
Started May 05 02:37:23 PM PDT 24
Finished May 05 02:37:27 PM PDT 24
Peak memory 217640 kb
Host smart-3be09e92-9a5e-48e5-9091-1d98454cc8f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129487
8486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1294878486
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3615598962
Short name T110
Test name
Test status
Simulation time 67285571 ps
CPU time 2.27 seconds
Started May 05 02:37:23 PM PDT 24
Finished May 05 02:37:25 PM PDT 24
Peak memory 209436 kb
Host smart-f63bf94c-64aa-46c3-88eb-843ec21cbe80
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615598962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3615598962
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2405878613
Short name T942
Test name
Test status
Simulation time 21513854 ps
CPU time 1.26 seconds
Started May 05 02:37:20 PM PDT 24
Finished May 05 02:37:22 PM PDT 24
Peak memory 211284 kb
Host smart-d659f58c-6a50-4c61-a3bf-782de88763e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405878613 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2405878613
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3131536222
Short name T904
Test name
Test status
Simulation time 15868900 ps
CPU time 1.01 seconds
Started May 05 02:37:27 PM PDT 24
Finished May 05 02:37:28 PM PDT 24
Peak memory 217628 kb
Host smart-01151851-1be1-468b-8f4b-dd42b5dbc639
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131536222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3131536222
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1227031513
Short name T102
Test name
Test status
Simulation time 766068308 ps
CPU time 3.49 seconds
Started May 05 02:37:28 PM PDT 24
Finished May 05 02:37:32 PM PDT 24
Peak memory 217648 kb
Host smart-4629b2f2-0b00-4190-9d35-05f3d4aebe2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227031513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1227031513
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1309678430
Short name T132
Test name
Test status
Simulation time 1918419447 ps
CPU time 3.96 seconds
Started May 05 02:37:27 PM PDT 24
Finished May 05 02:37:31 PM PDT 24
Peak memory 217628 kb
Host smart-f9fb50d6-114b-4a34-9475-66367aef9403
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309678430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1309678430
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.995841093
Short name T947
Test name
Test status
Simulation time 141587989 ps
CPU time 1.69 seconds
Started May 05 02:37:35 PM PDT 24
Finished May 05 02:37:38 PM PDT 24
Peak memory 209388 kb
Host smart-7903ea4d-de2d-4c41-bc3e-fc72cd813627
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995841093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.995841093
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1920828748
Short name T935
Test name
Test status
Simulation time 67570132 ps
CPU time 2.71 seconds
Started May 05 02:37:31 PM PDT 24
Finished May 05 02:37:35 PM PDT 24
Peak memory 209444 kb
Host smart-2c41bd90-d876-46d9-b1af-f1e691f50146
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920828748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1920828748
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.2898524840
Short name T943
Test name
Test status
Simulation time 15835358 ps
CPU time 0.93 seconds
Started May 05 02:37:35 PM PDT 24
Finished May 05 02:37:36 PM PDT 24
Peak memory 209948 kb
Host smart-6abbe78f-39be-4d6a-a19d-12d806834934
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898524840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.2898524840
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2074030251
Short name T1000
Test name
Test status
Simulation time 101074530 ps
CPU time 1.26 seconds
Started May 05 02:37:33 PM PDT 24
Finished May 05 02:37:35 PM PDT 24
Peak memory 218716 kb
Host smart-bfbeac48-c3e9-482a-937e-9ed200ea38bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074030251 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2074030251
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3136611297
Short name T922
Test name
Test status
Simulation time 53867647 ps
CPU time 0.9 seconds
Started May 05 02:37:34 PM PDT 24
Finished May 05 02:37:35 PM PDT 24
Peak memory 209412 kb
Host smart-3ecdaa1b-fe69-4957-9411-063da78ceca3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136611297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.3136611297
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.4026779611
Short name T920
Test name
Test status
Simulation time 68905475 ps
CPU time 0.9 seconds
Started May 05 02:37:33 PM PDT 24
Finished May 05 02:37:35 PM PDT 24
Peak memory 207956 kb
Host smart-f0392205-c085-41a2-8bb7-74e3f7183b32
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026779611 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.4026779611
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3116143546
Short name T881
Test name
Test status
Simulation time 951217598 ps
CPU time 2.78 seconds
Started May 05 02:37:34 PM PDT 24
Finished May 05 02:37:37 PM PDT 24
Peak memory 209116 kb
Host smart-8e388926-dcc5-4e64-aa1d-30354a2b5c30
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116143546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3116143546
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2671057104
Short name T885
Test name
Test status
Simulation time 1207598167 ps
CPU time 21.88 seconds
Started May 05 02:37:27 PM PDT 24
Finished May 05 02:37:50 PM PDT 24
Peak memory 208560 kb
Host smart-84d6faf7-1848-46f7-acdb-76e103511788
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671057104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.2671057104
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.156118072
Short name T978
Test name
Test status
Simulation time 682749536 ps
CPU time 2.33 seconds
Started May 05 02:37:29 PM PDT 24
Finished May 05 02:37:32 PM PDT 24
Peak memory 210988 kb
Host smart-9b166bac-91a7-4c1a-9b63-e75af0b353f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156118072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.156118072
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.440565867
Short name T893
Test name
Test status
Simulation time 367247260 ps
CPU time 2.06 seconds
Started May 05 02:37:27 PM PDT 24
Finished May 05 02:37:30 PM PDT 24
Peak memory 209312 kb
Host smart-4b8f3f4c-b78c-4648-a441-152b709ee8fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440565867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.440565867
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3124409105
Short name T183
Test name
Test status
Simulation time 35451576 ps
CPU time 1.1 seconds
Started May 05 02:37:32 PM PDT 24
Finished May 05 02:37:33 PM PDT 24
Peak memory 209452 kb
Host smart-ddfe5f41-fcfd-4cf1-8bee-7c027ac4201c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124409105 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3124409105
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3210421240
Short name T941
Test name
Test status
Simulation time 152433892 ps
CPU time 1.46 seconds
Started May 05 02:37:35 PM PDT 24
Finished May 05 02:37:37 PM PDT 24
Peak memory 211640 kb
Host smart-dca4aac5-416c-4499-96d8-b704fa2c69d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210421240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3210421240
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1539078889
Short name T115
Test name
Test status
Simulation time 515537961 ps
CPU time 3.76 seconds
Started May 05 02:37:32 PM PDT 24
Finished May 05 02:37:36 PM PDT 24
Peak memory 217684 kb
Host smart-02431a1a-4dd8-4415-848e-b495e1b14d09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539078889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1539078889
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.249737021
Short name T173
Test name
Test status
Simulation time 142758125 ps
CPU time 1.82 seconds
Started May 05 02:37:32 PM PDT 24
Finished May 05 02:37:34 PM PDT 24
Peak memory 209408 kb
Host smart-0ab31b8b-f9d8-4f25-a05d-4270c1eb16e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249737021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing
.249737021
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.431636440
Short name T193
Test name
Test status
Simulation time 143988757 ps
CPU time 1.26 seconds
Started May 05 02:37:33 PM PDT 24
Finished May 05 02:37:35 PM PDT 24
Peak memory 209392 kb
Host smart-a093d1b2-03df-435b-ae14-539c8bef8707
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431636440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.431636440
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3241974377
Short name T178
Test name
Test status
Simulation time 15216900 ps
CPU time 1.16 seconds
Started May 05 02:37:33 PM PDT 24
Finished May 05 02:37:35 PM PDT 24
Peak memory 209680 kb
Host smart-18d8aee0-d3a6-42ff-9777-d38c08d625e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241974377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3241974377
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1579549848
Short name T880
Test name
Test status
Simulation time 31421039 ps
CPU time 1.31 seconds
Started May 05 02:37:33 PM PDT 24
Finished May 05 02:37:35 PM PDT 24
Peak memory 218252 kb
Host smart-b93eea22-04c8-465d-9d09-aed42d0a878b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579549848 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1579549848
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3112746688
Short name T874
Test name
Test status
Simulation time 44930962 ps
CPU time 0.94 seconds
Started May 05 02:37:31 PM PDT 24
Finished May 05 02:37:33 PM PDT 24
Peak memory 208976 kb
Host smart-7c289bb4-0ff9-4b4e-84b0-b990dcccd6f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112746688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3112746688
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2407989998
Short name T909
Test name
Test status
Simulation time 57551111 ps
CPU time 1.81 seconds
Started May 05 02:37:33 PM PDT 24
Finished May 05 02:37:35 PM PDT 24
Peak memory 209300 kb
Host smart-d15e32fc-defe-4de0-85be-a7720788d8a0
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407989998 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2407989998
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2856785024
Short name T887
Test name
Test status
Simulation time 409179083 ps
CPU time 5.54 seconds
Started May 05 02:37:33 PM PDT 24
Finished May 05 02:37:39 PM PDT 24
Peak memory 209112 kb
Host smart-18cde610-542d-4ecf-934d-f01d325723dc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856785024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2856785024
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4187990628
Short name T916
Test name
Test status
Simulation time 939439878 ps
CPU time 9.13 seconds
Started May 05 02:37:32 PM PDT 24
Finished May 05 02:37:42 PM PDT 24
Peak memory 208504 kb
Host smart-618f307b-13bb-4bbe-83b0-5c5eb52da700
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187990628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.4187990628
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.1397983066
Short name T929
Test name
Test status
Simulation time 94291398 ps
CPU time 3.01 seconds
Started May 05 02:37:33 PM PDT 24
Finished May 05 02:37:37 PM PDT 24
Peak memory 210996 kb
Host smart-a7b21d3f-5167-4684-8066-da4cb38a079a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397983066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.1397983066
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.376217850
Short name T888
Test name
Test status
Simulation time 235606375 ps
CPU time 3.23 seconds
Started May 05 02:37:31 PM PDT 24
Finished May 05 02:37:35 PM PDT 24
Peak memory 218672 kb
Host smart-fd72aa2e-f02d-4e49-8ef2-57b47a262661
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376217
850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.376217850
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2233543687
Short name T996
Test name
Test status
Simulation time 166513681 ps
CPU time 1.59 seconds
Started May 05 02:37:30 PM PDT 24
Finished May 05 02:37:32 PM PDT 24
Peak memory 209296 kb
Host smart-74ef0f91-e504-49bc-91e3-cd21476001de
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233543687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2233543687
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1661352002
Short name T186
Test name
Test status
Simulation time 184770889 ps
CPU time 1.92 seconds
Started May 05 02:37:35 PM PDT 24
Finished May 05 02:37:37 PM PDT 24
Peak memory 211500 kb
Host smart-4df5a701-c7a8-41b6-b8e1-6a02beeb505e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661352002 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1661352002
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3875427357
Short name T956
Test name
Test status
Simulation time 712102610 ps
CPU time 1.7 seconds
Started May 05 02:37:32 PM PDT 24
Finished May 05 02:37:34 PM PDT 24
Peak memory 209156 kb
Host smart-3dd1fdfb-f09f-4b91-bbc9-1bac6b3063f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875427357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3875427357
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2108499181
Short name T105
Test name
Test status
Simulation time 47107346 ps
CPU time 1.49 seconds
Started May 05 02:37:38 PM PDT 24
Finished May 05 02:37:40 PM PDT 24
Peak memory 217636 kb
Host smart-7bf6111a-fb0c-4ef8-9e18-aedef8b19e46
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108499181 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.2108499181
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3404260327
Short name T948
Test name
Test status
Simulation time 27171739 ps
CPU time 1.08 seconds
Started May 05 02:37:37 PM PDT 24
Finished May 05 02:37:39 PM PDT 24
Peak memory 217412 kb
Host smart-86adf519-e279-428d-acb1-759e3012a7bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404260327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3404260327
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2282266997
Short name T963
Test name
Test status
Simulation time 257844555 ps
CPU time 1.34 seconds
Started May 05 02:37:38 PM PDT 24
Finished May 05 02:37:39 PM PDT 24
Peak memory 209368 kb
Host smart-e6bf7cc7-9cf4-4edc-9db5-e02600c0b7ce
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282266997 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2282266997
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3048476516
Short name T135
Test name
Test status
Simulation time 1139599131 ps
CPU time 6.76 seconds
Started May 05 02:37:37 PM PDT 24
Finished May 05 02:37:45 PM PDT 24
Peak memory 209148 kb
Host smart-dab2801f-012e-4b5a-8a85-9819623e694d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048476516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3048476516
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2488608305
Short name T923
Test name
Test status
Simulation time 1752052111 ps
CPU time 7.64 seconds
Started May 05 02:37:38 PM PDT 24
Finished May 05 02:37:47 PM PDT 24
Peak memory 209112 kb
Host smart-335ee9bb-5662-4ada-89c9-e654287559bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488608305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2488608305
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.678742554
Short name T931
Test name
Test status
Simulation time 233408284 ps
CPU time 1.83 seconds
Started May 05 02:37:34 PM PDT 24
Finished May 05 02:37:37 PM PDT 24
Peak memory 210844 kb
Host smart-cfbd5987-0a72-46d3-9eae-9be973fd9fc1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678742554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.678742554
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1180492320
Short name T953
Test name
Test status
Simulation time 143855803 ps
CPU time 1.58 seconds
Started May 05 02:37:37 PM PDT 24
Finished May 05 02:37:39 PM PDT 24
Peak memory 217700 kb
Host smart-fa6cf5b0-5944-4193-8535-4dc0b92cecc1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118049
2320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1180492320
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2382093305
Short name T984
Test name
Test status
Simulation time 74824150 ps
CPU time 2.35 seconds
Started May 05 02:37:37 PM PDT 24
Finished May 05 02:37:39 PM PDT 24
Peak memory 209332 kb
Host smart-285b710c-1803-4464-90df-545091791ba7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382093305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2382093305
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1826229633
Short name T921
Test name
Test status
Simulation time 15900882 ps
CPU time 1.25 seconds
Started May 05 02:37:40 PM PDT 24
Finished May 05 02:37:42 PM PDT 24
Peak memory 209340 kb
Host smart-c326c6f5-1a4e-4691-ae52-51114871697e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826229633 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1826229633
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2601450434
Short name T895
Test name
Test status
Simulation time 75551841 ps
CPU time 1.22 seconds
Started May 05 02:37:39 PM PDT 24
Finished May 05 02:37:40 PM PDT 24
Peak memory 209368 kb
Host smart-ce647319-a70d-4028-9d94-fecd236b682f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601450434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2601450434
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.4012993569
Short name T934
Test name
Test status
Simulation time 132385687 ps
CPU time 2.98 seconds
Started May 05 02:37:38 PM PDT 24
Finished May 05 02:37:41 PM PDT 24
Peak memory 217784 kb
Host smart-45de8b96-8875-43ec-93ac-4dff12c45496
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012993569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.4012993569
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1078044463
Short name T930
Test name
Test status
Simulation time 30735714 ps
CPU time 1.35 seconds
Started May 05 02:37:42 PM PDT 24
Finished May 05 02:37:44 PM PDT 24
Peak memory 218744 kb
Host smart-da944789-51fb-45c1-a109-b9dcb2d43cce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078044463 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1078044463
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.683060100
Short name T944
Test name
Test status
Simulation time 14952329 ps
CPU time 0.81 seconds
Started May 05 02:37:42 PM PDT 24
Finished May 05 02:37:44 PM PDT 24
Peak memory 209328 kb
Host smart-0f654e68-474f-4ce6-a0b3-8f82c8871e21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683060100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.683060100
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.733155398
Short name T875
Test name
Test status
Simulation time 165530740 ps
CPU time 1.11 seconds
Started May 05 02:37:37 PM PDT 24
Finished May 05 02:37:38 PM PDT 24
Peak memory 209260 kb
Host smart-cd456608-748a-4b22-929f-e9e86d2bdf7a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733155398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.733155398
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.742863846
Short name T883
Test name
Test status
Simulation time 926233470 ps
CPU time 5.62 seconds
Started May 05 02:37:36 PM PDT 24
Finished May 05 02:37:42 PM PDT 24
Peak memory 208520 kb
Host smart-5172e9d0-c84e-4cf2-985e-e447974bcd04
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742863846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.742863846
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2619077837
Short name T968
Test name
Test status
Simulation time 4579117094 ps
CPU time 45.86 seconds
Started May 05 02:37:39 PM PDT 24
Finished May 05 02:38:25 PM PDT 24
Peak memory 209360 kb
Host smart-e15c0a4e-087a-428d-ae00-a35e74e7b938
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619077837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2619077837
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2324066781
Short name T965
Test name
Test status
Simulation time 176567776 ps
CPU time 2.85 seconds
Started May 05 02:37:38 PM PDT 24
Finished May 05 02:37:41 PM PDT 24
Peak memory 211100 kb
Host smart-9c51491f-0465-4123-bdd4-888cff04c55c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324066781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2324066781
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1423917795
Short name T954
Test name
Test status
Simulation time 144401512 ps
CPU time 2.38 seconds
Started May 05 02:37:38 PM PDT 24
Finished May 05 02:37:41 PM PDT 24
Peak memory 217660 kb
Host smart-d20a57fc-9671-4f4c-9301-954d49c0766e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142391
7795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1423917795
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1555164568
Short name T884
Test name
Test status
Simulation time 227138407 ps
CPU time 1.49 seconds
Started May 05 02:37:38 PM PDT 24
Finished May 05 02:37:40 PM PDT 24
Peak memory 209352 kb
Host smart-1f1a95c3-3a67-4c03-a736-e95af1fea0ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555164568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1555164568
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.4150495055
Short name T991
Test name
Test status
Simulation time 143719679 ps
CPU time 1.65 seconds
Started May 05 02:37:40 PM PDT 24
Finished May 05 02:37:42 PM PDT 24
Peak memory 209340 kb
Host smart-a05f6f7e-29d2-4706-9acf-f38afa8df0ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150495055 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.4150495055
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1388256278
Short name T891
Test name
Test status
Simulation time 35689520 ps
CPU time 1.45 seconds
Started May 05 02:37:41 PM PDT 24
Finished May 05 02:37:43 PM PDT 24
Peak memory 217568 kb
Host smart-65104221-0611-4111-8918-afb14ccb4200
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388256278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1388256278
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2123200315
Short name T915
Test name
Test status
Simulation time 234377960 ps
CPU time 2.65 seconds
Started May 05 02:37:38 PM PDT 24
Finished May 05 02:37:41 PM PDT 24
Peak memory 217684 kb
Host smart-c6ed4c56-cf50-4858-9594-7ec2d2eedcca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123200315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2123200315
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1482251305
Short name T130
Test name
Test status
Simulation time 41999848 ps
CPU time 1.83 seconds
Started May 05 02:37:43 PM PDT 24
Finished May 05 02:37:45 PM PDT 24
Peak memory 221564 kb
Host smart-a19ccf7c-9339-4355-bb44-6e4807835fb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482251305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1482251305
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.4243447547
Short name T980
Test name
Test status
Simulation time 57299029 ps
CPU time 0.96 seconds
Started May 05 02:37:52 PM PDT 24
Finished May 05 02:37:53 PM PDT 24
Peak memory 209512 kb
Host smart-adcb1d3f-dd46-4825-8929-5394c65123e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243447547 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.4243447547
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3696351126
Short name T913
Test name
Test status
Simulation time 14400791 ps
CPU time 0.86 seconds
Started May 05 02:37:47 PM PDT 24
Finished May 05 02:37:48 PM PDT 24
Peak memory 209424 kb
Host smart-8d573195-313d-4c88-abfd-1854e2dd55eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696351126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3696351126
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.59029344
Short name T955
Test name
Test status
Simulation time 547782820 ps
CPU time 1.16 seconds
Started May 05 02:37:47 PM PDT 24
Finished May 05 02:37:49 PM PDT 24
Peak memory 208008 kb
Host smart-176d38d9-55a6-4399-8304-776d8deabc94
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59029344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_alert_test.59029344
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3038419032
Short name T136
Test name
Test status
Simulation time 321816971 ps
CPU time 3.63 seconds
Started May 05 02:37:40 PM PDT 24
Finished May 05 02:37:44 PM PDT 24
Peak memory 209148 kb
Host smart-c1c9de03-856d-484a-851d-4b89cd2369cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038419032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3038419032
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1597811608
Short name T896
Test name
Test status
Simulation time 2963761103 ps
CPU time 7.87 seconds
Started May 05 02:37:41 PM PDT 24
Finished May 05 02:37:50 PM PDT 24
Peak memory 209412 kb
Host smart-4db322e6-196a-49a0-9da2-88a3bfcbc622
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597811608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1597811608
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.877420580
Short name T882
Test name
Test status
Simulation time 406721281 ps
CPU time 4.39 seconds
Started May 05 02:37:42 PM PDT 24
Finished May 05 02:37:47 PM PDT 24
Peak memory 210980 kb
Host smart-e86095a3-179c-4a4b-9455-d5f771d91573
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877420580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.877420580
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3558630552
Short name T936
Test name
Test status
Simulation time 212628529 ps
CPU time 2.48 seconds
Started May 05 02:37:50 PM PDT 24
Finished May 05 02:37:53 PM PDT 24
Peak memory 219160 kb
Host smart-02bf5352-118e-40bd-8f9c-07fe1f57d904
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355863
0552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3558630552
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3655407921
Short name T979
Test name
Test status
Simulation time 39456310 ps
CPU time 1.11 seconds
Started May 05 02:37:41 PM PDT 24
Finished May 05 02:37:43 PM PDT 24
Peak memory 209336 kb
Host smart-d5a1ad46-6e75-48d4-8887-3ba20f64c3bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655407921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3655407921
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.495117773
Short name T187
Test name
Test status
Simulation time 178261675 ps
CPU time 1.22 seconds
Started May 05 02:37:42 PM PDT 24
Finished May 05 02:37:44 PM PDT 24
Peak memory 208884 kb
Host smart-45880f07-064a-43e0-b9b7-a33cdafc8e3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495117773 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.495117773
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3343568261
Short name T982
Test name
Test status
Simulation time 89283467 ps
CPU time 1.33 seconds
Started May 05 02:37:49 PM PDT 24
Finished May 05 02:37:51 PM PDT 24
Peak memory 209328 kb
Host smart-26065874-2760-4450-a034-4593fdc65ae0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343568261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3343568261
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2367561334
Short name T973
Test name
Test status
Simulation time 166717681 ps
CPU time 3.03 seconds
Started May 05 02:37:46 PM PDT 24
Finished May 05 02:37:50 PM PDT 24
Peak memory 217664 kb
Host smart-99e132fa-cb4a-4a55-9849-5b982ae7131c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367561334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.2367561334
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2131601554
Short name T131
Test name
Test status
Simulation time 48657872 ps
CPU time 2.33 seconds
Started May 05 02:37:48 PM PDT 24
Finished May 05 02:37:51 PM PDT 24
Peak memory 217584 kb
Host smart-38952f54-982e-4258-962b-379821ab6446
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131601554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2131601554
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2745686666
Short name T986
Test name
Test status
Simulation time 34111320 ps
CPU time 1.18 seconds
Started May 05 02:37:52 PM PDT 24
Finished May 05 02:37:53 PM PDT 24
Peak memory 217620 kb
Host smart-a93a9172-c179-4f8c-8ade-6bdacb4da274
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745686666 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.2745686666
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.971012158
Short name T144
Test name
Test status
Simulation time 53467817 ps
CPU time 1.04 seconds
Started May 05 02:37:47 PM PDT 24
Finished May 05 02:37:49 PM PDT 24
Peak memory 209384 kb
Host smart-5e8e5505-a3f4-47a6-91ca-f77df6fef11b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971012158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.971012158
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4053484459
Short name T886
Test name
Test status
Simulation time 46965565 ps
CPU time 1.33 seconds
Started May 05 02:37:48 PM PDT 24
Finished May 05 02:37:50 PM PDT 24
Peak memory 208012 kb
Host smart-5c91d548-8599-4ba4-83bf-a8097dc891ab
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053484459 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.4053484459
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2376317684
Short name T971
Test name
Test status
Simulation time 2345531403 ps
CPU time 6.96 seconds
Started May 05 02:37:47 PM PDT 24
Finished May 05 02:37:54 PM PDT 24
Peak memory 208616 kb
Host smart-dffd8d5a-95bf-4ae1-8f7e-f4fd9f86c6f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376317684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2376317684
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.299772958
Short name T917
Test name
Test status
Simulation time 1351305668 ps
CPU time 11.86 seconds
Started May 05 02:37:48 PM PDT 24
Finished May 05 02:38:00 PM PDT 24
Peak memory 208524 kb
Host smart-64f24346-6153-4df9-a510-e1e21fb70d91
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299772958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.299772958
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.657876618
Short name T928
Test name
Test status
Simulation time 179618964 ps
CPU time 1.74 seconds
Started May 05 02:37:47 PM PDT 24
Finished May 05 02:37:49 PM PDT 24
Peak memory 210940 kb
Host smart-54fd3414-e4c2-4d62-ada6-7593bb904880
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657876618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.657876618
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2359057957
Short name T967
Test name
Test status
Simulation time 78640405 ps
CPU time 2.65 seconds
Started May 05 02:37:48 PM PDT 24
Finished May 05 02:37:51 PM PDT 24
Peak memory 218260 kb
Host smart-4b55f577-9cc3-4705-b6c0-0c15a69c416b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235905
7957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2359057957
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1411485988
Short name T961
Test name
Test status
Simulation time 1202802928 ps
CPU time 3.65 seconds
Started May 05 02:37:47 PM PDT 24
Finished May 05 02:37:51 PM PDT 24
Peak memory 209312 kb
Host smart-6b24ae32-b3e4-405a-b3a0-8a6c58927ebd
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411485988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.1411485988
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1687786565
Short name T995
Test name
Test status
Simulation time 80020915 ps
CPU time 1.12 seconds
Started May 05 02:37:50 PM PDT 24
Finished May 05 02:37:52 PM PDT 24
Peak memory 209324 kb
Host smart-53e9d73a-38c7-4d34-a2c0-f6601d4d6bd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687786565 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1687786565
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.4167091279
Short name T958
Test name
Test status
Simulation time 88210766 ps
CPU time 1.12 seconds
Started May 05 02:37:48 PM PDT 24
Finished May 05 02:37:50 PM PDT 24
Peak memory 209516 kb
Host smart-312519d8-7f9d-4a46-bb84-f69d623099fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167091279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.4167091279
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.4142795496
Short name T977
Test name
Test status
Simulation time 44220154 ps
CPU time 2.94 seconds
Started May 05 02:37:48 PM PDT 24
Finished May 05 02:37:51 PM PDT 24
Peak memory 218668 kb
Host smart-75321e29-99e3-437e-94e8-6337b2c78270
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142795496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.4142795496
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1386809415
Short name T903
Test name
Test status
Simulation time 179488865 ps
CPU time 1.06 seconds
Started May 05 02:37:50 PM PDT 24
Finished May 05 02:37:52 PM PDT 24
Peak memory 219700 kb
Host smart-c5e27c80-084b-49f8-905e-6efa362ad598
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386809415 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1386809415
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1387123053
Short name T966
Test name
Test status
Simulation time 57272947 ps
CPU time 1.07 seconds
Started May 05 02:37:55 PM PDT 24
Finished May 05 02:37:57 PM PDT 24
Peak memory 217596 kb
Host smart-45a4036d-76b1-4b06-9279-08335ce4964e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387123053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1387123053
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1370184254
Short name T906
Test name
Test status
Simulation time 424795662 ps
CPU time 3.13 seconds
Started May 05 02:37:53 PM PDT 24
Finished May 05 02:37:57 PM PDT 24
Peak memory 209264 kb
Host smart-7e2fa469-eecc-48da-b998-c7803a47a2f2
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370184254 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1370184254
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3218992222
Short name T985
Test name
Test status
Simulation time 1501666392 ps
CPU time 4.68 seconds
Started May 05 02:37:51 PM PDT 24
Finished May 05 02:37:56 PM PDT 24
Peak memory 208664 kb
Host smart-ec61e7d5-46c1-456e-82ea-348b1dcff105
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218992222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3218992222
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2538541613
Short name T926
Test name
Test status
Simulation time 2804166221 ps
CPU time 7.43 seconds
Started May 05 02:37:51 PM PDT 24
Finished May 05 02:37:59 PM PDT 24
Peak memory 209380 kb
Host smart-f4680efe-bc9e-406a-a1ce-4ae0884526a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538541613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2538541613
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1829324840
Short name T137
Test name
Test status
Simulation time 720464197 ps
CPU time 2.34 seconds
Started May 05 02:37:50 PM PDT 24
Finished May 05 02:37:53 PM PDT 24
Peak memory 210944 kb
Host smart-2a2a57e2-809a-4797-aef3-7531a2b64167
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829324840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1829324840
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1663305808
Short name T946
Test name
Test status
Simulation time 371959360 ps
CPU time 2.09 seconds
Started May 05 02:37:50 PM PDT 24
Finished May 05 02:37:53 PM PDT 24
Peak memory 217740 kb
Host smart-2fc83513-5991-4282-a4eb-3de0778aceb6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166330
5808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1663305808
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.2048931157
Short name T962
Test name
Test status
Simulation time 42974310 ps
CPU time 1.14 seconds
Started May 05 02:37:51 PM PDT 24
Finished May 05 02:37:52 PM PDT 24
Peak memory 209324 kb
Host smart-0d6f6f00-79ae-4e81-b289-a7d86c3d905c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048931157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.2048931157
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3100964953
Short name T988
Test name
Test status
Simulation time 41140509 ps
CPU time 1.96 seconds
Started May 05 02:37:53 PM PDT 24
Finished May 05 02:37:55 PM PDT 24
Peak memory 209332 kb
Host smart-726816c4-f1c1-418b-bb0c-33ad122daefa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100964953 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3100964953
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4280796935
Short name T919
Test name
Test status
Simulation time 39412543 ps
CPU time 1.85 seconds
Started May 05 02:37:53 PM PDT 24
Finished May 05 02:37:55 PM PDT 24
Peak memory 211236 kb
Host smart-5a714c8f-1e1b-46bf-86fe-3f7fad0b5b43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280796935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.4280796935
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2883652481
Short name T989
Test name
Test status
Simulation time 114587593 ps
CPU time 2.71 seconds
Started May 05 02:37:53 PM PDT 24
Finished May 05 02:37:56 PM PDT 24
Peak memory 217700 kb
Host smart-f1205103-154e-4249-8aed-08c27b21f07f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883652481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2883652481
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1508100753
Short name T391
Test name
Test status
Simulation time 100316022 ps
CPU time 0.83 seconds
Started May 05 01:45:20 PM PDT 24
Finished May 05 01:45:22 PM PDT 24
Peak memory 209340 kb
Host smart-87ed6cd2-2445-479b-8d59-551caeedb0c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508100753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1508100753
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.146161608
Short name T424
Test name
Test status
Simulation time 236405410 ps
CPU time 10.58 seconds
Started May 05 01:45:21 PM PDT 24
Finished May 05 01:45:32 PM PDT 24
Peak memory 218056 kb
Host smart-1b4566c2-f766-4c05-99d1-0a3b8dae6307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146161608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.146161608
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.1403993024
Short name T397
Test name
Test status
Simulation time 809367630 ps
CPU time 7 seconds
Started May 05 01:45:23 PM PDT 24
Finished May 05 01:45:31 PM PDT 24
Peak memory 209704 kb
Host smart-a27f5c5f-7bca-40b1-ac1e-4619e087a706
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403993024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.1403993024
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1860667021
Short name T740
Test name
Test status
Simulation time 8817915645 ps
CPU time 53.14 seconds
Started May 05 01:45:23 PM PDT 24
Finished May 05 01:46:17 PM PDT 24
Peak memory 219536 kb
Host smart-09aa0c89-e82b-450b-8db5-3dead5c40f02
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860667021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1860667021
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2260351868
Short name T68
Test name
Test status
Simulation time 4734345639 ps
CPU time 10.31 seconds
Started May 05 01:45:28 PM PDT 24
Finished May 05 01:45:39 PM PDT 24
Peak memory 217940 kb
Host smart-44e3323a-86f4-4551-b6a4-f117a404bac2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260351868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.2
260351868
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2783751755
Short name T595
Test name
Test status
Simulation time 476209643 ps
CPU time 4.62 seconds
Started May 05 01:45:23 PM PDT 24
Finished May 05 01:45:28 PM PDT 24
Peak memory 218092 kb
Host smart-fb723a7f-ce18-43f4-a2c7-ec0e21a32384
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783751755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2783751755
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.242843468
Short name T318
Test name
Test status
Simulation time 2336116029 ps
CPU time 35.06 seconds
Started May 05 01:45:28 PM PDT 24
Finished May 05 01:46:04 PM PDT 24
Peak memory 213680 kb
Host smart-8cb3cf80-dba1-46a7-a74e-7ac06d2e2bc0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242843468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.242843468
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3926527819
Short name T288
Test name
Test status
Simulation time 192727298 ps
CPU time 2.26 seconds
Started May 05 01:45:27 PM PDT 24
Finished May 05 01:45:30 PM PDT 24
Peak memory 213224 kb
Host smart-e8bd7bf5-f3ef-4a40-92eb-7f2945a7fcf0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926527819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3926527819
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2243087575
Short name T798
Test name
Test status
Simulation time 10522125582 ps
CPU time 63.03 seconds
Started May 05 01:45:22 PM PDT 24
Finished May 05 01:46:25 PM PDT 24
Peak memory 278520 kb
Host smart-9cdcb6f2-730c-40ee-a247-97835dc0f0cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243087575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.2243087575
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.3715715235
Short name T275
Test name
Test status
Simulation time 1155391831 ps
CPU time 18.94 seconds
Started May 05 01:45:19 PM PDT 24
Finished May 05 01:45:38 PM PDT 24
Peak memory 250672 kb
Host smart-ee009357-8fce-42e4-ada5-860849b01931
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715715235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.3715715235
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1264439155
Short name T600
Test name
Test status
Simulation time 712620688 ps
CPU time 3.4 seconds
Started May 05 01:45:24 PM PDT 24
Finished May 05 01:45:28 PM PDT 24
Peak memory 218056 kb
Host smart-a6e21cf3-bc66-4981-b3fe-0261e0a31e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264439155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1264439155
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.4124367131
Short name T638
Test name
Test status
Simulation time 377998256 ps
CPU time 13.42 seconds
Started May 05 01:45:27 PM PDT 24
Finished May 05 01:45:41 PM PDT 24
Peak memory 218032 kb
Host smart-813b0e44-23e0-4532-897f-91c903095cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124367131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.4124367131
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2542163697
Short name T57
Test name
Test status
Simulation time 437102626 ps
CPU time 36.86 seconds
Started May 05 01:45:28 PM PDT 24
Finished May 05 01:46:06 PM PDT 24
Peak memory 280980 kb
Host smart-42021937-6f46-48b0-a868-87dadc68d98a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542163697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2542163697
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1300788088
Short name T704
Test name
Test status
Simulation time 2921441563 ps
CPU time 20.67 seconds
Started May 05 01:45:32 PM PDT 24
Finished May 05 01:45:53 PM PDT 24
Peak memory 220144 kb
Host smart-fad08767-42ee-4471-b008-faacd692256b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300788088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1300788088
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1143750091
Short name T259
Test name
Test status
Simulation time 291943388 ps
CPU time 9.58 seconds
Started May 05 01:45:22 PM PDT 24
Finished May 05 01:45:32 PM PDT 24
Peak memory 218088 kb
Host smart-34f40784-e3f8-4fc9-a434-2addb116567d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143750091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1143750091
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.568936332
Short name T229
Test name
Test status
Simulation time 189436431 ps
CPU time 6.95 seconds
Started May 05 01:45:23 PM PDT 24
Finished May 05 01:45:30 PM PDT 24
Peak memory 218076 kb
Host smart-c9e2eaef-e6a5-48d8-85c0-5e3018222af2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568936332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.568936332
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3991191028
Short name T486
Test name
Test status
Simulation time 262015871 ps
CPU time 6.18 seconds
Started May 05 01:45:37 PM PDT 24
Finished May 05 01:45:45 PM PDT 24
Peak memory 214344 kb
Host smart-af203e24-b64f-43e1-9f49-34ab3e112716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991191028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3991191028
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2226490655
Short name T324
Test name
Test status
Simulation time 556248419 ps
CPU time 27.65 seconds
Started May 05 01:45:40 PM PDT 24
Finished May 05 01:46:08 PM PDT 24
Peak memory 251060 kb
Host smart-1073fe5f-74db-472c-b390-fdea23320193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226490655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2226490655
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2845759118
Short name T707
Test name
Test status
Simulation time 294357772 ps
CPU time 8.3 seconds
Started May 05 01:45:23 PM PDT 24
Finished May 05 01:45:31 PM PDT 24
Peak memory 251084 kb
Host smart-d6eda1aa-d87f-475b-9877-5eced0d52799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845759118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2845759118
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.842057429
Short name T429
Test name
Test status
Simulation time 4077474419 ps
CPU time 143.85 seconds
Started May 05 01:45:21 PM PDT 24
Finished May 05 01:47:45 PM PDT 24
Peak memory 272844 kb
Host smart-bd3ee555-ca26-42b2-8bca-38a035446f64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842057429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.842057429
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.43177253
Short name T207
Test name
Test status
Simulation time 17096932 ps
CPU time 0.94 seconds
Started May 05 01:45:28 PM PDT 24
Finished May 05 01:45:30 PM PDT 24
Peak memory 211748 kb
Host smart-f9b59cc4-a8c6-4d3d-ae12-aa955b017c37
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43177253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_volatile_unlock_smoke.43177253
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.4110764046
Short name T834
Test name
Test status
Simulation time 29019541 ps
CPU time 1.17 seconds
Started May 05 01:45:31 PM PDT 24
Finished May 05 01:45:33 PM PDT 24
Peak memory 209676 kb
Host smart-c5498af0-0c14-4329-9715-09d959eb958b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110764046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.4110764046
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3113686554
Short name T369
Test name
Test status
Simulation time 275259019 ps
CPU time 12.13 seconds
Started May 05 01:45:22 PM PDT 24
Finished May 05 01:45:34 PM PDT 24
Peak memory 218396 kb
Host smart-5ede0fd0-bae4-437d-ac8b-9b1ad1d7a73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113686554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3113686554
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2410137834
Short name T466
Test name
Test status
Simulation time 751538168 ps
CPU time 9.46 seconds
Started May 05 01:45:24 PM PDT 24
Finished May 05 01:45:34 PM PDT 24
Peak memory 217092 kb
Host smart-f6e65c6e-a88e-4abf-9920-efe2c3ec08ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410137834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2410137834
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3477034688
Short name T23
Test name
Test status
Simulation time 4198307269 ps
CPU time 58.42 seconds
Started May 05 01:45:41 PM PDT 24
Finished May 05 01:46:41 PM PDT 24
Peak memory 218788 kb
Host smart-c038499e-04b8-4811-8163-4618a70174b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477034688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3477034688
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2312441126
Short name T470
Test name
Test status
Simulation time 180928990 ps
CPU time 5.55 seconds
Started May 05 01:45:27 PM PDT 24
Finished May 05 01:45:33 PM PDT 24
Peak memory 217328 kb
Host smart-56d6d3bb-f13b-4259-9488-683a2be02f72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312441126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
312441126
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.1469699093
Short name T572
Test name
Test status
Simulation time 1998610992 ps
CPU time 14.05 seconds
Started May 05 01:45:28 PM PDT 24
Finished May 05 01:45:43 PM PDT 24
Peak memory 218096 kb
Host smart-85abe302-5cd2-4034-ba98-6a4d99067229
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469699093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.1469699093
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3187944843
Short name T592
Test name
Test status
Simulation time 3026326337 ps
CPU time 19.54 seconds
Started May 05 01:45:35 PM PDT 24
Finished May 05 01:45:55 PM PDT 24
Peak memory 213644 kb
Host smart-3f87b452-d693-402b-a0d9-3aab0e80e631
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187944843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3187944843
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3823736497
Short name T519
Test name
Test status
Simulation time 2008023699 ps
CPU time 5.51 seconds
Started May 05 01:45:40 PM PDT 24
Finished May 05 01:45:46 PM PDT 24
Peak memory 213664 kb
Host smart-ff5495ca-6abb-4861-b0ff-c45109b23be1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823736497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3823736497
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3544843282
Short name T807
Test name
Test status
Simulation time 8453441740 ps
CPU time 50.2 seconds
Started May 05 01:45:23 PM PDT 24
Finished May 05 01:46:13 PM PDT 24
Peak memory 278184 kb
Host smart-5cd75a44-1461-46d2-bbfc-56ba5a0fb612
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544843282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3544843282
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1592652440
Short name T782
Test name
Test status
Simulation time 418835960 ps
CPU time 7.29 seconds
Started May 05 01:45:21 PM PDT 24
Finished May 05 01:45:29 PM PDT 24
Peak memory 224124 kb
Host smart-94953449-cda5-4b08-8a3b-51cbb9c74e2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592652440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1592652440
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1562418400
Short name T727
Test name
Test status
Simulation time 989819488 ps
CPU time 2.45 seconds
Started May 05 01:45:29 PM PDT 24
Finished May 05 01:45:32 PM PDT 24
Peak memory 218108 kb
Host smart-b85cc913-43ea-4234-9b90-ffe19fc7785f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562418400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1562418400
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.1968671043
Short name T96
Test name
Test status
Simulation time 318485648 ps
CPU time 8.11 seconds
Started May 05 01:45:26 PM PDT 24
Finished May 05 01:45:35 PM PDT 24
Peak memory 214592 kb
Host smart-1d8f45c4-2b25-410a-83c5-e65011475198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968671043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1968671043
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2706566560
Short name T263
Test name
Test status
Simulation time 719796974 ps
CPU time 15.06 seconds
Started May 05 01:45:35 PM PDT 24
Finished May 05 01:45:51 PM PDT 24
Peak memory 226200 kb
Host smart-6d256e0d-d1cf-403c-aac5-514173c7c10a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706566560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2706566560
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.289566467
Short name T218
Test name
Test status
Simulation time 3173121795 ps
CPU time 15.64 seconds
Started May 05 01:45:41 PM PDT 24
Finished May 05 01:45:58 PM PDT 24
Peak memory 219136 kb
Host smart-69ed932b-0cd3-4c2a-a8f4-d057bbf83803
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289566467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.289566467
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.237318925
Short name T785
Test name
Test status
Simulation time 2880197692 ps
CPU time 10.17 seconds
Started May 05 01:45:24 PM PDT 24
Finished May 05 01:45:34 PM PDT 24
Peak memory 218216 kb
Host smart-dc8d03e3-7408-4808-81d5-1145333af133
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237318925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.237318925
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3865867704
Short name T603
Test name
Test status
Simulation time 221564846 ps
CPU time 8.27 seconds
Started May 05 01:45:23 PM PDT 24
Finished May 05 01:45:32 PM PDT 24
Peak memory 218256 kb
Host smart-8de7f006-fe19-4c16-a428-b051d5b5ddba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865867704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3865867704
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3896618968
Short name T37
Test name
Test status
Simulation time 40345479 ps
CPU time 2.72 seconds
Started May 05 01:45:21 PM PDT 24
Finished May 05 01:45:24 PM PDT 24
Peak memory 214152 kb
Host smart-9b313b23-2d5e-458e-ba16-34be5e65c8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896618968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3896618968
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2499171134
Short name T268
Test name
Test status
Simulation time 166062727 ps
CPU time 22.86 seconds
Started May 05 01:45:46 PM PDT 24
Finished May 05 01:46:11 PM PDT 24
Peak memory 249384 kb
Host smart-1d810a30-1815-4fde-a766-0a8bdf23cbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499171134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2499171134
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.4104189223
Short name T741
Test name
Test status
Simulation time 163073807 ps
CPU time 8.74 seconds
Started May 05 01:45:23 PM PDT 24
Finished May 05 01:45:32 PM PDT 24
Peak memory 251116 kb
Host smart-19af0dfd-520b-4aea-a3ce-dd666d5dd302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104189223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.4104189223
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.807579896
Short name T505
Test name
Test status
Simulation time 3591509832 ps
CPU time 62.9 seconds
Started May 05 01:45:35 PM PDT 24
Finished May 05 01:46:38 PM PDT 24
Peak memory 271192 kb
Host smart-f6161159-5fbd-4e08-841b-410d1b24c5de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807579896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.807579896
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2661371036
Short name T59
Test name
Test status
Simulation time 13988710652 ps
CPU time 125.7 seconds
Started May 05 01:45:41 PM PDT 24
Finished May 05 01:47:48 PM PDT 24
Peak memory 283956 kb
Host smart-9c937cf9-29fa-4850-a477-f989f592a111
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2661371036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.2661371036
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2724498659
Short name T155
Test name
Test status
Simulation time 13220667 ps
CPU time 0.96 seconds
Started May 05 01:45:21 PM PDT 24
Finished May 05 01:45:23 PM PDT 24
Peak memory 211904 kb
Host smart-44ec0e95-3619-4019-b2e8-2677ffbc8925
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724498659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2724498659
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2238792022
Short name T777
Test name
Test status
Simulation time 62107654 ps
CPU time 0.86 seconds
Started May 05 01:45:45 PM PDT 24
Finished May 05 01:45:48 PM PDT 24
Peak memory 209648 kb
Host smart-8fedc3e9-26b1-442e-b4bb-5babf109d76e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238792022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2238792022
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.871256567
Short name T814
Test name
Test status
Simulation time 695018518 ps
CPU time 14.82 seconds
Started May 05 01:45:46 PM PDT 24
Finished May 05 01:46:02 PM PDT 24
Peak memory 218168 kb
Host smart-f1cb4775-6db9-4bbb-b5ee-8a65ca2e4bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871256567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.871256567
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.4038610571
Short name T507
Test name
Test status
Simulation time 1589824508 ps
CPU time 7.41 seconds
Started May 05 01:45:49 PM PDT 24
Finished May 05 01:45:57 PM PDT 24
Peak memory 209708 kb
Host smart-b286e7de-f1cc-44a0-b717-72679a08b00c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038610571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.4038610571
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.4063105916
Short name T611
Test name
Test status
Simulation time 848531265 ps
CPU time 15.42 seconds
Started May 05 01:45:45 PM PDT 24
Finished May 05 01:46:02 PM PDT 24
Peak memory 218076 kb
Host smart-6ebc8012-1d83-457c-9087-26dd4ab6655c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063105916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.4063105916
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1304038750
Short name T283
Test name
Test status
Simulation time 862858713 ps
CPU time 6.67 seconds
Started May 05 01:45:47 PM PDT 24
Finished May 05 01:45:55 PM PDT 24
Peak memory 213992 kb
Host smart-3205de0d-f560-44f4-92a1-09266c4fd60b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304038750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1304038750
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1308085094
Short name T714
Test name
Test status
Simulation time 4113175174 ps
CPU time 73.2 seconds
Started May 05 01:46:10 PM PDT 24
Finished May 05 01:47:24 PM PDT 24
Peak memory 271944 kb
Host smart-af9e8522-9319-4eda-ad73-894814350840
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308085094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1308085094
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3766013835
Short name T497
Test name
Test status
Simulation time 920852331 ps
CPU time 33.39 seconds
Started May 05 01:46:07 PM PDT 24
Finished May 05 01:46:41 PM PDT 24
Peak memory 249444 kb
Host smart-1dfbdf7b-9272-4fe5-8af4-697c21795eaa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766013835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3766013835
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2654690665
Short name T212
Test name
Test status
Simulation time 269136850 ps
CPU time 3.26 seconds
Started May 05 01:46:06 PM PDT 24
Finished May 05 01:46:10 PM PDT 24
Peak memory 218032 kb
Host smart-685de606-96eb-4591-b99a-1c45e66eb36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654690665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2654690665
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.2315828232
Short name T388
Test name
Test status
Simulation time 986812290 ps
CPU time 8.81 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:45:54 PM PDT 24
Peak memory 218068 kb
Host smart-a29e1b4c-30d4-40b9-b567-dfde1d12e9a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315828232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2315828232
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1710318545
Short name T634
Test name
Test status
Simulation time 365512907 ps
CPU time 8.97 seconds
Started May 05 01:45:47 PM PDT 24
Finished May 05 01:45:57 PM PDT 24
Peak memory 218112 kb
Host smart-d3f1937b-381d-4afa-9dbd-cf22a7f948b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710318545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1710318545
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2534355823
Short name T410
Test name
Test status
Simulation time 1594025370 ps
CPU time 11.82 seconds
Started May 05 01:45:47 PM PDT 24
Finished May 05 01:46:00 PM PDT 24
Peak memory 218060 kb
Host smart-ff570424-062c-49d3-80cc-f1c404df8895
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534355823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2534355823
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2054611932
Short name T618
Test name
Test status
Simulation time 336570961 ps
CPU time 8.53 seconds
Started May 05 01:45:44 PM PDT 24
Finished May 05 01:45:55 PM PDT 24
Peak memory 218180 kb
Host smart-1810e857-1b4f-4d33-8535-16f7157c0fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054611932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2054611932
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.1821392805
Short name T831
Test name
Test status
Simulation time 174644770 ps
CPU time 4.05 seconds
Started May 05 01:45:46 PM PDT 24
Finished May 05 01:45:52 PM PDT 24
Peak memory 218108 kb
Host smart-3f451a64-8dc7-4efe-a258-52e11cb7de95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821392805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.1821392805
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3524840204
Short name T787
Test name
Test status
Simulation time 360716791 ps
CPU time 31.63 seconds
Started May 05 01:45:52 PM PDT 24
Finished May 05 01:46:24 PM PDT 24
Peak memory 248824 kb
Host smart-ac87f61c-bccf-47e6-b6d0-3d08893f5579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524840204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3524840204
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.3613085657
Short name T608
Test name
Test status
Simulation time 51800716 ps
CPU time 6.45 seconds
Started May 05 01:45:44 PM PDT 24
Finished May 05 01:45:53 PM PDT 24
Peak memory 250960 kb
Host smart-fe959c29-e8ad-4bba-9535-db146360a7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613085657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.3613085657
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.4137770672
Short name T629
Test name
Test status
Simulation time 23247449927 ps
CPU time 187.69 seconds
Started May 05 01:46:01 PM PDT 24
Finished May 05 01:49:09 PM PDT 24
Peak memory 283948 kb
Host smart-d3af9e20-0f03-4405-98d1-f919042f7481
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137770672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.4137770672
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2995529269
Short name T3
Test name
Test status
Simulation time 35063741 ps
CPU time 0.98 seconds
Started May 05 01:45:57 PM PDT 24
Finished May 05 01:45:58 PM PDT 24
Peak memory 211732 kb
Host smart-c87f8c5f-d8cf-4d90-a698-dc1e67eb406a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995529269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2995529269
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1561128688
Short name T306
Test name
Test status
Simulation time 29610676 ps
CPU time 1.06 seconds
Started May 05 01:46:03 PM PDT 24
Finished May 05 01:46:05 PM PDT 24
Peak memory 209668 kb
Host smart-6d42ebff-bc63-4a46-9e41-7ce8c78d24fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561128688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1561128688
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2058100333
Short name T804
Test name
Test status
Simulation time 1797392246 ps
CPU time 15.72 seconds
Started May 05 01:45:53 PM PDT 24
Finished May 05 01:46:09 PM PDT 24
Peak memory 218104 kb
Host smart-7c186913-e07c-4f3f-ae9c-5dcd7adb939c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058100333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2058100333
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3639466051
Short name T170
Test name
Test status
Simulation time 61605943 ps
CPU time 1.42 seconds
Started May 05 01:46:07 PM PDT 24
Finished May 05 01:46:09 PM PDT 24
Peak memory 216996 kb
Host smart-e9eb767f-d1cd-4634-ae1e-b8971884ccf3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639466051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3639466051
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1013424739
Short name T46
Test name
Test status
Simulation time 6999920591 ps
CPU time 34.33 seconds
Started May 05 01:46:02 PM PDT 24
Finished May 05 01:46:37 PM PDT 24
Peak memory 218144 kb
Host smart-3c74e17a-2c7d-4fa4-9af4-4eaf7ed4ea53
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013424739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1013424739
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2017329051
Short name T689
Test name
Test status
Simulation time 2508600171 ps
CPU time 7.61 seconds
Started May 05 01:45:47 PM PDT 24
Finished May 05 01:45:56 PM PDT 24
Peak memory 218172 kb
Host smart-7e56fc69-a5d6-4662-b06a-0806804b482d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017329051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2017329051
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.2024542516
Short name T313
Test name
Test status
Simulation time 421563297 ps
CPU time 2.63 seconds
Started May 05 01:45:54 PM PDT 24
Finished May 05 01:45:57 PM PDT 24
Peak memory 213340 kb
Host smart-d2e6f2e4-cfe3-4030-99d1-deeb229943d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024542516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.2024542516
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2886251652
Short name T658
Test name
Test status
Simulation time 15813581016 ps
CPU time 45.41 seconds
Started May 05 01:45:58 PM PDT 24
Finished May 05 01:46:44 PM PDT 24
Peak memory 280652 kb
Host smart-cff5b26c-63cf-4c40-8fcd-74122624c518
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886251652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2886251652
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1359945634
Short name T585
Test name
Test status
Simulation time 1208295990 ps
CPU time 9.66 seconds
Started May 05 01:46:01 PM PDT 24
Finished May 05 01:46:11 PM PDT 24
Peak memory 247584 kb
Host smart-c4c71d49-be3a-4d9e-a378-372d49e8c68c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359945634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1359945634
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2730122732
Short name T824
Test name
Test status
Simulation time 89022437 ps
CPU time 2.59 seconds
Started May 05 01:46:04 PM PDT 24
Finished May 05 01:46:07 PM PDT 24
Peak memory 218100 kb
Host smart-f1405226-9132-4654-85c4-87d7c2ba95ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730122732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2730122732
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2008616238
Short name T599
Test name
Test status
Simulation time 3235997538 ps
CPU time 14.28 seconds
Started May 05 01:45:55 PM PDT 24
Finished May 05 01:46:10 PM PDT 24
Peak memory 226196 kb
Host smart-ce5f3991-fbde-490f-b080-562b13de051d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008616238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2008616238
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1900479351
Short name T244
Test name
Test status
Simulation time 392887000 ps
CPU time 15.12 seconds
Started May 05 01:45:49 PM PDT 24
Finished May 05 01:46:05 PM PDT 24
Peak memory 218132 kb
Host smart-077c02c1-6a4e-4720-a343-15bffa33aad4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900479351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1900479351
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3969801555
Short name T784
Test name
Test status
Simulation time 1022156358 ps
CPU time 6.52 seconds
Started May 05 01:45:46 PM PDT 24
Finished May 05 01:45:54 PM PDT 24
Peak memory 218016 kb
Host smart-6cae4e2f-2339-4419-95e3-cd0c74cc2017
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969801555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3969801555
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1464008087
Short name T761
Test name
Test status
Simulation time 186270339 ps
CPU time 6.24 seconds
Started May 05 01:46:02 PM PDT 24
Finished May 05 01:46:09 PM PDT 24
Peak memory 218140 kb
Host smart-ecb8b1d1-daed-4dc2-8ce3-21bdc5577132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464008087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1464008087
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.1083379798
Short name T91
Test name
Test status
Simulation time 193951067 ps
CPU time 2.69 seconds
Started May 05 01:45:57 PM PDT 24
Finished May 05 01:46:00 PM PDT 24
Peak memory 214252 kb
Host smart-428df5b8-8369-41bf-94ed-50b6f5e365cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083379798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1083379798
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.2394014857
Short name T678
Test name
Test status
Simulation time 1226903821 ps
CPU time 23.81 seconds
Started May 05 01:45:53 PM PDT 24
Finished May 05 01:46:17 PM PDT 24
Peak memory 248816 kb
Host smart-0e509a15-c22c-4e75-a7d4-6df9b62bd9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394014857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2394014857
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.4236174227
Short name T521
Test name
Test status
Simulation time 62936149 ps
CPU time 5.95 seconds
Started May 05 01:45:47 PM PDT 24
Finished May 05 01:45:54 PM PDT 24
Peak memory 242940 kb
Host smart-d3eecd3d-fef3-4dc5-be9c-7e3b2735b498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236174227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.4236174227
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.999800831
Short name T749
Test name
Test status
Simulation time 2497243424 ps
CPU time 46.17 seconds
Started May 05 01:45:54 PM PDT 24
Finished May 05 01:46:41 PM PDT 24
Peak memory 226648 kb
Host smart-07661716-9856-44ad-ae4b-8f745b0b0f88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999800831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.999800831
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.3753897996
Short name T165
Test name
Test status
Simulation time 77974235227 ps
CPU time 634.62 seconds
Started May 05 01:46:05 PM PDT 24
Finished May 05 01:56:41 PM PDT 24
Peak memory 283832 kb
Host smart-e31fcbe1-d156-4c77-a134-1d81950e7bf8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3753897996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.3753897996
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.762640418
Short name T353
Test name
Test status
Simulation time 20326643 ps
CPU time 0.86 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:45:46 PM PDT 24
Peak memory 211724 kb
Host smart-b46cd804-e833-46de-8acb-4483b77e4d2d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762640418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ct
rl_volatile_unlock_smoke.762640418
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.725847605
Short name T818
Test name
Test status
Simulation time 18549469 ps
CPU time 0.99 seconds
Started May 05 01:45:59 PM PDT 24
Finished May 05 01:46:00 PM PDT 24
Peak memory 209668 kb
Host smart-b12b0f0f-0a0e-4c1c-8ffc-ea749ac080ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725847605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.725847605
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3328646171
Short name T355
Test name
Test status
Simulation time 453238536 ps
CPU time 11.22 seconds
Started May 05 01:46:05 PM PDT 24
Finished May 05 01:46:17 PM PDT 24
Peak memory 218008 kb
Host smart-b851595f-ac5c-4d2f-ae8d-e9b0819b859c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328646171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3328646171
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1903393477
Short name T512
Test name
Test status
Simulation time 622067965 ps
CPU time 4.28 seconds
Started May 05 01:46:01 PM PDT 24
Finished May 05 01:46:05 PM PDT 24
Peak memory 209616 kb
Host smart-650aa95f-2e33-4706-aba2-e55f2e06fd5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903393477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1903393477
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1391520470
Short name T625
Test name
Test status
Simulation time 2624530354 ps
CPU time 21.31 seconds
Started May 05 01:46:02 PM PDT 24
Finished May 05 01:46:24 PM PDT 24
Peak memory 219104 kb
Host smart-126e884d-39eb-4885-b046-ae4135992cfa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391520470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1391520470
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1765912522
Short name T225
Test name
Test status
Simulation time 1933338499 ps
CPU time 6.04 seconds
Started May 05 01:46:05 PM PDT 24
Finished May 05 01:46:12 PM PDT 24
Peak memory 218132 kb
Host smart-f1fcb746-2573-4228-ae04-b0f979d594b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765912522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1765912522
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.883896521
Short name T578
Test name
Test status
Simulation time 1502225295 ps
CPU time 4.29 seconds
Started May 05 01:45:51 PM PDT 24
Finished May 05 01:45:56 PM PDT 24
Peak memory 213440 kb
Host smart-69347b1b-84e8-49ef-b123-ae185f5784a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883896521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.
883896521
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1209636014
Short name T420
Test name
Test status
Simulation time 3571926713 ps
CPU time 44.37 seconds
Started May 05 01:45:56 PM PDT 24
Finished May 05 01:46:41 PM PDT 24
Peak memory 251004 kb
Host smart-81eb6ff2-0e27-43f2-91d8-84f1e606317c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209636014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1209636014
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2650916810
Short name T560
Test name
Test status
Simulation time 1238215439 ps
CPU time 10 seconds
Started May 05 01:46:04 PM PDT 24
Finished May 05 01:46:15 PM PDT 24
Peak memory 251064 kb
Host smart-24b1f9ef-4364-4b48-af6f-5cce6260c1fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650916810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2650916810
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1543345462
Short name T732
Test name
Test status
Simulation time 129751271 ps
CPU time 3.54 seconds
Started May 05 01:45:49 PM PDT 24
Finished May 05 01:45:53 PM PDT 24
Peak memory 218100 kb
Host smart-355753e0-3881-4ce7-84b7-bae8c135d3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543345462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1543345462
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2588423894
Short name T635
Test name
Test status
Simulation time 696882574 ps
CPU time 18.05 seconds
Started May 05 01:46:05 PM PDT 24
Finished May 05 01:46:24 PM PDT 24
Peak memory 219052 kb
Host smart-2caddd89-f3fe-483c-a82a-1ed40e514765
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588423894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2588423894
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.473335487
Short name T852
Test name
Test status
Simulation time 2167495305 ps
CPU time 13.57 seconds
Started May 05 01:45:47 PM PDT 24
Finished May 05 01:46:02 PM PDT 24
Peak memory 218148 kb
Host smart-2de0ad54-b314-424a-bfd1-af344692988c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473335487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.473335487
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3090185896
Short name T783
Test name
Test status
Simulation time 306585570 ps
CPU time 12.47 seconds
Started May 05 01:46:02 PM PDT 24
Finished May 05 01:46:16 PM PDT 24
Peak memory 218116 kb
Host smart-7413807f-1718-433f-bf81-4e18d6111029
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090185896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3090185896
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1430865136
Short name T53
Test name
Test status
Simulation time 578077236 ps
CPU time 7.54 seconds
Started May 05 01:46:03 PM PDT 24
Finished May 05 01:46:12 PM PDT 24
Peak memory 218164 kb
Host smart-181face3-7c46-4eb9-81c2-c4dede21c379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430865136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1430865136
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1583655330
Short name T73
Test name
Test status
Simulation time 75236758 ps
CPU time 2.46 seconds
Started May 05 01:46:05 PM PDT 24
Finished May 05 01:46:09 PM PDT 24
Peak memory 217888 kb
Host smart-c03ec8d9-d23f-44b9-8a8a-54f5c6eb713a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583655330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1583655330
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1792786480
Short name T576
Test name
Test status
Simulation time 351033383 ps
CPU time 34.33 seconds
Started May 05 01:46:02 PM PDT 24
Finished May 05 01:46:37 PM PDT 24
Peak memory 251072 kb
Host smart-3b589ec3-038e-415b-9665-ee8ef988f69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792786480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1792786480
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.599784184
Short name T266
Test name
Test status
Simulation time 105750519 ps
CPU time 5.94 seconds
Started May 05 01:46:04 PM PDT 24
Finished May 05 01:46:10 PM PDT 24
Peak memory 251080 kb
Host smart-a87e8d18-8a2b-42f5-aebf-b26b75fd1d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599784184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.599784184
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1838917902
Short name T632
Test name
Test status
Simulation time 14911796 ps
CPU time 1.1 seconds
Started May 05 01:45:48 PM PDT 24
Finished May 05 01:45:50 PM PDT 24
Peak memory 211748 kb
Host smart-b3c3cd76-213f-4c89-abff-aaabf7e0ca4d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838917902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1838917902
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.738943453
Short name T264
Test name
Test status
Simulation time 21178358 ps
CPU time 1.26 seconds
Started May 05 01:46:02 PM PDT 24
Finished May 05 01:46:03 PM PDT 24
Peak memory 209688 kb
Host smart-4b0d6ffd-ce07-41cf-9f8e-70d3f481ed9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738943453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.738943453
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.847705538
Short name T609
Test name
Test status
Simulation time 353639002 ps
CPU time 12.91 seconds
Started May 05 01:45:52 PM PDT 24
Finished May 05 01:46:06 PM PDT 24
Peak memory 218092 kb
Host smart-81caf546-c170-4c30-9268-60d2ceaed812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847705538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.847705538
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2541294260
Short name T360
Test name
Test status
Simulation time 143647250 ps
CPU time 4.05 seconds
Started May 05 01:46:01 PM PDT 24
Finished May 05 01:46:06 PM PDT 24
Peak memory 209684 kb
Host smart-c24b9cc1-021c-4636-8098-f7800096dc21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541294260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2541294260
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2877311248
Short name T428
Test name
Test status
Simulation time 1827147944 ps
CPU time 30.77 seconds
Started May 05 01:46:01 PM PDT 24
Finished May 05 01:46:32 PM PDT 24
Peak memory 218080 kb
Host smart-06baac50-61f1-4854-bc4e-956a24ece5db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877311248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2877311248
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.165081871
Short name T536
Test name
Test status
Simulation time 3698964209 ps
CPU time 20.39 seconds
Started May 05 01:46:03 PM PDT 24
Finished May 05 01:46:24 PM PDT 24
Peak memory 218168 kb
Host smart-8f7d7ceb-49f2-4067-9d1c-e387b4ef72c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165081871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_prog_failure.165081871
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2850048820
Short name T685
Test name
Test status
Simulation time 231286024 ps
CPU time 2.32 seconds
Started May 05 01:46:05 PM PDT 24
Finished May 05 01:46:08 PM PDT 24
Peak memory 213116 kb
Host smart-13310070-6c60-4561-8e4f-56b21bb5e9c2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850048820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2850048820
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3854234880
Short name T633
Test name
Test status
Simulation time 2903384266 ps
CPU time 49.71 seconds
Started May 05 01:46:03 PM PDT 24
Finished May 05 01:46:54 PM PDT 24
Peak memory 270364 kb
Host smart-d9510717-b82e-4dfc-8ae2-f47a6d3c5df2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854234880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3854234880
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3376681446
Short name T550
Test name
Test status
Simulation time 3102226724 ps
CPU time 8.12 seconds
Started May 05 01:46:05 PM PDT 24
Finished May 05 01:46:14 PM PDT 24
Peak memory 223552 kb
Host smart-301e0815-7e0c-409c-b665-7863474934fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376681446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3376681446
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.2459221932
Short name T416
Test name
Test status
Simulation time 846042724 ps
CPU time 3.8 seconds
Started May 05 01:46:02 PM PDT 24
Finished May 05 01:46:06 PM PDT 24
Peak memory 218096 kb
Host smart-7b4f3255-0105-459b-8abf-7d2d4af39b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459221932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.2459221932
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1987782827
Short name T477
Test name
Test status
Simulation time 241088338 ps
CPU time 8.07 seconds
Started May 05 01:46:03 PM PDT 24
Finished May 05 01:46:12 PM PDT 24
Peak memory 218080 kb
Host smart-f904e7b5-f5d6-47ee-bc04-c9662f3cc581
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987782827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1987782827
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.119942705
Short name T441
Test name
Test status
Simulation time 1072131804 ps
CPU time 6.85 seconds
Started May 05 01:45:53 PM PDT 24
Finished May 05 01:46:01 PM PDT 24
Peak memory 218072 kb
Host smart-80aa945c-443b-4333-b2f7-0e82e24b415d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119942705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.119942705
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.108924487
Short name T159
Test name
Test status
Simulation time 395600167 ps
CPU time 9.41 seconds
Started May 05 01:46:04 PM PDT 24
Finished May 05 01:46:14 PM PDT 24
Peak memory 218124 kb
Host smart-73a07fea-ec2d-47eb-affd-23030ad072d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108924487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.108924487
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3043418300
Short name T561
Test name
Test status
Simulation time 1178101478 ps
CPU time 12.42 seconds
Started May 05 01:46:03 PM PDT 24
Finished May 05 01:46:16 PM PDT 24
Peak memory 218164 kb
Host smart-130e9fbd-7993-4ecd-83f5-a29b8e9544b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043418300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3043418300
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3786163816
Short name T368
Test name
Test status
Simulation time 21895434 ps
CPU time 1.5 seconds
Started May 05 01:46:04 PM PDT 24
Finished May 05 01:46:06 PM PDT 24
Peak memory 213660 kb
Host smart-abfb1d36-9983-4fc3-a545-520e2a3ce8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786163816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3786163816
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.1443631265
Short name T376
Test name
Test status
Simulation time 915135536 ps
CPU time 34.36 seconds
Started May 05 01:46:04 PM PDT 24
Finished May 05 01:46:40 PM PDT 24
Peak memory 247120 kb
Host smart-d1d05f99-05ef-4bd5-b571-3bfba6c0c571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443631265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.1443631265
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.3322884778
Short name T605
Test name
Test status
Simulation time 205292528 ps
CPU time 7.08 seconds
Started May 05 01:46:03 PM PDT 24
Finished May 05 01:46:11 PM PDT 24
Peak memory 251140 kb
Host smart-325c425b-1694-4b5a-a250-bb9611f84823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322884778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.3322884778
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3894117642
Short name T800
Test name
Test status
Simulation time 2738496310 ps
CPU time 125.08 seconds
Started May 05 01:45:49 PM PDT 24
Finished May 05 01:47:55 PM PDT 24
Peak memory 259332 kb
Host smart-cbc82626-c8c2-4186-8cb9-0450ca0756b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894117642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3894117642
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3698054565
Short name T721
Test name
Test status
Simulation time 12479891 ps
CPU time 0.99 seconds
Started May 05 01:46:03 PM PDT 24
Finished May 05 01:46:04 PM PDT 24
Peak memory 211796 kb
Host smart-9807dbe5-41e9-45f3-a9c4-d2635421b9c3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698054565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3698054565
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.2123663363
Short name T431
Test name
Test status
Simulation time 45349902 ps
CPU time 0.8 seconds
Started May 05 01:46:05 PM PDT 24
Finished May 05 01:46:07 PM PDT 24
Peak memory 209592 kb
Host smart-b756c6f9-d22d-4e55-9a46-e8c382ad453f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123663363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.2123663363
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1471040539
Short name T508
Test name
Test status
Simulation time 662908507 ps
CPU time 11.16 seconds
Started May 05 01:46:05 PM PDT 24
Finished May 05 01:46:17 PM PDT 24
Peak memory 218160 kb
Host smart-e9b6fd62-3124-4ab7-9f14-6ebd2a98af2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471040539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1471040539
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2392626981
Short name T238
Test name
Test status
Simulation time 10664218874 ps
CPU time 30.86 seconds
Started May 05 01:46:04 PM PDT 24
Finished May 05 01:46:36 PM PDT 24
Peak memory 218528 kb
Host smart-3ad5afe3-2997-437b-87e3-8f38103f1302
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392626981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2392626981
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.437674675
Short name T371
Test name
Test status
Simulation time 916534333 ps
CPU time 23.76 seconds
Started May 05 01:46:00 PM PDT 24
Finished May 05 01:46:24 PM PDT 24
Peak memory 218080 kb
Host smart-db385dc4-4937-487a-a2c1-6ebf9d8d3264
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437674675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.437674675
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1649116531
Short name T75
Test name
Test status
Simulation time 475923709 ps
CPU time 8.81 seconds
Started May 05 01:46:08 PM PDT 24
Finished May 05 01:46:18 PM PDT 24
Peak memory 213780 kb
Host smart-105ee606-722a-4ab2-94a8-78dbfc905395
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649116531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1649116531
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.320517928
Short name T627
Test name
Test status
Simulation time 3226311136 ps
CPU time 37.96 seconds
Started May 05 01:46:03 PM PDT 24
Finished May 05 01:46:42 PM PDT 24
Peak memory 251184 kb
Host smart-1a90d49f-2295-4be0-9966-841cf497a9f6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320517928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.320517928
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2851548721
Short name T320
Test name
Test status
Simulation time 2259488907 ps
CPU time 13.84 seconds
Started May 05 01:46:06 PM PDT 24
Finished May 05 01:46:20 PM PDT 24
Peak memory 251204 kb
Host smart-c3185342-868f-4a36-b2fd-aa2b0b0bd8f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851548721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2851548721
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2166531851
Short name T700
Test name
Test status
Simulation time 297563194 ps
CPU time 2.91 seconds
Started May 05 01:46:03 PM PDT 24
Finished May 05 01:46:06 PM PDT 24
Peak memory 218100 kb
Host smart-ab9413d6-6bd6-4212-891b-c4ad9c3fd157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166531851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2166531851
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.3937531350
Short name T19
Test name
Test status
Simulation time 12047565476 ps
CPU time 23.1 seconds
Started May 05 01:46:05 PM PDT 24
Finished May 05 01:46:29 PM PDT 24
Peak memory 219080 kb
Host smart-fc884955-aa1c-4843-8e72-1495a0ee2112
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937531350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3937531350
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.896834867
Short name T612
Test name
Test status
Simulation time 313601559 ps
CPU time 14.52 seconds
Started May 05 01:46:02 PM PDT 24
Finished May 05 01:46:17 PM PDT 24
Peak memory 218060 kb
Host smart-b146b012-a497-43fb-96dc-aa0015c860e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896834867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.896834867
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1902755117
Short name T474
Test name
Test status
Simulation time 612346845 ps
CPU time 11.44 seconds
Started May 05 01:46:04 PM PDT 24
Finished May 05 01:46:16 PM PDT 24
Peak memory 218120 kb
Host smart-4ef11a91-e873-4910-a78d-d73af501eb7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902755117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1902755117
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1360286886
Short name T613
Test name
Test status
Simulation time 517208344 ps
CPU time 6.09 seconds
Started May 05 01:46:03 PM PDT 24
Finished May 05 01:46:20 PM PDT 24
Peak memory 218124 kb
Host smart-26c3ff8c-339e-4e06-8aae-79675b89f845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360286886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1360286886
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3983127211
Short name T806
Test name
Test status
Simulation time 189262731 ps
CPU time 2.97 seconds
Started May 05 01:46:05 PM PDT 24
Finished May 05 01:46:09 PM PDT 24
Peak memory 214752 kb
Host smart-b234f83b-c3e5-496a-8535-fda70707b7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983127211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3983127211
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2366187374
Short name T695
Test name
Test status
Simulation time 1429948925 ps
CPU time 29.58 seconds
Started May 05 01:45:53 PM PDT 24
Finished May 05 01:46:23 PM PDT 24
Peak memory 251200 kb
Host smart-d81694f0-59e2-421b-b9f6-64763ebee0af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2366187374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2366187374
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1115692300
Short name T358
Test name
Test status
Simulation time 98887179 ps
CPU time 9.92 seconds
Started May 05 01:46:04 PM PDT 24
Finished May 05 01:46:15 PM PDT 24
Peak memory 251172 kb
Host smart-32648767-f040-4073-a9ab-9e4cdc8f2c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115692300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1115692300
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2233362804
Short name T654
Test name
Test status
Simulation time 3781146780 ps
CPU time 127.24 seconds
Started May 05 01:46:06 PM PDT 24
Finished May 05 01:48:14 PM PDT 24
Peak memory 274112 kb
Host smart-f36fc07f-ff4e-4b3d-b05a-032f49340a7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233362804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2233362804
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.2009921751
Short name T570
Test name
Test status
Simulation time 53497567061 ps
CPU time 478.54 seconds
Started May 05 01:46:03 PM PDT 24
Finished May 05 01:54:03 PM PDT 24
Peak memory 422280 kb
Host smart-705a7450-90ee-4106-bae8-bf9d32762840
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2009921751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.2009921751
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1478810691
Short name T813
Test name
Test status
Simulation time 11988281 ps
CPU time 0.86 seconds
Started May 05 01:45:56 PM PDT 24
Finished May 05 01:45:57 PM PDT 24
Peak memory 211728 kb
Host smart-50782a05-0364-4ce5-95bd-27c35da31b3d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478810691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1478810691
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3045681980
Short name T279
Test name
Test status
Simulation time 31608295 ps
CPU time 1.43 seconds
Started May 05 01:46:03 PM PDT 24
Finished May 05 01:46:06 PM PDT 24
Peak memory 209680 kb
Host smart-dbedb85b-632c-46f9-92ff-7ab597bc4c4a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045681980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3045681980
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.805037164
Short name T296
Test name
Test status
Simulation time 463321834 ps
CPU time 9.04 seconds
Started May 05 01:46:05 PM PDT 24
Finished May 05 01:46:15 PM PDT 24
Peak memory 218176 kb
Host smart-f6862fcd-00e0-4422-8998-380c5cad339e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805037164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.805037164
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1465154209
Short name T628
Test name
Test status
Simulation time 4572233281 ps
CPU time 16.72 seconds
Started May 05 01:46:07 PM PDT 24
Finished May 05 01:46:24 PM PDT 24
Peak memory 209732 kb
Host smart-20f5a14e-865e-4628-93d7-365d0bfa892d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465154209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1465154209
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2952509061
Short name T549
Test name
Test status
Simulation time 2430345775 ps
CPU time 69.34 seconds
Started May 05 01:46:08 PM PDT 24
Finished May 05 01:47:17 PM PDT 24
Peak memory 219120 kb
Host smart-6ec05fe0-f478-4bb0-a131-ba124fe8db31
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952509061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2952509061
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.100891413
Short name T696
Test name
Test status
Simulation time 1134937298 ps
CPU time 6.59 seconds
Started May 05 01:46:22 PM PDT 24
Finished May 05 01:46:29 PM PDT 24
Peak memory 217984 kb
Host smart-acb3653f-59f1-4fe3-922c-0545853c2c3a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100891413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.100891413
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2937833065
Short name T80
Test name
Test status
Simulation time 415270985 ps
CPU time 7.4 seconds
Started May 05 01:46:08 PM PDT 24
Finished May 05 01:46:16 PM PDT 24
Peak memory 213936 kb
Host smart-4556fe74-aa66-4d44-b8c6-eda3184d2141
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937833065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2937833065
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2061418230
Short name T289
Test name
Test status
Simulation time 4968815262 ps
CPU time 32.99 seconds
Started May 05 01:46:09 PM PDT 24
Finished May 05 01:46:43 PM PDT 24
Peak memory 269588 kb
Host smart-00527d54-51f6-4dd9-8190-683a03d637d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061418230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2061418230
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.786143103
Short name T606
Test name
Test status
Simulation time 2522923327 ps
CPU time 14.67 seconds
Started May 05 01:46:09 PM PDT 24
Finished May 05 01:46:24 PM PDT 24
Peak memory 251156 kb
Host smart-52f45417-63a6-4ea1-915e-7c8addae71c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786143103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_
jtag_state_post_trans.786143103
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2680692682
Short name T392
Test name
Test status
Simulation time 40882079 ps
CPU time 1.95 seconds
Started May 05 01:46:01 PM PDT 24
Finished May 05 01:46:04 PM PDT 24
Peak memory 218092 kb
Host smart-0fe63b66-2415-4da3-ba80-774fe230a4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680692682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2680692682
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.420513388
Short name T444
Test name
Test status
Simulation time 506402459 ps
CPU time 14.69 seconds
Started May 05 01:46:10 PM PDT 24
Finished May 05 01:46:25 PM PDT 24
Peak memory 219012 kb
Host smart-4a86782b-4c13-45a4-accb-7ee32a735064
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420513388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.420513388
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3694221620
Short name T331
Test name
Test status
Simulation time 308650830 ps
CPU time 12.62 seconds
Started May 05 01:46:03 PM PDT 24
Finished May 05 01:46:17 PM PDT 24
Peak memory 218080 kb
Host smart-014f1b5c-f8ed-468b-be1f-7903337b5c51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694221620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3694221620
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3201625221
Short name T237
Test name
Test status
Simulation time 216564499 ps
CPU time 8.83 seconds
Started May 05 01:46:04 PM PDT 24
Finished May 05 01:46:14 PM PDT 24
Peak memory 218188 kb
Host smart-d7d1be17-5075-450d-a75b-1b5fa031dffb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201625221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3201625221
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.822758147
Short name T717
Test name
Test status
Simulation time 110267204 ps
CPU time 1.98 seconds
Started May 05 01:45:58 PM PDT 24
Finished May 05 01:46:01 PM PDT 24
Peak memory 213976 kb
Host smart-500d7bea-83d8-44e5-ada4-6ed8303b7a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822758147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.822758147
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3985613674
Short name T648
Test name
Test status
Simulation time 462662047 ps
CPU time 26.55 seconds
Started May 05 01:46:03 PM PDT 24
Finished May 05 01:46:30 PM PDT 24
Peak memory 251036 kb
Host smart-33b656bf-1ed8-49fb-885d-899f9aeb0110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985613674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3985613674
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.4104837780
Short name T387
Test name
Test status
Simulation time 249865624 ps
CPU time 3.21 seconds
Started May 05 01:46:04 PM PDT 24
Finished May 05 01:46:08 PM PDT 24
Peak memory 222332 kb
Host smart-6a41d8a5-fd7e-4f69-b931-15fe8d64a067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104837780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.4104837780
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3457388916
Short name T733
Test name
Test status
Simulation time 2436713601 ps
CPU time 61.44 seconds
Started May 05 01:46:21 PM PDT 24
Finished May 05 01:47:23 PM PDT 24
Peak memory 277408 kb
Host smart-1a2d7183-7849-41ae-a48a-fd6f3af64af1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457388916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3457388916
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.1948038128
Short name T85
Test name
Test status
Simulation time 86347155182 ps
CPU time 546.24 seconds
Started May 05 01:46:04 PM PDT 24
Finished May 05 01:55:12 PM PDT 24
Peak memory 283976 kb
Host smart-e49d60c6-5183-456c-add6-805054c8f5b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1948038128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.1948038128
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.302577481
Short name T461
Test name
Test status
Simulation time 123307987 ps
CPU time 0.92 seconds
Started May 05 01:46:07 PM PDT 24
Finished May 05 01:46:08 PM PDT 24
Peak memory 212792 kb
Host smart-9351c88b-544c-4639-b0fa-5d85fbfc2c39
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302577481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.302577481
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2070297734
Short name T839
Test name
Test status
Simulation time 414068170 ps
CPU time 1.56 seconds
Started May 05 01:46:11 PM PDT 24
Finished May 05 01:46:13 PM PDT 24
Peak memory 209648 kb
Host smart-3b73c10d-3784-45cd-8846-f6edbeed5e0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070297734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2070297734
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.2612817188
Short name T705
Test name
Test status
Simulation time 550092571 ps
CPU time 9.45 seconds
Started May 05 01:46:06 PM PDT 24
Finished May 05 01:46:16 PM PDT 24
Peak memory 218128 kb
Host smart-920ca4c7-7de1-4160-84c8-71a47e475dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612817188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.2612817188
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1392024958
Short name T33
Test name
Test status
Simulation time 3230802032 ps
CPU time 8.6 seconds
Started May 05 01:46:11 PM PDT 24
Finished May 05 01:46:20 PM PDT 24
Peak memory 209632 kb
Host smart-62cdd7fa-7ef9-4a19-b597-b49209843972
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392024958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1392024958
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3551756897
Short name T246
Test name
Test status
Simulation time 5083237104 ps
CPU time 19.51 seconds
Started May 05 01:46:10 PM PDT 24
Finished May 05 01:46:30 PM PDT 24
Peak memory 218544 kb
Host smart-6c216f9a-83cc-4fa0-901f-abe0668bbc2f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551756897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3551756897
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.2942567978
Short name T579
Test name
Test status
Simulation time 455363316 ps
CPU time 4.22 seconds
Started May 05 01:46:07 PM PDT 24
Finished May 05 01:46:11 PM PDT 24
Peak memory 218104 kb
Host smart-28668bf3-b799-4422-b0a3-c02aeb465dba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942567978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.2942567978
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3274068288
Short name T314
Test name
Test status
Simulation time 305070664 ps
CPU time 5.38 seconds
Started May 05 01:46:04 PM PDT 24
Finished May 05 01:46:11 PM PDT 24
Peak memory 214020 kb
Host smart-049b41bf-1803-4369-aa43-ccc39851aa9a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274068288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3274068288
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.489098938
Short name T380
Test name
Test status
Simulation time 14804885954 ps
CPU time 66.48 seconds
Started May 05 01:46:10 PM PDT 24
Finished May 05 01:47:17 PM PDT 24
Peak memory 273192 kb
Host smart-b135d776-8678-4b54-8455-5d09136417f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489098938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.489098938
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3520263238
Short name T663
Test name
Test status
Simulation time 1686740737 ps
CPU time 16.36 seconds
Started May 05 01:46:08 PM PDT 24
Finished May 05 01:46:25 PM PDT 24
Peak memory 251120 kb
Host smart-b5e005f6-76ff-4808-a317-996b21762665
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520263238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3520263238
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.577695434
Short name T571
Test name
Test status
Simulation time 62187748 ps
CPU time 2.65 seconds
Started May 05 01:46:05 PM PDT 24
Finished May 05 01:46:08 PM PDT 24
Peak memory 218324 kb
Host smart-4ef1a46a-837f-4fe6-a1de-ff928d3062f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577695434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.577695434
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.4043941149
Short name T350
Test name
Test status
Simulation time 811293785 ps
CPU time 10.13 seconds
Started May 05 01:46:10 PM PDT 24
Finished May 05 01:46:21 PM PDT 24
Peak memory 218128 kb
Host smart-1f79b843-9149-4359-8966-efa1544c42aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043941149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.4043941149
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1207937490
Short name T243
Test name
Test status
Simulation time 982230808 ps
CPU time 8.27 seconds
Started May 05 01:46:24 PM PDT 24
Finished May 05 01:46:32 PM PDT 24
Peak memory 218112 kb
Host smart-c9ece131-ca07-4e2e-8480-4bfcc6886a51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207937490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1207937490
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1963972137
Short name T150
Test name
Test status
Simulation time 655210514 ps
CPU time 7.01 seconds
Started May 05 01:46:12 PM PDT 24
Finished May 05 01:46:19 PM PDT 24
Peak memory 218092 kb
Host smart-9b805146-85b6-453d-a7e1-6ae1dbf52082
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963972137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
1963972137
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2797761606
Short name T808
Test name
Test status
Simulation time 383711347 ps
CPU time 8.76 seconds
Started May 05 01:46:11 PM PDT 24
Finished May 05 01:46:20 PM PDT 24
Peak memory 218176 kb
Host smart-6874ef28-fe26-4899-bc8f-e3197772f977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797761606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2797761606
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1174121328
Short name T64
Test name
Test status
Simulation time 30365886 ps
CPU time 1.9 seconds
Started May 05 01:46:12 PM PDT 24
Finished May 05 01:46:14 PM PDT 24
Peak memory 213860 kb
Host smart-67327e68-a3b9-4a55-9778-4a4c79091324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174121328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1174121328
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.582486513
Short name T22
Test name
Test status
Simulation time 835115511 ps
CPU time 24.59 seconds
Started May 05 01:46:07 PM PDT 24
Finished May 05 01:46:37 PM PDT 24
Peak memory 251084 kb
Host smart-7a0b0900-7104-433f-95c6-539e2f5e4b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582486513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.582486513
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3143105551
Short name T858
Test name
Test status
Simulation time 281147489 ps
CPU time 2.75 seconds
Started May 05 01:46:08 PM PDT 24
Finished May 05 01:46:12 PM PDT 24
Peak memory 218036 kb
Host smart-c78ba572-b6df-4066-b0af-294e8910be21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143105551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3143105551
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.4293872221
Short name T242
Test name
Test status
Simulation time 9445948869 ps
CPU time 67.43 seconds
Started May 05 01:46:08 PM PDT 24
Finished May 05 01:47:16 PM PDT 24
Peak memory 276436 kb
Host smart-3c0271b8-d504-4322-a5e8-fedfc0a740df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293872221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.4293872221
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.658417239
Short name T430
Test name
Test status
Simulation time 13220650 ps
CPU time 0.91 seconds
Started May 05 01:46:16 PM PDT 24
Finished May 05 01:46:17 PM PDT 24
Peak memory 213060 kb
Host smart-595f83c1-da3c-47c0-b2a8-940c579cd5e5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658417239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.658417239
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.2921708058
Short name T209
Test name
Test status
Simulation time 26400696 ps
CPU time 1.27 seconds
Started May 05 01:46:09 PM PDT 24
Finished May 05 01:46:11 PM PDT 24
Peak memory 209720 kb
Host smart-06ad5687-5432-4eb3-a1df-cc27b070b38b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921708058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.2921708058
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3141731142
Short name T448
Test name
Test status
Simulation time 705523471 ps
CPU time 9.21 seconds
Started May 05 01:46:13 PM PDT 24
Finished May 05 01:46:23 PM PDT 24
Peak memory 218072 kb
Host smart-176afe3e-40bf-4ec8-a598-1b3dfef333fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141731142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3141731142
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2561894794
Short name T532
Test name
Test status
Simulation time 109316228 ps
CPU time 2.1 seconds
Started May 05 01:46:16 PM PDT 24
Finished May 05 01:46:19 PM PDT 24
Peak memory 209748 kb
Host smart-d3923199-b5b3-4b50-86c1-a44478d24c50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561894794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2561894794
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.4152609419
Short name T270
Test name
Test status
Simulation time 1882706654 ps
CPU time 26.4 seconds
Started May 05 01:46:12 PM PDT 24
Finished May 05 01:46:39 PM PDT 24
Peak memory 218160 kb
Host smart-81972ed0-5d76-47ea-b000-48b83fd2cc80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152609419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.4152609419
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2786292960
Short name T729
Test name
Test status
Simulation time 400949280 ps
CPU time 6.69 seconds
Started May 05 01:46:14 PM PDT 24
Finished May 05 01:46:22 PM PDT 24
Peak memory 218172 kb
Host smart-6ee5a115-73f9-4129-8d7d-90b6ed4de7a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786292960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2786292960
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.40735899
Short name T568
Test name
Test status
Simulation time 749030576 ps
CPU time 5.26 seconds
Started May 05 01:46:13 PM PDT 24
Finished May 05 01:46:19 PM PDT 24
Peak memory 213624 kb
Host smart-2a8a0985-5eca-4a9a-88cf-6d7fce244af8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40735899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.40735899
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3974990416
Short name T702
Test name
Test status
Simulation time 11916860147 ps
CPU time 73.19 seconds
Started May 05 01:46:28 PM PDT 24
Finished May 05 01:47:42 PM PDT 24
Peak memory 274416 kb
Host smart-5b6bb9d8-97f0-43da-b5ef-5563822c3ac4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974990416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3974990416
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.4170581031
Short name T655
Test name
Test status
Simulation time 1232170586 ps
CPU time 10.72 seconds
Started May 05 01:46:11 PM PDT 24
Finished May 05 01:46:23 PM PDT 24
Peak memory 251152 kb
Host smart-58376bc0-5a97-409b-be2d-2b57717c1d44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170581031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.4170581031
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.4151316379
Short name T844
Test name
Test status
Simulation time 51465871 ps
CPU time 3.02 seconds
Started May 05 01:46:08 PM PDT 24
Finished May 05 01:46:11 PM PDT 24
Peak memory 218072 kb
Host smart-6c58552b-021a-46c3-8ae5-3e9645858843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151316379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.4151316379
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1505063659
Short name T40
Test name
Test status
Simulation time 434511147 ps
CPU time 11.35 seconds
Started May 05 01:46:13 PM PDT 24
Finished May 05 01:46:25 PM PDT 24
Peak memory 218076 kb
Host smart-7368e4e2-2316-40a1-a627-4fe895adf4bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505063659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1505063659
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1567168308
Short name T499
Test name
Test status
Simulation time 533075840 ps
CPU time 10.76 seconds
Started May 05 01:46:20 PM PDT 24
Finished May 05 01:46:32 PM PDT 24
Peak memory 218224 kb
Host smart-8f6efe83-50a4-4b37-b73e-a3ea5abe2719
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567168308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
1567168308
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.652203440
Short name T841
Test name
Test status
Simulation time 256216635 ps
CPU time 7.3 seconds
Started May 05 01:46:10 PM PDT 24
Finished May 05 01:46:18 PM PDT 24
Peak memory 224672 kb
Host smart-925e27ec-a88d-4202-90d1-e228b0b6af04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=652203440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.652203440
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1082838418
Short name T694
Test name
Test status
Simulation time 31070880 ps
CPU time 2.51 seconds
Started May 05 01:46:09 PM PDT 24
Finished May 05 01:46:12 PM PDT 24
Peak memory 214648 kb
Host smart-f6b75693-47b4-4ae9-bebd-d17ef71ecb6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082838418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1082838418
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1829613408
Short name T845
Test name
Test status
Simulation time 399110230 ps
CPU time 23.76 seconds
Started May 05 01:46:16 PM PDT 24
Finished May 05 01:46:41 PM PDT 24
Peak memory 251160 kb
Host smart-69a6e9d2-e582-4060-92a3-181e3f5563b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829613408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1829613408
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3654325218
Short name T867
Test name
Test status
Simulation time 120179965 ps
CPU time 7.25 seconds
Started May 05 01:46:08 PM PDT 24
Finished May 05 01:46:16 PM PDT 24
Peak memory 250644 kb
Host smart-7a6194b7-9d1f-40d1-ad90-a2873718481f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654325218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3654325218
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2199735570
Short name T485
Test name
Test status
Simulation time 14093394775 ps
CPU time 144.64 seconds
Started May 05 01:46:21 PM PDT 24
Finished May 05 01:48:46 PM PDT 24
Peak memory 283920 kb
Host smart-30cefc48-418f-4277-8bc3-8bed9b2bfc19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199735570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2199735570
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.443981564
Short name T357
Test name
Test status
Simulation time 118691653 ps
CPU time 0.94 seconds
Started May 05 01:46:11 PM PDT 24
Finished May 05 01:46:13 PM PDT 24
Peak memory 211736 kb
Host smart-b3718f18-32ce-49a2-b61e-0c290c0eed5e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443981564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.443981564
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3034597061
Short name T206
Test name
Test status
Simulation time 38191677 ps
CPU time 0.95 seconds
Started May 05 01:46:14 PM PDT 24
Finished May 05 01:46:16 PM PDT 24
Peak memory 209600 kb
Host smart-4e2a819e-a39a-46cb-88c2-a170bc7e97d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034597061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3034597061
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.786475060
Short name T252
Test name
Test status
Simulation time 357060542 ps
CPU time 11.2 seconds
Started May 05 01:46:19 PM PDT 24
Finished May 05 01:46:31 PM PDT 24
Peak memory 218068 kb
Host smart-945addd1-10fd-444d-85c8-6275920c980c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786475060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.786475060
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3129970797
Short name T11
Test name
Test status
Simulation time 606383994 ps
CPU time 4.73 seconds
Started May 05 01:46:14 PM PDT 24
Finished May 05 01:46:19 PM PDT 24
Peak memory 209692 kb
Host smart-9eb4ffb8-0e57-41ca-9e18-60e74f34fa33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129970797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3129970797
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2650563275
Short name T317
Test name
Test status
Simulation time 4010984496 ps
CPU time 54.02 seconds
Started May 05 01:46:27 PM PDT 24
Finished May 05 01:47:21 PM PDT 24
Peak memory 219136 kb
Host smart-0488df8b-4641-4b4b-9f0a-1405d8a819c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650563275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2650563275
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2460426315
Short name T735
Test name
Test status
Simulation time 614564925 ps
CPU time 2.84 seconds
Started May 05 01:46:17 PM PDT 24
Finished May 05 01:46:20 PM PDT 24
Peak memory 218096 kb
Host smart-ff7e7a3d-5c07-463c-a7d7-91e9f58be823
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460426315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2460426315
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2863621268
Short name T843
Test name
Test status
Simulation time 681145794 ps
CPU time 16.35 seconds
Started May 05 01:46:13 PM PDT 24
Finished May 05 01:46:29 PM PDT 24
Peak memory 213656 kb
Host smart-2c1783a4-7985-4e77-a438-091539f8016a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863621268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2863621268
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.123941438
Short name T520
Test name
Test status
Simulation time 5015416649 ps
CPU time 27.77 seconds
Started May 05 01:46:09 PM PDT 24
Finished May 05 01:46:37 PM PDT 24
Peak memory 251228 kb
Host smart-cff8a3ce-91af-4894-b8ba-be44df29c6c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123941438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_state_failure.123941438
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3800258220
Short name T351
Test name
Test status
Simulation time 3555293858 ps
CPU time 16.22 seconds
Started May 05 01:46:08 PM PDT 24
Finished May 05 01:46:25 PM PDT 24
Peak memory 250800 kb
Host smart-907e353d-4018-45c8-8190-ea87b96fcbdc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800258220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3800258220
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.1150162454
Short name T345
Test name
Test status
Simulation time 77054324 ps
CPU time 1.53 seconds
Started May 05 01:46:10 PM PDT 24
Finished May 05 01:46:12 PM PDT 24
Peak memory 218172 kb
Host smart-4b092c11-60eb-45c9-94a4-3e42c648266b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150162454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1150162454
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2812215046
Short name T671
Test name
Test status
Simulation time 798631769 ps
CPU time 22.17 seconds
Started May 05 01:46:13 PM PDT 24
Finished May 05 01:46:35 PM PDT 24
Peak memory 226228 kb
Host smart-063c6718-bfd5-437a-bc3e-5b34211d7b21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812215046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2812215046
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.2767034302
Short name T811
Test name
Test status
Simulation time 918871668 ps
CPU time 7.5 seconds
Started May 05 01:46:11 PM PDT 24
Finished May 05 01:46:19 PM PDT 24
Peak memory 218068 kb
Host smart-daebb3c1-4d01-43aa-b52b-307c13c53d96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767034302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.2767034302
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1485665838
Short name T582
Test name
Test status
Simulation time 3206007953 ps
CPU time 12.12 seconds
Started May 05 01:46:14 PM PDT 24
Finished May 05 01:46:27 PM PDT 24
Peak memory 218188 kb
Host smart-9d96635f-932b-4a04-9e8d-b1f7d8cd2800
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485665838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1485665838
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2361975452
Short name T842
Test name
Test status
Simulation time 1443986114 ps
CPU time 8.94 seconds
Started May 05 01:46:15 PM PDT 24
Finished May 05 01:46:25 PM PDT 24
Peak memory 218248 kb
Host smart-1fed46e0-03ce-4966-882b-2a0c81b469a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361975452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2361975452
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2894916709
Short name T327
Test name
Test status
Simulation time 98624180 ps
CPU time 1.93 seconds
Started May 05 01:46:15 PM PDT 24
Finished May 05 01:46:18 PM PDT 24
Peak memory 218048 kb
Host smart-a170d470-edc3-42ab-867b-8664fc3043dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894916709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2894916709
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.20169091
Short name T869
Test name
Test status
Simulation time 889059873 ps
CPU time 19.13 seconds
Started May 05 01:46:13 PM PDT 24
Finished May 05 01:46:32 PM PDT 24
Peak memory 250740 kb
Host smart-1ca2415f-715e-4b1a-8427-4753757ddabd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20169091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.20169091
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1084853729
Short name T619
Test name
Test status
Simulation time 116311349 ps
CPU time 7.67 seconds
Started May 05 01:46:28 PM PDT 24
Finished May 05 01:46:36 PM PDT 24
Peak memory 246136 kb
Host smart-70786e63-5228-40a4-9c73-388a4185dfe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084853729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1084853729
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.4133790944
Short name T452
Test name
Test status
Simulation time 1073576248 ps
CPU time 37.88 seconds
Started May 05 01:46:22 PM PDT 24
Finished May 05 01:47:01 PM PDT 24
Peak memory 248604 kb
Host smart-b0ca457c-7ce3-4ac1-a084-3a59e85cb05f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133790944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.4133790944
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.245071313
Short name T580
Test name
Test status
Simulation time 20914338 ps
CPU time 0.92 seconds
Started May 05 01:46:16 PM PDT 24
Finished May 05 01:46:17 PM PDT 24
Peak memory 211724 kb
Host smart-76add1b8-29a0-42c9-af27-838e897d8e76
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245071313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.245071313
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3154887258
Short name T230
Test name
Test status
Simulation time 20917449 ps
CPU time 1.03 seconds
Started May 05 01:46:13 PM PDT 24
Finished May 05 01:46:15 PM PDT 24
Peak memory 209652 kb
Host smart-103b742e-36e1-47e6-9ae1-23262a629cb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154887258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3154887258
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2430466218
Short name T240
Test name
Test status
Simulation time 1082829758 ps
CPU time 13.03 seconds
Started May 05 01:46:12 PM PDT 24
Finished May 05 01:46:26 PM PDT 24
Peak memory 218092 kb
Host smart-c8f6844c-2bcc-4bb8-ad3b-4cbd80f512aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430466218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2430466218
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2930844765
Short name T482
Test name
Test status
Simulation time 3053427505 ps
CPU time 8.75 seconds
Started May 05 01:46:12 PM PDT 24
Finished May 05 01:46:21 PM PDT 24
Peak memory 209836 kb
Host smart-cc03dba7-5fd9-47c5-a5d8-1fb810c4ca76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930844765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2930844765
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1350298916
Short name T151
Test name
Test status
Simulation time 5974433735 ps
CPU time 30.05 seconds
Started May 05 01:46:24 PM PDT 24
Finished May 05 01:46:55 PM PDT 24
Peak memory 218672 kb
Host smart-02ae1b2e-f515-428f-b32f-bdad2ba9d1fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350298916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1350298916
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3048213586
Short name T412
Test name
Test status
Simulation time 894228527 ps
CPU time 1.99 seconds
Started May 05 01:46:13 PM PDT 24
Finished May 05 01:46:16 PM PDT 24
Peak memory 218064 kb
Host smart-605643ed-7d83-4357-a2e3-bf7c5179eccf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048213586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.3048213586
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3827934527
Short name T337
Test name
Test status
Simulation time 1972756948 ps
CPU time 11.4 seconds
Started May 05 01:46:15 PM PDT 24
Finished May 05 01:46:26 PM PDT 24
Peak memory 213912 kb
Host smart-0bc71225-21f0-432e-b906-ef0697024b79
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827934527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3827934527
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3822155150
Short name T665
Test name
Test status
Simulation time 3126425498 ps
CPU time 70.98 seconds
Started May 05 01:46:19 PM PDT 24
Finished May 05 01:47:30 PM PDT 24
Peak memory 283944 kb
Host smart-25ab429a-b401-4295-9c01-42c13cbcc88c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822155150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3822155150
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.2376980378
Short name T796
Test name
Test status
Simulation time 1845083403 ps
CPU time 8.67 seconds
Started May 05 01:46:15 PM PDT 24
Finished May 05 01:46:25 PM PDT 24
Peak memory 222864 kb
Host smart-a9ae81e9-9eb2-4a79-a8ad-2dd58d41db00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376980378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.2376980378
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3623351898
Short name T395
Test name
Test status
Simulation time 253725877 ps
CPU time 3.15 seconds
Started May 05 01:46:14 PM PDT 24
Finished May 05 01:46:17 PM PDT 24
Peak memory 218328 kb
Host smart-52734d04-a857-496b-a255-e52777b8b637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623351898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3623351898
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.2444286789
Short name T614
Test name
Test status
Simulation time 231400070 ps
CPU time 11.84 seconds
Started May 05 01:46:33 PM PDT 24
Finished May 05 01:46:46 PM PDT 24
Peak memory 226232 kb
Host smart-acef71fa-4a20-4d85-9057-a761eed3bcd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444286789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2444286789
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.389982587
Short name T758
Test name
Test status
Simulation time 656753526 ps
CPU time 12.64 seconds
Started May 05 01:46:14 PM PDT 24
Finished May 05 01:46:27 PM PDT 24
Peak memory 218156 kb
Host smart-44545349-088c-4a10-a0bb-b606b570ee7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389982587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_di
gest.389982587
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1427980337
Short name T862
Test name
Test status
Simulation time 180146885 ps
CPU time 7.07 seconds
Started May 05 01:46:27 PM PDT 24
Finished May 05 01:46:34 PM PDT 24
Peak memory 218184 kb
Host smart-8072de37-f5d4-4bf1-b09d-56d7d5e0ebab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427980337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1427980337
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.763937020
Short name T378
Test name
Test status
Simulation time 262461325 ps
CPU time 11.41 seconds
Started May 05 01:46:29 PM PDT 24
Finished May 05 01:46:41 PM PDT 24
Peak memory 218164 kb
Host smart-8ec78a49-b5d2-47dc-b2e3-80bb2860bcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763937020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.763937020
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1589022280
Short name T425
Test name
Test status
Simulation time 35683485 ps
CPU time 2.67 seconds
Started May 05 01:46:16 PM PDT 24
Finished May 05 01:46:19 PM PDT 24
Peak memory 214404 kb
Host smart-e71d74b2-dcd7-49c7-8fdb-e050cc56cce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589022280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1589022280
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3285357354
Short name T805
Test name
Test status
Simulation time 370861398 ps
CPU time 28.02 seconds
Started May 05 01:46:12 PM PDT 24
Finished May 05 01:46:41 PM PDT 24
Peak memory 249216 kb
Host smart-3927095a-9e89-4cd6-b065-d4fc31167797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285357354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3285357354
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2645624368
Short name T488
Test name
Test status
Simulation time 378546971 ps
CPU time 4.24 seconds
Started May 05 01:46:17 PM PDT 24
Finished May 05 01:46:21 PM PDT 24
Peak memory 226584 kb
Host smart-a163dfd9-494f-4769-9d2a-867e74453f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645624368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2645624368
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.285820798
Short name T872
Test name
Test status
Simulation time 12661506036 ps
CPU time 87.69 seconds
Started May 05 01:46:27 PM PDT 24
Finished May 05 01:47:55 PM PDT 24
Peak memory 267636 kb
Host smart-92c802b0-4d63-46cc-91f9-f1f6c2166692
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285820798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.285820798
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.4190118369
Short name T328
Test name
Test status
Simulation time 14477939 ps
CPU time 1.08 seconds
Started May 05 01:46:12 PM PDT 24
Finished May 05 01:46:14 PM PDT 24
Peak memory 211704 kb
Host smart-23355408-a450-41ee-955c-33ef71bcb69c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190118369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.4190118369
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2581346868
Short name T686
Test name
Test status
Simulation time 19461180 ps
CPU time 0.97 seconds
Started May 05 01:45:30 PM PDT 24
Finished May 05 01:45:32 PM PDT 24
Peak memory 209644 kb
Host smart-8da6e3a8-2b6f-48e9-977b-eebe4c09dc94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581346868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2581346868
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2267864861
Short name T573
Test name
Test status
Simulation time 32849775 ps
CPU time 0.78 seconds
Started May 05 01:45:39 PM PDT 24
Finished May 05 01:45:41 PM PDT 24
Peak memory 209432 kb
Host smart-280c81ba-18cf-4745-98f0-0d439457fd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267864861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2267864861
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2895612508
Short name T52
Test name
Test status
Simulation time 969471077 ps
CPU time 11.8 seconds
Started May 05 01:45:41 PM PDT 24
Finished May 05 01:45:55 PM PDT 24
Peak memory 218096 kb
Host smart-7cf1e299-9a3b-4bb9-8369-34608da5c6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895612508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2895612508
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2612980190
Short name T34
Test name
Test status
Simulation time 89306302 ps
CPU time 1.62 seconds
Started May 05 01:45:29 PM PDT 24
Finished May 05 01:45:31 PM PDT 24
Peak memory 216992 kb
Host smart-f9214d69-f366-4602-9a25-7dd37c6380e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612980190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2612980190
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1009127723
Short name T558
Test name
Test status
Simulation time 5195667719 ps
CPU time 26.14 seconds
Started May 05 01:45:42 PM PDT 24
Finished May 05 01:46:10 PM PDT 24
Peak memory 218760 kb
Host smart-93324cd4-4b78-4710-acd2-72425f67fe86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009127723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1009127723
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2225949365
Short name T363
Test name
Test status
Simulation time 1482930792 ps
CPU time 4.17 seconds
Started May 05 01:45:32 PM PDT 24
Finished May 05 01:45:36 PM PDT 24
Peak memory 217464 kb
Host smart-f6455d58-6ec7-4f22-bc76-87d8ae7eb7bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225949365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
225949365
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2231817079
Short name T192
Test name
Test status
Simulation time 463137687 ps
CPU time 12.19 seconds
Started May 05 01:45:44 PM PDT 24
Finished May 05 01:45:58 PM PDT 24
Peak memory 218080 kb
Host smart-0351f2ab-af85-4555-bb88-d4bc841707aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231817079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2231817079
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1831334585
Short name T622
Test name
Test status
Simulation time 1051457079 ps
CPU time 16.56 seconds
Started May 05 01:45:30 PM PDT 24
Finished May 05 01:45:47 PM PDT 24
Peak memory 213516 kb
Host smart-c11b0f25-257d-472d-adfb-cbee9eb19661
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831334585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1831334585
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2153162108
Short name T541
Test name
Test status
Simulation time 116649567 ps
CPU time 2.44 seconds
Started May 05 01:45:31 PM PDT 24
Finished May 05 01:45:34 PM PDT 24
Peak memory 213232 kb
Host smart-b876129a-afdf-4f46-b28e-2b6c59946843
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153162108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2153162108
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.184988956
Short name T687
Test name
Test status
Simulation time 1496887540 ps
CPU time 56.59 seconds
Started May 05 01:45:22 PM PDT 24
Finished May 05 01:46:19 PM PDT 24
Peak memory 251052 kb
Host smart-a749072d-89d6-4075-ac1a-002a8fee4cd0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184988956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.184988956
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3259704796
Short name T239
Test name
Test status
Simulation time 751153877 ps
CPU time 16.54 seconds
Started May 05 01:45:41 PM PDT 24
Finished May 05 01:45:59 PM PDT 24
Peak memory 217932 kb
Host smart-6cf5b6b4-38a7-425e-84c9-f3c75859324d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259704796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3259704796
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.4065019147
Short name T247
Test name
Test status
Simulation time 106479362 ps
CPU time 2.81 seconds
Started May 05 01:45:31 PM PDT 24
Finished May 05 01:45:34 PM PDT 24
Peak memory 218088 kb
Host smart-0ae5ba43-1638-4d5b-b303-12b08cb2337b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065019147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.4065019147
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1366382842
Short name T77
Test name
Test status
Simulation time 4138891397 ps
CPU time 8.76 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:45:54 PM PDT 24
Peak memory 217948 kb
Host smart-64d13b43-5ecf-48a5-ba81-96fcdcc290d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366382842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1366382842
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.137972737
Short name T74
Test name
Test status
Simulation time 619531390 ps
CPU time 23.72 seconds
Started May 05 01:45:24 PM PDT 24
Finished May 05 01:45:48 PM PDT 24
Peak memory 269500 kb
Host smart-613142ce-ba48-40c2-b5dc-6c52921ce6be
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137972737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.137972737
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.1571051858
Short name T821
Test name
Test status
Simulation time 730833209 ps
CPU time 7.67 seconds
Started May 05 01:45:29 PM PDT 24
Finished May 05 01:45:37 PM PDT 24
Peak memory 218100 kb
Host smart-d7d4aa18-cb0f-4544-a930-b2168ce3ea58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571051858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.1571051858
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2976887646
Short name T349
Test name
Test status
Simulation time 1342051833 ps
CPU time 13.19 seconds
Started May 05 01:45:31 PM PDT 24
Finished May 05 01:45:45 PM PDT 24
Peak memory 218080 kb
Host smart-cf4096c0-208b-4bee-b600-9c0538866a8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976887646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2976887646
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1796437979
Short name T362
Test name
Test status
Simulation time 392597178 ps
CPU time 9.6 seconds
Started May 05 01:45:29 PM PDT 24
Finished May 05 01:45:39 PM PDT 24
Peak memory 218160 kb
Host smart-a872c1d5-efba-457d-aa86-3f5fb5eafff2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796437979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
796437979
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1979379852
Short name T772
Test name
Test status
Simulation time 375147063 ps
CPU time 9.51 seconds
Started May 05 01:45:29 PM PDT 24
Finished May 05 01:45:39 PM PDT 24
Peak memory 218220 kb
Host smart-2d50bbd9-5aba-4038-8206-18e77d094c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979379852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1979379852
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1238342528
Short name T188
Test name
Test status
Simulation time 50517919 ps
CPU time 1.13 seconds
Started May 05 01:45:40 PM PDT 24
Finished May 05 01:45:43 PM PDT 24
Peak memory 212988 kb
Host smart-727cce98-e1b4-4f11-89d0-c0374e6787eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238342528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1238342528
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1020190544
Short name T647
Test name
Test status
Simulation time 585747792 ps
CPU time 26.88 seconds
Started May 05 01:45:24 PM PDT 24
Finished May 05 01:45:51 PM PDT 24
Peak memory 251144 kb
Host smart-b142b07d-07eb-452d-8539-d6ba5c4da44e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020190544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1020190544
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2419602787
Short name T370
Test name
Test status
Simulation time 71562756 ps
CPU time 7.92 seconds
Started May 05 01:45:29 PM PDT 24
Finished May 05 01:45:38 PM PDT 24
Peak memory 250748 kb
Host smart-3d526fe6-280a-47ba-9453-2039135b8cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419602787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2419602787
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1423232414
Short name T669
Test name
Test status
Simulation time 10394132144 ps
CPU time 180.82 seconds
Started May 05 01:45:42 PM PDT 24
Finished May 05 01:48:44 PM PDT 24
Peak memory 222088 kb
Host smart-8cea5db1-6ff3-4720-8391-7791dc12e746
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423232414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1423232414
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.2942544899
Short name T797
Test name
Test status
Simulation time 15628349 ps
CPU time 0.93 seconds
Started May 05 01:45:24 PM PDT 24
Finished May 05 01:45:25 PM PDT 24
Peak memory 211744 kb
Host smart-5d0bc22d-07de-47fb-b2af-e47b614d67d3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942544899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.2942544899
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2835543030
Short name T72
Test name
Test status
Simulation time 38308510 ps
CPU time 1.25 seconds
Started May 05 01:46:22 PM PDT 24
Finished May 05 01:46:24 PM PDT 24
Peak memory 209644 kb
Host smart-e187d2fd-f5fe-4b92-98d7-a43924c75328
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835543030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2835543030
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1232746613
Short name T227
Test name
Test status
Simulation time 1319832684 ps
CPU time 16.05 seconds
Started May 05 01:46:15 PM PDT 24
Finished May 05 01:46:32 PM PDT 24
Peak memory 218000 kb
Host smart-a6eedffc-61cf-4924-8ec3-ae1408e133c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232746613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1232746613
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.1084085943
Short name T36
Test name
Test status
Simulation time 1192436117 ps
CPU time 7.84 seconds
Started May 05 01:46:25 PM PDT 24
Finished May 05 01:46:33 PM PDT 24
Peak memory 209732 kb
Host smart-57e77573-9e12-432e-aedd-784b331543f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084085943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1084085943
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1084988470
Short name T745
Test name
Test status
Simulation time 17880433 ps
CPU time 1.47 seconds
Started May 05 01:46:18 PM PDT 24
Finished May 05 01:46:20 PM PDT 24
Peak memory 218124 kb
Host smart-e713f526-cf16-4f6a-9b15-c7c9edfd1cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084988470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1084988470
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.75530203
Short name T17
Test name
Test status
Simulation time 357074491 ps
CPU time 9.7 seconds
Started May 05 01:46:35 PM PDT 24
Finished May 05 01:46:45 PM PDT 24
Peak memory 225784 kb
Host smart-93ca624a-f7ef-4964-a2e4-17be9e9453fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75530203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.75530203
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.927272430
Short name T835
Test name
Test status
Simulation time 470348930 ps
CPU time 16.22 seconds
Started May 05 01:46:27 PM PDT 24
Finished May 05 01:46:43 PM PDT 24
Peak memory 218108 kb
Host smart-9af5fde4-6c81-4686-9a4b-8be759129ec0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927272430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.927272430
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2516528508
Short name T403
Test name
Test status
Simulation time 178215308 ps
CPU time 6.97 seconds
Started May 05 01:46:28 PM PDT 24
Finished May 05 01:46:36 PM PDT 24
Peak memory 218204 kb
Host smart-7f9396da-8c89-4cc9-b046-f0e82c8c01f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516528508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2516528508
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3903325768
Short name T829
Test name
Test status
Simulation time 726308900 ps
CPU time 12.72 seconds
Started May 05 01:46:19 PM PDT 24
Finished May 05 01:46:32 PM PDT 24
Peak memory 218136 kb
Host smart-31b452f1-5096-4329-8b40-278865d717ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903325768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3903325768
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1599029237
Short name T63
Test name
Test status
Simulation time 48615002 ps
CPU time 3.29 seconds
Started May 05 01:46:15 PM PDT 24
Finished May 05 01:46:19 PM PDT 24
Peak memory 217928 kb
Host smart-4fc783c2-6a8c-4b99-ac43-728ff4cd3e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599029237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1599029237
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.79820330
Short name T277
Test name
Test status
Simulation time 151247631 ps
CPU time 16.89 seconds
Started May 05 01:46:19 PM PDT 24
Finished May 05 01:46:36 PM PDT 24
Peak memory 251032 kb
Host smart-ed559355-b138-4565-829b-96aa4548a537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79820330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.79820330
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2300214585
Short name T682
Test name
Test status
Simulation time 158006537 ps
CPU time 4.69 seconds
Started May 05 01:46:23 PM PDT 24
Finished May 05 01:46:28 PM PDT 24
Peak memory 226544 kb
Host smart-432e8cd6-a4a2-4df8-92d3-55b725fd1529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300214585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2300214585
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2349090694
Short name T445
Test name
Test status
Simulation time 62364215198 ps
CPU time 281.65 seconds
Started May 05 01:46:27 PM PDT 24
Finished May 05 01:51:09 PM PDT 24
Peak memory 251044 kb
Host smart-8c42522c-b0a2-49a8-ade2-bb6915cc65e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349090694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2349090694
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.1455760830
Short name T99
Test name
Test status
Simulation time 10799862327 ps
CPU time 415.99 seconds
Started May 05 01:46:22 PM PDT 24
Finished May 05 01:53:19 PM PDT 24
Peak memory 277724 kb
Host smart-7e4c2196-320a-4d05-8238-905cba9f9362
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1455760830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.1455760830
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1165597404
Short name T792
Test name
Test status
Simulation time 12846077 ps
CPU time 0.88 seconds
Started May 05 01:46:29 PM PDT 24
Finished May 05 01:46:31 PM PDT 24
Peak memory 211856 kb
Host smart-1053d237-7476-44a5-a6a6-86f53e0bb080
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165597404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1165597404
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2091668448
Short name T232
Test name
Test status
Simulation time 52844799 ps
CPU time 0.88 seconds
Started May 05 01:46:35 PM PDT 24
Finished May 05 01:46:37 PM PDT 24
Peak memory 209592 kb
Host smart-be77b431-1fe3-4630-a067-40646d3261af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091668448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2091668448
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.602825868
Short name T584
Test name
Test status
Simulation time 870889336 ps
CPU time 14.07 seconds
Started May 05 01:46:25 PM PDT 24
Finished May 05 01:46:40 PM PDT 24
Peak memory 217996 kb
Host smart-0af26637-a0f4-4139-ae3a-d5d641863793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602825868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.602825868
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2145791867
Short name T623
Test name
Test status
Simulation time 55353527 ps
CPU time 2.12 seconds
Started May 05 01:46:32 PM PDT 24
Finished May 05 01:46:34 PM PDT 24
Peak memory 209712 kb
Host smart-32d0f5a7-d5b9-48b9-a6e6-d5b9120af52e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145791867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2145791867
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.4065025791
Short name T637
Test name
Test status
Simulation time 131598261 ps
CPU time 1.78 seconds
Started May 05 01:46:34 PM PDT 24
Finished May 05 01:46:36 PM PDT 24
Peak memory 218092 kb
Host smart-506e8859-f101-4e6f-b4f2-cf5578c7ff88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065025791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.4065025791
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.599442127
Short name T333
Test name
Test status
Simulation time 781436279 ps
CPU time 18.78 seconds
Started May 05 01:46:27 PM PDT 24
Finished May 05 01:46:47 PM PDT 24
Peak memory 219064 kb
Host smart-1953bd6f-dacb-434f-bb85-d3b9778eb98c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599442127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.599442127
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1729140316
Short name T437
Test name
Test status
Simulation time 635346238 ps
CPU time 8.61 seconds
Started May 05 01:46:18 PM PDT 24
Finished May 05 01:46:27 PM PDT 24
Peak memory 218104 kb
Host smart-f19d9218-f175-4fde-bdc6-7863a03a76c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729140316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1729140316
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3476142041
Short name T744
Test name
Test status
Simulation time 466031985 ps
CPU time 12.21 seconds
Started May 05 01:46:23 PM PDT 24
Finished May 05 01:46:36 PM PDT 24
Peak memory 218100 kb
Host smart-9efaa72a-d8e3-4d30-84e4-739ff4b4079d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476142041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3476142041
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.387906337
Short name T336
Test name
Test status
Simulation time 230277138 ps
CPU time 6.35 seconds
Started May 05 01:46:23 PM PDT 24
Finished May 05 01:46:30 PM PDT 24
Peak memory 218248 kb
Host smart-e83a6b47-9e0b-41fc-a559-121be9d8a39c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387906337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.387906337
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3766379908
Short name T219
Test name
Test status
Simulation time 30464792 ps
CPU time 1.51 seconds
Started May 05 01:46:21 PM PDT 24
Finished May 05 01:46:23 PM PDT 24
Peak memory 213408 kb
Host smart-24492e75-773f-40ad-95f0-98340101f281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766379908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3766379908
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1030494436
Short name T438
Test name
Test status
Simulation time 592643224 ps
CPU time 18.53 seconds
Started May 05 01:46:24 PM PDT 24
Finished May 05 01:46:43 PM PDT 24
Peak memory 245852 kb
Host smart-9b036f4c-9b54-468d-8b1d-07022f6ac456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030494436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1030494436
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3737797484
Short name T711
Test name
Test status
Simulation time 75840200 ps
CPU time 7.63 seconds
Started May 05 01:46:30 PM PDT 24
Finished May 05 01:46:38 PM PDT 24
Peak memory 248636 kb
Host smart-5d131f40-69b1-49cb-a615-7c973f5b156a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737797484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3737797484
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2033006735
Short name T310
Test name
Test status
Simulation time 4494950837 ps
CPU time 43.38 seconds
Started May 05 01:46:24 PM PDT 24
Finished May 05 01:47:07 PM PDT 24
Peak memory 251216 kb
Host smart-d713adff-6b3d-4493-a4be-3894c1d4bbe1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033006735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2033006735
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.3592753013
Short name T447
Test name
Test status
Simulation time 16526944872 ps
CPU time 519.12 seconds
Started May 05 01:46:35 PM PDT 24
Finished May 05 01:55:15 PM PDT 24
Peak memory 421892 kb
Host smart-9f4feeb1-023c-4a3b-ad0b-06dbb7f51a19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3592753013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.3592753013
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1949698287
Short name T626
Test name
Test status
Simulation time 30164303 ps
CPU time 0.92 seconds
Started May 05 01:46:27 PM PDT 24
Finished May 05 01:46:28 PM PDT 24
Peak memory 212788 kb
Host smart-0bb7d91d-1931-4755-bbf7-8948052ab538
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949698287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1949698287
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.4179720497
Short name T703
Test name
Test status
Simulation time 36968592 ps
CPU time 0.91 seconds
Started May 05 01:46:35 PM PDT 24
Finished May 05 01:46:36 PM PDT 24
Peak memory 209660 kb
Host smart-8a2ef229-5d46-4210-8397-bea27b45bedd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179720497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.4179720497
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3297260262
Short name T616
Test name
Test status
Simulation time 1642895859 ps
CPU time 13.16 seconds
Started May 05 01:46:27 PM PDT 24
Finished May 05 01:46:40 PM PDT 24
Peak memory 218112 kb
Host smart-457314b7-2999-4615-97f0-9451f30e2e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297260262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3297260262
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1340395117
Short name T312
Test name
Test status
Simulation time 767849002 ps
CPU time 4.46 seconds
Started May 05 01:46:29 PM PDT 24
Finished May 05 01:46:34 PM PDT 24
Peak memory 209708 kb
Host smart-b198da84-37f2-4590-be9f-bf00a7ef0b6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340395117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1340395117
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.36744651
Short name T554
Test name
Test status
Simulation time 95241211 ps
CPU time 2.51 seconds
Started May 05 01:46:26 PM PDT 24
Finished May 05 01:46:29 PM PDT 24
Peak memory 217996 kb
Host smart-4ce0779c-e595-4af6-8cd6-47031968bca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36744651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.36744651
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.781556639
Short name T750
Test name
Test status
Simulation time 771810305 ps
CPU time 13.64 seconds
Started May 05 01:46:37 PM PDT 24
Finished May 05 01:46:51 PM PDT 24
Peak memory 226188 kb
Host smart-7725bfff-cdee-4a52-a197-040cc9db413a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781556639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.781556639
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1254273191
Short name T489
Test name
Test status
Simulation time 2370205719 ps
CPU time 10.45 seconds
Started May 05 01:46:28 PM PDT 24
Finished May 05 01:46:39 PM PDT 24
Peak memory 218244 kb
Host smart-d2cc0c11-a131-40af-885d-e796882ac0c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254273191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1254273191
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2928455846
Short name T589
Test name
Test status
Simulation time 5921517306 ps
CPU time 8.36 seconds
Started May 05 01:46:45 PM PDT 24
Finished May 05 01:46:54 PM PDT 24
Peak memory 218148 kb
Host smart-560708de-4769-4523-8ea7-87a3bd9b0185
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928455846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2928455846
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1888047595
Short name T435
Test name
Test status
Simulation time 2422229218 ps
CPU time 9.13 seconds
Started May 05 01:46:27 PM PDT 24
Finished May 05 01:46:37 PM PDT 24
Peak memory 218140 kb
Host smart-4065d7d6-7bbb-4f41-b8e0-ac32322b96b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888047595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1888047595
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3176355329
Short name T418
Test name
Test status
Simulation time 31730816 ps
CPU time 2.18 seconds
Started May 05 01:46:22 PM PDT 24
Finished May 05 01:46:24 PM PDT 24
Peak memory 214308 kb
Host smart-83d7c2c7-fe41-4ed2-a3c8-1f77824f5f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176355329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3176355329
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3992763048
Short name T442
Test name
Test status
Simulation time 719520858 ps
CPU time 25.4 seconds
Started May 05 01:46:27 PM PDT 24
Finished May 05 01:46:53 PM PDT 24
Peak memory 251012 kb
Host smart-4c4e55ac-8915-454a-b8d1-75f459dd9ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992763048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3992763048
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1439446959
Short name T828
Test name
Test status
Simulation time 256769192 ps
CPU time 6.42 seconds
Started May 05 01:46:27 PM PDT 24
Finished May 05 01:46:34 PM PDT 24
Peak memory 250444 kb
Host smart-fe2214d6-680e-4370-94f7-462583798d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439446959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1439446959
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2744062785
Short name T697
Test name
Test status
Simulation time 29038550255 ps
CPU time 264.28 seconds
Started May 05 01:46:39 PM PDT 24
Finished May 05 01:51:04 PM PDT 24
Peak memory 268556 kb
Host smart-f72342d4-7a95-471b-8bb6-ea3ca9808851
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744062785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2744062785
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3873385699
Short name T291
Test name
Test status
Simulation time 11355888 ps
CPU time 1 seconds
Started May 05 01:46:30 PM PDT 24
Finished May 05 01:46:32 PM PDT 24
Peak memory 211728 kb
Host smart-7c0c4872-3583-49b9-89c7-c9c1daecb5e4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873385699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.3873385699
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1972913788
Short name T460
Test name
Test status
Simulation time 12334778 ps
CPU time 0.98 seconds
Started May 05 01:46:28 PM PDT 24
Finished May 05 01:46:29 PM PDT 24
Peak memory 209636 kb
Host smart-7d6ce62b-85a1-4584-bf22-026e0512b806
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972913788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1972913788
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2560043290
Short name T588
Test name
Test status
Simulation time 3679544081 ps
CPU time 20.61 seconds
Started May 05 01:46:27 PM PDT 24
Finished May 05 01:46:48 PM PDT 24
Peak memory 219044 kb
Host smart-f4189a6f-05d2-48a9-95f7-bacb24d13983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560043290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2560043290
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.4204175306
Short name T661
Test name
Test status
Simulation time 1477233420 ps
CPU time 4.48 seconds
Started May 05 01:46:37 PM PDT 24
Finished May 05 01:46:42 PM PDT 24
Peak memory 209680 kb
Host smart-1bd71ab6-0b9f-4d58-8d72-932c957e06c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204175306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.4204175306
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1628652108
Short name T495
Test name
Test status
Simulation time 123943276 ps
CPU time 3.42 seconds
Started May 05 01:46:36 PM PDT 24
Finished May 05 01:46:40 PM PDT 24
Peak memory 218068 kb
Host smart-7762d87e-f0c1-4ce8-a12e-6253899d966b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628652108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1628652108
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3498506051
Short name T294
Test name
Test status
Simulation time 279468643 ps
CPU time 10.15 seconds
Started May 05 01:46:36 PM PDT 24
Finished May 05 01:46:47 PM PDT 24
Peak memory 226192 kb
Host smart-4cf1a78a-68c9-44d4-acd2-f42f767a03ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498506051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3498506051
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1072401395
Short name T341
Test name
Test status
Simulation time 509084808 ps
CPU time 19.1 seconds
Started May 05 01:46:36 PM PDT 24
Finished May 05 01:46:56 PM PDT 24
Peak memory 218172 kb
Host smart-ee954605-0a0a-4de7-94da-b34013587f02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072401395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1072401395
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1466643980
Short name T873
Test name
Test status
Simulation time 598270581 ps
CPU time 19.05 seconds
Started May 05 01:46:35 PM PDT 24
Finished May 05 01:46:55 PM PDT 24
Peak memory 218188 kb
Host smart-94b329cd-1fd4-456c-ab9b-cc91e1e46cb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466643980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1466643980
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1720492285
Short name T161
Test name
Test status
Simulation time 837908939 ps
CPU time 15.97 seconds
Started May 05 01:46:40 PM PDT 24
Finished May 05 01:46:56 PM PDT 24
Peak memory 218224 kb
Host smart-7b79f8b1-3906-4f2e-951a-274ae9c43dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720492285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1720492285
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.3140647401
Short name T832
Test name
Test status
Simulation time 44216534 ps
CPU time 3.63 seconds
Started May 05 01:46:27 PM PDT 24
Finished May 05 01:46:32 PM PDT 24
Peak memory 214984 kb
Host smart-5153a8e7-309b-48b3-af89-8e5fd41080db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140647401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3140647401
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.2073626097
Short name T527
Test name
Test status
Simulation time 1168423432 ps
CPU time 33.44 seconds
Started May 05 01:46:42 PM PDT 24
Finished May 05 01:47:16 PM PDT 24
Peak memory 250916 kb
Host smart-79e10cf4-61e2-4ed7-bb51-866a440c6477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073626097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2073626097
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3295907529
Short name T722
Test name
Test status
Simulation time 216136453 ps
CPU time 6.92 seconds
Started May 05 01:46:29 PM PDT 24
Finished May 05 01:46:37 PM PDT 24
Peak memory 250540 kb
Host smart-cd7da215-6ecf-432f-a2b4-6eb4cfd773d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295907529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3295907529
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3725249201
Short name T737
Test name
Test status
Simulation time 5747605148 ps
CPU time 87.67 seconds
Started May 05 01:46:36 PM PDT 24
Finished May 05 01:48:04 PM PDT 24
Peak memory 221140 kb
Host smart-83734c5b-e777-4e8d-b169-10fae4305550
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725249201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3725249201
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2748104050
Short name T332
Test name
Test status
Simulation time 19324176 ps
CPU time 0.96 seconds
Started May 05 01:46:31 PM PDT 24
Finished May 05 01:46:33 PM PDT 24
Peak memory 211780 kb
Host smart-a768bf08-f06f-40a9-9a4d-c2f3d5eb8984
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748104050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2748104050
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.4168804091
Short name T309
Test name
Test status
Simulation time 20507716 ps
CPU time 1.02 seconds
Started May 05 01:46:33 PM PDT 24
Finished May 05 01:46:34 PM PDT 24
Peak memory 209708 kb
Host smart-bb90a412-76bf-4c8f-a744-9891c594067d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168804091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.4168804091
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1190462945
Short name T359
Test name
Test status
Simulation time 1679940662 ps
CPU time 14.78 seconds
Started May 05 01:46:32 PM PDT 24
Finished May 05 01:46:48 PM PDT 24
Peak memory 218148 kb
Host smart-7f54f02c-83eb-49dc-8421-4a9f5308986e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190462945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1190462945
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3659628456
Short name T415
Test name
Test status
Simulation time 1520161493 ps
CPU time 18.22 seconds
Started May 05 01:46:29 PM PDT 24
Finished May 05 01:46:48 PM PDT 24
Peak memory 217212 kb
Host smart-4c8cff96-5d23-407a-9ae8-634df374827d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659628456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3659628456
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.366442437
Short name T837
Test name
Test status
Simulation time 270717342 ps
CPU time 2.76 seconds
Started May 05 01:46:36 PM PDT 24
Finished May 05 01:46:39 PM PDT 24
Peak memory 218092 kb
Host smart-c38709e7-0928-47e8-be31-80966e173c11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366442437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.366442437
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.3517564437
Short name T88
Test name
Test status
Simulation time 827642862 ps
CPU time 7.82 seconds
Started May 05 01:46:37 PM PDT 24
Finished May 05 01:46:46 PM PDT 24
Peak memory 225576 kb
Host smart-0770833f-5001-40c2-b4fb-c6bafb3eb318
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517564437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3517564437
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2133566589
Short name T302
Test name
Test status
Simulation time 1002340991 ps
CPU time 10.93 seconds
Started May 05 01:46:38 PM PDT 24
Finished May 05 01:46:49 PM PDT 24
Peak memory 218088 kb
Host smart-bca5539d-7f93-43ee-9474-5256562a43ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133566589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2133566589
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3023919925
Short name T601
Test name
Test status
Simulation time 258748627 ps
CPU time 9.91 seconds
Started May 05 01:46:35 PM PDT 24
Finished May 05 01:46:45 PM PDT 24
Peak memory 218100 kb
Host smart-fd19c991-9198-4130-abe4-774bc5356cab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023919925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3023919925
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.502094863
Short name T738
Test name
Test status
Simulation time 429101469 ps
CPU time 10.99 seconds
Started May 05 01:46:28 PM PDT 24
Finished May 05 01:46:39 PM PDT 24
Peak memory 218324 kb
Host smart-01edac85-05f7-44fb-818a-79b977a4fe2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502094863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.502094863
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3589396983
Short name T794
Test name
Test status
Simulation time 32677362 ps
CPU time 1.44 seconds
Started May 05 01:46:42 PM PDT 24
Finished May 05 01:46:44 PM PDT 24
Peak memory 218052 kb
Host smart-7beee8a8-1e0b-48bc-8e3b-480cebbd3456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589396983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3589396983
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.4283752900
Short name T285
Test name
Test status
Simulation time 221426193 ps
CPU time 27.97 seconds
Started May 05 01:46:38 PM PDT 24
Finished May 05 01:47:07 PM PDT 24
Peak memory 251156 kb
Host smart-c87c5165-3b26-4ce9-8d18-8bc16de5eb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283752900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.4283752900
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3267901973
Short name T531
Test name
Test status
Simulation time 108979329 ps
CPU time 6.71 seconds
Started May 05 01:46:36 PM PDT 24
Finished May 05 01:46:44 PM PDT 24
Peak memory 251136 kb
Host smart-1192d8b1-0aa8-4532-9afd-75567861fede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267901973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3267901973
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3828460944
Short name T720
Test name
Test status
Simulation time 8099360896 ps
CPU time 53.42 seconds
Started May 05 01:46:40 PM PDT 24
Finished May 05 01:47:35 PM PDT 24
Peak memory 277112 kb
Host smart-a8b52972-810c-4e42-8bc2-8feb9fab95ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828460944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3828460944
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3977962903
Short name T97
Test name
Test status
Simulation time 9041664648 ps
CPU time 227.33 seconds
Started May 05 01:46:42 PM PDT 24
Finished May 05 01:50:30 PM PDT 24
Peak memory 382660 kb
Host smart-43f31db6-fdad-4b5e-b5b6-d1d3aaa8027a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3977962903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3977962903
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3385803475
Short name T491
Test name
Test status
Simulation time 13992714 ps
CPU time 1.18 seconds
Started May 05 01:46:37 PM PDT 24
Finished May 05 01:46:39 PM PDT 24
Peak memory 211780 kb
Host smart-a8f815fe-69c2-40e0-b4f1-af8f2559c23c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385803475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3385803475
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.3329118666
Short name T751
Test name
Test status
Simulation time 108842336 ps
CPU time 1 seconds
Started May 05 01:46:29 PM PDT 24
Finished May 05 01:46:30 PM PDT 24
Peak memory 209644 kb
Host smart-69ffc902-813c-43f0-84df-dd8bfb85d433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329118666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.3329118666
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3053383816
Short name T152
Test name
Test status
Simulation time 2369468384 ps
CPU time 9.65 seconds
Started May 05 01:46:36 PM PDT 24
Finished May 05 01:46:47 PM PDT 24
Peak memory 218136 kb
Host smart-05aa3f54-2ab7-4cfb-9ffe-dadc186e231a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053383816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3053383816
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3883413458
Short name T803
Test name
Test status
Simulation time 513942810 ps
CPU time 13.44 seconds
Started May 05 01:46:29 PM PDT 24
Finished May 05 01:46:43 PM PDT 24
Peak memory 217188 kb
Host smart-67d504dd-430d-4883-8dc7-91b93af5b5ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883413458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3883413458
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2776118871
Short name T587
Test name
Test status
Simulation time 477524199 ps
CPU time 5.72 seconds
Started May 05 01:46:37 PM PDT 24
Finished May 05 01:46:43 PM PDT 24
Peak memory 218120 kb
Host smart-4b9bb46d-7b0e-4814-a41c-a53c2687b68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776118871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2776118871
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.1682205094
Short name T849
Test name
Test status
Simulation time 1217291723 ps
CPU time 14.13 seconds
Started May 05 01:46:45 PM PDT 24
Finished May 05 01:47:00 PM PDT 24
Peak memory 218228 kb
Host smart-7649251d-1bdb-4f62-b7c1-f7fb86298ce3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682205094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.1682205094
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2132441645
Short name T347
Test name
Test status
Simulation time 1904971094 ps
CPU time 17.2 seconds
Started May 05 01:46:40 PM PDT 24
Finished May 05 01:46:58 PM PDT 24
Peak memory 218076 kb
Host smart-898b2cff-7087-48e7-9765-f2932312bc52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132441645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2132441645
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3712633942
Short name T254
Test name
Test status
Simulation time 429443429 ps
CPU time 11.73 seconds
Started May 05 01:46:34 PM PDT 24
Finished May 05 01:46:46 PM PDT 24
Peak memory 218128 kb
Host smart-04e221b2-3fdd-4518-a2a5-3509efebefea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712633942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3712633942
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2174712322
Short name T630
Test name
Test status
Simulation time 191103243 ps
CPU time 8.65 seconds
Started May 05 01:46:35 PM PDT 24
Finished May 05 01:46:44 PM PDT 24
Peak memory 218124 kb
Host smart-22f1d66a-8a84-4cee-9fc6-3e1f49a9be3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174712322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2174712322
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2295362370
Short name T83
Test name
Test status
Simulation time 167499153 ps
CPU time 2.93 seconds
Started May 05 01:46:39 PM PDT 24
Finished May 05 01:46:43 PM PDT 24
Peak memory 217880 kb
Host smart-6375de6b-1648-493e-80bb-a4634c5c2909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295362370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2295362370
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.966127945
Short name T753
Test name
Test status
Simulation time 1025505019 ps
CPU time 26.84 seconds
Started May 05 01:46:39 PM PDT 24
Finished May 05 01:47:07 PM PDT 24
Peak memory 251120 kb
Host smart-69f13e83-3d58-47bc-bf57-5575891e0687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966127945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.966127945
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.870597447
Short name T748
Test name
Test status
Simulation time 97212006 ps
CPU time 8.73 seconds
Started May 05 01:46:31 PM PDT 24
Finished May 05 01:46:40 PM PDT 24
Peak memory 251052 kb
Host smart-39296ded-adb2-4bd5-af75-612d83a6e749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870597447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.870597447
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2738287439
Short name T742
Test name
Test status
Simulation time 17959265749 ps
CPU time 95.98 seconds
Started May 05 01:46:36 PM PDT 24
Finished May 05 01:48:13 PM PDT 24
Peak memory 273124 kb
Host smart-3ac20661-9267-4b13-ae9b-cd3bb5276c47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738287439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2738287439
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.821479500
Short name T639
Test name
Test status
Simulation time 176872065003 ps
CPU time 309.28 seconds
Started May 05 01:46:38 PM PDT 24
Finished May 05 01:51:48 PM PDT 24
Peak memory 281264 kb
Host smart-a6146b38-9f36-4a7e-8334-25d415a44c4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=821479500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.821479500
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1278916969
Short name T746
Test name
Test status
Simulation time 13353524 ps
CPU time 1.04 seconds
Started May 05 01:46:32 PM PDT 24
Finished May 05 01:46:33 PM PDT 24
Peak memory 211800 kb
Host smart-8b9814fe-9f58-435d-be34-3fd625372e01
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278916969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1278916969
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.624357604
Short name T372
Test name
Test status
Simulation time 78262025 ps
CPU time 0.89 seconds
Started May 05 01:46:32 PM PDT 24
Finished May 05 01:46:34 PM PDT 24
Peak memory 209680 kb
Host smart-8d8b710a-5e86-4b8e-ae66-5cfc6fafe527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624357604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.624357604
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.2107732616
Short name T812
Test name
Test status
Simulation time 1124545574 ps
CPU time 17.34 seconds
Started May 05 01:46:40 PM PDT 24
Finished May 05 01:46:58 PM PDT 24
Peak memory 218072 kb
Host smart-ab7324a7-524e-4472-af95-c2de5a22ea3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107732616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.2107732616
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.908771465
Short name T483
Test name
Test status
Simulation time 2664986821 ps
CPU time 2.37 seconds
Started May 05 01:46:39 PM PDT 24
Finished May 05 01:46:42 PM PDT 24
Peak memory 217228 kb
Host smart-c0e726d4-24eb-4272-b97b-f948d22e5765
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908771465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.908771465
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1128738769
Short name T160
Test name
Test status
Simulation time 35754611 ps
CPU time 2.12 seconds
Started May 05 01:46:39 PM PDT 24
Finished May 05 01:46:42 PM PDT 24
Peak memory 218080 kb
Host smart-78c11723-61e8-4736-b300-cd7f5acb0dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128738769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1128738769
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.3608299278
Short name T405
Test name
Test status
Simulation time 1495656309 ps
CPU time 11.86 seconds
Started May 05 01:46:35 PM PDT 24
Finished May 05 01:46:48 PM PDT 24
Peak memory 219052 kb
Host smart-cc054f8e-5de2-4f46-ae89-b9e155715e9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608299278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3608299278
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2833785909
Short name T158
Test name
Test status
Simulation time 375038691 ps
CPU time 13.64 seconds
Started May 05 01:46:33 PM PDT 24
Finished May 05 01:46:47 PM PDT 24
Peak memory 218120 kb
Host smart-dc94b71b-b067-41f5-867e-225ccbf3aca7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833785909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2833785909
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.2824391253
Short name T490
Test name
Test status
Simulation time 1390763808 ps
CPU time 11.81 seconds
Started May 05 01:46:40 PM PDT 24
Finished May 05 01:46:52 PM PDT 24
Peak memory 218080 kb
Host smart-834cc3ea-0247-4aae-9425-52a48c1605bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824391253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
2824391253
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2904057157
Short name T305
Test name
Test status
Simulation time 338436954 ps
CPU time 8.81 seconds
Started May 05 01:46:32 PM PDT 24
Finished May 05 01:46:41 PM PDT 24
Peak memory 218124 kb
Host smart-da1371e2-fef6-4ddd-abce-db10b464e37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904057157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2904057157
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2062070340
Short name T149
Test name
Test status
Simulation time 72177928 ps
CPU time 4.4 seconds
Started May 05 01:46:28 PM PDT 24
Finished May 05 01:46:33 PM PDT 24
Peak memory 218408 kb
Host smart-b9cdf580-197b-4251-97a9-46a66a30c9ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062070340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2062070340
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.20406935
Short name T322
Test name
Test status
Simulation time 854082098 ps
CPU time 21.65 seconds
Started May 05 01:46:37 PM PDT 24
Finished May 05 01:47:00 PM PDT 24
Peak memory 251120 kb
Host smart-edf68f62-ba15-48bf-8e35-b02b3886d7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20406935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.20406935
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1518367616
Short name T323
Test name
Test status
Simulation time 1351391767 ps
CPU time 9.09 seconds
Started May 05 01:46:37 PM PDT 24
Finished May 05 01:46:47 PM PDT 24
Peak memory 250736 kb
Host smart-6008d8ba-6057-41c6-88e1-01cc8ae3dfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518367616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1518367616
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2129340951
Short name T833
Test name
Test status
Simulation time 339640641 ps
CPU time 6.97 seconds
Started May 05 01:46:39 PM PDT 24
Finished May 05 01:46:47 PM PDT 24
Peak memory 217996 kb
Host smart-a517e16c-d466-4cdc-aa4c-41430b88b495
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129340951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2129340951
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.1362660793
Short name T153
Test name
Test status
Simulation time 44711868796 ps
CPU time 283.1 seconds
Started May 05 01:46:36 PM PDT 24
Finished May 05 01:51:19 PM PDT 24
Peak memory 267596 kb
Host smart-c45e93eb-c6b4-408b-984b-b2d25099df64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1362660793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.1362660793
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2074603818
Short name T257
Test name
Test status
Simulation time 20847780 ps
CPU time 1.01 seconds
Started May 05 01:46:32 PM PDT 24
Finished May 05 01:46:33 PM PDT 24
Peak memory 211836 kb
Host smart-61618144-c8cc-4fc2-b0a7-2a8b930b483e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074603818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2074603818
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2959621833
Short name T71
Test name
Test status
Simulation time 50567635 ps
CPU time 1.02 seconds
Started May 05 01:46:41 PM PDT 24
Finished May 05 01:46:43 PM PDT 24
Peak memory 209680 kb
Host smart-a6961e68-94f2-4e6a-b255-cbd76ba91510
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959621833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2959621833
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.602213263
Short name T49
Test name
Test status
Simulation time 754234800 ps
CPU time 13.22 seconds
Started May 05 01:46:41 PM PDT 24
Finished May 05 01:46:55 PM PDT 24
Peak memory 218092 kb
Host smart-9ac36d54-cd21-48eb-901d-4b4fd08ceb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602213263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.602213263
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1541631859
Short name T679
Test name
Test status
Simulation time 84539370 ps
CPU time 1.77 seconds
Started May 05 01:46:53 PM PDT 24
Finished May 05 01:46:56 PM PDT 24
Peak memory 217012 kb
Host smart-da36ec14-39d6-4128-a7c7-dfc9be590ced
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541631859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1541631859
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3601964721
Short name T375
Test name
Test status
Simulation time 188488328 ps
CPU time 1.89 seconds
Started May 05 01:46:38 PM PDT 24
Finished May 05 01:46:40 PM PDT 24
Peak memory 218184 kb
Host smart-bd4bd418-c116-4b98-a618-ee6811ec1040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601964721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3601964721
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.251485791
Short name T236
Test name
Test status
Simulation time 238757703 ps
CPU time 10.56 seconds
Started May 05 01:46:32 PM PDT 24
Finished May 05 01:46:43 PM PDT 24
Peak memory 218132 kb
Host smart-96d52edc-19dd-406b-94df-2d2dc066b7c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251485791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.251485791
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.51260467
Short name T92
Test name
Test status
Simulation time 712543209 ps
CPU time 13.94 seconds
Started May 05 01:46:45 PM PDT 24
Finished May 05 01:46:59 PM PDT 24
Peak memory 218140 kb
Host smart-1b41ff3a-39da-4fef-849e-86d94747de17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51260467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_dig
est.51260467
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.3774326010
Short name T830
Test name
Test status
Simulation time 2465440516 ps
CPU time 10.64 seconds
Started May 05 01:46:36 PM PDT 24
Finished May 05 01:46:48 PM PDT 24
Peak memory 218180 kb
Host smart-6d45f610-75fb-43a1-a065-984259392f6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774326010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
3774326010
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.2442289015
Short name T458
Test name
Test status
Simulation time 249690067 ps
CPU time 7.4 seconds
Started May 05 01:46:36 PM PDT 24
Finished May 05 01:46:44 PM PDT 24
Peak memory 218256 kb
Host smart-03f8358a-3713-4e6c-9f5f-ff13bbddfbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442289015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.2442289015
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3054487473
Short name T94
Test name
Test status
Simulation time 37360153 ps
CPU time 1.06 seconds
Started May 05 01:46:32 PM PDT 24
Finished May 05 01:46:34 PM PDT 24
Peak memory 212164 kb
Host smart-3bd28942-11b8-45f0-99d6-568af0e20593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054487473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3054487473
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3619011943
Short name T205
Test name
Test status
Simulation time 55040585 ps
CPU time 7.58 seconds
Started May 05 01:46:31 PM PDT 24
Finished May 05 01:46:39 PM PDT 24
Peak memory 251136 kb
Host smart-0bfbbabb-88a7-48d6-abb8-bda87796013c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619011943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3619011943
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3505887249
Short name T640
Test name
Test status
Simulation time 4534728995 ps
CPU time 42.74 seconds
Started May 05 01:46:35 PM PDT 24
Finished May 05 01:47:18 PM PDT 24
Peak memory 267616 kb
Host smart-e8e6a29f-fd95-42b8-9927-04e6c0144868
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505887249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3505887249
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.936975931
Short name T79
Test name
Test status
Simulation time 78536015519 ps
CPU time 1274.34 seconds
Started May 05 01:46:39 PM PDT 24
Finished May 05 02:07:54 PM PDT 24
Peak memory 316824 kb
Host smart-6bb7d48a-f5e6-4529-b527-88e562a764d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=936975931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.936975931
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3895166662
Short name T860
Test name
Test status
Simulation time 28736233 ps
CPU time 1.07 seconds
Started May 05 01:46:38 PM PDT 24
Finished May 05 01:46:40 PM PDT 24
Peak memory 212940 kb
Host smart-d0a055ea-27b0-4b17-9693-321e06bf05ce
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895166662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3895166662
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.3016481037
Short name T871
Test name
Test status
Simulation time 55480400 ps
CPU time 0.9 seconds
Started May 05 01:46:42 PM PDT 24
Finished May 05 01:46:44 PM PDT 24
Peak memory 209696 kb
Host smart-96e91542-2c8a-4095-9db0-1b87d56093c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016481037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.3016481037
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.952838205
Short name T596
Test name
Test status
Simulation time 460689128 ps
CPU time 14.12 seconds
Started May 05 01:46:41 PM PDT 24
Finished May 05 01:46:56 PM PDT 24
Peak memory 218176 kb
Host smart-bd6808fb-d162-4f2e-bc1d-b53ae915cf95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952838205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.952838205
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1959144427
Short name T771
Test name
Test status
Simulation time 361768265 ps
CPU time 4.82 seconds
Started May 05 01:46:34 PM PDT 24
Finished May 05 01:46:39 PM PDT 24
Peak memory 217392 kb
Host smart-1fe9ab01-d12a-47be-9f90-b9e87f036958
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959144427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1959144427
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2935414146
Short name T61
Test name
Test status
Simulation time 111018181 ps
CPU time 3.81 seconds
Started May 05 01:46:42 PM PDT 24
Finished May 05 01:46:47 PM PDT 24
Peak memory 218108 kb
Host smart-7fa49a52-ad6d-40e8-bd73-a09afa3b1684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935414146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2935414146
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.2954536762
Short name T381
Test name
Test status
Simulation time 1818870085 ps
CPU time 17.47 seconds
Started May 05 01:46:36 PM PDT 24
Finished May 05 01:46:54 PM PDT 24
Peak memory 218248 kb
Host smart-635650c9-78b8-41a9-8079-c9d8ca71320e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954536762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.2954536762
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.442945388
Short name T775
Test name
Test status
Simulation time 680072426 ps
CPU time 8.12 seconds
Started May 05 01:46:41 PM PDT 24
Finished May 05 01:46:50 PM PDT 24
Peak memory 218060 kb
Host smart-ad6f7961-faaf-4f57-99ed-732bfd411497
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442945388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_di
gest.442945388
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.171086036
Short name T533
Test name
Test status
Simulation time 583722008 ps
CPU time 11.13 seconds
Started May 05 01:46:34 PM PDT 24
Finished May 05 01:46:46 PM PDT 24
Peak memory 218032 kb
Host smart-3667b77b-9d1d-4465-b2bf-c5d46cbef660
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171086036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.171086036
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.124520007
Short name T200
Test name
Test status
Simulation time 1386012063 ps
CPU time 11.18 seconds
Started May 05 01:46:41 PM PDT 24
Finished May 05 01:46:53 PM PDT 24
Peak memory 218248 kb
Host smart-5a190fd4-e96f-4fb4-af7f-d4f277a1aa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124520007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.124520007
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1363023344
Short name T767
Test name
Test status
Simulation time 126323840 ps
CPU time 2.12 seconds
Started May 05 01:46:36 PM PDT 24
Finished May 05 01:46:39 PM PDT 24
Peak memory 217864 kb
Host smart-11393f43-b60d-4fba-973f-9b81706db63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363023344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1363023344
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.836022254
Short name T364
Test name
Test status
Simulation time 709739226 ps
CPU time 25.48 seconds
Started May 05 01:46:38 PM PDT 24
Finished May 05 01:47:04 PM PDT 24
Peak memory 248764 kb
Host smart-cf002a5e-e407-41fb-9b2e-7d0558d560cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836022254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.836022254
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.662373109
Short name T556
Test name
Test status
Simulation time 102184851 ps
CPU time 8.75 seconds
Started May 05 01:46:37 PM PDT 24
Finished May 05 01:46:46 PM PDT 24
Peak memory 251072 kb
Host smart-4275c3b8-7e41-4936-9649-f081f5822465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662373109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.662373109
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.400802444
Short name T50
Test name
Test status
Simulation time 25936386972 ps
CPU time 337.89 seconds
Started May 05 01:46:38 PM PDT 24
Finished May 05 01:52:17 PM PDT 24
Peak memory 274932 kb
Host smart-093e972f-5bc6-4eff-85d7-bed2e30fe3d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400802444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.400802444
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1004925667
Short name T338
Test name
Test status
Simulation time 17778156 ps
CPU time 0.88 seconds
Started May 05 01:46:37 PM PDT 24
Finished May 05 01:46:39 PM PDT 24
Peak memory 211764 kb
Host smart-55d8045f-83c6-4639-85f4-5bc1bddbd61a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004925667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1004925667
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2250777827
Short name T70
Test name
Test status
Simulation time 20810874 ps
CPU time 0.97 seconds
Started May 05 01:46:38 PM PDT 24
Finished May 05 01:46:40 PM PDT 24
Peak memory 209632 kb
Host smart-a8c840a5-eb6c-4cbf-a66c-3f60a7145fce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250777827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2250777827
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2426149231
Short name T269
Test name
Test status
Simulation time 736074269 ps
CPU time 15.44 seconds
Started May 05 01:46:40 PM PDT 24
Finished May 05 01:46:56 PM PDT 24
Peak memory 218136 kb
Host smart-93e86b76-0855-4a42-a8a8-72237e27da47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426149231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2426149231
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1861934929
Short name T528
Test name
Test status
Simulation time 48474226 ps
CPU time 1.86 seconds
Started May 05 01:46:38 PM PDT 24
Finished May 05 01:46:41 PM PDT 24
Peak memory 217056 kb
Host smart-bfef8dbc-b207-496a-b014-f6f012fdada4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861934929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1861934929
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3815335407
Short name T373
Test name
Test status
Simulation time 469623624 ps
CPU time 2.35 seconds
Started May 05 01:46:39 PM PDT 24
Finished May 05 01:46:42 PM PDT 24
Peak memory 218176 kb
Host smart-690f88fe-4243-408e-9912-65eee6e412fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815335407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3815335407
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3263294215
Short name T690
Test name
Test status
Simulation time 610989118 ps
CPU time 12.34 seconds
Started May 05 01:46:36 PM PDT 24
Finished May 05 01:46:50 PM PDT 24
Peak memory 218156 kb
Host smart-ad3d05b4-b785-4d46-b56e-76b501b7557a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263294215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3263294215
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1830935043
Short name T366
Test name
Test status
Simulation time 705201407 ps
CPU time 10.43 seconds
Started May 05 01:46:41 PM PDT 24
Finished May 05 01:46:52 PM PDT 24
Peak memory 218132 kb
Host smart-81700166-0518-4ce4-9de7-76405297156b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830935043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1830935043
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2070040416
Short name T715
Test name
Test status
Simulation time 350200814 ps
CPU time 10.93 seconds
Started May 05 01:46:38 PM PDT 24
Finished May 05 01:46:50 PM PDT 24
Peak memory 218100 kb
Host smart-1a50f777-4856-48b7-b72b-f114d3f561f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070040416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2070040416
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.715477469
Short name T866
Test name
Test status
Simulation time 485003898 ps
CPU time 8.54 seconds
Started May 05 01:46:42 PM PDT 24
Finished May 05 01:46:51 PM PDT 24
Peak memory 218124 kb
Host smart-093e782d-0c25-4ca8-9ff7-683e33dd3b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715477469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.715477469
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2544357259
Short name T311
Test name
Test status
Simulation time 45239137 ps
CPU time 2.05 seconds
Started May 05 01:46:40 PM PDT 24
Finished May 05 01:46:43 PM PDT 24
Peak memory 213880 kb
Host smart-b958eab9-c6b1-4c67-a321-f484f49175b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544357259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2544357259
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2665545537
Short name T836
Test name
Test status
Simulation time 1101415356 ps
CPU time 29.8 seconds
Started May 05 01:46:45 PM PDT 24
Finished May 05 01:47:15 PM PDT 24
Peak memory 250996 kb
Host smart-5bf76a41-765d-400b-af27-f97aaef21a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665545537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2665545537
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.1357457589
Short name T396
Test name
Test status
Simulation time 57712463 ps
CPU time 6.18 seconds
Started May 05 01:46:35 PM PDT 24
Finished May 05 01:46:42 PM PDT 24
Peak memory 244768 kb
Host smart-b1c55d9d-93d4-4639-83ba-2067d8f6e91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357457589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.1357457589
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1110893416
Short name T819
Test name
Test status
Simulation time 3784832708 ps
CPU time 95.46 seconds
Started May 05 01:46:37 PM PDT 24
Finished May 05 01:48:13 PM PDT 24
Peak memory 272792 kb
Host smart-00ad77c6-d6a0-49c6-8a70-54b8637325c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110893416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1110893416
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3712807170
Short name T163
Test name
Test status
Simulation time 12123596 ps
CPU time 0.86 seconds
Started May 05 01:46:40 PM PDT 24
Finished May 05 01:46:41 PM PDT 24
Peak memory 211716 kb
Host smart-6fdb867a-3d64-4e85-9eb9-969b46319380
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712807170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3712807170
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3010361022
Short name T544
Test name
Test status
Simulation time 32457392 ps
CPU time 1.18 seconds
Started May 05 01:45:33 PM PDT 24
Finished May 05 01:45:34 PM PDT 24
Peak memory 209656 kb
Host smart-24901ab4-2db8-4f1d-b65b-325fe96fcb52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010361022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3010361022
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1170124254
Short name T18
Test name
Test status
Simulation time 1390824947 ps
CPU time 17 seconds
Started May 05 01:45:37 PM PDT 24
Finished May 05 01:45:55 PM PDT 24
Peak memory 218108 kb
Host smart-2213412a-261c-4fec-8dfe-dd3e9071efd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170124254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1170124254
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.866237543
Short name T394
Test name
Test status
Simulation time 126143581 ps
CPU time 3.77 seconds
Started May 05 01:45:31 PM PDT 24
Finished May 05 01:45:36 PM PDT 24
Peak memory 209652 kb
Host smart-12bf4631-d785-4d94-98f8-38a45a59441d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866237543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.866237543
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.3264280385
Short name T434
Test name
Test status
Simulation time 33332231554 ps
CPU time 117.78 seconds
Started May 05 01:45:42 PM PDT 24
Finished May 05 01:47:42 PM PDT 24
Peak memory 219108 kb
Host smart-ed028832-777a-4e8f-bf77-7ba73b75ccb6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264280385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.3264280385
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1303551440
Short name T672
Test name
Test status
Simulation time 2143118050 ps
CPU time 13.43 seconds
Started May 05 01:45:29 PM PDT 24
Finished May 05 01:45:43 PM PDT 24
Peak memory 217492 kb
Host smart-e6216c6d-181d-4656-9b95-440e539f4ae1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303551440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1
303551440
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.1273055073
Short name T706
Test name
Test status
Simulation time 710273130 ps
CPU time 19.8 seconds
Started May 05 01:45:44 PM PDT 24
Finished May 05 01:46:06 PM PDT 24
Peak memory 218076 kb
Host smart-9d74a193-48cf-41f9-9bb1-d5fdd702d8dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273055073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.1273055073
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2440822064
Short name T456
Test name
Test status
Simulation time 3258521599 ps
CPU time 18.1 seconds
Started May 05 01:45:41 PM PDT 24
Finished May 05 01:46:01 PM PDT 24
Peak memory 214112 kb
Host smart-7aa01244-2679-4f9b-a252-c9c83ecdd4f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440822064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2440822064
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1431465004
Short name T465
Test name
Test status
Simulation time 270328459 ps
CPU time 7.71 seconds
Started May 05 01:45:33 PM PDT 24
Finished May 05 01:45:41 PM PDT 24
Peak memory 213504 kb
Host smart-32afb6dc-056e-480b-b7a7-a7890845582d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431465004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1431465004
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.193044446
Short name T28
Test name
Test status
Simulation time 10165546313 ps
CPU time 52.7 seconds
Started May 05 01:45:28 PM PDT 24
Finished May 05 01:46:22 PM PDT 24
Peak memory 275740 kb
Host smart-9ab1ca3a-9fca-4a07-a53c-4492129b23f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193044446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_state_failure.193044446
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2370266900
Short name T398
Test name
Test status
Simulation time 2701897559 ps
CPU time 13.63 seconds
Started May 05 01:45:39 PM PDT 24
Finished May 05 01:45:54 PM PDT 24
Peak memory 251208 kb
Host smart-b975b353-e3eb-4f2e-ab6b-1824e1d1c177
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370266900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2370266900
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1143538569
Short name T538
Test name
Test status
Simulation time 180786673 ps
CPU time 2.54 seconds
Started May 05 01:45:41 PM PDT 24
Finished May 05 01:45:45 PM PDT 24
Peak memory 218392 kb
Host smart-95b1b25b-9d97-4bf0-9cf9-d9e57d10043f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143538569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1143538569
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1803176244
Short name T450
Test name
Test status
Simulation time 231425894 ps
CPU time 8.55 seconds
Started May 05 01:45:29 PM PDT 24
Finished May 05 01:45:39 PM PDT 24
Peak memory 218384 kb
Host smart-337347c8-b71a-4f8d-b853-96b80941619a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803176244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1803176244
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1212393148
Short name T56
Test name
Test status
Simulation time 139547858 ps
CPU time 23.92 seconds
Started May 05 01:45:32 PM PDT 24
Finished May 05 01:45:56 PM PDT 24
Peak memory 269188 kb
Host smart-e49233e4-2350-495b-981c-9a297432f78c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212393148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1212393148
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.74535653
Short name T545
Test name
Test status
Simulation time 375739741 ps
CPU time 12.99 seconds
Started May 05 01:45:42 PM PDT 24
Finished May 05 01:45:57 PM PDT 24
Peak memory 219084 kb
Host smart-1f505a86-26e9-4e26-aebd-df6d4f1c089b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74535653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.74535653
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.3073714498
Short name T617
Test name
Test status
Simulation time 172610291 ps
CPU time 7.96 seconds
Started May 05 01:45:32 PM PDT 24
Finished May 05 01:45:40 PM PDT 24
Peak memory 218044 kb
Host smart-aa4bb07f-89c2-45be-b93a-9faf9aa620b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073714498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.3073714498
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2491311227
Short name T443
Test name
Test status
Simulation time 1039233812 ps
CPU time 11.45 seconds
Started May 05 01:45:39 PM PDT 24
Finished May 05 01:45:51 PM PDT 24
Peak memory 218124 kb
Host smart-dc9c5be9-2068-4028-b04d-439120809ab9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491311227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
491311227
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3724153700
Short name T668
Test name
Test status
Simulation time 384496782 ps
CPU time 9.39 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:45:55 PM PDT 24
Peak memory 218164 kb
Host smart-1eb79f36-e45d-4fae-b61d-3809105a9d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724153700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3724153700
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3558364268
Short name T581
Test name
Test status
Simulation time 139628882 ps
CPU time 3.12 seconds
Started May 05 01:45:34 PM PDT 24
Finished May 05 01:45:37 PM PDT 24
Peak memory 217876 kb
Host smart-a7a8ca62-eb62-4c9d-95d9-5b2ac0e5cbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558364268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3558364268
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1876463754
Short name T361
Test name
Test status
Simulation time 1495034476 ps
CPU time 19.84 seconds
Started May 05 01:45:44 PM PDT 24
Finished May 05 01:46:06 PM PDT 24
Peak memory 251108 kb
Host smart-246f30e8-7c14-441a-89d6-cf7390939027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876463754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1876463754
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.537457376
Short name T148
Test name
Test status
Simulation time 98791887 ps
CPU time 8.24 seconds
Started May 05 01:45:29 PM PDT 24
Finished May 05 01:45:38 PM PDT 24
Peak memory 246808 kb
Host smart-db5bdcf6-6b8f-491c-b42c-68f3dddb5990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537457376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.537457376
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3441871657
Short name T343
Test name
Test status
Simulation time 7064060786 ps
CPU time 235.84 seconds
Started May 05 01:45:41 PM PDT 24
Finished May 05 01:49:39 PM PDT 24
Peak memory 271460 kb
Host smart-77012568-ab7a-4f46-8cfa-327e3d74b14f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441871657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3441871657
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.283100269
Short name T216
Test name
Test status
Simulation time 20005257 ps
CPU time 0.89 seconds
Started May 05 01:45:37 PM PDT 24
Finished May 05 01:45:38 PM PDT 24
Peak memory 211756 kb
Host smart-f6bddd41-8f45-480e-9cb4-e0e2d1052819
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283100269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr
l_volatile_unlock_smoke.283100269
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.340724127
Short name T260
Test name
Test status
Simulation time 239644199 ps
CPU time 0.98 seconds
Started May 05 01:46:49 PM PDT 24
Finished May 05 01:46:51 PM PDT 24
Peak memory 209612 kb
Host smart-a4b5c471-d325-447e-9cda-a25e66206ac0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340724127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.340724127
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.828360770
Short name T433
Test name
Test status
Simulation time 652202702 ps
CPU time 20.02 seconds
Started May 05 01:46:40 PM PDT 24
Finished May 05 01:47:00 PM PDT 24
Peak memory 218060 kb
Host smart-a3366fbb-504e-4d35-a238-ddc6cddfd7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828360770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.828360770
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.3399280596
Short name T562
Test name
Test status
Simulation time 613278101 ps
CPU time 4.67 seconds
Started May 05 01:46:40 PM PDT 24
Finished May 05 01:46:46 PM PDT 24
Peak memory 209724 kb
Host smart-d18b7709-fc9c-47b5-abad-92014d3fb413
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399280596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3399280596
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.151991405
Short name T856
Test name
Test status
Simulation time 27280565 ps
CPU time 1.79 seconds
Started May 05 01:46:40 PM PDT 24
Finished May 05 01:46:43 PM PDT 24
Peak memory 218244 kb
Host smart-b424960e-9240-4861-b4b7-015df8c539c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151991405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.151991405
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1967204299
Short name T708
Test name
Test status
Simulation time 943183065 ps
CPU time 8.84 seconds
Started May 05 01:46:44 PM PDT 24
Finished May 05 01:46:53 PM PDT 24
Peak memory 225912 kb
Host smart-0ed7afe9-adc5-4cd9-af66-7bbeed845392
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967204299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1967204299
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1246639505
Short name T265
Test name
Test status
Simulation time 296503122 ps
CPU time 9.19 seconds
Started May 05 01:46:43 PM PDT 24
Finished May 05 01:46:53 PM PDT 24
Peak memory 218108 kb
Host smart-6e34ce28-7385-406e-9829-8ffc2a55a1c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246639505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1246639505
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3992891569
Short name T537
Test name
Test status
Simulation time 1179418525 ps
CPU time 7.82 seconds
Started May 05 01:46:45 PM PDT 24
Finished May 05 01:46:54 PM PDT 24
Peak memory 218092 kb
Host smart-4964aa25-9ee7-421d-b5d8-14c31770d82e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992891569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3992891569
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.4204628843
Short name T316
Test name
Test status
Simulation time 942297060 ps
CPU time 10.95 seconds
Started May 05 01:46:39 PM PDT 24
Finished May 05 01:46:51 PM PDT 24
Peak memory 218064 kb
Host smart-9d2eb4ac-276e-4f16-87e9-16d0d23e1839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204628843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.4204628843
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1534969612
Short name T407
Test name
Test status
Simulation time 170117386 ps
CPU time 2.84 seconds
Started May 05 01:46:39 PM PDT 24
Finished May 05 01:46:42 PM PDT 24
Peak memory 214152 kb
Host smart-41b95dca-c9d8-436e-8f65-2c098a61c745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534969612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1534969612
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3441126243
Short name T271
Test name
Test status
Simulation time 340364321 ps
CPU time 34.38 seconds
Started May 05 01:46:45 PM PDT 24
Finished May 05 01:47:20 PM PDT 24
Peak memory 247204 kb
Host smart-42c7aa7e-f1a2-45e8-9628-b6a4c3140e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441126243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3441126243
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2852720414
Short name T659
Test name
Test status
Simulation time 70182594 ps
CPU time 7.74 seconds
Started May 05 01:46:45 PM PDT 24
Finished May 05 01:46:54 PM PDT 24
Peak memory 250488 kb
Host smart-587654b0-7dc8-4891-90c4-29558e5264c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852720414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2852720414
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1062013261
Short name T847
Test name
Test status
Simulation time 18238987015 ps
CPU time 167.84 seconds
Started May 05 01:46:43 PM PDT 24
Finished May 05 01:49:31 PM PDT 24
Peak memory 282852 kb
Host smart-74d2b43a-bce7-40ce-bf39-a2c3b1697bde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062013261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1062013261
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3897330199
Short name T393
Test name
Test status
Simulation time 11521232 ps
CPU time 0.91 seconds
Started May 05 01:46:40 PM PDT 24
Finished May 05 01:46:41 PM PDT 24
Peak memory 208164 kb
Host smart-5ed620e3-b7c2-40db-857b-e36eef9a26a3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897330199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3897330199
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3832182927
Short name T673
Test name
Test status
Simulation time 24074825 ps
CPU time 1.24 seconds
Started May 05 01:46:46 PM PDT 24
Finished May 05 01:46:48 PM PDT 24
Peak memory 209612 kb
Host smart-f4736523-5a6d-47da-a87c-20cf3c42ca78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832182927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3832182927
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1068932027
Short name T44
Test name
Test status
Simulation time 292348974 ps
CPU time 11.48 seconds
Started May 05 01:46:45 PM PDT 24
Finished May 05 01:46:57 PM PDT 24
Peak memory 218268 kb
Host smart-7a15135b-fa46-469b-8cd8-953af396c45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068932027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1068932027
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3086378474
Short name T548
Test name
Test status
Simulation time 131860288 ps
CPU time 2.73 seconds
Started May 05 01:46:39 PM PDT 24
Finished May 05 01:46:43 PM PDT 24
Peak memory 209740 kb
Host smart-9eccef29-7629-4a6c-87b1-0eabd0f9b83c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086378474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3086378474
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.1120309927
Short name T684
Test name
Test status
Simulation time 77798811 ps
CPU time 2.91 seconds
Started May 05 01:46:45 PM PDT 24
Finished May 05 01:46:49 PM PDT 24
Peak memory 218080 kb
Host smart-ef0f71bc-b37d-4a41-831d-b7da6364029f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120309927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1120309927
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.544371265
Short name T494
Test name
Test status
Simulation time 1401924192 ps
CPU time 11.29 seconds
Started May 05 01:46:41 PM PDT 24
Finished May 05 01:46:53 PM PDT 24
Peak memory 218144 kb
Host smart-4b30fa15-4c90-4c20-a8cd-226e37d734d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544371265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.544371265
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3391536706
Short name T401
Test name
Test status
Simulation time 211081177 ps
CPU time 8.81 seconds
Started May 05 01:46:47 PM PDT 24
Finished May 05 01:46:57 PM PDT 24
Peak memory 218244 kb
Host smart-a5e09e27-ccf5-47b2-8eab-35b26eecdd79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391536706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3391536706
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3856824118
Short name T825
Test name
Test status
Simulation time 473265765 ps
CPU time 9.13 seconds
Started May 05 01:46:46 PM PDT 24
Finished May 05 01:46:56 PM PDT 24
Peak memory 218052 kb
Host smart-f48c6f69-1314-4d49-a68a-b35aafc8247e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856824118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3856824118
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.277132613
Short name T773
Test name
Test status
Simulation time 338989174 ps
CPU time 10.05 seconds
Started May 05 01:46:45 PM PDT 24
Finished May 05 01:46:56 PM PDT 24
Peak memory 218172 kb
Host smart-1b8978ed-4ebb-4cdd-a822-f97c064c7e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277132613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.277132613
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3536949989
Short name T670
Test name
Test status
Simulation time 53750278 ps
CPU time 1.89 seconds
Started May 05 01:46:52 PM PDT 24
Finished May 05 01:46:55 PM PDT 24
Peak memory 213800 kb
Host smart-ece2f071-f264-4009-872d-4dc89140ae86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536949989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3536949989
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1458390417
Short name T339
Test name
Test status
Simulation time 357221817 ps
CPU time 16.64 seconds
Started May 05 01:46:43 PM PDT 24
Finished May 05 01:47:00 PM PDT 24
Peak memory 244588 kb
Host smart-3f74a763-12c2-45db-bcbc-428a5c511f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458390417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1458390417
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1129312230
Short name T853
Test name
Test status
Simulation time 165154724 ps
CPU time 7.03 seconds
Started May 05 01:46:37 PM PDT 24
Finished May 05 01:46:45 PM PDT 24
Peak memory 250736 kb
Host smart-cf29f2f1-f4a4-4ddb-b8d3-32e47a685b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129312230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1129312230
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.4154441085
Short name T501
Test name
Test status
Simulation time 40825941348 ps
CPU time 166.87 seconds
Started May 05 01:46:47 PM PDT 24
Finished May 05 01:49:35 PM PDT 24
Peak memory 251140 kb
Host smart-2d31e082-ca13-4db2-813b-a3f3b6db7dbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154441085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.4154441085
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1965355225
Short name T484
Test name
Test status
Simulation time 145353728 ps
CPU time 0.84 seconds
Started May 05 01:46:45 PM PDT 24
Finished May 05 01:46:47 PM PDT 24
Peak memory 211716 kb
Host smart-fd8c7059-bda0-4c00-9884-f40c75f00f0e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965355225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1965355225
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3396379485
Short name T529
Test name
Test status
Simulation time 56419996 ps
CPU time 0.9 seconds
Started May 05 01:46:42 PM PDT 24
Finished May 05 01:46:44 PM PDT 24
Peak memory 209628 kb
Host smart-c9b24795-75c5-44a6-a3c4-83b8de67d23d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396379485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3396379485
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.42907994
Short name T51
Test name
Test status
Simulation time 304479692 ps
CPU time 9.38 seconds
Started May 05 01:46:47 PM PDT 24
Finished May 05 01:46:57 PM PDT 24
Peak memory 218044 kb
Host smart-1e04c771-3ab8-4ea0-9aa0-9f4d2f261cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42907994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.42907994
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3485720663
Short name T542
Test name
Test status
Simulation time 175153452 ps
CPU time 2.34 seconds
Started May 05 01:46:38 PM PDT 24
Finished May 05 01:46:41 PM PDT 24
Peak memory 216956 kb
Host smart-68c703c1-ea0e-44f8-aaf6-b7ac2bb6d0c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485720663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3485720663
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.4205719378
Short name T754
Test name
Test status
Simulation time 178827014 ps
CPU time 2.64 seconds
Started May 05 01:46:40 PM PDT 24
Finished May 05 01:46:43 PM PDT 24
Peak memory 218068 kb
Host smart-f9bb7dc2-36f0-421f-8f7a-75ce7cb285cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205719378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.4205719378
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3376993347
Short name T526
Test name
Test status
Simulation time 891143238 ps
CPU time 20.33 seconds
Started May 05 01:46:47 PM PDT 24
Finished May 05 01:47:08 PM PDT 24
Peak memory 217952 kb
Host smart-daf7ecfc-0839-4038-9ee7-48a83ccc0d53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376993347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3376993347
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1241234518
Short name T846
Test name
Test status
Simulation time 2928019518 ps
CPU time 18.25 seconds
Started May 05 01:46:45 PM PDT 24
Finished May 05 01:47:04 PM PDT 24
Peak memory 218156 kb
Host smart-ccbd04ec-af3a-4c18-9e88-467d09c4acca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241234518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1241234518
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.4118449529
Short name T594
Test name
Test status
Simulation time 680735586 ps
CPU time 10.04 seconds
Started May 05 01:46:38 PM PDT 24
Finished May 05 01:46:49 PM PDT 24
Peak memory 218016 kb
Host smart-60f04dcd-77ac-4978-91d1-6fc5f3637306
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118449529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
4118449529
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.2450244389
Short name T652
Test name
Test status
Simulation time 570062591 ps
CPU time 11.21 seconds
Started May 05 01:46:37 PM PDT 24
Finished May 05 01:46:49 PM PDT 24
Peak memory 218064 kb
Host smart-fcd4a03c-94ff-49f5-8d80-1d2c46093630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450244389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.2450244389
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.4220278407
Short name T419
Test name
Test status
Simulation time 52807689 ps
CPU time 2.93 seconds
Started May 05 01:46:50 PM PDT 24
Finished May 05 01:46:54 PM PDT 24
Peak memory 214868 kb
Host smart-d0847e3d-2644-416a-b7b3-0f235c1f6f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220278407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.4220278407
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3969606460
Short name T389
Test name
Test status
Simulation time 1569057423 ps
CPU time 19.32 seconds
Started May 05 01:46:51 PM PDT 24
Finished May 05 01:47:11 PM PDT 24
Peak memory 251120 kb
Host smart-97ebcc57-d2ec-495e-ac64-bd271e884452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969606460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3969606460
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.2750695337
Short name T253
Test name
Test status
Simulation time 168929332 ps
CPU time 4.75 seconds
Started May 05 01:46:45 PM PDT 24
Finished May 05 01:46:51 PM PDT 24
Peak memory 223164 kb
Host smart-fd057c29-d68a-43f4-acbb-573084b7e13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750695337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2750695337
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3312559525
Short name T642
Test name
Test status
Simulation time 1731821472 ps
CPU time 82.4 seconds
Started May 05 01:46:42 PM PDT 24
Finished May 05 01:48:05 PM PDT 24
Peak memory 372104 kb
Host smart-4cbb2971-b154-4f37-8fd4-8349e865e96c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312559525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3312559525
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1808718119
Short name T281
Test name
Test status
Simulation time 39175190 ps
CPU time 0.92 seconds
Started May 05 01:46:44 PM PDT 24
Finished May 05 01:46:45 PM PDT 24
Peak memory 211828 kb
Host smart-1a6e00f0-c631-4ada-afc0-698a0d1967c1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808718119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1808718119
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.3764296752
Short name T565
Test name
Test status
Simulation time 19857217 ps
CPU time 0.88 seconds
Started May 05 01:46:45 PM PDT 24
Finished May 05 01:46:47 PM PDT 24
Peak memory 209696 kb
Host smart-ca9002ca-b7a4-4ae2-9feb-5bc29aa7e100
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764296752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.3764296752
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.958715159
Short name T546
Test name
Test status
Simulation time 611039894 ps
CPU time 13.24 seconds
Started May 05 01:46:44 PM PDT 24
Finished May 05 01:46:58 PM PDT 24
Peak memory 218192 kb
Host smart-0efaa35d-6dd1-46c4-bd24-e59339ee6752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958715159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.958715159
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.2309160888
Short name T382
Test name
Test status
Simulation time 139386603 ps
CPU time 1.56 seconds
Started May 05 01:46:47 PM PDT 24
Finished May 05 01:46:49 PM PDT 24
Peak memory 209648 kb
Host smart-545f01a0-2e7e-4ea2-a3e0-f8866500d35c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309160888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.2309160888
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.34793629
Short name T295
Test name
Test status
Simulation time 173678878 ps
CPU time 3.68 seconds
Started May 05 01:46:44 PM PDT 24
Finished May 05 01:46:48 PM PDT 24
Peak memory 218092 kb
Host smart-70de864c-30d9-4aa5-96ad-a73696bef41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34793629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.34793629
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1500832905
Short name T274
Test name
Test status
Simulation time 490495720 ps
CPU time 11.51 seconds
Started May 05 01:46:47 PM PDT 24
Finished May 05 01:46:59 PM PDT 24
Peak memory 226236 kb
Host smart-6ff62b51-c8d8-4c6f-883b-b7dfd1cfe09b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500832905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1500832905
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2178254617
Short name T301
Test name
Test status
Simulation time 463336387 ps
CPU time 10.44 seconds
Started May 05 01:46:48 PM PDT 24
Finished May 05 01:46:59 PM PDT 24
Peak memory 218152 kb
Host smart-ba566dee-ef5f-4517-9b4d-ef0982309599
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178254617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2178254617
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.469025054
Short name T439
Test name
Test status
Simulation time 896533196 ps
CPU time 10.72 seconds
Started May 05 01:46:47 PM PDT 24
Finished May 05 01:46:58 PM PDT 24
Peak memory 218072 kb
Host smart-cfb7e738-b84b-40ac-bb51-d3bfd763476a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469025054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.469025054
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1334214965
Short name T330
Test name
Test status
Simulation time 230344159 ps
CPU time 6 seconds
Started May 05 01:46:44 PM PDT 24
Finished May 05 01:46:50 PM PDT 24
Peak memory 218216 kb
Host smart-731d6b55-ba23-47dd-9a82-2a5d7c99b339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334214965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1334214965
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1478755919
Short name T710
Test name
Test status
Simulation time 74705647 ps
CPU time 1.1 seconds
Started May 05 01:46:46 PM PDT 24
Finished May 05 01:46:48 PM PDT 24
Peak memory 213212 kb
Host smart-c8b35eb0-0792-436c-b73d-d47a3c904b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478755919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1478755919
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.4145013548
Short name T423
Test name
Test status
Simulation time 661204417 ps
CPU time 31.41 seconds
Started May 05 01:46:46 PM PDT 24
Finished May 05 01:47:18 PM PDT 24
Peak memory 251004 kb
Host smart-d5c9607c-f510-4bd8-8c28-caa9caa7c76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145013548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.4145013548
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2594885825
Short name T413
Test name
Test status
Simulation time 67424092 ps
CPU time 3.71 seconds
Started May 05 01:46:51 PM PDT 24
Finished May 05 01:46:55 PM PDT 24
Peak memory 218076 kb
Host smart-0b93d940-6dcb-452b-9777-705589f16348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594885825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2594885825
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.4078013298
Short name T298
Test name
Test status
Simulation time 5141388994 ps
CPU time 59.1 seconds
Started May 05 01:46:43 PM PDT 24
Finished May 05 01:47:43 PM PDT 24
Peak memory 271800 kb
Host smart-828b488b-a24b-494d-b04f-ea85a462bfb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078013298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.4078013298
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.1287996125
Short name T140
Test name
Test status
Simulation time 208062546387 ps
CPU time 1622.92 seconds
Started May 05 01:46:45 PM PDT 24
Finished May 05 02:13:49 PM PDT 24
Peak memory 513396 kb
Host smart-f0eacd1a-af91-4f2e-97e2-6465ebf39e7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1287996125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.1287996125
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3234463478
Short name T299
Test name
Test status
Simulation time 13688340 ps
CPU time 0.92 seconds
Started May 05 01:46:46 PM PDT 24
Finished May 05 01:46:47 PM PDT 24
Peak memory 211672 kb
Host smart-8d2031bb-4663-4145-adb0-d194333e5dbf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234463478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.3234463478
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3057810030
Short name T757
Test name
Test status
Simulation time 69624896 ps
CPU time 1.04 seconds
Started May 05 01:46:50 PM PDT 24
Finished May 05 01:46:52 PM PDT 24
Peak memory 209644 kb
Host smart-97692e03-63aa-4547-ad32-95daa2b716ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057810030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3057810030
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2452188691
Short name T272
Test name
Test status
Simulation time 436258941 ps
CPU time 14.48 seconds
Started May 05 01:46:47 PM PDT 24
Finished May 05 01:47:02 PM PDT 24
Peak memory 218064 kb
Host smart-4bf70192-d643-4eec-83e1-c832ef1b775e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452188691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2452188691
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3890995466
Short name T31
Test name
Test status
Simulation time 2416037447 ps
CPU time 7.17 seconds
Started May 05 01:46:47 PM PDT 24
Finished May 05 01:46:55 PM PDT 24
Peak memory 209808 kb
Host smart-9c95c331-4cb3-4880-a916-b6ffc0efe93f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890995466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3890995466
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.4280295781
Short name T224
Test name
Test status
Simulation time 58226572 ps
CPU time 1.92 seconds
Started May 05 01:46:47 PM PDT 24
Finished May 05 01:46:50 PM PDT 24
Peak memory 218156 kb
Host smart-5507a290-3923-42d1-aee5-9bffad4f381b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280295781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.4280295781
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.476039930
Short name T802
Test name
Test status
Simulation time 1269494345 ps
CPU time 13.2 seconds
Started May 05 01:46:53 PM PDT 24
Finished May 05 01:47:07 PM PDT 24
Peak memory 226192 kb
Host smart-77da98ad-bb8f-46ce-9278-e4ba4064442d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476039930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.476039930
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2628416043
Short name T321
Test name
Test status
Simulation time 988184596 ps
CPU time 11.64 seconds
Started May 05 01:46:56 PM PDT 24
Finished May 05 01:47:08 PM PDT 24
Peak memory 217972 kb
Host smart-14192a64-1ba5-4cb6-94f2-9f9e1e01d4a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628416043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2628416043
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.2052644755
Short name T666
Test name
Test status
Simulation time 600416807 ps
CPU time 12.55 seconds
Started May 05 01:46:52 PM PDT 24
Finished May 05 01:47:06 PM PDT 24
Peak memory 218104 kb
Host smart-8c4ad0f7-d1c1-41e1-b450-0df179148f18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052644755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
2052644755
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.4039901133
Short name T400
Test name
Test status
Simulation time 5014578803 ps
CPU time 10.13 seconds
Started May 05 01:46:46 PM PDT 24
Finished May 05 01:46:57 PM PDT 24
Peak memory 218192 kb
Host smart-1b64fc6b-b950-407c-b9f5-9dbe3bb857f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039901133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.4039901133
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3600790873
Short name T653
Test name
Test status
Simulation time 42702818 ps
CPU time 2.31 seconds
Started May 05 01:46:50 PM PDT 24
Finished May 05 01:46:53 PM PDT 24
Peak memory 213952 kb
Host smart-1b2698ec-c8e9-429d-9623-cedfbccc1ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600790873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3600790873
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.3171353969
Short name T848
Test name
Test status
Simulation time 1093315719 ps
CPU time 33.69 seconds
Started May 05 01:46:52 PM PDT 24
Finished May 05 01:47:26 PM PDT 24
Peak memory 251088 kb
Host smart-f074816f-04eb-468f-b89b-278bba5fd694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171353969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3171353969
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.322485452
Short name T167
Test name
Test status
Simulation time 157728270 ps
CPU time 7.91 seconds
Started May 05 01:46:44 PM PDT 24
Finished May 05 01:46:52 PM PDT 24
Peak memory 246268 kb
Host smart-1222d55d-3278-4ed2-a881-b22c6d915e7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322485452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.322485452
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1696038604
Short name T752
Test name
Test status
Simulation time 1919948038 ps
CPU time 95.96 seconds
Started May 05 01:46:48 PM PDT 24
Finished May 05 01:48:24 PM PDT 24
Peak memory 422052 kb
Host smart-720d92d6-562b-4a6d-ab64-ecea85fdaafb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696038604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1696038604
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2802532864
Short name T384
Test name
Test status
Simulation time 38828792 ps
CPU time 0.92 seconds
Started May 05 01:46:44 PM PDT 24
Finished May 05 01:46:46 PM PDT 24
Peak memory 211704 kb
Host smart-1b7febd8-9d27-4bea-93a4-43572f5995b8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802532864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2802532864
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.28593530
Short name T290
Test name
Test status
Simulation time 17988279 ps
CPU time 0.91 seconds
Started May 05 01:46:51 PM PDT 24
Finished May 05 01:46:52 PM PDT 24
Peak memory 209616 kb
Host smart-84d19576-3bb8-4558-9996-1506ec013afc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28593530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.28593530
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.2616151936
Short name T325
Test name
Test status
Simulation time 866467552 ps
CPU time 23.99 seconds
Started May 05 01:46:54 PM PDT 24
Finished May 05 01:47:19 PM PDT 24
Peak memory 218152 kb
Host smart-ef34c51e-124c-4de3-97a9-e69a0649571d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616151936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2616151936
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.1355512875
Short name T591
Test name
Test status
Simulation time 3779723312 ps
CPU time 26.58 seconds
Started May 05 01:46:50 PM PDT 24
Finished May 05 01:47:17 PM PDT 24
Peak memory 218124 kb
Host smart-ed262f38-8f4e-4be2-afa3-899b66fa40da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355512875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.1355512875
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.771834207
Short name T514
Test name
Test status
Simulation time 487826910 ps
CPU time 2.59 seconds
Started May 05 01:46:47 PM PDT 24
Finished May 05 01:46:51 PM PDT 24
Peak memory 218108 kb
Host smart-e498d137-b9fc-4dfe-9f47-8d64afaafa91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771834207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.771834207
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.4195182103
Short name T455
Test name
Test status
Simulation time 1388682860 ps
CPU time 15.43 seconds
Started May 05 01:46:48 PM PDT 24
Finished May 05 01:47:04 PM PDT 24
Peak memory 219052 kb
Host smart-be350447-181d-499b-a24c-96a8dbdd43a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195182103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.4195182103
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.715217504
Short name T641
Test name
Test status
Simulation time 1042797773 ps
CPU time 11.19 seconds
Started May 05 01:46:53 PM PDT 24
Finished May 05 01:47:05 PM PDT 24
Peak memory 217984 kb
Host smart-1283bf38-5a09-4ef5-9ce0-49102cde530d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715217504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.715217504
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2704911428
Short name T597
Test name
Test status
Simulation time 596011789 ps
CPU time 7.9 seconds
Started May 05 01:46:48 PM PDT 24
Finished May 05 01:46:56 PM PDT 24
Peak memory 218168 kb
Host smart-1d0dfc4c-e594-402f-95fb-9af7980517b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704911428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2704911428
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.261370868
Short name T480
Test name
Test status
Simulation time 173193828 ps
CPU time 5.86 seconds
Started May 05 01:46:46 PM PDT 24
Finished May 05 01:46:53 PM PDT 24
Peak memory 218200 kb
Host smart-58fb6c89-b5a6-4a69-91e0-f6267c591aa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261370868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.261370868
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2448037340
Short name T857
Test name
Test status
Simulation time 194276997 ps
CPU time 3.04 seconds
Started May 05 01:46:47 PM PDT 24
Finished May 05 01:46:51 PM PDT 24
Peak memory 218080 kb
Host smart-490c2171-7ec8-4c2f-8c78-c86d5da88e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448037340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2448037340
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.4094468370
Short name T287
Test name
Test status
Simulation time 256823414 ps
CPU time 21.67 seconds
Started May 05 01:46:51 PM PDT 24
Finished May 05 01:47:13 PM PDT 24
Peak memory 251228 kb
Host smart-e6f63bc8-7eb1-448f-9a50-26dd4c2dda20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094468370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.4094468370
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3361600897
Short name T234
Test name
Test status
Simulation time 83025987 ps
CPU time 4.04 seconds
Started May 05 01:46:45 PM PDT 24
Finished May 05 01:46:50 PM PDT 24
Peak memory 222592 kb
Host smart-af7594f1-fac8-4968-9acd-ffe2517fba7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361600897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3361600897
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.514508471
Short name T864
Test name
Test status
Simulation time 3789109841 ps
CPU time 139.31 seconds
Started May 05 01:46:51 PM PDT 24
Finished May 05 01:49:11 PM PDT 24
Peak memory 272924 kb
Host smart-850d1c1f-852d-40eb-903e-8cb4937a2d67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514508471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.514508471
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3800130795
Short name T850
Test name
Test status
Simulation time 19468227 ps
CPU time 0.93 seconds
Started May 05 01:46:52 PM PDT 24
Finished May 05 01:46:53 PM PDT 24
Peak memory 209680 kb
Host smart-74b9f42b-4f3a-4a11-8ab3-bc6cbba4344c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800130795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3800130795
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2198010679
Short name T820
Test name
Test status
Simulation time 528060946 ps
CPU time 12.98 seconds
Started May 05 01:46:52 PM PDT 24
Finished May 05 01:47:05 PM PDT 24
Peak memory 218116 kb
Host smart-559ee051-1b47-4854-a98f-8464c6614b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198010679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2198010679
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1181357216
Short name T509
Test name
Test status
Simulation time 357695116 ps
CPU time 5.42 seconds
Started May 05 01:46:53 PM PDT 24
Finished May 05 01:47:00 PM PDT 24
Peak memory 209668 kb
Host smart-49da6740-bd8c-415a-a043-7ff07c73fb30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181357216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1181357216
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.4182320743
Short name T468
Test name
Test status
Simulation time 359724402 ps
CPU time 3.24 seconds
Started May 05 01:46:53 PM PDT 24
Finished May 05 01:46:57 PM PDT 24
Peak memory 218116 kb
Host smart-8d2f1e82-b1a1-4d61-8cc2-0b440425a3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182320743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.4182320743
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.503172205
Short name T280
Test name
Test status
Simulation time 1162218072 ps
CPU time 16.41 seconds
Started May 05 01:46:52 PM PDT 24
Finished May 05 01:47:09 PM PDT 24
Peak memory 219064 kb
Host smart-4b12fc41-1b82-41f4-94cb-00a568a7e607
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503172205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.503172205
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.359776774
Short name T190
Test name
Test status
Simulation time 246207017 ps
CPU time 10.79 seconds
Started May 05 01:46:52 PM PDT 24
Finished May 05 01:47:03 PM PDT 24
Peak memory 217984 kb
Host smart-dcd8214d-6547-4144-83fc-c940935fab93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359776774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.359776774
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.1277503337
Short name T475
Test name
Test status
Simulation time 440712902 ps
CPU time 15.62 seconds
Started May 05 01:46:53 PM PDT 24
Finished May 05 01:47:10 PM PDT 24
Peak memory 218168 kb
Host smart-8d8f04ce-08e0-4945-aacf-fab749522dac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277503337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
1277503337
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3958623386
Short name T58
Test name
Test status
Simulation time 1342023137 ps
CPU time 12.77 seconds
Started May 05 01:46:51 PM PDT 24
Finished May 05 01:47:05 PM PDT 24
Peak memory 218148 kb
Host smart-ad6b889b-60fa-4411-abb9-d4503b4a1ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958623386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3958623386
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3317598167
Short name T21
Test name
Test status
Simulation time 16427019 ps
CPU time 1.46 seconds
Started May 05 01:46:55 PM PDT 24
Finished May 05 01:46:57 PM PDT 24
Peak memory 213568 kb
Host smart-055c77f9-cab5-45c4-88a3-db6c6f1d619a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317598167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3317598167
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.840892580
Short name T793
Test name
Test status
Simulation time 1007386602 ps
CPU time 19.42 seconds
Started May 05 01:46:52 PM PDT 24
Finished May 05 01:47:13 PM PDT 24
Peak memory 249408 kb
Host smart-17e8b604-45c4-4586-b141-a2594bb2362e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840892580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.840892580
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.1710200270
Short name T763
Test name
Test status
Simulation time 238784391 ps
CPU time 3.44 seconds
Started May 05 01:46:55 PM PDT 24
Finished May 05 01:47:00 PM PDT 24
Peak memory 226608 kb
Host smart-328bb0ed-7f8b-4d64-9304-ab44ca8b380c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710200270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1710200270
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.3825205472
Short name T699
Test name
Test status
Simulation time 7481734724 ps
CPU time 132.43 seconds
Started May 05 01:46:50 PM PDT 24
Finished May 05 01:49:03 PM PDT 24
Peak memory 275760 kb
Host smart-425eebf8-7c97-4d89-a85c-a6646392a388
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825205472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.3825205472
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1816483640
Short name T221
Test name
Test status
Simulation time 17633825 ps
CPU time 0.9 seconds
Started May 05 01:46:52 PM PDT 24
Finished May 05 01:46:54 PM PDT 24
Peak memory 211744 kb
Host smart-5c35c9a6-0f51-4393-a743-5fd6a439531e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816483640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1816483640
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1874641647
Short name T575
Test name
Test status
Simulation time 21839371 ps
CPU time 0.99 seconds
Started May 05 01:46:53 PM PDT 24
Finished May 05 01:46:55 PM PDT 24
Peak memory 209688 kb
Host smart-c8a7ec77-3722-4612-93aa-627684176b90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874641647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1874641647
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2511433521
Short name T278
Test name
Test status
Simulation time 1346780720 ps
CPU time 12.22 seconds
Started May 05 01:46:53 PM PDT 24
Finished May 05 01:47:06 PM PDT 24
Peak memory 218172 kb
Host smart-72274505-55b3-4ca9-bf9f-79e66659eacc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511433521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2511433521
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1291182580
Short name T525
Test name
Test status
Simulation time 72257670 ps
CPU time 1.73 seconds
Started May 05 01:46:54 PM PDT 24
Finished May 05 01:46:57 PM PDT 24
Peak memory 209684 kb
Host smart-b8532be3-c220-4a17-8659-c28f9ff58680
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291182580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1291182580
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3325817172
Short name T479
Test name
Test status
Simulation time 136712519 ps
CPU time 2 seconds
Started May 05 01:46:56 PM PDT 24
Finished May 05 01:46:59 PM PDT 24
Peak memory 217940 kb
Host smart-a8762669-27c5-4628-a3a8-89d82150f724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325817172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3325817172
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.160645523
Short name T427
Test name
Test status
Simulation time 5380474787 ps
CPU time 22.07 seconds
Started May 05 01:46:52 PM PDT 24
Finished May 05 01:47:15 PM PDT 24
Peak memory 226352 kb
Host smart-45377b88-c5c6-4e50-a8f9-4d56fee74a2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160645523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.160645523
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1957240159
Short name T524
Test name
Test status
Simulation time 343790977 ps
CPU time 14.21 seconds
Started May 05 01:46:50 PM PDT 24
Finished May 05 01:47:05 PM PDT 24
Peak memory 218136 kb
Host smart-27ee3c64-9be1-4bf3-8be7-960c9b8b0ea1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957240159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1957240159
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.226995671
Short name T385
Test name
Test status
Simulation time 287973003 ps
CPU time 7.9 seconds
Started May 05 01:46:51 PM PDT 24
Finished May 05 01:46:59 PM PDT 24
Peak memory 218192 kb
Host smart-f504f5c8-8fe3-443a-9491-6b240a7d05c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226995671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.226995671
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1481184577
Short name T354
Test name
Test status
Simulation time 2007740733 ps
CPU time 11.57 seconds
Started May 05 01:46:51 PM PDT 24
Finished May 05 01:47:03 PM PDT 24
Peak memory 218228 kb
Host smart-1e2c58a2-8dc4-40e2-a392-4b4776b9c6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481184577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1481184577
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.3766382701
Short name T500
Test name
Test status
Simulation time 45372033 ps
CPU time 2.7 seconds
Started May 05 01:46:51 PM PDT 24
Finished May 05 01:46:54 PM PDT 24
Peak memory 214288 kb
Host smart-38d39602-0ce9-4e7e-ad19-e902d3c2283b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766382701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3766382701
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1435318661
Short name T765
Test name
Test status
Simulation time 5846136361 ps
CPU time 26.77 seconds
Started May 05 01:46:51 PM PDT 24
Finished May 05 01:47:18 PM PDT 24
Peak memory 251172 kb
Host smart-e66a8fd9-2916-4b57-a646-0239ebdc061d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435318661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1435318661
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2533355674
Short name T667
Test name
Test status
Simulation time 635163547 ps
CPU time 2.7 seconds
Started May 05 01:46:53 PM PDT 24
Finished May 05 01:46:57 PM PDT 24
Peak memory 217956 kb
Host smart-5370c420-9741-4efb-950f-c739a347afb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533355674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2533355674
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3929797593
Short name T42
Test name
Test status
Simulation time 40907909 ps
CPU time 0.99 seconds
Started May 05 01:46:55 PM PDT 24
Finished May 05 01:46:57 PM PDT 24
Peak memory 211808 kb
Host smart-8d0338fe-3751-4856-b988-3bb20f94f612
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929797593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3929797593
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1925421499
Short name T87
Test name
Test status
Simulation time 66736242 ps
CPU time 0.92 seconds
Started May 05 01:46:58 PM PDT 24
Finished May 05 01:47:00 PM PDT 24
Peak memory 209660 kb
Host smart-f5ded8e6-81d8-4fbe-87ac-c38b22a5400f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925421499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1925421499
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2447002558
Short name T214
Test name
Test status
Simulation time 553374651 ps
CPU time 14.25 seconds
Started May 05 01:46:58 PM PDT 24
Finished May 05 01:47:13 PM PDT 24
Peak memory 218076 kb
Host smart-cf3787ca-53f3-4b0d-9e84-2762811234be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447002558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2447002558
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.212483196
Short name T693
Test name
Test status
Simulation time 49454792 ps
CPU time 1.97 seconds
Started May 05 01:46:54 PM PDT 24
Finished May 05 01:46:57 PM PDT 24
Peak memory 209620 kb
Host smart-682c6d77-a06c-4ec8-afe1-ba7896ec974e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212483196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.212483196
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.30445441
Short name T340
Test name
Test status
Simulation time 335600926 ps
CPU time 3.45 seconds
Started May 05 01:46:49 PM PDT 24
Finished May 05 01:46:53 PM PDT 24
Peak memory 218104 kb
Host smart-17ed73bf-6580-4dd0-a99e-ecdc87d28ef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=30445441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.30445441
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1332042225
Short name T624
Test name
Test status
Simulation time 1574162141 ps
CPU time 12.72 seconds
Started May 05 01:46:55 PM PDT 24
Finished May 05 01:47:09 PM PDT 24
Peak memory 218464 kb
Host smart-ab42c4fe-5681-4231-9b49-0a62f10d7b20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332042225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1332042225
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3817737500
Short name T683
Test name
Test status
Simulation time 470128138 ps
CPU time 16.87 seconds
Started May 05 01:46:54 PM PDT 24
Finished May 05 01:47:12 PM PDT 24
Peak memory 218056 kb
Host smart-0877daa0-3840-4c93-9282-36d823d600d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817737500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3817737500
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.3404736128
Short name T226
Test name
Test status
Simulation time 487212055 ps
CPU time 8.57 seconds
Started May 05 01:46:53 PM PDT 24
Finished May 05 01:47:03 PM PDT 24
Peak memory 218128 kb
Host smart-360b164c-d5bd-4f74-bf9b-7b4a940afc84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404736128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
3404736128
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3265562828
Short name T739
Test name
Test status
Simulation time 399407313 ps
CPU time 7.55 seconds
Started May 05 01:46:56 PM PDT 24
Finished May 05 01:47:05 PM PDT 24
Peak memory 218124 kb
Host smart-2677fd03-8b46-4475-b57f-7f77363a85ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265562828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3265562828
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2846418579
Short name T657
Test name
Test status
Simulation time 61622616 ps
CPU time 3.04 seconds
Started May 05 01:46:56 PM PDT 24
Finished May 05 01:47:00 PM PDT 24
Peak memory 218068 kb
Host smart-a03be3fd-0816-4f5a-be07-3682e956100e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846418579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2846418579
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.808781631
Short name T346
Test name
Test status
Simulation time 639135102 ps
CPU time 20.69 seconds
Started May 05 01:46:51 PM PDT 24
Finished May 05 01:47:13 PM PDT 24
Peak memory 251148 kb
Host smart-51382e12-3e95-458a-b9a1-d057527d1d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808781631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.808781631
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1011336854
Short name T768
Test name
Test status
Simulation time 113767418 ps
CPU time 3.76 seconds
Started May 05 01:46:52 PM PDT 24
Finished May 05 01:46:57 PM PDT 24
Peak memory 222716 kb
Host smart-47946a1f-4f32-42a1-8cbc-1608f6681f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011336854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1011336854
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1656160764
Short name T462
Test name
Test status
Simulation time 7793242086 ps
CPU time 236.6 seconds
Started May 05 01:46:53 PM PDT 24
Finished May 05 01:50:51 PM PDT 24
Peak memory 283448 kb
Host smart-d7bd48ca-aff6-4cc2-a53f-b27029a58af2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656160764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1656160764
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.4133151550
Short name T590
Test name
Test status
Simulation time 41667458 ps
CPU time 1 seconds
Started May 05 01:46:53 PM PDT 24
Finished May 05 01:46:55 PM PDT 24
Peak memory 211728 kb
Host smart-b83d5dff-c201-4737-a89a-5ca0df1a67fd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133151550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.4133151550
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.2022839915
Short name T530
Test name
Test status
Simulation time 74277405 ps
CPU time 1.18 seconds
Started May 05 01:46:56 PM PDT 24
Finished May 05 01:46:58 PM PDT 24
Peak memory 209712 kb
Host smart-c3eac2a4-e247-43b0-a485-d2779a09b982
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022839915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2022839915
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3613479806
Short name T827
Test name
Test status
Simulation time 451303243 ps
CPU time 14.52 seconds
Started May 05 01:46:53 PM PDT 24
Finished May 05 01:47:09 PM PDT 24
Peak memory 218036 kb
Host smart-4226f1b3-d4a4-4539-abad-9d1d3548caa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613479806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3613479806
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3984848451
Short name T12
Test name
Test status
Simulation time 168935211 ps
CPU time 5.03 seconds
Started May 05 01:46:55 PM PDT 24
Finished May 05 01:47:01 PM PDT 24
Peak memory 209608 kb
Host smart-acdd6339-cc3c-455f-ae29-a18efd05390c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984848451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3984848451
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2388285594
Short name T766
Test name
Test status
Simulation time 45228943 ps
CPU time 1.65 seconds
Started May 05 01:46:58 PM PDT 24
Finished May 05 01:47:00 PM PDT 24
Peak memory 218072 kb
Host smart-d24ffc63-afb2-4bcf-bf7e-a5c3f0676f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2388285594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2388285594
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.4030496971
Short name T736
Test name
Test status
Simulation time 393964661 ps
CPU time 18.36 seconds
Started May 05 01:46:55 PM PDT 24
Finished May 05 01:47:15 PM PDT 24
Peak memory 218428 kb
Host smart-599a2c45-fdff-413c-a8c0-4f4599328d9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030496971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.4030496971
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3290361340
Short name T352
Test name
Test status
Simulation time 363951700 ps
CPU time 15.05 seconds
Started May 05 01:46:53 PM PDT 24
Finished May 05 01:47:10 PM PDT 24
Peak memory 218104 kb
Host smart-c165b7d5-c138-47f9-851c-f4f9f78b608f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290361340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3290361340
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.75804663
Short name T356
Test name
Test status
Simulation time 1650479932 ps
CPU time 10.01 seconds
Started May 05 01:46:55 PM PDT 24
Finished May 05 01:47:05 PM PDT 24
Peak memory 218136 kb
Host smart-9e7bbaf1-46e4-47bb-8822-3c785f035505
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75804663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.75804663
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.1031802717
Short name T496
Test name
Test status
Simulation time 1144963668 ps
CPU time 10.74 seconds
Started May 05 01:46:58 PM PDT 24
Finished May 05 01:47:10 PM PDT 24
Peak memory 218124 kb
Host smart-c55ab4de-a381-4dea-ab34-7a207010015f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031802717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1031802717
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.347287573
Short name T543
Test name
Test status
Simulation time 73636438 ps
CPU time 1.43 seconds
Started May 05 01:46:57 PM PDT 24
Finished May 05 01:46:59 PM PDT 24
Peak memory 213516 kb
Host smart-3493249d-d9aa-434d-83bb-81bc7099400c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347287573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.347287573
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3063664385
Short name T691
Test name
Test status
Simulation time 777221794 ps
CPU time 23.57 seconds
Started May 05 01:46:55 PM PDT 24
Finished May 05 01:47:20 PM PDT 24
Peak memory 251144 kb
Host smart-10b1cf13-eb87-436e-a0a3-9a65f6b289bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063664385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3063664385
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.1076678979
Short name T162
Test name
Test status
Simulation time 271814434 ps
CPU time 6.51 seconds
Started May 05 01:46:56 PM PDT 24
Finished May 05 01:47:03 PM PDT 24
Peak memory 243652 kb
Host smart-b45ecd64-b720-4661-89be-fc8d641fb56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076678979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.1076678979
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3308921931
Short name T168
Test name
Test status
Simulation time 5198518467 ps
CPU time 66.74 seconds
Started May 05 01:46:54 PM PDT 24
Finished May 05 01:48:02 PM PDT 24
Peak memory 251184 kb
Host smart-bc5ff407-9b94-426c-a8c2-a71142192f19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308921931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3308921931
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3718943857
Short name T724
Test name
Test status
Simulation time 14701211 ps
CPU time 0.92 seconds
Started May 05 01:46:55 PM PDT 24
Finished May 05 01:46:56 PM PDT 24
Peak memory 211724 kb
Host smart-41bf7eaa-ad58-40e7-9506-7c44b696849b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718943857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3718943857
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1272598371
Short name T730
Test name
Test status
Simulation time 14259844 ps
CPU time 1.03 seconds
Started May 05 01:45:47 PM PDT 24
Finished May 05 01:45:49 PM PDT 24
Peak memory 209672 kb
Host smart-1bd2ca37-8272-4968-ae42-afcdd9a0a7b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272598371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1272598371
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.139709567
Short name T307
Test name
Test status
Simulation time 457846799 ps
CPU time 18.13 seconds
Started May 05 01:45:45 PM PDT 24
Finished May 05 01:46:05 PM PDT 24
Peak memory 218088 kb
Host smart-9af84653-8b6b-45a1-8846-c2df45658830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139709567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.139709567
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.393053332
Short name T726
Test name
Test status
Simulation time 141550683 ps
CPU time 1.46 seconds
Started May 05 01:46:07 PM PDT 24
Finished May 05 01:46:09 PM PDT 24
Peak memory 209652 kb
Host smart-42593f2d-0afd-4b1c-9585-6ccffe0a9491
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393053332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.393053332
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.2982019968
Short name T518
Test name
Test status
Simulation time 5470817338 ps
CPU time 40.66 seconds
Started May 05 01:45:38 PM PDT 24
Finished May 05 01:46:19 PM PDT 24
Peak memory 218076 kb
Host smart-c289b07e-c72e-4f9d-be96-4a1800609b7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982019968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.2982019968
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.508204592
Short name T342
Test name
Test status
Simulation time 4949838246 ps
CPU time 19.02 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:46:04 PM PDT 24
Peak memory 217948 kb
Host smart-a0847ae6-f64c-4991-90dc-2989a3068857
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508204592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.508204592
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.824801479
Short name T535
Test name
Test status
Simulation time 253282918 ps
CPU time 2.99 seconds
Started May 05 01:45:32 PM PDT 24
Finished May 05 01:45:36 PM PDT 24
Peak memory 218140 kb
Host smart-63108f9c-7c50-4003-bbbb-4c34e18a71c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824801479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.824801479
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3922072860
Short name T621
Test name
Test status
Simulation time 4607727594 ps
CPU time 18.98 seconds
Started May 05 01:45:35 PM PDT 24
Finished May 05 01:45:54 PM PDT 24
Peak memory 214216 kb
Host smart-1225efb0-ed0d-45af-9dd7-68ebf44c8592
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922072860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3922072860
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.13259747
Short name T552
Test name
Test status
Simulation time 1124573487 ps
CPU time 6.08 seconds
Started May 05 01:45:27 PM PDT 24
Finished May 05 01:45:34 PM PDT 24
Peak memory 213588 kb
Host smart-75ccf81d-4dc9-4932-a7a0-1b1e691c8c68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13259747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.13259747
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.465671688
Short name T374
Test name
Test status
Simulation time 3110677421 ps
CPU time 64.76 seconds
Started May 05 01:45:33 PM PDT 24
Finished May 05 01:46:38 PM PDT 24
Peak memory 278032 kb
Host smart-220137de-4e2e-4ad3-b031-b8067052ab11
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465671688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_state_failure.465671688
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3519386178
Short name T45
Test name
Test status
Simulation time 2803863746 ps
CPU time 15.96 seconds
Started May 05 01:45:42 PM PDT 24
Finished May 05 01:46:00 PM PDT 24
Peak memory 247400 kb
Host smart-5a97fc8f-7372-446e-b45c-7ecb08b6a3f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519386178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.3519386178
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2906045841
Short name T408
Test name
Test status
Simulation time 389419993 ps
CPU time 1.96 seconds
Started May 05 01:45:44 PM PDT 24
Finished May 05 01:45:49 PM PDT 24
Peak memory 218088 kb
Host smart-db5ed826-8df4-4448-ace7-c6eb2937cb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906045841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2906045841
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3376167472
Short name T84
Test name
Test status
Simulation time 2921095822 ps
CPU time 21.76 seconds
Started May 05 01:45:29 PM PDT 24
Finished May 05 01:45:52 PM PDT 24
Peak memory 215016 kb
Host smart-0ac8aa6a-ac86-4b6b-ba07-dfa6e1987480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376167472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3376167472
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2864883914
Short name T86
Test name
Test status
Simulation time 427321556 ps
CPU time 31.39 seconds
Started May 05 01:45:32 PM PDT 24
Finished May 05 01:46:04 PM PDT 24
Peak memory 269404 kb
Host smart-a9313a9b-5b74-49f3-ad30-4e6a823ce280
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864883914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2864883914
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1252546112
Short name T660
Test name
Test status
Simulation time 1264889924 ps
CPU time 14.63 seconds
Started May 05 01:45:51 PM PDT 24
Finished May 05 01:46:06 PM PDT 24
Peak memory 219044 kb
Host smart-d497a316-8e0f-45eb-b241-f2e6b9df8a8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252546112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1252546112
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1943107561
Short name T402
Test name
Test status
Simulation time 760986201 ps
CPU time 12.65 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:45:58 PM PDT 24
Peak memory 218064 kb
Host smart-ed3ccdfb-d8ed-4d82-a5ee-15e06527e11c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943107561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1943107561
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.983919908
Short name T674
Test name
Test status
Simulation time 628414111 ps
CPU time 6.89 seconds
Started May 05 01:45:35 PM PDT 24
Finished May 05 01:45:42 PM PDT 24
Peak memory 218028 kb
Host smart-3b890ca2-922d-4617-a88d-088b0667491f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983919908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.983919908
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2794574089
Short name T319
Test name
Test status
Simulation time 2415893082 ps
CPU time 8.9 seconds
Started May 05 01:45:28 PM PDT 24
Finished May 05 01:45:38 PM PDT 24
Peak memory 218248 kb
Host smart-a997f7fe-be72-48e5-aec8-4e0890827566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794574089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2794574089
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.2804189830
Short name T421
Test name
Test status
Simulation time 93187505 ps
CPU time 3.12 seconds
Started May 05 01:45:33 PM PDT 24
Finished May 05 01:45:36 PM PDT 24
Peak memory 213640 kb
Host smart-0e452dcd-41a5-4e87-8caf-f2a82ae76318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804189830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.2804189830
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3443477750
Short name T404
Test name
Test status
Simulation time 2628164622 ps
CPU time 18.65 seconds
Started May 05 01:45:28 PM PDT 24
Finished May 05 01:45:47 PM PDT 24
Peak memory 251016 kb
Host smart-c33c4357-146b-4eae-bb32-162304cd7650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443477750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3443477750
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.610423646
Short name T631
Test name
Test status
Simulation time 61612829 ps
CPU time 7.43 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:45:52 PM PDT 24
Peak memory 251128 kb
Host smart-71df930d-63a1-4fec-9184-f541b847fccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610423646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.610423646
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1861741970
Short name T426
Test name
Test status
Simulation time 4473612210 ps
CPU time 65.75 seconds
Started May 05 01:45:37 PM PDT 24
Finished May 05 01:46:43 PM PDT 24
Peak memory 279080 kb
Host smart-d10fe833-0400-4f9c-9bb0-74e41efa5bc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861741970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1861741970
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.383486379
Short name T859
Test name
Test status
Simulation time 37230295 ps
CPU time 0.86 seconds
Started May 05 01:45:46 PM PDT 24
Finished May 05 01:45:49 PM PDT 24
Peak memory 208560 kb
Host smart-b6df6e47-213f-40b1-ae18-bcd4ccbcbba2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383486379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.383486379
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1534104325
Short name T607
Test name
Test status
Simulation time 1120881720 ps
CPU time 11.59 seconds
Started May 05 01:46:53 PM PDT 24
Finished May 05 01:47:05 PM PDT 24
Peak memory 218108 kb
Host smart-0de4f41c-9898-408b-9a82-c65d171607a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534104325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1534104325
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3731496019
Short name T725
Test name
Test status
Simulation time 2004087614 ps
CPU time 13.31 seconds
Started May 05 01:46:59 PM PDT 24
Finished May 05 01:47:13 PM PDT 24
Peak memory 209672 kb
Host smart-98f71cb1-1001-4a55-b72d-4b95258d74fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731496019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3731496019
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3466361509
Short name T411
Test name
Test status
Simulation time 36591488 ps
CPU time 2.56 seconds
Started May 05 01:46:55 PM PDT 24
Finished May 05 01:46:58 PM PDT 24
Peak memory 218260 kb
Host smart-96a7eb8f-6a2e-4d08-b730-75249b3d4042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466361509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3466361509
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2551802356
Short name T414
Test name
Test status
Simulation time 1033257008 ps
CPU time 14.2 seconds
Started May 05 01:46:55 PM PDT 24
Finished May 05 01:47:10 PM PDT 24
Peak memory 218968 kb
Host smart-bf576cd2-fb30-4a83-a2dd-78bf1d1ae8ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551802356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2551802356
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2589889690
Short name T473
Test name
Test status
Simulation time 1609933521 ps
CPU time 10.2 seconds
Started May 05 01:46:59 PM PDT 24
Finished May 05 01:47:10 PM PDT 24
Peak memory 218080 kb
Host smart-b6d7574d-9058-46cc-911c-85238b3e42a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589889690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2589889690
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3629725949
Short name T399
Test name
Test status
Simulation time 363083170 ps
CPU time 6.38 seconds
Started May 05 01:46:58 PM PDT 24
Finished May 05 01:47:05 PM PDT 24
Peak memory 218076 kb
Host smart-64abd916-ae73-4410-9d95-ca785ccb7277
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629725949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3629725949
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.2092635290
Short name T870
Test name
Test status
Simulation time 276763052 ps
CPU time 10.88 seconds
Started May 05 01:46:56 PM PDT 24
Finished May 05 01:47:08 PM PDT 24
Peak memory 218120 kb
Host smart-8fe2566a-edc0-4107-b51a-c89b223e67cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092635290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.2092635290
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1022187033
Short name T66
Test name
Test status
Simulation time 41933089 ps
CPU time 1.91 seconds
Started May 05 01:46:53 PM PDT 24
Finished May 05 01:46:56 PM PDT 24
Peak memory 213956 kb
Host smart-73b36dce-dc16-4314-8304-db8dfe53f108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022187033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1022187033
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.411069904
Short name T255
Test name
Test status
Simulation time 345149842 ps
CPU time 29.29 seconds
Started May 05 01:46:58 PM PDT 24
Finished May 05 01:47:28 PM PDT 24
Peak memory 249156 kb
Host smart-c1691ad1-3fad-4fa9-8177-1ebdf3f223ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411069904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.411069904
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.262172305
Short name T390
Test name
Test status
Simulation time 405518875 ps
CPU time 3.93 seconds
Started May 05 01:46:56 PM PDT 24
Finished May 05 01:47:01 PM PDT 24
Peak memory 221900 kb
Host smart-758b20fb-e49e-4a36-b194-8d849aae4a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262172305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.262172305
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.259566742
Short name T29
Test name
Test status
Simulation time 1339044308 ps
CPU time 57.2 seconds
Started May 05 01:46:56 PM PDT 24
Finished May 05 01:47:54 PM PDT 24
Peak memory 248920 kb
Host smart-c8426ede-2cd1-4541-b3ca-41172b1df1e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259566742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.259566742
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1866574389
Short name T297
Test name
Test status
Simulation time 15706376 ps
CPU time 1.1 seconds
Started May 05 01:46:53 PM PDT 24
Finished May 05 01:46:56 PM PDT 24
Peak memory 211788 kb
Host smart-a71fe3e7-d479-45d4-a01f-a96b34a27dfc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866574389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.1866574389
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2392014250
Short name T308
Test name
Test status
Simulation time 19647164 ps
CPU time 0.87 seconds
Started May 05 01:47:00 PM PDT 24
Finished May 05 01:47:01 PM PDT 24
Peak memory 209568 kb
Host smart-008a03ad-890a-4c59-b5e5-88f65fe15815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392014250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2392014250
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.1360444913
Short name T367
Test name
Test status
Simulation time 244146752 ps
CPU time 11.02 seconds
Started May 05 01:46:59 PM PDT 24
Finished May 05 01:47:11 PM PDT 24
Peak memory 218008 kb
Host smart-ce2139f4-59fc-4aac-a5df-0a0304f7429c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360444913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.1360444913
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1443611839
Short name T764
Test name
Test status
Simulation time 3649155225 ps
CPU time 6.35 seconds
Started May 05 01:47:11 PM PDT 24
Finished May 05 01:47:18 PM PDT 24
Peak memory 209780 kb
Host smart-3be6fb0e-cf0e-489c-b0a5-9b5fc690082d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443611839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1443611839
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1110447525
Short name T566
Test name
Test status
Simulation time 65598588 ps
CPU time 2.47 seconds
Started May 05 01:46:59 PM PDT 24
Finished May 05 01:47:02 PM PDT 24
Peak memory 218132 kb
Host smart-3c775c9f-2b59-4cac-b5ab-c89f237ec940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110447525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1110447525
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3946267768
Short name T776
Test name
Test status
Simulation time 1683649947 ps
CPU time 16.36 seconds
Started May 05 01:46:59 PM PDT 24
Finished May 05 01:47:16 PM PDT 24
Peak memory 226220 kb
Host smart-b4c4a538-5f08-4676-8e70-4a40d6820f91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946267768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3946267768
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.387030148
Short name T493
Test name
Test status
Simulation time 2793727721 ps
CPU time 14.78 seconds
Started May 05 01:47:06 PM PDT 24
Finished May 05 01:47:21 PM PDT 24
Peak memory 218172 kb
Host smart-2b9abb4f-dcf1-4121-9ab2-42b871a9d26d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387030148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_di
gest.387030148
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2441931686
Short name T747
Test name
Test status
Simulation time 1395902860 ps
CPU time 9.16 seconds
Started May 05 01:47:01 PM PDT 24
Finished May 05 01:47:11 PM PDT 24
Peak memory 218096 kb
Host smart-951291bc-0cec-4119-a2ff-ef8a80a98b42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441931686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2441931686
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.4190459067
Short name T201
Test name
Test status
Simulation time 233179367 ps
CPU time 8.86 seconds
Started May 05 01:47:05 PM PDT 24
Finished May 05 01:47:14 PM PDT 24
Peak memory 218400 kb
Host smart-c936aafe-2755-48f5-b5fb-8c36877e45d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190459067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.4190459067
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.14230954
Short name T539
Test name
Test status
Simulation time 209135453 ps
CPU time 1.84 seconds
Started May 05 01:46:59 PM PDT 24
Finished May 05 01:47:02 PM PDT 24
Peak memory 213744 kb
Host smart-38181bdb-d2b2-42ea-ac3c-bb05e70ac183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14230954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.14230954
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.3395815299
Short name T734
Test name
Test status
Simulation time 248018941 ps
CPU time 28.86 seconds
Started May 05 01:47:05 PM PDT 24
Finished May 05 01:47:34 PM PDT 24
Peak memory 251080 kb
Host smart-496a3cad-04f1-4c27-b7db-629b58f826fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395815299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3395815299
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.4155085151
Short name T569
Test name
Test status
Simulation time 248595432 ps
CPU time 9.03 seconds
Started May 05 01:46:59 PM PDT 24
Finished May 05 01:47:09 PM PDT 24
Peak memory 251112 kb
Host smart-3ab84173-30ab-4233-8f8b-73ebe3a78021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155085151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.4155085151
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2039855655
Short name T406
Test name
Test status
Simulation time 58086186725 ps
CPU time 229.44 seconds
Started May 05 01:47:01 PM PDT 24
Finished May 05 01:50:52 PM PDT 24
Peak memory 273384 kb
Host smart-a18c341a-4fa9-4aba-975a-8dcb9ea5c1aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039855655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2039855655
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.77081297
Short name T517
Test name
Test status
Simulation time 17822100 ps
CPU time 0.94 seconds
Started May 05 01:47:13 PM PDT 24
Finished May 05 01:47:15 PM PDT 24
Peak memory 212800 kb
Host smart-61fc19f8-35e7-4a63-a02c-6df57f62a87b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77081297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctr
l_volatile_unlock_smoke.77081297
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.152396896
Short name T215
Test name
Test status
Simulation time 58817809 ps
CPU time 1.07 seconds
Started May 05 01:47:10 PM PDT 24
Finished May 05 01:47:12 PM PDT 24
Peak memory 209680 kb
Host smart-50cefc0b-1822-41cf-b2a7-cf83bde95041
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152396896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.152396896
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.4084330621
Short name T256
Test name
Test status
Simulation time 478826233 ps
CPU time 19.71 seconds
Started May 05 01:47:15 PM PDT 24
Finished May 05 01:47:36 PM PDT 24
Peak memory 217984 kb
Host smart-2bce2a09-5388-4ff2-a7b8-c89bda26b66d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084330621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.4084330621
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.4289589917
Short name T30
Test name
Test status
Simulation time 2731238507 ps
CPU time 6.4 seconds
Started May 05 01:47:09 PM PDT 24
Finished May 05 01:47:17 PM PDT 24
Peak memory 209752 kb
Host smart-6bade769-17ed-4b86-8566-97438e27b2d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289589917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.4289589917
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2605673629
Short name T786
Test name
Test status
Simulation time 33625586 ps
CPU time 1.72 seconds
Started May 05 01:47:11 PM PDT 24
Finished May 05 01:47:13 PM PDT 24
Peak memory 218032 kb
Host smart-b3b47fcb-f807-4e47-a474-ab5e06bc59c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605673629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2605673629
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.3777041183
Short name T48
Test name
Test status
Simulation time 328191285 ps
CPU time 14.36 seconds
Started May 05 01:47:05 PM PDT 24
Finished May 05 01:47:20 PM PDT 24
Peak memory 219056 kb
Host smart-eccb9630-2d2b-433d-904f-13b6f01c5e97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777041183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.3777041183
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1332785783
Short name T574
Test name
Test status
Simulation time 351735334 ps
CPU time 14.14 seconds
Started May 05 01:46:58 PM PDT 24
Finished May 05 01:47:14 PM PDT 24
Peak memory 218148 kb
Host smart-7f6ef29e-1232-46ab-a2c3-3a5cee648087
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332785783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1332785783
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.1371708091
Short name T692
Test name
Test status
Simulation time 1566783848 ps
CPU time 11.18 seconds
Started May 05 01:47:16 PM PDT 24
Finished May 05 01:47:27 PM PDT 24
Peak memory 218100 kb
Host smart-5d4687de-9429-4595-8113-de448a129cc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371708091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
1371708091
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2031125694
Short name T547
Test name
Test status
Simulation time 1131966290 ps
CPU time 8.48 seconds
Started May 05 01:46:59 PM PDT 24
Finished May 05 01:47:08 PM PDT 24
Peak memory 218148 kb
Host smart-c3dcf815-ef1f-44ff-a22b-f7f87871731e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031125694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2031125694
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3862916746
Short name T62
Test name
Test status
Simulation time 41887536 ps
CPU time 2.77 seconds
Started May 05 01:47:00 PM PDT 24
Finished May 05 01:47:03 PM PDT 24
Peak memory 218084 kb
Host smart-ebdea792-3ad0-4c72-b6c9-288ee58f7947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862916746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3862916746
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1802815777
Short name T481
Test name
Test status
Simulation time 210928678 ps
CPU time 25.42 seconds
Started May 05 01:47:10 PM PDT 24
Finished May 05 01:47:36 PM PDT 24
Peak memory 251112 kb
Host smart-65d60664-113c-4848-9632-28cbf6a03984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802815777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1802815777
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.759140006
Short name T513
Test name
Test status
Simulation time 118815380 ps
CPU time 5.93 seconds
Started May 05 01:47:00 PM PDT 24
Finished May 05 01:47:06 PM PDT 24
Peak memory 251156 kb
Host smart-732bc87c-1972-4218-a090-828e357a27cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759140006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.759140006
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.4046348940
Short name T615
Test name
Test status
Simulation time 10828662843 ps
CPU time 324.22 seconds
Started May 05 01:47:04 PM PDT 24
Finished May 05 01:52:28 PM PDT 24
Peak memory 222752 kb
Host smart-b79e5898-b7bf-4142-b2b0-e4b37e9120c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046348940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.4046348940
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.789608748
Short name T27
Test name
Test status
Simulation time 25709357653 ps
CPU time 522.56 seconds
Started May 05 01:47:22 PM PDT 24
Finished May 05 01:56:05 PM PDT 24
Peak memory 447724 kb
Host smart-c4ce0b20-95c1-49b8-8991-09fc38be5c08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=789608748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.789608748
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.4241427624
Short name T487
Test name
Test status
Simulation time 12522685 ps
CPU time 0.98 seconds
Started May 05 01:47:01 PM PDT 24
Finished May 05 01:47:02 PM PDT 24
Peak memory 211804 kb
Host smart-88cd8dc6-b348-4191-a147-b5f312e0386f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241427624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.4241427624
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.1135774717
Short name T223
Test name
Test status
Simulation time 32793913 ps
CPU time 1.44 seconds
Started May 05 01:47:05 PM PDT 24
Finished May 05 01:47:07 PM PDT 24
Peak memory 209700 kb
Host smart-dfe701ca-2d2a-4c03-9fc1-8c829e6d8b2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135774717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.1135774717
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2748989554
Short name T604
Test name
Test status
Simulation time 358462365 ps
CPU time 7.21 seconds
Started May 05 01:47:03 PM PDT 24
Finished May 05 01:47:11 PM PDT 24
Peak memory 218032 kb
Host smart-3ee72d0b-e264-41b7-96d4-9c9f61353454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748989554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2748989554
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.559295004
Short name T498
Test name
Test status
Simulation time 200695539 ps
CPU time 5.95 seconds
Started May 05 01:47:05 PM PDT 24
Finished May 05 01:47:12 PM PDT 24
Peak memory 217260 kb
Host smart-3c2eb66e-5bc5-4f78-b2d8-92cba61cedc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559295004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.559295004
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3732347100
Short name T262
Test name
Test status
Simulation time 143319104 ps
CPU time 2.5 seconds
Started May 05 01:47:16 PM PDT 24
Finished May 05 01:47:19 PM PDT 24
Peak memory 218060 kb
Host smart-f94cb8a6-c4bb-47b7-a9b0-97f15262856b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732347100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3732347100
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.4260560141
Short name T731
Test name
Test status
Simulation time 353037209 ps
CPU time 16.4 seconds
Started May 05 01:47:09 PM PDT 24
Finished May 05 01:47:27 PM PDT 24
Peak memory 226216 kb
Host smart-26642fb6-ecb1-4cef-a57d-fe78184835a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260560141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.4260560141
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2641757927
Short name T329
Test name
Test status
Simulation time 1078134827 ps
CPU time 11.43 seconds
Started May 05 01:47:21 PM PDT 24
Finished May 05 01:47:33 PM PDT 24
Peak memory 218104 kb
Host smart-f3c61bf4-048a-4bd0-9a07-275874d5ba5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641757927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2641757927
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3614962158
Short name T769
Test name
Test status
Simulation time 4467199493 ps
CPU time 9.18 seconds
Started May 05 01:47:11 PM PDT 24
Finished May 05 01:47:21 PM PDT 24
Peak memory 218064 kb
Host smart-5dd0ce44-0133-409a-ad08-bc685b1dfaf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614962158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3614962158
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.4141983708
Short name T383
Test name
Test status
Simulation time 237628755 ps
CPU time 7.34 seconds
Started May 05 01:47:14 PM PDT 24
Finished May 05 01:47:22 PM PDT 24
Peak memory 218176 kb
Host smart-0b62576e-8069-498b-8421-68e731167b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141983708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.4141983708
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.236294256
Short name T464
Test name
Test status
Simulation time 58740332 ps
CPU time 1.67 seconds
Started May 05 01:47:03 PM PDT 24
Finished May 05 01:47:05 PM PDT 24
Peak memory 213756 kb
Host smart-2765515c-6191-4ed7-8761-194a7a29c465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236294256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.236294256
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.14822262
Short name T510
Test name
Test status
Simulation time 1521439254 ps
CPU time 31.5 seconds
Started May 05 01:47:09 PM PDT 24
Finished May 05 01:47:41 PM PDT 24
Peak memory 251068 kb
Host smart-c85a6dd7-1c2f-426c-a5e8-77a998554c70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14822262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.14822262
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2688735412
Short name T241
Test name
Test status
Simulation time 83896486 ps
CPU time 6.67 seconds
Started May 05 01:47:17 PM PDT 24
Finished May 05 01:47:25 PM PDT 24
Peak memory 246248 kb
Host smart-beedc885-0b82-45a3-9489-79bf23285212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688735412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2688735412
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.261445290
Short name T762
Test name
Test status
Simulation time 4893324671 ps
CPU time 91.97 seconds
Started May 05 01:47:03 PM PDT 24
Finished May 05 01:48:35 PM PDT 24
Peak memory 267572 kb
Host smart-641b7bbf-b3df-472c-b118-1bc8945fb344
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261445290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.261445290
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.608172219
Short name T141
Test name
Test status
Simulation time 32363583818 ps
CPU time 545.46 seconds
Started May 05 01:47:04 PM PDT 24
Finished May 05 01:56:10 PM PDT 24
Peak memory 440720 kb
Host smart-054c0d65-ae9b-4e16-b7fc-2f209b51b25c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=608172219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.608172219
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2666898301
Short name T817
Test name
Test status
Simulation time 24643542 ps
CPU time 1.01 seconds
Started May 05 01:47:20 PM PDT 24
Finished May 05 01:47:21 PM PDT 24
Peak memory 211776 kb
Host smart-ea5db608-a86c-4723-abab-e4bff5488428
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666898301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2666898301
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2278986279
Short name T743
Test name
Test status
Simulation time 80552047 ps
CPU time 0.9 seconds
Started May 05 01:47:14 PM PDT 24
Finished May 05 01:47:15 PM PDT 24
Peak memory 209660 kb
Host smart-1f8fa12b-d00c-4c83-8a8a-3c97a5890fdd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278986279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2278986279
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1482712929
Short name T503
Test name
Test status
Simulation time 2383304841 ps
CPU time 14.62 seconds
Started May 05 01:47:13 PM PDT 24
Finished May 05 01:47:28 PM PDT 24
Peak memory 218100 kb
Host smart-4462aa17-5301-4880-91f8-be9fbeebec32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482712929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1482712929
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2174486157
Short name T446
Test name
Test status
Simulation time 1508715411 ps
CPU time 17.38 seconds
Started May 05 01:47:18 PM PDT 24
Finished May 05 01:47:36 PM PDT 24
Peak memory 209648 kb
Host smart-74a2d3d4-a868-43d4-8114-1149f2bb0390
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174486157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2174486157
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2251150684
Short name T664
Test name
Test status
Simulation time 45627312 ps
CPU time 2.86 seconds
Started May 05 01:47:15 PM PDT 24
Finished May 05 01:47:18 PM PDT 24
Peak memory 218100 kb
Host smart-3450323e-0fe5-4dbb-b935-6692e509d85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251150684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2251150684
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.83806362
Short name T436
Test name
Test status
Simulation time 843071713 ps
CPU time 10.32 seconds
Started May 05 01:47:05 PM PDT 24
Finished May 05 01:47:15 PM PDT 24
Peak memory 217312 kb
Host smart-438c866b-5183-405f-b81d-92deaa319312
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83806362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.83806362
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.4140274478
Short name T217
Test name
Test status
Simulation time 1104102124 ps
CPU time 12.15 seconds
Started May 05 01:47:08 PM PDT 24
Finished May 05 01:47:20 PM PDT 24
Peak memory 218120 kb
Host smart-97bcf53c-5cfb-4bc2-a6d3-5a5007e18ba2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140274478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.4140274478
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2590360378
Short name T712
Test name
Test status
Simulation time 522316024 ps
CPU time 7.61 seconds
Started May 05 01:47:19 PM PDT 24
Finished May 05 01:47:28 PM PDT 24
Peak memory 218196 kb
Host smart-57b626b0-cc04-4bc7-a4ef-368c872b5eb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590360378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2590360378
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.56744556
Short name T38
Test name
Test status
Simulation time 93465085 ps
CPU time 2.74 seconds
Started May 05 01:47:23 PM PDT 24
Finished May 05 01:47:31 PM PDT 24
Peak memory 214240 kb
Host smart-e6e7ec73-72d2-4579-b5e0-0bb56ed5a912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56744556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.56744556
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2313286750
Short name T502
Test name
Test status
Simulation time 4119713824 ps
CPU time 18.21 seconds
Started May 05 01:47:10 PM PDT 24
Finished May 05 01:47:29 PM PDT 24
Peak memory 251172 kb
Host smart-ae57acb3-00b8-43ff-bfaf-2d960da4a188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313286750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2313286750
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.2925050116
Short name T220
Test name
Test status
Simulation time 67741193 ps
CPU time 8.1 seconds
Started May 05 01:47:21 PM PDT 24
Finished May 05 01:47:30 PM PDT 24
Peak memory 250980 kb
Host smart-dcbac160-6e29-4757-9a9e-33ecbf7dd517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925050116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.2925050116
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2820172835
Short name T790
Test name
Test status
Simulation time 3900931443 ps
CPU time 47.07 seconds
Started May 05 01:47:04 PM PDT 24
Finished May 05 01:47:51 PM PDT 24
Peak memory 251140 kb
Host smart-bf1bdcc7-e047-4561-a553-413f325479fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820172835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2820172835
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2028735663
Short name T598
Test name
Test status
Simulation time 23979933 ps
CPU time 0.99 seconds
Started May 05 01:47:03 PM PDT 24
Finished May 05 01:47:05 PM PDT 24
Peak memory 211696 kb
Host smart-f18b6f24-4f39-470f-8875-a70279ed23bc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028735663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2028735663
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3871382385
Short name T791
Test name
Test status
Simulation time 52890707 ps
CPU time 0.99 seconds
Started May 05 01:47:14 PM PDT 24
Finished May 05 01:47:16 PM PDT 24
Peak memory 209644 kb
Host smart-34fa6730-e734-46e9-a2d4-09ae84b3bfbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871382385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3871382385
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3060038239
Short name T816
Test name
Test status
Simulation time 221699517 ps
CPU time 11.45 seconds
Started May 05 01:47:17 PM PDT 24
Finished May 05 01:47:29 PM PDT 24
Peak memory 218068 kb
Host smart-c7b3829b-3b0e-4246-b9b0-2e1fdc58beee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060038239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3060038239
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2703500343
Short name T471
Test name
Test status
Simulation time 630957454 ps
CPU time 7.8 seconds
Started May 05 01:47:15 PM PDT 24
Finished May 05 01:47:24 PM PDT 24
Peak memory 217288 kb
Host smart-f0b2f63c-ce1f-4419-98bf-523dc973f466
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703500343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2703500343
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.1277514141
Short name T344
Test name
Test status
Simulation time 28505361 ps
CPU time 1.78 seconds
Started May 05 01:47:16 PM PDT 24
Finished May 05 01:47:18 PM PDT 24
Peak memory 218096 kb
Host smart-993a0e41-d417-4a0c-8180-d29d28fad2e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277514141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.1277514141
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2236766825
Short name T89
Test name
Test status
Simulation time 310831535 ps
CPU time 13.52 seconds
Started May 05 01:47:08 PM PDT 24
Finished May 05 01:47:22 PM PDT 24
Peak memory 219068 kb
Host smart-2f8e7974-a546-46ea-b2fb-77a6fe1d2eb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236766825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2236766825
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.1573146116
Short name T515
Test name
Test status
Simulation time 2145488638 ps
CPU time 16.04 seconds
Started May 05 01:47:17 PM PDT 24
Finished May 05 01:47:33 PM PDT 24
Peak memory 218124 kb
Host smart-e797c015-f600-4174-92a0-4f86f189869d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573146116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.1573146116
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1685771708
Short name T292
Test name
Test status
Simulation time 278935091 ps
CPU time 9.48 seconds
Started May 05 01:47:23 PM PDT 24
Finished May 05 01:47:33 PM PDT 24
Peak memory 218136 kb
Host smart-1ef96712-80c1-4d64-bf65-bf317160f15b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685771708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1685771708
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2187251241
Short name T822
Test name
Test status
Simulation time 1076568831 ps
CPU time 12.17 seconds
Started May 05 01:47:24 PM PDT 24
Finished May 05 01:47:37 PM PDT 24
Peak memory 218224 kb
Host smart-2ecbbe1a-9c98-4854-8e23-cc80444fa583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187251241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2187251241
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2481581630
Short name T469
Test name
Test status
Simulation time 31622744 ps
CPU time 1.71 seconds
Started May 05 01:47:18 PM PDT 24
Finished May 05 01:47:20 PM PDT 24
Peak memory 213940 kb
Host smart-c6180b1e-9496-4cd6-9f9b-a03e6e75b0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481581630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2481581630
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.296061516
Short name T610
Test name
Test status
Simulation time 950396817 ps
CPU time 20.69 seconds
Started May 05 01:47:23 PM PDT 24
Finished May 05 01:47:44 PM PDT 24
Peak memory 251136 kb
Host smart-32a50f33-9f49-4a8a-959c-dd3934008966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296061516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.296061516
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.3860508716
Short name T454
Test name
Test status
Simulation time 320523032 ps
CPU time 7.59 seconds
Started May 05 01:47:23 PM PDT 24
Finished May 05 01:47:31 PM PDT 24
Peak memory 247608 kb
Host smart-c6b734e2-f25a-4d5d-809a-c46e1f155116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860508716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.3860508716
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1887671280
Short name T101
Test name
Test status
Simulation time 89486874888 ps
CPU time 312.33 seconds
Started May 05 01:47:15 PM PDT 24
Finished May 05 01:52:28 PM PDT 24
Peak memory 279304 kb
Host smart-b2cb2a1f-e854-48f6-8b12-86b362bcf71a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887671280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1887671280
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.2654177189
Short name T139
Test name
Test status
Simulation time 742267670491 ps
CPU time 785.32 seconds
Started May 05 01:47:12 PM PDT 24
Finished May 05 02:00:18 PM PDT 24
Peak memory 447840 kb
Host smart-3d308502-a0ab-454a-9893-3118522cb610
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2654177189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.2654177189
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.555725012
Short name T211
Test name
Test status
Simulation time 14301462 ps
CPU time 1.1 seconds
Started May 05 01:47:16 PM PDT 24
Finished May 05 01:47:18 PM PDT 24
Peak memory 211824 kb
Host smart-c21dbdc2-34d7-4bd4-88e8-88a8e2f68157
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555725012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.555725012
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1665378640
Short name T231
Test name
Test status
Simulation time 76862122 ps
CPU time 0.89 seconds
Started May 05 01:47:16 PM PDT 24
Finished May 05 01:47:18 PM PDT 24
Peak memory 209696 kb
Host smart-b2fe19dd-9642-417d-abad-1194720a8a0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665378640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1665378640
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2690788233
Short name T838
Test name
Test status
Simulation time 234816213 ps
CPU time 11.15 seconds
Started May 05 01:47:17 PM PDT 24
Finished May 05 01:47:28 PM PDT 24
Peak memory 218100 kb
Host smart-41d15f8a-61e4-4883-8283-8ff01ee58957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690788233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2690788233
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.396068977
Short name T35
Test name
Test status
Simulation time 505391829 ps
CPU time 5.76 seconds
Started May 05 01:47:25 PM PDT 24
Finished May 05 01:47:31 PM PDT 24
Peak memory 209708 kb
Host smart-95ec0ef7-6067-4c68-9353-1d94deac8043
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396068977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.396068977
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1043060890
Short name T222
Test name
Test status
Simulation time 87365189 ps
CPU time 1.6 seconds
Started May 05 01:47:26 PM PDT 24
Finished May 05 01:47:28 PM PDT 24
Peak memory 218136 kb
Host smart-913c8f8b-4157-41e7-8eeb-be7548b9ac6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043060890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1043060890
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.1207258268
Short name T315
Test name
Test status
Simulation time 366591462 ps
CPU time 12.89 seconds
Started May 05 01:47:17 PM PDT 24
Finished May 05 01:47:30 PM PDT 24
Peak memory 226224 kb
Host smart-ae0ef0e3-a8ec-4017-99ab-37bb4672d737
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207258268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.1207258268
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1044474808
Short name T267
Test name
Test status
Simulation time 1425302779 ps
CPU time 12.62 seconds
Started May 05 01:47:22 PM PDT 24
Finished May 05 01:47:36 PM PDT 24
Peak memory 218188 kb
Host smart-aaade861-d9c4-4574-a865-3046a8e717b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044474808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1044474808
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.20979974
Short name T564
Test name
Test status
Simulation time 1709269052 ps
CPU time 10.41 seconds
Started May 05 01:47:14 PM PDT 24
Finished May 05 01:47:25 PM PDT 24
Peak memory 218064 kb
Host smart-a9019099-96a6-4802-8b5b-ecca78a1c58c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20979974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.20979974
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1363565968
Short name T147
Test name
Test status
Simulation time 2880759596 ps
CPU time 11.26 seconds
Started May 05 01:47:17 PM PDT 24
Finished May 05 01:47:28 PM PDT 24
Peak memory 218248 kb
Host smart-91ed73b2-390e-44d1-9b3a-f8322b23f6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1363565968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1363565968
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1975335727
Short name T457
Test name
Test status
Simulation time 43105506 ps
CPU time 1.48 seconds
Started May 05 01:47:18 PM PDT 24
Finished May 05 01:47:20 PM PDT 24
Peak memory 217912 kb
Host smart-56ba4d63-8282-44af-a6bc-c9a3981dd2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975335727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1975335727
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1311066067
Short name T854
Test name
Test status
Simulation time 392054380 ps
CPU time 24.91 seconds
Started May 05 01:47:19 PM PDT 24
Finished May 05 01:47:44 PM PDT 24
Peak memory 251036 kb
Host smart-4a88895d-74fc-49e4-9309-a0a1aa4e5e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311066067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1311066067
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2137061801
Short name T559
Test name
Test status
Simulation time 90154930 ps
CPU time 7.54 seconds
Started May 05 01:47:18 PM PDT 24
Finished May 05 01:47:26 PM PDT 24
Peak memory 251136 kb
Host smart-597010f8-b035-46e5-bb64-bb616aa85885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137061801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2137061801
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3007084460
Short name T335
Test name
Test status
Simulation time 35989345407 ps
CPU time 289.16 seconds
Started May 05 01:47:24 PM PDT 24
Finished May 05 01:52:14 PM PDT 24
Peak memory 219704 kb
Host smart-db25ce2a-13cb-40ef-bd6e-2197dcc59f6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007084460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3007084460
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.80087364
Short name T417
Test name
Test status
Simulation time 114284837273 ps
CPU time 381.92 seconds
Started May 05 01:47:13 PM PDT 24
Finished May 05 01:53:36 PM PDT 24
Peak memory 279196 kb
Host smart-1db84908-9893-46b9-b2c1-10e08edc9bce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=80087364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.80087364
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2915442219
Short name T789
Test name
Test status
Simulation time 15169944 ps
CPU time 0.91 seconds
Started May 05 01:47:19 PM PDT 24
Finished May 05 01:47:20 PM PDT 24
Peak memory 211728 kb
Host smart-36e13cee-09dc-4e95-8247-fa10f39ea32b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915442219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.2915442219
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.575800695
Short name T146
Test name
Test status
Simulation time 26604688 ps
CPU time 0.84 seconds
Started May 05 01:47:24 PM PDT 24
Finished May 05 01:47:25 PM PDT 24
Peak memory 209536 kb
Host smart-f0a469ff-337a-46f8-b87c-aaa9f371380d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575800695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.575800695
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3115243965
Short name T334
Test name
Test status
Simulation time 1458905863 ps
CPU time 11.47 seconds
Started May 05 01:47:30 PM PDT 24
Finished May 05 01:47:42 PM PDT 24
Peak memory 218208 kb
Host smart-d46e3ba3-dad3-4b34-9282-d4c48e376177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115243965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3115243965
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1488916118
Short name T865
Test name
Test status
Simulation time 461176551 ps
CPU time 6.64 seconds
Started May 05 01:47:25 PM PDT 24
Finished May 05 01:47:32 PM PDT 24
Peak memory 209692 kb
Host smart-8559359e-3fba-405d-a661-8d19a63f3db8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488916118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.1488916118
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.710746396
Short name T472
Test name
Test status
Simulation time 170356384 ps
CPU time 3.15 seconds
Started May 05 01:47:25 PM PDT 24
Finished May 05 01:47:29 PM PDT 24
Peak memory 218104 kb
Host smart-8bd4e7bb-11dd-45df-ac5d-6c28d6b3f653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710746396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.710746396
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.1812690922
Short name T245
Test name
Test status
Simulation time 2347927141 ps
CPU time 17.94 seconds
Started May 05 01:47:27 PM PDT 24
Finished May 05 01:47:46 PM PDT 24
Peak memory 226192 kb
Host smart-e8259a40-dbcc-4ec2-b7aa-e83e4ddff7de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812690922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.1812690922
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.4218754154
Short name T593
Test name
Test status
Simulation time 1217946603 ps
CPU time 9.16 seconds
Started May 05 01:47:19 PM PDT 24
Finished May 05 01:47:29 PM PDT 24
Peak memory 218172 kb
Host smart-6cb8475a-e708-4490-ae51-eb7cd2f30f3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218754154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.4218754154
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.52800575
Short name T567
Test name
Test status
Simulation time 1901724894 ps
CPU time 18.15 seconds
Started May 05 01:47:19 PM PDT 24
Finished May 05 01:47:38 PM PDT 24
Peak memory 218056 kb
Host smart-6d3a5f8b-b654-41fb-a5dc-abbe3805b3d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52800575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.52800575
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1231281737
Short name T54
Test name
Test status
Simulation time 746571561 ps
CPU time 16.09 seconds
Started May 05 01:47:19 PM PDT 24
Finished May 05 01:47:36 PM PDT 24
Peak memory 218228 kb
Host smart-8c40e0b4-9547-4164-ab24-89e3a8ee35da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231281737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1231281737
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3214957338
Short name T82
Test name
Test status
Simulation time 26188889 ps
CPU time 1.58 seconds
Started May 05 01:47:21 PM PDT 24
Finished May 05 01:47:23 PM PDT 24
Peak memory 213648 kb
Host smart-c4628ac7-2ed4-45ce-bdaf-e6228d72b380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214957338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3214957338
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.661341632
Short name T467
Test name
Test status
Simulation time 986578363 ps
CPU time 26.89 seconds
Started May 05 01:47:16 PM PDT 24
Finished May 05 01:47:44 PM PDT 24
Peak memory 249084 kb
Host smart-cd2db1f9-814a-4dfa-8ea3-f63780eebcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661341632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.661341632
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.62961531
Short name T208
Test name
Test status
Simulation time 107735480 ps
CPU time 6.38 seconds
Started May 05 01:47:26 PM PDT 24
Finished May 05 01:47:32 PM PDT 24
Peak memory 250780 kb
Host smart-43a17e21-9c86-4368-b4ab-b93b5d8cc378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62961531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.62961531
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.713064389
Short name T166
Test name
Test status
Simulation time 4291578512 ps
CPU time 103.87 seconds
Started May 05 01:47:27 PM PDT 24
Finished May 05 01:49:12 PM PDT 24
Peak memory 251232 kb
Host smart-722f813b-a796-4e8d-bbfe-14f9d5f7e716
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713064389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.713064389
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2772356432
Short name T145
Test name
Test status
Simulation time 44626216 ps
CPU time 0.85 seconds
Started May 05 01:47:27 PM PDT 24
Finished May 05 01:47:29 PM PDT 24
Peak memory 211840 kb
Host smart-4782b41b-ae3b-47a4-84cf-fe30e2c9fe6b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772356432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2772356432
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2093928884
Short name T823
Test name
Test status
Simulation time 17150148 ps
CPU time 0.96 seconds
Started May 05 01:47:22 PM PDT 24
Finished May 05 01:47:23 PM PDT 24
Peak memory 209692 kb
Host smart-89ca13fe-238e-480d-b5f5-4f3620673d63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093928884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2093928884
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2330521218
Short name T643
Test name
Test status
Simulation time 539964669 ps
CPU time 9.01 seconds
Started May 05 01:47:18 PM PDT 24
Finished May 05 01:47:28 PM PDT 24
Peak memory 218084 kb
Host smart-ce7d303a-a848-4117-915d-646ad73e4f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330521218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2330521218
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.652050371
Short name T755
Test name
Test status
Simulation time 279316704 ps
CPU time 3.63 seconds
Started May 05 01:47:24 PM PDT 24
Finished May 05 01:47:28 PM PDT 24
Peak memory 209704 kb
Host smart-b947395e-eb21-4f63-9f81-81c5ba7442f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652050371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.652050371
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.27688289
Short name T677
Test name
Test status
Simulation time 61898891 ps
CPU time 3.11 seconds
Started May 05 01:47:26 PM PDT 24
Finished May 05 01:47:29 PM PDT 24
Peak memory 218148 kb
Host smart-324b6055-6709-4e5b-83f4-76650b7c9559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27688289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.27688289
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.192838871
Short name T586
Test name
Test status
Simulation time 635264998 ps
CPU time 9.49 seconds
Started May 05 01:47:20 PM PDT 24
Finished May 05 01:47:30 PM PDT 24
Peak memory 226220 kb
Host smart-b1954e6e-e351-4ad7-815f-44da52aa456e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192838871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.192838871
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2826658654
Short name T156
Test name
Test status
Simulation time 2507370269 ps
CPU time 13.88 seconds
Started May 05 01:47:19 PM PDT 24
Finished May 05 01:47:34 PM PDT 24
Peak memory 218248 kb
Host smart-08c5736c-9a2e-41de-aac0-4789f889f8b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826658654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2826658654
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.194036544
Short name T478
Test name
Test status
Simulation time 324001913 ps
CPU time 7.87 seconds
Started May 05 01:47:20 PM PDT 24
Finished May 05 01:47:29 PM PDT 24
Peak memory 218056 kb
Host smart-79499349-72e6-4fd9-845f-19663ff27ba5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194036544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.194036544
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2405104915
Short name T810
Test name
Test status
Simulation time 571897529 ps
CPU time 6.9 seconds
Started May 05 01:47:33 PM PDT 24
Finished May 05 01:47:40 PM PDT 24
Peak memory 218284 kb
Host smart-609022bf-b17e-4615-b8db-7edc6ab98ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405104915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2405104915
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3578917622
Short name T41
Test name
Test status
Simulation time 92198066 ps
CPU time 1.96 seconds
Started May 05 01:47:15 PM PDT 24
Finished May 05 01:47:17 PM PDT 24
Peak memory 214132 kb
Host smart-fe8d8771-35bb-4702-9ed2-decd9a417ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578917622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3578917622
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2013886279
Short name T620
Test name
Test status
Simulation time 1813515481 ps
CPU time 20.22 seconds
Started May 05 01:47:21 PM PDT 24
Finished May 05 01:47:42 PM PDT 24
Peak memory 250984 kb
Host smart-ae19dcaa-3671-4318-870a-0c7585c0c490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013886279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2013886279
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1699183795
Short name T210
Test name
Test status
Simulation time 62302345 ps
CPU time 8.87 seconds
Started May 05 01:47:26 PM PDT 24
Finished May 05 01:47:36 PM PDT 24
Peak memory 251028 kb
Host smart-a0965f7e-8932-43d6-bdab-249f35266bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699183795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1699183795
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1696030485
Short name T440
Test name
Test status
Simulation time 30531544352 ps
CPU time 58.05 seconds
Started May 05 01:47:24 PM PDT 24
Finished May 05 01:48:22 PM PDT 24
Peak memory 250864 kb
Host smart-70f888fb-2088-4b29-b423-4320769c8d6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696030485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1696030485
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.905917381
Short name T723
Test name
Test status
Simulation time 16140122 ps
CPU time 1.01 seconds
Started May 05 01:47:25 PM PDT 24
Finished May 05 01:47:27 PM PDT 24
Peak memory 212968 kb
Host smart-f7f1cb56-fe23-4499-9442-c5114c0dad91
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905917381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct
rl_volatile_unlock_smoke.905917381
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3258535830
Short name T300
Test name
Test status
Simulation time 82053250 ps
CPU time 1.26 seconds
Started May 05 01:47:24 PM PDT 24
Finished May 05 01:47:25 PM PDT 24
Peak memory 209732 kb
Host smart-4cf21c76-ba4b-45d4-8d43-64c79de492ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258535830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3258535830
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1557875749
Short name T649
Test name
Test status
Simulation time 1308079188 ps
CPU time 13.82 seconds
Started May 05 01:47:26 PM PDT 24
Finished May 05 01:47:40 PM PDT 24
Peak memory 218232 kb
Host smart-041b8603-f9dd-471c-b116-b7c29b6f6cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557875749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1557875749
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2249986016
Short name T760
Test name
Test status
Simulation time 2089168083 ps
CPU time 24.38 seconds
Started May 05 01:47:29 PM PDT 24
Finished May 05 01:47:54 PM PDT 24
Peak memory 209752 kb
Host smart-29f67ed9-7380-4939-9e8f-42420670f58a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249986016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2249986016
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.801209290
Short name T774
Test name
Test status
Simulation time 119046687 ps
CPU time 3.16 seconds
Started May 05 01:47:20 PM PDT 24
Finished May 05 01:47:24 PM PDT 24
Peak memory 218112 kb
Host smart-e6d1dee4-1d72-466e-ac74-abd8bdbed6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801209290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.801209290
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2706829270
Short name T676
Test name
Test status
Simulation time 442741115 ps
CPU time 14.49 seconds
Started May 05 01:47:16 PM PDT 24
Finished May 05 01:47:31 PM PDT 24
Peak memory 219064 kb
Host smart-37f8ea5c-808b-4649-a30d-a883a9901f73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2706829270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2706829270
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2242974215
Short name T698
Test name
Test status
Simulation time 681324400 ps
CPU time 11.75 seconds
Started May 05 01:47:24 PM PDT 24
Finished May 05 01:47:37 PM PDT 24
Peak memory 218064 kb
Host smart-07bd4b9f-a193-4233-af05-743c0641efe5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242974215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2242974215
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2635863579
Short name T39
Test name
Test status
Simulation time 856530300 ps
CPU time 8.62 seconds
Started May 05 01:47:23 PM PDT 24
Finished May 05 01:47:32 PM PDT 24
Peak memory 218176 kb
Host smart-3c933cb1-0218-4db0-b08f-213a21cfdaa4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635863579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2635863579
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.1504739135
Short name T728
Test name
Test status
Simulation time 2633644289 ps
CPU time 7.93 seconds
Started May 05 01:47:25 PM PDT 24
Finished May 05 01:47:33 PM PDT 24
Peak memory 218256 kb
Host smart-fed95c07-5370-47e4-ae1c-2eb6fd2e01c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504739135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1504739135
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2764971790
Short name T251
Test name
Test status
Simulation time 213195335 ps
CPU time 3.11 seconds
Started May 05 01:47:24 PM PDT 24
Finished May 05 01:47:28 PM PDT 24
Peak memory 214504 kb
Host smart-45dc0520-3927-43a2-9e59-c854c56efb1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764971790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2764971790
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3564962806
Short name T861
Test name
Test status
Simulation time 478345638 ps
CPU time 28.36 seconds
Started May 05 01:47:16 PM PDT 24
Finished May 05 01:47:45 PM PDT 24
Peak memory 247676 kb
Host smart-76412d03-e82e-4081-a833-3f7243f37e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564962806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3564962806
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.513385629
Short name T453
Test name
Test status
Simulation time 60865868 ps
CPU time 8.15 seconds
Started May 05 01:47:22 PM PDT 24
Finished May 05 01:47:31 PM PDT 24
Peak memory 250988 kb
Host smart-6eda2625-c1f9-4e3b-846a-6e4e3a1a1ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513385629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.513385629
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3676600986
Short name T164
Test name
Test status
Simulation time 7253329055 ps
CPU time 213.69 seconds
Started May 05 01:47:17 PM PDT 24
Finished May 05 01:50:51 PM PDT 24
Peak memory 251132 kb
Host smart-d57573fd-2f6c-4457-8aa1-0b5fe355bd4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676600986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3676600986
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.4033438450
Short name T154
Test name
Test status
Simulation time 31105488979 ps
CPU time 716.46 seconds
Started May 05 01:47:20 PM PDT 24
Finished May 05 01:59:18 PM PDT 24
Peak memory 300264 kb
Host smart-48d1a14d-6067-4d43-9428-c675f83e4af4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4033438450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.4033438450
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.275388505
Short name T718
Test name
Test status
Simulation time 48211150 ps
CPU time 0.93 seconds
Started May 05 01:47:21 PM PDT 24
Finished May 05 01:47:22 PM PDT 24
Peak memory 213024 kb
Host smart-f1374199-6048-49f3-83a8-e858fb88e3ca
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275388505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ct
rl_volatile_unlock_smoke.275388505
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.2013847734
Short name T851
Test name
Test status
Simulation time 44900811 ps
CPU time 0.87 seconds
Started May 05 01:45:38 PM PDT 24
Finished May 05 01:45:40 PM PDT 24
Peak memory 209704 kb
Host smart-278a315c-d68e-490e-bd31-aff49729ee78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013847734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.2013847734
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2721138686
Short name T199
Test name
Test status
Simulation time 24303785 ps
CPU time 0.95 seconds
Started May 05 01:45:37 PM PDT 24
Finished May 05 01:45:39 PM PDT 24
Peak memory 209656 kb
Host smart-721499ff-7ff0-4890-87b0-223bcd83df91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721138686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2721138686
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.3201604672
Short name T656
Test name
Test status
Simulation time 2035091356 ps
CPU time 16.57 seconds
Started May 05 01:45:45 PM PDT 24
Finished May 05 01:46:04 PM PDT 24
Peak memory 218108 kb
Host smart-0c138a5d-e31e-43c5-8441-019596d34394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201604672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3201604672
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2558329896
Short name T780
Test name
Test status
Simulation time 917832689 ps
CPU time 11.35 seconds
Started May 05 01:45:41 PM PDT 24
Finished May 05 01:45:54 PM PDT 24
Peak memory 209708 kb
Host smart-c98d3fc6-515a-41cf-9909-43344e1537c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558329896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2558329896
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.3427805101
Short name T25
Test name
Test status
Simulation time 6551574013 ps
CPU time 28.45 seconds
Started May 05 01:45:34 PM PDT 24
Finished May 05 01:46:03 PM PDT 24
Peak memory 219144 kb
Host smart-20e1168c-8d11-4e4b-a1d0-56435c7d0828
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427805101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.3427805101
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.3634319418
Short name T557
Test name
Test status
Simulation time 1353872135 ps
CPU time 8.59 seconds
Started May 05 01:45:33 PM PDT 24
Finished May 05 01:45:42 PM PDT 24
Peak memory 217428 kb
Host smart-d60ee0af-0d94-43ac-9b5e-447665197cd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634319418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.3
634319418
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.665291570
Short name T93
Test name
Test status
Simulation time 165369436 ps
CPU time 2.28 seconds
Started May 05 01:45:42 PM PDT 24
Finished May 05 01:45:46 PM PDT 24
Peak memory 218124 kb
Host smart-8249ca55-b5a8-4c90-9d29-c20a0b662551
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665291570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
prog_failure.665291570
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2104860162
Short name T799
Test name
Test status
Simulation time 985618543 ps
CPU time 14.6 seconds
Started May 05 01:45:42 PM PDT 24
Finished May 05 01:45:58 PM PDT 24
Peak memory 213336 kb
Host smart-42ed266e-9250-491b-bde4-9b096cde0ceb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104860162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2104860162
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.2064730833
Short name T516
Test name
Test status
Simulation time 1845374429 ps
CPU time 6.32 seconds
Started May 05 01:45:35 PM PDT 24
Finished May 05 01:45:41 PM PDT 24
Peak memory 213736 kb
Host smart-fa19379b-5537-453e-9fb9-bc321ee94119
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064730833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
2064730833
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3938613363
Short name T701
Test name
Test status
Simulation time 4733841639 ps
CPU time 35.18 seconds
Started May 05 01:45:42 PM PDT 24
Finished May 05 01:46:19 PM PDT 24
Peak memory 251072 kb
Host smart-5b6c9962-3758-4507-977a-e821c1ffeddc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938613363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3938613363
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2045541552
Short name T809
Test name
Test status
Simulation time 838147397 ps
CPU time 12.71 seconds
Started May 05 01:45:40 PM PDT 24
Finished May 05 01:45:55 PM PDT 24
Peak memory 225040 kb
Host smart-66075ecc-edf5-4930-89fb-c5236fdb022a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045541552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2045541552
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1591829191
Short name T213
Test name
Test status
Simulation time 109433518 ps
CPU time 3.21 seconds
Started May 05 01:45:34 PM PDT 24
Finished May 05 01:45:38 PM PDT 24
Peak memory 218092 kb
Host smart-36b16b65-3c38-43ba-bd40-dc1f8056129c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591829191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1591829191
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1375927367
Short name T795
Test name
Test status
Simulation time 1253067199 ps
CPU time 15.45 seconds
Started May 05 01:45:32 PM PDT 24
Finished May 05 01:45:48 PM PDT 24
Peak memory 214792 kb
Host smart-91f1049e-6db7-4eab-9bab-84b29539277b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375927367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1375927367
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2558261072
Short name T203
Test name
Test status
Simulation time 606625841 ps
CPU time 12.93 seconds
Started May 05 01:45:41 PM PDT 24
Finished May 05 01:45:55 PM PDT 24
Peak memory 226136 kb
Host smart-aa92145d-f1f3-4e7f-b3ec-d81357e7c851
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558261072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2558261072
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1366383949
Short name T650
Test name
Test status
Simulation time 1092436319 ps
CPU time 12.65 seconds
Started May 05 01:45:34 PM PDT 24
Finished May 05 01:45:47 PM PDT 24
Peak memory 218056 kb
Host smart-2001509a-3c5e-42ad-87b9-1195999d1f98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366383949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.1366383949
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.764233149
Short name T250
Test name
Test status
Simulation time 983197498 ps
CPU time 9.44 seconds
Started May 05 01:45:34 PM PDT 24
Finished May 05 01:45:44 PM PDT 24
Peak memory 218156 kb
Host smart-c0910990-3947-4a85-a06e-16900a854bcd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764233149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.764233149
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.2446591337
Short name T534
Test name
Test status
Simulation time 1267261951 ps
CPU time 11.69 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:45:57 PM PDT 24
Peak memory 218168 kb
Host smart-c4a279c3-2293-49d4-89fb-f2691cf08571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446591337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2446591337
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.1329487960
Short name T551
Test name
Test status
Simulation time 206108583 ps
CPU time 1.57 seconds
Started May 05 01:45:41 PM PDT 24
Finished May 05 01:45:44 PM PDT 24
Peak memory 213612 kb
Host smart-b6a268bc-46e4-4ac4-bf15-1b542bd9342e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329487960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.1329487960
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3512165179
Short name T511
Test name
Test status
Simulation time 198179668 ps
CPU time 23.74 seconds
Started May 05 01:45:33 PM PDT 24
Finished May 05 01:45:58 PM PDT 24
Peak memory 248892 kb
Host smart-da7a0649-9aef-439d-b5b1-41b026a4e92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512165179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3512165179
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.492174963
Short name T379
Test name
Test status
Simulation time 115175090 ps
CPU time 8.68 seconds
Started May 05 01:45:38 PM PDT 24
Finished May 05 01:45:48 PM PDT 24
Peak memory 251100 kb
Host smart-c18d1cf0-4302-4f55-ba11-3408ce3471bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492174963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.492174963
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.195928394
Short name T78
Test name
Test status
Simulation time 1271111210 ps
CPU time 32.05 seconds
Started May 05 01:45:49 PM PDT 24
Finished May 05 01:46:22 PM PDT 24
Peak memory 251120 kb
Host smart-f718cbbb-5c7f-409c-a752-db76b23986eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195928394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.195928394
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.832944383
Short name T95
Test name
Test status
Simulation time 163633152400 ps
CPU time 891.42 seconds
Started May 05 01:45:46 PM PDT 24
Finished May 05 02:00:39 PM PDT 24
Peak memory 438648 kb
Host smart-d5329bb7-4687-4490-9aac-ee184cfe0d29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=832944383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.832944383
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.4209354571
Short name T293
Test name
Test status
Simulation time 13790793 ps
CPU time 0.77 seconds
Started May 05 01:45:36 PM PDT 24
Finished May 05 01:45:37 PM PDT 24
Peak memory 208108 kb
Host smart-84e809e2-37de-49a5-9348-ed425dc69367
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209354571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.4209354571
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2946958275
Short name T680
Test name
Test status
Simulation time 20360895 ps
CPU time 0.94 seconds
Started May 05 01:45:40 PM PDT 24
Finished May 05 01:45:49 PM PDT 24
Peak memory 209640 kb
Host smart-6274db79-4616-46fe-8274-c185ccd4bcfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946958275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2946958275
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.55125726
Short name T196
Test name
Test status
Simulation time 38644521 ps
CPU time 0.91 seconds
Started May 05 01:45:44 PM PDT 24
Finished May 05 01:45:47 PM PDT 24
Peak memory 209628 kb
Host smart-fe4b582b-6766-48fd-a426-e29ce78dffc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55125726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.55125726
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.627743184
Short name T14
Test name
Test status
Simulation time 5781362726 ps
CPU time 13.55 seconds
Started May 05 01:45:41 PM PDT 24
Finished May 05 01:45:56 PM PDT 24
Peak memory 218428 kb
Host smart-436753ac-4060-4763-8c20-e4c22e9f6b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627743184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.627743184
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1742250243
Short name T32
Test name
Test status
Simulation time 2347135058 ps
CPU time 14.54 seconds
Started May 05 01:45:41 PM PDT 24
Finished May 05 01:45:57 PM PDT 24
Peak memory 209772 kb
Host smart-14d550a1-aef9-4b9a-87a2-c1d090fe4a20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742250243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1742250243
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3677111201
Short name T365
Test name
Test status
Simulation time 6019876984 ps
CPU time 43.68 seconds
Started May 05 01:45:45 PM PDT 24
Finished May 05 01:46:31 PM PDT 24
Peak memory 218632 kb
Host smart-4049cefd-e53d-49ca-83ff-5a7629e26648
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677111201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3677111201
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2148495783
Short name T286
Test name
Test status
Simulation time 1827664723 ps
CPU time 9.48 seconds
Started May 05 01:45:47 PM PDT 24
Finished May 05 01:45:58 PM PDT 24
Peak memory 217604 kb
Host smart-631b6647-bf9c-4d38-966b-dda4defdb9b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148495783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.2
148495783
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3005147049
Short name T449
Test name
Test status
Simulation time 475168748 ps
CPU time 14.17 seconds
Started May 05 01:45:44 PM PDT 24
Finished May 05 01:46:01 PM PDT 24
Peak memory 218076 kb
Host smart-657583e2-e02e-4696-9707-b91bccb4e28e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005147049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3005147049
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3948060301
Short name T65
Test name
Test status
Simulation time 881015719 ps
CPU time 16.99 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:46:02 PM PDT 24
Peak memory 213368 kb
Host smart-2d6fb2e0-3c63-40fa-ace4-f03349ab509f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948060301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3948060301
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1198540194
Short name T602
Test name
Test status
Simulation time 320389578 ps
CPU time 4.93 seconds
Started May 05 01:45:46 PM PDT 24
Finished May 05 01:45:53 PM PDT 24
Peak memory 213604 kb
Host smart-84c117ab-6768-4366-bced-619dc9fd532f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198540194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1198540194
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3332243277
Short name T651
Test name
Test status
Simulation time 972819523 ps
CPU time 42.83 seconds
Started May 05 01:45:44 PM PDT 24
Finished May 05 01:46:29 PM PDT 24
Peak memory 251096 kb
Host smart-32df8f8c-8c3e-4b22-a52c-3ac0fcf3daa7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332243277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3332243277
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3306314662
Short name T432
Test name
Test status
Simulation time 3961643542 ps
CPU time 32.3 seconds
Started May 05 01:45:41 PM PDT 24
Finished May 05 01:46:15 PM PDT 24
Peak memory 251336 kb
Host smart-9fbcb895-6a82-4a28-91f5-e7b265005ef7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306314662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3306314662
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1325397603
Short name T840
Test name
Test status
Simulation time 144239068 ps
CPU time 1.84 seconds
Started May 05 01:45:34 PM PDT 24
Finished May 05 01:45:37 PM PDT 24
Peak memory 218156 kb
Host smart-c38579e5-1cdb-4a55-9592-e0b4ec03fa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325397603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1325397603
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.418601913
Short name T716
Test name
Test status
Simulation time 5639879094 ps
CPU time 10.82 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:45:55 PM PDT 24
Peak memory 218120 kb
Host smart-38b090c7-2a08-47ea-92b9-7e724a89a737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418601913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.418601913
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3547844242
Short name T326
Test name
Test status
Simulation time 1237774958 ps
CPU time 14.49 seconds
Started May 05 01:45:38 PM PDT 24
Finished May 05 01:45:53 PM PDT 24
Peak memory 226168 kb
Host smart-f76cfd09-ad95-44a9-a281-e492e60088ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547844242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3547844242
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.5110805
Short name T759
Test name
Test status
Simulation time 592047374 ps
CPU time 9.59 seconds
Started May 05 01:45:38 PM PDT 24
Finished May 05 01:45:48 PM PDT 24
Peak memory 218084 kb
Host smart-2593f061-ba9e-44c5-92ba-4aca435f3731
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5110805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dige
st_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_diges
t.5110805
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1735111915
Short name T781
Test name
Test status
Simulation time 287834056 ps
CPU time 10.58 seconds
Started May 05 01:45:41 PM PDT 24
Finished May 05 01:45:53 PM PDT 24
Peak memory 218256 kb
Host smart-ba55a6ac-788b-4bad-b922-797fc48ce47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735111915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1735111915
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.412741601
Short name T522
Test name
Test status
Simulation time 205699841 ps
CPU time 3.41 seconds
Started May 05 01:45:34 PM PDT 24
Finished May 05 01:45:38 PM PDT 24
Peak memory 213852 kb
Host smart-3d23da10-06db-4c33-86b7-eeac9e02c518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412741601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.412741601
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1777756019
Short name T249
Test name
Test status
Simulation time 1135229517 ps
CPU time 21.67 seconds
Started May 05 01:45:40 PM PDT 24
Finished May 05 01:46:03 PM PDT 24
Peak memory 251052 kb
Host smart-f8fe43e8-f3d6-455e-808a-7014520bad9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777756019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1777756019
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.967300079
Short name T258
Test name
Test status
Simulation time 183890172 ps
CPU time 7.53 seconds
Started May 05 01:45:41 PM PDT 24
Finished May 05 01:45:51 PM PDT 24
Peak memory 250844 kb
Host smart-87871ae2-faf6-430c-b055-3fa6ba74f3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967300079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.967300079
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.2189562778
Short name T386
Test name
Test status
Simulation time 5863501226 ps
CPU time 99.22 seconds
Started May 05 01:45:50 PM PDT 24
Finished May 05 01:47:30 PM PDT 24
Peak memory 250956 kb
Host smart-ff812022-b927-4042-8b81-b7aa77bb0734
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189562778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.2189562778
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2121816182
Short name T235
Test name
Test status
Simulation time 17303513 ps
CPU time 0.83 seconds
Started May 05 01:45:44 PM PDT 24
Finished May 05 01:45:47 PM PDT 24
Peak memory 211756 kb
Host smart-3a1cd5cc-54fe-47bd-8359-e1410869b175
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121816182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2121816182
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2344807167
Short name T709
Test name
Test status
Simulation time 24712764 ps
CPU time 1.33 seconds
Started May 05 01:45:46 PM PDT 24
Finished May 05 01:45:49 PM PDT 24
Peak memory 209736 kb
Host smart-84973c8c-d35c-44ab-a4d0-ed413d9b7a5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344807167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2344807167
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2507274104
Short name T644
Test name
Test status
Simulation time 26834014 ps
CPU time 0.92 seconds
Started May 05 01:45:37 PM PDT 24
Finished May 05 01:45:39 PM PDT 24
Peak memory 209568 kb
Host smart-0a91ae4c-864b-4c89-afa2-76af83b59b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507274104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2507274104
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.40457972
Short name T506
Test name
Test status
Simulation time 351782229 ps
CPU time 9.43 seconds
Started May 05 01:45:50 PM PDT 24
Finished May 05 01:46:00 PM PDT 24
Peak memory 218176 kb
Host smart-e0f5b217-e56e-4a31-a249-24d7738a1ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40457972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.40457972
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.966697477
Short name T451
Test name
Test status
Simulation time 1140611107 ps
CPU time 18.58 seconds
Started May 05 01:45:51 PM PDT 24
Finished May 05 01:46:10 PM PDT 24
Peak memory 209664 kb
Host smart-4be1980e-9bbc-436e-b279-ed6ff18da7e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966697477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.966697477
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1984024471
Short name T60
Test name
Test status
Simulation time 1718623277 ps
CPU time 29.14 seconds
Started May 05 01:45:46 PM PDT 24
Finished May 05 01:46:17 PM PDT 24
Peak memory 218068 kb
Host smart-7398050b-0150-4b3f-8acb-a7fb0d0cf8a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984024471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1984024471
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1044129283
Short name T69
Test name
Test status
Simulation time 3754006932 ps
CPU time 18.33 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:46:03 PM PDT 24
Peak memory 217980 kb
Host smart-a95bd9a2-fff9-495f-8d1a-550444017895
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044129283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
044129283
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3306262813
Short name T248
Test name
Test status
Simulation time 797795973 ps
CPU time 7.03 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:45:52 PM PDT 24
Peak memory 218072 kb
Host smart-f1e48314-5814-4486-9288-4d4f0f1085f4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306262813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.3306262813
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3790237181
Short name T67
Test name
Test status
Simulation time 971928707 ps
CPU time 22.41 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:46:07 PM PDT 24
Peak memory 213348 kb
Host smart-d228580d-396a-4e98-9aa9-60b16b349ba4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790237181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3790237181
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2311824755
Short name T81
Test name
Test status
Simulation time 518022833 ps
CPU time 4.1 seconds
Started May 05 01:45:39 PM PDT 24
Finished May 05 01:45:44 PM PDT 24
Peak memory 213232 kb
Host smart-054b0831-c3c5-4acf-8218-798e710cf32f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311824755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2311824755
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.3989359395
Short name T555
Test name
Test status
Simulation time 2953340431 ps
CPU time 79.73 seconds
Started May 05 01:45:49 PM PDT 24
Finished May 05 01:47:09 PM PDT 24
Peak memory 269984 kb
Host smart-a561fbef-e67c-4b45-9416-d6e1790222e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989359395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.3989359395
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.139458804
Short name T24
Test name
Test status
Simulation time 1012340243 ps
CPU time 9.63 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:45:55 PM PDT 24
Peak memory 222856 kb
Host smart-fb49e530-a952-4d41-8c8b-576965c45cf8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139458804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.139458804
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3189889882
Short name T868
Test name
Test status
Simulation time 756955446 ps
CPU time 3.14 seconds
Started May 05 01:45:41 PM PDT 24
Finished May 05 01:45:46 PM PDT 24
Peak memory 218088 kb
Host smart-e8fb2939-4dc6-401e-9c97-bb5eb6f8708b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189889882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3189889882
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.2732436622
Short name T815
Test name
Test status
Simulation time 303891147 ps
CPU time 7.27 seconds
Started May 05 01:45:41 PM PDT 24
Finished May 05 01:45:50 PM PDT 24
Peak memory 217916 kb
Host smart-14d0f412-f6ab-4ad8-84ce-cb6b4410fcbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732436622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.2732436622
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.348943962
Short name T304
Test name
Test status
Simulation time 427930061 ps
CPU time 13.21 seconds
Started May 05 01:45:40 PM PDT 24
Finished May 05 01:45:55 PM PDT 24
Peak memory 226184 kb
Host smart-64ef0a86-e348-414e-8b64-3faf3ff3d14c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348943962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.348943962
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3568881243
Short name T756
Test name
Test status
Simulation time 1872469772 ps
CPU time 13.91 seconds
Started May 05 01:45:45 PM PDT 24
Finished May 05 01:46:01 PM PDT 24
Peak memory 226172 kb
Host smart-f51793cc-4835-420f-bca7-bf6ba81ff227
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568881243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3568881243
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1373731126
Short name T563
Test name
Test status
Simulation time 455621370 ps
CPU time 8.83 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:45:55 PM PDT 24
Peak memory 218160 kb
Host smart-aaaed391-e312-4413-8342-5dbb7fe1f5bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373731126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
373731126
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1205334645
Short name T577
Test name
Test status
Simulation time 2034819201 ps
CPU time 8.2 seconds
Started May 05 01:45:40 PM PDT 24
Finished May 05 01:45:49 PM PDT 24
Peak memory 218188 kb
Host smart-57b24a62-ce36-4127-9e9e-90b48ad435e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205334645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1205334645
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.4055434893
Short name T662
Test name
Test status
Simulation time 61701196 ps
CPU time 1.91 seconds
Started May 05 01:45:42 PM PDT 24
Finished May 05 01:45:46 PM PDT 24
Peak memory 223148 kb
Host smart-3620431e-5e4b-4e07-bf8f-9f1e6c65cbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055434893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.4055434893
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2821937581
Short name T20
Test name
Test status
Simulation time 239037556 ps
CPU time 29.91 seconds
Started May 05 01:45:50 PM PDT 24
Finished May 05 01:46:20 PM PDT 24
Peak memory 250956 kb
Host smart-2fc9fecd-6540-4bc7-a9ac-ce75872ebe5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821937581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2821937581
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.4098266910
Short name T688
Test name
Test status
Simulation time 58585301 ps
CPU time 9.2 seconds
Started May 05 01:45:36 PM PDT 24
Finished May 05 01:45:46 PM PDT 24
Peak memory 246892 kb
Host smart-2ad7a506-288a-48f9-88f1-15526a76c010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098266910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.4098266910
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.3446203632
Short name T273
Test name
Test status
Simulation time 20362716554 ps
CPU time 159.56 seconds
Started May 05 01:45:42 PM PDT 24
Finished May 05 01:48:24 PM PDT 24
Peak memory 226292 kb
Host smart-6df1e402-2f33-42de-9709-13622a55f8c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446203632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.3446203632
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.341478668
Short name T204
Test name
Test status
Simulation time 20907449 ps
CPU time 0.97 seconds
Started May 05 01:45:39 PM PDT 24
Finished May 05 01:45:41 PM PDT 24
Peak memory 211768 kb
Host smart-cce8a6cf-bfa8-4ee7-bb64-a08da9f3907c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341478668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.341478668
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3160006407
Short name T636
Test name
Test status
Simulation time 52217342 ps
CPU time 0.99 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:45:46 PM PDT 24
Peak memory 209616 kb
Host smart-378c45b1-8527-498a-97ac-a21165afc4fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160006407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3160006407
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2389583137
Short name T197
Test name
Test status
Simulation time 38670572 ps
CPU time 0.91 seconds
Started May 05 01:45:42 PM PDT 24
Finished May 05 01:45:45 PM PDT 24
Peak memory 209584 kb
Host smart-e62dee86-9721-4b93-9d3e-44d4d6690d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389583137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2389583137
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.771745476
Short name T459
Test name
Test status
Simulation time 320204533 ps
CPU time 14.82 seconds
Started May 05 01:45:50 PM PDT 24
Finished May 05 01:46:05 PM PDT 24
Peak memory 218044 kb
Host smart-385dfe25-0a8a-4305-a640-145f90aa6141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771745476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.771745476
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.442763773
Short name T90
Test name
Test status
Simulation time 215418661 ps
CPU time 1.38 seconds
Started May 05 01:45:46 PM PDT 24
Finished May 05 01:45:49 PM PDT 24
Peak memory 209644 kb
Host smart-32bff50f-330e-4ee4-a10b-e10bb046c97a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442763773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.442763773
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1020063593
Short name T476
Test name
Test status
Simulation time 17231259340 ps
CPU time 54.42 seconds
Started May 05 01:46:08 PM PDT 24
Finished May 05 01:47:02 PM PDT 24
Peak memory 219688 kb
Host smart-87fb4466-c38b-4e65-8ff3-81aeda25ee40
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020063593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1020063593
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1487835099
Short name T713
Test name
Test status
Simulation time 3800530727 ps
CPU time 24.07 seconds
Started May 05 01:45:42 PM PDT 24
Finished May 05 01:46:08 PM PDT 24
Peak memory 218000 kb
Host smart-27d0a43a-4ef5-4222-bd92-ce06aff1fb12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487835099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
487835099
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2866684300
Short name T463
Test name
Test status
Simulation time 3439745484 ps
CPU time 24.13 seconds
Started May 05 01:45:50 PM PDT 24
Finished May 05 01:46:15 PM PDT 24
Peak memory 218232 kb
Host smart-762ccd0b-6bea-4d9f-b360-5700befa972d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866684300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2866684300
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1978365754
Short name T377
Test name
Test status
Simulation time 1329925308 ps
CPU time 19.16 seconds
Started May 05 01:45:50 PM PDT 24
Finished May 05 01:46:09 PM PDT 24
Peak memory 213400 kb
Host smart-c049c4ec-ee40-4cc7-98bc-628dda1f0271
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978365754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.1978365754
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.183679715
Short name T778
Test name
Test status
Simulation time 308843328 ps
CPU time 8.32 seconds
Started May 05 01:46:08 PM PDT 24
Finished May 05 01:46:16 PM PDT 24
Peak memory 213708 kb
Host smart-330a7c9c-26a1-4268-835d-ab800c89c296
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183679715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.183679715
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2442755850
Short name T675
Test name
Test status
Simulation time 9105771585 ps
CPU time 133.72 seconds
Started May 05 01:45:41 PM PDT 24
Finished May 05 01:47:57 PM PDT 24
Peak memory 283392 kb
Host smart-e15b6e70-86c1-4d3c-9198-63dfbd1f620f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442755850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2442755850
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.316096904
Short name T228
Test name
Test status
Simulation time 397879973 ps
CPU time 17.49 seconds
Started May 05 01:46:06 PM PDT 24
Finished May 05 01:46:24 PM PDT 24
Peak memory 251176 kb
Host smart-76b5deaf-49af-4dbc-b3b1-59c96a0a98e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316096904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.316096904
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1440328332
Short name T492
Test name
Test status
Simulation time 529507302 ps
CPU time 2.19 seconds
Started May 05 01:45:58 PM PDT 24
Finished May 05 01:46:00 PM PDT 24
Peak memory 218072 kb
Host smart-eb39b0ca-d384-45cd-bfc1-615600486068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440328332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1440328332
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1630544530
Short name T169
Test name
Test status
Simulation time 1178342075 ps
CPU time 20.06 seconds
Started May 05 01:45:40 PM PDT 24
Finished May 05 01:46:01 PM PDT 24
Peak memory 213996 kb
Host smart-d0054668-2542-4312-9a35-212571fb531b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630544530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1630544530
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.2302530150
Short name T779
Test name
Test status
Simulation time 1713257130 ps
CPU time 14.26 seconds
Started May 05 01:45:53 PM PDT 24
Finished May 05 01:46:07 PM PDT 24
Peak memory 219032 kb
Host smart-a0c83f99-567b-49a9-a118-47cdf02f391f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302530150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.2302530150
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.143079344
Short name T303
Test name
Test status
Simulation time 1428808420 ps
CPU time 14.93 seconds
Started May 05 01:45:45 PM PDT 24
Finished May 05 01:46:02 PM PDT 24
Peak memory 218056 kb
Host smart-b8c83ee4-3226-423f-9595-a13e582ee613
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143079344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_dig
est.143079344
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.2496937240
Short name T15
Test name
Test status
Simulation time 237046627 ps
CPU time 6.64 seconds
Started May 05 01:45:59 PM PDT 24
Finished May 05 01:46:06 PM PDT 24
Peak memory 218196 kb
Host smart-f44b066b-5ad4-4354-be72-1bf5ccbbb3a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496937240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2
496937240
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3591809392
Short name T348
Test name
Test status
Simulation time 1637135316 ps
CPU time 14.57 seconds
Started May 05 01:45:57 PM PDT 24
Finished May 05 01:46:12 PM PDT 24
Peak memory 218148 kb
Host smart-7ddea370-423c-455c-9544-5a02a018c4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591809392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3591809392
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3740950537
Short name T646
Test name
Test status
Simulation time 26921993 ps
CPU time 1.88 seconds
Started May 05 01:45:45 PM PDT 24
Finished May 05 01:45:49 PM PDT 24
Peak memory 213756 kb
Host smart-ba00a3c4-8672-4dc5-bf75-197d31e1e322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740950537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3740950537
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.780839989
Short name T276
Test name
Test status
Simulation time 316463823 ps
CPU time 30.27 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:46:15 PM PDT 24
Peak memory 251164 kb
Host smart-507b50e0-ce20-40c2-96ce-72c6bc63b8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780839989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.780839989
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.192268021
Short name T233
Test name
Test status
Simulation time 294353967 ps
CPU time 7.64 seconds
Started May 05 01:45:37 PM PDT 24
Finished May 05 01:45:46 PM PDT 24
Peak memory 246628 kb
Host smart-03fd0bfe-46cd-4fe2-b1d5-d48f771917fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192268021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.192268021
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2600449852
Short name T523
Test name
Test status
Simulation time 16023084443 ps
CPU time 486.64 seconds
Started May 05 01:45:57 PM PDT 24
Finished May 05 01:54:04 PM PDT 24
Peak memory 269472 kb
Host smart-bada29ea-a0ff-428e-aadb-609e03468e76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600449852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2600449852
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3356095649
Short name T138
Test name
Test status
Simulation time 14604632548 ps
CPU time 240.82 seconds
Started May 05 01:46:08 PM PDT 24
Finished May 05 01:50:09 PM PDT 24
Peak memory 284088 kb
Host smart-eadfac51-b7c4-4df4-9720-368127ad610e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3356095649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3356095649
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1028221321
Short name T719
Test name
Test status
Simulation time 14089736 ps
CPU time 1.06 seconds
Started May 05 01:46:08 PM PDT 24
Finished May 05 01:46:10 PM PDT 24
Peak memory 211760 kb
Host smart-1d2331bc-fae7-47e9-9cb7-e499f6349114
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028221321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1028221321
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.404856778
Short name T282
Test name
Test status
Simulation time 68287672 ps
CPU time 0.98 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:45:47 PM PDT 24
Peak memory 209720 kb
Host smart-df013311-3437-436a-b345-52a9b6742b44
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404856778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.404856778
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.4025957113
Short name T261
Test name
Test status
Simulation time 12604388 ps
CPU time 0.88 seconds
Started May 05 01:45:47 PM PDT 24
Finished May 05 01:45:49 PM PDT 24
Peak memory 209516 kb
Host smart-427eaa1c-cdaa-4265-b2eb-bff4e96deeda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025957113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.4025957113
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.2357950400
Short name T189
Test name
Test status
Simulation time 532542444 ps
CPU time 9.49 seconds
Started May 05 01:45:43 PM PDT 24
Finished May 05 01:45:54 PM PDT 24
Peak memory 218100 kb
Host smart-ffa4cbab-fdc1-45af-8de0-2b13953dccec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357950400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2357950400
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3864778479
Short name T6
Test name
Test status
Simulation time 105639441 ps
CPU time 1.92 seconds
Started May 05 01:45:55 PM PDT 24
Finished May 05 01:45:57 PM PDT 24
Peak memory 209700 kb
Host smart-4e98dd9c-d162-4db4-a201-b56b452fa2b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864778479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3864778479
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1132208266
Short name T47
Test name
Test status
Simulation time 3051562427 ps
CPU time 40.9 seconds
Started May 05 01:46:06 PM PDT 24
Finished May 05 01:46:48 PM PDT 24
Peak memory 220064 kb
Host smart-4044289d-756a-4d61-9fc1-6e1172bbf64f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132208266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1132208266
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.1458735932
Short name T9
Test name
Test status
Simulation time 2430017570 ps
CPU time 4.98 seconds
Started May 05 01:46:00 PM PDT 24
Finished May 05 01:46:05 PM PDT 24
Peak memory 217800 kb
Host smart-10bf32f1-3f1a-4d39-a8fe-366a71625909
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458735932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.1
458735932
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2543786725
Short name T826
Test name
Test status
Simulation time 391238985 ps
CPU time 4.31 seconds
Started May 05 01:46:05 PM PDT 24
Finished May 05 01:46:10 PM PDT 24
Peak memory 218168 kb
Host smart-a2f43bdc-48de-4108-aa98-060a593a04d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543786725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2543786725
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2668380072
Short name T540
Test name
Test status
Simulation time 1542476068 ps
CPU time 17.96 seconds
Started May 05 01:45:44 PM PDT 24
Finished May 05 01:46:04 PM PDT 24
Peak memory 213476 kb
Host smart-04f4b0ef-5bbe-4193-b592-e8b5f85a555a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668380072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2668380072
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2691531241
Short name T422
Test name
Test status
Simulation time 3698599587 ps
CPU time 10.1 seconds
Started May 05 01:45:46 PM PDT 24
Finished May 05 01:45:58 PM PDT 24
Peak memory 214664 kb
Host smart-66f69d37-bdb2-40cf-99e9-e02b56ba1ff5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691531241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2691531241
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.888494435
Short name T770
Test name
Test status
Simulation time 4193445660 ps
CPU time 126.66 seconds
Started May 05 01:46:03 PM PDT 24
Finished May 05 01:48:11 PM PDT 24
Peak memory 283780 kb
Host smart-004a1e2c-62bf-43cd-9249-f8b853432f14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888494435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.888494435
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.154425729
Short name T409
Test name
Test status
Simulation time 915032083 ps
CPU time 8.94 seconds
Started May 05 01:45:49 PM PDT 24
Finished May 05 01:45:58 PM PDT 24
Peak memory 224832 kb
Host smart-f55190df-faee-43f8-9eee-39a41410a65a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154425729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_state_post_trans.154425729
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1696220862
Short name T855
Test name
Test status
Simulation time 117913470 ps
CPU time 1.89 seconds
Started May 05 01:45:42 PM PDT 24
Finished May 05 01:45:46 PM PDT 24
Peak memory 218160 kb
Host smart-e71b2f09-4fc5-4627-83aa-a12c9b0ece9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696220862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1696220862
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.969850225
Short name T788
Test name
Test status
Simulation time 205396654 ps
CPU time 8.39 seconds
Started May 05 01:45:46 PM PDT 24
Finished May 05 01:45:56 PM PDT 24
Peak memory 214424 kb
Host smart-c8bce8e3-a3df-4aa1-bcf4-4bff449b9be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969850225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.969850225
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.2175307311
Short name T801
Test name
Test status
Simulation time 287351404 ps
CPU time 9.17 seconds
Started May 05 01:46:04 PM PDT 24
Finished May 05 01:46:14 PM PDT 24
Peak memory 219060 kb
Host smart-647626b0-a775-4e8e-984e-f0e0ecb0c122
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175307311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2175307311
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.664161616
Short name T504
Test name
Test status
Simulation time 183366365 ps
CPU time 9.05 seconds
Started May 05 01:45:48 PM PDT 24
Finished May 05 01:45:57 PM PDT 24
Peak memory 218172 kb
Host smart-be028aad-d8cf-4675-b1cc-d1a0a38ebe73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664161616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.664161616
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2852262054
Short name T645
Test name
Test status
Simulation time 915457863 ps
CPU time 9.42 seconds
Started May 05 01:45:45 PM PDT 24
Finished May 05 01:45:57 PM PDT 24
Peak memory 218076 kb
Host smart-b58d5c4c-9e81-4ffc-9311-f04a5224a59e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852262054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
852262054
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1361350774
Short name T202
Test name
Test status
Simulation time 396811534 ps
CPU time 14.89 seconds
Started May 05 01:45:42 PM PDT 24
Finished May 05 01:45:59 PM PDT 24
Peak memory 218132 kb
Host smart-cc529300-efbc-4ff5-abd4-ee087600d7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361350774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1361350774
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1893701987
Short name T553
Test name
Test status
Simulation time 213352903 ps
CPU time 6.91 seconds
Started May 05 01:45:50 PM PDT 24
Finished May 05 01:45:57 PM PDT 24
Peak memory 218040 kb
Host smart-71a485be-e4b8-46d3-b095-a9cbe25ff5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893701987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1893701987
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2169808096
Short name T284
Test name
Test status
Simulation time 244111807 ps
CPU time 24.89 seconds
Started May 05 01:46:01 PM PDT 24
Finished May 05 01:46:26 PM PDT 24
Peak memory 247664 kb
Host smart-9ad838d8-b754-42f5-8560-ae9f4d49fe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169808096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2169808096
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1195256252
Short name T681
Test name
Test status
Simulation time 130672266 ps
CPU time 7.8 seconds
Started May 05 01:46:03 PM PDT 24
Finished May 05 01:46:11 PM PDT 24
Peak memory 246168 kb
Host smart-0f20ec7e-65dc-4640-bcff-60923a69912e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195256252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1195256252
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.4255714488
Short name T583
Test name
Test status
Simulation time 7429706025 ps
CPU time 71.92 seconds
Started May 05 01:45:49 PM PDT 24
Finished May 05 01:47:01 PM PDT 24
Peak memory 250984 kb
Host smart-41e47b98-293d-4bb8-8e22-599162f0233b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255714488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.4255714488
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.3322487583
Short name T863
Test name
Test status
Simulation time 17013912440 ps
CPU time 88.29 seconds
Started May 05 01:45:57 PM PDT 24
Finished May 05 01:47:26 PM PDT 24
Peak memory 267648 kb
Host smart-cd5eb5cf-5677-4530-bc0a-f8e3f7427dbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3322487583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.3322487583
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2536994689
Short name T191
Test name
Test status
Simulation time 42734916 ps
CPU time 0.99 seconds
Started May 05 01:45:57 PM PDT 24
Finished May 05 01:45:58 PM PDT 24
Peak memory 211744 kb
Host smart-0e50e446-498b-483f-9bcf-c65ebabb3686
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536994689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2536994689
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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