Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50514 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
592 |
auto[1] |
1693 |
1 |
|
|
T3 |
4 |
|
T14 |
12 |
|
T15 |
45 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51462 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
596 |
auto[1] |
745 |
1 |
|
|
T36 |
13 |
|
T51 |
14 |
|
T52 |
7 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50487 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
560 |
auto[1] |
1720 |
1 |
|
|
T3 |
36 |
|
T10 |
1 |
|
T15 |
54 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50425 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
559 |
auto[1] |
1782 |
1 |
|
|
T3 |
37 |
|
T15 |
48 |
|
T18 |
1 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50303 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
541 |
auto[1] |
1904 |
1 |
|
|
T3 |
55 |
|
T15 |
53 |
|
T18 |
8 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
47263 |
1 |
|
|
T2 |
3 |
|
T3 |
483 |
|
T10 |
5 |
no_err_inj |
4944 |
1 |
|
|
T1 |
8 |
|
T3 |
113 |
|
T9 |
1 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50475 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
589 |
auto[1] |
1732 |
1 |
|
|
T3 |
7 |
|
T14 |
9 |
|
T15 |
52 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51471 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
596 |
auto[1] |
736 |
1 |
|
|
T36 |
18 |
|
T51 |
21 |
|
T52 |
17 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37552 |
1 |
|
|
T2 |
3 |
|
T3 |
287 |
|
T9 |
1 |
auto[1] |
14655 |
1 |
|
|
T1 |
8 |
|
T3 |
309 |
|
T4 |
19 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50381 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
560 |
auto[1] |
1826 |
1 |
|
|
T3 |
36 |
|
T15 |
41 |
|
T18 |
8 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50321 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
545 |
auto[1] |
1886 |
1 |
|
|
T3 |
51 |
|
T10 |
1 |
|
T15 |
50 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50362 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
553 |
auto[1] |
1845 |
1 |
|
|
T3 |
43 |
|
T15 |
46 |
|
T18 |
7 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50556 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
589 |
auto[1] |
1651 |
1 |
|
|
T3 |
7 |
|
T14 |
13 |
|
T15 |
49 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49923 |
1 |
|
|
T1 |
8 |
|
T3 |
552 |
|
T9 |
1 |
auto[1] |
2284 |
1 |
|
|
T2 |
3 |
|
T3 |
44 |
|
T15 |
51 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51432 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
596 |
auto[1] |
775 |
1 |
|
|
T36 |
9 |
|
T51 |
24 |
|
T52 |
18 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51448 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
596 |
auto[1] |
759 |
1 |
|
|
T36 |
16 |
|
T51 |
23 |
|
T52 |
10 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51446 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
596 |
auto[1] |
761 |
1 |
|
|
T36 |
11 |
|
T51 |
7 |
|
T52 |
10 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49563 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
560 |
auto[1] |
2644 |
1 |
|
|
T3 |
36 |
|
T10 |
10 |
|
T15 |
60 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48608 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
596 |
auto[1] |
3599 |
1 |
|
|
T11 |
66 |
|
T12 |
80 |
|
T31 |
79 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50368 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
553 |
auto[1] |
1839 |
1 |
|
|
T3 |
43 |
|
T15 |
49 |
|
T18 |
9 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50324 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
541 |
auto[1] |
1883 |
1 |
|
|
T3 |
55 |
|
T10 |
2 |
|
T15 |
52 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50382 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
553 |
auto[1] |
1825 |
1 |
|
|
T3 |
43 |
|
T10 |
1 |
|
T15 |
51 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50527 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
592 |
auto[1] |
1680 |
1 |
|
|
T3 |
4 |
|
T14 |
11 |
|
T15 |
41 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46723 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
592 |
auto[1] |
5484 |
1 |
|
|
T3 |
4 |
|
T14 |
12 |
|
T15 |
40 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48454 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
596 |
auto[1] |
3753 |
1 |
|
|
T16 |
96 |
|
T40 |
51 |
|
T50 |
68 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52207 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
596 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50490 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
593 |
auto[1] |
1717 |
1 |
|
|
T3 |
3 |
|
T14 |
8 |
|
T15 |
45 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50500 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
589 |
auto[1] |
1707 |
1 |
|
|
T3 |
7 |
|
T14 |
10 |
|
T15 |
21 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50530 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
592 |
auto[1] |
1677 |
1 |
|
|
T3 |
4 |
|
T14 |
11 |
|
T15 |
27 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
45961 |
1 |
|
|
T2 |
3 |
|
T3 |
463 |
|
T11 |
66 |
auto[0] |
no_err_inj |
3602 |
1 |
|
|
T1 |
8 |
|
T3 |
97 |
|
T9 |
1 |
auto[1] |
err_inj |
1302 |
1 |
|
|
T3 |
20 |
|
T10 |
5 |
|
T15 |
27 |
auto[1] |
no_err_inj |
1342 |
1 |
|
|
T3 |
16 |
|
T10 |
5 |
|
T15 |
33 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47817 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
506 |
auto[0] |
auto[1] |
1746 |
1 |
|
|
T3 |
54 |
|
T15 |
50 |
|
T18 |
6 |
auto[1] |
auto[0] |
2507 |
1 |
|
|
T3 |
35 |
|
T10 |
8 |
|
T15 |
58 |
auto[1] |
auto[1] |
137 |
1 |
|
|
T3 |
1 |
|
T10 |
2 |
|
T15 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47835 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
513 |
auto[0] |
auto[1] |
1728 |
1 |
|
|
T3 |
47 |
|
T15 |
48 |
|
T18 |
6 |
auto[1] |
auto[0] |
2486 |
1 |
|
|
T3 |
32 |
|
T10 |
9 |
|
T15 |
58 |
auto[1] |
auto[1] |
158 |
1 |
|
|
T3 |
4 |
|
T10 |
1 |
|
T15 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47878 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
517 |
auto[0] |
auto[1] |
1685 |
1 |
|
|
T3 |
43 |
|
T15 |
48 |
|
T18 |
2 |
auto[1] |
auto[0] |
2504 |
1 |
|
|
T3 |
36 |
|
T10 |
9 |
|
T15 |
57 |
auto[1] |
auto[1] |
140 |
1 |
|
|
T10 |
1 |
|
T15 |
3 |
|
T19 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47909 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
524 |
auto[0] |
auto[1] |
1654 |
1 |
|
|
T3 |
36 |
|
T15 |
47 |
|
T18 |
1 |
auto[1] |
auto[0] |
2516 |
1 |
|
|
T3 |
35 |
|
T10 |
10 |
|
T15 |
59 |
auto[1] |
auto[1] |
128 |
1 |
|
|
T3 |
1 |
|
T15 |
1 |
|
T34 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47831 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
510 |
auto[0] |
auto[1] |
1732 |
1 |
|
|
T3 |
50 |
|
T15 |
47 |
|
T18 |
8 |
auto[1] |
auto[0] |
2472 |
1 |
|
|
T3 |
31 |
|
T10 |
10 |
|
T15 |
54 |
auto[1] |
auto[1] |
172 |
1 |
|
|
T3 |
5 |
|
T15 |
6 |
|
T34 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47981 |
1 |
|
|
T1 |
8 |
|
T2 |
3 |
|
T3 |
525 |
auto[0] |
auto[1] |
1582 |
1 |
|
|
T3 |
35 |
|
T15 |
50 |
|
T18 |
5 |
auto[1] |
auto[0] |
2506 |
1 |
|
|
T3 |
35 |
|
T10 |
9 |
|
T15 |
56 |
auto[1] |
auto[1] |
138 |
1 |
|
|
T3 |
1 |
|
T10 |
1 |
|
T15 |
4 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36506 |
1 |
|
|
T2 |
3 |
|
T3 |
283 |
|
T9 |
1 |
auto[0] |
auto[1] |
1046 |
1 |
|
|
T3 |
4 |
|
T14 |
12 |
|
T15 |
25 |
auto[1] |
auto[0] |
14008 |
1 |
|
|
T1 |
8 |
|
T3 |
309 |
|
T4 |
19 |
auto[1] |
auto[1] |
647 |
1 |
|
|
T15 |
20 |
|
T19 |
18 |
|
T35 |
10 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36463 |
1 |
|
|
T2 |
3 |
|
T3 |
280 |
|
T9 |
1 |
auto[0] |
auto[1] |
1089 |
1 |
|
|
T3 |
7 |
|
T14 |
9 |
|
T15 |
29 |
auto[1] |
auto[0] |
14012 |
1 |
|
|
T1 |
8 |
|
T3 |
309 |
|
T4 |
19 |
auto[1] |
auto[1] |
643 |
1 |
|
|
T15 |
23 |
|
T19 |
18 |
|
T35 |
7 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36239 |
1 |
|
|
T3 |
258 |
|
T9 |
1 |
|
T10 |
10 |
auto[0] |
auto[1] |
1313 |
1 |
|
|
T2 |
3 |
|
T3 |
29 |
|
T15 |
15 |
auto[1] |
auto[0] |
13684 |
1 |
|
|
T1 |
8 |
|
T3 |
294 |
|
T4 |
19 |
auto[1] |
auto[1] |
971 |
1 |
|
|
T3 |
15 |
|
T15 |
36 |
|
T19 |
3 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36511 |
1 |
|
|
T2 |
3 |
|
T3 |
280 |
|
T9 |
1 |
auto[0] |
auto[1] |
1041 |
1 |
|
|
T3 |
7 |
|
T14 |
13 |
|
T15 |
30 |
auto[1] |
auto[0] |
14045 |
1 |
|
|
T1 |
8 |
|
T3 |
309 |
|
T4 |
19 |
auto[1] |
auto[1] |
610 |
1 |
|
|
T15 |
19 |
|
T19 |
18 |
|
T35 |
13 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32682 |
1 |
|
|
T2 |
3 |
|
T3 |
283 |
|
T9 |
1 |
auto[0] |
auto[1] |
4870 |
1 |
|
|
T3 |
4 |
|
T14 |
12 |
|
T15 |
13 |
auto[1] |
auto[0] |
14041 |
1 |
|
|
T1 |
8 |
|
T3 |
309 |
|
T4 |
19 |
auto[1] |
auto[1] |
614 |
1 |
|
|
T15 |
27 |
|
T19 |
13 |
|
T35 |
2 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36413 |
1 |
|
|
T2 |
3 |
|
T3 |
264 |
|
T9 |
1 |
auto[0] |
auto[1] |
1139 |
1 |
|
|
T3 |
23 |
|
T10 |
2 |
|
T15 |
43 |
auto[1] |
auto[0] |
13911 |
1 |
|
|
T1 |
8 |
|
T3 |
277 |
|
T4 |
19 |
auto[1] |
auto[1] |
744 |
1 |
|
|
T3 |
32 |
|
T15 |
9 |
|
T18 |
6 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36451 |
1 |
|
|
T2 |
3 |
|
T3 |
275 |
|
T9 |
1 |
auto[0] |
auto[1] |
1101 |
1 |
|
|
T3 |
12 |
|
T15 |
38 |
|
T34 |
2 |
auto[1] |
auto[0] |
13917 |
1 |
|
|
T1 |
8 |
|
T3 |
278 |
|
T4 |
19 |
auto[1] |
auto[1] |
738 |
1 |
|
|
T3 |
31 |
|
T15 |
11 |
|
T18 |
9 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36390 |
1 |
|
|
T2 |
3 |
|
T3 |
266 |
|
T9 |
1 |
auto[0] |
auto[1] |
1162 |
1 |
|
|
T3 |
21 |
|
T10 |
1 |
|
T15 |
38 |
auto[1] |
auto[0] |
13931 |
1 |
|
|
T1 |
8 |
|
T3 |
279 |
|
T4 |
19 |
auto[1] |
auto[1] |
724 |
1 |
|
|
T3 |
30 |
|
T15 |
12 |
|
T18 |
6 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36484 |
1 |
|
|
T2 |
3 |
|
T3 |
277 |
|
T9 |
1 |
auto[0] |
auto[1] |
1068 |
1 |
|
|
T3 |
10 |
|
T15 |
31 |
|
T34 |
1 |
auto[1] |
auto[0] |
13897 |
1 |
|
|
T1 |
8 |
|
T3 |
283 |
|
T4 |
19 |
auto[1] |
auto[1] |
758 |
1 |
|
|
T3 |
26 |
|
T15 |
10 |
|
T18 |
8 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36456 |
1 |
|
|
T2 |
3 |
|
T3 |
276 |
|
T9 |
1 |
auto[0] |
auto[1] |
1096 |
1 |
|
|
T3 |
11 |
|
T15 |
37 |
|
T34 |
2 |
auto[1] |
auto[0] |
13969 |
1 |
|
|
T1 |
8 |
|
T3 |
283 |
|
T4 |
19 |
auto[1] |
auto[1] |
686 |
1 |
|
|
T3 |
26 |
|
T15 |
11 |
|
T18 |
1 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36514 |
1 |
|
|
T2 |
3 |
|
T3 |
273 |
|
T9 |
1 |
auto[0] |
auto[1] |
1038 |
1 |
|
|
T3 |
14 |
|
T10 |
1 |
|
T15 |
43 |
auto[1] |
auto[0] |
13973 |
1 |
|
|
T1 |
8 |
|
T3 |
287 |
|
T4 |
19 |
auto[1] |
auto[1] |
682 |
1 |
|
|
T3 |
22 |
|
T15 |
11 |
|
T18 |
5 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36452 |
1 |
|
|
T2 |
3 |
|
T3 |
283 |
|
T9 |
1 |
auto[0] |
auto[1] |
1100 |
1 |
|
|
T3 |
4 |
|
T14 |
11 |
|
T15 |
11 |
auto[1] |
auto[0] |
14078 |
1 |
|
|
T1 |
8 |
|
T3 |
309 |
|
T4 |
19 |
auto[1] |
auto[1] |
577 |
1 |
|
|
T15 |
16 |
|
T19 |
15 |
|
T35 |
13 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36455 |
1 |
|
|
T2 |
3 |
|
T3 |
280 |
|
T9 |
1 |
auto[0] |
auto[1] |
1097 |
1 |
|
|
T3 |
7 |
|
T14 |
10 |
|
T15 |
10 |
auto[1] |
auto[0] |
14045 |
1 |
|
|
T1 |
8 |
|
T3 |
309 |
|
T4 |
19 |
auto[1] |
auto[1] |
610 |
1 |
|
|
T15 |
11 |
|
T19 |
15 |
|
T35 |
10 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36077 |
1 |
|
|
T2 |
3 |
|
T3 |
261 |
|
T9 |
1 |
auto[0] |
auto[1] |
1475 |
1 |
|
|
T3 |
26 |
|
T10 |
10 |
|
T15 |
25 |
auto[1] |
auto[0] |
13486 |
1 |
|
|
T1 |
8 |
|
T3 |
299 |
|
T4 |
19 |
auto[1] |
auto[1] |
1169 |
1 |
|
|
T3 |
10 |
|
T15 |
35 |
|
T19 |
11 |