Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93300431

1

T1

15731

T2

1676

T3

187557

auto[1]

1345367

1

T2

297

T3

16037

T10

99

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93293801

1

T1

15731

T2

1973

T3

187212

auto[1]

1351997

1

T3

19485

T10

297

T11

10570

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6797507	1			T1	736		T2	355		T3	140623
auto[IdleSt]	19321181	1			T1	10531		T2	975		T3	192480
auto[ClkMuxSt]	34514	1			T1	8		T2	3		T3	195
auto[CntIncrSt]	34290	1			T1	8		T2	3		T3	195
auto[CntProgSt]	1457505	1			T1	16		T2	6		T3	373
auto[TransCheckSt]	26801	1			T1	8		T3	141		T9	1
auto[TokenHashSt]	39471843	1			T1	2174		T3	813639		T9	162
auto[FlashRmaSt]	27755	1			T1	12		T3	223		T9	1
auto[TokenCheck0St]	12525	1			T1	8		T3	125		T9	1
auto[TokenCheck1St]	9295	1			T1	8		T3	119		T9	1
auto[TransProgSt]	400238	1			T1	16		T3	236		T9	32
auto[PostTransSt]	10962314	1			T1	2206		T2	221		T3	59885
auto[ScrapSt]	183455	1			T3	2254		T4	233		T13	28
auto[EscalateSt]	6107173	1			T2	410		T3	175050		T10	799
auto[InvalidSt]	9797445	1			T3	506021		T10	518		T15	172046

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1957	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	9797445	1			T3	506021		T10	518		T15	172046
EscalateSt	6107173	1			T2	410		T3	175050		T10	799
ScrapSt	183455	1			T3	2254		T4	233		T13	28
PostTransSt	10962314	1			T1	2206		T2	221		T3	59885
TransProgSt	400238	1			T1	16		T3	236		T9	32
TokenCheck1St	9295	1			T1	8		T3	119		T9	1
TokenCheck0St	12525	1			T1	8		T3	125		T9	1
FlashRmaSt	27755	1			T1	12		T3	223		T9	1
TokenHashSt	39471843	1			T1	2174		T3	813639		T9	162
TransCheckSt	26801	1			T1	8		T3	141		T9	1
CntProgSt	1457505	1			T1	16		T2	6		T3	373
CntIncrSt	34290	1			T1	8		T2	3		T3	195
ClkMuxSt	34514	1			T1	8		T2	3		T3	195
IdleSt	19321181	1			T1	10531		T2	975		T3	192480
ResetSt	6797507	1			T1	736		T2	355		T3	140623
arcs[ResetSt=>IdleSt]	52445	1			T1	8		T2	4		T3	569
arcs[IdleSt=>ScrapSt]	317	1			T3	4		T4	1		T13	1
arcs[IdleSt=>ClkMuxSt]	34355	1			T1	8		T2	3		T3	195
arcs[ClkMuxSt=>CntIncrSt]	34290	1			T1	8		T2	3		T3	195
arcs[CntIncrSt=>PostTransSt]	1707	1			T3	7		T14	10		T15	21
arcs[CntIncrSt=>CntProgSt]	32512	1			T1	8		T2	3		T3	188
arcs[CntProgSt=>PostTransSt]	4669	1			T2	3		T3	47		T14	12
arcs[CntProgSt=>TransCheckSt]	26801	1			T1	8		T3	141		T9	1
arcs[TransCheckSt=>PostTransSt]	3527	1			T3	4		T14	11		T15	27
arcs[TransCheckSt=>TokenHashSt]	23171	1			T1	8		T3	137		T9	1
arcs[TokenHashSt=>PostTransSt]	9885	1			T3	11		T14	31		T15	128
arcs[TokenHashSt=>FlashRmaSt]	12618	1			T1	8		T3	125		T9	1
arcs[FlashRmaSt=>TokenCheck0St]	12525	1			T1	8		T3	125		T9	1
arcs[TokenCheck0St=>PostTransSt]	3194	1			T3	6		T14	9		T15	45
arcs[TokenCheck0St=>TokenCheck1St]	9295	1			T1	8		T3	119		T9	1
arcs[TokenCheck1St=>PostTransSt]	630	1			T3	1		T15	6		T16	6
arcs[TransProgSt=>PostTransSt]	7829	1			T1	8		T3	118		T9	1
arcs[IdleSt=>EscalateSt]	153	1			T11	4		T31	2		T42	7
arcs[ClkMuxSt=>EscalateSt]	65	1			T12	2		T31	4		T41	2
arcs[CntIncrSt=>EscalateSt]	71	1			T31	3		T42	3		T43	1
arcs[CntProgSt=>EscalateSt]	1042	1			T11	22		T12	37		T31	8
arcs[TransCheckSt=>EscalateSt]	103	1			T31	9		T42	1		T43	5
arcs[TokenHashSt=>EscalateSt]	668	1			T3	1		T11	10		T12	9
arcs[FlashRmaSt=>EscalateSt]	93	1			T11	1		T12	2		T31	1
arcs[TokenCheck0St=>EscalateSt]	36	1			T12	1		T41	1		T47	1
arcs[TokenCheck1St=>EscalateSt]	154	1			T11	1		T12	6		T31	5
arcs[TransProgSt=>EscalateSt]	682	1			T11	18		T12	22		T31	13
arcs[PostTransSt=>EscalateSt]	4941	1			T2	3		T3	47		T11	1
arcs[InvalidSt=>EscalateSt]	13610	1			T3	313		T10	4		T15	348

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6797329	1			T1	736		T2	355		T3	140623
auto[0]	auto[IdleSt]	19321077	1			T1	10531		T2	975		T3	192480
auto[0]	auto[ClkMuxSt]	34470	1			T1	8		T2	3		T3	195
auto[0]	auto[CntIncrSt]	34237	1			T1	8		T2	3		T3	195
auto[0]	auto[CntProgSt]	1456806	1			T1	16		T2	6		T3	373
auto[0]	auto[TransCheckSt]	26731	1			T1	8		T3	141		T9	1
auto[0]	auto[TokenHashSt]	39471394	1			T1	2174		T3	813638		T9	162
auto[0]	auto[FlashRmaSt]	27690	1			T1	12		T3	223		T9	1
auto[0]	auto[TokenCheck0St]	12498	1			T1	8		T3	125		T9	1
auto[0]	auto[TokenCheck1St]	9197	1			T1	8		T3	119		T9	1
auto[0]	auto[TransProgSt]	399791	1			T1	16		T3	236		T9	32
auto[0]	auto[PostTransSt]	10959813	1			T1	2206		T2	218		T3	59863
auto[0]	auto[ScrapSt]	183419	1			T3	2254		T4	233		T13	28
auto[0]	auto[EscalateSt]	4773323	1			T2	116		T3	159176		T10	701
auto[0]	auto[InvalidSt]	9790699	1			T3	505881		T10	517		T15	171877
auto[1]	auto[ResetSt]	178	1			T11	7		T12	1		T31	4
auto[1]	auto[IdleSt]	104	1			T11	4		T31	2		T42	2
auto[1]	auto[ClkMuxSt]	44	1			T12	2		T31	1		T41	2
auto[1]	auto[CntIncrSt]	53	1			T31	2		T42	1		T43	1
auto[1]	auto[CntProgSt]	699	1			T11	12		T12	20		T31	8
auto[1]	auto[TransCheckSt]	70	1			T31	6		T42	1		T43	4
auto[1]	auto[TokenHashSt]	449	1			T3	1		T11	6		T12	4
auto[1]	auto[FlashRmaSt]	65	1			T11	1		T12	1		T31	1
auto[1]	auto[TokenCheck0St]	27	1			T41	1		T47	1		T220	1
auto[1]	auto[TokenCheck1St]	98	1			T11	1		T12	2		T31	4
auto[1]	auto[TransProgSt]	447	1			T11	10		T12	16		T31	7
auto[1]	auto[PostTransSt]	2501	1			T2	3		T3	22		T11	1
auto[1]	auto[ScrapSt]	36	1			T41	1		T42	1		T74	2
auto[1]	auto[EscalateSt]	1333850	1			T2	294		T3	15874		T10	98
auto[1]	auto[InvalidSt]	6746	1			T3	140		T10	1		T15	169

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6797336	1			T1	736		T2	355		T3	140623
auto[0]	auto[IdleSt]	19321076	1			T1	10531		T2	975		T3	192480
auto[0]	auto[ClkMuxSt]	34473	1			T1	8		T2	3		T3	195
auto[0]	auto[CntIncrSt]	34243	1			T1	8		T2	3		T3	195
auto[0]	auto[CntProgSt]	1456812	1			T1	16		T2	6		T3	373
auto[0]	auto[TransCheckSt]	26739	1			T1	8		T3	141		T9	1
auto[0]	auto[TokenHashSt]	39471405	1			T1	2174		T3	813639		T9	162
auto[0]	auto[FlashRmaSt]	27694	1			T1	12		T3	223		T9	1
auto[0]	auto[TokenCheck0St]	12508	1			T1	8		T3	125		T9	1
auto[0]	auto[TokenCheck1St]	9182	1			T1	8		T3	119		T9	1
auto[0]	auto[TransProgSt]	399771	1			T1	16		T3	236		T9	32
auto[0]	auto[PostTransSt]	10959794	1			T1	2206		T2	221		T3	59860
auto[0]	auto[ScrapSt]	183408	1			T3	2254		T4	233		T13	28
auto[0]	auto[EscalateSt]	4766822	1			T2	410		T3	155763		T10	505
auto[0]	auto[InvalidSt]	9790581	1			T3	505848		T10	515		T15	171867
auto[1]	auto[ResetSt]	171	1			T11	6		T12	1		T31	4
auto[1]	auto[IdleSt]	105	1			T11	4		T31	2		T42	7
auto[1]	auto[ClkMuxSt]	41	1			T12	2		T31	3		T41	1
auto[1]	auto[CntIncrSt]	47	1			T31	2		T42	2		T47	1
auto[1]	auto[CntProgSt]	693	1			T11	17		T12	26		T31	6
auto[1]	auto[TransCheckSt]	62	1			T31	6		T42	1		T43	3
auto[1]	auto[TokenHashSt]	438	1			T11	7		T12	7		T31	13
auto[1]	auto[FlashRmaSt]	61	1			T12	1		T41	3		T42	1
auto[1]	auto[TokenCheck0St]	17	1			T12	1		T47	1		T220	1
auto[1]	auto[TokenCheck1St]	113	1			T12	6		T31	3		T41	3
auto[1]	auto[TransProgSt]	467	1			T11	13		T12	14		T31	11
auto[1]	auto[PostTransSt]	2520	1			T3	25		T14	10		T15	42
auto[1]	auto[ScrapSt]	47	1			T31	2		T41	1		T74	3
auto[1]	auto[EscalateSt]	1340351	1			T3	19287		T10	294		T11	10523
auto[1]	auto[InvalidSt]	6864	1			T3	173		T10	3		T15	179