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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.89 97.82 96.03 93.31 97.62 98.52 98.51 96.47


Total test records in report: 1002
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T823 /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3620833528 May 07 03:20:33 PM PDT 24 May 07 03:20:44 PM PDT 24 1127403556 ps
T824 /workspace/coverage/default/42.lc_ctrl_errors.1115386906 May 07 03:20:59 PM PDT 24 May 07 03:21:13 PM PDT 24 1089038939 ps
T825 /workspace/coverage/default/46.lc_ctrl_errors.4274628734 May 07 03:21:13 PM PDT 24 May 07 03:21:25 PM PDT 24 307658236 ps
T826 /workspace/coverage/default/13.lc_ctrl_state_failure.576373053 May 07 03:19:43 PM PDT 24 May 07 03:20:12 PM PDT 24 347117581 ps
T827 /workspace/coverage/default/31.lc_ctrl_state_failure.4038108331 May 07 03:20:38 PM PDT 24 May 07 03:21:05 PM PDT 24 199404253 ps
T828 /workspace/coverage/default/36.lc_ctrl_security_escalation.3717375212 May 07 03:20:49 PM PDT 24 May 07 03:20:57 PM PDT 24 763257354 ps
T829 /workspace/coverage/default/31.lc_ctrl_prog_failure.4220578793 May 07 03:20:30 PM PDT 24 May 07 03:20:34 PM PDT 24 154578460 ps
T830 /workspace/coverage/default/37.lc_ctrl_state_post_trans.2851275180 May 07 03:20:48 PM PDT 24 May 07 03:20:58 PM PDT 24 74341802 ps
T831 /workspace/coverage/default/30.lc_ctrl_jtag_access.627105105 May 07 03:20:31 PM PDT 24 May 07 03:20:36 PM PDT 24 430381992 ps
T832 /workspace/coverage/default/27.lc_ctrl_prog_failure.1496369110 May 07 03:20:26 PM PDT 24 May 07 03:20:30 PM PDT 24 173111908 ps
T833 /workspace/coverage/default/37.lc_ctrl_stress_all.4265573797 May 07 03:20:49 PM PDT 24 May 07 03:25:10 PM PDT 24 39943543720 ps
T217 /workspace/coverage/default/2.lc_ctrl_claim_transition_if.4097844685 May 07 03:19:06 PM PDT 24 May 07 03:19:09 PM PDT 24 12970433 ps
T834 /workspace/coverage/default/9.lc_ctrl_security_escalation.2592756868 May 07 03:19:32 PM PDT 24 May 07 03:19:43 PM PDT 24 1151994267 ps
T835 /workspace/coverage/default/15.lc_ctrl_sec_mubi.2022535294 May 07 03:19:49 PM PDT 24 May 07 03:20:07 PM PDT 24 697436810 ps
T836 /workspace/coverage/default/0.lc_ctrl_state_failure.2596228252 May 07 03:18:58 PM PDT 24 May 07 03:19:19 PM PDT 24 358325886 ps
T837 /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.153405068 May 07 03:18:56 PM PDT 24 May 07 03:19:31 PM PDT 24 1097269169 ps
T838 /workspace/coverage/default/27.lc_ctrl_jtag_access.958815780 May 07 03:20:27 PM PDT 24 May 07 03:20:40 PM PDT 24 1807662282 ps
T839 /workspace/coverage/default/18.lc_ctrl_alert_test.501174013 May 07 03:20:01 PM PDT 24 May 07 03:20:03 PM PDT 24 89532153 ps
T840 /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1968462373 May 07 03:19:48 PM PDT 24 May 07 03:19:55 PM PDT 24 669385646 ps
T841 /workspace/coverage/default/20.lc_ctrl_security_escalation.1084619169 May 07 03:20:07 PM PDT 24 May 07 03:20:14 PM PDT 24 237828504 ps
T842 /workspace/coverage/default/29.lc_ctrl_errors.2866948651 May 07 03:20:26 PM PDT 24 May 07 03:20:40 PM PDT 24 305682359 ps
T843 /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.4156067181 May 07 03:19:44 PM PDT 24 May 07 03:19:51 PM PDT 24 302578799 ps
T844 /workspace/coverage/default/38.lc_ctrl_jtag_access.2921806192 May 07 03:20:53 PM PDT 24 May 07 03:21:07 PM PDT 24 1054623165 ps
T845 /workspace/coverage/default/34.lc_ctrl_prog_failure.2836813077 May 07 03:20:42 PM PDT 24 May 07 03:20:48 PM PDT 24 421660843 ps
T846 /workspace/coverage/default/36.lc_ctrl_prog_failure.4218525031 May 07 03:20:43 PM PDT 24 May 07 03:20:49 PM PDT 24 142126160 ps
T847 /workspace/coverage/default/26.lc_ctrl_prog_failure.3481773808 May 07 03:20:20 PM PDT 24 May 07 03:20:24 PM PDT 24 44281423 ps
T848 /workspace/coverage/default/19.lc_ctrl_alert_test.3580421577 May 07 03:20:05 PM PDT 24 May 07 03:20:07 PM PDT 24 40499154 ps
T849 /workspace/coverage/default/8.lc_ctrl_jtag_priority.3447156686 May 07 03:19:24 PM PDT 24 May 07 03:21:04 PM PDT 24 4310910149 ps
T850 /workspace/coverage/default/12.lc_ctrl_alert_test.3854497050 May 07 03:19:42 PM PDT 24 May 07 03:19:45 PM PDT 24 30620420 ps
T851 /workspace/coverage/default/11.lc_ctrl_errors.4177908261 May 07 03:19:30 PM PDT 24 May 07 03:19:45 PM PDT 24 1405480369 ps
T852 /workspace/coverage/default/8.lc_ctrl_regwen_during_op.127583767 May 07 03:19:24 PM PDT 24 May 07 03:19:35 PM PDT 24 265973354 ps
T853 /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.96701503 May 07 03:19:21 PM PDT 24 May 07 03:19:38 PM PDT 24 4442564886 ps
T854 /workspace/coverage/default/21.lc_ctrl_jtag_access.3831531553 May 07 03:20:05 PM PDT 24 May 07 03:20:10 PM PDT 24 635218272 ps
T855 /workspace/coverage/default/5.lc_ctrl_state_failure.2798179824 May 07 03:19:11 PM PDT 24 May 07 03:19:40 PM PDT 24 734302502 ps
T856 /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1275296403 May 07 03:19:23 PM PDT 24 May 07 03:19:41 PM PDT 24 1183421072 ps
T857 /workspace/coverage/default/10.lc_ctrl_jtag_errors.2590963520 May 07 03:19:36 PM PDT 24 May 07 03:20:10 PM PDT 24 1969159303 ps
T858 /workspace/coverage/default/45.lc_ctrl_jtag_access.3844244207 May 07 03:21:11 PM PDT 24 May 07 03:21:24 PM PDT 24 1781132203 ps
T859 /workspace/coverage/default/12.lc_ctrl_prog_failure.1381501767 May 07 03:19:37 PM PDT 24 May 07 03:19:42 PM PDT 24 348514719 ps
T63 /workspace/coverage/default/0.lc_ctrl_smoke.2260113787 May 07 03:19:14 PM PDT 24 May 07 03:19:18 PM PDT 24 45536660 ps
T860 /workspace/coverage/default/19.lc_ctrl_state_post_trans.2573669227 May 07 03:19:58 PM PDT 24 May 07 03:20:02 PM PDT 24 491433250 ps
T861 /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2590490470 May 07 03:19:21 PM PDT 24 May 07 03:19:34 PM PDT 24 1379523419 ps
T862 /workspace/coverage/default/9.lc_ctrl_sec_mubi.162969443 May 07 03:19:32 PM PDT 24 May 07 03:19:49 PM PDT 24 782556179 ps
T863 /workspace/coverage/default/5.lc_ctrl_jtag_priority.2886434601 May 07 03:19:14 PM PDT 24 May 07 03:19:19 PM PDT 24 111174774 ps
T864 /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2254364875 May 07 03:19:16 PM PDT 24 May 07 03:19:20 PM PDT 24 18541871 ps
T162 /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.757304021 May 07 03:19:09 PM PDT 24 May 07 03:56:00 PM PDT 24 115400630455 ps
T865 /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1168214456 May 07 03:19:00 PM PDT 24 May 07 03:19:47 PM PDT 24 9469266000 ps
T866 /workspace/coverage/default/0.lc_ctrl_stress_all.3885581978 May 07 03:18:58 PM PDT 24 May 07 03:20:18 PM PDT 24 4990638032 ps
T867 /workspace/coverage/default/16.lc_ctrl_stress_all.1403274312 May 07 03:19:56 PM PDT 24 May 07 03:22:52 PM PDT 24 4614914693 ps
T868 /workspace/coverage/default/38.lc_ctrl_alert_test.2581382368 May 07 03:20:55 PM PDT 24 May 07 03:20:57 PM PDT 24 19119991 ps
T869 /workspace/coverage/default/13.lc_ctrl_sec_token_mux.4182577921 May 07 03:19:46 PM PDT 24 May 07 03:19:58 PM PDT 24 3280729155 ps
T870 /workspace/coverage/default/31.lc_ctrl_smoke.1950349661 May 07 03:20:30 PM PDT 24 May 07 03:20:35 PM PDT 24 165734987 ps
T871 /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1051207054 May 07 03:20:34 PM PDT 24 May 07 03:20:46 PM PDT 24 370843905 ps
T872 /workspace/coverage/default/8.lc_ctrl_alert_test.2500246275 May 07 03:19:37 PM PDT 24 May 07 03:19:41 PM PDT 24 80894598 ps
T46 /workspace/coverage/default/1.lc_ctrl_sec_cm.880484818 May 07 03:19:14 PM PDT 24 May 07 03:19:54 PM PDT 24 482561360 ps
T873 /workspace/coverage/default/46.lc_ctrl_alert_test.3377162678 May 07 03:21:12 PM PDT 24 May 07 03:21:15 PM PDT 24 123351086 ps
T874 /workspace/coverage/default/18.lc_ctrl_jtag_errors.2123101620 May 07 03:20:02 PM PDT 24 May 07 03:20:44 PM PDT 24 5402729174 ps
T875 /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2067725322 May 07 03:20:08 PM PDT 24 May 07 03:20:11 PM PDT 24 17502131 ps
T876 /workspace/coverage/default/42.lc_ctrl_alert_test.2511352751 May 07 03:21:06 PM PDT 24 May 07 03:21:10 PM PDT 24 57074990 ps
T877 /workspace/coverage/default/2.lc_ctrl_jtag_access.527996327 May 07 03:19:08 PM PDT 24 May 07 03:19:12 PM PDT 24 70215434 ps
T878 /workspace/coverage/default/7.lc_ctrl_sec_mubi.1527438982 May 07 03:19:20 PM PDT 24 May 07 03:19:36 PM PDT 24 1057069825 ps
T879 /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2593678793 May 07 03:21:13 PM PDT 24 May 07 03:21:28 PM PDT 24 295851139 ps
T880 /workspace/coverage/default/15.lc_ctrl_jtag_access.2804075996 May 07 03:19:47 PM PDT 24 May 07 03:19:52 PM PDT 24 697504751 ps
T881 /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.4216883886 May 07 03:19:51 PM PDT 24 May 07 03:19:53 PM PDT 24 44136276 ps
T882 /workspace/coverage/default/38.lc_ctrl_security_escalation.883111684 May 07 03:20:51 PM PDT 24 May 07 03:21:00 PM PDT 24 797614252 ps
T883 /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2181932234 May 07 03:20:11 PM PDT 24 May 07 03:21:08 PM PDT 24 1372393804 ps
T884 /workspace/coverage/default/16.lc_ctrl_state_post_trans.2180838643 May 07 03:19:49 PM PDT 24 May 07 03:19:57 PM PDT 24 506622608 ps
T885 /workspace/coverage/default/39.lc_ctrl_prog_failure.2828057380 May 07 03:20:54 PM PDT 24 May 07 03:20:58 PM PDT 24 68425676 ps
T104 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.801605632 May 07 03:06:42 PM PDT 24 May 07 03:06:45 PM PDT 24 73581902 ps
T92 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.2813494973 May 07 03:07:03 PM PDT 24 May 07 03:07:09 PM PDT 24 226568946 ps
T130 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.4242046291 May 07 03:06:47 PM PDT 24 May 07 03:06:50 PM PDT 24 33506856 ps
T93 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1449811961 May 07 03:07:17 PM PDT 24 May 07 03:07:21 PM PDT 24 75362845 ps
T105 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.411427919 May 07 03:06:54 PM PDT 24 May 07 03:06:57 PM PDT 24 18400372 ps
T98 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2275970914 May 07 03:07:01 PM PDT 24 May 07 03:07:04 PM PDT 24 103933299 ps
T95 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.625461434 May 07 03:06:45 PM PDT 24 May 07 03:06:50 PM PDT 24 367468903 ps
T100 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3613132092 May 07 03:07:29 PM PDT 24 May 07 03:07:32 PM PDT 24 158512087 ps
T99 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.4071843348 May 07 03:07:25 PM PDT 24 May 07 03:07:28 PM PDT 24 28373427 ps
T138 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1999689623 May 07 03:06:59 PM PDT 24 May 07 03:07:01 PM PDT 24 26867294 ps
T202 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3398689101 May 07 03:06:50 PM PDT 24 May 07 03:06:54 PM PDT 24 47678927 ps
T203 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2579511051 May 07 03:06:57 PM PDT 24 May 07 03:07:00 PM PDT 24 23469481 ps
T128 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1355372379 May 07 03:07:00 PM PDT 24 May 07 03:07:02 PM PDT 24 236746022 ps
T185 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1927392238 May 07 03:07:15 PM PDT 24 May 07 03:07:18 PM PDT 24 33984514 ps
T186 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1479693730 May 07 03:06:55 PM PDT 24 May 07 03:06:57 PM PDT 24 61693904 ps
T125 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.888677874 May 07 03:07:08 PM PDT 24 May 07 03:07:11 PM PDT 24 148166227 ps
T129 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.822584761 May 07 03:06:56 PM PDT 24 May 07 03:06:59 PM PDT 24 214485795 ps
T187 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.250736243 May 07 03:07:13 PM PDT 24 May 07 03:07:15 PM PDT 24 13334983 ps
T152 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2701333456 May 07 03:07:16 PM PDT 24 May 07 03:07:19 PM PDT 24 91591370 ps
T886 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2500214351 May 07 03:07:09 PM PDT 24 May 07 03:07:12 PM PDT 24 17381564 ps
T139 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.4087638485 May 07 03:07:02 PM PDT 24 May 07 03:07:05 PM PDT 24 54005613 ps
T204 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.971309014 May 07 03:07:20 PM PDT 24 May 07 03:07:23 PM PDT 24 169988472 ps
T96 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.3630798250 May 07 03:07:25 PM PDT 24 May 07 03:07:28 PM PDT 24 82909977 ps
T126 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2936560685 May 07 03:07:05 PM PDT 24 May 07 03:07:14 PM PDT 24 280836513 ps
T188 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.305942120 May 07 03:07:07 PM PDT 24 May 07 03:07:10 PM PDT 24 59146940 ps
T127 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.939895877 May 07 03:07:03 PM PDT 24 May 07 03:07:08 PM PDT 24 164585642 ps
T140 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3118864018 May 07 03:06:56 PM PDT 24 May 07 03:06:58 PM PDT 24 81900093 ps
T887 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2402941091 May 07 03:07:04 PM PDT 24 May 07 03:07:07 PM PDT 24 21672766 ps
T141 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1176435621 May 07 03:07:03 PM PDT 24 May 07 03:07:06 PM PDT 24 99608600 ps
T97 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3881528919 May 07 03:07:16 PM PDT 24 May 07 03:07:21 PM PDT 24 875050827 ps
T103 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.207577730 May 07 03:07:00 PM PDT 24 May 07 03:07:03 PM PDT 24 188112660 ps
T142 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2858186845 May 07 03:07:12 PM PDT 24 May 07 03:07:15 PM PDT 24 80641959 ps
T205 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1193373702 May 07 03:07:08 PM PDT 24 May 07 03:07:11 PM PDT 24 13733290 ps
T189 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1718020951 May 07 03:06:56 PM PDT 24 May 07 03:06:58 PM PDT 24 17946060 ps
T888 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1964437702 May 07 03:06:41 PM PDT 24 May 07 03:06:45 PM PDT 24 168296274 ps
T206 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3692899908 May 07 03:07:16 PM PDT 24 May 07 03:07:19 PM PDT 24 28019648 ps
T889 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2463247658 May 07 03:06:49 PM PDT 24 May 07 03:06:53 PM PDT 24 169458853 ps
T890 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1102058180 May 07 03:07:08 PM PDT 24 May 07 03:07:13 PM PDT 24 79785272 ps
T114 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2847665495 May 07 03:07:20 PM PDT 24 May 07 03:07:23 PM PDT 24 47598113 ps
T101 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.616942522 May 07 03:07:02 PM PDT 24 May 07 03:07:07 PM PDT 24 42381901 ps
T116 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.160504862 May 07 03:06:48 PM PDT 24 May 07 03:06:52 PM PDT 24 330857655 ps
T891 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.881949179 May 07 03:07:07 PM PDT 24 May 07 03:07:10 PM PDT 24 68937603 ps
T107 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2393342086 May 07 03:06:42 PM PDT 24 May 07 03:06:49 PM PDT 24 364709590 ps
T892 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.297787465 May 07 03:06:49 PM PDT 24 May 07 03:06:53 PM PDT 24 15875621 ps
T108 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2667736168 May 07 03:06:48 PM PDT 24 May 07 03:06:52 PM PDT 24 96418829 ps
T893 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1517504401 May 07 03:07:02 PM PDT 24 May 07 03:07:06 PM PDT 24 60951757 ps
T894 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.2599492125 May 07 03:06:54 PM PDT 24 May 07 03:07:00 PM PDT 24 405132228 ps
T120 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3320159216 May 07 03:06:50 PM PDT 24 May 07 03:06:55 PM PDT 24 83977777 ps
T895 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.50550684 May 07 03:07:03 PM PDT 24 May 07 03:07:06 PM PDT 24 206903618 ps
T190 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2297695154 May 07 03:06:47 PM PDT 24 May 07 03:06:50 PM PDT 24 21991528 ps
T896 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3985180541 May 07 03:07:03 PM PDT 24 May 07 03:07:05 PM PDT 24 17092076 ps
T191 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1128314844 May 07 03:07:17 PM PDT 24 May 07 03:07:20 PM PDT 24 31132255 ps
T897 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.240050895 May 07 03:07:02 PM PDT 24 May 07 03:07:05 PM PDT 24 97518611 ps
T898 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3087859266 May 07 03:07:16 PM PDT 24 May 07 03:07:19 PM PDT 24 36647055 ps
T899 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.881093571 May 07 03:06:58 PM PDT 24 May 07 03:07:01 PM PDT 24 110874681 ps
T900 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.13627008 May 07 03:06:49 PM PDT 24 May 07 03:06:53 PM PDT 24 40468595 ps
T901 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3599180895 May 07 03:06:56 PM PDT 24 May 07 03:06:59 PM PDT 24 93943255 ps
T902 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.362660065 May 07 03:07:21 PM PDT 24 May 07 03:07:24 PM PDT 24 121208217 ps
T106 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2110174892 May 07 03:07:17 PM PDT 24 May 07 03:07:21 PM PDT 24 88301649 ps
T192 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3376600205 May 07 03:07:29 PM PDT 24 May 07 03:07:31 PM PDT 24 53277277 ps
T903 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.426022447 May 07 03:07:09 PM PDT 24 May 07 03:07:13 PM PDT 24 184832670 ps
T904 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2729407803 May 07 03:06:54 PM PDT 24 May 07 03:06:57 PM PDT 24 119677032 ps
T905 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.406423102 May 07 03:07:09 PM PDT 24 May 07 03:07:22 PM PDT 24 2546442477 ps
T906 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4028874694 May 07 03:07:14 PM PDT 24 May 07 03:07:17 PM PDT 24 16586957 ps
T193 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3152775479 May 07 03:06:45 PM PDT 24 May 07 03:06:47 PM PDT 24 16461169 ps
T110 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2548277325 May 07 03:07:10 PM PDT 24 May 07 03:07:14 PM PDT 24 58933478 ps
T117 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1539228452 May 07 03:07:13 PM PDT 24 May 07 03:07:16 PM PDT 24 67685963 ps
T195 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.466443586 May 07 03:06:50 PM PDT 24 May 07 03:06:54 PM PDT 24 46319740 ps
T111 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3931483309 May 07 03:07:05 PM PDT 24 May 07 03:07:11 PM PDT 24 131510061 ps
T907 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.625512726 May 07 03:06:46 PM PDT 24 May 07 03:06:49 PM PDT 24 421821391 ps
T908 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2723042452 May 07 03:06:56 PM PDT 24 May 07 03:06:59 PM PDT 24 157616923 ps
T909 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2465875855 May 07 03:06:56 PM PDT 24 May 07 03:06:58 PM PDT 24 87755251 ps
T910 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3176935579 May 07 03:07:17 PM PDT 24 May 07 03:07:20 PM PDT 24 15435093 ps
T911 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2649665659 May 07 03:06:49 PM PDT 24 May 07 03:06:52 PM PDT 24 57495550 ps
T912 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2863566624 May 07 03:07:03 PM PDT 24 May 07 03:07:06 PM PDT 24 155456828 ps
T913 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1864592369 May 07 03:06:42 PM PDT 24 May 07 03:06:45 PM PDT 24 145707423 ps
T914 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1042835242 May 07 03:07:01 PM PDT 24 May 07 03:07:06 PM PDT 24 132953734 ps
T915 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.857182594 May 07 03:07:09 PM PDT 24 May 07 03:07:13 PM PDT 24 186528139 ps
T916 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.3375113234 May 07 03:06:57 PM PDT 24 May 07 03:07:06 PM PDT 24 615540956 ps
T119 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.241777650 May 07 03:07:04 PM PDT 24 May 07 03:07:09 PM PDT 24 680224644 ps
T917 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2331360681 May 07 03:07:22 PM PDT 24 May 07 03:07:24 PM PDT 24 28920377 ps
T918 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1270703043 May 07 03:07:23 PM PDT 24 May 07 03:07:26 PM PDT 24 109767167 ps
T919 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2790145983 May 07 03:06:50 PM PDT 24 May 07 03:06:54 PM PDT 24 21111582 ps
T920 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1515698830 May 07 03:07:02 PM PDT 24 May 07 03:07:05 PM PDT 24 32421411 ps
T921 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2313829929 May 07 03:06:48 PM PDT 24 May 07 03:06:53 PM PDT 24 527195233 ps
T922 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3260345578 May 07 03:07:20 PM PDT 24 May 07 03:07:23 PM PDT 24 33235915 ps
T923 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.975655013 May 07 03:07:23 PM PDT 24 May 07 03:07:26 PM PDT 24 27185507 ps
T924 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1165102551 May 07 03:07:08 PM PDT 24 May 07 03:07:11 PM PDT 24 162963215 ps
T925 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2761240702 May 07 03:07:09 PM PDT 24 May 07 03:07:12 PM PDT 24 95323450 ps
T926 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3295142572 May 07 03:07:03 PM PDT 24 May 07 03:07:06 PM PDT 24 45987663 ps
T927 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1260036539 May 07 03:07:20 PM PDT 24 May 07 03:07:22 PM PDT 24 12088456 ps
T928 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.234968648 May 07 03:06:53 PM PDT 24 May 07 03:07:04 PM PDT 24 945959178 ps
T929 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1554451164 May 07 03:06:54 PM PDT 24 May 07 03:06:59 PM PDT 24 429098992 ps
T930 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.4053405715 May 07 03:07:17 PM PDT 24 May 07 03:07:20 PM PDT 24 26552318 ps
T931 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3599650920 May 07 03:07:23 PM PDT 24 May 07 03:07:27 PM PDT 24 77514537 ps
T932 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1826181529 May 07 03:07:03 PM PDT 24 May 07 03:07:08 PM PDT 24 107290599 ps
T115 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1882682952 May 07 03:07:16 PM PDT 24 May 07 03:07:21 PM PDT 24 749342181 ps
T933 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3198338049 May 07 03:07:02 PM PDT 24 May 07 03:07:06 PM PDT 24 43024713 ps
T934 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3668345550 May 07 03:06:42 PM PDT 24 May 07 03:06:50 PM PDT 24 613592611 ps
T935 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1028127877 May 07 03:07:14 PM PDT 24 May 07 03:07:17 PM PDT 24 91541521 ps
T936 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3499227332 May 07 03:06:54 PM PDT 24 May 07 03:06:57 PM PDT 24 20351952 ps
T937 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4038698811 May 07 03:07:08 PM PDT 24 May 07 03:07:14 PM PDT 24 96006588 ps
T938 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.414214048 May 07 03:06:54 PM PDT 24 May 07 03:06:56 PM PDT 24 31142043 ps
T939 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.847471247 May 07 03:06:50 PM PDT 24 May 07 03:06:54 PM PDT 24 40497454 ps
T940 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.403804346 May 07 03:07:11 PM PDT 24 May 07 03:07:16 PM PDT 24 218604212 ps
T941 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3646230790 May 07 03:06:48 PM PDT 24 May 07 03:06:52 PM PDT 24 52120097 ps
T112 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3306918733 May 07 03:06:54 PM PDT 24 May 07 03:06:59 PM PDT 24 80158576 ps
T942 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.4280169611 May 07 03:07:15 PM PDT 24 May 07 03:07:19 PM PDT 24 223031775 ps
T199 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1059409294 May 07 03:06:55 PM PDT 24 May 07 03:06:58 PM PDT 24 90053377 ps
T943 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2065931534 May 07 03:07:01 PM PDT 24 May 07 03:07:05 PM PDT 24 185310055 ps
T944 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.809283414 May 07 03:07:03 PM PDT 24 May 07 03:07:06 PM PDT 24 91563248 ps
T218 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3409814817 May 07 03:07:12 PM PDT 24 May 07 03:07:16 PM PDT 24 218662285 ps
T945 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1648497288 May 07 03:06:50 PM PDT 24 May 07 03:07:13 PM PDT 24 3217334054 ps
T946 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3409769881 May 07 03:06:50 PM PDT 24 May 07 03:06:54 PM PDT 24 67281243 ps
T194 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.417627763 May 07 03:07:16 PM PDT 24 May 07 03:07:19 PM PDT 24 15386660 ps
T947 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.217994151 May 07 03:06:51 PM PDT 24 May 07 03:06:55 PM PDT 24 269527044 ps
T948 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1671648765 May 07 03:07:21 PM PDT 24 May 07 03:07:23 PM PDT 24 41030002 ps
T949 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3864124400 May 07 03:07:01 PM PDT 24 May 07 03:07:03 PM PDT 24 22036502 ps
T950 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3178184034 May 07 03:06:50 PM PDT 24 May 07 03:06:57 PM PDT 24 193452450 ps
T951 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.776939749 May 07 03:07:11 PM PDT 24 May 07 03:07:14 PM PDT 24 17326355 ps
T196 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3671257329 May 07 03:06:48 PM PDT 24 May 07 03:06:51 PM PDT 24 44263142 ps
T197 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3181651436 May 07 03:06:57 PM PDT 24 May 07 03:07:00 PM PDT 24 19344299 ps
T952 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1415252614 May 07 03:06:43 PM PDT 24 May 07 03:07:03 PM PDT 24 1480264971 ps
T953 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.941799172 May 07 03:07:04 PM PDT 24 May 07 03:07:07 PM PDT 24 68509563 ps
T954 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.676901419 May 07 03:07:18 PM PDT 24 May 07 03:07:21 PM PDT 24 40074613 ps
T955 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2262812400 May 07 03:07:22 PM PDT 24 May 07 03:07:26 PM PDT 24 43417288 ps
T124 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1411570002 May 07 03:07:01 PM PDT 24 May 07 03:07:04 PM PDT 24 163973359 ps
T956 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1819702536 May 07 03:07:03 PM PDT 24 May 07 03:07:07 PM PDT 24 476695103 ps
T957 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.356127460 May 07 03:07:02 PM PDT 24 May 07 03:07:04 PM PDT 24 18983101 ps
T958 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.4120777605 May 07 03:07:24 PM PDT 24 May 07 03:07:27 PM PDT 24 66130078 ps
T959 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3538349563 May 07 03:07:02 PM PDT 24 May 07 03:07:24 PM PDT 24 3326146223 ps
T960 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.4157393174 May 07 03:06:48 PM PDT 24 May 07 03:06:51 PM PDT 24 59489901 ps
T961 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3891227446 May 07 03:07:01 PM PDT 24 May 07 03:07:03 PM PDT 24 82762447 ps
T962 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1476787995 May 07 03:06:49 PM PDT 24 May 07 03:06:53 PM PDT 24 193842338 ps
T198 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3284316502 May 07 03:06:48 PM PDT 24 May 07 03:06:51 PM PDT 24 78375321 ps
T963 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.246800166 May 07 03:06:50 PM PDT 24 May 07 03:06:54 PM PDT 24 47788598 ps
T964 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1278941194 May 07 03:07:04 PM PDT 24 May 07 03:07:07 PM PDT 24 20096530 ps
T965 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.642225662 May 07 03:07:15 PM PDT 24 May 07 03:07:18 PM PDT 24 21409729 ps
T966 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.4149507982 May 07 03:06:57 PM PDT 24 May 07 03:06:59 PM PDT 24 23748588 ps
T967 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1817392064 May 07 03:06:47 PM PDT 24 May 07 03:06:59 PM PDT 24 1643396677 ps
T968 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.299775883 May 07 03:07:10 PM PDT 24 May 07 03:07:13 PM PDT 24 102266326 ps
T969 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1760652451 May 07 03:07:15 PM PDT 24 May 07 03:07:18 PM PDT 24 118250832 ps
T970 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2747860496 May 07 03:06:48 PM PDT 24 May 07 03:06:51 PM PDT 24 218487446 ps
T971 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2230611979 May 07 03:06:48 PM PDT 24 May 07 03:06:54 PM PDT 24 1097745557 ps
T113 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2446661746 May 07 03:07:11 PM PDT 24 May 07 03:07:17 PM PDT 24 606444165 ps
T972 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1875615851 May 07 03:07:29 PM PDT 24 May 07 03:07:31 PM PDT 24 14716094 ps
T201 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2163973141 May 07 03:06:47 PM PDT 24 May 07 03:06:50 PM PDT 24 91375906 ps
T973 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1967014872 May 07 03:07:16 PM PDT 24 May 07 03:07:20 PM PDT 24 76923385 ps
T200 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3708331872 May 07 03:06:50 PM PDT 24 May 07 03:06:53 PM PDT 24 170670940 ps
T974 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2829775908 May 07 03:06:56 PM PDT 24 May 07 03:07:01 PM PDT 24 169378440 ps
T975 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4083078306 May 07 03:07:11 PM PDT 24 May 07 03:07:14 PM PDT 24 334025101 ps
T109 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3330982017 May 07 03:06:50 PM PDT 24 May 07 03:06:56 PM PDT 24 162423877 ps
T976 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.3095472086 May 07 03:07:16 PM PDT 24 May 07 03:07:20 PM PDT 24 142290614 ps
T121 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.4068404188 May 07 03:07:24 PM PDT 24 May 07 03:07:30 PM PDT 24 270685904 ps
T977 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.192902617 May 07 03:07:07 PM PDT 24 May 07 03:07:20 PM PDT 24 2475918024 ps
T978 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.778989995 May 07 03:07:09 PM PDT 24 May 07 03:07:13 PM PDT 24 146020614 ps
T979 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1189003549 May 07 03:06:56 PM PDT 24 May 07 03:06:59 PM PDT 24 59707803 ps
T122 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3495295302 May 07 03:07:02 PM PDT 24 May 07 03:07:06 PM PDT 24 436285044 ps
T980 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.4287041028 May 07 03:07:15 PM PDT 24 May 07 03:07:19 PM PDT 24 470209959 ps
T981 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.1072111414 May 07 03:07:15 PM PDT 24 May 07 03:07:18 PM PDT 24 55087271 ps
T982 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2485735847 May 07 03:07:21 PM PDT 24 May 07 03:07:23 PM PDT 24 14380131 ps
T983 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4185485042 May 07 03:06:51 PM PDT 24 May 07 03:07:23 PM PDT 24 2412418218 ps
T984 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1236668359 May 07 03:07:17 PM PDT 24 May 07 03:07:23 PM PDT 24 211485641 ps
T985 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.666344723 May 07 03:06:56 PM PDT 24 May 07 03:07:00 PM PDT 24 323328841 ps
T102 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1352979651 May 07 03:07:25 PM PDT 24 May 07 03:07:29 PM PDT 24 148225613 ps
T219 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2063967329 May 07 03:06:57 PM PDT 24 May 07 03:07:01 PM PDT 24 180280752 ps
T986 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.991510868 May 07 03:06:56 PM PDT 24 May 07 03:07:08 PM PDT 24 1703324516 ps
T987 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1992589247 May 07 03:07:02 PM PDT 24 May 07 03:07:04 PM PDT 24 106123614 ps
T988 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2578579054 May 07 03:07:08 PM PDT 24 May 07 03:07:25 PM PDT 24 8402309478 ps
T989 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3302221530 May 07 03:06:53 PM PDT 24 May 07 03:06:56 PM PDT 24 70329773 ps
T990 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3681429631 May 07 03:07:02 PM PDT 24 May 07 03:07:10 PM PDT 24 1297061141 ps
T991 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3999386726 May 07 03:07:17 PM PDT 24 May 07 03:07:21 PM PDT 24 236579782 ps
T992 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3569872425 May 07 03:07:20 PM PDT 24 May 07 03:07:22 PM PDT 24 12929817 ps
T993 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3510420446 May 07 03:06:53 PM PDT 24 May 07 03:06:56 PM PDT 24 123900090 ps
T118 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4235256806 May 07 03:07:22 PM PDT 24 May 07 03:07:25 PM PDT 24 445558877 ps
T994 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3520142945 May 07 03:07:12 PM PDT 24 May 07 03:07:17 PM PDT 24 96065616 ps
T995 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2404506426 May 07 03:07:01 PM PDT 24 May 07 03:07:27 PM PDT 24 2277089064 ps
T996 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.169494545 May 07 03:07:03 PM PDT 24 May 07 03:07:54 PM PDT 24 9457419669 ps
T997 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1072215548 May 07 03:07:21 PM PDT 24 May 07 03:07:24 PM PDT 24 73684810 ps
T998 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1011947575 May 07 03:07:01 PM PDT 24 May 07 03:07:03 PM PDT 24 26246063 ps
T999 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1445274418 May 07 03:07:23 PM PDT 24 May 07 03:07:25 PM PDT 24 13927306 ps
T1000 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2285048492 May 07 03:07:11 PM PDT 24 May 07 03:07:14 PM PDT 24 17515808 ps
T1001 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2453663050 May 07 03:06:49 PM PDT 24 May 07 03:06:53 PM PDT 24 219468748 ps
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