Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52892 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
1861 |
1 |
|
|
T15 |
32 |
|
T16 |
10 |
|
T17 |
8 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53988 |
1 |
|
|
T1 |
53 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
765 |
1 |
|
|
T1 |
18 |
|
T46 |
12 |
|
T62 |
22 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52701 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
9 |
auto[1] |
2052 |
1 |
|
|
T3 |
2 |
|
T15 |
11 |
|
T52 |
5 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52795 |
1 |
|
|
T1 |
71 |
|
T2 |
12 |
|
T3 |
10 |
auto[1] |
1958 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
14 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52772 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
1981 |
1 |
|
|
T15 |
7 |
|
T52 |
5 |
|
T39 |
6 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
49838 |
1 |
|
|
T1 |
71 |
|
T2 |
5 |
|
T3 |
7 |
no_err_inj |
4915 |
1 |
|
|
T2 |
8 |
|
T3 |
4 |
|
T5 |
7 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52891 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
1862 |
1 |
|
|
T15 |
29 |
|
T16 |
9 |
|
T17 |
7 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54000 |
1 |
|
|
T1 |
63 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
753 |
1 |
|
|
T1 |
8 |
|
T46 |
22 |
|
T62 |
17 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38008 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
16745 |
1 |
|
|
T4 |
20 |
|
T5 |
12 |
|
T6 |
5 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52730 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
2023 |
1 |
|
|
T15 |
14 |
|
T52 |
9 |
|
T39 |
7 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52774 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
10 |
auto[1] |
1979 |
1 |
|
|
T3 |
1 |
|
T5 |
2 |
|
T15 |
11 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52739 |
1 |
|
|
T1 |
71 |
|
T2 |
12 |
|
T3 |
10 |
auto[1] |
2014 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
13 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53026 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
1727 |
1 |
|
|
T15 |
26 |
|
T16 |
6 |
|
T17 |
10 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52228 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
2525 |
1 |
|
|
T11 |
18 |
|
T4 |
20 |
|
T13 |
7 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54075 |
1 |
|
|
T1 |
57 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
678 |
1 |
|
|
T1 |
14 |
|
T46 |
10 |
|
T62 |
15 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54035 |
1 |
|
|
T1 |
55 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
718 |
1 |
|
|
T1 |
16 |
|
T46 |
20 |
|
T62 |
20 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54030 |
1 |
|
|
T1 |
56 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
723 |
1 |
|
|
T1 |
15 |
|
T46 |
15 |
|
T62 |
22 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51962 |
1 |
|
|
T1 |
71 |
|
T11 |
18 |
|
T4 |
20 |
auto[1] |
2791 |
1 |
|
|
T2 |
13 |
|
T3 |
11 |
|
T5 |
12 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50949 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
3804 |
1 |
|
|
T14 |
99 |
|
T25 |
51 |
|
T53 |
58 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52818 |
1 |
|
|
T1 |
71 |
|
T2 |
11 |
|
T3 |
11 |
auto[1] |
1935 |
1 |
|
|
T2 |
2 |
|
T5 |
1 |
|
T15 |
13 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52752 |
1 |
|
|
T1 |
71 |
|
T2 |
12 |
|
T3 |
9 |
auto[1] |
2001 |
1 |
|
|
T2 |
1 |
|
T3 |
2 |
|
T15 |
10 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52707 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
2046 |
1 |
|
|
T5 |
2 |
|
T15 |
10 |
|
T52 |
7 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52973 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
1780 |
1 |
|
|
T15 |
28 |
|
T16 |
5 |
|
T17 |
13 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49054 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
5699 |
1 |
|
|
T15 |
18 |
|
T18 |
89 |
|
T16 |
3 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51153 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
3600 |
1 |
|
|
T22 |
69 |
|
T69 |
54 |
|
T70 |
54 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54753 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52931 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
1822 |
1 |
|
|
T15 |
34 |
|
T16 |
9 |
|
T17 |
14 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52942 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
1811 |
1 |
|
|
T15 |
35 |
|
T16 |
9 |
|
T17 |
10 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53032 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[1] |
1721 |
1 |
|
|
T15 |
24 |
|
T16 |
8 |
|
T17 |
7 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
48385 |
1 |
|
|
T1 |
71 |
|
T11 |
18 |
|
T4 |
20 |
auto[0] |
no_err_inj |
3577 |
1 |
|
|
T6 |
5 |
|
T15 |
10 |
|
T28 |
11 |
auto[1] |
err_inj |
1453 |
1 |
|
|
T2 |
5 |
|
T3 |
7 |
|
T5 |
5 |
auto[1] |
no_err_inj |
1338 |
1 |
|
|
T2 |
8 |
|
T3 |
4 |
|
T5 |
7 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50115 |
1 |
|
|
T1 |
71 |
|
T11 |
18 |
|
T4 |
20 |
auto[0] |
auto[1] |
1847 |
1 |
|
|
T15 |
10 |
|
T52 |
12 |
|
T39 |
9 |
auto[1] |
auto[0] |
2637 |
1 |
|
|
T2 |
12 |
|
T3 |
9 |
|
T5 |
12 |
auto[1] |
auto[1] |
154 |
1 |
|
|
T2 |
1 |
|
T3 |
2 |
|
T24 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50174 |
1 |
|
|
T1 |
71 |
|
T11 |
18 |
|
T4 |
20 |
auto[0] |
auto[1] |
1788 |
1 |
|
|
T15 |
11 |
|
T52 |
8 |
|
T39 |
7 |
auto[1] |
auto[0] |
2600 |
1 |
|
|
T2 |
13 |
|
T3 |
10 |
|
T5 |
10 |
auto[1] |
auto[1] |
191 |
1 |
|
|
T3 |
1 |
|
T5 |
2 |
|
T47 |
3 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50099 |
1 |
|
|
T1 |
71 |
|
T11 |
18 |
|
T4 |
20 |
auto[0] |
auto[1] |
1863 |
1 |
|
|
T15 |
8 |
|
T52 |
7 |
|
T39 |
10 |
auto[1] |
auto[0] |
2608 |
1 |
|
|
T2 |
13 |
|
T3 |
11 |
|
T5 |
10 |
auto[1] |
auto[1] |
183 |
1 |
|
|
T5 |
2 |
|
T15 |
2 |
|
T47 |
2 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50141 |
1 |
|
|
T1 |
71 |
|
T11 |
18 |
|
T4 |
20 |
auto[0] |
auto[1] |
1821 |
1 |
|
|
T15 |
12 |
|
T52 |
7 |
|
T39 |
17 |
auto[1] |
auto[0] |
2654 |
1 |
|
|
T2 |
12 |
|
T3 |
10 |
|
T5 |
12 |
auto[1] |
auto[1] |
137 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50140 |
1 |
|
|
T1 |
71 |
|
T11 |
18 |
|
T4 |
20 |
auto[0] |
auto[1] |
1822 |
1 |
|
|
T15 |
6 |
|
T52 |
5 |
|
T39 |
6 |
auto[1] |
auto[0] |
2632 |
1 |
|
|
T2 |
13 |
|
T3 |
11 |
|
T5 |
12 |
auto[1] |
auto[1] |
159 |
1 |
|
|
T15 |
1 |
|
T47 |
2 |
|
T19 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50058 |
1 |
|
|
T1 |
71 |
|
T11 |
18 |
|
T4 |
20 |
auto[0] |
auto[1] |
1904 |
1 |
|
|
T15 |
9 |
|
T52 |
5 |
|
T39 |
11 |
auto[1] |
auto[0] |
2643 |
1 |
|
|
T2 |
13 |
|
T3 |
9 |
|
T5 |
12 |
auto[1] |
auto[1] |
148 |
1 |
|
|
T3 |
2 |
|
T15 |
2 |
|
T47 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36887 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[0] |
auto[1] |
1121 |
1 |
|
|
T15 |
10 |
|
T16 |
10 |
|
T17 |
8 |
auto[1] |
auto[0] |
16005 |
1 |
|
|
T4 |
20 |
|
T5 |
12 |
|
T6 |
5 |
auto[1] |
auto[1] |
740 |
1 |
|
|
T15 |
22 |
|
T26 |
12 |
|
T24 |
29 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36880 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[0] |
auto[1] |
1128 |
1 |
|
|
T15 |
6 |
|
T16 |
9 |
|
T17 |
7 |
auto[1] |
auto[0] |
16011 |
1 |
|
|
T4 |
20 |
|
T5 |
12 |
|
T6 |
5 |
auto[1] |
auto[1] |
734 |
1 |
|
|
T15 |
23 |
|
T26 |
12 |
|
T24 |
25 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36646 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[0] |
auto[1] |
1362 |
1 |
|
|
T11 |
18 |
|
T13 |
7 |
|
T193 |
8 |
auto[1] |
auto[0] |
15582 |
1 |
|
|
T5 |
12 |
|
T6 |
5 |
|
T15 |
194 |
auto[1] |
auto[1] |
1163 |
1 |
|
|
T4 |
20 |
|
T24 |
32 |
|
T222 |
6 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36985 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[0] |
auto[1] |
1023 |
1 |
|
|
T15 |
8 |
|
T16 |
6 |
|
T17 |
10 |
auto[1] |
auto[0] |
16041 |
1 |
|
|
T4 |
20 |
|
T5 |
12 |
|
T6 |
5 |
auto[1] |
auto[1] |
704 |
1 |
|
|
T15 |
18 |
|
T26 |
11 |
|
T24 |
29 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33031 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[0] |
auto[1] |
4977 |
1 |
|
|
T15 |
4 |
|
T18 |
89 |
|
T16 |
3 |
auto[1] |
auto[0] |
16023 |
1 |
|
|
T4 |
20 |
|
T5 |
12 |
|
T6 |
5 |
auto[1] |
auto[1] |
722 |
1 |
|
|
T15 |
14 |
|
T26 |
12 |
|
T24 |
21 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36853 |
1 |
|
|
T1 |
71 |
|
T2 |
12 |
|
T3 |
9 |
auto[0] |
auto[1] |
1155 |
1 |
|
|
T2 |
1 |
|
T3 |
2 |
|
T15 |
10 |
auto[1] |
auto[0] |
15899 |
1 |
|
|
T4 |
20 |
|
T5 |
12 |
|
T6 |
5 |
auto[1] |
auto[1] |
846 |
1 |
|
|
T24 |
2 |
|
T68 |
24 |
|
T92 |
14 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36912 |
1 |
|
|
T1 |
71 |
|
T2 |
11 |
|
T3 |
11 |
auto[0] |
auto[1] |
1096 |
1 |
|
|
T2 |
2 |
|
T15 |
12 |
|
T52 |
10 |
auto[1] |
auto[0] |
15906 |
1 |
|
|
T4 |
20 |
|
T5 |
11 |
|
T6 |
5 |
auto[1] |
auto[1] |
839 |
1 |
|
|
T5 |
1 |
|
T15 |
1 |
|
T24 |
1 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36862 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
10 |
auto[0] |
auto[1] |
1146 |
1 |
|
|
T3 |
1 |
|
T15 |
11 |
|
T52 |
8 |
auto[1] |
auto[0] |
15912 |
1 |
|
|
T4 |
20 |
|
T5 |
10 |
|
T6 |
5 |
auto[1] |
auto[1] |
833 |
1 |
|
|
T5 |
2 |
|
T24 |
2 |
|
T68 |
21 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36879 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[0] |
auto[1] |
1129 |
1 |
|
|
T15 |
12 |
|
T52 |
9 |
|
T39 |
7 |
auto[1] |
auto[0] |
15851 |
1 |
|
|
T4 |
20 |
|
T5 |
12 |
|
T6 |
5 |
auto[1] |
auto[1] |
894 |
1 |
|
|
T15 |
2 |
|
T68 |
17 |
|
T92 |
12 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36899 |
1 |
|
|
T1 |
71 |
|
T2 |
12 |
|
T3 |
10 |
auto[0] |
auto[1] |
1109 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T15 |
12 |
auto[1] |
auto[0] |
15896 |
1 |
|
|
T4 |
20 |
|
T5 |
12 |
|
T6 |
5 |
auto[1] |
auto[1] |
849 |
1 |
|
|
T15 |
2 |
|
T24 |
2 |
|
T68 |
16 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36825 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
9 |
auto[0] |
auto[1] |
1183 |
1 |
|
|
T3 |
2 |
|
T15 |
9 |
|
T52 |
5 |
auto[1] |
auto[0] |
15876 |
1 |
|
|
T4 |
20 |
|
T5 |
12 |
|
T6 |
5 |
auto[1] |
auto[1] |
869 |
1 |
|
|
T15 |
2 |
|
T24 |
1 |
|
T68 |
11 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36975 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[0] |
auto[1] |
1033 |
1 |
|
|
T15 |
6 |
|
T16 |
8 |
|
T17 |
7 |
auto[1] |
auto[0] |
16057 |
1 |
|
|
T4 |
20 |
|
T5 |
12 |
|
T6 |
5 |
auto[1] |
auto[1] |
688 |
1 |
|
|
T15 |
18 |
|
T26 |
13 |
|
T24 |
20 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36909 |
1 |
|
|
T1 |
71 |
|
T2 |
13 |
|
T3 |
11 |
auto[0] |
auto[1] |
1099 |
1 |
|
|
T15 |
12 |
|
T16 |
9 |
|
T17 |
10 |
auto[1] |
auto[0] |
16033 |
1 |
|
|
T4 |
20 |
|
T5 |
12 |
|
T6 |
5 |
auto[1] |
auto[1] |
712 |
1 |
|
|
T15 |
23 |
|
T26 |
10 |
|
T24 |
31 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36500 |
1 |
|
|
T1 |
71 |
|
T11 |
18 |
|
T13 |
7 |
auto[0] |
auto[1] |
1508 |
1 |
|
|
T2 |
13 |
|
T3 |
11 |
|
T47 |
15 |
auto[1] |
auto[0] |
15462 |
1 |
|
|
T4 |
20 |
|
T6 |
5 |
|
T15 |
179 |
auto[1] |
auto[1] |
1283 |
1 |
|
|
T5 |
12 |
|
T15 |
15 |
|
T24 |
20 |