Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104298234

1

T1

34410

T2

10141

T3

4311

auto[1]

1446106

1

T1

1485

T2

99

T3

297

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104282861

1

T1

34014

T2

9943

T3

4311

auto[1]

1461479

1

T1

1881

T2

297

T3

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7882992	1			T1	6601		T2	1328		T3	1075
auto[IdleSt]	21826360	1			T1	5105		T2	1980		T3	1317
auto[ClkMuxSt]	35698	1			T1	55		T2	8		T3	4
auto[CntIncrSt]	35374	1			T1	55		T2	8		T3	4
auto[CntProgSt]	1752215	1			T1	751		T2	16		T3	8
auto[TransCheckSt]	27304	1			T1	37		T2	8		T3	4
auto[TokenHashSt]	39800315	1			T1	8029		T2	2631		T3	44
auto[FlashRmaSt]	28290	1			T1	45		T2	8		T3	4
auto[TokenCheck0St]	12563	1			T1	28		T2	8		T3	4
auto[TokenCheck1St]	9312	1			T1	21		T2	8		T3	4
auto[TransProgSt]	406675	1			T1	393		T2	16		T3	8
auto[PostTransSt]	12606156	1			T1	7792		T2	2508		T3	647
auto[ScrapSt]	305807	1			T15	237		T25	3		T43	80
auto[EscalateSt]	7474392	1			T1	4782		T2	1012		T3	1052
auto[InvalidSt]	13538836	1			T1	2201		T2	701		T3	432

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2051	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	13538836	1			T1	2201		T2	701		T3	432
EscalateSt	7474392	1			T1	4782		T2	1012		T3	1052
ScrapSt	305807	1			T15	237		T25	3		T43	80
PostTransSt	12606156	1			T1	7792		T2	2508		T3	647
TransProgSt	406675	1			T1	393		T2	16		T3	8
TokenCheck1St	9312	1			T1	21		T2	8		T3	4
TokenCheck0St	12563	1			T1	28		T2	8		T3	4
FlashRmaSt	28290	1			T1	45		T2	8		T3	4
TokenHashSt	39800315	1			T1	8029		T2	2631		T3	44
TransCheckSt	27304	1			T1	37		T2	8		T3	4
CntProgSt	1752215	1			T1	751		T2	16		T3	8
CntIncrSt	35374	1			T1	55		T2	8		T3	4
ClkMuxSt	35698	1			T1	55		T2	8		T3	4
IdleSt	21826360	1			T1	5105		T2	1980		T3	1317
ResetSt	7882992	1			T1	6601		T2	1328		T3	1075
arcs[ResetSt=>IdleSt]	54912	1			T1	72		T2	13		T3	11
arcs[IdleSt=>ScrapSt]	290	1			T15	1		T25	1		T43	2
arcs[IdleSt=>ClkMuxSt]	35434	1			T1	55		T2	8		T3	4
arcs[ClkMuxSt=>CntIncrSt]	35374	1			T1	55		T2	8		T3	4
arcs[CntIncrSt=>PostTransSt]	1816	1			T15	35		T16	9		T17	10
arcs[CntIncrSt=>CntProgSt]	33483	1			T1	55		T2	8		T3	4
arcs[CntProgSt=>PostTransSt]	5116	1			T1	18		T11	18		T4	20
arcs[CntProgSt=>TransCheckSt]	27304	1			T1	37		T2	8		T3	4
arcs[TransCheckSt=>PostTransSt]	3522	1			T15	24		T16	8		T22	37
arcs[TransCheckSt=>TokenHashSt]	23650	1			T1	37		T2	8		T3	4
arcs[TokenHashSt=>PostTransSt]	10291	1			T1	9		T12	1		T15	80
arcs[TokenHashSt=>FlashRmaSt]	12651	1			T1	28		T2	8		T3	4
arcs[FlashRmaSt=>TokenCheck0St]	12563	1			T1	28		T2	8		T3	4
arcs[TokenCheck0St=>PostTransSt]	3220	1			T1	7		T15	25		T16	5
arcs[TokenCheck0St=>TokenCheck1St]	9312	1			T1	21		T2	8		T3	4
arcs[TokenCheck1St=>PostTransSt]	654	1			T15	3		T16	3		T22	9
arcs[TransProgSt=>PostTransSt]	7787	1			T1	21		T2	8		T3	4
arcs[IdleSt=>EscalateSt]	236	1			T14	10		T53	5		T54	3
arcs[ClkMuxSt=>EscalateSt]	60	1			T14	1		T53	1		T54	3
arcs[CntIncrSt=>EscalateSt]	75	1			T14	3		T53	1		T54	1
arcs[CntProgSt=>EscalateSt]	1063	1			T14	26		T25	22		T53	18
arcs[TransCheckSt=>EscalateSt]	132	1			T14	1		T55	3		T61	8
arcs[TokenHashSt=>EscalateSt]	708	1			T14	12		T25	8		T53	10
arcs[FlashRmaSt=>EscalateSt]	88	1			T14	2		T25	2		T53	1
arcs[TokenCheck0St=>EscalateSt]	31	1			T55	1		T59	1		T60	1
arcs[TokenCheck1St=>EscalateSt]	142	1			T14	8		T53	1		T54	2
arcs[TransProgSt=>EscalateSt]	729	1			T14	32		T25	15		T53	15
arcs[PostTransSt=>EscalateSt]	5393	1			T1	18		T11	18		T4	20
arcs[InvalidSt=>EscalateSt]	14666	1			T1	16		T2	4		T3	6

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7882826	1			T1	6601		T2	1328		T3	1075
auto[0]	auto[IdleSt]	21826205	1			T1	5105		T2	1980		T3	1317
auto[0]	auto[ClkMuxSt]	35659	1			T1	55		T2	8		T3	4
auto[0]	auto[CntIncrSt]	35325	1			T1	55		T2	8		T3	4
auto[0]	auto[CntProgSt]	1751507	1			T1	751		T2	16		T3	8
auto[0]	auto[TransCheckSt]	27223	1			T1	37		T2	8		T3	4
auto[0]	auto[TokenHashSt]	39799852	1			T1	8029		T2	2631		T3	44
auto[0]	auto[FlashRmaSt]	28234	1			T1	45		T2	8		T3	4
auto[0]	auto[TokenCheck0St]	12545	1			T1	28		T2	8		T3	4
auto[0]	auto[TokenCheck1St]	9210	1			T1	21		T2	8		T3	4
auto[0]	auto[TransProgSt]	406175	1			T1	393		T2	16		T3	8
auto[0]	auto[PostTransSt]	12603412	1			T1	7782		T2	2508		T3	647
auto[0]	auto[ScrapSt]	305763	1			T15	237		T25	2		T43	80
auto[0]	auto[EscalateSt]	6040674	1			T1	3312		T2	914		T3	758
auto[0]	auto[InvalidSt]	13531573	1			T1	2196		T2	700		T3	429
auto[1]	auto[ResetSt]	166	1			T14	3		T25	1		T53	3
auto[1]	auto[IdleSt]	155	1			T14	7		T53	2		T54	3
auto[1]	auto[ClkMuxSt]	39	1			T14	1		T53	1		T54	1
auto[1]	auto[CntIncrSt]	49	1			T14	2		T53	1		T54	1
auto[1]	auto[CntProgSt]	708	1			T14	18		T25	13		T53	13
auto[1]	auto[TransCheckSt]	81	1			T14	1		T55	1		T61	5
auto[1]	auto[TokenHashSt]	463	1			T14	7		T25	6		T53	4
auto[1]	auto[FlashRmaSt]	56	1			T14	1		T53	1		T54	1
auto[1]	auto[TokenCheck0St]	18	1			T55	1		T60	1		T177	1
auto[1]	auto[TokenCheck1St]	102	1			T14	6		T53	1		T54	2
auto[1]	auto[TransProgSt]	500	1			T14	25		T25	12		T53	7
auto[1]	auto[PostTransSt]	2744	1			T1	10		T11	8		T4	15
auto[1]	auto[ScrapSt]	44	1			T25	1		T54	1		T61	1
auto[1]	auto[EscalateSt]	1433718	1			T1	1470		T2	98		T3	294
auto[1]	auto[InvalidSt]	7263	1			T1	5		T2	1		T3	3

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7882833	1			T1	6601		T2	1328		T3	1075
auto[0]	auto[IdleSt]	21826206	1			T1	5105		T2	1980		T3	1317
auto[0]	auto[ClkMuxSt]	35651	1			T1	55		T2	8		T3	4
auto[0]	auto[CntIncrSt]	35328	1			T1	55		T2	8		T3	4
auto[0]	auto[CntProgSt]	1751487	1			T1	751		T2	16		T3	8
auto[0]	auto[TransCheckSt]	27204	1			T1	37		T2	8		T3	4
auto[0]	auto[TokenHashSt]	39799834	1			T1	8029		T2	2631		T3	44
auto[0]	auto[FlashRmaSt]	28236	1			T1	45		T2	8		T3	4
auto[0]	auto[TokenCheck0St]	12543	1			T1	28		T2	8		T3	4
auto[0]	auto[TokenCheck1St]	9218	1			T1	21		T2	8		T3	4
auto[0]	auto[TransProgSt]	406209	1			T1	393		T2	16		T3	8
auto[0]	auto[PostTransSt]	12603409	1			T1	7784		T2	2508		T3	647
auto[0]	auto[ScrapSt]	305767	1			T15	237		T25	2		T43	80
auto[0]	auto[EscalateSt]	6025452	1			T1	2920		T2	718		T3	758
auto[0]	auto[InvalidSt]	13531433	1			T1	2190		T2	698		T3	429
auto[1]	auto[ResetSt]	159	1			T25	1		T53	2		T54	8
auto[1]	auto[IdleSt]	154	1			T14	9		T53	4		T54	1
auto[1]	auto[ClkMuxSt]	47	1			T54	3		T55	1		T61	2
auto[1]	auto[CntIncrSt]	46	1			T14	2		T53	1		T54	1
auto[1]	auto[CntProgSt]	728	1			T14	14		T25	18		T53	13
auto[1]	auto[TransCheckSt]	100	1			T14	1		T55	2		T61	7
auto[1]	auto[TokenHashSt]	481	1			T14	10		T25	5		T53	9
auto[1]	auto[FlashRmaSt]	54	1			T14	1		T25	2		T53	1
auto[1]	auto[TokenCheck0St]	20	1			T55	1		T59	1		T221	1
auto[1]	auto[TokenCheck1St]	94	1			T14	6		T53	1		T54	2
auto[1]	auto[TransProgSt]	466	1			T14	17		T25	9		T53	11
auto[1]	auto[PostTransSt]	2747	1			T1	8		T11	10		T4	5
auto[1]	auto[ScrapSt]	40	1			T25	1		T54	3		T55	1
auto[1]	auto[EscalateSt]	1448940	1			T1	1862		T2	294		T3	294
auto[1]	auto[InvalidSt]	7403	1			T1	11		T2	3		T3	3