Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52620 |
1 |
|
|
T1 |
11 |
|
T2 |
359 |
|
T4 |
15 |
auto[1] |
1861 |
1 |
|
|
T2 |
22 |
|
T10 |
9 |
|
T5 |
24 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53692 |
1 |
|
|
T1 |
11 |
|
T2 |
381 |
|
T4 |
15 |
auto[1] |
789 |
1 |
|
|
T17 |
16 |
|
T54 |
8 |
|
T55 |
20 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52472 |
1 |
|
|
T1 |
11 |
|
T2 |
359 |
|
T4 |
15 |
auto[1] |
2009 |
1 |
|
|
T2 |
22 |
|
T5 |
43 |
|
T21 |
11 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52451 |
1 |
|
|
T1 |
11 |
|
T2 |
346 |
|
T4 |
15 |
auto[1] |
2030 |
1 |
|
|
T2 |
35 |
|
T5 |
37 |
|
T21 |
9 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52468 |
1 |
|
|
T1 |
9 |
|
T2 |
355 |
|
T4 |
15 |
auto[1] |
2013 |
1 |
|
|
T1 |
2 |
|
T2 |
26 |
|
T5 |
50 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
49590 |
1 |
|
|
T1 |
7 |
|
T2 |
364 |
|
T4 |
6 |
no_err_inj |
4891 |
1 |
|
|
T1 |
4 |
|
T2 |
17 |
|
T4 |
9 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52672 |
1 |
|
|
T1 |
11 |
|
T2 |
368 |
|
T4 |
15 |
auto[1] |
1809 |
1 |
|
|
T2 |
13 |
|
T10 |
10 |
|
T5 |
21 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53689 |
1 |
|
|
T1 |
11 |
|
T2 |
381 |
|
T4 |
15 |
auto[1] |
792 |
1 |
|
|
T17 |
11 |
|
T54 |
9 |
|
T55 |
20 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38356 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T10 |
57 |
auto[1] |
16125 |
1 |
|
|
T2 |
368 |
|
T4 |
15 |
|
T5 |
185 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52518 |
1 |
|
|
T1 |
11 |
|
T2 |
354 |
|
T4 |
15 |
auto[1] |
1963 |
1 |
|
|
T2 |
27 |
|
T5 |
37 |
|
T21 |
7 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52621 |
1 |
|
|
T1 |
11 |
|
T2 |
352 |
|
T4 |
13 |
auto[1] |
1860 |
1 |
|
|
T2 |
29 |
|
T4 |
2 |
|
T5 |
30 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52461 |
1 |
|
|
T1 |
11 |
|
T2 |
362 |
|
T4 |
14 |
auto[1] |
2020 |
1 |
|
|
T2 |
19 |
|
T4 |
1 |
|
T5 |
30 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52695 |
1 |
|
|
T1 |
11 |
|
T2 |
371 |
|
T4 |
15 |
auto[1] |
1786 |
1 |
|
|
T2 |
10 |
|
T10 |
5 |
|
T5 |
30 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52158 |
1 |
|
|
T1 |
11 |
|
T2 |
381 |
|
T4 |
15 |
auto[1] |
2323 |
1 |
|
|
T5 |
39 |
|
T23 |
5 |
|
T53 |
12 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53741 |
1 |
|
|
T1 |
11 |
|
T2 |
381 |
|
T4 |
15 |
auto[1] |
740 |
1 |
|
|
T17 |
10 |
|
T54 |
12 |
|
T55 |
17 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53717 |
1 |
|
|
T1 |
11 |
|
T2 |
381 |
|
T4 |
15 |
auto[1] |
764 |
1 |
|
|
T17 |
17 |
|
T54 |
16 |
|
T55 |
18 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53686 |
1 |
|
|
T1 |
11 |
|
T2 |
381 |
|
T4 |
15 |
auto[1] |
795 |
1 |
|
|
T17 |
8 |
|
T54 |
7 |
|
T55 |
19 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51713 |
1 |
|
|
T2 |
357 |
|
T10 |
57 |
|
T11 |
55 |
auto[1] |
2768 |
1 |
|
|
T1 |
11 |
|
T2 |
24 |
|
T4 |
15 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50673 |
1 |
|
|
T1 |
11 |
|
T2 |
381 |
|
T4 |
15 |
auto[1] |
3808 |
1 |
|
|
T14 |
73 |
|
T19 |
81 |
|
T43 |
50 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52608 |
1 |
|
|
T1 |
9 |
|
T2 |
357 |
|
T4 |
14 |
auto[1] |
1873 |
1 |
|
|
T1 |
2 |
|
T2 |
24 |
|
T4 |
1 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52576 |
1 |
|
|
T1 |
11 |
|
T2 |
349 |
|
T4 |
13 |
auto[1] |
1905 |
1 |
|
|
T2 |
32 |
|
T4 |
2 |
|
T5 |
37 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52486 |
1 |
|
|
T1 |
8 |
|
T2 |
354 |
|
T4 |
15 |
auto[1] |
1995 |
1 |
|
|
T1 |
3 |
|
T2 |
27 |
|
T5 |
40 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52669 |
1 |
|
|
T1 |
11 |
|
T2 |
367 |
|
T4 |
15 |
auto[1] |
1812 |
1 |
|
|
T2 |
14 |
|
T10 |
5 |
|
T5 |
25 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49028 |
1 |
|
|
T1 |
11 |
|
T2 |
362 |
|
T4 |
15 |
auto[1] |
5453 |
1 |
|
|
T2 |
19 |
|
T10 |
5 |
|
T11 |
55 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50754 |
1 |
|
|
T1 |
11 |
|
T2 |
381 |
|
T4 |
15 |
auto[1] |
3727 |
1 |
|
|
T20 |
69 |
|
T31 |
86 |
|
T16 |
85 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54481 |
1 |
|
|
T1 |
11 |
|
T2 |
381 |
|
T4 |
15 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52638 |
1 |
|
|
T1 |
11 |
|
T2 |
363 |
|
T4 |
15 |
auto[1] |
1843 |
1 |
|
|
T2 |
18 |
|
T10 |
8 |
|
T5 |
15 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52634 |
1 |
|
|
T1 |
11 |
|
T2 |
366 |
|
T4 |
15 |
auto[1] |
1847 |
1 |
|
|
T2 |
15 |
|
T10 |
10 |
|
T5 |
31 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52708 |
1 |
|
|
T1 |
11 |
|
T2 |
369 |
|
T4 |
15 |
auto[1] |
1773 |
1 |
|
|
T2 |
12 |
|
T10 |
5 |
|
T5 |
15 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
48213 |
1 |
|
|
T2 |
357 |
|
T10 |
57 |
|
T11 |
55 |
auto[0] |
no_err_inj |
3500 |
1 |
|
|
T5 |
61 |
|
T18 |
16 |
|
T51 |
1 |
auto[1] |
err_inj |
1377 |
1 |
|
|
T1 |
7 |
|
T2 |
7 |
|
T4 |
6 |
auto[1] |
no_err_inj |
1391 |
1 |
|
|
T1 |
4 |
|
T2 |
17 |
|
T4 |
9 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49961 |
1 |
|
|
T2 |
328 |
|
T10 |
57 |
|
T11 |
55 |
auto[0] |
auto[1] |
1752 |
1 |
|
|
T2 |
29 |
|
T5 |
34 |
|
T21 |
17 |
auto[1] |
auto[0] |
2615 |
1 |
|
|
T1 |
11 |
|
T2 |
21 |
|
T4 |
13 |
auto[1] |
auto[1] |
153 |
1 |
|
|
T2 |
3 |
|
T4 |
2 |
|
T5 |
3 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
50001 |
1 |
|
|
T2 |
328 |
|
T10 |
57 |
|
T11 |
55 |
auto[0] |
auto[1] |
1712 |
1 |
|
|
T2 |
29 |
|
T5 |
29 |
|
T21 |
9 |
auto[1] |
auto[0] |
2620 |
1 |
|
|
T1 |
11 |
|
T2 |
24 |
|
T4 |
13 |
auto[1] |
auto[1] |
148 |
1 |
|
|
T4 |
2 |
|
T5 |
1 |
|
T18 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49875 |
1 |
|
|
T2 |
331 |
|
T10 |
57 |
|
T11 |
55 |
auto[0] |
auto[1] |
1838 |
1 |
|
|
T2 |
26 |
|
T5 |
37 |
|
T21 |
5 |
auto[1] |
auto[0] |
2611 |
1 |
|
|
T1 |
8 |
|
T2 |
23 |
|
T4 |
15 |
auto[1] |
auto[1] |
157 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T5 |
3 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49850 |
1 |
|
|
T2 |
323 |
|
T10 |
57 |
|
T11 |
55 |
auto[0] |
auto[1] |
1863 |
1 |
|
|
T2 |
34 |
|
T5 |
37 |
|
T21 |
9 |
auto[1] |
auto[0] |
2601 |
1 |
|
|
T1 |
11 |
|
T2 |
23 |
|
T4 |
15 |
auto[1] |
auto[1] |
167 |
1 |
|
|
T2 |
1 |
|
T18 |
1 |
|
T34 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49831 |
1 |
|
|
T2 |
332 |
|
T10 |
57 |
|
T11 |
55 |
auto[0] |
auto[1] |
1882 |
1 |
|
|
T2 |
25 |
|
T5 |
50 |
|
T21 |
5 |
auto[1] |
auto[0] |
2637 |
1 |
|
|
T1 |
9 |
|
T2 |
23 |
|
T4 |
15 |
auto[1] |
auto[1] |
131 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T80 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49851 |
1 |
|
|
T2 |
335 |
|
T10 |
57 |
|
T11 |
55 |
auto[0] |
auto[1] |
1862 |
1 |
|
|
T2 |
22 |
|
T5 |
37 |
|
T21 |
11 |
auto[1] |
auto[0] |
2621 |
1 |
|
|
T1 |
11 |
|
T2 |
24 |
|
T4 |
15 |
auto[1] |
auto[1] |
147 |
1 |
|
|
T5 |
6 |
|
T34 |
1 |
|
T80 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37204 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T10 |
48 |
auto[0] |
auto[1] |
1152 |
1 |
|
|
T10 |
9 |
|
T5 |
18 |
|
T18 |
37 |
auto[1] |
auto[0] |
15416 |
1 |
|
|
T2 |
346 |
|
T4 |
15 |
|
T5 |
179 |
auto[1] |
auto[1] |
709 |
1 |
|
|
T2 |
22 |
|
T5 |
6 |
|
T56 |
12 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37243 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T10 |
47 |
auto[0] |
auto[1] |
1113 |
1 |
|
|
T10 |
10 |
|
T5 |
17 |
|
T18 |
29 |
auto[1] |
auto[0] |
15429 |
1 |
|
|
T2 |
355 |
|
T4 |
15 |
|
T5 |
181 |
auto[1] |
auto[1] |
696 |
1 |
|
|
T2 |
13 |
|
T5 |
4 |
|
T56 |
13 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37015 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T10 |
57 |
auto[0] |
auto[1] |
1341 |
1 |
|
|
T5 |
32 |
|
T53 |
12 |
|
T56 |
4 |
auto[1] |
auto[0] |
15143 |
1 |
|
|
T2 |
368 |
|
T4 |
15 |
|
T5 |
178 |
auto[1] |
auto[1] |
982 |
1 |
|
|
T5 |
7 |
|
T23 |
5 |
|
T49 |
28 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37236 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T10 |
52 |
auto[0] |
auto[1] |
1120 |
1 |
|
|
T10 |
5 |
|
T5 |
26 |
|
T18 |
34 |
auto[1] |
auto[0] |
15459 |
1 |
|
|
T2 |
358 |
|
T4 |
15 |
|
T5 |
181 |
auto[1] |
auto[1] |
666 |
1 |
|
|
T2 |
10 |
|
T5 |
4 |
|
T56 |
9 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33632 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T10 |
52 |
auto[0] |
auto[1] |
4724 |
1 |
|
|
T10 |
5 |
|
T11 |
55 |
|
T5 |
10 |
auto[1] |
auto[0] |
15396 |
1 |
|
|
T2 |
349 |
|
T4 |
15 |
|
T5 |
181 |
auto[1] |
auto[1] |
729 |
1 |
|
|
T2 |
19 |
|
T5 |
4 |
|
T56 |
14 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37259 |
1 |
|
|
T1 |
11 |
|
T2 |
12 |
|
T10 |
57 |
auto[0] |
auto[1] |
1097 |
1 |
|
|
T2 |
1 |
|
T5 |
23 |
|
T18 |
18 |
auto[1] |
auto[0] |
15317 |
1 |
|
|
T2 |
337 |
|
T4 |
13 |
|
T5 |
171 |
auto[1] |
auto[1] |
808 |
1 |
|
|
T2 |
31 |
|
T4 |
2 |
|
T5 |
14 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37275 |
1 |
|
|
T1 |
9 |
|
T2 |
12 |
|
T10 |
57 |
auto[0] |
auto[1] |
1081 |
1 |
|
|
T1 |
2 |
|
T2 |
1 |
|
T5 |
31 |
auto[1] |
auto[0] |
15333 |
1 |
|
|
T2 |
345 |
|
T4 |
14 |
|
T5 |
170 |
auto[1] |
auto[1] |
792 |
1 |
|
|
T2 |
23 |
|
T4 |
1 |
|
T5 |
15 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37299 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T10 |
57 |
auto[0] |
auto[1] |
1057 |
1 |
|
|
T5 |
13 |
|
T18 |
13 |
|
T56 |
8 |
auto[1] |
auto[0] |
15322 |
1 |
|
|
T2 |
339 |
|
T4 |
13 |
|
T5 |
168 |
auto[1] |
auto[1] |
803 |
1 |
|
|
T2 |
29 |
|
T4 |
2 |
|
T5 |
17 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37225 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T10 |
57 |
auto[0] |
auto[1] |
1131 |
1 |
|
|
T5 |
24 |
|
T15 |
1 |
|
T18 |
16 |
auto[1] |
auto[0] |
15293 |
1 |
|
|
T2 |
341 |
|
T4 |
15 |
|
T5 |
172 |
auto[1] |
auto[1] |
832 |
1 |
|
|
T2 |
27 |
|
T5 |
13 |
|
T21 |
7 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37183 |
1 |
|
|
T1 |
11 |
|
T2 |
12 |
|
T10 |
57 |
auto[0] |
auto[1] |
1173 |
1 |
|
|
T2 |
1 |
|
T5 |
27 |
|
T18 |
14 |
auto[1] |
auto[0] |
15268 |
1 |
|
|
T2 |
334 |
|
T4 |
15 |
|
T5 |
175 |
auto[1] |
auto[1] |
857 |
1 |
|
|
T2 |
34 |
|
T5 |
10 |
|
T21 |
9 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37196 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T10 |
57 |
auto[0] |
auto[1] |
1160 |
1 |
|
|
T5 |
25 |
|
T18 |
17 |
|
T34 |
1 |
auto[1] |
auto[0] |
15276 |
1 |
|
|
T2 |
346 |
|
T4 |
15 |
|
T5 |
167 |
auto[1] |
auto[1] |
849 |
1 |
|
|
T2 |
22 |
|
T5 |
18 |
|
T21 |
11 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37268 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T10 |
52 |
auto[0] |
auto[1] |
1088 |
1 |
|
|
T10 |
5 |
|
T5 |
13 |
|
T18 |
28 |
auto[1] |
auto[0] |
15440 |
1 |
|
|
T2 |
356 |
|
T4 |
15 |
|
T5 |
183 |
auto[1] |
auto[1] |
685 |
1 |
|
|
T2 |
12 |
|
T5 |
2 |
|
T56 |
6 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37199 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T10 |
47 |
auto[0] |
auto[1] |
1157 |
1 |
|
|
T10 |
10 |
|
T5 |
29 |
|
T18 |
26 |
auto[1] |
auto[0] |
15435 |
1 |
|
|
T2 |
353 |
|
T4 |
15 |
|
T5 |
183 |
auto[1] |
auto[1] |
690 |
1 |
|
|
T2 |
15 |
|
T5 |
2 |
|
T56 |
11 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36707 |
1 |
|
|
T10 |
57 |
|
T11 |
55 |
|
T5 |
449 |
auto[0] |
auto[1] |
1649 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T5 |
11 |
auto[1] |
auto[0] |
15006 |
1 |
|
|
T2 |
357 |
|
T5 |
159 |
|
T21 |
75 |
auto[1] |
auto[1] |
1119 |
1 |
|
|
T2 |
11 |
|
T4 |
15 |
|
T5 |
26 |