Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104602411

1

T1

5541

T2

170233

T3

1909

auto[1]

1425154

1

T1

99

T2

11480

T4

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104596687

1

T1

5343

T2

170400

T3

1909

auto[1]

1430878

1

T1

297

T2

9812

T4

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7613300	1			T1	1079		T2	115308		T3	107
auto[IdleSt]	21967284	1			T1	1219		T2	387832		T3	1802
auto[ClkMuxSt]	35706	1			T1	4		T2	140		T4	9
auto[CntIncrSt]	35409	1			T1	4		T2	140		T4	9
auto[CntProgSt]	1300201	1			T1	8		T2	2336		T4	2254
auto[TransCheckSt]	27532	1			T1	4		T2	103		T4	9
auto[TokenHashSt]	41512718	1			T1	77		T2	43879		T4	222
auto[FlashRmaSt]	28698	1			T1	29		T2	114		T4	9
auto[TokenCheck0St]	12804	1			T1	4		T2	40		T4	9
auto[TokenCheck1St]	9413	1			T1	4		T2	28		T4	9
auto[TransProgSt]	305143	1			T1	8		T2	532		T4	2303
auto[PostTransSt]	13124353	1			T1	1140		T2	284589		T4	26927
auto[ScrapSt]	244555	1			T5	33		T14	9		T35	25
auto[EscalateSt]	7094284	1			T1	1131		T2	196135		T4	7984
auto[InvalidSt]	12714210	1			T1	929		T2	682613		T4	10427

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1955	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12714210	1			T1	929		T2	682613		T4	10427
EscalateSt	7094284	1			T1	1131		T2	196135		T4	7984
ScrapSt	244555	1			T5	33		T14	9		T35	25
PostTransSt	13124353	1			T1	1140		T2	284589		T4	26927
TransProgSt	305143	1			T1	8		T2	532		T4	2303
TokenCheck1St	9413	1			T1	4		T2	28		T4	9
TokenCheck0St	12804	1			T1	4		T2	40		T4	9
FlashRmaSt	28698	1			T1	29		T2	114		T4	9
TokenHashSt	41512718	1			T1	77		T2	43879		T4	222
TransCheckSt	27532	1			T1	4		T2	103		T4	9
CntProgSt	1300201	1			T1	8		T2	2336		T4	2254
CntIncrSt	35409	1			T1	4		T2	140		T4	9
ClkMuxSt	35706	1			T1	4		T2	140		T4	9
IdleSt	21967284	1			T1	1219		T2	387832		T3	1802
ResetSt	7613300	1			T1	1079		T2	115308		T3	107
arcs[ResetSt=>IdleSt]	54722	1			T1	12		T2	370		T3	1
arcs[IdleSt=>ScrapSt]	309	1			T5	3		T14	3		T35	2
arcs[IdleSt=>ClkMuxSt]	35476	1			T1	4		T2	140		T4	9
arcs[ClkMuxSt=>CntIncrSt]	35409	1			T1	4		T2	140		T4	9
arcs[CntIncrSt=>PostTransSt]	1850	1			T2	15		T10	10		T5	31
arcs[CntIncrSt=>CntProgSt]	33496	1			T1	4		T2	125		T4	9
arcs[CntProgSt=>PostTransSt]	4953	1			T2	22		T10	9		T5	63
arcs[CntProgSt=>TransCheckSt]	27532	1			T1	4		T2	103		T4	9
arcs[TransCheckSt=>PostTransSt]	3565	1			T2	12		T10	5		T5	15
arcs[TransCheckSt=>TokenHashSt]	23811	1			T1	4		T2	91		T4	9
arcs[TokenHashSt=>PostTransSt]	10128	1			T2	51		T10	18		T11	55
arcs[TokenHashSt=>FlashRmaSt]	12893	1			T1	4		T2	40		T4	9
arcs[FlashRmaSt=>TokenCheck0St]	12804	1			T1	4		T2	40		T4	9
arcs[TokenCheck0St=>PostTransSt]	3352	1			T2	12		T10	10		T5	18
arcs[TokenCheck0St=>TokenCheck1St]	9413	1			T1	4		T2	28		T4	9
arcs[TokenCheck1St=>PostTransSt]	673	1			T5	3		T20	8		T17	1
arcs[TransProgSt=>PostTransSt]	7881	1			T1	4		T2	28		T4	9
arcs[IdleSt=>EscalateSt]	155	1			T14	4		T19	9		T44	8
arcs[ClkMuxSt=>EscalateSt]	67	1			T14	1		T19	1		T43	1
arcs[CntIncrSt=>EscalateSt]	63	1			T14	1		T19	2		T43	1
arcs[CntProgSt=>EscalateSt]	1011	1			T14	18		T19	24		T43	11
arcs[TransCheckSt=>EscalateSt]	156	1			T14	1		T43	2		T44	7
arcs[TokenHashSt=>EscalateSt]	790	1			T14	13		T19	15		T43	12
arcs[FlashRmaSt=>EscalateSt]	89	1			T14	5		T19	1		T44	3
arcs[TokenCheck0St=>EscalateSt]	39	1			T19	1		T44	1		T48	2
arcs[TokenCheck1St=>EscalateSt]	160	1			T14	2		T19	2		T43	4
arcs[TransProgSt=>EscalateSt]	699	1			T14	13		T19	21		T43	13
arcs[PostTransSt=>EscalateSt]	5233	1			T2	22		T10	9		T5	63
arcs[InvalidSt=>EscalateSt]	14432	1			T1	4		T2	195		T4	5

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7613115	1			T1	1079		T2	115308		T3	107
auto[0]	auto[IdleSt]	21967171	1			T1	1219		T2	387832		T3	1802
auto[0]	auto[ClkMuxSt]	35665	1			T1	4		T2	140		T4	9
auto[0]	auto[CntIncrSt]	35370	1			T1	4		T2	140		T4	9
auto[0]	auto[CntProgSt]	1299526	1			T1	8		T2	2336		T4	2254
auto[0]	auto[TransCheckSt]	27435	1			T1	4		T2	103		T4	9
auto[0]	auto[TokenHashSt]	41512198	1			T1	77		T2	43879		T4	222
auto[0]	auto[FlashRmaSt]	28646	1			T1	29		T2	114		T4	9
auto[0]	auto[TokenCheck0St]	12775	1			T1	4		T2	40		T4	9
auto[0]	auto[TokenCheck1St]	9297	1			T1	4		T2	28		T4	9
auto[0]	auto[TransProgSt]	304648	1			T1	8		T2	532		T4	2303
auto[0]	auto[PostTransSt]	13121702	1			T1	1140		T2	284578		T4	26927
auto[0]	auto[ScrapSt]	244508	1			T5	33		T14	6		T35	25
auto[0]	auto[EscalateSt]	5681378	1			T1	1033		T2	184772		T4	7788
auto[0]	auto[InvalidSt]	12707022	1			T1	928		T2	682507		T4	10425
auto[1]	auto[ResetSt]	185	1			T14	2		T19	3		T43	2
auto[1]	auto[IdleSt]	113	1			T14	4		T19	6		T44	7
auto[1]	auto[ClkMuxSt]	41	1			T19	1		T210	1		T88	2
auto[1]	auto[CntIncrSt]	39	1			T19	1		T43	1		T44	1
auto[1]	auto[CntProgSt]	675	1			T14	10		T19	15		T43	7
auto[1]	auto[TransCheckSt]	97	1			T14	1		T43	1		T44	3
auto[1]	auto[TokenHashSt]	520	1			T14	9		T19	11		T43	8
auto[1]	auto[FlashRmaSt]	52	1			T14	3		T44	1		T48	1
auto[1]	auto[TokenCheck0St]	29	1			T19	1		T44	1		T48	1
auto[1]	auto[TokenCheck1St]	116	1			T14	2		T19	2		T43	2
auto[1]	auto[TransProgSt]	495	1			T14	8		T19	15		T43	10
auto[1]	auto[PostTransSt]	2651	1			T2	11		T10	3		T5	33
auto[1]	auto[ScrapSt]	47	1			T14	3		T43	2		T44	1
auto[1]	auto[EscalateSt]	1412906	1			T1	98		T2	11363		T4	196
auto[1]	auto[InvalidSt]	7188	1			T1	1		T2	106		T4	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7613134	1			T1	1079		T2	115308		T3	107
auto[0]	auto[IdleSt]	21967187	1			T1	1219		T2	387832		T3	1802
auto[0]	auto[ClkMuxSt]	35663	1			T1	4		T2	140		T4	9
auto[0]	auto[CntIncrSt]	35365	1			T1	4		T2	140		T4	9
auto[0]	auto[CntProgSt]	1299487	1			T1	8		T2	2336		T4	2254
auto[0]	auto[TransCheckSt]	27431	1			T1	4		T2	103		T4	9
auto[0]	auto[TokenHashSt]	41512181	1			T1	77		T2	43879		T4	222
auto[0]	auto[FlashRmaSt]	28637	1			T1	29		T2	114		T4	9
auto[0]	auto[TokenCheck0St]	12778	1			T1	4		T2	40		T4	9
auto[0]	auto[TokenCheck1St]	9311	1			T1	4		T2	28		T4	9
auto[0]	auto[TransProgSt]	304685	1			T1	8		T2	532		T4	2303
auto[0]	auto[PostTransSt]	13121681	1			T1	1140		T2	284578		T4	26927
auto[0]	auto[ScrapSt]	244507	1			T5	33		T14	6		T35	25
auto[0]	auto[EscalateSt]	5675719	1			T1	837		T2	186423		T4	7690
auto[0]	auto[InvalidSt]	12706966	1			T1	926		T2	682524		T4	10424
auto[1]	auto[ResetSt]	166	1			T14	6		T19	3		T44	5
auto[1]	auto[IdleSt]	97	1			T14	1		T19	8		T44	4
auto[1]	auto[ClkMuxSt]	43	1			T14	1		T43	1		T210	2
auto[1]	auto[CntIncrSt]	44	1			T14	1		T19	1		T44	1
auto[1]	auto[CntProgSt]	714	1			T14	14		T19	17		T43	7
auto[1]	auto[TransCheckSt]	101	1			T43	1		T44	4		T48	1
auto[1]	auto[TokenHashSt]	537	1			T14	7		T19	9		T43	8
auto[1]	auto[FlashRmaSt]	61	1			T14	5		T19	1		T44	2
auto[1]	auto[TokenCheck0St]	26	1			T19	1		T44	1		T48	1
auto[1]	auto[TokenCheck1St]	102	1			T14	1		T19	1		T43	3
auto[1]	auto[TransProgSt]	458	1			T14	11		T19	13		T43	7
auto[1]	auto[PostTransSt]	2672	1			T2	11		T10	6		T5	30
auto[1]	auto[ScrapSt]	48	1			T14	3		T43	3		T48	1
auto[1]	auto[EscalateSt]	1418565	1			T1	294		T2	9712		T4	294
auto[1]	auto[InvalidSt]	7244	1			T1	3		T2	89		T4	3