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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.18 97.82 95.84 93.31 100.00 98.52 98.51 96.29


Total test records in report: 1000
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T811 /workspace/coverage/default/36.lc_ctrl_prog_failure.3848446037 May 12 01:32:33 PM PDT 24 May 12 01:32:38 PM PDT 24 130132167 ps
T812 /workspace/coverage/default/34.lc_ctrl_state_post_trans.2186657611 May 12 01:32:22 PM PDT 24 May 12 01:32:26 PM PDT 24 189796215 ps
T813 /workspace/coverage/default/6.lc_ctrl_security_escalation.351447890 May 12 01:31:00 PM PDT 24 May 12 01:31:13 PM PDT 24 1183285898 ps
T814 /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3173564915 May 12 01:30:38 PM PDT 24 May 12 01:30:39 PM PDT 24 14510619 ps
T815 /workspace/coverage/default/4.lc_ctrl_state_failure.3964882620 May 12 01:30:44 PM PDT 24 May 12 01:31:16 PM PDT 24 1219479994 ps
T816 /workspace/coverage/default/9.lc_ctrl_jtag_errors.2163651346 May 12 01:31:07 PM PDT 24 May 12 01:32:16 PM PDT 24 8692810183 ps
T817 /workspace/coverage/default/16.lc_ctrl_state_post_trans.3712811850 May 12 01:31:35 PM PDT 24 May 12 01:31:46 PM PDT 24 254034512 ps
T818 /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3954668281 May 12 01:32:50 PM PDT 24 May 12 01:33:02 PM PDT 24 2130250127 ps
T819 /workspace/coverage/default/2.lc_ctrl_errors.964455542 May 12 01:30:36 PM PDT 24 May 12 01:30:46 PM PDT 24 596844139 ps
T820 /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2557382753 May 12 01:31:04 PM PDT 24 May 12 01:31:40 PM PDT 24 4742214875 ps
T821 /workspace/coverage/default/20.lc_ctrl_stress_all.4235688977 May 12 01:31:49 PM PDT 24 May 12 01:32:54 PM PDT 24 8781990707 ps
T822 /workspace/coverage/default/13.lc_ctrl_alert_test.1300259524 May 12 01:31:29 PM PDT 24 May 12 01:31:30 PM PDT 24 30607979 ps
T823 /workspace/coverage/default/22.lc_ctrl_stress_all.324876219 May 12 01:31:55 PM PDT 24 May 12 01:36:47 PM PDT 24 18915393405 ps
T824 /workspace/coverage/default/24.lc_ctrl_alert_test.3528451235 May 12 01:32:02 PM PDT 24 May 12 01:32:04 PM PDT 24 58589654 ps
T825 /workspace/coverage/default/5.lc_ctrl_state_failure.1115454244 May 12 01:30:56 PM PDT 24 May 12 01:31:16 PM PDT 24 439682202 ps
T826 /workspace/coverage/default/37.lc_ctrl_smoke.2423665586 May 12 01:32:29 PM PDT 24 May 12 01:32:32 PM PDT 24 18845674 ps
T827 /workspace/coverage/default/2.lc_ctrl_jtag_priority.3277732272 May 12 01:30:40 PM PDT 24 May 12 01:30:44 PM PDT 24 130845490 ps
T828 /workspace/coverage/default/42.lc_ctrl_state_post_trans.4145188796 May 12 01:32:45 PM PDT 24 May 12 01:32:53 PM PDT 24 82824313 ps
T829 /workspace/coverage/default/17.lc_ctrl_stress_all.2156906086 May 12 01:31:42 PM PDT 24 May 12 01:32:15 PM PDT 24 7420558040 ps
T830 /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.721724355 May 12 01:30:27 PM PDT 24 May 12 01:32:25 PM PDT 24 15770962642 ps
T831 /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1704534755 May 12 01:31:35 PM PDT 24 May 12 01:31:48 PM PDT 24 491409049 ps
T832 /workspace/coverage/default/47.lc_ctrl_security_escalation.3938765657 May 12 01:32:53 PM PDT 24 May 12 01:33:05 PM PDT 24 1099189493 ps
T833 /workspace/coverage/default/23.lc_ctrl_state_post_trans.2001489084 May 12 01:31:54 PM PDT 24 May 12 01:32:00 PM PDT 24 387440379 ps
T834 /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3896836788 May 12 01:31:42 PM PDT 24 May 12 01:31:47 PM PDT 24 187979810 ps
T835 /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2192063485 May 12 01:30:37 PM PDT 24 May 12 01:30:39 PM PDT 24 32529369 ps
T836 /workspace/coverage/default/12.lc_ctrl_sec_mubi.3949690000 May 12 01:31:20 PM PDT 24 May 12 01:31:38 PM PDT 24 1602751299 ps
T837 /workspace/coverage/default/44.lc_ctrl_state_failure.3384635298 May 12 01:32:49 PM PDT 24 May 12 01:33:06 PM PDT 24 175632955 ps
T838 /workspace/coverage/default/12.lc_ctrl_jtag_access.3535655249 May 12 01:31:26 PM PDT 24 May 12 01:31:29 PM PDT 24 167224669 ps
T839 /workspace/coverage/default/17.lc_ctrl_state_post_trans.2013111211 May 12 01:31:44 PM PDT 24 May 12 01:31:48 PM PDT 24 68621457 ps
T840 /workspace/coverage/default/26.lc_ctrl_alert_test.3626458536 May 12 01:32:06 PM PDT 24 May 12 01:32:08 PM PDT 24 71450638 ps
T841 /workspace/coverage/default/40.lc_ctrl_state_post_trans.547204373 May 12 01:32:41 PM PDT 24 May 12 01:32:49 PM PDT 24 560802703 ps
T842 /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1318107826 May 12 01:32:28 PM PDT 24 May 12 01:32:30 PM PDT 24 46531526 ps
T843 /workspace/coverage/default/7.lc_ctrl_prog_failure.3604326243 May 12 01:31:02 PM PDT 24 May 12 01:31:07 PM PDT 24 210233938 ps
T844 /workspace/coverage/default/25.lc_ctrl_sec_token_digest.567374833 May 12 01:32:07 PM PDT 24 May 12 01:32:18 PM PDT 24 213288985 ps
T845 /workspace/coverage/default/12.lc_ctrl_state_failure.431113135 May 12 01:31:23 PM PDT 24 May 12 01:31:55 PM PDT 24 1505238122 ps
T846 /workspace/coverage/default/20.lc_ctrl_sec_mubi.2535593410 May 12 01:31:51 PM PDT 24 May 12 01:32:06 PM PDT 24 3714988582 ps
T847 /workspace/coverage/default/26.lc_ctrl_jtag_access.1407059513 May 12 01:32:05 PM PDT 24 May 12 01:32:10 PM PDT 24 1087885477 ps
T848 /workspace/coverage/default/49.lc_ctrl_sec_mubi.1349071379 May 12 01:33:03 PM PDT 24 May 12 01:33:18 PM PDT 24 265432215 ps
T849 /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2838808009 May 12 01:31:29 PM PDT 24 May 12 01:31:41 PM PDT 24 329514110 ps
T850 /workspace/coverage/default/7.lc_ctrl_jtag_priority.80150611 May 12 01:31:02 PM PDT 24 May 12 01:31:09 PM PDT 24 575113994 ps
T97 /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.1734705211 May 12 01:32:34 PM PDT 24 May 12 01:39:23 PM PDT 24 54543505052 ps
T851 /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1631706476 May 12 01:32:29 PM PDT 24 May 12 01:32:39 PM PDT 24 5139846713 ps
T852 /workspace/coverage/default/27.lc_ctrl_state_post_trans.1229712055 May 12 01:32:09 PM PDT 24 May 12 01:32:19 PM PDT 24 179402463 ps
T853 /workspace/coverage/default/45.lc_ctrl_jtag_access.2999267119 May 12 01:32:50 PM PDT 24 May 12 01:32:57 PM PDT 24 552392134 ps
T854 /workspace/coverage/default/8.lc_ctrl_alert_test.3966172812 May 12 01:31:03 PM PDT 24 May 12 01:31:05 PM PDT 24 18675864 ps
T855 /workspace/coverage/default/12.lc_ctrl_stress_all.832170693 May 12 01:31:22 PM PDT 24 May 12 01:35:43 PM PDT 24 42547167734 ps
T856 /workspace/coverage/default/26.lc_ctrl_state_post_trans.3968758834 May 12 01:32:06 PM PDT 24 May 12 01:32:14 PM PDT 24 102436495 ps
T857 /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3157056058 May 12 01:30:32 PM PDT 24 May 12 01:30:48 PM PDT 24 1390678100 ps
T858 /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3014643786 May 12 01:31:20 PM PDT 24 May 12 01:31:26 PM PDT 24 236832349 ps
T859 /workspace/coverage/default/40.lc_ctrl_stress_all.3237964939 May 12 01:32:39 PM PDT 24 May 12 01:35:44 PM PDT 24 4916529633 ps
T860 /workspace/coverage/default/20.lc_ctrl_state_post_trans.2993499894 May 12 01:31:51 PM PDT 24 May 12 01:31:58 PM PDT 24 166865198 ps
T861 /workspace/coverage/default/20.lc_ctrl_smoke.3908387963 May 12 01:31:46 PM PDT 24 May 12 01:31:48 PM PDT 24 44376271 ps
T862 /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.323335188 May 12 01:31:26 PM PDT 24 May 12 01:31:27 PM PDT 24 12615427 ps
T863 /workspace/coverage/default/9.lc_ctrl_state_post_trans.1894061123 May 12 01:31:08 PM PDT 24 May 12 01:31:14 PM PDT 24 59055531 ps
T864 /workspace/coverage/default/10.lc_ctrl_state_post_trans.477935297 May 12 01:31:13 PM PDT 24 May 12 01:31:21 PM PDT 24 486163526 ps
T865 /workspace/coverage/default/18.lc_ctrl_smoke.3620520826 May 12 01:31:43 PM PDT 24 May 12 01:31:49 PM PDT 24 393202042 ps
T866 /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.860265047 May 12 01:31:06 PM PDT 24 May 12 01:32:20 PM PDT 24 8530057129 ps
T867 /workspace/coverage/default/21.lc_ctrl_jtag_access.3945535085 May 12 01:31:55 PM PDT 24 May 12 01:32:03 PM PDT 24 1775651620 ps
T868 /workspace/coverage/default/49.lc_ctrl_sec_token_digest.863661619 May 12 01:32:59 PM PDT 24 May 12 01:33:22 PM PDT 24 726132325 ps
T869 /workspace/coverage/default/14.lc_ctrl_errors.3379333756 May 12 01:31:26 PM PDT 24 May 12 01:31:40 PM PDT 24 1218239044 ps
T870 /workspace/coverage/default/49.lc_ctrl_security_escalation.384695027 May 12 01:33:00 PM PDT 24 May 12 01:33:10 PM PDT 24 1037715571 ps
T871 /workspace/coverage/default/20.lc_ctrl_state_failure.3652130488 May 12 01:31:52 PM PDT 24 May 12 01:32:24 PM PDT 24 1027282215 ps
T872 /workspace/coverage/default/30.lc_ctrl_errors.897428009 May 12 01:32:15 PM PDT 24 May 12 01:32:26 PM PDT 24 606061042 ps
T873 /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1816987651 May 12 01:31:10 PM PDT 24 May 12 01:31:33 PM PDT 24 2268750385 ps
T874 /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3195671398 May 12 01:30:55 PM PDT 24 May 12 01:31:08 PM PDT 24 1442406782 ps
T105 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3959951037 May 12 01:23:50 PM PDT 24 May 12 01:23:52 PM PDT 24 37408886 ps
T106 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3345631148 May 12 01:24:05 PM PDT 24 May 12 01:24:11 PM PDT 24 2698923714 ps
T94 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.737102146 May 12 01:24:10 PM PDT 24 May 12 01:24:15 PM PDT 24 109852959 ps
T95 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3219922398 May 12 01:24:09 PM PDT 24 May 12 01:24:15 PM PDT 24 159329800 ps
T107 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.888373091 May 12 01:23:58 PM PDT 24 May 12 01:24:13 PM PDT 24 1887233434 ps
T101 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.760178203 May 12 01:23:51 PM PDT 24 May 12 01:23:53 PM PDT 24 73094800 ps
T98 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4020376751 May 12 01:24:05 PM PDT 24 May 12 01:24:09 PM PDT 24 531342311 ps
T125 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3879721640 May 12 01:23:57 PM PDT 24 May 12 01:24:00 PM PDT 24 26181195 ps
T96 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2047213615 May 12 01:23:50 PM PDT 24 May 12 01:23:55 PM PDT 24 78088258 ps
T875 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2354563142 May 12 01:23:54 PM PDT 24 May 12 01:23:56 PM PDT 24 119564071 ps
T102 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3304991431 May 12 01:23:56 PM PDT 24 May 12 01:23:58 PM PDT 24 16730817 ps
T195 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3673479219 May 12 01:24:04 PM PDT 24 May 12 01:24:06 PM PDT 24 55602092 ps
T180 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2128627664 May 12 01:24:13 PM PDT 24 May 12 01:24:14 PM PDT 24 13906598 ps
T137 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1892549859 May 12 01:23:57 PM PDT 24 May 12 01:23:58 PM PDT 24 39132471 ps
T129 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4001260363 May 12 01:23:52 PM PDT 24 May 12 01:24:07 PM PDT 24 2029343895 ps
T114 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2101522666 May 12 01:24:08 PM PDT 24 May 12 01:24:10 PM PDT 24 110987168 ps
T876 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1483089515 May 12 01:23:52 PM PDT 24 May 12 01:23:58 PM PDT 24 2254827859 ps
T877 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3216479151 May 12 01:23:58 PM PDT 24 May 12 01:24:00 PM PDT 24 58840024 ps
T128 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.282351322 May 12 01:23:47 PM PDT 24 May 12 01:23:54 PM PDT 24 330632512 ps
T103 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.462310841 May 12 01:24:15 PM PDT 24 May 12 01:24:17 PM PDT 24 79739587 ps
T878 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1083434614 May 12 01:23:55 PM PDT 24 May 12 01:23:57 PM PDT 24 93021298 ps
T109 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3433698585 May 12 01:24:04 PM PDT 24 May 12 01:24:10 PM PDT 24 1049589993 ps
T99 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3688746911 May 12 01:24:04 PM PDT 24 May 12 01:24:08 PM PDT 24 72135994 ps
T196 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.545317582 May 12 01:24:18 PM PDT 24 May 12 01:24:19 PM PDT 24 49246308 ps
T110 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.764158942 May 12 01:24:09 PM PDT 24 May 12 01:24:12 PM PDT 24 202115221 ps
T181 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3500361310 May 12 01:24:03 PM PDT 24 May 12 01:24:05 PM PDT 24 16533192 ps
T126 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3685765593 May 12 01:23:58 PM PDT 24 May 12 01:24:11 PM PDT 24 570716271 ps
T127 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2904088492 May 12 01:23:51 PM PDT 24 May 12 01:23:54 PM PDT 24 104613676 ps
T100 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3419133797 May 12 01:23:58 PM PDT 24 May 12 01:24:01 PM PDT 24 107169362 ps
T118 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3580440747 May 12 01:23:54 PM PDT 24 May 12 01:23:57 PM PDT 24 48304893 ps
T879 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1718745458 May 12 01:23:53 PM PDT 24 May 12 01:23:56 PM PDT 24 254948367 ps
T880 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3359811674 May 12 01:24:04 PM PDT 24 May 12 01:24:06 PM PDT 24 17731987 ps
T881 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.639845303 May 12 01:23:52 PM PDT 24 May 12 01:23:57 PM PDT 24 486344876 ps
T104 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3428951065 May 12 01:24:08 PM PDT 24 May 12 01:24:11 PM PDT 24 116978813 ps
T882 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3232432285 May 12 01:23:56 PM PDT 24 May 12 01:23:57 PM PDT 24 83146064 ps
T182 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2979095158 May 12 01:24:16 PM PDT 24 May 12 01:24:18 PM PDT 24 38584944 ps
T883 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2757707927 May 12 01:23:57 PM PDT 24 May 12 01:23:59 PM PDT 24 84059655 ps
T884 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1700646092 May 12 01:24:15 PM PDT 24 May 12 01:24:16 PM PDT 24 38001176 ps
T885 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.199208804 May 12 01:23:58 PM PDT 24 May 12 01:23:59 PM PDT 24 17890791 ps
T886 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.162388702 May 12 01:24:17 PM PDT 24 May 12 01:24:22 PM PDT 24 401423583 ps
T887 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3081633316 May 12 01:24:07 PM PDT 24 May 12 01:24:10 PM PDT 24 422153393 ps
T197 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2086625792 May 12 01:24:18 PM PDT 24 May 12 01:24:20 PM PDT 24 453927220 ps
T888 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2956435048 May 12 01:24:15 PM PDT 24 May 12 01:24:19 PM PDT 24 84659613 ps
T115 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.621270276 May 12 01:23:55 PM PDT 24 May 12 01:23:58 PM PDT 24 52545763 ps
T183 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3765500447 May 12 01:23:54 PM PDT 24 May 12 01:23:55 PM PDT 24 36184272 ps
T889 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2598879944 May 12 01:24:09 PM PDT 24 May 12 01:24:11 PM PDT 24 116488652 ps
T198 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1061829887 May 12 01:24:13 PM PDT 24 May 12 01:24:15 PM PDT 24 38856561 ps
T890 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1988727313 May 12 01:23:57 PM PDT 24 May 12 01:23:59 PM PDT 24 198013280 ps
T891 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3214435405 May 12 01:23:59 PM PDT 24 May 12 01:24:01 PM PDT 24 28140340 ps
T892 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2659853543 May 12 01:24:05 PM PDT 24 May 12 01:24:07 PM PDT 24 61419759 ps
T120 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2413610416 May 12 01:23:52 PM PDT 24 May 12 01:23:55 PM PDT 24 57523341 ps
T893 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2473392723 May 12 01:23:58 PM PDT 24 May 12 01:24:00 PM PDT 24 99119479 ps
T121 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1916030363 May 12 01:24:17 PM PDT 24 May 12 01:24:20 PM PDT 24 173225495 ps
T894 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1398330235 May 12 01:23:57 PM PDT 24 May 12 01:24:00 PM PDT 24 98794531 ps
T895 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.623004302 May 12 01:24:15 PM PDT 24 May 12 01:24:19 PM PDT 24 90265349 ps
T199 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3600438882 May 12 01:24:08 PM PDT 24 May 12 01:24:10 PM PDT 24 21448230 ps
T896 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.508879819 May 12 01:23:55 PM PDT 24 May 12 01:23:57 PM PDT 24 30305692 ps
T897 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1815601286 May 12 01:23:45 PM PDT 24 May 12 01:23:49 PM PDT 24 448919670 ps
T898 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.563543653 May 12 01:23:51 PM PDT 24 May 12 01:23:53 PM PDT 24 124359985 ps
T200 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.443302097 May 12 01:24:00 PM PDT 24 May 12 01:24:01 PM PDT 24 42802756 ps
T899 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2361683113 May 12 01:24:04 PM PDT 24 May 12 01:24:21 PM PDT 24 7164895958 ps
T201 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3932551239 May 12 01:24:00 PM PDT 24 May 12 01:24:02 PM PDT 24 66695609 ps
T900 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3944552917 May 12 01:24:09 PM PDT 24 May 12 01:24:11 PM PDT 24 28849060 ps
T901 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.267459067 May 12 01:24:15 PM PDT 24 May 12 01:24:17 PM PDT 24 101043315 ps
T116 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.339403153 May 12 01:24:11 PM PDT 24 May 12 01:24:14 PM PDT 24 117363151 ps
T902 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2449240035 May 12 01:23:55 PM PDT 24 May 12 01:23:58 PM PDT 24 433608900 ps
T903 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.4185988307 May 12 01:24:04 PM PDT 24 May 12 01:24:09 PM PDT 24 353325362 ps
T904 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4147475545 May 12 01:24:09 PM PDT 24 May 12 01:24:11 PM PDT 24 27117750 ps
T905 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.55565082 May 12 01:24:17 PM PDT 24 May 12 01:24:19 PM PDT 24 71157984 ps
T906 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2155702283 May 12 01:23:55 PM PDT 24 May 12 01:23:57 PM PDT 24 41059091 ps
T907 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3696569748 May 12 01:23:56 PM PDT 24 May 12 01:24:07 PM PDT 24 9672766620 ps
T908 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2186149497 May 12 01:24:11 PM PDT 24 May 12 01:24:13 PM PDT 24 106128659 ps
T909 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3642196657 May 12 01:24:18 PM PDT 24 May 12 01:24:19 PM PDT 24 173592513 ps
T113 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3146834977 May 12 01:24:12 PM PDT 24 May 12 01:24:15 PM PDT 24 44247991 ps
T184 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.573362056 May 12 01:23:51 PM PDT 24 May 12 01:23:53 PM PDT 24 80553511 ps
T910 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.744231107 May 12 01:24:14 PM PDT 24 May 12 01:24:16 PM PDT 24 70252736 ps
T911 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.160786329 May 12 01:24:07 PM PDT 24 May 12 01:24:09 PM PDT 24 81678014 ps
T912 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.901973015 May 12 01:23:58 PM PDT 24 May 12 01:24:00 PM PDT 24 53187111 ps
T913 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3043369463 May 12 01:24:05 PM PDT 24 May 12 01:24:07 PM PDT 24 83062066 ps
T914 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.267627219 May 12 01:23:51 PM PDT 24 May 12 01:23:54 PM PDT 24 48347706 ps
T915 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.344945709 May 12 01:24:05 PM PDT 24 May 12 01:24:08 PM PDT 24 26239427 ps
T916 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.205284867 May 12 01:24:05 PM PDT 24 May 12 01:24:08 PM PDT 24 140914387 ps
T917 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.29641683 May 12 01:23:50 PM PDT 24 May 12 01:23:56 PM PDT 24 3034088062 ps
T918 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2183720019 May 12 01:23:54 PM PDT 24 May 12 01:23:56 PM PDT 24 313806527 ps
T919 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.120523599 May 12 01:23:45 PM PDT 24 May 12 01:23:47 PM PDT 24 39016000 ps
T209 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2058411273 May 12 01:24:10 PM PDT 24 May 12 01:24:16 PM PDT 24 103010117 ps
T920 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1509152628 May 12 01:23:58 PM PDT 24 May 12 01:24:00 PM PDT 24 496297357 ps
T185 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3452216816 May 12 01:23:52 PM PDT 24 May 12 01:23:55 PM PDT 24 75505610 ps
T921 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3322070671 May 12 01:24:18 PM PDT 24 May 12 01:24:22 PM PDT 24 184236584 ps
T922 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.283943502 May 12 01:24:13 PM PDT 24 May 12 01:24:14 PM PDT 24 53348370 ps
T923 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3479521550 May 12 01:23:48 PM PDT 24 May 12 01:23:50 PM PDT 24 107697286 ps
T924 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2729804976 May 12 01:24:04 PM PDT 24 May 12 01:24:26 PM PDT 24 6384360783 ps
T925 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.4246813083 May 12 01:23:55 PM PDT 24 May 12 01:23:57 PM PDT 24 82786726 ps
T926 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2894663284 May 12 01:24:06 PM PDT 24 May 12 01:24:08 PM PDT 24 188771810 ps
T119 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3646244476 May 12 01:24:04 PM PDT 24 May 12 01:24:08 PM PDT 24 148685465 ps
T927 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4115991954 May 12 01:23:58 PM PDT 24 May 12 01:24:05 PM PDT 24 2749117543 ps
T928 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.143460400 May 12 01:23:59 PM PDT 24 May 12 01:24:08 PM PDT 24 1266356089 ps
T929 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1331792325 May 12 01:23:55 PM PDT 24 May 12 01:23:57 PM PDT 24 193286582 ps
T930 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2345392699 May 12 01:24:10 PM PDT 24 May 12 01:24:13 PM PDT 24 23973373 ps
T931 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1824341430 May 12 01:23:58 PM PDT 24 May 12 01:24:00 PM PDT 24 56809131 ps
T932 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4216937940 May 12 01:23:53 PM PDT 24 May 12 01:23:55 PM PDT 24 170994934 ps
T186 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1750673305 May 12 01:24:13 PM PDT 24 May 12 01:24:14 PM PDT 24 36943694 ps
T933 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1838112085 May 12 01:23:50 PM PDT 24 May 12 01:23:52 PM PDT 24 98096096 ps
T934 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2440802691 May 12 01:24:19 PM PDT 24 May 12 01:24:23 PM PDT 24 748626331 ps
T935 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3675111797 May 12 01:24:09 PM PDT 24 May 12 01:24:10 PM PDT 24 13395666 ps
T936 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2067825654 May 12 01:24:09 PM PDT 24 May 12 01:24:11 PM PDT 24 87967405 ps
T187 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2396944836 May 12 01:23:51 PM PDT 24 May 12 01:23:53 PM PDT 24 44014288 ps
T937 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.629074235 May 12 01:24:04 PM PDT 24 May 12 01:24:08 PM PDT 24 112064355 ps
T938 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.377076555 May 12 01:24:14 PM PDT 24 May 12 01:24:17 PM PDT 24 232889463 ps
T117 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2517971696 May 12 01:24:10 PM PDT 24 May 12 01:24:13 PM PDT 24 109007535 ps
T939 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2300914462 May 12 01:24:06 PM PDT 24 May 12 01:24:37 PM PDT 24 4143329200 ps
T940 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.854152679 May 12 01:24:06 PM PDT 24 May 12 01:24:08 PM PDT 24 76631880 ps
T941 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1721232345 May 12 01:24:09 PM PDT 24 May 12 01:24:10 PM PDT 24 16852885 ps
T188 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1072049946 May 12 01:24:10 PM PDT 24 May 12 01:24:12 PM PDT 24 46143738 ps
T942 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.186572343 May 12 01:24:04 PM PDT 24 May 12 01:24:09 PM PDT 24 83248756 ps
T943 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3834398658 May 12 01:23:49 PM PDT 24 May 12 01:23:50 PM PDT 24 30863973 ps
T944 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.788682332 May 12 01:24:04 PM PDT 24 May 12 01:24:06 PM PDT 24 25986140 ps
T111 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2632628152 May 12 01:24:12 PM PDT 24 May 12 01:24:17 PM PDT 24 371521540 ps
T945 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3661970585 May 12 01:24:02 PM PDT 24 May 12 01:24:05 PM PDT 24 141179265 ps
T946 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3021292900 May 12 01:24:04 PM PDT 24 May 12 01:24:07 PM PDT 24 120036156 ps
T947 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1071848723 May 12 01:23:51 PM PDT 24 May 12 01:23:53 PM PDT 24 53395517 ps
T948 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1351883879 May 12 01:24:10 PM PDT 24 May 12 01:24:12 PM PDT 24 26957010 ps
T949 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3167634374 May 12 01:24:17 PM PDT 24 May 12 01:24:45 PM PDT 24 5460481024 ps
T950 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2482146085 May 12 01:24:02 PM PDT 24 May 12 01:24:04 PM PDT 24 38131374 ps
T951 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3780691271 May 12 01:23:49 PM PDT 24 May 12 01:23:51 PM PDT 24 66064469 ps
T122 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3698563796 May 12 01:23:57 PM PDT 24 May 12 01:24:00 PM PDT 24 104219722 ps
T952 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1007400533 May 12 01:24:18 PM PDT 24 May 12 01:24:20 PM PDT 24 26383013 ps
T953 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2937928713 May 12 01:24:03 PM PDT 24 May 12 01:24:05 PM PDT 24 14749319 ps
T954 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1672136241 May 12 01:24:16 PM PDT 24 May 12 01:24:19 PM PDT 24 29396596 ps
T955 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.141499334 May 12 01:24:04 PM PDT 24 May 12 01:24:06 PM PDT 24 409770652 ps
T956 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3116879436 May 12 01:23:51 PM PDT 24 May 12 01:23:53 PM PDT 24 40798521 ps
T112 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2107477814 May 12 01:24:04 PM PDT 24 May 12 01:24:07 PM PDT 24 56008471 ps
T957 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1500826362 May 12 01:23:56 PM PDT 24 May 12 01:23:59 PM PDT 24 93105847 ps
T189 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3927534847 May 12 01:24:10 PM PDT 24 May 12 01:24:11 PM PDT 24 23167883 ps
T108 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1280338408 May 12 01:24:09 PM PDT 24 May 12 01:24:13 PM PDT 24 244311741 ps
T958 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2689551434 May 12 01:24:14 PM PDT 24 May 12 01:24:16 PM PDT 24 37017460 ps
T959 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1287670374 May 12 01:24:01 PM PDT 24 May 12 01:24:03 PM PDT 24 28334832 ps
T960 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.622892931 May 12 01:23:59 PM PDT 24 May 12 01:24:01 PM PDT 24 276573470 ps
T961 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3134776111 May 12 01:23:55 PM PDT 24 May 12 01:23:57 PM PDT 24 26536568 ps
T193 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.723321551 May 12 01:23:50 PM PDT 24 May 12 01:23:52 PM PDT 24 55644534 ps
T962 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3699664679 May 12 01:24:11 PM PDT 24 May 12 01:24:13 PM PDT 24 87325115 ps
T963 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1665066306 May 12 01:24:18 PM PDT 24 May 12 01:24:24 PM PDT 24 958613967 ps
T964 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.726957011 May 12 01:24:06 PM PDT 24 May 12 01:24:08 PM PDT 24 51309794 ps
T965 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3397984369 May 12 01:24:12 PM PDT 24 May 12 01:24:13 PM PDT 24 328551384 ps
T966 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.778014957 May 12 01:23:49 PM PDT 24 May 12 01:23:52 PM PDT 24 284299909 ps
T967 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2216570278 May 12 01:23:58 PM PDT 24 May 12 01:24:00 PM PDT 24 19583434 ps
T968 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2823036902 May 12 01:24:10 PM PDT 24 May 12 01:24:14 PM PDT 24 67794358 ps
T969 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2203760409 May 12 01:24:05 PM PDT 24 May 12 01:24:07 PM PDT 24 39008060 ps
T970 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.249170292 May 12 01:24:03 PM PDT 24 May 12 01:24:26 PM PDT 24 1085301122 ps
T124 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.375476042 May 12 01:24:16 PM PDT 24 May 12 01:24:20 PM PDT 24 83900541 ps
T971 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4132721171 May 12 01:24:10 PM PDT 24 May 12 01:24:12 PM PDT 24 67623151 ps
T972 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3966031512 May 12 01:24:03 PM PDT 24 May 12 01:24:05 PM PDT 24 20602273 ps
T190 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3031414492 May 12 01:23:51 PM PDT 24 May 12 01:23:53 PM PDT 24 30926762 ps
T973 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2157043320 May 12 01:24:14 PM PDT 24 May 12 01:24:15 PM PDT 24 15967085 ps
T974 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.257867123 May 12 01:24:00 PM PDT 24 May 12 01:24:04 PM PDT 24 122376726 ps
T975 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.226115389 May 12 01:24:04 PM PDT 24 May 12 01:24:06 PM PDT 24 403923703 ps
T976 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3098564053 May 12 01:23:46 PM PDT 24 May 12 01:23:51 PM PDT 24 161974788 ps
T977 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1710744770 May 12 01:24:10 PM PDT 24 May 12 01:24:13 PM PDT 24 114940429 ps
T978 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2539774401 May 12 01:23:55 PM PDT 24 May 12 01:23:56 PM PDT 24 199918454 ps
T979 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.666563241 May 12 01:23:50 PM PDT 24 May 12 01:23:51 PM PDT 24 714060198 ps
T980 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1404600236 May 12 01:23:44 PM PDT 24 May 12 01:23:53 PM PDT 24 4327556024 ps
T981 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1094932284 May 12 01:23:50 PM PDT 24 May 12 01:23:53 PM PDT 24 75741136 ps
T982 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2338644293 May 12 01:23:59 PM PDT 24 May 12 01:24:13 PM PDT 24 548637190 ps
T983 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2355982347 May 12 01:23:55 PM PDT 24 May 12 01:23:59 PM PDT 24 4072229357 ps
T984 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3742405005 May 12 01:24:19 PM PDT 24 May 12 01:24:20 PM PDT 24 54076046 ps
T191 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1962438685 May 12 01:24:11 PM PDT 24 May 12 01:24:12 PM PDT 24 48236215 ps
T194 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3811897362 May 12 01:24:04 PM PDT 24 May 12 01:24:06 PM PDT 24 16748523 ps
T123 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4179784182 May 12 01:24:12 PM PDT 24 May 12 01:24:17 PM PDT 24 1104520466 ps
T985 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1702200948 May 12 01:23:53 PM PDT 24 May 12 01:23:56 PM PDT 24 53181629 ps
T986 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3245097387 May 12 01:23:49 PM PDT 24 May 12 01:23:51 PM PDT 24 45778819 ps
T987 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.894369735 May 12 01:24:05 PM PDT 24 May 12 01:24:07 PM PDT 24 60274183 ps
T988 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1062493722 May 12 01:24:19 PM PDT 24 May 12 01:24:20 PM PDT 24 25044155 ps
T989 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3382542692 May 12 01:24:06 PM PDT 24 May 12 01:24:08 PM PDT 24 177726732 ps
T990 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1810242253 May 12 01:23:59 PM PDT 24 May 12 01:24:00 PM PDT 24 81173531 ps
T991 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.948926174 May 12 01:23:56 PM PDT 24 May 12 01:23:58 PM PDT 24 57640599 ps
T992 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2693610291 May 12 01:23:45 PM PDT 24 May 12 01:23:47 PM PDT 24 27529141 ps
T192 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1964167943 May 12 01:24:09 PM PDT 24 May 12 01:24:11 PM PDT 24 13100583 ps
T993 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.983532513 May 12 01:24:17 PM PDT 24 May 12 01:24:21 PM PDT 24 156122839 ps
T994 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2692266193 May 12 01:23:49 PM PDT 24 May 12 01:23:51 PM PDT 24 205940869 ps
T995 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.885415968 May 12 01:23:48 PM PDT 24 May 12 01:23:50 PM PDT 24 51504743 ps
T996 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2286685831 May 12 01:24:05 PM PDT 24 May 12 01:24:07 PM PDT 24 65703528 ps
T997 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.9578080 May 12 01:24:04 PM PDT 24 May 12 01:24:07 PM PDT 24 142952884 ps
T998 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1940719254 May 12 01:24:04 PM PDT 24 May 12 01:24:08 PM PDT 24 207325485 ps
T999 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2844667990 May 12 01:23:48 PM PDT 24 May 12 01:23:50 PM PDT 24 75450320 ps
T1000 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1580775802 May 12 01:23:52 PM PDT 24 May 12 01:23:54 PM PDT 24 153077591 ps

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.612924475
Short name T5
Test name
Test status
Simulation time 36054015540 ps
CPU time 327.99 seconds
Started May 12 01:31:37 PM PDT 24
Finished May 12 01:37:06 PM PDT 24
Peak memory 333084 kb
Host smart-cd96fed2-1029-4cfc-a746-2d22dc2343f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=612924475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.612924475
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1927722294
Short name T14
Test name
Test status
Simulation time 265591812 ps
CPU time 11.19 seconds
Started May 12 01:32:03 PM PDT 24
Finished May 12 01:32:15 PM PDT 24
Peak memory 218068 kb
Host smart-11203aef-595b-4a5f-8226-f68e4813e12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927722294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1927722294
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3710486735
Short name T17
Test name
Test status
Simulation time 1985356084 ps
CPU time 11.67 seconds
Started May 12 01:31:45 PM PDT 24
Finished May 12 01:31:57 PM PDT 24
Peak memory 225548 kb
Host smart-c8affbff-ab52-4a72-a9af-bae7b2b88521
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710486735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3710486735
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2047213615
Short name T96
Test name
Test status
Simulation time 78088258 ps
CPU time 3.61 seconds
Started May 12 01:23:50 PM PDT 24
Finished May 12 01:23:55 PM PDT 24
Peak memory 217356 kb
Host smart-f294c8f5-f943-4861-995f-037264294f0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047213615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2047213615
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1993981924
Short name T18
Test name
Test status
Simulation time 1718228199 ps
CPU time 81.46 seconds
Started May 12 01:32:25 PM PDT 24
Finished May 12 01:33:47 PM PDT 24
Peak memory 276500 kb
Host smart-018ffde3-4d97-477e-a324-0593a8ddb433
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993981924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1993981924
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.1932047381
Short name T145
Test name
Test status
Simulation time 851649717 ps
CPU time 9.43 seconds
Started May 12 01:31:58 PM PDT 24
Finished May 12 01:32:08 PM PDT 24
Peak memory 218044 kb
Host smart-86536b5a-41ef-4203-8fca-dea7ae89a79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932047381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.1932047381
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2522288761
Short name T45
Test name
Test status
Simulation time 401499468 ps
CPU time 38.69 seconds
Started May 12 01:30:41 PM PDT 24
Finished May 12 01:31:21 PM PDT 24
Peak memory 270108 kb
Host smart-29f49446-604f-411b-96ab-ab8928ee446a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522288761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2522288761
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3366155843
Short name T7
Test name
Test status
Simulation time 415558803 ps
CPU time 3.2 seconds
Started May 12 01:32:01 PM PDT 24
Finished May 12 01:32:05 PM PDT 24
Peak memory 209524 kb
Host smart-d0077e09-1e92-4b5b-9e8b-b8798ad65c1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366155843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3366155843
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.3796493598
Short name T130
Test name
Test status
Simulation time 59148133976 ps
CPU time 385.46 seconds
Started May 12 01:31:44 PM PDT 24
Finished May 12 01:38:11 PM PDT 24
Peak memory 290256 kb
Host smart-bb9ade5b-dfcf-48f1-8dff-221be1acdfee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3796493598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.3796493598
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2101522666
Short name T114
Test name
Test status
Simulation time 110987168 ps
CPU time 1.57 seconds
Started May 12 01:24:08 PM PDT 24
Finished May 12 01:24:10 PM PDT 24
Peak memory 218812 kb
Host smart-87dac2d2-4a70-4275-b8d9-d12d305ff3b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210152
2666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2101522666
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2812944256
Short name T31
Test name
Test status
Simulation time 698248472 ps
CPU time 13.78 seconds
Started May 12 01:31:49 PM PDT 24
Finished May 12 01:32:03 PM PDT 24
Peak memory 217996 kb
Host smart-be6c3a42-ea36-425c-a42d-9e0ca2a323d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812944256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2812944256
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3452216816
Short name T185
Test name
Test status
Simulation time 75505610 ps
CPU time 1.76 seconds
Started May 12 01:23:52 PM PDT 24
Finished May 12 01:23:55 PM PDT 24
Peak memory 209132 kb
Host smart-fe4090a8-dfc1-411b-91a5-2334e3a05ee8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452216816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3452216816
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2282132481
Short name T3
Test name
Test status
Simulation time 73527534 ps
CPU time 0.86 seconds
Started May 12 01:32:18 PM PDT 24
Finished May 12 01:32:20 PM PDT 24
Peak memory 209596 kb
Host smart-cf3eef4a-fb9f-4ea9-b083-e22c9cb9e3f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282132481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2282132481
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.764158942
Short name T110
Test name
Test status
Simulation time 202115221 ps
CPU time 2.89 seconds
Started May 12 01:24:09 PM PDT 24
Finished May 12 01:24:12 PM PDT 24
Peak memory 217424 kb
Host smart-323d68d8-a5f6-4929-af2e-c8a2177af6c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764158942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.764158942
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3428951065
Short name T104
Test name
Test status
Simulation time 116978813 ps
CPU time 2.96 seconds
Started May 12 01:24:08 PM PDT 24
Finished May 12 01:24:11 PM PDT 24
Peak memory 221848 kb
Host smart-c7b1aaeb-e548-450e-86fe-bc801c3a2c88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428951065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3428951065
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2632628152
Short name T111
Test name
Test status
Simulation time 371521540 ps
CPU time 4.03 seconds
Started May 12 01:24:12 PM PDT 24
Finished May 12 01:24:17 PM PDT 24
Peak memory 217416 kb
Host smart-809fc3d5-acbd-4cbd-9da7-6db8961104a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632628152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2632628152
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1309854794
Short name T211
Test name
Test status
Simulation time 434111338 ps
CPU time 10.47 seconds
Started May 12 01:30:32 PM PDT 24
Finished May 12 01:30:43 PM PDT 24
Peak memory 226024 kb
Host smart-a26d4287-7ddd-4ab9-b860-3f0929774906
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309854794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1309854794
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.3283988975
Short name T56
Test name
Test status
Simulation time 69933432312 ps
CPU time 498.81 seconds
Started May 12 01:32:05 PM PDT 24
Finished May 12 01:40:25 PM PDT 24
Peak memory 267328 kb
Host smart-51642717-53b3-4799-957b-3f9e6e0a5c5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283988975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.3283988975
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2020834920
Short name T29
Test name
Test status
Simulation time 1388707211 ps
CPU time 10.39 seconds
Started May 12 01:30:30 PM PDT 24
Finished May 12 01:30:41 PM PDT 24
Peak memory 209468 kb
Host smart-0c76750a-8707-433f-8576-e36aafcd5633
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020834920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2020834920
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2128627664
Short name T180
Test name
Test status
Simulation time 13906598 ps
CPU time 1.02 seconds
Started May 12 01:24:13 PM PDT 24
Finished May 12 01:24:14 PM PDT 24
Peak memory 208808 kb
Host smart-588a6779-7383-4250-a94e-3fe1cd05c39e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128627664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2128627664
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3753330196
Short name T32
Test name
Test status
Simulation time 22530910 ps
CPU time 0.93 seconds
Started May 12 01:32:45 PM PDT 24
Finished May 12 01:32:46 PM PDT 24
Peak memory 212728 kb
Host smart-62a42371-29d2-4b2f-b2e7-09d8aa706ece
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753330196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3753330196
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3146834977
Short name T113
Test name
Test status
Simulation time 44247991 ps
CPU time 2.32 seconds
Started May 12 01:24:12 PM PDT 24
Finished May 12 01:24:15 PM PDT 24
Peak memory 221788 kb
Host smart-5be6beac-178d-4adb-a673-b00cd375720d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146834977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3146834977
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1280338408
Short name T108
Test name
Test status
Simulation time 244311741 ps
CPU time 2.72 seconds
Started May 12 01:24:09 PM PDT 24
Finished May 12 01:24:13 PM PDT 24
Peak memory 221756 kb
Host smart-de231b62-667f-4d40-81c6-7574403ff176
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280338408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1280338408
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3580440747
Short name T118
Test name
Test status
Simulation time 48304893 ps
CPU time 2.26 seconds
Started May 12 01:23:54 PM PDT 24
Finished May 12 01:23:57 PM PDT 24
Peak memory 217376 kb
Host smart-39b3d3b9-ff6c-412e-906c-770a08e0657a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580440747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.3580440747
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2107477814
Short name T112
Test name
Test status
Simulation time 56008471 ps
CPU time 2.01 seconds
Started May 12 01:24:04 PM PDT 24
Finished May 12 01:24:07 PM PDT 24
Peak memory 221748 kb
Host smart-bb0c0d5d-fec9-4e3a-bacb-5e1eeaeedfb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107477814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2107477814
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.3944983868
Short name T208
Test name
Test status
Simulation time 33060133 ps
CPU time 0.84 seconds
Started May 12 01:30:31 PM PDT 24
Finished May 12 01:30:32 PM PDT 24
Peak memory 209276 kb
Host smart-698373fe-0d6d-4265-bd06-2ded15896db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944983868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.3944983868
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.781092005
Short name T167
Test name
Test status
Simulation time 12328260 ps
CPU time 0.78 seconds
Started May 12 01:30:42 PM PDT 24
Finished May 12 01:30:43 PM PDT 24
Peak memory 209292 kb
Host smart-8e1cf950-97fd-4480-bd71-3d76f80b46a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781092005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.781092005
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.489470889
Short name T206
Test name
Test status
Simulation time 21454642 ps
CPU time 0.82 seconds
Started May 12 01:30:45 PM PDT 24
Finished May 12 01:30:46 PM PDT 24
Peak memory 209220 kb
Host smart-898af7e6-6c25-496b-95ba-aa78ed85a8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489470889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.489470889
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.916910398
Short name T204
Test name
Test status
Simulation time 10479637 ps
CPU time 0.96 seconds
Started May 12 01:31:03 PM PDT 24
Finished May 12 01:31:05 PM PDT 24
Peak memory 209500 kb
Host smart-c63e9ef0-e7b3-4ce7-8bb6-0a2bcb3c53be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916910398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.916910398
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.282519452
Short name T22
Test name
Test status
Simulation time 247928217 ps
CPU time 4.4 seconds
Started May 12 01:31:18 PM PDT 24
Finished May 12 01:31:23 PM PDT 24
Peak memory 213744 kb
Host smart-ae3101e0-4ced-4f24-887d-01ab055e6aa1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282519452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke.
282519452
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3419133797
Short name T100
Test name
Test status
Simulation time 107169362 ps
CPU time 2.26 seconds
Started May 12 01:23:58 PM PDT 24
Finished May 12 01:24:01 PM PDT 24
Peak memory 217384 kb
Host smart-53e77f03-48bb-438b-94cd-3e2073d16cc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419133797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3419133797
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.339403153
Short name T116
Test name
Test status
Simulation time 117363151 ps
CPU time 2.02 seconds
Started May 12 01:24:11 PM PDT 24
Finished May 12 01:24:14 PM PDT 24
Peak memory 221664 kb
Host smart-8991aef4-8c94-4f23-8f0a-734665f4de01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339403153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.339403153
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1916030363
Short name T121
Test name
Test status
Simulation time 173225495 ps
CPU time 2.2 seconds
Started May 12 01:24:17 PM PDT 24
Finished May 12 01:24:20 PM PDT 24
Peak memory 212780 kb
Host smart-4c769d3e-676b-466e-939f-95001736206b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916030363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1916030363
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3698563796
Short name T122
Test name
Test status
Simulation time 104219722 ps
CPU time 2.45 seconds
Started May 12 01:23:57 PM PDT 24
Finished May 12 01:24:00 PM PDT 24
Peak memory 217372 kb
Host smart-f598b18b-ec4a-458b-a7a6-c68c868bc280
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698563796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.3698563796
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3646244476
Short name T119
Test name
Test status
Simulation time 148685465 ps
CPU time 2.89 seconds
Started May 12 01:24:04 PM PDT 24
Finished May 12 01:24:08 PM PDT 24
Peak memory 222228 kb
Host smart-5c27e365-26ac-4a78-b8c2-667a7ff1881f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646244476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3646244476
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.1098302421
Short name T40
Test name
Test status
Simulation time 23309145710 ps
CPU time 757.15 seconds
Started May 12 01:31:32 PM PDT 24
Finished May 12 01:44:10 PM PDT 24
Peak memory 396128 kb
Host smart-ad4c9faf-52ea-4c5d-bf62-113156a0d614
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1098302421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.1098302421
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1351826319
Short name T15
Test name
Test status
Simulation time 56088131 ps
CPU time 2.83 seconds
Started May 12 01:31:47 PM PDT 24
Finished May 12 01:31:51 PM PDT 24
Peak memory 222272 kb
Host smart-85981d8b-c9f1-42b6-a7ee-8ee0ee3d70a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351826319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1351826319
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.2652592531
Short name T213
Test name
Test status
Simulation time 3323569706 ps
CPU time 11.98 seconds
Started May 12 01:30:32 PM PDT 24
Finished May 12 01:30:44 PM PDT 24
Peak memory 250504 kb
Host smart-ea960e48-245e-49b6-980b-51b311bb648b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652592531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.2652592531
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.901973015
Short name T912
Test name
Test status
Simulation time 53187111 ps
CPU time 1.54 seconds
Started May 12 01:23:58 PM PDT 24
Finished May 12 01:24:00 PM PDT 24
Peak memory 209176 kb
Host smart-47e3cc1c-45e9-426c-8b26-2e9e19d087b6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901973015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bash
.901973015
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2396944836
Short name T187
Test name
Test status
Simulation time 44014288 ps
CPU time 0.95 seconds
Started May 12 01:23:51 PM PDT 24
Finished May 12 01:23:53 PM PDT 24
Peak memory 208816 kb
Host smart-0e3acc0e-7caa-4515-b7c3-bd362165bb1c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396944836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2396944836
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2473392723
Short name T893
Test name
Test status
Simulation time 99119479 ps
CPU time 1.28 seconds
Started May 12 01:23:58 PM PDT 24
Finished May 12 01:24:00 PM PDT 24
Peak memory 219584 kb
Host smart-0e3b40d3-7d91-4031-b4f3-d5b883f53b6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473392723 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2473392723
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.199208804
Short name T885
Test name
Test status
Simulation time 17890791 ps
CPU time 0.94 seconds
Started May 12 01:23:58 PM PDT 24
Finished May 12 01:23:59 PM PDT 24
Peak memory 209196 kb
Host smart-4bd1db7f-71dc-400c-8c06-193c19d01eb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199208804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.199208804
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3116879436
Short name T956
Test name
Test status
Simulation time 40798521 ps
CPU time 1.6 seconds
Started May 12 01:23:51 PM PDT 24
Finished May 12 01:23:53 PM PDT 24
Peak memory 209024 kb
Host smart-291dc3ef-6d72-4988-81c1-c229c0a99611
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116879436 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3116879436
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1404600236
Short name T980
Test name
Test status
Simulation time 4327556024 ps
CPU time 8.61 seconds
Started May 12 01:23:44 PM PDT 24
Finished May 12 01:23:53 PM PDT 24
Peak memory 209136 kb
Host smart-1ba75dce-96d5-4fac-9c8a-b93285a0f4f9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404600236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1404600236
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4115991954
Short name T927
Test name
Test status
Simulation time 2749117543 ps
CPU time 6.68 seconds
Started May 12 01:23:58 PM PDT 24
Finished May 12 01:24:05 PM PDT 24
Peak memory 209244 kb
Host smart-2c52eede-4e9d-4970-98a6-f7d1178ebe2c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115991954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.4115991954
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3780691271
Short name T951
Test name
Test status
Simulation time 66064469 ps
CPU time 1.49 seconds
Started May 12 01:23:49 PM PDT 24
Finished May 12 01:23:51 PM PDT 24
Peak memory 210532 kb
Host smart-e43106ec-fd21-4bd7-81ee-af4bf95e103b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780691271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3780691271
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1815601286
Short name T897
Test name
Test status
Simulation time 448919670 ps
CPU time 3.95 seconds
Started May 12 01:23:45 PM PDT 24
Finished May 12 01:23:49 PM PDT 24
Peak memory 217464 kb
Host smart-e7c46ddc-0c99-409b-9e6f-b8fbcf453fec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181560
1286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1815601286
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3479521550
Short name T923
Test name
Test status
Simulation time 107697286 ps
CPU time 1.64 seconds
Started May 12 01:23:48 PM PDT 24
Finished May 12 01:23:50 PM PDT 24
Peak memory 209112 kb
Host smart-b3224751-0d1c-4607-88e6-de20ffd422ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479521550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3479521550
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.2693610291
Short name T992
Test name
Test status
Simulation time 27529141 ps
CPU time 1.43 seconds
Started May 12 01:23:45 PM PDT 24
Finished May 12 01:23:47 PM PDT 24
Peak memory 209116 kb
Host smart-08c8eb4f-b7b7-41e3-bdf0-beb30e909030
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693610291 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.2693610291
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.120523599
Short name T919
Test name
Test status
Simulation time 39016000 ps
CPU time 1.09 seconds
Started May 12 01:23:45 PM PDT 24
Finished May 12 01:23:47 PM PDT 24
Peak memory 209052 kb
Host smart-67f5e629-0053-4769-b6b3-4a12dbb416f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120523599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
same_csr_outstanding.120523599
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3098564053
Short name T976
Test name
Test status
Simulation time 161974788 ps
CPU time 4.63 seconds
Started May 12 01:23:46 PM PDT 24
Finished May 12 01:23:51 PM PDT 24
Peak memory 217460 kb
Host smart-6a297b6a-00ae-4d12-a5c3-a2f3ba4630f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098564053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3098564053
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3959951037
Short name T105
Test name
Test status
Simulation time 37408886 ps
CPU time 1.79 seconds
Started May 12 01:23:50 PM PDT 24
Finished May 12 01:23:52 PM PDT 24
Peak memory 209184 kb
Host smart-2072595f-b934-45ac-abd5-64c99d0a1f14
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959951037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3959951037
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.508879819
Short name T896
Test name
Test status
Simulation time 30305692 ps
CPU time 1.56 seconds
Started May 12 01:23:55 PM PDT 24
Finished May 12 01:23:57 PM PDT 24
Peak memory 209176 kb
Host smart-21b6e0d1-0094-4012-b5b8-14128a48772d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508879819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.508879819
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.573362056
Short name T184
Test name
Test status
Simulation time 80553511 ps
CPU time 0.97 seconds
Started May 12 01:23:51 PM PDT 24
Finished May 12 01:23:53 PM PDT 24
Peak memory 211176 kb
Host smart-2926b424-607e-430c-8f70-ec814779928d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573362056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.573362056
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1071848723
Short name T947
Test name
Test status
Simulation time 53395517 ps
CPU time 1 seconds
Started May 12 01:23:51 PM PDT 24
Finished May 12 01:23:53 PM PDT 24
Peak memory 217436 kb
Host smart-5ceb7a44-03e2-467a-963f-3419af68cc67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071848723 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1071848723
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.723321551
Short name T193
Test name
Test status
Simulation time 55644534 ps
CPU time 1.02 seconds
Started May 12 01:23:50 PM PDT 24
Finished May 12 01:23:52 PM PDT 24
Peak memory 217056 kb
Host smart-863cbf10-35e3-49b3-899c-49111da3fea4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723321551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.723321551
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1094932284
Short name T981
Test name
Test status
Simulation time 75741136 ps
CPU time 2.38 seconds
Started May 12 01:23:50 PM PDT 24
Finished May 12 01:23:53 PM PDT 24
Peak memory 208928 kb
Host smart-b34c6fca-5a87-4a91-bd18-001b299a3449
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094932284 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1094932284
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.282351322
Short name T128
Test name
Test status
Simulation time 330632512 ps
CPU time 5.84 seconds
Started May 12 01:23:47 PM PDT 24
Finished May 12 01:23:54 PM PDT 24
Peak memory 208800 kb
Host smart-d1cdf6a8-2e40-4893-bf1c-dfe2fc78ab27
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282351322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.282351322
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.888373091
Short name T107
Test name
Test status
Simulation time 1887233434 ps
CPU time 15.04 seconds
Started May 12 01:23:58 PM PDT 24
Finished May 12 01:24:13 PM PDT 24
Peak memory 208820 kb
Host smart-5f294c8b-6d0e-4991-8704-2c883f72ea45
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888373091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.888373091
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2757707927
Short name T883
Test name
Test status
Simulation time 84059655 ps
CPU time 1.53 seconds
Started May 12 01:23:57 PM PDT 24
Finished May 12 01:23:59 PM PDT 24
Peak memory 210712 kb
Host smart-deb8409f-e083-417b-94dd-65a835455b71
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757707927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2757707927
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2904088492
Short name T127
Test name
Test status
Simulation time 104613676 ps
CPU time 1.92 seconds
Started May 12 01:23:51 PM PDT 24
Finished May 12 01:23:54 PM PDT 24
Peak memory 217404 kb
Host smart-a639b7a9-c58f-4b86-9b71-cebc5652ed3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290408
8492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2904088492
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2844667990
Short name T999
Test name
Test status
Simulation time 75450320 ps
CPU time 1.08 seconds
Started May 12 01:23:48 PM PDT 24
Finished May 12 01:23:50 PM PDT 24
Peak memory 209060 kb
Host smart-42c78e9e-6cd1-4b9c-af54-2ecbcfe0be3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844667990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2844667990
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.885415968
Short name T995
Test name
Test status
Simulation time 51504743 ps
CPU time 1.02 seconds
Started May 12 01:23:48 PM PDT 24
Finished May 12 01:23:50 PM PDT 24
Peak memory 209168 kb
Host smart-a476ba06-7cdb-4e0e-aed6-33a3b7ca1a32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885415968 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.885415968
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3245097387
Short name T986
Test name
Test status
Simulation time 45778819 ps
CPU time 1.11 seconds
Started May 12 01:23:49 PM PDT 24
Finished May 12 01:23:51 PM PDT 24
Peak memory 209176 kb
Host smart-7418b2ee-4b58-4b42-a268-4154c5a22b5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245097387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3245097387
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.267627219
Short name T914
Test name
Test status
Simulation time 48347706 ps
CPU time 2.26 seconds
Started May 12 01:23:51 PM PDT 24
Finished May 12 01:23:54 PM PDT 24
Peak memory 217508 kb
Host smart-90f6f490-e6d5-4f07-90ac-91d999c38c1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267627219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.267627219
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2598879944
Short name T889
Test name
Test status
Simulation time 116488652 ps
CPU time 1.33 seconds
Started May 12 01:24:09 PM PDT 24
Finished May 12 01:24:11 PM PDT 24
Peak memory 217416 kb
Host smart-e96c80af-1568-41b3-989c-0eed9a6531f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598879944 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2598879944
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1964167943
Short name T192
Test name
Test status
Simulation time 13100583 ps
CPU time 0.91 seconds
Started May 12 01:24:09 PM PDT 24
Finished May 12 01:24:11 PM PDT 24
Peak memory 209028 kb
Host smart-391d6642-ed9c-46bd-95ac-81fa3bcba85d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964167943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1964167943
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2345392699
Short name T930
Test name
Test status
Simulation time 23973373 ps
CPU time 1.34 seconds
Started May 12 01:24:10 PM PDT 24
Finished May 12 01:24:13 PM PDT 24
Peak memory 209092 kb
Host smart-63122266-3dc8-4a8e-8ad3-2faefb47d535
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345392699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2345392699
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3322070671
Short name T921
Test name
Test status
Simulation time 184236584 ps
CPU time 3.88 seconds
Started May 12 01:24:18 PM PDT 24
Finished May 12 01:24:22 PM PDT 24
Peak memory 217464 kb
Host smart-a519e96b-7e47-424f-a7cb-a1155e8050d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322070671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.3322070671
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2186149497
Short name T908
Test name
Test status
Simulation time 106128659 ps
CPU time 1.08 seconds
Started May 12 01:24:11 PM PDT 24
Finished May 12 01:24:13 PM PDT 24
Peak memory 217516 kb
Host smart-d11adc49-4b05-4271-ae39-34c16d99fa29
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186149497 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2186149497
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3675111797
Short name T935
Test name
Test status
Simulation time 13395666 ps
CPU time 0.98 seconds
Started May 12 01:24:09 PM PDT 24
Finished May 12 01:24:10 PM PDT 24
Peak memory 208532 kb
Host smart-3abb6a90-5d7e-4c90-8053-96b884f00981
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675111797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3675111797
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1721232345
Short name T941
Test name
Test status
Simulation time 16852885 ps
CPU time 1.15 seconds
Started May 12 01:24:09 PM PDT 24
Finished May 12 01:24:10 PM PDT 24
Peak memory 209108 kb
Host smart-4ac3d203-17c7-41eb-b40a-d9b50f918a3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721232345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1721232345
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3219922398
Short name T95
Test name
Test status
Simulation time 159329800 ps
CPU time 5.69 seconds
Started May 12 01:24:09 PM PDT 24
Finished May 12 01:24:15 PM PDT 24
Peak memory 217440 kb
Host smart-e1a27f62-f9f4-435b-a590-5c4017b9e022
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219922398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3219922398
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1710744770
Short name T977
Test name
Test status
Simulation time 114940429 ps
CPU time 1.62 seconds
Started May 12 01:24:10 PM PDT 24
Finished May 12 01:24:13 PM PDT 24
Peak memory 217560 kb
Host smart-4b28091f-1dd8-415e-b2bb-5c0c99b47063
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710744770 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1710744770
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1351883879
Short name T948
Test name
Test status
Simulation time 26957010 ps
CPU time 0.87 seconds
Started May 12 01:24:10 PM PDT 24
Finished May 12 01:24:12 PM PDT 24
Peak memory 209124 kb
Host smart-b5bec17b-86f5-41e3-ad64-36d5a31b1783
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351883879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1351883879
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.4147475545
Short name T904
Test name
Test status
Simulation time 27117750 ps
CPU time 1.05 seconds
Started May 12 01:24:09 PM PDT 24
Finished May 12 01:24:11 PM PDT 24
Peak memory 209168 kb
Host smart-60470606-d095-4359-9239-e90160088ad6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147475545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.4147475545
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.4132721171
Short name T971
Test name
Test status
Simulation time 67623151 ps
CPU time 1.59 seconds
Started May 12 01:24:10 PM PDT 24
Finished May 12 01:24:12 PM PDT 24
Peak memory 217788 kb
Host smart-63611c68-1af9-4a83-a41c-54f956ec4766
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132721171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.4132721171
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2067825654
Short name T936
Test name
Test status
Simulation time 87967405 ps
CPU time 1.1 seconds
Started May 12 01:24:09 PM PDT 24
Finished May 12 01:24:11 PM PDT 24
Peak memory 217584 kb
Host smart-ae54aaf2-27cc-441c-882c-0efc6910686d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067825654 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2067825654
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3699664679
Short name T962
Test name
Test status
Simulation time 87325115 ps
CPU time 1.05 seconds
Started May 12 01:24:11 PM PDT 24
Finished May 12 01:24:13 PM PDT 24
Peak memory 209128 kb
Host smart-ea5c8eae-19d6-46aa-8c3a-9f0b2fdf5e8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699664679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3699664679
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2823036902
Short name T968
Test name
Test status
Simulation time 67794358 ps
CPU time 3.01 seconds
Started May 12 01:24:10 PM PDT 24
Finished May 12 01:24:14 PM PDT 24
Peak memory 217408 kb
Host smart-f01a1cae-1818-4027-a631-198277e85406
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823036902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2823036902
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3944552917
Short name T900
Test name
Test status
Simulation time 28849060 ps
CPU time 1.3 seconds
Started May 12 01:24:09 PM PDT 24
Finished May 12 01:24:11 PM PDT 24
Peak memory 219004 kb
Host smart-2518ea79-75b4-4cdf-b276-e1477a433af4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944552917 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3944552917
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3927534847
Short name T189
Test name
Test status
Simulation time 23167883 ps
CPU time 1 seconds
Started May 12 01:24:10 PM PDT 24
Finished May 12 01:24:11 PM PDT 24
Peak memory 209156 kb
Host smart-de8b575a-9f51-49b7-86d1-4373e30b6f2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927534847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3927534847
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3600438882
Short name T199
Test name
Test status
Simulation time 21448230 ps
CPU time 1.51 seconds
Started May 12 01:24:08 PM PDT 24
Finished May 12 01:24:10 PM PDT 24
Peak memory 211012 kb
Host smart-1792e9ad-25fb-4ab1-b9f8-4dc5c097ea5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600438882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3600438882
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.2517971696
Short name T117
Test name
Test status
Simulation time 109007535 ps
CPU time 1.81 seconds
Started May 12 01:24:10 PM PDT 24
Finished May 12 01:24:13 PM PDT 24
Peak memory 221300 kb
Host smart-84c2d9ea-80d6-4101-94eb-94e17d8879aa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517971696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.2517971696
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.744231107
Short name T910
Test name
Test status
Simulation time 70252736 ps
CPU time 1.16 seconds
Started May 12 01:24:14 PM PDT 24
Finished May 12 01:24:16 PM PDT 24
Peak memory 217356 kb
Host smart-1b35b01b-db53-40b6-b744-0466406a6b17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744231107 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.744231107
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1962438685
Short name T191
Test name
Test status
Simulation time 48236215 ps
CPU time 0.91 seconds
Started May 12 01:24:11 PM PDT 24
Finished May 12 01:24:12 PM PDT 24
Peak memory 209208 kb
Host smart-82ee539e-79b5-41fa-9ef6-a8be74f269ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962438685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.1962438685
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1061829887
Short name T198
Test name
Test status
Simulation time 38856561 ps
CPU time 1.41 seconds
Started May 12 01:24:13 PM PDT 24
Finished May 12 01:24:15 PM PDT 24
Peak memory 209204 kb
Host smart-5e57fae8-582c-4609-af76-7ce19e19c37b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061829887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1061829887
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.737102146
Short name T94
Test name
Test status
Simulation time 109852959 ps
CPU time 4.42 seconds
Started May 12 01:24:10 PM PDT 24
Finished May 12 01:24:15 PM PDT 24
Peak memory 217420 kb
Host smart-0db9fd2d-12cc-4c67-86a5-ff637c8d9cb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737102146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.737102146
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2058411273
Short name T209
Test name
Test status
Simulation time 103010117 ps
CPU time 4.16 seconds
Started May 12 01:24:10 PM PDT 24
Finished May 12 01:24:16 PM PDT 24
Peak memory 217452 kb
Host smart-cf1d0302-c3e9-425d-839b-50a375744663
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058411273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2058411273
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2689551434
Short name T958
Test name
Test status
Simulation time 37017460 ps
CPU time 1.16 seconds
Started May 12 01:24:14 PM PDT 24
Finished May 12 01:24:16 PM PDT 24
Peak memory 217796 kb
Host smart-5efef4a9-66ab-468d-8f45-c8f2202aed06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689551434 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2689551434
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1750673305
Short name T186
Test name
Test status
Simulation time 36943694 ps
CPU time 0.97 seconds
Started May 12 01:24:13 PM PDT 24
Finished May 12 01:24:14 PM PDT 24
Peak memory 209112 kb
Host smart-91a82b14-aeeb-4c60-a7d0-5ed98c07f9b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750673305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1750673305
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.377076555
Short name T938
Test name
Test status
Simulation time 232889463 ps
CPU time 1.98 seconds
Started May 12 01:24:14 PM PDT 24
Finished May 12 01:24:17 PM PDT 24
Peak memory 209164 kb
Host smart-52256390-1a32-4535-b6b0-b7dc63c90153
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377076555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_same_csr_outstanding.377076555
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.623004302
Short name T895
Test name
Test status
Simulation time 90265349 ps
CPU time 3.41 seconds
Started May 12 01:24:15 PM PDT 24
Finished May 12 01:24:19 PM PDT 24
Peak memory 217428 kb
Host smart-4be60dbf-79d7-419b-916e-3e0053d75bda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623004302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.623004302
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.267459067
Short name T901
Test name
Test status
Simulation time 101043315 ps
CPU time 1.29 seconds
Started May 12 01:24:15 PM PDT 24
Finished May 12 01:24:17 PM PDT 24
Peak memory 217508 kb
Host smart-471dda94-4418-4a19-be4e-db0fdeabfc11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267459067 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.267459067
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2979095158
Short name T182
Test name
Test status
Simulation time 38584944 ps
CPU time 0.92 seconds
Started May 12 01:24:16 PM PDT 24
Finished May 12 01:24:18 PM PDT 24
Peak memory 209136 kb
Host smart-b612b15b-3f2c-4942-805f-be7f4ff7a5a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979095158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2979095158
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2086625792
Short name T197
Test name
Test status
Simulation time 453927220 ps
CPU time 1.52 seconds
Started May 12 01:24:18 PM PDT 24
Finished May 12 01:24:20 PM PDT 24
Peak memory 211332 kb
Host smart-33762318-b382-424f-a354-204dbc56201c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086625792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2086625792
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.162388702
Short name T886
Test name
Test status
Simulation time 401423583 ps
CPU time 3.9 seconds
Started May 12 01:24:17 PM PDT 24
Finished May 12 01:24:22 PM PDT 24
Peak memory 217868 kb
Host smart-839422bf-0d8b-408d-99b2-1cc83310ab8f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162388702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.162388702
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.283943502
Short name T922
Test name
Test status
Simulation time 53348370 ps
CPU time 0.99 seconds
Started May 12 01:24:13 PM PDT 24
Finished May 12 01:24:14 PM PDT 24
Peak memory 217460 kb
Host smart-f8128e2d-1ddc-4b99-bc55-5695da707512
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283943502 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.283943502
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1700646092
Short name T884
Test name
Test status
Simulation time 38001176 ps
CPU time 0.81 seconds
Started May 12 01:24:15 PM PDT 24
Finished May 12 01:24:16 PM PDT 24
Peak memory 208980 kb
Host smart-b7bae06e-dd52-4a48-96f6-9c5251587bb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700646092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1700646092
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3397984369
Short name T965
Test name
Test status
Simulation time 328551384 ps
CPU time 1.11 seconds
Started May 12 01:24:12 PM PDT 24
Finished May 12 01:24:13 PM PDT 24
Peak memory 209212 kb
Host smart-460c03e7-c749-4806-bcb3-dc8f687f19d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397984369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3397984369
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.462310841
Short name T103
Test name
Test status
Simulation time 79739587 ps
CPU time 1.65 seconds
Started May 12 01:24:15 PM PDT 24
Finished May 12 01:24:17 PM PDT 24
Peak memory 217484 kb
Host smart-7652be12-2783-4766-9b5f-b3b6deeb1b51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462310841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.462310841
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4179784182
Short name T123
Test name
Test status
Simulation time 1104520466 ps
CPU time 3.91 seconds
Started May 12 01:24:12 PM PDT 24
Finished May 12 01:24:17 PM PDT 24
Peak memory 217264 kb
Host smart-62494b57-d011-4269-a0aa-faaaa85759b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179784182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.4179784182
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3642196657
Short name T909
Test name
Test status
Simulation time 173592513 ps
CPU time 1.06 seconds
Started May 12 01:24:18 PM PDT 24
Finished May 12 01:24:19 PM PDT 24
Peak memory 217452 kb
Host smart-b297aed6-e9a4-48b8-a172-ebdc20ee3f2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642196657 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3642196657
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2157043320
Short name T973
Test name
Test status
Simulation time 15967085 ps
CPU time 1.13 seconds
Started May 12 01:24:14 PM PDT 24
Finished May 12 01:24:15 PM PDT 24
Peak memory 209132 kb
Host smart-34e9ede9-f6cb-4437-8382-a5ce485a72a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157043320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2157043320
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1672136241
Short name T954
Test name
Test status
Simulation time 29396596 ps
CPU time 1.53 seconds
Started May 12 01:24:16 PM PDT 24
Finished May 12 01:24:19 PM PDT 24
Peak memory 209172 kb
Host smart-5d32a207-5d30-40a1-acb5-92d8dafcc6e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672136241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1672136241
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2956435048
Short name T888
Test name
Test status
Simulation time 84659613 ps
CPU time 3.53 seconds
Started May 12 01:24:15 PM PDT 24
Finished May 12 01:24:19 PM PDT 24
Peak memory 217412 kb
Host smart-433f47da-e5e8-43b6-a8d9-5cdbc8544c3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956435048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2956435048
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.375476042
Short name T124
Test name
Test status
Simulation time 83900541 ps
CPU time 3.62 seconds
Started May 12 01:24:16 PM PDT 24
Finished May 12 01:24:20 PM PDT 24
Peak memory 221964 kb
Host smart-33ac7f2d-3cab-44f8-b5cf-3ca7d8370d9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375476042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.375476042
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.141499334
Short name T955
Test name
Test status
Simulation time 409770652 ps
CPU time 1.28 seconds
Started May 12 01:24:04 PM PDT 24
Finished May 12 01:24:06 PM PDT 24
Peak memory 209416 kb
Host smart-f520be12-59a5-4cfd-b384-504de850bfa2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141499334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.141499334
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2692266193
Short name T994
Test name
Test status
Simulation time 205940869 ps
CPU time 1.78 seconds
Started May 12 01:23:49 PM PDT 24
Finished May 12 01:23:51 PM PDT 24
Peak memory 207952 kb
Host smart-c3572422-ab89-41a8-8e84-3bf969852779
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692266193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2692266193
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3031414492
Short name T190
Test name
Test status
Simulation time 30926762 ps
CPU time 1 seconds
Started May 12 01:23:51 PM PDT 24
Finished May 12 01:23:53 PM PDT 24
Peak memory 209572 kb
Host smart-14a32567-7544-497c-8d8f-7ca55fb2361d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031414492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3031414492
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.563543653
Short name T898
Test name
Test status
Simulation time 124359985 ps
CPU time 1.32 seconds
Started May 12 01:23:51 PM PDT 24
Finished May 12 01:23:53 PM PDT 24
Peak memory 219012 kb
Host smart-cc58f9a5-b8a3-49ca-9bab-dd26d9aa5e88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563543653 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.563543653
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3765500447
Short name T183
Test name
Test status
Simulation time 36184272 ps
CPU time 0.91 seconds
Started May 12 01:23:54 PM PDT 24
Finished May 12 01:23:55 PM PDT 24
Peak memory 209176 kb
Host smart-aff5f07e-4ea8-4152-9183-36b04275e2a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765500447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3765500447
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3359811674
Short name T880
Test name
Test status
Simulation time 17731987 ps
CPU time 0.86 seconds
Started May 12 01:24:04 PM PDT 24
Finished May 12 01:24:06 PM PDT 24
Peak memory 209024 kb
Host smart-fd689e45-f261-4008-abea-961fa11bd9ae
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359811674 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3359811674
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1718745458
Short name T879
Test name
Test status
Simulation time 254948367 ps
CPU time 3.22 seconds
Started May 12 01:23:53 PM PDT 24
Finished May 12 01:23:56 PM PDT 24
Peak memory 207708 kb
Host smart-1c973b95-759d-43fc-98f0-d182104bfa04
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718745458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1718745458
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1483089515
Short name T876
Test name
Test status
Simulation time 2254827859 ps
CPU time 5.4 seconds
Started May 12 01:23:52 PM PDT 24
Finished May 12 01:23:58 PM PDT 24
Peak memory 208880 kb
Host smart-734dbe2a-68aa-4fc3-ad25-6af6c84c094a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483089515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1483089515
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.666563241
Short name T979
Test name
Test status
Simulation time 714060198 ps
CPU time 1.25 seconds
Started May 12 01:23:50 PM PDT 24
Finished May 12 01:23:51 PM PDT 24
Peak memory 210568 kb
Host smart-e72cc057-ffa5-4a09-84e4-c841be7999b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666563241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.666563241
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.778014957
Short name T966
Test name
Test status
Simulation time 284299909 ps
CPU time 2.73 seconds
Started May 12 01:23:49 PM PDT 24
Finished May 12 01:23:52 PM PDT 24
Peak memory 217420 kb
Host smart-f092293d-7883-46e3-80f0-023d2953f40d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778014
957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.778014957
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1838112085
Short name T933
Test name
Test status
Simulation time 98096096 ps
CPU time 1.21 seconds
Started May 12 01:23:50 PM PDT 24
Finished May 12 01:23:52 PM PDT 24
Peak memory 209124 kb
Host smart-8e2e89f3-3291-49ce-b7ac-077d9d7aaf3d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838112085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1838112085
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.9578080
Short name T997
Test name
Test status
Simulation time 142952884 ps
CPU time 1.84 seconds
Started May 12 01:24:04 PM PDT 24
Finished May 12 01:24:07 PM PDT 24
Peak memory 209256 kb
Host smart-b9727e05-c383-4dbf-bb4e-7ebb653d26e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9578080 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.9578080
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.760178203
Short name T101
Test name
Test status
Simulation time 73094800 ps
CPU time 1.35 seconds
Started May 12 01:23:51 PM PDT 24
Finished May 12 01:23:53 PM PDT 24
Peak memory 209256 kb
Host smart-7688ce6c-a909-4eac-b420-88f0638b17d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760178203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
same_csr_outstanding.760178203
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.639845303
Short name T881
Test name
Test status
Simulation time 486344876 ps
CPU time 3.71 seconds
Started May 12 01:23:52 PM PDT 24
Finished May 12 01:23:57 PM PDT 24
Peak memory 217728 kb
Host smart-5cdfac87-edf2-4c6d-a501-a4510195a2a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639845303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.639845303
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2413610416
Short name T120
Test name
Test status
Simulation time 57523341 ps
CPU time 2.03 seconds
Started May 12 01:23:52 PM PDT 24
Finished May 12 01:23:55 PM PDT 24
Peak memory 221204 kb
Host smart-1a415466-99f2-4703-9efc-38139ed3f9d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413610416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2413610416
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2183720019
Short name T918
Test name
Test status
Simulation time 313806527 ps
CPU time 1.72 seconds
Started May 12 01:23:54 PM PDT 24
Finished May 12 01:23:56 PM PDT 24
Peak memory 208928 kb
Host smart-8a82d696-b8d1-49d7-a80f-edd76220cf3f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183720019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2183720019
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2216570278
Short name T967
Test name
Test status
Simulation time 19583434 ps
CPU time 1.21 seconds
Started May 12 01:23:58 PM PDT 24
Finished May 12 01:24:00 PM PDT 24
Peak memory 209180 kb
Host smart-8db1aa2d-2c30-4028-b661-2ee6ed75e1be
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216570278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2216570278
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3811897362
Short name T194
Test name
Test status
Simulation time 16748523 ps
CPU time 0.95 seconds
Started May 12 01:24:04 PM PDT 24
Finished May 12 01:24:06 PM PDT 24
Peak memory 209680 kb
Host smart-6898f71e-2e51-4019-9679-cfda92c6ec8b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811897362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3811897362
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.4246813083
Short name T925
Test name
Test status
Simulation time 82786726 ps
CPU time 1.36 seconds
Started May 12 01:23:55 PM PDT 24
Finished May 12 01:23:57 PM PDT 24
Peak memory 218556 kb
Host smart-ce486597-7904-4a4b-9f16-757628d3355b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246813083 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.4246813083
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1892549859
Short name T137
Test name
Test status
Simulation time 39132471 ps
CPU time 0.86 seconds
Started May 12 01:23:57 PM PDT 24
Finished May 12 01:23:58 PM PDT 24
Peak memory 208928 kb
Host smart-d3a137ec-440b-45e3-844d-49c8dd5fb37c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892549859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1892549859
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2155702283
Short name T906
Test name
Test status
Simulation time 41059091 ps
CPU time 1.89 seconds
Started May 12 01:23:55 PM PDT 24
Finished May 12 01:23:57 PM PDT 24
Peak memory 209060 kb
Host smart-8974ddf0-68e3-41a6-9094-74fef47df0a8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155702283 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2155702283
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.29641683
Short name T917
Test name
Test status
Simulation time 3034088062 ps
CPU time 5.32 seconds
Started May 12 01:23:50 PM PDT 24
Finished May 12 01:23:56 PM PDT 24
Peak memory 208372 kb
Host smart-bd7ab901-67ff-4400-98b9-bff918728752
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29641683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.lc_ctrl_jtag_csr_aliasing.29641683
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4001260363
Short name T129
Test name
Test status
Simulation time 2029343895 ps
CPU time 14.45 seconds
Started May 12 01:23:52 PM PDT 24
Finished May 12 01:24:07 PM PDT 24
Peak memory 209316 kb
Host smart-91153b0f-5f06-43b3-a610-0e26d28895c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001260363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.4001260363
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2539774401
Short name T978
Test name
Test status
Simulation time 199918454 ps
CPU time 1.3 seconds
Started May 12 01:23:55 PM PDT 24
Finished May 12 01:23:56 PM PDT 24
Peak memory 210504 kb
Host smart-68cfc804-3585-42b3-a7ff-6e6cf0f9e575
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539774401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2539774401
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2449240035
Short name T902
Test name
Test status
Simulation time 433608900 ps
CPU time 1.68 seconds
Started May 12 01:23:55 PM PDT 24
Finished May 12 01:23:58 PM PDT 24
Peak memory 218432 kb
Host smart-9d9738ad-0156-465e-9ef2-5ca7db13578d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244924
0035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2449240035
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1580775802
Short name T1000
Test name
Test status
Simulation time 153077591 ps
CPU time 1.24 seconds
Started May 12 01:23:52 PM PDT 24
Finished May 12 01:23:54 PM PDT 24
Peak memory 209072 kb
Host smart-137cd155-65ff-400a-a7d6-e8008b31164e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580775802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1580775802
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3834398658
Short name T943
Test name
Test status
Simulation time 30863973 ps
CPU time 1.14 seconds
Started May 12 01:23:49 PM PDT 24
Finished May 12 01:23:50 PM PDT 24
Peak memory 208792 kb
Host smart-05877297-d04f-4ee3-ab0a-a0f00f87f628
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834398658 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3834398658
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.948926174
Short name T991
Test name
Test status
Simulation time 57640599 ps
CPU time 1.49 seconds
Started May 12 01:23:56 PM PDT 24
Finished May 12 01:23:58 PM PDT 24
Peak memory 209188 kb
Host smart-e8b0d7d2-286e-4aaf-97b1-5f3638cc4ea6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948926174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.948926174
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1702200948
Short name T985
Test name
Test status
Simulation time 53181629 ps
CPU time 1.98 seconds
Started May 12 01:23:53 PM PDT 24
Finished May 12 01:23:56 PM PDT 24
Peak memory 217424 kb
Host smart-cbe5c215-204b-48f0-a48b-ce2edd8a04d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702200948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1702200948
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.621270276
Short name T115
Test name
Test status
Simulation time 52545763 ps
CPU time 2.49 seconds
Started May 12 01:23:55 PM PDT 24
Finished May 12 01:23:58 PM PDT 24
Peak memory 217468 kb
Host smart-e6702376-9dc2-42bc-a08d-c40af5f1ac6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621270276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_e
rr.621270276
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2354563142
Short name T875
Test name
Test status
Simulation time 119564071 ps
CPU time 1.29 seconds
Started May 12 01:23:54 PM PDT 24
Finished May 12 01:23:56 PM PDT 24
Peak memory 209376 kb
Host smart-bdc3a71e-4e74-4f5c-a7f3-a2118e20b697
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354563142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2354563142
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1083434614
Short name T878
Test name
Test status
Simulation time 93021298 ps
CPU time 1.65 seconds
Started May 12 01:23:55 PM PDT 24
Finished May 12 01:23:57 PM PDT 24
Peak memory 209152 kb
Host smart-a765b7ee-8d70-4b7a-919a-718ee5c0d7dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083434614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1083434614
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1287670374
Short name T959
Test name
Test status
Simulation time 28334832 ps
CPU time 1.03 seconds
Started May 12 01:24:01 PM PDT 24
Finished May 12 01:24:03 PM PDT 24
Peak memory 209580 kb
Host smart-0e7177ec-8df1-464a-96c3-75aa704186ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287670374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1287670374
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3134776111
Short name T961
Test name
Test status
Simulation time 26536568 ps
CPU time 1.66 seconds
Started May 12 01:23:55 PM PDT 24
Finished May 12 01:23:57 PM PDT 24
Peak memory 224164 kb
Host smart-a7243d0f-7f16-4c92-9c74-325568417a6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134776111 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3134776111
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3304991431
Short name T102
Test name
Test status
Simulation time 16730817 ps
CPU time 1.18 seconds
Started May 12 01:23:56 PM PDT 24
Finished May 12 01:23:58 PM PDT 24
Peak memory 209128 kb
Host smart-33dc8730-e33c-4189-a987-1b4c6f67c746
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304991431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3304991431
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3232432285
Short name T882
Test name
Test status
Simulation time 83146064 ps
CPU time 1.17 seconds
Started May 12 01:23:56 PM PDT 24
Finished May 12 01:23:57 PM PDT 24
Peak memory 209036 kb
Host smart-ba7ad0b9-c8ac-4f8e-ad78-332582bf0f12
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232432285 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3232432285
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2355982347
Short name T983
Test name
Test status
Simulation time 4072229357 ps
CPU time 3.28 seconds
Started May 12 01:23:55 PM PDT 24
Finished May 12 01:23:59 PM PDT 24
Peak memory 207840 kb
Host smart-979b3d92-23bd-4410-83fb-a84a74f9e0d9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355982347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2355982347
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3696569748
Short name T907
Test name
Test status
Simulation time 9672766620 ps
CPU time 10.55 seconds
Started May 12 01:23:56 PM PDT 24
Finished May 12 01:24:07 PM PDT 24
Peak memory 208384 kb
Host smart-5255bc38-f5a6-41f6-ac4a-441bca23d034
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696569748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3696569748
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3021292900
Short name T946
Test name
Test status
Simulation time 120036156 ps
CPU time 2.07 seconds
Started May 12 01:24:04 PM PDT 24
Finished May 12 01:24:07 PM PDT 24
Peak memory 210556 kb
Host smart-ec0ba237-40f3-40e2-a832-e512eeb3960a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021292900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3021292900
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1500826362
Short name T957
Test name
Test status
Simulation time 93105847 ps
CPU time 2.93 seconds
Started May 12 01:23:56 PM PDT 24
Finished May 12 01:23:59 PM PDT 24
Peak memory 217496 kb
Host smart-468b5ec1-5fe8-4de4-bac3-f8c085e84421
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150082
6362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1500826362
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1940719254
Short name T998
Test name
Test status
Simulation time 207325485 ps
CPU time 3.05 seconds
Started May 12 01:24:04 PM PDT 24
Finished May 12 01:24:08 PM PDT 24
Peak memory 209332 kb
Host smart-bb35d7ef-3a39-4d73-81aa-ee5b18ef6ba8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940719254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1940719254
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3879721640
Short name T125
Test name
Test status
Simulation time 26181195 ps
CPU time 1.28 seconds
Started May 12 01:23:57 PM PDT 24
Finished May 12 01:24:00 PM PDT 24
Peak memory 209168 kb
Host smart-ea004e76-b15b-46d6-9204-eb126b2fd35c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879721640 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3879721640
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1331792325
Short name T929
Test name
Test status
Simulation time 193286582 ps
CPU time 1.5 seconds
Started May 12 01:23:55 PM PDT 24
Finished May 12 01:23:57 PM PDT 24
Peak memory 211224 kb
Host smart-caa69f32-cb1b-40cb-97c7-8d8aaf96ee75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331792325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1331792325
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.186572343
Short name T942
Test name
Test status
Simulation time 83248756 ps
CPU time 3.47 seconds
Started May 12 01:24:04 PM PDT 24
Finished May 12 01:24:09 PM PDT 24
Peak memory 217604 kb
Host smart-16b61197-e6f1-47d5-adcb-0bb310d0ac23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186572343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.186572343
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3214435405
Short name T891
Test name
Test status
Simulation time 28140340 ps
CPU time 1.3 seconds
Started May 12 01:23:59 PM PDT 24
Finished May 12 01:24:01 PM PDT 24
Peak memory 218916 kb
Host smart-f3ad18ad-d087-422a-9de6-21ccb6b798d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214435405 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3214435405
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1824341430
Short name T931
Test name
Test status
Simulation time 56809131 ps
CPU time 0.94 seconds
Started May 12 01:23:58 PM PDT 24
Finished May 12 01:24:00 PM PDT 24
Peak memory 209156 kb
Host smart-af282a15-6ece-47b2-84d4-f9e6736f406c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824341430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1824341430
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3216479151
Short name T877
Test name
Test status
Simulation time 58840024 ps
CPU time 0.96 seconds
Started May 12 01:23:58 PM PDT 24
Finished May 12 01:24:00 PM PDT 24
Peak memory 208968 kb
Host smart-e4f4f56b-f7c3-4808-9bb2-6eb0bf165abd
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216479151 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3216479151
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3685765593
Short name T126
Test name
Test status
Simulation time 570716271 ps
CPU time 12.87 seconds
Started May 12 01:23:58 PM PDT 24
Finished May 12 01:24:11 PM PDT 24
Peak memory 208908 kb
Host smart-973dea88-1924-45fe-9de1-d3108dd3bd66
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685765593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3685765593
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2361683113
Short name T899
Test name
Test status
Simulation time 7164895958 ps
CPU time 15.5 seconds
Started May 12 01:24:04 PM PDT 24
Finished May 12 01:24:21 PM PDT 24
Peak memory 209336 kb
Host smart-7ed5f91d-389d-45c0-9387-a8e1d6481eb7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361683113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2361683113
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4216937940
Short name T932
Test name
Test status
Simulation time 170994934 ps
CPU time 1.61 seconds
Started May 12 01:23:53 PM PDT 24
Finished May 12 01:23:55 PM PDT 24
Peak memory 210880 kb
Host smart-661f0ab3-bdb5-4c2a-843e-89d1352c5b3a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216937940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.4216937940
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1509152628
Short name T920
Test name
Test status
Simulation time 496297357 ps
CPU time 1.65 seconds
Started May 12 01:23:58 PM PDT 24
Finished May 12 01:24:00 PM PDT 24
Peak memory 217652 kb
Host smart-283da0be-571b-4a79-945b-e1e862819797
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150915
2628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1509152628
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1988727313
Short name T890
Test name
Test status
Simulation time 198013280 ps
CPU time 1.36 seconds
Started May 12 01:23:57 PM PDT 24
Finished May 12 01:23:59 PM PDT 24
Peak memory 209060 kb
Host smart-4eb0a7a0-67b1-45d9-aa9e-de49bebb805d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988727313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1988727313
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.622892931
Short name T960
Test name
Test status
Simulation time 276573470 ps
CPU time 1.3 seconds
Started May 12 01:23:59 PM PDT 24
Finished May 12 01:24:01 PM PDT 24
Peak memory 209140 kb
Host smart-a55e562e-4760-4a5b-80c2-7917f3d2aad7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622892931 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.622892931
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.3932551239
Short name T201
Test name
Test status
Simulation time 66695609 ps
CPU time 1.38 seconds
Started May 12 01:24:00 PM PDT 24
Finished May 12 01:24:02 PM PDT 24
Peak memory 209244 kb
Host smart-f0a2492d-3b7f-44b4-ae8c-b116ce4f3e6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932551239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.3932551239
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1398330235
Short name T894
Test name
Test status
Simulation time 98794531 ps
CPU time 1.87 seconds
Started May 12 01:23:57 PM PDT 24
Finished May 12 01:24:00 PM PDT 24
Peak memory 217508 kb
Host smart-ad0f2b64-1572-432a-87c7-58801c327a3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398330235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1398330235
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2659853543
Short name T892
Test name
Test status
Simulation time 61419759 ps
CPU time 1.17 seconds
Started May 12 01:24:05 PM PDT 24
Finished May 12 01:24:07 PM PDT 24
Peak memory 217496 kb
Host smart-f9659e00-2340-42bb-a640-f0aa7db9c649
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659853543 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2659853543
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1072049946
Short name T188
Test name
Test status
Simulation time 46143738 ps
CPU time 0.99 seconds
Started May 12 01:24:10 PM PDT 24
Finished May 12 01:24:12 PM PDT 24
Peak memory 209192 kb
Host smart-d49db26e-d9d6-4a76-9aa8-c846eb82838f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072049946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1072049946
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2286685831
Short name T996
Test name
Test status
Simulation time 65703528 ps
CPU time 1.1 seconds
Started May 12 01:24:05 PM PDT 24
Finished May 12 01:24:07 PM PDT 24
Peak memory 209148 kb
Host smart-1bc441a1-34a7-4627-aea1-4c151c92be79
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286685831 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.2286685831
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.143460400
Short name T928
Test name
Test status
Simulation time 1266356089 ps
CPU time 8.51 seconds
Started May 12 01:23:59 PM PDT 24
Finished May 12 01:24:08 PM PDT 24
Peak memory 208936 kb
Host smart-530d528a-6338-45ee-9b38-1fad8a3d893f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143460400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.143460400
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2338644293
Short name T982
Test name
Test status
Simulation time 548637190 ps
CPU time 12.95 seconds
Started May 12 01:23:59 PM PDT 24
Finished May 12 01:24:13 PM PDT 24
Peak memory 208908 kb
Host smart-8b50575e-1daa-4470-a608-70bc8fc94dde
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338644293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2338644293
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.257867123
Short name T974
Test name
Test status
Simulation time 122376726 ps
CPU time 3.33 seconds
Started May 12 01:24:00 PM PDT 24
Finished May 12 01:24:04 PM PDT 24
Peak memory 210320 kb
Host smart-3d2559d2-a196-4ba1-a1a5-e59141461c7c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257867123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.257867123
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.55565082
Short name T905
Test name
Test status
Simulation time 71157984 ps
CPU time 1.47 seconds
Started May 12 01:24:17 PM PDT 24
Finished May 12 01:24:19 PM PDT 24
Peak memory 220268 kb
Host smart-55e7862c-24b7-4ca0-a058-df95eb6094e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555650
82 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.55565082
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1810242253
Short name T990
Test name
Test status
Simulation time 81173531 ps
CPU time 1.08 seconds
Started May 12 01:23:59 PM PDT 24
Finished May 12 01:24:00 PM PDT 24
Peak memory 209068 kb
Host smart-5ca8e519-5af4-46c7-8317-e511ad7f5195
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810242253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1810242253
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.443302097
Short name T200
Test name
Test status
Simulation time 42802756 ps
CPU time 1 seconds
Started May 12 01:24:00 PM PDT 24
Finished May 12 01:24:01 PM PDT 24
Peak memory 209084 kb
Host smart-8421e28c-c8ff-42e9-a7b5-30c5888da1b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443302097 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.443302097
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.1062493722
Short name T988
Test name
Test status
Simulation time 25044155 ps
CPU time 1.08 seconds
Started May 12 01:24:19 PM PDT 24
Finished May 12 01:24:20 PM PDT 24
Peak memory 209192 kb
Host smart-a0487ac8-a8e2-4e5a-909e-418e5c521b92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062493722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.1062493722
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.160786329
Short name T911
Test name
Test status
Simulation time 81678014 ps
CPU time 2.41 seconds
Started May 12 01:24:07 PM PDT 24
Finished May 12 01:24:09 PM PDT 24
Peak memory 217480 kb
Host smart-151d794d-0df1-4fe0-8d56-668271890c82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160786329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.160786329
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3688746911
Short name T99
Test name
Test status
Simulation time 72135994 ps
CPU time 2.85 seconds
Started May 12 01:24:04 PM PDT 24
Finished May 12 01:24:08 PM PDT 24
Peak memory 222228 kb
Host smart-95cb73df-a44e-4095-a271-d3fdcc0362f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688746911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3688746911
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2482146085
Short name T950
Test name
Test status
Simulation time 38131374 ps
CPU time 1.58 seconds
Started May 12 01:24:02 PM PDT 24
Finished May 12 01:24:04 PM PDT 24
Peak memory 219480 kb
Host smart-fc41153b-723b-44bb-864d-4010d5847fc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482146085 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2482146085
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.3500361310
Short name T181
Test name
Test status
Simulation time 16533192 ps
CPU time 1.11 seconds
Started May 12 01:24:03 PM PDT 24
Finished May 12 01:24:05 PM PDT 24
Peak memory 209064 kb
Host smart-74299a19-802a-496e-91cb-b6a7163ced47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500361310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.3500361310
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2203760409
Short name T969
Test name
Test status
Simulation time 39008060 ps
CPU time 1.14 seconds
Started May 12 01:24:05 PM PDT 24
Finished May 12 01:24:07 PM PDT 24
Peak memory 208996 kb
Host smart-56075c3c-2aea-4101-9548-5a355c1c5d0a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203760409 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2203760409
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.249170292
Short name T970
Test name
Test status
Simulation time 1085301122 ps
CPU time 23.08 seconds
Started May 12 01:24:03 PM PDT 24
Finished May 12 01:24:26 PM PDT 24
Peak memory 208952 kb
Host smart-93793924-b105-4341-900e-ee7551bc2c81
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249170292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.249170292
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2729804976
Short name T924
Test name
Test status
Simulation time 6384360783 ps
CPU time 21.56 seconds
Started May 12 01:24:04 PM PDT 24
Finished May 12 01:24:26 PM PDT 24
Peak memory 209064 kb
Host smart-6cced352-4b3c-458b-9c23-15c3c253f81f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729804976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2729804976
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.226115389
Short name T975
Test name
Test status
Simulation time 403923703 ps
CPU time 1.88 seconds
Started May 12 01:24:04 PM PDT 24
Finished May 12 01:24:06 PM PDT 24
Peak memory 210492 kb
Host smart-92ce859f-27ea-4988-827d-65618eeedccf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226115389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.226115389
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2440802691
Short name T934
Test name
Test status
Simulation time 748626331 ps
CPU time 3.8 seconds
Started May 12 01:24:19 PM PDT 24
Finished May 12 01:24:23 PM PDT 24
Peak memory 218384 kb
Host smart-8b111052-9527-427d-b88b-62449c3d39af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244080
2691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2440802691
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2894663284
Short name T926
Test name
Test status
Simulation time 188771810 ps
CPU time 1.27 seconds
Started May 12 01:24:06 PM PDT 24
Finished May 12 01:24:08 PM PDT 24
Peak memory 209088 kb
Host smart-1c5725fa-4428-4620-8806-dd9785be8563
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894663284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2894663284
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3742405005
Short name T984
Test name
Test status
Simulation time 54076046 ps
CPU time 1.07 seconds
Started May 12 01:24:19 PM PDT 24
Finished May 12 01:24:20 PM PDT 24
Peak memory 209028 kb
Host smart-cbe6bd26-fe58-4105-aebb-11938e300ddd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742405005 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3742405005
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.788682332
Short name T944
Test name
Test status
Simulation time 25986140 ps
CPU time 1.01 seconds
Started May 12 01:24:04 PM PDT 24
Finished May 12 01:24:06 PM PDT 24
Peak memory 209112 kb
Host smart-ae789a03-f2c3-473f-ba65-2e5a6d8197af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788682332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
same_csr_outstanding.788682332
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.629074235
Short name T937
Test name
Test status
Simulation time 112064355 ps
CPU time 3.62 seconds
Started May 12 01:24:04 PM PDT 24
Finished May 12 01:24:08 PM PDT 24
Peak memory 217392 kb
Host smart-e4b41a83-3be6-436f-9b26-7d2461f3ee52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629074235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.629074235
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3661970585
Short name T945
Test name
Test status
Simulation time 141179265 ps
CPU time 2.58 seconds
Started May 12 01:24:02 PM PDT 24
Finished May 12 01:24:05 PM PDT 24
Peak memory 217276 kb
Host smart-0fbb66de-788a-4810-9d0f-4bab8cbec8d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661970585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.3661970585
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.344945709
Short name T915
Test name
Test status
Simulation time 26239427 ps
CPU time 1.66 seconds
Started May 12 01:24:05 PM PDT 24
Finished May 12 01:24:08 PM PDT 24
Peak memory 217676 kb
Host smart-af49c7bd-6207-4819-9683-ab5eeb34d5f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344945709 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.344945709
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2937928713
Short name T953
Test name
Test status
Simulation time 14749319 ps
CPU time 0.85 seconds
Started May 12 01:24:03 PM PDT 24
Finished May 12 01:24:05 PM PDT 24
Peak memory 208444 kb
Host smart-11027a89-2129-4f68-935d-a95594e1be4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937928713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2937928713
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.3043369463
Short name T913
Test name
Test status
Simulation time 83062066 ps
CPU time 1.15 seconds
Started May 12 01:24:05 PM PDT 24
Finished May 12 01:24:07 PM PDT 24
Peak memory 209004 kb
Host smart-7938572b-6e1d-4549-8df2-8b8111e5f984
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043369463 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.3043369463
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1665066306
Short name T963
Test name
Test status
Simulation time 958613967 ps
CPU time 6.07 seconds
Started May 12 01:24:18 PM PDT 24
Finished May 12 01:24:24 PM PDT 24
Peak memory 208920 kb
Host smart-573890c4-5c96-49bd-8925-690d1f38df45
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665066306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1665066306
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3167634374
Short name T949
Test name
Test status
Simulation time 5460481024 ps
CPU time 27.69 seconds
Started May 12 01:24:17 PM PDT 24
Finished May 12 01:24:45 PM PDT 24
Peak memory 209080 kb
Host smart-0eb93dc9-5b68-4f8a-8a62-4db4f9f18894
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167634374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3167634374
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.4185988307
Short name T903
Test name
Test status
Simulation time 353325362 ps
CPU time 4.73 seconds
Started May 12 01:24:04 PM PDT 24
Finished May 12 01:24:09 PM PDT 24
Peak memory 210740 kb
Host smart-f4878d43-3468-4118-87aa-9e39e3465dfa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185988307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.4185988307
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.205284867
Short name T916
Test name
Test status
Simulation time 140914387 ps
CPU time 1.32 seconds
Started May 12 01:24:05 PM PDT 24
Finished May 12 01:24:08 PM PDT 24
Peak memory 209068 kb
Host smart-2491f9b7-d3cd-4929-9919-88ddcdf939a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205284867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.205284867
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.854152679
Short name T940
Test name
Test status
Simulation time 76631880 ps
CPU time 1.26 seconds
Started May 12 01:24:06 PM PDT 24
Finished May 12 01:24:08 PM PDT 24
Peak memory 217364 kb
Host smart-c4731105-9ada-4608-8d16-faabd9323764
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854152679 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.854152679
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3966031512
Short name T972
Test name
Test status
Simulation time 20602273 ps
CPU time 1.54 seconds
Started May 12 01:24:03 PM PDT 24
Finished May 12 01:24:05 PM PDT 24
Peak memory 217364 kb
Host smart-b2397859-dba9-4cc4-a816-283be8b952f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966031512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.3966031512
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3433698585
Short name T109
Test name
Test status
Simulation time 1049589993 ps
CPU time 5.26 seconds
Started May 12 01:24:04 PM PDT 24
Finished May 12 01:24:10 PM PDT 24
Peak memory 217356 kb
Host smart-cc3384b1-5c75-421c-be75-69ce862b96af
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433698585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3433698585
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.726957011
Short name T964
Test name
Test status
Simulation time 51309794 ps
CPU time 1.15 seconds
Started May 12 01:24:06 PM PDT 24
Finished May 12 01:24:08 PM PDT 24
Peak memory 217576 kb
Host smart-33963a06-ca35-4634-ac1f-94c602481cf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726957011 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.726957011
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.545317582
Short name T196
Test name
Test status
Simulation time 49246308 ps
CPU time 0.86 seconds
Started May 12 01:24:18 PM PDT 24
Finished May 12 01:24:19 PM PDT 24
Peak memory 209200 kb
Host smart-a7f5eedc-49b0-4bba-a3f2-cf0395ceb7a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545317582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.545317582
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.894369735
Short name T987
Test name
Test status
Simulation time 60274183 ps
CPU time 1.42 seconds
Started May 12 01:24:05 PM PDT 24
Finished May 12 01:24:07 PM PDT 24
Peak memory 207740 kb
Host smart-b98ec79e-ee18-48de-a76d-a78f5de49154
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894369735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.894369735
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3345631148
Short name T106
Test name
Test status
Simulation time 2698923714 ps
CPU time 4.74 seconds
Started May 12 01:24:05 PM PDT 24
Finished May 12 01:24:11 PM PDT 24
Peak memory 209184 kb
Host smart-f62b932e-2f33-4dfe-9827-d6896f8c71a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345631148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3345631148
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2300914462
Short name T939
Test name
Test status
Simulation time 4143329200 ps
CPU time 30.46 seconds
Started May 12 01:24:06 PM PDT 24
Finished May 12 01:24:37 PM PDT 24
Peak memory 209100 kb
Host smart-43da9d3a-ae5e-4b3e-bb8b-b4dae3d818ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300914462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2300914462
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.983532513
Short name T993
Test name
Test status
Simulation time 156122839 ps
CPU time 3.57 seconds
Started May 12 01:24:17 PM PDT 24
Finished May 12 01:24:21 PM PDT 24
Peak memory 209160 kb
Host smart-54ffb24f-8abe-4da5-bc51-cf236bf20099
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983532513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.983532513
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3081633316
Short name T887
Test name
Test status
Simulation time 422153393 ps
CPU time 2.07 seconds
Started May 12 01:24:07 PM PDT 24
Finished May 12 01:24:10 PM PDT 24
Peak memory 218496 kb
Host smart-5ea48600-3f0f-4766-9ee6-a93bb83c76c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308163
3316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3081633316
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3382542692
Short name T989
Test name
Test status
Simulation time 177726732 ps
CPU time 1.11 seconds
Started May 12 01:24:06 PM PDT 24
Finished May 12 01:24:08 PM PDT 24
Peak memory 209088 kb
Host smart-b22e8261-325c-4b2c-ae05-231fbd078181
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382542692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3382542692
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3673479219
Short name T195
Test name
Test status
Simulation time 55602092 ps
CPU time 0.96 seconds
Started May 12 01:24:04 PM PDT 24
Finished May 12 01:24:06 PM PDT 24
Peak memory 209172 kb
Host smart-fa48387d-8715-487a-9499-bb4b0cfd1a8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673479219 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3673479219
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1007400533
Short name T952
Test name
Test status
Simulation time 26383013 ps
CPU time 1.31 seconds
Started May 12 01:24:18 PM PDT 24
Finished May 12 01:24:20 PM PDT 24
Peak memory 209200 kb
Host smart-39a546da-1308-4def-8a97-3f133440deb9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007400533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.1007400533
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4020376751
Short name T98
Test name
Test status
Simulation time 531342311 ps
CPU time 2.4 seconds
Started May 12 01:24:05 PM PDT 24
Finished May 12 01:24:09 PM PDT 24
Peak memory 217688 kb
Host smart-4b950725-3595-46f2-ad2e-fc2eeda64214
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020376751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.4020376751
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2555452751
Short name T579
Test name
Test status
Simulation time 19712489 ps
CPU time 1.1 seconds
Started May 12 01:30:32 PM PDT 24
Finished May 12 01:30:34 PM PDT 24
Peak memory 209564 kb
Host smart-c6d9a582-ddeb-4ec2-afce-a049b753de56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555452751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2555452751
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3501909680
Short name T64
Test name
Test status
Simulation time 31304441 ps
CPU time 0.78 seconds
Started May 12 01:30:27 PM PDT 24
Finished May 12 01:30:29 PM PDT 24
Peak memory 209272 kb
Host smart-ae5f51cc-67d0-4f0e-8b50-1d982dd3ccd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501909680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3501909680
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.335332721
Short name T163
Test name
Test status
Simulation time 1941092132 ps
CPU time 7.54 seconds
Started May 12 01:30:27 PM PDT 24
Finished May 12 01:30:34 PM PDT 24
Peak memory 218004 kb
Host smart-1ec0c20a-17c0-4627-a46b-7a116541b3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335332721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.335332721
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2253202259
Short name T686
Test name
Test status
Simulation time 987880218 ps
CPU time 30.85 seconds
Started May 12 01:30:27 PM PDT 24
Finished May 12 01:30:58 PM PDT 24
Peak memory 218068 kb
Host smart-c2fa6aaa-835a-415e-a067-5367b1d0101a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253202259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2253202259
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.741438100
Short name T158
Test name
Test status
Simulation time 917421672 ps
CPU time 2.69 seconds
Started May 12 01:30:29 PM PDT 24
Finished May 12 01:30:32 PM PDT 24
Peak memory 217840 kb
Host smart-03749abb-8f56-48cb-acda-065a62100e9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741438100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.741438100
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3412729501
Short name T368
Test name
Test status
Simulation time 1170415964 ps
CPU time 9.16 seconds
Started May 12 01:30:26 PM PDT 24
Finished May 12 01:30:35 PM PDT 24
Peak memory 218104 kb
Host smart-4eb3307d-8913-447c-9787-0673c1860175
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412729501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3412729501
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.905335079
Short name T796
Test name
Test status
Simulation time 5849335489 ps
CPU time 18.36 seconds
Started May 12 01:30:29 PM PDT 24
Finished May 12 01:30:48 PM PDT 24
Peak memory 214072 kb
Host smart-e5307957-34f8-4408-8c95-dd0134e14f03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905335079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.905335079
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.3487861443
Short name T610
Test name
Test status
Simulation time 584035191 ps
CPU time 15.88 seconds
Started May 12 01:30:27 PM PDT 24
Finished May 12 01:30:44 PM PDT 24
Peak memory 213912 kb
Host smart-b0a9179b-96c3-44ae-819b-194640037d11
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487861443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
3487861443
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.721724355
Short name T830
Test name
Test status
Simulation time 15770962642 ps
CPU time 117.25 seconds
Started May 12 01:30:27 PM PDT 24
Finished May 12 01:32:25 PM PDT 24
Peak memory 275648 kb
Host smart-049bbff4-2ddd-4fd1-8831-bc89c0752e3d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721724355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_state_failure.721724355
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.2433868724
Short name T266
Test name
Test status
Simulation time 1161080820 ps
CPU time 35.04 seconds
Started May 12 01:30:26 PM PDT 24
Finished May 12 01:31:01 PM PDT 24
Peak memory 250952 kb
Host smart-4435a2f3-f9e8-40ee-8986-614af5453aa6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433868724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.2433868724
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1158370188
Short name T395
Test name
Test status
Simulation time 328341260 ps
CPU time 3.99 seconds
Started May 12 01:30:25 PM PDT 24
Finished May 12 01:30:30 PM PDT 24
Peak memory 218004 kb
Host smart-77d10733-dd0a-430a-acd9-a6b5b8c0988e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158370188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1158370188
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2913811576
Short name T177
Test name
Test status
Simulation time 2181259843 ps
CPU time 19.86 seconds
Started May 12 01:30:27 PM PDT 24
Finished May 12 01:30:48 PM PDT 24
Peak memory 218152 kb
Host smart-62c9cac5-4982-4640-9d09-fd6a75191272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913811576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2913811576
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2865117473
Short name T83
Test name
Test status
Simulation time 689598787 ps
CPU time 34.67 seconds
Started May 12 01:30:30 PM PDT 24
Finished May 12 01:31:05 PM PDT 24
Peak memory 270652 kb
Host smart-53d277c2-e976-4f6f-89ed-9b66d6cab283
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865117473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2865117473
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1129074081
Short name T646
Test name
Test status
Simulation time 1094941919 ps
CPU time 14.72 seconds
Started May 12 01:30:29 PM PDT 24
Finished May 12 01:30:44 PM PDT 24
Peak memory 225752 kb
Host smart-b5f15eda-9107-461a-bcd6-f3adc50277d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129074081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1129074081
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3504482939
Short name T649
Test name
Test status
Simulation time 1660554315 ps
CPU time 9.44 seconds
Started May 12 01:30:28 PM PDT 24
Finished May 12 01:30:38 PM PDT 24
Peak memory 217976 kb
Host smart-d237b38a-ca1a-41d3-b158-6d137be9cdea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504482939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3504482939
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3157056058
Short name T857
Test name
Test status
Simulation time 1390678100 ps
CPU time 15.85 seconds
Started May 12 01:30:32 PM PDT 24
Finished May 12 01:30:48 PM PDT 24
Peak memory 218072 kb
Host smart-225b5887-887a-471e-8a67-38000e12bb3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157056058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
157056058
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3809202631
Short name T575
Test name
Test status
Simulation time 2343540938 ps
CPU time 11.29 seconds
Started May 12 01:30:25 PM PDT 24
Finished May 12 01:30:37 PM PDT 24
Peak memory 218120 kb
Host smart-7a519991-166b-4f99-98c3-c15219eec2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809202631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3809202631
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2607050650
Short name T283
Test name
Test status
Simulation time 123292993 ps
CPU time 2.5 seconds
Started May 12 01:30:22 PM PDT 24
Finished May 12 01:30:27 PM PDT 24
Peak memory 214340 kb
Host smart-9d21a4ce-f902-46ac-8e1c-3fcc258aae25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607050650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2607050650
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1059721783
Short name T290
Test name
Test status
Simulation time 239014520 ps
CPU time 32.3 seconds
Started May 12 01:30:22 PM PDT 24
Finished May 12 01:30:56 PM PDT 24
Peak memory 250748 kb
Host smart-2080197e-9941-4aaf-b364-5d15312ef000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059721783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1059721783
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3943467588
Short name T219
Test name
Test status
Simulation time 45094980 ps
CPU time 5.47 seconds
Started May 12 01:30:24 PM PDT 24
Finished May 12 01:30:31 PM PDT 24
Peak memory 246508 kb
Host smart-48ed4f4e-507c-4980-a4e4-3c67ce0ef084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943467588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3943467588
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.4183454136
Short name T700
Test name
Test status
Simulation time 150151959243 ps
CPU time 338.19 seconds
Started May 12 01:30:32 PM PDT 24
Finished May 12 01:36:11 PM PDT 24
Peak memory 250836 kb
Host smart-c4f5ad2d-d0aa-4b0e-b59b-c4c9edab04ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183454136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.4183454136
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2865468331
Short name T757
Test name
Test status
Simulation time 67064756 ps
CPU time 0.88 seconds
Started May 12 01:30:23 PM PDT 24
Finished May 12 01:30:25 PM PDT 24
Peak memory 212892 kb
Host smart-10ff7c6d-69ed-49ce-a5bd-1fa514251f0c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865468331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2865468331
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.554717649
Short name T657
Test name
Test status
Simulation time 43511080 ps
CPU time 1.34 seconds
Started May 12 01:30:37 PM PDT 24
Finished May 12 01:30:39 PM PDT 24
Peak memory 209468 kb
Host smart-96832191-8501-4b71-b4f0-d093aa22b556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554717649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.554717649
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3972235714
Short name T477
Test name
Test status
Simulation time 1806372051 ps
CPU time 20.67 seconds
Started May 12 01:30:32 PM PDT 24
Finished May 12 01:30:53 PM PDT 24
Peak memory 217952 kb
Host smart-04b0ac76-1745-45d2-bd6b-7ece8b9800cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972235714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3972235714
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.857444010
Short name T659
Test name
Test status
Simulation time 620956156 ps
CPU time 3.95 seconds
Started May 12 01:30:33 PM PDT 24
Finished May 12 01:30:37 PM PDT 24
Peak memory 217100 kb
Host smart-f0dc3e10-9d39-4ed3-b0dc-eb5074767ceb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857444010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.857444010
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.3497259039
Short name T647
Test name
Test status
Simulation time 1627261762 ps
CPU time 26.43 seconds
Started May 12 01:30:34 PM PDT 24
Finished May 12 01:31:01 PM PDT 24
Peak memory 217972 kb
Host smart-9fd4bac0-a844-4a08-90db-a36477b4f8d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497259039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.3497259039
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2888101915
Short name T679
Test name
Test status
Simulation time 318920903 ps
CPU time 4.5 seconds
Started May 12 01:30:34 PM PDT 24
Finished May 12 01:30:39 PM PDT 24
Peak memory 217212 kb
Host smart-df1f2946-789f-43e1-ad58-89ad8d054537
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888101915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
888101915
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2493822978
Short name T797
Test name
Test status
Simulation time 224187508 ps
CPU time 3.97 seconds
Started May 12 01:30:32 PM PDT 24
Finished May 12 01:30:37 PM PDT 24
Peak memory 218000 kb
Host smart-06f1b940-d64a-4ca2-9c99-0460a302bab7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493822978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2493822978
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.953757445
Short name T303
Test name
Test status
Simulation time 6443199494 ps
CPU time 23.52 seconds
Started May 12 01:30:33 PM PDT 24
Finished May 12 01:30:57 PM PDT 24
Peak memory 213944 kb
Host smart-c44c9586-41e0-4cfa-82c5-2f73de41cfde
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953757445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_regwen_during_op.953757445
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3645440720
Short name T770
Test name
Test status
Simulation time 1541704805 ps
CPU time 5.9 seconds
Started May 12 01:30:29 PM PDT 24
Finished May 12 01:30:36 PM PDT 24
Peak memory 213640 kb
Host smart-c59c43de-f1a6-459c-acb9-0e153774d5b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645440720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3645440720
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2084255803
Short name T323
Test name
Test status
Simulation time 5070774954 ps
CPU time 49.48 seconds
Started May 12 01:30:32 PM PDT 24
Finished May 12 01:31:22 PM PDT 24
Peak memory 269292 kb
Host smart-19191d9f-a2c5-4861-8094-025da4302480
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084255803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2084255803
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.683479563
Short name T349
Test name
Test status
Simulation time 66165023 ps
CPU time 1.91 seconds
Started May 12 01:30:32 PM PDT 24
Finished May 12 01:30:34 PM PDT 24
Peak memory 218056 kb
Host smart-dceb3510-592c-4d97-939d-ff3bc7c5608e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683479563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.683479563
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.31580735
Short name T178
Test name
Test status
Simulation time 1195684175 ps
CPU time 26.32 seconds
Started May 12 01:30:32 PM PDT 24
Finished May 12 01:30:59 PM PDT 24
Peak memory 214596 kb
Host smart-ac2567d8-c398-4dbe-8a60-a48c3d5e80d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31580735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.31580735
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.4270869256
Short name T46
Test name
Test status
Simulation time 963237583 ps
CPU time 31.97 seconds
Started May 12 01:30:37 PM PDT 24
Finished May 12 01:31:10 PM PDT 24
Peak memory 284556 kb
Host smart-8629ad32-0a4f-484e-aab7-4d4d7a14e4fd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270869256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.4270869256
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.155323710
Short name T450
Test name
Test status
Simulation time 256642927 ps
CPU time 8.85 seconds
Started May 12 01:30:33 PM PDT 24
Finished May 12 01:30:42 PM PDT 24
Peak memory 218032 kb
Host smart-a49d990e-b27d-44bb-bf47-808fece5347b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155323710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.155323710
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2837864229
Short name T557
Test name
Test status
Simulation time 198416458 ps
CPU time 8.59 seconds
Started May 12 01:30:34 PM PDT 24
Finished May 12 01:30:43 PM PDT 24
Peak memory 217968 kb
Host smart-26598c41-276f-4fdf-8b86-b010005bd6de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837864229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
837864229
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2129186196
Short name T352
Test name
Test status
Simulation time 267453224 ps
CPU time 11.21 seconds
Started May 12 01:30:30 PM PDT 24
Finished May 12 01:30:42 PM PDT 24
Peak memory 218004 kb
Host smart-0dcd8a68-a215-47aa-b7d3-941ec926fbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129186196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2129186196
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.229084910
Short name T73
Test name
Test status
Simulation time 103768414 ps
CPU time 5.79 seconds
Started May 12 01:30:32 PM PDT 24
Finished May 12 01:30:38 PM PDT 24
Peak memory 214196 kb
Host smart-891eafd2-5ca2-4fe7-872e-c6a1e5f9c193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229084910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.229084910
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.159300290
Short name T422
Test name
Test status
Simulation time 787893573 ps
CPU time 20.26 seconds
Started May 12 01:30:30 PM PDT 24
Finished May 12 01:30:50 PM PDT 24
Peak memory 245104 kb
Host smart-1a2af515-ded9-4825-8c33-6d9280012abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159300290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.159300290
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3027765632
Short name T90
Test name
Test status
Simulation time 105441789 ps
CPU time 3.38 seconds
Started May 12 01:30:30 PM PDT 24
Finished May 12 01:30:34 PM PDT 24
Peak memory 226404 kb
Host smart-14064e59-4331-4aaf-82ad-04c1e5f47206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027765632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3027765632
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2825329176
Short name T562
Test name
Test status
Simulation time 12206062752 ps
CPU time 60.67 seconds
Started May 12 01:30:33 PM PDT 24
Finished May 12 01:31:34 PM PDT 24
Peak memory 259192 kb
Host smart-185513e5-8aae-4087-b0e6-7170219e3401
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825329176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2825329176
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2384818919
Short name T155
Test name
Test status
Simulation time 20504385 ps
CPU time 0.96 seconds
Started May 12 01:30:30 PM PDT 24
Finished May 12 01:30:31 PM PDT 24
Peak memory 211620 kb
Host smart-4c3cb290-2030-4c19-9b0a-3a13fc458ba7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384818919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2384818919
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3946033599
Short name T256
Test name
Test status
Simulation time 31655755 ps
CPU time 0.97 seconds
Started May 12 01:31:26 PM PDT 24
Finished May 12 01:31:27 PM PDT 24
Peak memory 209532 kb
Host smart-aff16030-d180-4499-bcba-93a81670fd15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946033599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3946033599
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.727632105
Short name T761
Test name
Test status
Simulation time 507990996 ps
CPU time 12.8 seconds
Started May 12 01:31:14 PM PDT 24
Finished May 12 01:31:28 PM PDT 24
Peak memory 218000 kb
Host smart-cbd7eadd-cfc7-422a-bca7-6740ea5e4b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727632105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.727632105
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.2316883383
Short name T685
Test name
Test status
Simulation time 988988300 ps
CPU time 2.92 seconds
Started May 12 01:31:13 PM PDT 24
Finished May 12 01:31:16 PM PDT 24
Peak memory 209660 kb
Host smart-e6d68618-4edf-49f4-a560-15dac9bdd673
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316883383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.2316883383
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1743691201
Short name T428
Test name
Test status
Simulation time 8467019835 ps
CPU time 31.16 seconds
Started May 12 01:31:16 PM PDT 24
Finished May 12 01:31:48 PM PDT 24
Peak memory 218252 kb
Host smart-996b77f5-1697-4ad5-8455-f87caa01497b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743691201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1743691201
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1233558584
Short name T268
Test name
Test status
Simulation time 172523853 ps
CPU time 3.37 seconds
Started May 12 01:31:13 PM PDT 24
Finished May 12 01:31:17 PM PDT 24
Peak memory 218012 kb
Host smart-25592795-4f5b-4359-b864-bcdc3d74c67b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233558584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1233558584
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.3371453521
Short name T162
Test name
Test status
Simulation time 384921805 ps
CPU time 10.79 seconds
Started May 12 01:31:11 PM PDT 24
Finished May 12 01:31:22 PM PDT 24
Peak memory 213764 kb
Host smart-60e0059a-54ab-4770-bc39-17b64332d95b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371453521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.3371453521
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3477214081
Short name T377
Test name
Test status
Simulation time 9767130275 ps
CPU time 56.02 seconds
Started May 12 01:31:14 PM PDT 24
Finished May 12 01:32:11 PM PDT 24
Peak memory 283756 kb
Host smart-c9405e7a-a707-49f2-9004-250b9edb86c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477214081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3477214081
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.116395284
Short name T4
Test name
Test status
Simulation time 731303204 ps
CPU time 24.63 seconds
Started May 12 01:31:13 PM PDT 24
Finished May 12 01:31:38 PM PDT 24
Peak memory 247776 kb
Host smart-672feb0e-a122-437b-91ac-3dd6625333c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116395284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.116395284
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2095483284
Short name T727
Test name
Test status
Simulation time 122251579 ps
CPU time 1.44 seconds
Started May 12 01:31:13 PM PDT 24
Finished May 12 01:31:14 PM PDT 24
Peak memory 217932 kb
Host smart-cfb7c595-06fd-4ddb-82d0-0a0110a25247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095483284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2095483284
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.462471277
Short name T331
Test name
Test status
Simulation time 949128303 ps
CPU time 11.15 seconds
Started May 12 01:31:15 PM PDT 24
Finished May 12 01:31:27 PM PDT 24
Peak memory 218904 kb
Host smart-cefdbd53-7b2c-4f79-9538-3ab56c02c155
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462471277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.462471277
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.704375371
Short name T466
Test name
Test status
Simulation time 822643611 ps
CPU time 8.39 seconds
Started May 12 01:31:13 PM PDT 24
Finished May 12 01:31:21 PM PDT 24
Peak memory 217912 kb
Host smart-a647c49c-db9e-464c-a9f3-4b1643582b1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704375371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_di
gest.704375371
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.4167319640
Short name T317
Test name
Test status
Simulation time 1927956246 ps
CPU time 10.14 seconds
Started May 12 01:31:15 PM PDT 24
Finished May 12 01:31:26 PM PDT 24
Peak memory 218076 kb
Host smart-baeb363b-38a8-42a6-9864-5584814f0b77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167319640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
4167319640
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2185237519
Short name T386
Test name
Test status
Simulation time 202959616 ps
CPU time 6.91 seconds
Started May 12 01:31:15 PM PDT 24
Finished May 12 01:31:23 PM PDT 24
Peak memory 218052 kb
Host smart-a91af84d-786c-4b9c-a618-3bfc9a678960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185237519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2185237519
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3375441629
Short name T602
Test name
Test status
Simulation time 103534370 ps
CPU time 3.49 seconds
Started May 12 01:31:08 PM PDT 24
Finished May 12 01:31:13 PM PDT 24
Peak memory 217856 kb
Host smart-1c4dafe5-557e-47a1-abd8-e6143cd49f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375441629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3375441629
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.1536910662
Short name T413
Test name
Test status
Simulation time 933128456 ps
CPU time 23.73 seconds
Started May 12 01:31:16 PM PDT 24
Finished May 12 01:31:40 PM PDT 24
Peak memory 250844 kb
Host smart-d12eb69e-f295-45ab-9e38-895315b47805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536910662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.1536910662
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.477935297
Short name T864
Test name
Test status
Simulation time 486163526 ps
CPU time 7.77 seconds
Started May 12 01:31:13 PM PDT 24
Finished May 12 01:31:21 PM PDT 24
Peak memory 250408 kb
Host smart-03650b06-2629-40fc-9d7a-146895aeae04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477935297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.477935297
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2026517638
Short name T734
Test name
Test status
Simulation time 18117639017 ps
CPU time 591.11 seconds
Started May 12 01:31:16 PM PDT 24
Finished May 12 01:41:08 PM PDT 24
Peak memory 252668 kb
Host smart-5604a9e7-737b-4833-afa2-37979ab27a05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026517638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2026517638
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.3224383600
Short name T156
Test name
Test status
Simulation time 81822672125 ps
CPU time 591.55 seconds
Started May 12 01:31:16 PM PDT 24
Finished May 12 01:41:08 PM PDT 24
Peak memory 496972 kb
Host smart-08a7ddd8-6b6a-4f6a-8689-64baa0628043
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3224383600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.3224383600
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1931069622
Short name T168
Test name
Test status
Simulation time 39079625 ps
CPU time 0.95 seconds
Started May 12 01:31:16 PM PDT 24
Finished May 12 01:31:17 PM PDT 24
Peak memory 211548 kb
Host smart-d266e340-437e-4301-a699-dacbb2eef463
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1931069622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1931069622
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2301738673
Short name T265
Test name
Test status
Simulation time 18120783 ps
CPU time 0.95 seconds
Started May 12 01:31:23 PM PDT 24
Finished May 12 01:31:24 PM PDT 24
Peak memory 209568 kb
Host smart-bfcb3968-c6ae-4edc-b81e-a0c97e6d1783
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301738673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2301738673
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2328266473
Short name T572
Test name
Test status
Simulation time 475823844 ps
CPU time 16.6 seconds
Started May 12 01:31:20 PM PDT 24
Finished May 12 01:31:37 PM PDT 24
Peak memory 218100 kb
Host smart-9078bd97-4459-4a34-83e8-4548123ca3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328266473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2328266473
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1143187758
Short name T441
Test name
Test status
Simulation time 632935144 ps
CPU time 6.52 seconds
Started May 12 01:31:26 PM PDT 24
Finished May 12 01:31:33 PM PDT 24
Peak memory 209480 kb
Host smart-6f0174da-7917-4acf-aad6-3306b19801eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143187758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1143187758
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.270909727
Short name T638
Test name
Test status
Simulation time 2939305615 ps
CPU time 45.17 seconds
Started May 12 01:31:19 PM PDT 24
Finished May 12 01:32:04 PM PDT 24
Peak memory 219136 kb
Host smart-f27b3129-ddb1-4186-816c-6bd11a4eb8e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270909727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er
rors.270909727
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3630696937
Short name T578
Test name
Test status
Simulation time 2344776045 ps
CPU time 18.95 seconds
Started May 12 01:31:18 PM PDT 24
Finished May 12 01:31:37 PM PDT 24
Peak memory 218072 kb
Host smart-8d0aa695-1c86-4a39-bd18-9a04f1536213
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630696937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.3630696937
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.4227365862
Short name T553
Test name
Test status
Simulation time 1643970116 ps
CPU time 71.57 seconds
Started May 12 01:31:18 PM PDT 24
Finished May 12 01:32:30 PM PDT 24
Peak memory 274416 kb
Host smart-0649baea-fcd4-44ce-ad4d-40b26f2caf43
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227365862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.4227365862
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1142871779
Short name T310
Test name
Test status
Simulation time 3424245383 ps
CPU time 31.51 seconds
Started May 12 01:31:16 PM PDT 24
Finished May 12 01:31:48 PM PDT 24
Peak memory 251248 kb
Host smart-7f4d6c01-5993-4012-881c-04632564d996
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142871779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1142871779
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1280670846
Short name T161
Test name
Test status
Simulation time 718503187 ps
CPU time 3.8 seconds
Started May 12 01:31:18 PM PDT 24
Finished May 12 01:31:22 PM PDT 24
Peak memory 218048 kb
Host smart-1ee21bb5-3639-44dd-9497-3dc15d68855b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280670846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1280670846
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.347963612
Short name T267
Test name
Test status
Simulation time 383398206 ps
CPU time 12.53 seconds
Started May 12 01:31:20 PM PDT 24
Finished May 12 01:31:33 PM PDT 24
Peak memory 218004 kb
Host smart-45848d8a-e18f-4658-b8f3-b33c00b0d04e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347963612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.347963612
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.730571607
Short name T273
Test name
Test status
Simulation time 346794885 ps
CPU time 13.98 seconds
Started May 12 01:31:21 PM PDT 24
Finished May 12 01:31:35 PM PDT 24
Peak memory 217976 kb
Host smart-972acfb9-a82b-4a92-a9f4-eb1750e7a67b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730571607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_di
gest.730571607
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.780035868
Short name T374
Test name
Test status
Simulation time 632147990 ps
CPU time 12.55 seconds
Started May 12 01:31:26 PM PDT 24
Finished May 12 01:31:39 PM PDT 24
Peak memory 217900 kb
Host smart-73ae4b36-34cf-4815-9637-3727adc4dddb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780035868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.780035868
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2930141247
Short name T391
Test name
Test status
Simulation time 416161878 ps
CPU time 8.1 seconds
Started May 12 01:31:17 PM PDT 24
Finished May 12 01:31:26 PM PDT 24
Peak memory 218008 kb
Host smart-fd15a866-6f7c-417a-af9b-c6e4dc21b592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930141247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2930141247
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.277471684
Short name T70
Test name
Test status
Simulation time 34201818 ps
CPU time 1.69 seconds
Started May 12 01:31:20 PM PDT 24
Finished May 12 01:31:22 PM PDT 24
Peak memory 213644 kb
Host smart-e5330f3f-fa47-4b54-b6ad-454b2356a3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277471684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.277471684
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3861751427
Short name T750
Test name
Test status
Simulation time 318912408 ps
CPU time 25.46 seconds
Started May 12 01:31:18 PM PDT 24
Finished May 12 01:31:44 PM PDT 24
Peak memory 250576 kb
Host smart-36ce7c09-dd83-447d-b23f-7027e4de70ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861751427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3861751427
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.852585355
Short name T462
Test name
Test status
Simulation time 893203934 ps
CPU time 8.06 seconds
Started May 12 01:31:18 PM PDT 24
Finished May 12 01:31:27 PM PDT 24
Peak memory 250868 kb
Host smart-b40cef07-0028-4a73-918e-09534c61ecb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852585355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.852585355
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3307722213
Short name T58
Test name
Test status
Simulation time 76466980216 ps
CPU time 344.02 seconds
Started May 12 01:31:20 PM PDT 24
Finished May 12 01:37:04 PM PDT 24
Peak memory 273620 kb
Host smart-64962e34-243e-4d94-862e-d86b3fca84a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307722213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3307722213
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3592299217
Short name T144
Test name
Test status
Simulation time 12505638 ps
CPU time 0.72 seconds
Started May 12 01:31:16 PM PDT 24
Finished May 12 01:31:18 PM PDT 24
Peak memory 207832 kb
Host smart-a66f9fb4-398b-4077-8fda-6e41b786e59c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592299217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3592299217
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.3712497234
Short name T755
Test name
Test status
Simulation time 38971819 ps
CPU time 0.95 seconds
Started May 12 01:31:20 PM PDT 24
Finished May 12 01:31:22 PM PDT 24
Peak memory 209540 kb
Host smart-d1f5f878-46b3-4a66-a6eb-2ea537180e0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712497234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.3712497234
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3667221488
Short name T399
Test name
Test status
Simulation time 282320649 ps
CPU time 11.04 seconds
Started May 12 01:31:20 PM PDT 24
Finished May 12 01:31:32 PM PDT 24
Peak memory 218032 kb
Host smart-8deaf9e7-4093-4212-b167-76449b799742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667221488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3667221488
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3535655249
Short name T838
Test name
Test status
Simulation time 167224669 ps
CPU time 2.75 seconds
Started May 12 01:31:26 PM PDT 24
Finished May 12 01:31:29 PM PDT 24
Peak memory 209560 kb
Host smart-ac150523-aa21-47b1-973a-bf62b657a40d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535655249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3535655249
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3652619638
Short name T472
Test name
Test status
Simulation time 3540769720 ps
CPU time 51.89 seconds
Started May 12 01:31:29 PM PDT 24
Finished May 12 01:32:21 PM PDT 24
Peak memory 218852 kb
Host smart-76e927ad-f9d4-4a74-9da6-b824c5d771f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652619638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3652619638
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.3014643786
Short name T858
Test name
Test status
Simulation time 236832349 ps
CPU time 5.76 seconds
Started May 12 01:31:20 PM PDT 24
Finished May 12 01:31:26 PM PDT 24
Peak memory 218024 kb
Host smart-c53bfe84-3d19-4ddc-8488-d24bf681230f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014643786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.3014643786
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3474498921
Short name T541
Test name
Test status
Simulation time 2819599195 ps
CPU time 3.43 seconds
Started May 12 01:31:29 PM PDT 24
Finished May 12 01:31:33 PM PDT 24
Peak memory 213652 kb
Host smart-370d29ed-a6b4-4015-a5fd-bcf4a739e7c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474498921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3474498921
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1462187935
Short name T688
Test name
Test status
Simulation time 4844880919 ps
CPU time 75.35 seconds
Started May 12 01:31:20 PM PDT 24
Finished May 12 01:32:36 PM PDT 24
Peak memory 276412 kb
Host smart-44009a73-0c6a-482f-9f77-c811aaf41dcb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462187935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1462187935
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.568375864
Short name T716
Test name
Test status
Simulation time 1067672858 ps
CPU time 14.55 seconds
Started May 12 01:31:25 PM PDT 24
Finished May 12 01:31:40 PM PDT 24
Peak memory 250724 kb
Host smart-6e9b4c82-592b-4934-9e11-2e921178f43f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568375864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.568375864
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1732930127
Short name T390
Test name
Test status
Simulation time 63523756 ps
CPU time 2.7 seconds
Started May 12 01:31:25 PM PDT 24
Finished May 12 01:31:28 PM PDT 24
Peak memory 217884 kb
Host smart-b2271f75-8505-4c1d-a9f6-405b727eeb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732930127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1732930127
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.3949690000
Short name T836
Test name
Test status
Simulation time 1602751299 ps
CPU time 17.25 seconds
Started May 12 01:31:20 PM PDT 24
Finished May 12 01:31:38 PM PDT 24
Peak memory 219176 kb
Host smart-9207d63b-9b3a-4fba-8074-fef85dfe73b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949690000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3949690000
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1921324101
Short name T767
Test name
Test status
Simulation time 1898236963 ps
CPU time 14.93 seconds
Started May 12 01:31:20 PM PDT 24
Finished May 12 01:31:36 PM PDT 24
Peak memory 217884 kb
Host smart-eb84b85c-662e-4895-96bb-5f029a9bbadd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921324101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1921324101
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2838808009
Short name T849
Test name
Test status
Simulation time 329514110 ps
CPU time 11.49 seconds
Started May 12 01:31:29 PM PDT 24
Finished May 12 01:31:41 PM PDT 24
Peak memory 217692 kb
Host smart-fabac978-8f16-4516-97a1-50b03e692d76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838808009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2838808009
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2448511929
Short name T661
Test name
Test status
Simulation time 321426356 ps
CPU time 10.04 seconds
Started May 12 01:31:21 PM PDT 24
Finished May 12 01:31:32 PM PDT 24
Peak memory 218048 kb
Host smart-6fdf0744-b1a5-451b-adb8-00671d89597a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448511929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2448511929
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1690797327
Short name T771
Test name
Test status
Simulation time 156736234 ps
CPU time 2.82 seconds
Started May 12 01:31:29 PM PDT 24
Finished May 12 01:31:32 PM PDT 24
Peak memory 214176 kb
Host smart-81e3d780-53a2-4bf5-a1f1-7ece06b54fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690797327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1690797327
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.431113135
Short name T845
Test name
Test status
Simulation time 1505238122 ps
CPU time 32.06 seconds
Started May 12 01:31:23 PM PDT 24
Finished May 12 01:31:55 PM PDT 24
Peak memory 250984 kb
Host smart-7b4d7de0-6a87-4300-949e-bf0c0d58c952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431113135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.431113135
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2850627876
Short name T784
Test name
Test status
Simulation time 497148602 ps
CPU time 5.58 seconds
Started May 12 01:31:22 PM PDT 24
Finished May 12 01:31:28 PM PDT 24
Peak memory 226376 kb
Host smart-5b023254-0f25-4db4-91b6-470f3217c7df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850627876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2850627876
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.832170693
Short name T855
Test name
Test status
Simulation time 42547167734 ps
CPU time 260.83 seconds
Started May 12 01:31:22 PM PDT 24
Finished May 12 01:35:43 PM PDT 24
Peak memory 283784 kb
Host smart-e14a954d-0a2e-4821-8e3d-e9e4b041c7ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=832170693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.832170693
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2075533983
Short name T89
Test name
Test status
Simulation time 34685604 ps
CPU time 0.8 seconds
Started May 12 01:31:29 PM PDT 24
Finished May 12 01:31:31 PM PDT 24
Peak memory 211468 kb
Host smart-ccd62eec-2d93-44cd-9cef-cc1a7a54256f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075533983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.2075533983
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.1300259524
Short name T822
Test name
Test status
Simulation time 30607979 ps
CPU time 1.12 seconds
Started May 12 01:31:29 PM PDT 24
Finished May 12 01:31:30 PM PDT 24
Peak memory 209588 kb
Host smart-5c8d1715-3706-4021-840b-430a2d4845a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300259524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1300259524
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2729290268
Short name T780
Test name
Test status
Simulation time 272533989 ps
CPU time 11.83 seconds
Started May 12 01:31:25 PM PDT 24
Finished May 12 01:31:37 PM PDT 24
Peak memory 218200 kb
Host smart-8cf3364a-c06d-4ddd-8cb9-8758a8bf226b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729290268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2729290268
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1992982765
Short name T57
Test name
Test status
Simulation time 205732331 ps
CPU time 1.5 seconds
Started May 12 01:31:25 PM PDT 24
Finished May 12 01:31:27 PM PDT 24
Peak memory 216844 kb
Host smart-167bff77-c550-4498-b22a-c1606aef69d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992982765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1992982765
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2745346215
Short name T299
Test name
Test status
Simulation time 2817826477 ps
CPU time 34.59 seconds
Started May 12 01:31:24 PM PDT 24
Finished May 12 01:31:59 PM PDT 24
Peak memory 218060 kb
Host smart-7a082324-f41e-4502-b56d-d9d924db49f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745346215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2745346215
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2943295167
Short name T139
Test name
Test status
Simulation time 388023271 ps
CPU time 7.2 seconds
Started May 12 01:31:26 PM PDT 24
Finished May 12 01:31:34 PM PDT 24
Peak memory 217948 kb
Host smart-f36a4fa1-15b6-4323-b5a1-a6840cf06bc0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943295167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2943295167
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3522676346
Short name T492
Test name
Test status
Simulation time 2339668135 ps
CPU time 3.89 seconds
Started May 12 01:31:24 PM PDT 24
Finished May 12 01:31:28 PM PDT 24
Peak memory 213508 kb
Host smart-cd3304b5-ae72-4564-b75f-e30818430784
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522676346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3522676346
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1339820536
Short name T635
Test name
Test status
Simulation time 912516606 ps
CPU time 46.14 seconds
Started May 12 01:31:24 PM PDT 24
Finished May 12 01:32:10 PM PDT 24
Peak memory 250744 kb
Host smart-397eb364-c718-40f8-8958-c97856c97a1a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339820536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1339820536
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2681929066
Short name T513
Test name
Test status
Simulation time 1558121256 ps
CPU time 31.17 seconds
Started May 12 01:31:23 PM PDT 24
Finished May 12 01:31:55 PM PDT 24
Peak memory 250964 kb
Host smart-16f1d38f-12f6-4537-98f1-09a5d33ef899
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681929066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2681929066
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.4210251376
Short name T218
Test name
Test status
Simulation time 107892738 ps
CPU time 1.72 seconds
Started May 12 01:31:23 PM PDT 24
Finished May 12 01:31:25 PM PDT 24
Peak memory 217944 kb
Host smart-2e776bbf-9fb8-43eb-97c0-0203ecfc3064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210251376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.4210251376
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.86524994
Short name T345
Test name
Test status
Simulation time 1365269156 ps
CPU time 14.53 seconds
Started May 12 01:31:25 PM PDT 24
Finished May 12 01:31:40 PM PDT 24
Peak memory 218912 kb
Host smart-13a83d28-7e29-4ae1-9928-8735bb12019f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86524994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.86524994
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.137192217
Short name T787
Test name
Test status
Simulation time 1352439870 ps
CPU time 12.79 seconds
Started May 12 01:31:25 PM PDT 24
Finished May 12 01:31:38 PM PDT 24
Peak memory 218028 kb
Host smart-7d82807d-8290-449f-b3c2-4b51cd7aa782
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137192217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.137192217
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.3204907119
Short name T681
Test name
Test status
Simulation time 275118917 ps
CPU time 8.75 seconds
Started May 12 01:31:24 PM PDT 24
Finished May 12 01:31:33 PM PDT 24
Peak memory 217964 kb
Host smart-2b70c315-19c1-44be-8989-b0e8d85a4ddf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204907119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
3204907119
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2326794561
Short name T88
Test name
Test status
Simulation time 5214032216 ps
CPU time 10.42 seconds
Started May 12 01:31:26 PM PDT 24
Finished May 12 01:31:37 PM PDT 24
Peak memory 218176 kb
Host smart-6601a415-eb64-439e-9e67-bf5ba963d51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326794561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2326794561
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1078919968
Short name T288
Test name
Test status
Simulation time 16589864 ps
CPU time 1.05 seconds
Started May 12 01:31:27 PM PDT 24
Finished May 12 01:31:29 PM PDT 24
Peak memory 212016 kb
Host smart-75ad3843-8c19-4a87-98fe-4a290b09338c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078919968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1078919968
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2871558985
Short name T694
Test name
Test status
Simulation time 3153459369 ps
CPU time 24.18 seconds
Started May 12 01:31:25 PM PDT 24
Finished May 12 01:31:49 PM PDT 24
Peak memory 250676 kb
Host smart-76089726-19b8-4c6e-b553-664be93013f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871558985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2871558985
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1287072079
Short name T330
Test name
Test status
Simulation time 72271478 ps
CPU time 6.31 seconds
Started May 12 01:31:25 PM PDT 24
Finished May 12 01:31:31 PM PDT 24
Peak memory 246636 kb
Host smart-938a8cf2-bb42-4b96-baac-673efbdad360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287072079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1287072079
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.448752250
Short name T364
Test name
Test status
Simulation time 2380133261 ps
CPU time 28.77 seconds
Started May 12 01:31:27 PM PDT 24
Finished May 12 01:31:56 PM PDT 24
Peak memory 250868 kb
Host smart-b9c5bb01-7221-4997-9cae-6c4f5ae5e630
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448752250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.448752250
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.2726930090
Short name T78
Test name
Test status
Simulation time 52706599954 ps
CPU time 295.82 seconds
Started May 12 01:31:29 PM PDT 24
Finished May 12 01:36:26 PM PDT 24
Peak memory 333116 kb
Host smart-af07a43d-fd11-4fad-90f9-0c36054a3177
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2726930090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.2726930090
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.323335188
Short name T862
Test name
Test status
Simulation time 12615427 ps
CPU time 0.83 seconds
Started May 12 01:31:26 PM PDT 24
Finished May 12 01:31:27 PM PDT 24
Peak memory 211548 kb
Host smart-9b41dc01-4e17-42fb-a97d-c02f24b6c118
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323335188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.323335188
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1575122820
Short name T583
Test name
Test status
Simulation time 51240590 ps
CPU time 0.87 seconds
Started May 12 01:31:38 PM PDT 24
Finished May 12 01:31:40 PM PDT 24
Peak memory 209352 kb
Host smart-fe32f683-a270-4b3e-8092-65fda5960e5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575122820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1575122820
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3379333756
Short name T869
Test name
Test status
Simulation time 1218239044 ps
CPU time 12.96 seconds
Started May 12 01:31:26 PM PDT 24
Finished May 12 01:31:40 PM PDT 24
Peak memory 217996 kb
Host smart-605013a5-0a34-4d37-bf29-e71bac4200aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379333756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3379333756
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2374634822
Short name T28
Test name
Test status
Simulation time 1092565430 ps
CPU time 26.28 seconds
Started May 12 01:31:27 PM PDT 24
Finished May 12 01:31:54 PM PDT 24
Peak memory 209524 kb
Host smart-c181148c-5e12-4606-8d17-e8c634ebaac8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374634822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2374634822
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1828990297
Short name T236
Test name
Test status
Simulation time 1390967925 ps
CPU time 26.24 seconds
Started May 12 01:31:27 PM PDT 24
Finished May 12 01:31:54 PM PDT 24
Peak memory 217908 kb
Host smart-53dd31c2-95fa-4a8b-99e7-d1f918ab1b31
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828990297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1828990297
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3763815448
Short name T696
Test name
Test status
Simulation time 217665704 ps
CPU time 4.14 seconds
Started May 12 01:31:29 PM PDT 24
Finished May 12 01:31:34 PM PDT 24
Peak memory 218044 kb
Host smart-35f9964b-c7e9-4471-8add-09155444ee2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763815448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3763815448
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1550740252
Short name T785
Test name
Test status
Simulation time 300795272 ps
CPU time 5.5 seconds
Started May 12 01:31:27 PM PDT 24
Finished May 12 01:31:33 PM PDT 24
Peak memory 214104 kb
Host smart-c71d1bfa-54d1-4a43-8213-4144ac037328
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550740252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1550740252
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.4069592379
Short name T21
Test name
Test status
Simulation time 3347386245 ps
CPU time 42.71 seconds
Started May 12 01:31:29 PM PDT 24
Finished May 12 01:32:12 PM PDT 24
Peak memory 251808 kb
Host smart-6366527e-6dfa-4658-89c1-90df0d4fbda2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069592379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.4069592379
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1369542854
Short name T560
Test name
Test status
Simulation time 1954303329 ps
CPU time 15.98 seconds
Started May 12 01:31:30 PM PDT 24
Finished May 12 01:31:46 PM PDT 24
Peak memory 248324 kb
Host smart-73de2baf-22dd-457f-9943-76977df025e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369542854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1369542854
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2671253884
Short name T291
Test name
Test status
Simulation time 32876291 ps
CPU time 1.7 seconds
Started May 12 01:31:29 PM PDT 24
Finished May 12 01:31:32 PM PDT 24
Peak memory 218064 kb
Host smart-59ad75fc-1442-4834-b527-39592ee9dc59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671253884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2671253884
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.260183311
Short name T411
Test name
Test status
Simulation time 1956049419 ps
CPU time 15.37 seconds
Started May 12 01:31:32 PM PDT 24
Finished May 12 01:31:48 PM PDT 24
Peak memory 226060 kb
Host smart-34eda6ef-57dc-45db-9c18-4ab33405081e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260183311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.260183311
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.4059856819
Short name T756
Test name
Test status
Simulation time 1369936922 ps
CPU time 9.73 seconds
Started May 12 01:31:31 PM PDT 24
Finished May 12 01:31:41 PM PDT 24
Peak memory 217892 kb
Host smart-166fdb2c-5c0d-4d79-b559-50cbe9cb9435
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059856819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.4059856819
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1575543750
Short name T498
Test name
Test status
Simulation time 315068708 ps
CPU time 9.79 seconds
Started May 12 01:31:32 PM PDT 24
Finished May 12 01:31:43 PM PDT 24
Peak memory 218080 kb
Host smart-22f3878c-45c2-46e5-833e-e0c19c480d57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575543750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1575543750
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.31186033
Short name T421
Test name
Test status
Simulation time 223867165 ps
CPU time 8.94 seconds
Started May 12 01:31:29 PM PDT 24
Finished May 12 01:31:39 PM PDT 24
Peak memory 217988 kb
Host smart-54a60835-e7bf-4f03-92df-19e28742007c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31186033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.31186033
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1327533926
Short name T69
Test name
Test status
Simulation time 34490923 ps
CPU time 2.17 seconds
Started May 12 01:31:29 PM PDT 24
Finished May 12 01:31:32 PM PDT 24
Peak memory 217780 kb
Host smart-c1eca0b8-beb9-4ef4-a3db-132af089b16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327533926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1327533926
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3477004787
Short name T555
Test name
Test status
Simulation time 189344980 ps
CPU time 20.03 seconds
Started May 12 01:31:28 PM PDT 24
Finished May 12 01:31:48 PM PDT 24
Peak memory 250888 kb
Host smart-18d0b2ee-1695-4e75-9f5f-aceaa5a56ff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477004787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3477004787
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.1273892352
Short name T80
Test name
Test status
Simulation time 81610040 ps
CPU time 6.7 seconds
Started May 12 01:31:29 PM PDT 24
Finished May 12 01:31:36 PM PDT 24
Peak memory 248356 kb
Host smart-1755cf3b-de84-41bd-8542-95ea40f378a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273892352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.1273892352
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.4160916002
Short name T380
Test name
Test status
Simulation time 7842794416 ps
CPU time 63.04 seconds
Started May 12 01:31:36 PM PDT 24
Finished May 12 01:32:39 PM PDT 24
Peak memory 250800 kb
Host smart-c755614e-c077-44e7-8cca-75130dd7788a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160916002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.4160916002
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1140418683
Short name T658
Test name
Test status
Simulation time 18924035 ps
CPU time 0.93 seconds
Started May 12 01:31:27 PM PDT 24
Finished May 12 01:31:28 PM PDT 24
Peak memory 211600 kb
Host smart-9682b767-4ef7-493e-942c-714106f8ff98
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140418683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1140418683
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3139585485
Short name T782
Test name
Test status
Simulation time 34385446 ps
CPU time 1.14 seconds
Started May 12 01:31:36 PM PDT 24
Finished May 12 01:31:38 PM PDT 24
Peak memory 209576 kb
Host smart-9dd3da5c-d290-45db-80ed-59eca7e75e13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139585485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3139585485
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.317225597
Short name T619
Test name
Test status
Simulation time 1596699334 ps
CPU time 11.13 seconds
Started May 12 01:31:31 PM PDT 24
Finished May 12 01:31:43 PM PDT 24
Peak memory 218020 kb
Host smart-4c6ec4d7-27b6-4c27-a7fb-7498ae12c0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317225597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.317225597
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.681407392
Short name T342
Test name
Test status
Simulation time 501624112 ps
CPU time 7.75 seconds
Started May 12 01:31:44 PM PDT 24
Finished May 12 01:31:53 PM PDT 24
Peak memory 209536 kb
Host smart-c1448026-0024-478a-9431-6b4283ddf403
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681407392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.681407392
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.3576756697
Short name T554
Test name
Test status
Simulation time 6676056134 ps
CPU time 21.53 seconds
Started May 12 01:31:37 PM PDT 24
Finished May 12 01:31:59 PM PDT 24
Peak memory 219024 kb
Host smart-58b522a8-b7fe-451c-84e6-0f7b6137c449
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576756697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.3576756697
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.572791
Short name T437
Test name
Test status
Simulation time 343391989 ps
CPU time 4.59 seconds
Started May 12 01:31:39 PM PDT 24
Finished May 12 01:31:44 PM PDT 24
Peak memory 217952 kb
Host smart-9b3c15fc-42e2-48cc-b8fe-48f5ddfb22d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_pro
g_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_pr
og_failure.572791
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1704534755
Short name T831
Test name
Test status
Simulation time 491409049 ps
CPU time 12.66 seconds
Started May 12 01:31:35 PM PDT 24
Finished May 12 01:31:48 PM PDT 24
Peak memory 213656 kb
Host smart-baacdaf7-edf9-4ad9-9e0c-218589ff6643
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704534755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1704534755
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3954879080
Short name T571
Test name
Test status
Simulation time 3248422748 ps
CPU time 118.93 seconds
Started May 12 01:31:36 PM PDT 24
Finished May 12 01:33:35 PM PDT 24
Peak memory 277980 kb
Host smart-a5f72769-fbfb-42f8-82c6-edabf222616e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954879080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3954879080
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3992703315
Short name T720
Test name
Test status
Simulation time 727774272 ps
CPU time 15.33 seconds
Started May 12 01:31:36 PM PDT 24
Finished May 12 01:31:52 PM PDT 24
Peak memory 247556 kb
Host smart-fc4ebf73-76c9-4b7d-9ef9-7e9b9a458071
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992703315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.3992703315
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1413932441
Short name T556
Test name
Test status
Simulation time 38073356 ps
CPU time 1.74 seconds
Started May 12 01:31:32 PM PDT 24
Finished May 12 01:31:35 PM PDT 24
Peak memory 217944 kb
Host smart-4a7aac4b-d03c-4a3d-a81e-80b24ecf2d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413932441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1413932441
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1273184063
Short name T653
Test name
Test status
Simulation time 255459691 ps
CPU time 9.27 seconds
Started May 12 01:31:36 PM PDT 24
Finished May 12 01:31:46 PM PDT 24
Peak memory 217908 kb
Host smart-425a8d6d-ee70-4c4d-8d4b-3c9b4364e9ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273184063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1273184063
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.122996890
Short name T697
Test name
Test status
Simulation time 1013363951 ps
CPU time 16.96 seconds
Started May 12 01:31:36 PM PDT 24
Finished May 12 01:31:54 PM PDT 24
Peak memory 218040 kb
Host smart-a48bf7fd-de52-43f8-829c-70689ea6f29a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122996890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.122996890
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.862331292
Short name T260
Test name
Test status
Simulation time 3877342630 ps
CPU time 7.03 seconds
Started May 12 01:31:39 PM PDT 24
Finished May 12 01:31:47 PM PDT 24
Peak memory 218012 kb
Host smart-70dd48eb-b8bc-4c6f-bf9b-162e18d7c4fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862331292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.862331292
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.867951081
Short name T469
Test name
Test status
Simulation time 346691079 ps
CPU time 11.83 seconds
Started May 12 01:31:35 PM PDT 24
Finished May 12 01:31:47 PM PDT 24
Peak memory 218104 kb
Host smart-031e49e9-0a3c-44a8-bfda-aa669f0fbb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867951081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.867951081
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.2565442180
Short name T507
Test name
Test status
Simulation time 69533281 ps
CPU time 1.45 seconds
Started May 12 01:31:32 PM PDT 24
Finished May 12 01:31:34 PM PDT 24
Peak memory 213700 kb
Host smart-95696ed5-e8b8-48da-a4c3-b8ddcf08d140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565442180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.2565442180
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2299389369
Short name T344
Test name
Test status
Simulation time 501511401 ps
CPU time 14.41 seconds
Started May 12 01:31:32 PM PDT 24
Finished May 12 01:31:47 PM PDT 24
Peak memory 250628 kb
Host smart-955393ce-28a7-4fce-9e9a-547f4de96696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299389369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2299389369
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.4280612696
Short name T567
Test name
Test status
Simulation time 49550103 ps
CPU time 6.34 seconds
Started May 12 01:31:33 PM PDT 24
Finished May 12 01:31:40 PM PDT 24
Peak memory 246808 kb
Host smart-18977e67-239e-4dae-8a72-0d2bc8078b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280612696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.4280612696
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.522119527
Short name T656
Test name
Test status
Simulation time 45438034475 ps
CPU time 399.41 seconds
Started May 12 01:31:37 PM PDT 24
Finished May 12 01:38:17 PM PDT 24
Peak memory 274032 kb
Host smart-f20371b5-1cae-423d-b4b4-8acc8bd16fc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522119527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.522119527
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2463105952
Short name T628
Test name
Test status
Simulation time 84145374 ps
CPU time 0.96 seconds
Started May 12 01:31:32 PM PDT 24
Finished May 12 01:31:33 PM PDT 24
Peak memory 211560 kb
Host smart-a491d494-e2a7-452e-af33-920750759fc4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463105952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2463105952
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2053617399
Short name T747
Test name
Test status
Simulation time 14974702 ps
CPU time 0.9 seconds
Started May 12 01:31:42 PM PDT 24
Finished May 12 01:31:44 PM PDT 24
Peak memory 209488 kb
Host smart-08e5bef0-5571-41c5-a9b6-7489a922cb36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053617399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2053617399
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.1816985820
Short name T704
Test name
Test status
Simulation time 2425092631 ps
CPU time 16.4 seconds
Started May 12 01:31:36 PM PDT 24
Finished May 12 01:31:53 PM PDT 24
Peak memory 218112 kb
Host smart-d73345e6-561a-4527-81c0-8a86259d6456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816985820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.1816985820
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3169835158
Short name T745
Test name
Test status
Simulation time 1269435027 ps
CPU time 6.54 seconds
Started May 12 01:31:39 PM PDT 24
Finished May 12 01:31:46 PM PDT 24
Peak memory 209372 kb
Host smart-fac01e35-2aea-4bf5-8553-7747079f35fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169835158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3169835158
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2573846355
Short name T499
Test name
Test status
Simulation time 3289465850 ps
CPU time 61.71 seconds
Started May 12 01:31:41 PM PDT 24
Finished May 12 01:32:43 PM PDT 24
Peak memory 218948 kb
Host smart-a1a9f2e1-0295-4508-8fc6-5e78089145d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573846355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2573846355
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1034453697
Short name T800
Test name
Test status
Simulation time 309660231 ps
CPU time 6.1 seconds
Started May 12 01:31:39 PM PDT 24
Finished May 12 01:31:46 PM PDT 24
Peak memory 218028 kb
Host smart-0a7494f8-08a7-406b-9206-0326075c948a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034453697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1034453697
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.649318903
Short name T59
Test name
Test status
Simulation time 237231034 ps
CPU time 6.63 seconds
Started May 12 01:31:37 PM PDT 24
Finished May 12 01:31:44 PM PDT 24
Peak memory 213384 kb
Host smart-da8ad9fb-2b48-430e-a486-9ffd1f9ddc6b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649318903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke.
649318903
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3227212167
Short name T400
Test name
Test status
Simulation time 1605775476 ps
CPU time 55.86 seconds
Started May 12 01:31:36 PM PDT 24
Finished May 12 01:32:32 PM PDT 24
Peak memory 250884 kb
Host smart-ba532dde-2b1c-4561-a23f-4559715a52b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227212167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3227212167
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.674095068
Short name T664
Test name
Test status
Simulation time 416361374 ps
CPU time 8.37 seconds
Started May 12 01:31:40 PM PDT 24
Finished May 12 01:31:49 PM PDT 24
Peak memory 222992 kb
Host smart-10858700-3e26-4fe9-9db6-01f6e9b435f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674095068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.674095068
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2749420860
Short name T247
Test name
Test status
Simulation time 91197184 ps
CPU time 4.5 seconds
Started May 12 01:31:44 PM PDT 24
Finished May 12 01:31:49 PM PDT 24
Peak memory 217940 kb
Host smart-6af41e59-ad2c-4158-9f18-5ab3d9ba0419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749420860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2749420860
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2599372926
Short name T284
Test name
Test status
Simulation time 358675594 ps
CPU time 14.93 seconds
Started May 12 01:31:39 PM PDT 24
Finished May 12 01:31:55 PM PDT 24
Peak memory 218008 kb
Host smart-4bf30f98-21e9-4dc1-8c11-320fc27a5968
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599372926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2599372926
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.109820355
Short name T249
Test name
Test status
Simulation time 890542046 ps
CPU time 8.43 seconds
Started May 12 01:31:38 PM PDT 24
Finished May 12 01:31:47 PM PDT 24
Peak memory 217936 kb
Host smart-7e8bf767-8739-4477-937d-a614dcf5e73f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109820355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.109820355
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1981113930
Short name T357
Test name
Test status
Simulation time 1199587662 ps
CPU time 12.09 seconds
Started May 12 01:31:35 PM PDT 24
Finished May 12 01:31:47 PM PDT 24
Peak memory 218036 kb
Host smart-1eca1e2f-f75d-4fa7-8e21-f4bd6993dca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981113930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1981113930
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.451314996
Short name T759
Test name
Test status
Simulation time 92531759 ps
CPU time 1.84 seconds
Started May 12 01:31:44 PM PDT 24
Finished May 12 01:31:47 PM PDT 24
Peak memory 213824 kb
Host smart-a33c08cb-5df3-400f-8139-47eeab2efc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451314996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.451314996
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2602446695
Short name T701
Test name
Test status
Simulation time 1691134668 ps
CPU time 32.45 seconds
Started May 12 01:31:44 PM PDT 24
Finished May 12 01:32:18 PM PDT 24
Peak memory 250876 kb
Host smart-30816514-e163-4885-b3a5-2679ec331411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602446695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2602446695
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3712811850
Short name T817
Test name
Test status
Simulation time 254034512 ps
CPU time 11.23 seconds
Started May 12 01:31:35 PM PDT 24
Finished May 12 01:31:46 PM PDT 24
Peak memory 250880 kb
Host smart-9a6edec7-c4a5-46da-bd3a-3c864713459b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712811850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3712811850
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1493855298
Short name T250
Test name
Test status
Simulation time 21094962891 ps
CPU time 621.31 seconds
Started May 12 01:31:40 PM PDT 24
Finished May 12 01:42:02 PM PDT 24
Peak memory 300268 kb
Host smart-4d5f2f8c-d60a-462e-9bd8-0e115c26f28b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493855298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1493855298
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1251372118
Short name T289
Test name
Test status
Simulation time 28618504 ps
CPU time 0.79 seconds
Started May 12 01:31:39 PM PDT 24
Finished May 12 01:31:40 PM PDT 24
Peak memory 211568 kb
Host smart-a951658d-73d5-40ba-a704-2f2bda401494
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251372118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1251372118
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3498227571
Short name T481
Test name
Test status
Simulation time 40291185 ps
CPU time 0.86 seconds
Started May 12 01:31:48 PM PDT 24
Finished May 12 01:31:49 PM PDT 24
Peak memory 209512 kb
Host smart-8ba2f9b9-85df-474a-ba47-1a2c98835e7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498227571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3498227571
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2278433707
Short name T677
Test name
Test status
Simulation time 429361277 ps
CPU time 12.2 seconds
Started May 12 01:31:43 PM PDT 24
Finished May 12 01:31:56 PM PDT 24
Peak memory 217848 kb
Host smart-674d3177-20c5-4c49-ac9a-8cc942295dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278433707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2278433707
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3804108
Short name T478
Test name
Test status
Simulation time 1402724573 ps
CPU time 32.31 seconds
Started May 12 01:31:43 PM PDT 24
Finished May 12 01:32:16 PM PDT 24
Peak memory 209432 kb
Host smart-fe0b8ec0-9c79-44d8-8c4e-7e4aa7705e5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3804108
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.714838390
Short name T36
Test name
Test status
Simulation time 10035680029 ps
CPU time 62.25 seconds
Started May 12 01:31:41 PM PDT 24
Finished May 12 01:32:43 PM PDT 24
Peak memory 218952 kb
Host smart-e58e7c01-03ea-4298-ac20-f90f2e617148
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714838390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_er
rors.714838390
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.4207650286
Short name T764
Test name
Test status
Simulation time 126465014 ps
CPU time 4.73 seconds
Started May 12 01:31:40 PM PDT 24
Finished May 12 01:31:45 PM PDT 24
Peak memory 218012 kb
Host smart-b48a67d8-e2ab-433f-891f-cf7e07c98056
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207650286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.4207650286
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1473830196
Short name T536
Test name
Test status
Simulation time 580714435 ps
CPU time 4.51 seconds
Started May 12 01:31:39 PM PDT 24
Finished May 12 01:31:44 PM PDT 24
Peak memory 213448 kb
Host smart-56448d0a-e192-47df-b742-ab404b3c0f9f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473830196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1473830196
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.4161019907
Short name T143
Test name
Test status
Simulation time 1033745597 ps
CPU time 32.98 seconds
Started May 12 01:31:42 PM PDT 24
Finished May 12 01:32:15 PM PDT 24
Peak memory 250884 kb
Host smart-3347323a-90d7-454f-a6cc-22bf62959dae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161019907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.4161019907
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2912549269
Short name T379
Test name
Test status
Simulation time 2714470888 ps
CPU time 15.2 seconds
Started May 12 01:31:39 PM PDT 24
Finished May 12 01:31:55 PM PDT 24
Peak memory 250632 kb
Host smart-9396b6f6-0bba-4dc0-bda5-dee1d9cbbe5d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912549269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2912549269
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2977063043
Short name T652
Test name
Test status
Simulation time 220250947 ps
CPU time 2.89 seconds
Started May 12 01:31:39 PM PDT 24
Finished May 12 01:31:43 PM PDT 24
Peak memory 217924 kb
Host smart-9cc75ca8-6b66-4619-942c-d7fd097f1af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2977063043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2977063043
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3728272375
Short name T779
Test name
Test status
Simulation time 1397435711 ps
CPU time 18.78 seconds
Started May 12 01:31:40 PM PDT 24
Finished May 12 01:31:59 PM PDT 24
Peak memory 218852 kb
Host smart-4f64bda4-0558-4a49-8bce-5a55574843f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728272375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3728272375
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.4194537410
Short name T360
Test name
Test status
Simulation time 563906719 ps
CPU time 11.46 seconds
Started May 12 01:31:43 PM PDT 24
Finished May 12 01:31:55 PM PDT 24
Peak memory 217848 kb
Host smart-39adb433-546d-4bad-86d4-c7e5c4722cbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194537410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.4194537410
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3230771874
Short name T742
Test name
Test status
Simulation time 7717037351 ps
CPU time 13.7 seconds
Started May 12 01:31:40 PM PDT 24
Finished May 12 01:31:54 PM PDT 24
Peak memory 218200 kb
Host smart-456a2195-adc6-45e5-b0ca-9190045c2044
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230771874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3230771874
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.462520855
Short name T312
Test name
Test status
Simulation time 436092998 ps
CPU time 15.49 seconds
Started May 12 01:31:39 PM PDT 24
Finished May 12 01:31:55 PM PDT 24
Peak memory 218028 kb
Host smart-bc90b8f4-13ca-4552-9ca6-355379396f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462520855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.462520855
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.352781653
Short name T547
Test name
Test status
Simulation time 72227242 ps
CPU time 1.27 seconds
Started May 12 01:31:40 PM PDT 24
Finished May 12 01:31:42 PM PDT 24
Peak memory 213384 kb
Host smart-27b64276-3788-4c2e-b3d9-14bfbd26d9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352781653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.352781653
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3052838093
Short name T85
Test name
Test status
Simulation time 1194935111 ps
CPU time 30.2 seconds
Started May 12 01:31:41 PM PDT 24
Finished May 12 01:32:12 PM PDT 24
Peak memory 250868 kb
Host smart-536cf3a1-ac34-443b-8495-c9878ec4b96a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052838093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3052838093
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2013111211
Short name T839
Test name
Test status
Simulation time 68621457 ps
CPU time 3.08 seconds
Started May 12 01:31:44 PM PDT 24
Finished May 12 01:31:48 PM PDT 24
Peak memory 222440 kb
Host smart-c947f06a-3418-435a-b64b-ae52194bd4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013111211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2013111211
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.2156906086
Short name T829
Test name
Test status
Simulation time 7420558040 ps
CPU time 32.5 seconds
Started May 12 01:31:42 PM PDT 24
Finished May 12 01:32:15 PM PDT 24
Peak memory 226868 kb
Host smart-55396e02-10fa-4961-9db8-041162f815ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156906086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.2156906086
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.841956922
Short name T134
Test name
Test status
Simulation time 105323695909 ps
CPU time 287.5 seconds
Started May 12 01:31:44 PM PDT 24
Finished May 12 01:36:33 PM PDT 24
Peak memory 286388 kb
Host smart-842d742d-a3e6-41b2-9d7f-b8e97c22645b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=841956922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.841956922
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2548218947
Short name T585
Test name
Test status
Simulation time 17598372 ps
CPU time 0.92 seconds
Started May 12 01:31:42 PM PDT 24
Finished May 12 01:31:43 PM PDT 24
Peak memory 211724 kb
Host smart-c4685255-1cac-4c67-a23f-a4171ecb61b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548218947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2548218947
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.44754782
Short name T293
Test name
Test status
Simulation time 27126198 ps
CPU time 0.86 seconds
Started May 12 01:31:42 PM PDT 24
Finished May 12 01:31:43 PM PDT 24
Peak memory 209372 kb
Host smart-7bd64800-f47e-47af-9d98-490a5d51bded
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44754782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.44754782
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2955227225
Short name T799
Test name
Test status
Simulation time 469349108 ps
CPU time 8.65 seconds
Started May 12 01:31:42 PM PDT 24
Finished May 12 01:31:52 PM PDT 24
Peak memory 217940 kb
Host smart-a93fc76c-f075-455b-bd46-9012ff4afa51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955227225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2955227225
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.2545301405
Short name T721
Test name
Test status
Simulation time 383344622 ps
CPU time 3.21 seconds
Started May 12 01:31:44 PM PDT 24
Finished May 12 01:31:48 PM PDT 24
Peak memory 209540 kb
Host smart-b36e6ca3-48ea-4152-830c-e21b31689e81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545301405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2545301405
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.3283025739
Short name T412
Test name
Test status
Simulation time 3710368958 ps
CPU time 48.79 seconds
Started May 12 01:31:42 PM PDT 24
Finished May 12 01:32:31 PM PDT 24
Peak memory 219004 kb
Host smart-aceb53f5-87ba-4030-8a98-8e2bfef00126
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283025739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.3283025739
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3896836788
Short name T834
Test name
Test status
Simulation time 187979810 ps
CPU time 3.53 seconds
Started May 12 01:31:42 PM PDT 24
Finished May 12 01:31:47 PM PDT 24
Peak memory 218016 kb
Host smart-9e4d0014-9c62-4f1c-b37c-da77ecc82102
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896836788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3896836788
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3020192554
Short name T272
Test name
Test status
Simulation time 58711454 ps
CPU time 1.69 seconds
Started May 12 01:31:43 PM PDT 24
Finished May 12 01:31:46 PM PDT 24
Peak memory 212976 kb
Host smart-7cf90177-94f2-4b47-b96a-00ca3887aa18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020192554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3020192554
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3273809352
Short name T729
Test name
Test status
Simulation time 4622841844 ps
CPU time 35.97 seconds
Started May 12 01:31:44 PM PDT 24
Finished May 12 01:32:21 PM PDT 24
Peak memory 267396 kb
Host smart-7cc75379-f51d-4050-8a0b-9f8166b51c39
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273809352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3273809352
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3532664718
Short name T246
Test name
Test status
Simulation time 732736696 ps
CPU time 16.13 seconds
Started May 12 01:31:44 PM PDT 24
Finished May 12 01:32:01 PM PDT 24
Peak memory 250312 kb
Host smart-74e6477f-0167-41e0-ab7a-2fe655e62943
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532664718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3532664718
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.1894190749
Short name T684
Test name
Test status
Simulation time 349117302 ps
CPU time 3.44 seconds
Started May 12 01:31:42 PM PDT 24
Finished May 12 01:31:45 PM PDT 24
Peak memory 218092 kb
Host smart-1ecc7b70-7069-4d05-a40c-e2a220725aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894190749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1894190749
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1722998935
Short name T473
Test name
Test status
Simulation time 1321551822 ps
CPU time 12.77 seconds
Started May 12 01:31:42 PM PDT 24
Finished May 12 01:31:56 PM PDT 24
Peak memory 218952 kb
Host smart-895e72ec-bfaa-4d5d-9a57-aa1e20926ac3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722998935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1722998935
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.2079217089
Short name T693
Test name
Test status
Simulation time 602209735 ps
CPU time 9.34 seconds
Started May 12 01:31:42 PM PDT 24
Finished May 12 01:31:52 PM PDT 24
Peak memory 218040 kb
Host smart-debb5efc-9759-47a7-806c-16a21a0cd3df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079217089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.2079217089
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3865571847
Short name T451
Test name
Test status
Simulation time 1536681301 ps
CPU time 13.12 seconds
Started May 12 01:31:41 PM PDT 24
Finished May 12 01:31:55 PM PDT 24
Peak memory 217980 kb
Host smart-6e028924-30c6-46fa-8b91-9af1cee318da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865571847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3865571847
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2484684112
Short name T436
Test name
Test status
Simulation time 900471647 ps
CPU time 9.25 seconds
Started May 12 01:31:43 PM PDT 24
Finished May 12 01:31:53 PM PDT 24
Peak memory 225396 kb
Host smart-f4d2cf45-992f-4d78-95d2-1241037c3c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484684112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2484684112
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3620520826
Short name T865
Test name
Test status
Simulation time 393202042 ps
CPU time 4.71 seconds
Started May 12 01:31:43 PM PDT 24
Finished May 12 01:31:49 PM PDT 24
Peak memory 217752 kb
Host smart-8a50ef1c-4b4c-4c51-a35a-500c0d40b455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620520826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3620520826
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2117439866
Short name T228
Test name
Test status
Simulation time 1776705173 ps
CPU time 25.51 seconds
Started May 12 01:31:44 PM PDT 24
Finished May 12 01:32:10 PM PDT 24
Peak memory 248960 kb
Host smart-78c0dc82-6819-416f-86ea-530a96cccb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117439866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2117439866
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1990708349
Short name T222
Test name
Test status
Simulation time 100503272 ps
CPU time 9.77 seconds
Started May 12 01:31:43 PM PDT 24
Finished May 12 01:31:54 PM PDT 24
Peak memory 247780 kb
Host smart-30a5019c-04a5-408d-8fd9-e1ddbb6216de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990708349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1990708349
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.755786852
Short name T287
Test name
Test status
Simulation time 17779235874 ps
CPU time 160.09 seconds
Started May 12 01:31:47 PM PDT 24
Finished May 12 01:34:29 PM PDT 24
Peak memory 275832 kb
Host smart-d8c24be1-6df1-4c66-a83e-4b1357e4cdcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755786852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.755786852
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.746364445
Short name T313
Test name
Test status
Simulation time 11866508 ps
CPU time 0.86 seconds
Started May 12 01:31:44 PM PDT 24
Finished May 12 01:31:45 PM PDT 24
Peak memory 211584 kb
Host smart-e7528f17-b626-412a-8e92-ffc43ed5f7b8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746364445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.746364445
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.707588862
Short name T341
Test name
Test status
Simulation time 65562951 ps
CPU time 0.82 seconds
Started May 12 01:31:48 PM PDT 24
Finished May 12 01:31:50 PM PDT 24
Peak memory 209388 kb
Host smart-1ce75ad1-9eb9-40b7-ac06-98818000d6c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707588862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.707588862
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2161306108
Short name T166
Test name
Test status
Simulation time 2320721850 ps
CPU time 13.03 seconds
Started May 12 01:31:48 PM PDT 24
Finished May 12 01:32:02 PM PDT 24
Peak memory 218064 kb
Host smart-b7d39525-341b-4c7e-a5ee-f303a460c156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161306108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2161306108
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3166418176
Short name T406
Test name
Test status
Simulation time 1434503901 ps
CPU time 4.68 seconds
Started May 12 01:31:46 PM PDT 24
Finished May 12 01:31:52 PM PDT 24
Peak memory 209540 kb
Host smart-ba9fe635-99d0-4fdc-a9bb-9d76e7df9452
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166418176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3166418176
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.796642813
Short name T484
Test name
Test status
Simulation time 3187617050 ps
CPU time 49.28 seconds
Started May 12 01:31:47 PM PDT 24
Finished May 12 01:32:38 PM PDT 24
Peak memory 220336 kb
Host smart-099f5002-a38b-4696-b133-c6279f5a4349
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796642813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.796642813
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2208532423
Short name T626
Test name
Test status
Simulation time 879446881 ps
CPU time 6.19 seconds
Started May 12 01:31:46 PM PDT 24
Finished May 12 01:31:53 PM PDT 24
Peak memory 218084 kb
Host smart-2a4e4cfb-9c28-4f7e-8d5a-92fc2c44adf9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208532423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2208532423
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2925234553
Short name T75
Test name
Test status
Simulation time 1418430562 ps
CPU time 9.77 seconds
Started May 12 01:31:47 PM PDT 24
Finished May 12 01:31:58 PM PDT 24
Peak memory 214000 kb
Host smart-4b7d792c-c0f9-4e69-b7a1-a3b995c5479f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925234553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2925234553
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3333149853
Short name T387
Test name
Test status
Simulation time 2834367213 ps
CPU time 36.24 seconds
Started May 12 01:31:44 PM PDT 24
Finished May 12 01:32:21 PM PDT 24
Peak memory 267740 kb
Host smart-94838460-a031-4d28-a687-c21b660e775d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333149853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3333149853
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1731400590
Short name T285
Test name
Test status
Simulation time 998715160 ps
CPU time 10.29 seconds
Started May 12 01:31:47 PM PDT 24
Finished May 12 01:31:59 PM PDT 24
Peak memory 224172 kb
Host smart-772fe7fb-4e71-4ef7-a25d-11ef5ec31cbe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731400590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1731400590
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2608981016
Short name T173
Test name
Test status
Simulation time 73633476 ps
CPU time 4.02 seconds
Started May 12 01:31:47 PM PDT 24
Finished May 12 01:31:52 PM PDT 24
Peak memory 217948 kb
Host smart-19176cbd-c157-42c6-af77-bb6236fe3fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608981016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2608981016
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3190788366
Short name T648
Test name
Test status
Simulation time 310206502 ps
CPU time 10.18 seconds
Started May 12 01:31:48 PM PDT 24
Finished May 12 01:31:59 PM PDT 24
Peak memory 226116 kb
Host smart-4b653db5-4654-4db6-8151-88638230bcad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190788366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3190788366
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.3677922299
Short name T529
Test name
Test status
Simulation time 417887002 ps
CPU time 13.13 seconds
Started May 12 01:31:45 PM PDT 24
Finished May 12 01:31:59 PM PDT 24
Peak memory 218088 kb
Host smart-3b621177-3576-43d4-862c-5607362c56e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677922299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.3677922299
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2361745510
Short name T43
Test name
Test status
Simulation time 184914575 ps
CPU time 5.38 seconds
Started May 12 01:31:44 PM PDT 24
Finished May 12 01:31:50 PM PDT 24
Peak memory 218064 kb
Host smart-67fd487c-a73b-4d23-9077-fe3f376d8c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361745510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2361745510
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1778758420
Short name T74
Test name
Test status
Simulation time 19393133 ps
CPU time 1.44 seconds
Started May 12 01:31:47 PM PDT 24
Finished May 12 01:31:49 PM PDT 24
Peak memory 218012 kb
Host smart-ce70dfdf-f98c-401d-a9f2-5d9f9edde971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778758420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1778758420
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1896495651
Short name T257
Test name
Test status
Simulation time 147307287 ps
CPU time 18.65 seconds
Started May 12 01:31:45 PM PDT 24
Finished May 12 01:32:04 PM PDT 24
Peak memory 250884 kb
Host smart-208bec94-049a-430a-b17f-76a282e1ef92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896495651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1896495651
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2948284500
Short name T545
Test name
Test status
Simulation time 12239534895 ps
CPU time 186.2 seconds
Started May 12 01:31:46 PM PDT 24
Finished May 12 01:34:53 PM PDT 24
Peak memory 421784 kb
Host smart-829573fa-1432-45ad-9b02-3b6391b3655b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948284500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2948284500
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.4074201255
Short name T381
Test name
Test status
Simulation time 38845690556 ps
CPU time 403.06 seconds
Started May 12 01:31:48 PM PDT 24
Finished May 12 01:38:32 PM PDT 24
Peak memory 283996 kb
Host smart-0ee1dcfb-191e-42ed-bba0-9797c96faed6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4074201255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.4074201255
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1281436488
Short name T464
Test name
Test status
Simulation time 23541234 ps
CPU time 0.84 seconds
Started May 12 01:31:45 PM PDT 24
Finished May 12 01:31:47 PM PDT 24
Peak memory 211464 kb
Host smart-a3c4b6ff-547b-4675-9a8c-1423db6bf223
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281436488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.1281436488
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2161120224
Short name T407
Test name
Test status
Simulation time 20044030 ps
CPU time 0.93 seconds
Started May 12 01:30:42 PM PDT 24
Finished May 12 01:30:44 PM PDT 24
Peak memory 209548 kb
Host smart-49e48023-d598-4a92-a327-93134e63d265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161120224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2161120224
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.2192063485
Short name T835
Test name
Test status
Simulation time 32529369 ps
CPU time 0.9 seconds
Started May 12 01:30:37 PM PDT 24
Finished May 12 01:30:39 PM PDT 24
Peak memory 209456 kb
Host smart-4f3d38e1-a21b-4c2b-bd9f-f9dc9e09a8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192063485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.2192063485
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.964455542
Short name T819
Test name
Test status
Simulation time 596844139 ps
CPU time 8.58 seconds
Started May 12 01:30:36 PM PDT 24
Finished May 12 01:30:46 PM PDT 24
Peak memory 217912 kb
Host smart-16251e81-b324-4d2d-90d8-d6767e194a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964455542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.964455542
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.290699221
Short name T24
Test name
Test status
Simulation time 603307930 ps
CPU time 7.02 seconds
Started May 12 01:30:37 PM PDT 24
Finished May 12 01:30:45 PM PDT 24
Peak memory 209772 kb
Host smart-027c9260-1cbd-4d9a-8614-7d1ecc7fcc4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290699221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.290699221
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1105151982
Short name T316
Test name
Test status
Simulation time 1426216268 ps
CPU time 25.45 seconds
Started May 12 01:30:39 PM PDT 24
Finished May 12 01:31:05 PM PDT 24
Peak memory 217948 kb
Host smart-e7474b01-87f4-431a-a8b9-51549e228f7e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105151982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1105151982
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.3277732272
Short name T827
Test name
Test status
Simulation time 130845490 ps
CPU time 4.14 seconds
Started May 12 01:30:40 PM PDT 24
Finished May 12 01:30:44 PM PDT 24
Peak memory 209528 kb
Host smart-f2115d6f-7dd9-49e6-96ce-5cb7ee909260
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277732272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.3
277732272
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3873363164
Short name T533
Test name
Test status
Simulation time 3981544855 ps
CPU time 13.36 seconds
Started May 12 01:30:37 PM PDT 24
Finished May 12 01:30:51 PM PDT 24
Peak memory 218104 kb
Host smart-f025a2b5-6c76-46e1-a9d5-01398a13afa6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873363164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3873363164
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3961545048
Short name T335
Test name
Test status
Simulation time 710007845 ps
CPU time 20.14 seconds
Started May 12 01:30:41 PM PDT 24
Finished May 12 01:31:02 PM PDT 24
Peak memory 213244 kb
Host smart-dc367563-c70c-42ce-a4ca-3945f2d8a649
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961545048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.3961545048
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1983574500
Short name T314
Test name
Test status
Simulation time 680309236 ps
CPU time 8.99 seconds
Started May 12 01:30:40 PM PDT 24
Finished May 12 01:30:49 PM PDT 24
Peak memory 213676 kb
Host smart-a8f0a455-aff1-493d-865b-7a4c79bf716a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983574500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1983574500
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2479038787
Short name T244
Test name
Test status
Simulation time 2343816577 ps
CPU time 40.69 seconds
Started May 12 01:30:37 PM PDT 24
Finished May 12 01:31:18 PM PDT 24
Peak memory 267436 kb
Host smart-1c7a06df-4dc9-49cc-a91d-fb411d55de18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479038787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2479038787
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2083791993
Short name T776
Test name
Test status
Simulation time 895890659 ps
CPU time 17.15 seconds
Started May 12 01:30:40 PM PDT 24
Finished May 12 01:30:58 PM PDT 24
Peak memory 250452 kb
Host smart-b936d2ad-8f42-419c-be7d-b8c236845ea4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083791993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2083791993
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.4292246026
Short name T778
Test name
Test status
Simulation time 116008193 ps
CPU time 1.7 seconds
Started May 12 01:30:40 PM PDT 24
Finished May 12 01:30:42 PM PDT 24
Peak memory 218016 kb
Host smart-e8c31a3e-1a90-4466-9538-b655af39f71b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292246026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.4292246026
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2335954590
Short name T332
Test name
Test status
Simulation time 201951505 ps
CPU time 13.93 seconds
Started May 12 01:30:36 PM PDT 24
Finished May 12 01:30:51 PM PDT 24
Peak memory 217788 kb
Host smart-3234f851-9b1b-4006-8d2f-ee4aefc18a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335954590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2335954590
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.220246070
Short name T271
Test name
Test status
Simulation time 321162032 ps
CPU time 10.77 seconds
Started May 12 01:30:35 PM PDT 24
Finished May 12 01:30:46 PM PDT 24
Peak memory 226080 kb
Host smart-ecf135b3-dc76-4bbc-853e-b74fdeccb5d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220246070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.220246070
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3871060240
Short name T465
Test name
Test status
Simulation time 411329437 ps
CPU time 12.41 seconds
Started May 12 01:30:38 PM PDT 24
Finished May 12 01:30:51 PM PDT 24
Peak memory 218072 kb
Host smart-618eb726-5c3c-431e-94d0-afd4c3484f56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871060240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3871060240
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3040761986
Short name T621
Test name
Test status
Simulation time 390787725 ps
CPU time 10.21 seconds
Started May 12 01:30:37 PM PDT 24
Finished May 12 01:30:48 PM PDT 24
Peak memory 218144 kb
Host smart-cb5151ed-5828-461b-b98f-4c8aaa4fd784
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040761986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
040761986
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1607390969
Short name T622
Test name
Test status
Simulation time 1162478319 ps
CPU time 9.48 seconds
Started May 12 01:30:37 PM PDT 24
Finished May 12 01:30:48 PM PDT 24
Peak memory 218008 kb
Host smart-491f621e-30cd-4e04-981b-b0a4fa27976e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607390969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1607390969
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1458661471
Short name T620
Test name
Test status
Simulation time 50856351 ps
CPU time 2.5 seconds
Started May 12 01:30:36 PM PDT 24
Finished May 12 01:30:39 PM PDT 24
Peak memory 214148 kb
Host smart-d1b714ff-9d4f-49f8-887a-35c1dc7051c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458661471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1458661471
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.725874925
Short name T632
Test name
Test status
Simulation time 990283259 ps
CPU time 27.57 seconds
Started May 12 01:30:36 PM PDT 24
Finished May 12 01:31:04 PM PDT 24
Peak memory 250692 kb
Host smart-50b73bb4-ebb9-49d2-89ab-59d99e1cc677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725874925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.725874925
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.2910321417
Short name T423
Test name
Test status
Simulation time 50951149 ps
CPU time 6.24 seconds
Started May 12 01:30:44 PM PDT 24
Finished May 12 01:30:51 PM PDT 24
Peak memory 250916 kb
Host smart-545ef924-39c7-4a2e-b7f4-2492ef7c5b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910321417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.2910321417
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.551900803
Short name T2
Test name
Test status
Simulation time 17311299471 ps
CPU time 260.11 seconds
Started May 12 01:30:40 PM PDT 24
Finished May 12 01:35:01 PM PDT 24
Peak memory 324912 kb
Host smart-1f047087-54d2-4b3f-880e-7f5a5996ac4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551900803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.551900803
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3173564915
Short name T814
Test name
Test status
Simulation time 14510619 ps
CPU time 0.83 seconds
Started May 12 01:30:38 PM PDT 24
Finished May 12 01:30:39 PM PDT 24
Peak memory 211680 kb
Host smart-0e956cf0-5359-41f5-ba82-c2f7a81089ad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173564915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3173564915
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3358165348
Short name T376
Test name
Test status
Simulation time 77820255 ps
CPU time 1.01 seconds
Started May 12 01:31:52 PM PDT 24
Finished May 12 01:31:54 PM PDT 24
Peak memory 209632 kb
Host smart-8d3436fa-5ef1-4f24-b5b1-8428826331da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358165348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3358165348
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2196205816
Short name T10
Test name
Test status
Simulation time 1309432018 ps
CPU time 8.75 seconds
Started May 12 01:31:52 PM PDT 24
Finished May 12 01:32:02 PM PDT 24
Peak memory 217976 kb
Host smart-f2be36e9-5dc1-41e3-b113-c22209a3f7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196205816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2196205816
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3719659488
Short name T176
Test name
Test status
Simulation time 2313241883 ps
CPU time 27.61 seconds
Started May 12 01:31:52 PM PDT 24
Finished May 12 01:32:21 PM PDT 24
Peak memory 217208 kb
Host smart-845ff254-699e-4bf3-99d1-9f939e97157d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719659488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3719659488
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.3306065262
Short name T608
Test name
Test status
Simulation time 860699393 ps
CPU time 2.79 seconds
Started May 12 01:31:51 PM PDT 24
Finished May 12 01:31:54 PM PDT 24
Peak memory 217988 kb
Host smart-cd1a0f44-5da9-4d5a-8ba4-08e34132f0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306065262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3306065262
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2535593410
Short name T846
Test name
Test status
Simulation time 3714988582 ps
CPU time 14.41 seconds
Started May 12 01:31:51 PM PDT 24
Finished May 12 01:32:06 PM PDT 24
Peak memory 218952 kb
Host smart-4e392541-8938-48a0-8b92-a6eac91be315
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535593410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2535593410
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2198717134
Short name T624
Test name
Test status
Simulation time 5505755524 ps
CPU time 14.4 seconds
Started May 12 01:31:54 PM PDT 24
Finished May 12 01:32:09 PM PDT 24
Peak memory 218004 kb
Host smart-26bb82e5-ee7f-43f2-93c1-ece809bb5674
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198717134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2198717134
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2018168861
Short name T324
Test name
Test status
Simulation time 305578058 ps
CPU time 11.35 seconds
Started May 12 01:31:50 PM PDT 24
Finished May 12 01:32:02 PM PDT 24
Peak memory 218084 kb
Host smart-b4df4fe2-4b57-4517-9a00-576b52391eb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018168861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2018168861
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1277817524
Short name T517
Test name
Test status
Simulation time 365039783 ps
CPU time 12.95 seconds
Started May 12 01:31:51 PM PDT 24
Finished May 12 01:32:06 PM PDT 24
Peak memory 218056 kb
Host smart-3a2bdba5-dbd0-4e31-ade6-d81d1fded95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277817524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1277817524
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3908387963
Short name T861
Test name
Test status
Simulation time 44376271 ps
CPU time 1.5 seconds
Started May 12 01:31:46 PM PDT 24
Finished May 12 01:31:48 PM PDT 24
Peak memory 213720 kb
Host smart-49a6ea85-cc08-4b28-8832-b93e3e346b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908387963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3908387963
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3652130488
Short name T871
Test name
Test status
Simulation time 1027282215 ps
CPU time 30.15 seconds
Started May 12 01:31:52 PM PDT 24
Finished May 12 01:32:24 PM PDT 24
Peak memory 248444 kb
Host smart-d7ffe337-7b4f-4d40-acd8-e0851f060b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652130488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3652130488
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2993499894
Short name T860
Test name
Test status
Simulation time 166865198 ps
CPU time 6.43 seconds
Started May 12 01:31:51 PM PDT 24
Finished May 12 01:31:58 PM PDT 24
Peak memory 246764 kb
Host smart-c55c48c9-f2b3-470f-95c7-db5663836f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993499894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2993499894
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.4235688977
Short name T821
Test name
Test status
Simulation time 8781990707 ps
CPU time 64.27 seconds
Started May 12 01:31:49 PM PDT 24
Finished May 12 01:32:54 PM PDT 24
Peak memory 275236 kb
Host smart-0caad357-861e-4972-bbbf-7c61548a722c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235688977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.4235688977
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.446690852
Short name T378
Test name
Test status
Simulation time 17872531 ps
CPU time 0.84 seconds
Started May 12 01:31:50 PM PDT 24
Finished May 12 01:31:51 PM PDT 24
Peak memory 208356 kb
Host smart-91c8689e-f03c-418c-aa16-647fd2cb022e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446690852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.446690852
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3720634898
Short name T749
Test name
Test status
Simulation time 21328630 ps
CPU time 1.17 seconds
Started May 12 01:31:55 PM PDT 24
Finished May 12 01:31:57 PM PDT 24
Peak memory 209464 kb
Host smart-eee84755-55f1-46d7-839f-6093713b0dd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720634898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3720634898
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3988469232
Short name T37
Test name
Test status
Simulation time 857213049 ps
CPU time 12.18 seconds
Started May 12 01:31:51 PM PDT 24
Finished May 12 01:32:04 PM PDT 24
Peak memory 217980 kb
Host smart-ff2173ee-fa0d-4784-8782-1c5321c44d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988469232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3988469232
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.3945535085
Short name T867
Test name
Test status
Simulation time 1775651620 ps
CPU time 7.49 seconds
Started May 12 01:31:55 PM PDT 24
Finished May 12 01:32:03 PM PDT 24
Peak memory 209464 kb
Host smart-a6dc084c-ce8b-43ea-9902-604d0f8e4d67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945535085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.3945535085
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.4205451166
Short name T225
Test name
Test status
Simulation time 423535717 ps
CPU time 2.95 seconds
Started May 12 01:31:52 PM PDT 24
Finished May 12 01:31:56 PM PDT 24
Peak memory 218044 kb
Host smart-91ba57a6-107d-4e71-95bd-dc3f85669dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205451166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.4205451166
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1167222415
Short name T270
Test name
Test status
Simulation time 1358914813 ps
CPU time 11.83 seconds
Started May 12 01:31:56 PM PDT 24
Finished May 12 01:32:09 PM PDT 24
Peak memory 226116 kb
Host smart-089a4d98-8daa-414c-8e6b-926009ffbe4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167222415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1167222415
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3857756996
Short name T240
Test name
Test status
Simulation time 346521626 ps
CPU time 9.61 seconds
Started May 12 01:31:54 PM PDT 24
Finished May 12 01:32:04 PM PDT 24
Peak memory 217900 kb
Host smart-033fafcd-a5b3-4e6d-99ef-d739aa091ea5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857756996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3857756996
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3937161172
Short name T86
Test name
Test status
Simulation time 618072721 ps
CPU time 11.76 seconds
Started May 12 01:31:56 PM PDT 24
Finished May 12 01:32:08 PM PDT 24
Peak memory 218016 kb
Host smart-62b44996-f60b-49b1-948c-01d830875d35
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937161172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3937161172
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2713095968
Short name T636
Test name
Test status
Simulation time 451038812 ps
CPU time 9.77 seconds
Started May 12 01:31:56 PM PDT 24
Finished May 12 01:32:07 PM PDT 24
Peak memory 218036 kb
Host smart-9ed6ef1a-3ee3-4780-b880-aeb2e0d0d1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713095968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2713095968
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.2403898355
Short name T512
Test name
Test status
Simulation time 146514341 ps
CPU time 3.71 seconds
Started May 12 01:31:51 PM PDT 24
Finished May 12 01:31:56 PM PDT 24
Peak memory 214324 kb
Host smart-17303561-d58b-4c9d-98b0-067c736b2e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403898355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2403898355
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3909905282
Short name T356
Test name
Test status
Simulation time 387221056 ps
CPU time 26.66 seconds
Started May 12 01:31:50 PM PDT 24
Finished May 12 01:32:17 PM PDT 24
Peak memory 248204 kb
Host smart-35704d89-bbcc-4e6c-85b1-696360a1d3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909905282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3909905282
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1926256556
Short name T365
Test name
Test status
Simulation time 2121325144 ps
CPU time 8.06 seconds
Started May 12 01:31:51 PM PDT 24
Finished May 12 01:31:59 PM PDT 24
Peak memory 243716 kb
Host smart-b02f9a9d-6bb5-4b8a-810c-968083801b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926256556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1926256556
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.1868635291
Short name T76
Test name
Test status
Simulation time 3825695251 ps
CPU time 121.22 seconds
Started May 12 01:31:54 PM PDT 24
Finished May 12 01:33:56 PM PDT 24
Peak memory 251024 kb
Host smart-112a8b4e-3824-49d2-ab84-60f8a8d759b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868635291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.1868635291
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3189563139
Short name T233
Test name
Test status
Simulation time 18807717 ps
CPU time 1.15 seconds
Started May 12 01:31:50 PM PDT 24
Finished May 12 01:31:52 PM PDT 24
Peak memory 212948 kb
Host smart-4181fe67-6e73-4515-b8df-2769267e265e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189563139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3189563139
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2186977878
Short name T510
Test name
Test status
Simulation time 46228823 ps
CPU time 0.82 seconds
Started May 12 01:31:55 PM PDT 24
Finished May 12 01:31:57 PM PDT 24
Peak memory 209412 kb
Host smart-589d92d5-d5de-45d9-be22-ad50f292fcbf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186977878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2186977878
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2874557154
Short name T666
Test name
Test status
Simulation time 500713997 ps
CPU time 11.4 seconds
Started May 12 01:31:53 PM PDT 24
Finished May 12 01:32:05 PM PDT 24
Peak memory 218008 kb
Host smart-1893e503-7345-499c-9cda-8371c6ca7f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874557154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2874557154
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.4200645653
Short name T718
Test name
Test status
Simulation time 221015184 ps
CPU time 6.17 seconds
Started May 12 01:31:53 PM PDT 24
Finished May 12 01:32:00 PM PDT 24
Peak memory 209456 kb
Host smart-f1e8a22a-7b8e-4aba-966a-bd38cbf007e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200645653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.4200645653
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.608506239
Short name T738
Test name
Test status
Simulation time 82443108 ps
CPU time 3.96 seconds
Started May 12 01:31:53 PM PDT 24
Finished May 12 01:31:58 PM PDT 24
Peak memory 218008 kb
Host smart-9b44c0e8-1e45-4987-a024-eace0e3d9289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608506239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.608506239
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2835426360
Short name T722
Test name
Test status
Simulation time 1543022682 ps
CPU time 11.31 seconds
Started May 12 01:31:56 PM PDT 24
Finished May 12 01:32:08 PM PDT 24
Peak memory 218496 kb
Host smart-5c5fea8f-7d89-4282-a4ea-862456bda3c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835426360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2835426360
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.4093709125
Short name T489
Test name
Test status
Simulation time 1882294152 ps
CPU time 13.5 seconds
Started May 12 01:31:54 PM PDT 24
Finished May 12 01:32:08 PM PDT 24
Peak memory 218056 kb
Host smart-46bb7ea3-88f2-40c7-a648-43572724bcab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093709125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.4093709125
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2616174179
Short name T447
Test name
Test status
Simulation time 691601338 ps
CPU time 7.64 seconds
Started May 12 01:31:54 PM PDT 24
Finished May 12 01:32:03 PM PDT 24
Peak memory 218004 kb
Host smart-7a228c49-fe77-4e5e-bd66-f9777a664434
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616174179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2616174179
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1177093100
Short name T389
Test name
Test status
Simulation time 1763305469 ps
CPU time 9.54 seconds
Started May 12 01:31:55 PM PDT 24
Finished May 12 01:32:05 PM PDT 24
Peak memory 218144 kb
Host smart-6d5acd69-98a0-46b3-9d05-7fc87e98a300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177093100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1177093100
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1654957415
Short name T371
Test name
Test status
Simulation time 403513014 ps
CPU time 1.82 seconds
Started May 12 01:31:55 PM PDT 24
Finished May 12 01:31:58 PM PDT 24
Peak memory 213856 kb
Host smart-95acacfc-3440-4f92-8bbf-a375ceb7654e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654957415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1654957415
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3619410394
Short name T424
Test name
Test status
Simulation time 1126372656 ps
CPU time 20.78 seconds
Started May 12 01:31:55 PM PDT 24
Finished May 12 01:32:16 PM PDT 24
Peak memory 250084 kb
Host smart-9c3a9a8d-8095-46e8-9bef-caacb9e52b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619410394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3619410394
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2933177779
Short name T354
Test name
Test status
Simulation time 256493971 ps
CPU time 8.55 seconds
Started May 12 01:31:57 PM PDT 24
Finished May 12 01:32:06 PM PDT 24
Peak memory 250644 kb
Host smart-964e6875-cdde-406e-9e58-d3880e24cd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933177779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2933177779
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.324876219
Short name T823
Test name
Test status
Simulation time 18915393405 ps
CPU time 291.36 seconds
Started May 12 01:31:55 PM PDT 24
Finished May 12 01:36:47 PM PDT 24
Peak memory 250672 kb
Host smart-b426805a-a6fd-43a5-9065-5fa3ecbca8ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324876219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.324876219
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.1988024156
Short name T136
Test name
Test status
Simulation time 68488636487 ps
CPU time 691.79 seconds
Started May 12 01:31:54 PM PDT 24
Finished May 12 01:43:27 PM PDT 24
Peak memory 464160 kb
Host smart-1ff25677-916a-4ae9-922f-734ccddeb79e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1988024156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.1988024156
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.991948393
Short name T595
Test name
Test status
Simulation time 28000464 ps
CPU time 0.74 seconds
Started May 12 01:31:55 PM PDT 24
Finished May 12 01:31:57 PM PDT 24
Peak memory 206852 kb
Host smart-7a275435-b90e-423c-bb2c-59acf618cbb4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991948393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.991948393
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1674832032
Short name T334
Test name
Test status
Simulation time 23157427 ps
CPU time 0.96 seconds
Started May 12 01:31:57 PM PDT 24
Finished May 12 01:31:59 PM PDT 24
Peak memory 209520 kb
Host smart-2cd3c74f-c573-494b-86e4-fd613047f218
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674832032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1674832032
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2034674298
Short name T546
Test name
Test status
Simulation time 1368517738 ps
CPU time 15.16 seconds
Started May 12 01:31:56 PM PDT 24
Finished May 12 01:32:12 PM PDT 24
Peak memory 218080 kb
Host smart-35c7da5f-8d01-45fd-a58e-3c0ac00b635a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034674298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2034674298
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.4100123503
Short name T25
Test name
Test status
Simulation time 1222506593 ps
CPU time 4.58 seconds
Started May 12 01:31:57 PM PDT 24
Finished May 12 01:32:03 PM PDT 24
Peak memory 209548 kb
Host smart-d900633a-dd39-470c-bef9-812c3136ccb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100123503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.4100123503
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3813959154
Short name T775
Test name
Test status
Simulation time 82453981 ps
CPU time 1.81 seconds
Started May 12 01:31:58 PM PDT 24
Finished May 12 01:32:00 PM PDT 24
Peak memory 218012 kb
Host smart-76e54db9-3b7e-4c7a-bbe0-339ec3a24d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813959154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3813959154
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3909527646
Short name T403
Test name
Test status
Simulation time 291396306 ps
CPU time 11.98 seconds
Started May 12 01:31:58 PM PDT 24
Finished May 12 01:32:10 PM PDT 24
Peak memory 218936 kb
Host smart-f728fcc8-8df3-478d-a761-0678ec9bcaae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909527646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3909527646
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3340775256
Short name T792
Test name
Test status
Simulation time 477171191 ps
CPU time 9.31 seconds
Started May 12 01:31:58 PM PDT 24
Finished May 12 01:32:08 PM PDT 24
Peak memory 218000 kb
Host smart-71561e36-bc20-4ef1-ab6f-62110cabf969
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340775256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3340775256
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.495157688
Short name T538
Test name
Test status
Simulation time 5020678460 ps
CPU time 9.62 seconds
Started May 12 01:31:58 PM PDT 24
Finished May 12 01:32:08 PM PDT 24
Peak memory 218180 kb
Host smart-9590672a-e1ff-49af-8dfb-b9bd39b72078
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495157688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.495157688
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.59492146
Short name T67
Test name
Test status
Simulation time 51737098 ps
CPU time 2.89 seconds
Started May 12 01:31:57 PM PDT 24
Finished May 12 01:32:00 PM PDT 24
Peak memory 214428 kb
Host smart-cbc7ef9d-a179-47f0-899d-ae956b5c78d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59492146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.59492146
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.518238290
Short name T367
Test name
Test status
Simulation time 664831755 ps
CPU time 33.62 seconds
Started May 12 01:31:57 PM PDT 24
Finished May 12 01:32:31 PM PDT 24
Peak memory 248644 kb
Host smart-7498eda4-3dac-4909-bc17-4d44e574efd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518238290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.518238290
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2001489084
Short name T833
Test name
Test status
Simulation time 387440379 ps
CPU time 5.61 seconds
Started May 12 01:31:54 PM PDT 24
Finished May 12 01:32:00 PM PDT 24
Peak memory 222468 kb
Host smart-b454526d-5964-45c6-b150-73c82845395f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001489084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2001489084
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3982256959
Short name T725
Test name
Test status
Simulation time 45967262128 ps
CPU time 387.34 seconds
Started May 12 01:31:58 PM PDT 24
Finished May 12 01:38:26 PM PDT 24
Peak memory 251000 kb
Host smart-0de5710a-1d76-4309-9ff5-780d5722a6f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982256959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3982256959
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.781455086
Short name T132
Test name
Test status
Simulation time 157037317265 ps
CPU time 702.91 seconds
Started May 12 01:31:57 PM PDT 24
Finished May 12 01:43:41 PM PDT 24
Peak memory 316756 kb
Host smart-efef9a54-3cdf-463f-83ae-71d544c37330
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=781455086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.781455086
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.776539393
Short name T548
Test name
Test status
Simulation time 13086956 ps
CPU time 0.87 seconds
Started May 12 01:31:54 PM PDT 24
Finished May 12 01:31:55 PM PDT 24
Peak memory 211628 kb
Host smart-2e167f3e-d6dc-4a2d-8254-270efe94301b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776539393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ct
rl_volatile_unlock_smoke.776539393
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3528451235
Short name T824
Test name
Test status
Simulation time 58589654 ps
CPU time 1.04 seconds
Started May 12 01:32:02 PM PDT 24
Finished May 12 01:32:04 PM PDT 24
Peak memory 209292 kb
Host smart-d1b7b65c-d318-475b-a050-5e4df3e4de54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528451235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3528451235
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.589689382
Short name T802
Test name
Test status
Simulation time 483292009 ps
CPU time 12.43 seconds
Started May 12 01:31:58 PM PDT 24
Finished May 12 01:32:11 PM PDT 24
Peak memory 218004 kb
Host smart-19a5eccf-dc2e-4174-83c8-a311acec20cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589689382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.589689382
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1810203015
Short name T490
Test name
Test status
Simulation time 290089432 ps
CPU time 2.18 seconds
Started May 12 01:32:00 PM PDT 24
Finished May 12 01:32:03 PM PDT 24
Peak memory 217976 kb
Host smart-6be24284-6401-49b2-b472-b65ac66e04f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810203015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1810203015
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2144538640
Short name T504
Test name
Test status
Simulation time 1114429060 ps
CPU time 9.87 seconds
Started May 12 01:32:01 PM PDT 24
Finished May 12 01:32:12 PM PDT 24
Peak memory 226088 kb
Host smart-bf3e655e-c905-4de1-8a39-b61b35e3e270
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144538640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2144538640
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1216434298
Short name T416
Test name
Test status
Simulation time 903093190 ps
CPU time 9.42 seconds
Started May 12 01:32:02 PM PDT 24
Finished May 12 01:32:13 PM PDT 24
Peak memory 217652 kb
Host smart-41742d53-cb4a-4616-a56e-00eda12e6a21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216434298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1216434298
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1354325966
Short name T20
Test name
Test status
Simulation time 513588506 ps
CPU time 10.22 seconds
Started May 12 01:32:01 PM PDT 24
Finished May 12 01:32:12 PM PDT 24
Peak memory 218032 kb
Host smart-a582c3c3-d237-4cca-8958-492e8d0164d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354325966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1354325966
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3998379110
Short name T328
Test name
Test status
Simulation time 3182996883 ps
CPU time 9.5 seconds
Started May 12 01:32:01 PM PDT 24
Finished May 12 01:32:12 PM PDT 24
Peak memory 218128 kb
Host smart-57cb8c50-026c-41cf-ab82-b37b76af6e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998379110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3998379110
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2692259865
Short name T52
Test name
Test status
Simulation time 85441408 ps
CPU time 6.09 seconds
Started May 12 01:31:57 PM PDT 24
Finished May 12 01:32:04 PM PDT 24
Peak memory 217788 kb
Host smart-118296cd-7ffa-4e5a-a91f-d0bc599021d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692259865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2692259865
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1420621804
Short name T719
Test name
Test status
Simulation time 271626913 ps
CPU time 36.21 seconds
Started May 12 01:31:57 PM PDT 24
Finished May 12 01:32:34 PM PDT 24
Peak memory 250740 kb
Host smart-e12d8d75-400d-4c15-985d-5733fb7f908f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420621804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1420621804
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.1848167480
Short name T781
Test name
Test status
Simulation time 110527858 ps
CPU time 8.53 seconds
Started May 12 01:31:57 PM PDT 24
Finished May 12 01:32:07 PM PDT 24
Peak memory 250684 kb
Host smart-38fd3a12-b01e-4136-97d1-cb68659b3cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848167480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.1848167480
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3733592694
Short name T175
Test name
Test status
Simulation time 9522915627 ps
CPU time 150.5 seconds
Started May 12 01:32:03 PM PDT 24
Finished May 12 01:34:34 PM PDT 24
Peak memory 251072 kb
Host smart-96e8b375-9c0b-4d49-92e9-2661421bf66a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733592694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3733592694
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2718852637
Short name T689
Test name
Test status
Simulation time 11146276 ps
CPU time 0.88 seconds
Started May 12 01:31:57 PM PDT 24
Finished May 12 01:31:59 PM PDT 24
Peak memory 211600 kb
Host smart-94099202-07df-4217-a2b0-6ceefe074b8a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718852637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2718852637
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1873622678
Short name T66
Test name
Test status
Simulation time 92551119 ps
CPU time 1.15 seconds
Started May 12 01:32:08 PM PDT 24
Finished May 12 01:32:10 PM PDT 24
Peak memory 209572 kb
Host smart-987158ec-39c7-4d5d-8f00-3dc2e9e1b21c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873622678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1873622678
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3291657025
Short name T789
Test name
Test status
Simulation time 419651144 ps
CPU time 16.07 seconds
Started May 12 01:32:02 PM PDT 24
Finished May 12 01:32:19 PM PDT 24
Peak memory 218056 kb
Host smart-49ccfd5c-7062-455b-915c-fe28b7980c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291657025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3291657025
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3438297975
Short name T243
Test name
Test status
Simulation time 69994326 ps
CPU time 2.54 seconds
Started May 12 01:32:02 PM PDT 24
Finished May 12 01:32:05 PM PDT 24
Peak memory 209528 kb
Host smart-cdfa6776-840f-4279-95b4-ebe90695f24f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438297975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3438297975
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.326131330
Short name T675
Test name
Test status
Simulation time 106735729 ps
CPU time 1.82 seconds
Started May 12 01:32:00 PM PDT 24
Finished May 12 01:32:03 PM PDT 24
Peak memory 217976 kb
Host smart-444ff89d-8dae-4451-b59d-94c4fb7f229e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326131330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.326131330
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.425206232
Short name T333
Test name
Test status
Simulation time 953277716 ps
CPU time 11.2 seconds
Started May 12 01:32:01 PM PDT 24
Finished May 12 01:32:12 PM PDT 24
Peak memory 226064 kb
Host smart-6e917daa-9d7f-4ad7-b062-dd70aa29ebe4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425206232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.425206232
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.567374833
Short name T844
Test name
Test status
Simulation time 213288985 ps
CPU time 10.01 seconds
Started May 12 01:32:07 PM PDT 24
Finished May 12 01:32:18 PM PDT 24
Peak memory 217852 kb
Host smart-76eaf69e-15ae-49a6-9539-64e907ec1867
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567374833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.567374833
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2681807226
Short name T248
Test name
Test status
Simulation time 314877362 ps
CPU time 7.86 seconds
Started May 12 01:32:02 PM PDT 24
Finished May 12 01:32:11 PM PDT 24
Peak memory 218008 kb
Host smart-19b9a3d9-5399-4680-8796-31f0e43ec4f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681807226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2681807226
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1476871620
Short name T667
Test name
Test status
Simulation time 318876032 ps
CPU time 7.49 seconds
Started May 12 01:31:59 PM PDT 24
Finished May 12 01:32:07 PM PDT 24
Peak memory 218008 kb
Host smart-231b74d5-c5da-48b4-aa01-af52faa5a142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476871620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1476871620
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.4024317126
Short name T62
Test name
Test status
Simulation time 21023587 ps
CPU time 1.6 seconds
Started May 12 01:32:00 PM PDT 24
Finished May 12 01:32:02 PM PDT 24
Peak memory 213580 kb
Host smart-77d07e11-abe1-4b0c-a4b2-35c39d09317e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024317126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.4024317126
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2882605592
Short name T470
Test name
Test status
Simulation time 367249394 ps
CPU time 26.49 seconds
Started May 12 01:32:02 PM PDT 24
Finished May 12 01:32:29 PM PDT 24
Peak memory 249636 kb
Host smart-a32ab105-3027-406e-981b-95a1e06ae83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882605592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2882605592
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.413558001
Short name T525
Test name
Test status
Simulation time 200164028 ps
CPU time 7.81 seconds
Started May 12 01:32:00 PM PDT 24
Finished May 12 01:32:09 PM PDT 24
Peak memory 244344 kb
Host smart-7a1f315b-f702-4ac4-bc02-57bf9d69ac2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413558001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.413558001
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.894940241
Short name T363
Test name
Test status
Simulation time 61036957 ps
CPU time 1.02 seconds
Started May 12 01:32:02 PM PDT 24
Finished May 12 01:32:04 PM PDT 24
Peak memory 212784 kb
Host smart-b319d163-d619-4d38-8d9e-827f20bc5d6c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894940241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ct
rl_volatile_unlock_smoke.894940241
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.3626458536
Short name T840
Test name
Test status
Simulation time 71450638 ps
CPU time 0.93 seconds
Started May 12 01:32:06 PM PDT 24
Finished May 12 01:32:08 PM PDT 24
Peak memory 209460 kb
Host smart-1945e591-ba52-4da6-a2e0-245a7f9fd60c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626458536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.3626458536
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1350282033
Short name T724
Test name
Test status
Simulation time 423323229 ps
CPU time 13.07 seconds
Started May 12 01:32:04 PM PDT 24
Finished May 12 01:32:18 PM PDT 24
Peak memory 218020 kb
Host smart-6c35996f-9a0b-44de-a4b5-df9c3743f598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350282033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1350282033
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1407059513
Short name T847
Test name
Test status
Simulation time 1087885477 ps
CPU time 4.26 seconds
Started May 12 01:32:05 PM PDT 24
Finished May 12 01:32:10 PM PDT 24
Peak memory 209496 kb
Host smart-af5b0a42-d54c-449a-8b4c-3af812b84b9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407059513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1407059513
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.4092356902
Short name T140
Test name
Test status
Simulation time 174462668 ps
CPU time 4.09 seconds
Started May 12 01:32:03 PM PDT 24
Finished May 12 01:32:08 PM PDT 24
Peak memory 217956 kb
Host smart-52a03530-bd73-4d3c-b65e-ce58a72f33cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092356902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.4092356902
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.3983173277
Short name T805
Test name
Test status
Simulation time 1167344494 ps
CPU time 13.35 seconds
Started May 12 01:32:05 PM PDT 24
Finished May 12 01:32:19 PM PDT 24
Peak memory 226080 kb
Host smart-11f120de-abb9-42f9-a082-2df15bbafb63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983173277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3983173277
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3634691659
Short name T373
Test name
Test status
Simulation time 331525453 ps
CPU time 14.52 seconds
Started May 12 01:32:07 PM PDT 24
Finished May 12 01:32:22 PM PDT 24
Peak memory 218004 kb
Host smart-8afd5623-2226-416c-91df-af34a4668709
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634691659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3634691659
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3992442401
Short name T614
Test name
Test status
Simulation time 1067633632 ps
CPU time 6.71 seconds
Started May 12 01:32:07 PM PDT 24
Finished May 12 01:32:14 PM PDT 24
Peak memory 217896 kb
Host smart-f0fc425b-ca39-4fdd-ba22-0990a42d6a7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992442401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3992442401
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3467820630
Short name T138
Test name
Test status
Simulation time 16832848 ps
CPU time 1.38 seconds
Started May 12 01:32:06 PM PDT 24
Finished May 12 01:32:08 PM PDT 24
Peak memory 213540 kb
Host smart-cf79b134-65dd-4fdb-bb13-c35508d69eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467820630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3467820630
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.369477435
Short name T468
Test name
Test status
Simulation time 392982608 ps
CPU time 36.56 seconds
Started May 12 01:32:06 PM PDT 24
Finished May 12 01:32:43 PM PDT 24
Peak memory 250852 kb
Host smart-0c9702a9-35c0-4a57-92da-c3908fcd98eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369477435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.369477435
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3968758834
Short name T856
Test name
Test status
Simulation time 102436495 ps
CPU time 6.74 seconds
Started May 12 01:32:06 PM PDT 24
Finished May 12 01:32:14 PM PDT 24
Peak memory 246648 kb
Host smart-71694ccb-e72a-4be8-8525-b4e37df76fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968758834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3968758834
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.747496218
Short name T432
Test name
Test status
Simulation time 13526480 ps
CPU time 1.12 seconds
Started May 12 01:32:09 PM PDT 24
Finished May 12 01:32:11 PM PDT 24
Peak memory 211588 kb
Host smart-4681a0ff-e922-4a29-9e12-c8e783cbf47d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747496218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.747496218
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.612734327
Short name T803
Test name
Test status
Simulation time 32470922 ps
CPU time 0.99 seconds
Started May 12 01:32:08 PM PDT 24
Finished May 12 01:32:10 PM PDT 24
Peak memory 209584 kb
Host smart-2c9910a1-2969-4441-93f4-b9db369df716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612734327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.612734327
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.906702525
Short name T676
Test name
Test status
Simulation time 722009810 ps
CPU time 16.2 seconds
Started May 12 01:32:15 PM PDT 24
Finished May 12 01:32:32 PM PDT 24
Peak memory 217492 kb
Host smart-bbe78cdd-ec42-4bb8-b838-01ee5a240d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906702525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.906702525
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.116963650
Short name T297
Test name
Test status
Simulation time 86560094 ps
CPU time 2.93 seconds
Started May 12 01:32:08 PM PDT 24
Finished May 12 01:32:11 PM PDT 24
Peak memory 209536 kb
Host smart-6d29b692-1b0e-4227-9adc-8bf612bde711
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116963650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.116963650
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3399131447
Short name T680
Test name
Test status
Simulation time 249798433 ps
CPU time 2.96 seconds
Started May 12 01:32:07 PM PDT 24
Finished May 12 01:32:11 PM PDT 24
Peak memory 218092 kb
Host smart-add2d341-b8ba-4d42-803d-5eba20446df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399131447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3399131447
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.1404057085
Short name T645
Test name
Test status
Simulation time 2332566090 ps
CPU time 13.25 seconds
Started May 12 01:32:06 PM PDT 24
Finished May 12 01:32:20 PM PDT 24
Peak memory 219012 kb
Host smart-31330933-2c61-4c7f-ad80-720df0a57b56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404057085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.1404057085
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1776045081
Short name T282
Test name
Test status
Simulation time 226280150 ps
CPU time 10.7 seconds
Started May 12 01:32:07 PM PDT 24
Finished May 12 01:32:18 PM PDT 24
Peak memory 217820 kb
Host smart-a2a68efd-499d-4654-ba20-7a40fd8efc5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776045081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1776045081
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1507537606
Short name T442
Test name
Test status
Simulation time 779232515 ps
CPU time 13.05 seconds
Started May 12 01:32:15 PM PDT 24
Finished May 12 01:32:29 PM PDT 24
Peak memory 217936 kb
Host smart-d3d61545-99a3-4fab-abb1-4a23e89eb565
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507537606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1507537606
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.299464436
Short name T286
Test name
Test status
Simulation time 219484161 ps
CPU time 6.5 seconds
Started May 12 01:32:15 PM PDT 24
Finished May 12 01:32:22 PM PDT 24
Peak memory 217520 kb
Host smart-338d9f67-45c9-47d3-9bb0-e958429afcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299464436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.299464436
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.103914598
Short name T152
Test name
Test status
Simulation time 337337486 ps
CPU time 1.62 seconds
Started May 12 01:32:09 PM PDT 24
Finished May 12 01:32:11 PM PDT 24
Peak memory 217748 kb
Host smart-c5f21c9e-2458-47c2-b492-285beb47321d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103914598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.103914598
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.3929424679
Short name T485
Test name
Test status
Simulation time 1267512235 ps
CPU time 21.73 seconds
Started May 12 01:32:10 PM PDT 24
Finished May 12 01:32:32 PM PDT 24
Peak memory 250624 kb
Host smart-70923b8f-f168-4b49-92ab-d6e405b6b21a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929424679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.3929424679
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1229712055
Short name T852
Test name
Test status
Simulation time 179402463 ps
CPU time 9.85 seconds
Started May 12 01:32:09 PM PDT 24
Finished May 12 01:32:19 PM PDT 24
Peak memory 250940 kb
Host smart-cf733844-b710-4040-8c76-fe92ad489573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229712055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1229712055
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.1240974843
Short name T39
Test name
Test status
Simulation time 355589240339 ps
CPU time 438.44 seconds
Started May 12 01:32:08 PM PDT 24
Finished May 12 01:39:27 PM PDT 24
Peak memory 316956 kb
Host smart-dc57f8cf-e2cd-43d7-beae-ff130926c7b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1240974843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.1240974843
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.4283838974
Short name T153
Test name
Test status
Simulation time 79487389 ps
CPU time 1.26 seconds
Started May 12 01:32:09 PM PDT 24
Finished May 12 01:32:10 PM PDT 24
Peak memory 212736 kb
Host smart-47cd3bad-4ff3-4290-ab06-e79a19b7b304
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283838974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.4283838974
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.70325069
Short name T142
Test name
Test status
Simulation time 14790137 ps
CPU time 0.85 seconds
Started May 12 01:32:11 PM PDT 24
Finished May 12 01:32:13 PM PDT 24
Peak memory 209280 kb
Host smart-5f0497de-522b-4bed-8137-c6c6a24500fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70325069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.70325069
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.1777496009
Short name T708
Test name
Test status
Simulation time 328164068 ps
CPU time 15.77 seconds
Started May 12 01:32:10 PM PDT 24
Finished May 12 01:32:26 PM PDT 24
Peak memory 217908 kb
Host smart-199252fd-86a4-479c-878c-725cd9d73aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777496009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.1777496009
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3237764820
Short name T315
Test name
Test status
Simulation time 97200954 ps
CPU time 3.05 seconds
Started May 12 01:32:10 PM PDT 24
Finished May 12 01:32:14 PM PDT 24
Peak memory 209540 kb
Host smart-9beaa3d6-659c-41f1-aaf1-629cbaaad10c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237764820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3237764820
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2249273229
Short name T748
Test name
Test status
Simulation time 40751975 ps
CPU time 1.51 seconds
Started May 12 01:32:07 PM PDT 24
Finished May 12 01:32:09 PM PDT 24
Peak memory 217932 kb
Host smart-df6b0994-fa67-47d5-ae59-2f186ae37759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249273229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2249273229
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.377330643
Short name T458
Test name
Test status
Simulation time 1408866073 ps
CPU time 14.89 seconds
Started May 12 01:32:13 PM PDT 24
Finished May 12 01:32:28 PM PDT 24
Peak memory 218128 kb
Host smart-1925b438-6105-4057-8773-18e86ee5d16a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377330643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.377330643
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1255143039
Short name T655
Test name
Test status
Simulation time 286323897 ps
CPU time 9.68 seconds
Started May 12 01:32:13 PM PDT 24
Finished May 12 01:32:23 PM PDT 24
Peak memory 217980 kb
Host smart-cf7c00c3-8404-419e-bfce-3515215a9ee2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255143039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1255143039
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1457892823
Short name T405
Test name
Test status
Simulation time 288778936 ps
CPU time 8.84 seconds
Started May 12 01:32:15 PM PDT 24
Finished May 12 01:32:25 PM PDT 24
Peak memory 217936 kb
Host smart-7f1aaec2-052b-4a32-952a-33011fb4ab1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457892823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1457892823
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3974279830
Short name T48
Test name
Test status
Simulation time 471919561 ps
CPU time 6.79 seconds
Started May 12 01:32:15 PM PDT 24
Finished May 12 01:32:23 PM PDT 24
Peak memory 217904 kb
Host smart-fc9aeaa7-46f8-45e7-980e-78eb299a18d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974279830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3974279830
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1176717942
Short name T348
Test name
Test status
Simulation time 331943324 ps
CPU time 2.69 seconds
Started May 12 01:32:08 PM PDT 24
Finished May 12 01:32:12 PM PDT 24
Peak memory 214276 kb
Host smart-a4613612-e600-49e0-a92c-d922486f6efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176717942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1176717942
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3223984932
Short name T590
Test name
Test status
Simulation time 431944502 ps
CPU time 20.25 seconds
Started May 12 01:32:07 PM PDT 24
Finished May 12 01:32:28 PM PDT 24
Peak memory 245656 kb
Host smart-f61f7740-d751-4ef7-9845-defc0e622fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223984932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3223984932
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1876835734
Short name T1
Test name
Test status
Simulation time 217034784 ps
CPU time 7.43 seconds
Started May 12 01:32:08 PM PDT 24
Finished May 12 01:32:16 PM PDT 24
Peak memory 250980 kb
Host smart-f11a7be4-1e19-4512-82b1-5af35cac453c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876835734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1876835734
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3623188035
Short name T276
Test name
Test status
Simulation time 13932505928 ps
CPU time 81.48 seconds
Started May 12 01:32:11 PM PDT 24
Finished May 12 01:33:34 PM PDT 24
Peak memory 269832 kb
Host smart-27162765-a716-4e22-b74f-1692091f1e1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623188035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3623188035
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.967040603
Short name T322
Test name
Test status
Simulation time 13829851 ps
CPU time 1.08 seconds
Started May 12 01:32:08 PM PDT 24
Finished May 12 01:32:09 PM PDT 24
Peak memory 211540 kb
Host smart-68337a6b-b4ed-4129-939c-43d78692b01a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967040603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ct
rl_volatile_unlock_smoke.967040603
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2908986753
Short name T82
Test name
Test status
Simulation time 15331759 ps
CPU time 0.94 seconds
Started May 12 01:32:18 PM PDT 24
Finished May 12 01:32:19 PM PDT 24
Peak memory 209552 kb
Host smart-af27884e-c3c3-479b-9971-39d3539df96b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908986753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2908986753
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.4217850669
Short name T723
Test name
Test status
Simulation time 1024505553 ps
CPU time 9.29 seconds
Started May 12 01:32:13 PM PDT 24
Finished May 12 01:32:23 PM PDT 24
Peak memory 217980 kb
Host smart-a9435922-cecb-466f-8e12-4bade2e36071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217850669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.4217850669
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2354421850
Short name T576
Test name
Test status
Simulation time 781460201 ps
CPU time 19.61 seconds
Started May 12 01:32:11 PM PDT 24
Finished May 12 01:32:32 PM PDT 24
Peak memory 209548 kb
Host smart-bf4d8b64-2238-46e5-969e-641e5043c211
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354421850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2354421850
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3156870553
Short name T773
Test name
Test status
Simulation time 209098800 ps
CPU time 4.56 seconds
Started May 12 01:32:12 PM PDT 24
Finished May 12 01:32:17 PM PDT 24
Peak memory 217876 kb
Host smart-ca6baa72-413a-4a67-87d3-c86db0985d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156870553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3156870553
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3571913109
Short name T54
Test name
Test status
Simulation time 1122884011 ps
CPU time 10.59 seconds
Started May 12 01:32:13 PM PDT 24
Finished May 12 01:32:24 PM PDT 24
Peak memory 226044 kb
Host smart-679cecdc-f02c-4272-9ecc-b6490ee6d0f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571913109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3571913109
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2757573643
Short name T593
Test name
Test status
Simulation time 2080833554 ps
CPU time 13 seconds
Started May 12 01:32:11 PM PDT 24
Finished May 12 01:32:24 PM PDT 24
Peak memory 226060 kb
Host smart-9e52f9b5-16b2-46ec-80e5-ea5c356ba775
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757573643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2757573643
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3612478962
Short name T634
Test name
Test status
Simulation time 594985748 ps
CPU time 7.57 seconds
Started May 12 01:32:14 PM PDT 24
Finished May 12 01:32:23 PM PDT 24
Peak memory 218048 kb
Host smart-4037158a-31b2-43e0-aa17-0eb729cb93d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612478962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3612478962
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.4087577991
Short name T777
Test name
Test status
Simulation time 2313533385 ps
CPU time 10.61 seconds
Started May 12 01:32:16 PM PDT 24
Finished May 12 01:32:27 PM PDT 24
Peak memory 218092 kb
Host smart-cd86d4f5-648d-4793-8877-85fb764da8d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087577991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.4087577991
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2869341720
Short name T604
Test name
Test status
Simulation time 26579482 ps
CPU time 1.6 seconds
Started May 12 01:32:11 PM PDT 24
Finished May 12 01:32:13 PM PDT 24
Peak memory 217732 kb
Host smart-30d2b897-33a7-4964-ae41-e44dbb62b358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869341720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2869341720
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1990950067
Short name T682
Test name
Test status
Simulation time 243477504 ps
CPU time 23.35 seconds
Started May 12 01:32:15 PM PDT 24
Finished May 12 01:32:39 PM PDT 24
Peak memory 250840 kb
Host smart-b015b127-926e-4ea4-b1a6-e151b54f8870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990950067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1990950067
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2137966946
Short name T215
Test name
Test status
Simulation time 222313329 ps
CPU time 3.51 seconds
Started May 12 01:32:14 PM PDT 24
Finished May 12 01:32:18 PM PDT 24
Peak memory 222372 kb
Host smart-9ec3a83c-95d9-4b4e-9e5a-44358b103524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137966946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2137966946
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1518245607
Short name T151
Test name
Test status
Simulation time 24152552481 ps
CPU time 191.99 seconds
Started May 12 01:32:17 PM PDT 24
Finished May 12 01:35:30 PM PDT 24
Peak memory 267504 kb
Host smart-95327c70-1e01-40ce-a1b3-6146b7804b8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518245607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1518245607
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.603381839
Short name T278
Test name
Test status
Simulation time 14941079 ps
CPU time 1.06 seconds
Started May 12 01:32:15 PM PDT 24
Finished May 12 01:32:17 PM PDT 24
Peak memory 212640 kb
Host smart-f3be67d8-5b54-4fad-875f-02440e3eca93
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603381839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.603381839
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.940953083
Short name T445
Test name
Test status
Simulation time 27292704 ps
CPU time 1.05 seconds
Started May 12 01:30:46 PM PDT 24
Finished May 12 01:30:47 PM PDT 24
Peak memory 209588 kb
Host smart-34af6b1d-014a-490e-bc09-f9336c2f8076
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940953083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.940953083
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1059859234
Short name T591
Test name
Test status
Simulation time 321817858 ps
CPU time 9.73 seconds
Started May 12 01:30:41 PM PDT 24
Finished May 12 01:30:51 PM PDT 24
Peak memory 218040 kb
Host smart-44a6e9e9-1628-4cd9-b1f2-d2e5f0b7aadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059859234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1059859234
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2126636274
Short name T8
Test name
Test status
Simulation time 574238759 ps
CPU time 4.12 seconds
Started May 12 01:30:50 PM PDT 24
Finished May 12 01:30:54 PM PDT 24
Peak memory 209464 kb
Host smart-3e3ebfb9-7476-4daf-b9d6-6809ce7bd8b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126636274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2126636274
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1095158911
Short name T296
Test name
Test status
Simulation time 17600919413 ps
CPU time 32.55 seconds
Started May 12 01:30:50 PM PDT 24
Finished May 12 01:31:22 PM PDT 24
Peak memory 219004 kb
Host smart-3c0ec92a-7a2a-4ca3-95a9-e343ecb4f149
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095158911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1095158911
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2210719920
Short name T519
Test name
Test status
Simulation time 482652992 ps
CPU time 6.19 seconds
Started May 12 01:30:49 PM PDT 24
Finished May 12 01:30:56 PM PDT 24
Peak memory 217052 kb
Host smart-b4a4a631-b010-4639-b5f4-2b478cef2128
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210719920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
210719920
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.3204248857
Short name T401
Test name
Test status
Simulation time 495670493 ps
CPU time 2.48 seconds
Started May 12 01:30:42 PM PDT 24
Finished May 12 01:30:45 PM PDT 24
Peak memory 218088 kb
Host smart-94888418-5a42-4442-a4de-3e1f4ca85734
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204248857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.3204248857
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1924975879
Short name T573
Test name
Test status
Simulation time 4201671142 ps
CPU time 34.11 seconds
Started May 12 01:30:50 PM PDT 24
Finished May 12 01:31:25 PM PDT 24
Peak memory 214044 kb
Host smart-d34af875-0925-48c1-8fa9-98f16a2fefb7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924975879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1924975879
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1484741685
Short name T154
Test name
Test status
Simulation time 259376702 ps
CPU time 7.8 seconds
Started May 12 01:30:42 PM PDT 24
Finished May 12 01:30:50 PM PDT 24
Peak memory 213840 kb
Host smart-74cad7e9-be3e-4dd2-9b5a-db15117def91
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484741685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1484741685
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.4159653877
Short name T526
Test name
Test status
Simulation time 1822733779 ps
CPU time 52.26 seconds
Started May 12 01:30:44 PM PDT 24
Finished May 12 01:31:36 PM PDT 24
Peak memory 275280 kb
Host smart-9183c99c-2be5-4e9a-b1b5-cb9bceaf02d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159653877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.4159653877
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.497017510
Short name T794
Test name
Test status
Simulation time 1257213972 ps
CPU time 6.39 seconds
Started May 12 01:30:41 PM PDT 24
Finished May 12 01:30:48 PM PDT 24
Peak memory 222000 kb
Host smart-06362375-046f-47ed-8502-2cd72b179b7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497017510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.497017510
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2267574533
Short name T768
Test name
Test status
Simulation time 40189096 ps
CPU time 1.99 seconds
Started May 12 01:30:49 PM PDT 24
Finished May 12 01:30:51 PM PDT 24
Peak memory 217932 kb
Host smart-b3c32f10-1f6a-416f-ba78-9e52064624b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267574533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2267574533
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.960464303
Short name T763
Test name
Test status
Simulation time 396088848 ps
CPU time 25.46 seconds
Started May 12 01:30:50 PM PDT 24
Finished May 12 01:31:16 PM PDT 24
Peak memory 214016 kb
Host smart-3dc47903-8d36-4fe8-950a-00d7e59bc6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960464303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.960464303
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1141663105
Short name T47
Test name
Test status
Simulation time 517306624 ps
CPU time 38.06 seconds
Started May 12 01:30:42 PM PDT 24
Finished May 12 01:31:20 PM PDT 24
Peak memory 269264 kb
Host smart-6b95eed3-b247-4bd9-9f8f-83682da132a6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141663105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1141663105
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1151774141
Short name T592
Test name
Test status
Simulation time 695661509 ps
CPU time 11.79 seconds
Started May 12 01:30:39 PM PDT 24
Finished May 12 01:30:51 PM PDT 24
Peak memory 219140 kb
Host smart-8e78af2f-204e-46d9-ab76-ef7ddc3bdbf6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151774141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1151774141
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.805706853
Short name T508
Test name
Test status
Simulation time 235182595 ps
CPU time 8.42 seconds
Started May 12 01:30:42 PM PDT 24
Finished May 12 01:30:51 PM PDT 24
Peak memory 217944 kb
Host smart-38bc1d29-22ce-4bda-ad3d-d2146838cad3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805706853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig
est.805706853
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.230736743
Short name T245
Test name
Test status
Simulation time 457490149 ps
CPU time 9.43 seconds
Started May 12 01:30:40 PM PDT 24
Finished May 12 01:30:50 PM PDT 24
Peak memory 218088 kb
Host smart-c4488104-18b0-4aec-a07e-02a719be53fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230736743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.230736743
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.528780734
Short name T404
Test name
Test status
Simulation time 209992492 ps
CPU time 6.37 seconds
Started May 12 01:30:41 PM PDT 24
Finished May 12 01:30:48 PM PDT 24
Peak memory 218036 kb
Host smart-5696bcc5-2442-405f-ac1c-301935018381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528780734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.528780734
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1004632674
Short name T77
Test name
Test status
Simulation time 82272051 ps
CPU time 3.15 seconds
Started May 12 01:30:42 PM PDT 24
Finished May 12 01:30:46 PM PDT 24
Peak memory 217896 kb
Host smart-ba74f2a9-6ad8-4a21-a479-a0200ca99769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004632674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1004632674
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.4235941349
Short name T668
Test name
Test status
Simulation time 179859236 ps
CPU time 21.7 seconds
Started May 12 01:30:41 PM PDT 24
Finished May 12 01:31:03 PM PDT 24
Peak memory 250832 kb
Host smart-2e0c5381-a3c9-4a6b-8ad2-27c2208abfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235941349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.4235941349
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.844265348
Short name T353
Test name
Test status
Simulation time 110448910 ps
CPU time 7.21 seconds
Started May 12 01:30:40 PM PDT 24
Finished May 12 01:30:47 PM PDT 24
Peak memory 250736 kb
Host smart-9b82776b-b906-42c4-9677-99e4abb07152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844265348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.844265348
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2124514983
Short name T398
Test name
Test status
Simulation time 3634960192 ps
CPU time 107.88 seconds
Started May 12 01:30:42 PM PDT 24
Finished May 12 01:32:31 PM PDT 24
Peak memory 280820 kb
Host smart-e15c9349-2300-4b84-961c-f395e6083055
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124514983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2124514983
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.628063337
Short name T630
Test name
Test status
Simulation time 22125463 ps
CPU time 1.09 seconds
Started May 12 01:30:39 PM PDT 24
Finished May 12 01:30:41 PM PDT 24
Peak memory 211740 kb
Host smart-277354e5-23fe-42b5-addc-060d1c9fb09f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628063337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctr
l_volatile_unlock_smoke.628063337
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.897428009
Short name T872
Test name
Test status
Simulation time 606061042 ps
CPU time 10.33 seconds
Started May 12 01:32:15 PM PDT 24
Finished May 12 01:32:26 PM PDT 24
Peak memory 217896 kb
Host smart-a1cd32fd-888a-4992-9ff7-0f0b563a0336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897428009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.897428009
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.274993674
Short name T418
Test name
Test status
Simulation time 588352436 ps
CPU time 14.41 seconds
Started May 12 01:32:16 PM PDT 24
Finished May 12 01:32:31 PM PDT 24
Peak memory 217200 kb
Host smart-1e9a38a5-370e-498f-b98a-00187a174a1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274993674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.274993674
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2385453463
Short name T715
Test name
Test status
Simulation time 16407022 ps
CPU time 1.63 seconds
Started May 12 01:32:15 PM PDT 24
Finished May 12 01:32:17 PM PDT 24
Peak memory 217956 kb
Host smart-e570c57d-4995-4a03-b683-03bfd413119f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385453463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2385453463
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.937470281
Short name T496
Test name
Test status
Simulation time 791957573 ps
CPU time 13.56 seconds
Started May 12 01:32:16 PM PDT 24
Finished May 12 01:32:30 PM PDT 24
Peak memory 226080 kb
Host smart-ebf708f6-4a38-4013-a00f-62aaf020120a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937470281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.937470281
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.4062298752
Short name T427
Test name
Test status
Simulation time 593276778 ps
CPU time 12.37 seconds
Started May 12 01:32:16 PM PDT 24
Finished May 12 01:32:29 PM PDT 24
Peak memory 218000 kb
Host smart-349b5c78-dd51-40be-b4d9-ee3f17e8f7df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062298752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.4062298752
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2517429612
Short name T524
Test name
Test status
Simulation time 850701364 ps
CPU time 6.55 seconds
Started May 12 01:32:15 PM PDT 24
Finished May 12 01:32:23 PM PDT 24
Peak memory 217956 kb
Host smart-0bdecf38-3d3d-4f79-a589-92768c5c9f79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517429612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2517429612
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.2898425574
Short name T577
Test name
Test status
Simulation time 572495432 ps
CPU time 7.89 seconds
Started May 12 01:32:14 PM PDT 24
Finished May 12 01:32:23 PM PDT 24
Peak memory 218032 kb
Host smart-11f12489-c1cb-4a1b-a28b-2cf940c047d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898425574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2898425574
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.677197089
Short name T61
Test name
Test status
Simulation time 60923522 ps
CPU time 1.33 seconds
Started May 12 01:32:15 PM PDT 24
Finished May 12 01:32:17 PM PDT 24
Peak memory 213268 kb
Host smart-ca1306b6-eca0-4a32-acce-bdfb763e7893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677197089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.677197089
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.4213438616
Short name T148
Test name
Test status
Simulation time 1759395399 ps
CPU time 26.36 seconds
Started May 12 01:32:17 PM PDT 24
Finished May 12 01:32:43 PM PDT 24
Peak memory 248692 kb
Host smart-9efb1f97-d895-422c-b7c0-b21ba5919ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213438616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.4213438616
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3790301467
Short name T698
Test name
Test status
Simulation time 72621575 ps
CPU time 3.34 seconds
Started May 12 01:32:16 PM PDT 24
Finished May 12 01:32:20 PM PDT 24
Peak memory 226252 kb
Host smart-84c9b82c-886b-4d7d-a8fe-62925f358bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790301467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3790301467
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3618907848
Short name T674
Test name
Test status
Simulation time 15950263376 ps
CPU time 99.08 seconds
Started May 12 01:32:15 PM PDT 24
Finished May 12 01:33:55 PM PDT 24
Peak memory 284176 kb
Host smart-790c4f8a-feeb-41ce-b40c-64ad3519dfc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618907848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3618907848
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.4132379767
Short name T358
Test name
Test status
Simulation time 32384791 ps
CPU time 1.11 seconds
Started May 12 01:32:16 PM PDT 24
Finished May 12 01:32:18 PM PDT 24
Peak memory 212864 kb
Host smart-015ef52d-259b-47e2-b496-e8b5fd2ddf84
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132379767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.4132379767
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2598166663
Short name T551
Test name
Test status
Simulation time 48904622 ps
CPU time 1.07 seconds
Started May 12 01:32:29 PM PDT 24
Finished May 12 01:32:31 PM PDT 24
Peak memory 209508 kb
Host smart-ebf03075-a6e0-44d8-81ba-626cc8a8df87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598166663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2598166663
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.195741542
Short name T637
Test name
Test status
Simulation time 1135176645 ps
CPU time 9.36 seconds
Started May 12 01:32:20 PM PDT 24
Finished May 12 01:32:30 PM PDT 24
Peak memory 218020 kb
Host smart-9d41e556-d0f5-4df7-8c5a-fa5cc4299f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195741542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.195741542
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3430969408
Short name T452
Test name
Test status
Simulation time 3927737252 ps
CPU time 6.94 seconds
Started May 12 01:32:22 PM PDT 24
Finished May 12 01:32:29 PM PDT 24
Peak memory 217652 kb
Host smart-f718e7f8-f14f-4d94-bb88-352eebfecd54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430969408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3430969408
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.621682955
Short name T431
Test name
Test status
Simulation time 25617928 ps
CPU time 1.75 seconds
Started May 12 01:32:18 PM PDT 24
Finished May 12 01:32:21 PM PDT 24
Peak memory 217984 kb
Host smart-68affd92-ce2b-4441-8ca9-b3d791718bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621682955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.621682955
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2410232303
Short name T808
Test name
Test status
Simulation time 277476979 ps
CPU time 12.73 seconds
Started May 12 01:32:22 PM PDT 24
Finished May 12 01:32:35 PM PDT 24
Peak memory 226076 kb
Host smart-bc8149ce-f756-4d87-965e-d83d7afcb057
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410232303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2410232303
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1631706476
Short name T851
Test name
Test status
Simulation time 5139846713 ps
CPU time 9.19 seconds
Started May 12 01:32:29 PM PDT 24
Finished May 12 01:32:39 PM PDT 24
Peak memory 218052 kb
Host smart-5c0e9e00-0c9e-4409-a2bf-0580c9aef3cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631706476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1631706476
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2767774509
Short name T429
Test name
Test status
Simulation time 468741626 ps
CPU time 15.74 seconds
Started May 12 01:32:29 PM PDT 24
Finished May 12 01:32:46 PM PDT 24
Peak memory 217948 kb
Host smart-a2e399a3-815d-47da-ad63-bc7acefbb20f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767774509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2767774509
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.4206417174
Short name T343
Test name
Test status
Simulation time 1472998183 ps
CPU time 12.68 seconds
Started May 12 01:32:20 PM PDT 24
Finished May 12 01:32:33 PM PDT 24
Peak memory 218132 kb
Host smart-7266a366-860e-4dd3-9b10-f5a60529e1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206417174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.4206417174
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3620658276
Short name T687
Test name
Test status
Simulation time 297593722 ps
CPU time 1.38 seconds
Started May 12 01:32:19 PM PDT 24
Finished May 12 01:32:21 PM PDT 24
Peak memory 213544 kb
Host smart-571bdc22-c691-4ac7-9ecb-bd33fb88448c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620658276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3620658276
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.819589854
Short name T587
Test name
Test status
Simulation time 913251465 ps
CPU time 21.55 seconds
Started May 12 01:32:18 PM PDT 24
Finished May 12 01:32:40 PM PDT 24
Peak memory 250868 kb
Host smart-2db0d51b-f6f4-4e30-b445-bdf11069a69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819589854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.819589854
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2228834232
Short name T238
Test name
Test status
Simulation time 89123272 ps
CPU time 2.8 seconds
Started May 12 01:32:18 PM PDT 24
Finished May 12 01:32:22 PM PDT 24
Peak memory 217996 kb
Host smart-622cc77d-8388-4d06-9d92-647cdaede61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228834232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2228834232
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.3345979219
Short name T329
Test name
Test status
Simulation time 1078573256 ps
CPU time 30.54 seconds
Started May 12 01:32:29 PM PDT 24
Finished May 12 01:33:00 PM PDT 24
Peak memory 244868 kb
Host smart-89a08489-1005-4de8-8e53-08777a54253d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345979219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.3345979219
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.39557777
Short name T453
Test name
Test status
Simulation time 16108921 ps
CPU time 0.91 seconds
Started May 12 01:32:22 PM PDT 24
Finished May 12 01:32:24 PM PDT 24
Peak memory 211784 kb
Host smart-5abe2d65-4451-4913-95db-b6f334a4b71e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39557777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctr
l_volatile_unlock_smoke.39557777
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.841273774
Short name T543
Test name
Test status
Simulation time 49017521 ps
CPU time 1.06 seconds
Started May 12 01:32:29 PM PDT 24
Finished May 12 01:32:31 PM PDT 24
Peak memory 209528 kb
Host smart-e878ebd1-2b9c-4004-96f4-24f13006a244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841273774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.841273774
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2198859381
Short name T596
Test name
Test status
Simulation time 824946129 ps
CPU time 20.46 seconds
Started May 12 01:32:20 PM PDT 24
Finished May 12 01:32:41 PM PDT 24
Peak memory 217888 kb
Host smart-10d35bd3-4e81-4729-9056-63f694fde2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198859381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2198859381
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3841499027
Short name T754
Test name
Test status
Simulation time 2339153354 ps
CPU time 14.63 seconds
Started May 12 01:32:18 PM PDT 24
Finished May 12 01:32:33 PM PDT 24
Peak memory 209572 kb
Host smart-7df57633-629c-4f3d-a7cd-f106b315a55e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841499027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3841499027
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.4222578421
Short name T216
Test name
Test status
Simulation time 1393905002 ps
CPU time 3.37 seconds
Started May 12 01:32:22 PM PDT 24
Finished May 12 01:32:26 PM PDT 24
Peak memory 217900 kb
Host smart-aa53352f-290e-46e5-935e-45ad676308d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222578421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.4222578421
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.103856959
Short name T580
Test name
Test status
Simulation time 2008134070 ps
CPU time 13.71 seconds
Started May 12 01:32:21 PM PDT 24
Finished May 12 01:32:35 PM PDT 24
Peak memory 219080 kb
Host smart-e00b7782-5272-4351-bc15-adb9255d9bc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103856959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.103856959
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1452186205
Short name T502
Test name
Test status
Simulation time 1007330054 ps
CPU time 10.56 seconds
Started May 12 01:32:19 PM PDT 24
Finished May 12 01:32:30 PM PDT 24
Peak memory 218064 kb
Host smart-99df8038-a8cf-4a46-a551-529e73aa920c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452186205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1452186205
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.2767733214
Short name T809
Test name
Test status
Simulation time 371617374 ps
CPU time 14.3 seconds
Started May 12 01:32:21 PM PDT 24
Finished May 12 01:32:36 PM PDT 24
Peak memory 218100 kb
Host smart-2ae7ae48-e990-45fe-99f5-27a130da5e41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767733214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
2767733214
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.644679526
Short name T479
Test name
Test status
Simulation time 1646032035 ps
CPU time 10.16 seconds
Started May 12 01:32:23 PM PDT 24
Finished May 12 01:32:34 PM PDT 24
Peak memory 217996 kb
Host smart-ff75b3c0-9af1-4186-9aca-fff781c622bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644679526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.644679526
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2345798468
Short name T730
Test name
Test status
Simulation time 46393428 ps
CPU time 1.44 seconds
Started May 12 01:32:21 PM PDT 24
Finished May 12 01:32:23 PM PDT 24
Peak memory 217908 kb
Host smart-5c0aad7e-6522-48d6-8612-92c4ecc6f0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345798468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2345798468
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1083253083
Short name T570
Test name
Test status
Simulation time 1087777352 ps
CPU time 26.65 seconds
Started May 12 01:32:20 PM PDT 24
Finished May 12 01:32:47 PM PDT 24
Peak memory 250856 kb
Host smart-706b168a-d2e5-4bb9-bd39-e43e068f184c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083253083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1083253083
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.2847903023
Short name T663
Test name
Test status
Simulation time 308378224 ps
CPU time 6.51 seconds
Started May 12 01:32:22 PM PDT 24
Finished May 12 01:32:29 PM PDT 24
Peak memory 250972 kb
Host smart-999aa526-4c47-4c16-b9ad-886503eac2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847903023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.2847903023
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.2597469203
Short name T758
Test name
Test status
Simulation time 1104022492 ps
CPU time 53.25 seconds
Started May 12 01:32:29 PM PDT 24
Finished May 12 01:33:23 PM PDT 24
Peak memory 250912 kb
Host smart-f5771be0-eb44-4e7f-8221-7f9a4dd60a0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597469203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.2597469203
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2480507821
Short name T695
Test name
Test status
Simulation time 92307401788 ps
CPU time 447.65 seconds
Started May 12 01:32:23 PM PDT 24
Finished May 12 01:39:52 PM PDT 24
Peak memory 373008 kb
Host smart-0794088b-5bc9-4f59-98ee-57f42394560c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2480507821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.2480507821
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.580239213
Short name T497
Test name
Test status
Simulation time 10771331 ps
CPU time 0.84 seconds
Started May 12 01:32:23 PM PDT 24
Finished May 12 01:32:25 PM PDT 24
Peak memory 211508 kb
Host smart-0d4aa459-4ee3-4693-9f1a-22bf414ee0c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580239213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.580239213
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.757291856
Short name T505
Test name
Test status
Simulation time 68581799 ps
CPU time 1.02 seconds
Started May 12 01:32:23 PM PDT 24
Finished May 12 01:32:25 PM PDT 24
Peak memory 209524 kb
Host smart-ffda088a-e2ac-4466-bf9b-419877304b81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757291856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.757291856
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1254991633
Short name T569
Test name
Test status
Simulation time 3210651419 ps
CPU time 17.51 seconds
Started May 12 01:32:21 PM PDT 24
Finished May 12 01:32:39 PM PDT 24
Peak memory 219008 kb
Host smart-33d605be-b7d1-44d5-937e-38e1576d46f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254991633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1254991633
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3306193581
Short name T321
Test name
Test status
Simulation time 314367120 ps
CPU time 4.66 seconds
Started May 12 01:32:24 PM PDT 24
Finished May 12 01:32:29 PM PDT 24
Peak memory 209464 kb
Host smart-045ca823-1064-4bfb-8121-a6915d349537
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306193581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3306193581
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.910812752
Short name T774
Test name
Test status
Simulation time 222638641 ps
CPU time 2.23 seconds
Started May 12 01:32:23 PM PDT 24
Finished May 12 01:32:26 PM PDT 24
Peak memory 218004 kb
Host smart-2cf765fc-f11f-4a0e-adbc-8cb8511340c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910812752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.910812752
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.3049319339
Short name T417
Test name
Test status
Simulation time 2541926017 ps
CPU time 13.56 seconds
Started May 12 01:32:21 PM PDT 24
Finished May 12 01:32:35 PM PDT 24
Peak memory 226140 kb
Host smart-14435c44-efb9-46b2-a15f-398b0758d3fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049319339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.3049319339
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3152404916
Short name T448
Test name
Test status
Simulation time 1394224143 ps
CPU time 11.18 seconds
Started May 12 01:32:22 PM PDT 24
Finished May 12 01:32:34 PM PDT 24
Peak memory 218028 kb
Host smart-d4f09ecb-803d-4ffc-a2db-ed04819723b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152404916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3152404916
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.327269503
Short name T483
Test name
Test status
Simulation time 955072186 ps
CPU time 9.52 seconds
Started May 12 01:32:23 PM PDT 24
Finished May 12 01:32:33 PM PDT 24
Peak memory 217996 kb
Host smart-aad7d3c0-eb42-4bc8-85e6-145f07a2ce27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327269503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.327269503
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3588227621
Short name T692
Test name
Test status
Simulation time 1323129808 ps
CPU time 10.62 seconds
Started May 12 01:32:23 PM PDT 24
Finished May 12 01:32:34 PM PDT 24
Peak memory 218128 kb
Host smart-f19b2ec2-7aff-4ec9-832b-c878ac5ae873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588227621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3588227621
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.262887296
Short name T588
Test name
Test status
Simulation time 37770578 ps
CPU time 1.17 seconds
Started May 12 01:32:21 PM PDT 24
Finished May 12 01:32:23 PM PDT 24
Peak memory 213172 kb
Host smart-3c44e01e-3b5d-45bd-a6b0-f4a97b8bb235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262887296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.262887296
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3128665359
Short name T302
Test name
Test status
Simulation time 267186771 ps
CPU time 25.83 seconds
Started May 12 01:32:24 PM PDT 24
Finished May 12 01:32:50 PM PDT 24
Peak memory 250640 kb
Host smart-8bcd1705-0ad0-48dc-b336-4dcf639ef31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128665359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3128665359
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1120444599
Short name T795
Test name
Test status
Simulation time 71035103 ps
CPU time 8.34 seconds
Started May 12 01:32:22 PM PDT 24
Finished May 12 01:32:31 PM PDT 24
Peak memory 250948 kb
Host smart-4c64c764-f0b1-4c8e-828c-c604e4b7541b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120444599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1120444599
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.939004135
Short name T41
Test name
Test status
Simulation time 26639640332 ps
CPU time 1079.83 seconds
Started May 12 01:32:24 PM PDT 24
Finished May 12 01:50:25 PM PDT 24
Peak memory 283656 kb
Host smart-d0306de2-f404-4589-be6f-c3a6c4d3fee2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=939004135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.939004135
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.831098372
Short name T474
Test name
Test status
Simulation time 46821288 ps
CPU time 1.02 seconds
Started May 12 01:32:24 PM PDT 24
Finished May 12 01:32:25 PM PDT 24
Peak memory 211544 kb
Host smart-8fab4bad-3a2b-4fec-98f2-10f8279a3892
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831098372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.831098372
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2740616100
Short name T252
Test name
Test status
Simulation time 58314770 ps
CPU time 0.98 seconds
Started May 12 01:32:26 PM PDT 24
Finished May 12 01:32:28 PM PDT 24
Peak memory 209524 kb
Host smart-083fe2b1-5a08-4ab0-816e-b4b1bd10723d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740616100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2740616100
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2747235044
Short name T435
Test name
Test status
Simulation time 1564323796 ps
CPU time 12.81 seconds
Started May 12 01:32:27 PM PDT 24
Finished May 12 01:32:40 PM PDT 24
Peak memory 218156 kb
Host smart-132a0227-bfa2-4786-adf0-b3619460d70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747235044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2747235044
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.1325145283
Short name T733
Test name
Test status
Simulation time 374058767 ps
CPU time 6.09 seconds
Started May 12 01:32:26 PM PDT 24
Finished May 12 01:32:32 PM PDT 24
Peak memory 216912 kb
Host smart-dbec9977-eb72-4aed-b721-b76693f38ee9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325145283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.1325145283
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2121333078
Short name T307
Test name
Test status
Simulation time 62717155 ps
CPU time 2.43 seconds
Started May 12 01:32:27 PM PDT 24
Finished May 12 01:32:30 PM PDT 24
Peak memory 218044 kb
Host smart-4e57c19e-73d3-4d9b-a7b8-f56fc8548fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121333078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2121333078
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.971750025
Short name T385
Test name
Test status
Simulation time 1134717020 ps
CPU time 10.66 seconds
Started May 12 01:32:29 PM PDT 24
Finished May 12 01:32:41 PM PDT 24
Peak memory 217988 kb
Host smart-18aa0070-b8a2-4b43-bb0c-f27a56d1595f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971750025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.971750025
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.812934406
Short name T480
Test name
Test status
Simulation time 2032231166 ps
CPU time 10.62 seconds
Started May 12 01:32:26 PM PDT 24
Finished May 12 01:32:37 PM PDT 24
Peak memory 217936 kb
Host smart-7d63a3f7-5c29-4400-9e6b-5df798963657
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812934406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.812934406
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.74206296
Short name T326
Test name
Test status
Simulation time 867648511 ps
CPU time 9.48 seconds
Started May 12 01:32:28 PM PDT 24
Finished May 12 01:32:38 PM PDT 24
Peak memory 217932 kb
Host smart-46ddbc52-3acc-465f-9f85-1d872658bc9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74206296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.74206296
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.4075014603
Short name T255
Test name
Test status
Simulation time 417964553 ps
CPU time 6.46 seconds
Started May 12 01:32:27 PM PDT 24
Finished May 12 01:32:34 PM PDT 24
Peak memory 218064 kb
Host smart-0046e9e6-79b6-4d2f-84d4-0e8b74ececa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075014603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.4075014603
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.345861594
Short name T810
Test name
Test status
Simulation time 82297946 ps
CPU time 1.92 seconds
Started May 12 01:32:23 PM PDT 24
Finished May 12 01:32:25 PM PDT 24
Peak memory 213540 kb
Host smart-9ac9ad62-d241-416a-8c72-b8a05a3a389f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345861594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.345861594
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2513503017
Short name T550
Test name
Test status
Simulation time 1218364225 ps
CPU time 21.93 seconds
Started May 12 01:32:24 PM PDT 24
Finished May 12 01:32:47 PM PDT 24
Peak memory 250932 kb
Host smart-305879ec-08ec-4625-9fc0-cfdf2acdb8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513503017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2513503017
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2186657611
Short name T812
Test name
Test status
Simulation time 189796215 ps
CPU time 3.07 seconds
Started May 12 01:32:22 PM PDT 24
Finished May 12 01:32:26 PM PDT 24
Peak memory 222176 kb
Host smart-e97ae1f4-d887-4eb6-b8d2-6e5734c4c4ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186657611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2186657611
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2606116518
Short name T319
Test name
Test status
Simulation time 5758478606 ps
CPU time 204.72 seconds
Started May 12 01:32:27 PM PDT 24
Finished May 12 01:35:52 PM PDT 24
Peak memory 283864 kb
Host smart-f3daa326-579b-4679-bb9f-f10a3499b0f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606116518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2606116518
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2287289573
Short name T362
Test name
Test status
Simulation time 13258111 ps
CPU time 1.04 seconds
Started May 12 01:32:26 PM PDT 24
Finished May 12 01:32:27 PM PDT 24
Peak memory 211596 kb
Host smart-7c9fdf3a-ac27-45f9-8546-381cd7e17960
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287289573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2287289573
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.1915970341
Short name T544
Test name
Test status
Simulation time 39150855 ps
CPU time 1.3 seconds
Started May 12 01:32:27 PM PDT 24
Finished May 12 01:32:29 PM PDT 24
Peak memory 209796 kb
Host smart-e63fb006-da64-4af9-b6cb-f8cb3d1e7958
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915970341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.1915970341
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.2663978211
Short name T673
Test name
Test status
Simulation time 866921836 ps
CPU time 10.72 seconds
Started May 12 01:32:28 PM PDT 24
Finished May 12 01:32:39 PM PDT 24
Peak memory 218088 kb
Host smart-2e92a190-0c41-40b4-82ea-886b0c041bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663978211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2663978211
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.209389203
Short name T149
Test name
Test status
Simulation time 180240337 ps
CPU time 4.53 seconds
Started May 12 01:32:29 PM PDT 24
Finished May 12 01:32:34 PM PDT 24
Peak memory 216724 kb
Host smart-380f8a75-eb2e-4fe9-9e48-ec334d8b0b3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209389203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.209389203
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.4175610564
Short name T669
Test name
Test status
Simulation time 49806120 ps
CPU time 2.13 seconds
Started May 12 01:32:27 PM PDT 24
Finished May 12 01:32:29 PM PDT 24
Peak memory 217944 kb
Host smart-a12a20fe-f92d-4229-b9d2-bd54b4b45b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175610564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.4175610564
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2216849919
Short name T55
Test name
Test status
Simulation time 2643083016 ps
CPU time 16.28 seconds
Started May 12 01:32:26 PM PDT 24
Finished May 12 01:32:43 PM PDT 24
Peak memory 219072 kb
Host smart-a34d7289-ee54-49cb-a02e-2a82e4b2f7dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216849919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2216849919
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1926603847
Short name T13
Test name
Test status
Simulation time 424863637 ps
CPU time 9.58 seconds
Started May 12 01:32:26 PM PDT 24
Finished May 12 01:32:36 PM PDT 24
Peak memory 217956 kb
Host smart-0ba11eb7-a6b1-45d5-ba55-28cbea7c7606
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926603847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.1926603847
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.559347838
Short name T226
Test name
Test status
Simulation time 358683172 ps
CPU time 8.32 seconds
Started May 12 01:32:27 PM PDT 24
Finished May 12 01:32:36 PM PDT 24
Peak memory 218036 kb
Host smart-dfb85068-34cb-4586-9598-18ae35fb218e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559347838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.559347838
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.330165080
Short name T672
Test name
Test status
Simulation time 1493996799 ps
CPU time 13.6 seconds
Started May 12 01:32:26 PM PDT 24
Finished May 12 01:32:40 PM PDT 24
Peak memory 218032 kb
Host smart-edcd0cc2-6275-4291-99ec-3b18ef17755b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330165080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.330165080
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3392935828
Short name T242
Test name
Test status
Simulation time 32701064 ps
CPU time 2.3 seconds
Started May 12 01:32:26 PM PDT 24
Finished May 12 01:32:29 PM PDT 24
Peak memory 213880 kb
Host smart-b10342a0-2fa7-4897-9180-ca5e678b29d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392935828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3392935828
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3124754085
Short name T752
Test name
Test status
Simulation time 327312592 ps
CPU time 35.17 seconds
Started May 12 01:32:25 PM PDT 24
Finished May 12 01:33:00 PM PDT 24
Peak memory 248800 kb
Host smart-efeb8947-ad77-43f4-8384-0bd9fdc6c3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124754085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3124754085
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1517610093
Short name T251
Test name
Test status
Simulation time 133384845 ps
CPU time 4.76 seconds
Started May 12 01:32:27 PM PDT 24
Finished May 12 01:32:32 PM PDT 24
Peak memory 226408 kb
Host smart-342fee19-2bdf-4886-8b8d-b2dc349f28d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517610093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1517610093
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3406693952
Short name T42
Test name
Test status
Simulation time 7352390238 ps
CPU time 154.31 seconds
Started May 12 01:32:25 PM PDT 24
Finished May 12 01:35:00 PM PDT 24
Peak memory 372848 kb
Host smart-e330eae9-5570-4d94-85cb-01b523859df7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406693952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3406693952
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1842321811
Short name T49
Test name
Test status
Simulation time 18718056740 ps
CPU time 382.44 seconds
Started May 12 01:32:30 PM PDT 24
Finished May 12 01:38:53 PM PDT 24
Peak memory 438368 kb
Host smart-922b97e6-ef8f-4165-9c47-23c9a0cf147d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1842321811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1842321811
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1318107826
Short name T842
Test name
Test status
Simulation time 46531526 ps
CPU time 0.92 seconds
Started May 12 01:32:28 PM PDT 24
Finished May 12 01:32:30 PM PDT 24
Peak memory 211616 kb
Host smart-c12d93b3-5891-4035-a448-fa9ec4200e29
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318107826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1318107826
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.66321772
Short name T223
Test name
Test status
Simulation time 19158117 ps
CPU time 1.19 seconds
Started May 12 01:32:31 PM PDT 24
Finished May 12 01:32:33 PM PDT 24
Peak memory 209476 kb
Host smart-98922274-645a-4da0-ae4a-0cc2db854a1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66321772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.66321772
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.355841072
Short name T487
Test name
Test status
Simulation time 843614962 ps
CPU time 12.67 seconds
Started May 12 01:32:31 PM PDT 24
Finished May 12 01:32:44 PM PDT 24
Peak memory 217936 kb
Host smart-9c8a020f-7f1b-4711-8377-1edc760d8c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355841072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.355841072
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1918189022
Short name T633
Test name
Test status
Simulation time 173260388 ps
CPU time 2.83 seconds
Started May 12 01:32:29 PM PDT 24
Finished May 12 01:32:33 PM PDT 24
Peak memory 216904 kb
Host smart-f6e9a536-2c17-40c4-a08a-24f0a803f50f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918189022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1918189022
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3848446037
Short name T811
Test name
Test status
Simulation time 130132167 ps
CPU time 3.83 seconds
Started May 12 01:32:33 PM PDT 24
Finished May 12 01:32:38 PM PDT 24
Peak memory 218044 kb
Host smart-542ffcd5-8242-4914-b4ee-c989e96684ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848446037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3848446037
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.255150672
Short name T506
Test name
Test status
Simulation time 766274614 ps
CPU time 15.37 seconds
Started May 12 01:32:33 PM PDT 24
Finished May 12 01:32:49 PM PDT 24
Peak memory 226016 kb
Host smart-9f69dcd5-57f5-4c0b-9ca1-b0c30c00a88e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255150672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.255150672
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1655364938
Short name T174
Test name
Test status
Simulation time 430384637 ps
CPU time 11 seconds
Started May 12 01:32:29 PM PDT 24
Finished May 12 01:32:41 PM PDT 24
Peak memory 217976 kb
Host smart-6fff9bb2-583f-45f6-81cd-d759a8f8ffaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655364938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1655364938
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2860214059
Short name T746
Test name
Test status
Simulation time 1757358695 ps
CPU time 13.97 seconds
Started May 12 01:32:32 PM PDT 24
Finished May 12 01:32:46 PM PDT 24
Peak memory 218000 kb
Host smart-e4b66eef-1bb3-414b-8e9f-33d7f75c2574
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860214059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2860214059
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1255340409
Short name T793
Test name
Test status
Simulation time 1566822250 ps
CPU time 14.98 seconds
Started May 12 01:32:31 PM PDT 24
Finished May 12 01:32:46 PM PDT 24
Peak memory 218068 kb
Host smart-775dc61c-bc89-434e-a2e5-8c77b27179b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255340409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1255340409
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3286971913
Short name T454
Test name
Test status
Simulation time 43351555 ps
CPU time 2.58 seconds
Started May 12 01:32:31 PM PDT 24
Finished May 12 01:32:35 PM PDT 24
Peak memory 213960 kb
Host smart-0146a93e-2a5d-4050-bc87-1431591ee0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286971913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3286971913
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3416734073
Short name T235
Test name
Test status
Simulation time 229009014 ps
CPU time 18.64 seconds
Started May 12 01:32:31 PM PDT 24
Finished May 12 01:32:51 PM PDT 24
Peak memory 248460 kb
Host smart-d1df2349-15b8-4954-a0fa-baba1781bc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416734073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3416734073
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.1161159411
Short name T232
Test name
Test status
Simulation time 67041112 ps
CPU time 6.55 seconds
Started May 12 01:32:29 PM PDT 24
Finished May 12 01:32:37 PM PDT 24
Peak memory 250748 kb
Host smart-819f0489-855b-46ff-a936-bfc02adf610b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161159411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1161159411
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.3620526933
Short name T434
Test name
Test status
Simulation time 11817451310 ps
CPU time 28.9 seconds
Started May 12 01:32:30 PM PDT 24
Finished May 12 01:33:00 PM PDT 24
Peak memory 226220 kb
Host smart-484f4555-cc4d-4d22-8f48-10292d7079fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620526933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.3620526933
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.2400247426
Short name T133
Test name
Test status
Simulation time 230746116917 ps
CPU time 326.43 seconds
Started May 12 01:32:31 PM PDT 24
Finished May 12 01:37:59 PM PDT 24
Peak memory 284372 kb
Host smart-d08b04a0-8d75-45f5-92ab-fe6c6dd6bbd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2400247426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.2400247426
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1872058241
Short name T670
Test name
Test status
Simulation time 30523659 ps
CPU time 0.99 seconds
Started May 12 01:32:32 PM PDT 24
Finished May 12 01:32:34 PM PDT 24
Peak memory 211628 kb
Host smart-85e9fb0e-d1b4-4b06-a19f-3204bfb37637
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872058241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1872058241
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.4062233197
Short name T33
Test name
Test status
Simulation time 19204788 ps
CPU time 0.94 seconds
Started May 12 01:32:38 PM PDT 24
Finished May 12 01:32:39 PM PDT 24
Peak memory 209516 kb
Host smart-c9e75990-f6f1-4b55-8065-519b4c9ac249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062233197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.4062233197
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.188617055
Short name T710
Test name
Test status
Simulation time 573189075 ps
CPU time 6.84 seconds
Started May 12 01:32:30 PM PDT 24
Finished May 12 01:32:38 PM PDT 24
Peak memory 209536 kb
Host smart-bae7a4ac-5846-41e9-9fcd-b19d836553d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188617055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.188617055
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.4149420465
Short name T239
Test name
Test status
Simulation time 141927335 ps
CPU time 4.25 seconds
Started May 12 01:32:32 PM PDT 24
Finished May 12 01:32:37 PM PDT 24
Peak memory 218000 kb
Host smart-463aa356-98d3-427f-8a00-203b768b7dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149420465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.4149420465
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.4142114374
Short name T397
Test name
Test status
Simulation time 608895415 ps
CPU time 23.37 seconds
Started May 12 01:32:29 PM PDT 24
Finished May 12 01:32:53 PM PDT 24
Peak memory 218892 kb
Host smart-aec6bb0e-0a07-49eb-bc48-6ae5118650ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142114374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.4142114374
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2965839754
Short name T753
Test name
Test status
Simulation time 1363502487 ps
CPU time 9.72 seconds
Started May 12 01:32:29 PM PDT 24
Finished May 12 01:32:40 PM PDT 24
Peak memory 218000 kb
Host smart-948160f1-9629-47b6-b135-e0a4e4e00fae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965839754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2965839754
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1637238903
Short name T798
Test name
Test status
Simulation time 953739074 ps
CPU time 8.92 seconds
Started May 12 01:32:29 PM PDT 24
Finished May 12 01:32:39 PM PDT 24
Peak memory 218028 kb
Host smart-c3d0478d-7666-4109-91c5-d344ddb84105
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637238903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1637238903
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3571084683
Short name T488
Test name
Test status
Simulation time 289428698 ps
CPU time 11.77 seconds
Started May 12 01:32:35 PM PDT 24
Finished May 12 01:32:48 PM PDT 24
Peak memory 218204 kb
Host smart-de91b71b-b0a2-4023-8d13-32c4f802dcc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571084683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3571084683
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2423665586
Short name T826
Test name
Test status
Simulation time 18845674 ps
CPU time 1.55 seconds
Started May 12 01:32:29 PM PDT 24
Finished May 12 01:32:32 PM PDT 24
Peak memory 213508 kb
Host smart-ba826e55-5340-4b95-96c5-cc655b8efd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423665586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2423665586
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.1589806914
Short name T561
Test name
Test status
Simulation time 209493905 ps
CPU time 25.97 seconds
Started May 12 01:32:30 PM PDT 24
Finished May 12 01:32:57 PM PDT 24
Peak memory 249604 kb
Host smart-4b37dbb0-2370-4fbd-ac92-35c9c790b364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589806914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.1589806914
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1356210836
Short name T274
Test name
Test status
Simulation time 93360527 ps
CPU time 6.7 seconds
Started May 12 01:32:31 PM PDT 24
Finished May 12 01:32:38 PM PDT 24
Peak memory 246804 kb
Host smart-b40d96f1-455c-4bcf-9291-5ea2a8909023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356210836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1356210836
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.3773569310
Short name T559
Test name
Test status
Simulation time 3519323871 ps
CPU time 31.11 seconds
Started May 12 01:32:35 PM PDT 24
Finished May 12 01:33:07 PM PDT 24
Peak memory 221736 kb
Host smart-b7ddf9d1-5843-4834-9bd9-b990e782017b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773569310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.3773569310
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.1734705211
Short name T97
Test name
Test status
Simulation time 54543505052 ps
CPU time 407.45 seconds
Started May 12 01:32:34 PM PDT 24
Finished May 12 01:39:23 PM PDT 24
Peak memory 310608 kb
Host smart-75d0f6ef-4c66-4547-9a3c-0bdbb0fa94cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1734705211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.1734705211
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3816270808
Short name T790
Test name
Test status
Simulation time 32828006 ps
CPU time 0.92 seconds
Started May 12 01:32:29 PM PDT 24
Finished May 12 01:32:31 PM PDT 24
Peak memory 211652 kb
Host smart-08bf0926-db15-4f8d-a66e-7b3f1c511219
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816270808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3816270808
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3018722785
Short name T568
Test name
Test status
Simulation time 29688338 ps
CPU time 0.86 seconds
Started May 12 01:32:34 PM PDT 24
Finished May 12 01:32:36 PM PDT 24
Peak memory 209460 kb
Host smart-04b8ef35-edc6-4f31-8910-91f367b81d5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018722785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3018722785
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2449812655
Short name T501
Test name
Test status
Simulation time 4454493594 ps
CPU time 13.45 seconds
Started May 12 01:32:35 PM PDT 24
Finished May 12 01:32:49 PM PDT 24
Peak memory 219076 kb
Host smart-8c8bb034-d7d6-4498-b4f8-8b911fb85c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449812655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2449812655
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.4235488697
Short name T179
Test name
Test status
Simulation time 1085664221 ps
CPU time 24.41 seconds
Started May 12 01:32:34 PM PDT 24
Finished May 12 01:33:00 PM PDT 24
Peak memory 216976 kb
Host smart-fb9deb53-50b3-45c8-aeba-24188673c2a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235488697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.4235488697
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2476479119
Short name T53
Test name
Test status
Simulation time 1243404914 ps
CPU time 2.46 seconds
Started May 12 01:32:36 PM PDT 24
Finished May 12 01:32:39 PM PDT 24
Peak memory 217948 kb
Host smart-df5afd10-68e6-4621-a462-9cd01c6b8e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476479119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2476479119
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3577754753
Short name T171
Test name
Test status
Simulation time 970325523 ps
CPU time 11.01 seconds
Started May 12 01:32:34 PM PDT 24
Finished May 12 01:32:46 PM PDT 24
Peak memory 217976 kb
Host smart-d4595b2b-f242-4e11-9a50-74492670f3f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577754753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3577754753
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.563093197
Short name T11
Test name
Test status
Simulation time 178719950 ps
CPU time 8.7 seconds
Started May 12 01:32:35 PM PDT 24
Finished May 12 01:32:44 PM PDT 24
Peak memory 217888 kb
Host smart-ba35db56-9fe1-4c7e-9440-77a981413744
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563093197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_di
gest.563093197
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1603762514
Short name T84
Test name
Test status
Simulation time 188497061 ps
CPU time 8.51 seconds
Started May 12 01:32:37 PM PDT 24
Finished May 12 01:32:46 PM PDT 24
Peak memory 218012 kb
Host smart-16cffc9c-4e18-4db8-9c1b-735ee5de8d11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603762514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1603762514
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2899068050
Short name T44
Test name
Test status
Simulation time 322050661 ps
CPU time 12.05 seconds
Started May 12 01:32:35 PM PDT 24
Finished May 12 01:32:48 PM PDT 24
Peak memory 218096 kb
Host smart-81611a21-aa1d-41b8-a9a9-8e6411859457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899068050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2899068050
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.4034927222
Short name T87
Test name
Test status
Simulation time 35417743 ps
CPU time 1.48 seconds
Started May 12 01:32:33 PM PDT 24
Finished May 12 01:32:35 PM PDT 24
Peak memory 217916 kb
Host smart-76888f5d-e4d7-4c65-aca0-9e96077e36e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034927222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.4034927222
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3420430113
Short name T644
Test name
Test status
Simulation time 483965577 ps
CPU time 31.26 seconds
Started May 12 01:32:34 PM PDT 24
Finished May 12 01:33:06 PM PDT 24
Peak memory 245560 kb
Host smart-4f8609e5-ada8-4ef8-962b-fc96e30eb529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420430113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3420430113
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.107931818
Short name T320
Test name
Test status
Simulation time 617473338 ps
CPU time 6.94 seconds
Started May 12 01:32:34 PM PDT 24
Finished May 12 01:32:42 PM PDT 24
Peak memory 247220 kb
Host smart-989172ba-2a17-47a5-8615-a1161364d48a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107931818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.107931818
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.588482791
Short name T606
Test name
Test status
Simulation time 30467710300 ps
CPU time 220.66 seconds
Started May 12 01:32:42 PM PDT 24
Finished May 12 01:36:23 PM PDT 24
Peak memory 251008 kb
Host smart-4028abb7-c4ab-4a08-b570-40c007be4e85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588482791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.588482791
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.882293543
Short name T292
Test name
Test status
Simulation time 17481046 ps
CPU time 1.19 seconds
Started May 12 01:32:35 PM PDT 24
Finished May 12 01:32:37 PM PDT 24
Peak memory 212956 kb
Host smart-fc1fdb50-c658-4b19-a725-d003e28372f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882293543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.882293543
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1299698033
Short name T60
Test name
Test status
Simulation time 31067843 ps
CPU time 1 seconds
Started May 12 01:32:39 PM PDT 24
Finished May 12 01:32:41 PM PDT 24
Peak memory 209792 kb
Host smart-c5cc89f5-aaac-4d56-b578-2e3e12263f03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299698033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1299698033
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1662139651
Short name T702
Test name
Test status
Simulation time 476175238 ps
CPU time 11.52 seconds
Started May 12 01:32:44 PM PDT 24
Finished May 12 01:32:56 PM PDT 24
Peak memory 217908 kb
Host smart-da0cb39c-4350-4f62-8514-b8c5b6166101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662139651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1662139651
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2689213324
Short name T806
Test name
Test status
Simulation time 3137839378 ps
CPU time 19.29 seconds
Started May 12 01:32:37 PM PDT 24
Finished May 12 01:32:57 PM PDT 24
Peak memory 209520 kb
Host smart-2a71770e-3cfd-48b6-b3b5-2e54d43d085c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689213324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2689213324
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.765422504
Short name T410
Test name
Test status
Simulation time 80391415 ps
CPU time 2.16 seconds
Started May 12 01:32:39 PM PDT 24
Finished May 12 01:32:42 PM PDT 24
Peak memory 218008 kb
Host smart-4b6e2e31-a6f8-48f5-8cdc-da658bbc797b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765422504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.765422504
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.457877069
Short name T444
Test name
Test status
Simulation time 1028507667 ps
CPU time 21.54 seconds
Started May 12 01:32:44 PM PDT 24
Finished May 12 01:33:06 PM PDT 24
Peak memory 218860 kb
Host smart-0202fe17-ed50-4d5d-931d-87d9e677beaf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457877069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.457877069
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.255457920
Short name T482
Test name
Test status
Simulation time 558250491 ps
CPU time 12.97 seconds
Started May 12 01:32:44 PM PDT 24
Finished May 12 01:32:58 PM PDT 24
Peak memory 217904 kb
Host smart-85c8212b-b43d-4802-b710-3c06ee1236f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255457920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.255457920
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1377347098
Short name T765
Test name
Test status
Simulation time 11570898140 ps
CPU time 12.25 seconds
Started May 12 01:32:39 PM PDT 24
Finished May 12 01:32:51 PM PDT 24
Peak memory 218068 kb
Host smart-59036fe3-e090-4a20-8666-88c70bd6cd72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377347098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1377347098
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3736475628
Short name T515
Test name
Test status
Simulation time 200691257 ps
CPU time 7.69 seconds
Started May 12 01:32:36 PM PDT 24
Finished May 12 01:32:45 PM PDT 24
Peak memory 218120 kb
Host smart-1f7eead4-d252-4898-ad42-07dd2f5f92ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736475628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3736475628
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1544120144
Short name T460
Test name
Test status
Simulation time 27026985 ps
CPU time 2.21 seconds
Started May 12 01:32:33 PM PDT 24
Finished May 12 01:32:35 PM PDT 24
Peak memory 213880 kb
Host smart-a758ba01-d1a8-476d-ab9f-5c907b37864d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544120144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1544120144
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3119368210
Short name T336
Test name
Test status
Simulation time 503161608 ps
CPU time 27.18 seconds
Started May 12 01:32:35 PM PDT 24
Finished May 12 01:33:03 PM PDT 24
Peak memory 250840 kb
Host smart-3e0ab9ee-8ec0-4505-af4f-2ff02c416582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119368210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3119368210
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.847730763
Short name T461
Test name
Test status
Simulation time 427495330 ps
CPU time 6.55 seconds
Started May 12 01:32:40 PM PDT 24
Finished May 12 01:32:47 PM PDT 24
Peak memory 250968 kb
Host smart-d89176d0-fc16-4ced-bb82-8855e400aa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847730763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.847730763
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1716152356
Short name T263
Test name
Test status
Simulation time 4345058164 ps
CPU time 157.24 seconds
Started May 12 01:32:38 PM PDT 24
Finished May 12 01:35:16 PM PDT 24
Peak memory 246632 kb
Host smart-70972071-21eb-47fc-b109-ce741bc98cf4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716152356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1716152356
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1164969905
Short name T599
Test name
Test status
Simulation time 16498719 ps
CPU time 0.93 seconds
Started May 12 01:32:33 PM PDT 24
Finished May 12 01:32:35 PM PDT 24
Peak memory 212908 kb
Host smart-71015743-ce1f-438a-89bb-4c43bf658d29
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164969905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1164969905
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3632196943
Short name T351
Test name
Test status
Simulation time 22113921 ps
CPU time 0.88 seconds
Started May 12 01:30:55 PM PDT 24
Finished May 12 01:30:57 PM PDT 24
Peak memory 209400 kb
Host smart-206c38e7-5069-44e4-a667-16bcc4e90844
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632196943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3632196943
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.4053967426
Short name T169
Test name
Test status
Simulation time 5202685646 ps
CPU time 14.91 seconds
Started May 12 01:30:46 PM PDT 24
Finished May 12 01:31:02 PM PDT 24
Peak memory 218380 kb
Host smart-e8b39841-dfe7-428b-aaa8-f248e6efcf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053967426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.4053967426
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.2238019326
Short name T301
Test name
Test status
Simulation time 191398577 ps
CPU time 3.07 seconds
Started May 12 01:30:49 PM PDT 24
Finished May 12 01:30:52 PM PDT 24
Peak memory 216760 kb
Host smart-7c48237a-dffa-4487-9571-f6e17e25951a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238019326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.2238019326
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.4134146284
Short name T703
Test name
Test status
Simulation time 1891438083 ps
CPU time 31.25 seconds
Started May 12 01:30:51 PM PDT 24
Finished May 12 01:31:23 PM PDT 24
Peak memory 218108 kb
Host smart-4f9bcec7-06eb-4f16-88db-f16b8e0e5b0f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134146284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.4134146284
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2978511136
Short name T277
Test name
Test status
Simulation time 1027653101 ps
CPU time 5.63 seconds
Started May 12 01:30:50 PM PDT 24
Finished May 12 01:30:56 PM PDT 24
Peak memory 217108 kb
Host smart-9dbc1653-978d-4c79-8ea6-24c6a0c74d71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978511136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
978511136
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.971885241
Short name T709
Test name
Test status
Simulation time 399622951 ps
CPU time 7.16 seconds
Started May 12 01:30:52 PM PDT 24
Finished May 12 01:31:00 PM PDT 24
Peak memory 218024 kb
Host smart-5809d115-acbf-4301-964a-c768d8253cc4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971885241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.971885241
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.4045858383
Short name T346
Test name
Test status
Simulation time 2310828582 ps
CPU time 19.67 seconds
Started May 12 01:30:49 PM PDT 24
Finished May 12 01:31:09 PM PDT 24
Peak memory 213500 kb
Host smart-9b7ed648-033a-4c87-81fe-18589df12a3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045858383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.4045858383
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.4132760071
Short name T72
Test name
Test status
Simulation time 516074624 ps
CPU time 1.87 seconds
Started May 12 01:30:46 PM PDT 24
Finished May 12 01:30:48 PM PDT 24
Peak memory 212812 kb
Host smart-f53cf778-c30f-4445-a9da-b0e74582bc44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132760071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
4132760071
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3486339501
Short name T231
Test name
Test status
Simulation time 7602642927 ps
CPU time 52.4 seconds
Started May 12 01:30:48 PM PDT 24
Finished May 12 01:31:41 PM PDT 24
Peak memory 277804 kb
Host smart-66e2e69b-b591-4c7d-8d87-38b130e52ab2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486339501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3486339501
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1441968198
Short name T804
Test name
Test status
Simulation time 1701733332 ps
CPU time 11.22 seconds
Started May 12 01:30:50 PM PDT 24
Finished May 12 01:31:02 PM PDT 24
Peak memory 250448 kb
Host smart-2dffac75-210b-4dc5-9b50-54c33c937d62
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441968198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1441968198
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.411736040
Short name T170
Test name
Test status
Simulation time 81522956 ps
CPU time 2.59 seconds
Started May 12 01:30:45 PM PDT 24
Finished May 12 01:30:48 PM PDT 24
Peak memory 218020 kb
Host smart-9bd309b4-45f5-497c-902c-af224007d7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411736040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.411736040
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.1747756056
Short name T71
Test name
Test status
Simulation time 1255800955 ps
CPU time 7.85 seconds
Started May 12 01:30:45 PM PDT 24
Finished May 12 01:30:53 PM PDT 24
Peak memory 214324 kb
Host smart-ed5f8049-6363-410b-96ad-2fe0462feb5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747756056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.1747756056
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1294365093
Short name T81
Test name
Test status
Simulation time 511301603 ps
CPU time 24.18 seconds
Started May 12 01:30:57 PM PDT 24
Finished May 12 01:31:22 PM PDT 24
Peak memory 268904 kb
Host smart-32b6fa80-8fed-467e-b5da-9fb87d634035
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294365093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1294365093
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1606535689
Short name T164
Test name
Test status
Simulation time 411770699 ps
CPU time 13.92 seconds
Started May 12 01:31:01 PM PDT 24
Finished May 12 01:31:16 PM PDT 24
Peak memory 225996 kb
Host smart-6c24951e-d86f-414b-8ded-4528617d566b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606535689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1606535689
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.3082372009
Short name T735
Test name
Test status
Simulation time 1496548410 ps
CPU time 11.35 seconds
Started May 12 01:30:56 PM PDT 24
Finished May 12 01:31:07 PM PDT 24
Peak memory 218008 kb
Host smart-93774bb3-f89c-4954-b0a1-c322a06e32a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082372009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.3082372009
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.390619308
Short name T625
Test name
Test status
Simulation time 463972071 ps
CPU time 8.96 seconds
Started May 12 01:30:56 PM PDT 24
Finished May 12 01:31:06 PM PDT 24
Peak memory 218064 kb
Host smart-fd92ced6-96e4-443b-95c0-7c2870e33358
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390619308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.390619308
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3530246648
Short name T369
Test name
Test status
Simulation time 461177476 ps
CPU time 10.04 seconds
Started May 12 01:30:46 PM PDT 24
Finished May 12 01:30:56 PM PDT 24
Peak memory 218012 kb
Host smart-22fac80b-10c7-4b43-9ff2-88fdf6668e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530246648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3530246648
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3364427826
Short name T516
Test name
Test status
Simulation time 26396163 ps
CPU time 1.32 seconds
Started May 12 01:30:46 PM PDT 24
Finished May 12 01:30:48 PM PDT 24
Peak memory 213412 kb
Host smart-938b5aea-63da-47e2-9d2c-e416924f1e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364427826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3364427826
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3964882620
Short name T815
Test name
Test status
Simulation time 1219479994 ps
CPU time 31.79 seconds
Started May 12 01:30:44 PM PDT 24
Finished May 12 01:31:16 PM PDT 24
Peak memory 250872 kb
Host smart-d15a42b9-86fc-46a6-8370-7624e2b8b66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964882620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3964882620
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1161163459
Short name T281
Test name
Test status
Simulation time 82912279 ps
CPU time 6.79 seconds
Started May 12 01:30:44 PM PDT 24
Finished May 12 01:30:51 PM PDT 24
Peak memory 250372 kb
Host smart-c80a9f81-effa-4bf1-8452-5db5230f25a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161163459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1161163459
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1829984728
Short name T623
Test name
Test status
Simulation time 20470921965 ps
CPU time 155.91 seconds
Started May 12 01:30:55 PM PDT 24
Finished May 12 01:33:31 PM PDT 24
Peak memory 267532 kb
Host smart-70257c4c-62bb-49b9-8a90-a10d36afa346
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829984728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1829984728
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.1397261350
Short name T135
Test name
Test status
Simulation time 85733452151 ps
CPU time 770.17 seconds
Started May 12 01:30:55 PM PDT 24
Finished May 12 01:43:46 PM PDT 24
Peak memory 513216 kb
Host smart-6f054b92-64aa-4abf-b5b2-8bb077700a6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1397261350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.1397261350
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.713802106
Short name T409
Test name
Test status
Simulation time 23212693 ps
CPU time 1 seconds
Started May 12 01:30:46 PM PDT 24
Finished May 12 01:30:48 PM PDT 24
Peak memory 211544 kb
Host smart-203c57d5-0c80-4633-b2b2-6c4271f2bc7a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713802106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.713802106
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3032478486
Short name T309
Test name
Test status
Simulation time 59959293 ps
CPU time 0.9 seconds
Started May 12 01:32:40 PM PDT 24
Finished May 12 01:32:42 PM PDT 24
Peak memory 209588 kb
Host smart-a28e7d3b-f0d4-4a71-806e-3db100508bab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032478486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3032478486
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.4086634714
Short name T589
Test name
Test status
Simulation time 1779613156 ps
CPU time 14.29 seconds
Started May 12 01:32:40 PM PDT 24
Finished May 12 01:32:55 PM PDT 24
Peak memory 218016 kb
Host smart-892ebe30-d8c9-4846-a99b-ce1c990339c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086634714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.4086634714
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.74335439
Short name T318
Test name
Test status
Simulation time 393606081 ps
CPU time 9.98 seconds
Started May 12 01:32:37 PM PDT 24
Finished May 12 01:32:47 PM PDT 24
Peak memory 209520 kb
Host smart-0d77c124-3470-42e6-8a12-791124e71bf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74335439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.74335439
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1571110421
Short name T308
Test name
Test status
Simulation time 465690911 ps
CPU time 2.23 seconds
Started May 12 01:32:44 PM PDT 24
Finished May 12 01:32:47 PM PDT 24
Peak memory 217900 kb
Host smart-6f0995ce-b16a-4dfd-a5a6-449996e60d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571110421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1571110421
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.4059319175
Short name T665
Test name
Test status
Simulation time 345194165 ps
CPU time 10.47 seconds
Started May 12 01:32:44 PM PDT 24
Finished May 12 01:32:55 PM PDT 24
Peak memory 218556 kb
Host smart-c42e58a6-baaa-4c7a-9db9-598789efe788
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059319175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.4059319175
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3151729873
Short name T383
Test name
Test status
Simulation time 948720380 ps
CPU time 10.94 seconds
Started May 12 01:32:39 PM PDT 24
Finished May 12 01:32:51 PM PDT 24
Peak memory 217936 kb
Host smart-8c01e8ed-d431-42a4-aa14-cef2b4aaa46f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151729873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3151729873
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1489950080
Short name T563
Test name
Test status
Simulation time 280805348 ps
CPU time 9.12 seconds
Started May 12 01:32:41 PM PDT 24
Finished May 12 01:32:50 PM PDT 24
Peak memory 217908 kb
Host smart-f707a455-d8ec-4ff1-b50b-929a67ed92e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489950080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1489950080
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.249507468
Short name T50
Test name
Test status
Simulation time 500293813 ps
CPU time 10.34 seconds
Started May 12 01:32:38 PM PDT 24
Finished May 12 01:32:49 PM PDT 24
Peak memory 218008 kb
Host smart-97162310-e4c1-4a90-bcd6-6f0555abc19e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249507468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.249507468
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1844969076
Short name T801
Test name
Test status
Simulation time 98748773 ps
CPU time 4.52 seconds
Started May 12 01:32:44 PM PDT 24
Finished May 12 01:32:49 PM PDT 24
Peak memory 217712 kb
Host smart-6115a450-a8b1-4930-9487-cfc175b7ebdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844969076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1844969076
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.303717186
Short name T600
Test name
Test status
Simulation time 621912128 ps
CPU time 26.56 seconds
Started May 12 01:32:39 PM PDT 24
Finished May 12 01:33:06 PM PDT 24
Peak memory 250816 kb
Host smart-9797afec-7b7a-4b5c-9320-599b9cb79b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303717186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.303717186
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.547204373
Short name T841
Test name
Test status
Simulation time 560802703 ps
CPU time 7.57 seconds
Started May 12 01:32:41 PM PDT 24
Finished May 12 01:32:49 PM PDT 24
Peak memory 246252 kb
Host smart-35fee327-85bf-43b2-ad29-ac315b924358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547204373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.547204373
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3237964939
Short name T859
Test name
Test status
Simulation time 4916529633 ps
CPU time 184.42 seconds
Started May 12 01:32:39 PM PDT 24
Finished May 12 01:35:44 PM PDT 24
Peak memory 283784 kb
Host smart-5821c7d1-2ad9-46f0-a7f7-d6324d432e39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237964939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3237964939
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.2646399978
Short name T147
Test name
Test status
Simulation time 181230348595 ps
CPU time 836.54 seconds
Started May 12 01:32:39 PM PDT 24
Finished May 12 01:46:36 PM PDT 24
Peak memory 447808 kb
Host smart-f5311948-6423-44e4-80f1-a3c11928fedb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2646399978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.2646399978
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.217662532
Short name T419
Test name
Test status
Simulation time 25659984 ps
CPU time 1.15 seconds
Started May 12 01:32:37 PM PDT 24
Finished May 12 01:32:39 PM PDT 24
Peak memory 212788 kb
Host smart-774e494f-8426-486c-983a-6cdca3f8a963
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217662532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.217662532
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2913046463
Short name T650
Test name
Test status
Simulation time 16809552 ps
CPU time 0.87 seconds
Started May 12 01:32:48 PM PDT 24
Finished May 12 01:32:49 PM PDT 24
Peak memory 209540 kb
Host smart-9c8d50b3-e978-4afd-9f6d-ea49bbb26690
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913046463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2913046463
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.4123920088
Short name T402
Test name
Test status
Simulation time 2333642719 ps
CPU time 15.69 seconds
Started May 12 01:32:43 PM PDT 24
Finished May 12 01:32:59 PM PDT 24
Peak memory 218000 kb
Host smart-b7a3a7ae-204e-4189-9740-fc0eb5d6dd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123920088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.4123920088
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2599932121
Short name T304
Test name
Test status
Simulation time 1157145727 ps
CPU time 13.6 seconds
Started May 12 01:32:43 PM PDT 24
Finished May 12 01:32:57 PM PDT 24
Peak memory 217236 kb
Host smart-d6afd6d5-efb7-4054-b707-d5a17fd5746b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599932121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2599932121
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1213417552
Short name T503
Test name
Test status
Simulation time 21048891 ps
CPU time 1.84 seconds
Started May 12 01:32:45 PM PDT 24
Finished May 12 01:32:47 PM PDT 24
Peak memory 217968 kb
Host smart-0d0484da-5af6-4299-8bc8-8be57dfe6f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213417552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1213417552
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1721083611
Short name T707
Test name
Test status
Simulation time 1349896203 ps
CPU time 16.99 seconds
Started May 12 01:32:42 PM PDT 24
Finished May 12 01:32:59 PM PDT 24
Peak memory 226236 kb
Host smart-1c8b587f-04fa-47c1-8873-f2ad59df3a76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721083611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1721083611
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3448655323
Short name T426
Test name
Test status
Simulation time 2888890283 ps
CPU time 16.34 seconds
Started May 12 01:32:44 PM PDT 24
Finished May 12 01:33:02 PM PDT 24
Peak memory 218040 kb
Host smart-1e62aad2-814e-4c77-8944-f3d18c1b4b09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448655323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.3448655323
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1402915748
Short name T601
Test name
Test status
Simulation time 311574446 ps
CPU time 7.77 seconds
Started May 12 01:32:42 PM PDT 24
Finished May 12 01:32:50 PM PDT 24
Peak memory 218016 kb
Host smart-7d2f24df-a08e-4e04-a8b8-6571df3eb39e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402915748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1402915748
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.405257708
Short name T210
Test name
Test status
Simulation time 1947744310 ps
CPU time 10.52 seconds
Started May 12 01:32:44 PM PDT 24
Finished May 12 01:32:56 PM PDT 24
Peak memory 218044 kb
Host smart-428b8c12-ddda-4d32-a82d-2fb02a045a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405257708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.405257708
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.348873922
Short name T415
Test name
Test status
Simulation time 39656544 ps
CPU time 1.55 seconds
Started May 12 01:32:41 PM PDT 24
Finished May 12 01:32:43 PM PDT 24
Peak memory 217796 kb
Host smart-1defbe89-6471-487b-b893-2e9dc6870a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348873922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.348873922
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2029289253
Short name T269
Test name
Test status
Simulation time 552196884 ps
CPU time 37.02 seconds
Started May 12 01:32:40 PM PDT 24
Finished May 12 01:33:18 PM PDT 24
Peak memory 248648 kb
Host smart-b1334560-a26d-41ca-8fad-4b20f20cd018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029289253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2029289253
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1881472194
Short name T160
Test name
Test status
Simulation time 70257854 ps
CPU time 7.14 seconds
Started May 12 01:32:41 PM PDT 24
Finished May 12 01:32:48 PM PDT 24
Peak memory 250904 kb
Host smart-405e550a-0c08-4580-a94a-a1884f2166b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881472194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1881472194
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.839210235
Short name T581
Test name
Test status
Simulation time 86420931918 ps
CPU time 463.04 seconds
Started May 12 01:32:42 PM PDT 24
Finished May 12 01:40:26 PM PDT 24
Peak memory 314240 kb
Host smart-ad536819-9382-48fc-8e1e-8089ccf54877
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839210235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.839210235
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3001010667
Short name T528
Test name
Test status
Simulation time 32340970 ps
CPU time 0.88 seconds
Started May 12 01:32:42 PM PDT 24
Finished May 12 01:32:43 PM PDT 24
Peak memory 211508 kb
Host smart-e5e0acb2-e46f-4ca3-a9ba-4197d95e86f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001010667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3001010667
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1162101930
Short name T438
Test name
Test status
Simulation time 38608262 ps
CPU time 0.97 seconds
Started May 12 01:32:43 PM PDT 24
Finished May 12 01:32:45 PM PDT 24
Peak memory 209456 kb
Host smart-be637d0d-b0f8-4f48-9b80-b468c4f88552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162101930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1162101930
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3032280082
Short name T361
Test name
Test status
Simulation time 548317487 ps
CPU time 14.15 seconds
Started May 12 01:32:44 PM PDT 24
Finished May 12 01:32:59 PM PDT 24
Peak memory 218004 kb
Host smart-a10b03e3-a5f8-477f-a27f-29d66552d074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032280082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3032280082
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1870204578
Short name T737
Test name
Test status
Simulation time 680216979 ps
CPU time 7.05 seconds
Started May 12 01:32:49 PM PDT 24
Finished May 12 01:32:56 PM PDT 24
Peak memory 217080 kb
Host smart-fa0ecfdb-3b1f-456a-90e0-652ee0018c18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870204578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1870204578
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.3604333977
Short name T706
Test name
Test status
Simulation time 409698297 ps
CPU time 3.33 seconds
Started May 12 01:32:45 PM PDT 24
Finished May 12 01:32:49 PM PDT 24
Peak memory 217964 kb
Host smart-e76f8de8-55fa-4353-8136-b599f93c8610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604333977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.3604333977
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1998288657
Short name T372
Test name
Test status
Simulation time 3167927620 ps
CPU time 9.45 seconds
Started May 12 01:32:44 PM PDT 24
Finished May 12 01:32:55 PM PDT 24
Peak memory 226240 kb
Host smart-7699bc7c-23c5-4292-9a8c-71e2323c9cba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998288657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1998288657
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.3212364752
Short name T532
Test name
Test status
Simulation time 3283424017 ps
CPU time 18.86 seconds
Started May 12 01:32:49 PM PDT 24
Finished May 12 01:33:08 PM PDT 24
Peak memory 218040 kb
Host smart-c1ba04de-fc3e-4d43-ba87-c1ccc56d8f8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212364752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.3212364752
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3138952049
Short name T408
Test name
Test status
Simulation time 808337437 ps
CPU time 12.18 seconds
Started May 12 01:32:44 PM PDT 24
Finished May 12 01:32:57 PM PDT 24
Peak memory 217996 kb
Host smart-933dcc88-6294-40fa-8c8e-e9cb0f5e0675
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138952049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3138952049
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1400098402
Short name T280
Test name
Test status
Simulation time 513539337 ps
CPU time 9.62 seconds
Started May 12 01:32:41 PM PDT 24
Finished May 12 01:32:51 PM PDT 24
Peak memory 218076 kb
Host smart-d9afbb06-f517-4061-a593-d2516ab146a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400098402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1400098402
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.3509814215
Short name T230
Test name
Test status
Simulation time 139232155 ps
CPU time 2.79 seconds
Started May 12 01:32:42 PM PDT 24
Finished May 12 01:32:45 PM PDT 24
Peak memory 214360 kb
Host smart-1800b3b2-8579-416f-aed1-1a373f6ae8a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509814215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.3509814215
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3968121465
Short name T471
Test name
Test status
Simulation time 253791472 ps
CPU time 30.49 seconds
Started May 12 01:32:42 PM PDT 24
Finished May 12 01:33:13 PM PDT 24
Peak memory 250884 kb
Host smart-67885929-5c0d-412e-a33d-1e27ea951399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968121465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3968121465
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.4145188796
Short name T828
Test name
Test status
Simulation time 82824313 ps
CPU time 7.08 seconds
Started May 12 01:32:45 PM PDT 24
Finished May 12 01:32:53 PM PDT 24
Peak memory 250944 kb
Host smart-d3327ef5-f367-4428-bf4f-df614da23c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145188796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.4145188796
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.770231305
Short name T629
Test name
Test status
Simulation time 4324596250 ps
CPU time 136.1 seconds
Started May 12 01:32:41 PM PDT 24
Finished May 12 01:34:57 PM PDT 24
Peak memory 247548 kb
Host smart-df1fe9ab-08d1-47a1-8744-26fbbe8edaa6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770231305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.770231305
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.4197243699
Short name T202
Test name
Test status
Simulation time 37935932 ps
CPU time 0.89 seconds
Started May 12 01:32:43 PM PDT 24
Finished May 12 01:32:44 PM PDT 24
Peak memory 211636 kb
Host smart-17e279e2-efa5-4f40-84a9-7771f1790126
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197243699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.4197243699
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2684761648
Short name T760
Test name
Test status
Simulation time 84895840 ps
CPU time 1.17 seconds
Started May 12 01:32:45 PM PDT 24
Finished May 12 01:32:47 PM PDT 24
Peak memory 209564 kb
Host smart-c89c81d7-d5ad-4fa3-9595-3afc46577038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684761648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2684761648
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2508251307
Short name T294
Test name
Test status
Simulation time 1325255585 ps
CPU time 15.44 seconds
Started May 12 01:32:45 PM PDT 24
Finished May 12 01:33:01 PM PDT 24
Peak memory 218072 kb
Host smart-270024e5-f028-4269-bb8e-a302def41f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508251307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2508251307
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1823221345
Short name T772
Test name
Test status
Simulation time 221530574 ps
CPU time 3.12 seconds
Started May 12 01:32:48 PM PDT 24
Finished May 12 01:32:51 PM PDT 24
Peak memory 209372 kb
Host smart-17116e2f-641c-4dc1-9b4d-f9dda8812671
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823221345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1823221345
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.396999208
Short name T654
Test name
Test status
Simulation time 241738775 ps
CPU time 3.49 seconds
Started May 12 01:32:44 PM PDT 24
Finished May 12 01:32:49 PM PDT 24
Peak memory 217996 kb
Host smart-9ed1e6b6-d793-41a3-9bf9-a83504a4520c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396999208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.396999208
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2078173585
Short name T611
Test name
Test status
Simulation time 294929879 ps
CPU time 13.5 seconds
Started May 12 01:32:46 PM PDT 24
Finished May 12 01:33:00 PM PDT 24
Peak memory 225780 kb
Host smart-bf2c2a21-c623-49cf-b000-d18e449380a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078173585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2078173585
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.577911911
Short name T726
Test name
Test status
Simulation time 593965115 ps
CPU time 13.87 seconds
Started May 12 01:32:46 PM PDT 24
Finished May 12 01:33:00 PM PDT 24
Peak memory 218028 kb
Host smart-b4094f7c-2831-4cb7-866b-9898df165aae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577911911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_di
gest.577911911
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3317986694
Short name T258
Test name
Test status
Simulation time 260889309 ps
CPU time 7.31 seconds
Started May 12 01:32:47 PM PDT 24
Finished May 12 01:32:56 PM PDT 24
Peak memory 217860 kb
Host smart-7cf51402-46d6-4404-a6ab-85f7f2b68915
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317986694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3317986694
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1930040890
Short name T19
Test name
Test status
Simulation time 1380075668 ps
CPU time 8.81 seconds
Started May 12 01:32:46 PM PDT 24
Finished May 12 01:32:55 PM PDT 24
Peak memory 218100 kb
Host smart-53e0fde7-7df3-48d2-aee2-604f63b3c8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930040890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1930040890
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.698983902
Short name T631
Test name
Test status
Simulation time 459240128 ps
CPU time 4.04 seconds
Started May 12 01:32:45 PM PDT 24
Finished May 12 01:32:49 PM PDT 24
Peak memory 217732 kb
Host smart-651a7bab-8702-4d4a-8c45-a7daf1ff9352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698983902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.698983902
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3002611061
Short name T366
Test name
Test status
Simulation time 637885649 ps
CPU time 31.38 seconds
Started May 12 01:32:43 PM PDT 24
Finished May 12 01:33:15 PM PDT 24
Peak memory 250580 kb
Host smart-74f5edee-819c-4a3d-8f4a-4dc5fa3b856f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002611061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3002611061
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2733141900
Short name T540
Test name
Test status
Simulation time 54513768 ps
CPU time 8.12 seconds
Started May 12 01:32:45 PM PDT 24
Finished May 12 01:32:54 PM PDT 24
Peak memory 250764 kb
Host smart-d8888fc5-e55a-4c82-92ea-36d17b9e35f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733141900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2733141900
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.821934868
Short name T643
Test name
Test status
Simulation time 4349388192 ps
CPU time 180.57 seconds
Started May 12 01:32:45 PM PDT 24
Finished May 12 01:35:46 PM PDT 24
Peak memory 273324 kb
Host smart-851df785-cd04-4861-afa7-f684b7f07594
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821934868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.821934868
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2201364742
Short name T491
Test name
Test status
Simulation time 29502648 ps
CPU time 0.9 seconds
Started May 12 01:32:48 PM PDT 24
Finished May 12 01:32:49 PM PDT 24
Peak memory 209536 kb
Host smart-9c14e311-0246-481d-accd-1868b2203c36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201364742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2201364742
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.3470387337
Short name T565
Test name
Test status
Simulation time 371515863 ps
CPU time 11.78 seconds
Started May 12 01:32:44 PM PDT 24
Finished May 12 01:32:56 PM PDT 24
Peak memory 217964 kb
Host smart-0b4ede32-82be-4639-b5d7-44652d4f1b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470387337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3470387337
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2711016277
Short name T26
Test name
Test status
Simulation time 242931837 ps
CPU time 1.6 seconds
Started May 12 01:32:47 PM PDT 24
Finished May 12 01:32:50 PM PDT 24
Peak memory 209420 kb
Host smart-43666c5d-778c-491d-929b-7f9de70c1e2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711016277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2711016277
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2852912606
Short name T229
Test name
Test status
Simulation time 43060241 ps
CPU time 1.85 seconds
Started May 12 01:32:45 PM PDT 24
Finished May 12 01:32:47 PM PDT 24
Peak memory 218012 kb
Host smart-ae10f8c0-ef6a-45d0-bf88-8d6d953d52e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852912606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2852912606
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2642757865
Short name T527
Test name
Test status
Simulation time 1925727219 ps
CPU time 19.43 seconds
Started May 12 01:32:47 PM PDT 24
Finished May 12 01:33:06 PM PDT 24
Peak memory 218200 kb
Host smart-cbbbaad8-5a18-4512-b913-90cc04951bf8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642757865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2642757865
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.3613637650
Short name T220
Test name
Test status
Simulation time 1905134104 ps
CPU time 12.09 seconds
Started May 12 01:32:51 PM PDT 24
Finished May 12 01:33:04 PM PDT 24
Peak memory 217968 kb
Host smart-7272c661-b586-4457-816a-8f03a6a56001
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613637650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.3613637650
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.3123365795
Short name T467
Test name
Test status
Simulation time 298265548 ps
CPU time 8.68 seconds
Started May 12 01:32:49 PM PDT 24
Finished May 12 01:32:58 PM PDT 24
Peak memory 217956 kb
Host smart-5174de77-7624-4c96-822a-884989780962
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123365795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
3123365795
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.3335936099
Short name T261
Test name
Test status
Simulation time 1484758352 ps
CPU time 7.65 seconds
Started May 12 01:32:45 PM PDT 24
Finished May 12 01:32:53 PM PDT 24
Peak memory 218092 kb
Host smart-248016cb-28fc-428e-acf6-19e642114457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335936099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3335936099
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.4226515814
Short name T241
Test name
Test status
Simulation time 612013282 ps
CPU time 3.2 seconds
Started May 12 01:32:47 PM PDT 24
Finished May 12 01:32:51 PM PDT 24
Peak memory 214196 kb
Host smart-c3e30f39-5637-49de-a2e0-bde0db2801f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226515814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.4226515814
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3384635298
Short name T837
Test name
Test status
Simulation time 175632955 ps
CPU time 17.23 seconds
Started May 12 01:32:49 PM PDT 24
Finished May 12 01:33:06 PM PDT 24
Peak memory 250804 kb
Host smart-8f6e88fb-47a6-451f-b973-253700d973e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384635298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3384635298
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3002121725
Short name T382
Test name
Test status
Simulation time 255051798 ps
CPU time 3.15 seconds
Started May 12 01:32:45 PM PDT 24
Finished May 12 01:32:49 PM PDT 24
Peak memory 226296 kb
Host smart-b3fcfa8c-d3da-45a0-a856-385a782a2b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002121725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3002121725
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3224770817
Short name T393
Test name
Test status
Simulation time 16619206788 ps
CPU time 97.78 seconds
Started May 12 01:32:48 PM PDT 24
Finished May 12 01:34:26 PM PDT 24
Peak memory 272400 kb
Host smart-2b1e3ead-c91e-4f0a-b256-3b65574c6b38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224770817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3224770817
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.647965414
Short name T564
Test name
Test status
Simulation time 29264257 ps
CPU time 0.91 seconds
Started May 12 01:32:46 PM PDT 24
Finished May 12 01:32:47 PM PDT 24
Peak memory 212636 kb
Host smart-0e332224-32b3-40d3-b165-3c1f022e65e9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647965414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.647965414
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.13350843
Short name T520
Test name
Test status
Simulation time 21490303 ps
CPU time 0.94 seconds
Started May 12 01:32:53 PM PDT 24
Finished May 12 01:32:54 PM PDT 24
Peak memory 209572 kb
Host smart-d02d4cf0-1f35-460c-ab37-4e1d3c6d7584
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13350843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.13350843
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.508653652
Short name T791
Test name
Test status
Simulation time 397988196 ps
CPU time 12.84 seconds
Started May 12 01:32:51 PM PDT 24
Finished May 12 01:33:05 PM PDT 24
Peak memory 218084 kb
Host smart-65ccdd87-2941-4c33-a09c-9cf6c1df5659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508653652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.508653652
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2999267119
Short name T853
Test name
Test status
Simulation time 552392134 ps
CPU time 6.22 seconds
Started May 12 01:32:50 PM PDT 24
Finished May 12 01:32:57 PM PDT 24
Peak memory 209528 kb
Host smart-09d2b240-d969-4c75-8fcc-0340c4273d0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999267119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2999267119
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2575124934
Short name T740
Test name
Test status
Simulation time 115569452 ps
CPU time 2.58 seconds
Started May 12 01:32:49 PM PDT 24
Finished May 12 01:32:52 PM PDT 24
Peak memory 217852 kb
Host smart-95630a74-b5a3-4b17-a9bc-3752b5f8ba49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575124934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2575124934
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3134972970
Short name T305
Test name
Test status
Simulation time 795464860 ps
CPU time 19.19 seconds
Started May 12 01:32:48 PM PDT 24
Finished May 12 01:33:07 PM PDT 24
Peak memory 226132 kb
Host smart-9aed5cad-1f00-4ce6-bd47-1018b549e684
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134972970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3134972970
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3954668281
Short name T818
Test name
Test status
Simulation time 2130250127 ps
CPU time 11.44 seconds
Started May 12 01:32:50 PM PDT 24
Finished May 12 01:33:02 PM PDT 24
Peak memory 217968 kb
Host smart-acfd185d-a77b-481d-8c92-ff87e8cbe330
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954668281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3954668281
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.299527601
Short name T16
Test name
Test status
Simulation time 1171652460 ps
CPU time 11.53 seconds
Started May 12 01:32:47 PM PDT 24
Finished May 12 01:32:59 PM PDT 24
Peak memory 218016 kb
Host smart-a7746ac8-9a88-4680-b823-c17dabeccf18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299527601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.299527601
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2455844981
Short name T678
Test name
Test status
Simulation time 991237272 ps
CPU time 10.62 seconds
Started May 12 01:32:49 PM PDT 24
Finished May 12 01:33:00 PM PDT 24
Peak memory 217964 kb
Host smart-1bc34e07-4d2c-4299-b4ac-1a5cc253db24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455844981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2455844981
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.808109538
Short name T549
Test name
Test status
Simulation time 96811337 ps
CPU time 2.4 seconds
Started May 12 01:32:49 PM PDT 24
Finished May 12 01:32:52 PM PDT 24
Peak memory 213912 kb
Host smart-968ac5d7-13dc-4f9f-b0d6-ad5a384bc3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808109538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.808109538
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.3732960340
Short name T459
Test name
Test status
Simulation time 759329675 ps
CPU time 19.29 seconds
Started May 12 01:32:48 PM PDT 24
Finished May 12 01:33:08 PM PDT 24
Peak memory 250852 kb
Host smart-5cb0ff7c-7886-4ca0-aad3-bb5d16deba78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732960340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3732960340
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2420243352
Short name T253
Test name
Test status
Simulation time 301169882 ps
CPU time 6.04 seconds
Started May 12 01:32:50 PM PDT 24
Finished May 12 01:32:57 PM PDT 24
Peak memory 250800 kb
Host smart-a7f3c677-35d3-4e5f-81ee-61dc9f71858a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420243352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2420243352
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2864906884
Short name T420
Test name
Test status
Simulation time 4140341683 ps
CPU time 85.74 seconds
Started May 12 01:32:51 PM PDT 24
Finished May 12 01:34:17 PM PDT 24
Peak memory 251708 kb
Host smart-f684d677-06e2-45b8-ab56-4d500d77b23a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864906884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2864906884
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.2111159373
Short name T146
Test name
Test status
Simulation time 14494576893 ps
CPU time 316.48 seconds
Started May 12 01:32:55 PM PDT 24
Finished May 12 01:38:12 PM PDT 24
Peak memory 284000 kb
Host smart-fd460a46-307a-4a52-bf0f-a6cfc19bb4d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2111159373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.2111159373
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3976182173
Short name T262
Test name
Test status
Simulation time 22639669 ps
CPU time 1 seconds
Started May 12 01:32:48 PM PDT 24
Finished May 12 01:32:49 PM PDT 24
Peak memory 212716 kb
Host smart-3ac7212c-b6b1-4d80-a6de-5ca8d5807f73
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976182173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.3976182173
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2273101918
Short name T254
Test name
Test status
Simulation time 16450039 ps
CPU time 1.09 seconds
Started May 12 01:32:55 PM PDT 24
Finished May 12 01:32:56 PM PDT 24
Peak memory 209420 kb
Host smart-482ce459-ccfa-479d-9df1-fcb59d75e79e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273101918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2273101918
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2344016649
Short name T214
Test name
Test status
Simulation time 584411481 ps
CPU time 9.94 seconds
Started May 12 01:32:51 PM PDT 24
Finished May 12 01:33:01 PM PDT 24
Peak memory 217980 kb
Host smart-daf38842-b3e3-49df-a03e-8eeb5246cec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344016649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2344016649
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.503908148
Short name T660
Test name
Test status
Simulation time 948292813 ps
CPU time 3.87 seconds
Started May 12 01:32:52 PM PDT 24
Finished May 12 01:32:57 PM PDT 24
Peak memory 216980 kb
Host smart-78e4d27c-149f-4d39-b328-56547de8a084
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503908148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.503908148
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.323043234
Short name T739
Test name
Test status
Simulation time 146474709 ps
CPU time 1.68 seconds
Started May 12 01:32:51 PM PDT 24
Finished May 12 01:32:54 PM PDT 24
Peak memory 218064 kb
Host smart-67045c98-49ac-4853-983a-ce1d1b5ca32f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323043234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.323043234
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3290010628
Short name T439
Test name
Test status
Simulation time 952810291 ps
CPU time 13.42 seconds
Started May 12 01:32:52 PM PDT 24
Finished May 12 01:33:06 PM PDT 24
Peak memory 218132 kb
Host smart-b13303cc-97c3-49f0-a009-f83d86724015
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290010628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3290010628
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.2545205684
Short name T642
Test name
Test status
Simulation time 465168212 ps
CPU time 17.59 seconds
Started May 12 01:32:52 PM PDT 24
Finished May 12 01:33:10 PM PDT 24
Peak memory 217920 kb
Host smart-2a595ccf-db53-4717-9803-beaaaf121d04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545205684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.2545205684
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2015820735
Short name T598
Test name
Test status
Simulation time 851258899 ps
CPU time 6.58 seconds
Started May 12 01:32:51 PM PDT 24
Finished May 12 01:32:58 PM PDT 24
Peak memory 217992 kb
Host smart-593816b5-824d-48ff-bc1b-8aad270ad96d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015820735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2015820735
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3931519801
Short name T311
Test name
Test status
Simulation time 1309511407 ps
CPU time 7.75 seconds
Started May 12 01:32:52 PM PDT 24
Finished May 12 01:33:00 PM PDT 24
Peak memory 218060 kb
Host smart-df81d4b9-2766-4a53-a628-afd90a0837a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931519801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3931519801
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1641800388
Short name T521
Test name
Test status
Simulation time 49081449 ps
CPU time 2.67 seconds
Started May 12 01:32:54 PM PDT 24
Finished May 12 01:32:57 PM PDT 24
Peak memory 217800 kb
Host smart-9898ac98-1dc8-4c69-b1fb-1942600ed5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641800388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1641800388
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.4254166184
Short name T627
Test name
Test status
Simulation time 783009443 ps
CPU time 40.98 seconds
Started May 12 01:32:55 PM PDT 24
Finished May 12 01:33:36 PM PDT 24
Peak memory 250920 kb
Host smart-e7b4e2fe-06fd-4fe0-8e75-c27a1d7a034c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254166184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.4254166184
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1169542101
Short name T91
Test name
Test status
Simulation time 289350089 ps
CPU time 8.39 seconds
Started May 12 01:32:52 PM PDT 24
Finished May 12 01:33:01 PM PDT 24
Peak memory 248564 kb
Host smart-c76df8d7-02f5-4e4f-80fd-00e7dd4b1c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169542101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1169542101
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1788633765
Short name T141
Test name
Test status
Simulation time 10526719339 ps
CPU time 59.32 seconds
Started May 12 01:32:51 PM PDT 24
Finished May 12 01:33:51 PM PDT 24
Peak memory 271000 kb
Host smart-f5e06c4f-9533-469d-99f1-c51a61191377
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788633765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1788633765
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.701225220
Short name T203
Test name
Test status
Simulation time 30803420 ps
CPU time 0.83 seconds
Started May 12 01:32:53 PM PDT 24
Finished May 12 01:32:54 PM PDT 24
Peak memory 211552 kb
Host smart-c31ad6fd-6f68-48f5-8df7-71baa74ea1d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701225220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ct
rl_volatile_unlock_smoke.701225220
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2904113528
Short name T63
Test name
Test status
Simulation time 62021841 ps
CPU time 0.88 seconds
Started May 12 01:32:56 PM PDT 24
Finished May 12 01:32:57 PM PDT 24
Peak memory 209572 kb
Host smart-8d27650c-65e2-404e-8941-98f09af7777a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904113528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2904113528
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3317837405
Short name T172
Test name
Test status
Simulation time 3898834561 ps
CPU time 14.35 seconds
Started May 12 01:32:57 PM PDT 24
Finished May 12 01:33:12 PM PDT 24
Peak memory 218052 kb
Host smart-43088c97-f2ca-4062-bc60-5cfe7c2456e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317837405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3317837405
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3281740882
Short name T306
Test name
Test status
Simulation time 789374867 ps
CPU time 18.18 seconds
Started May 12 01:32:55 PM PDT 24
Finished May 12 01:33:14 PM PDT 24
Peak memory 209544 kb
Host smart-e2e6e986-7322-4619-b8d5-4c3355ffec2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281740882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3281740882
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2113316600
Short name T522
Test name
Test status
Simulation time 22720272 ps
CPU time 1.72 seconds
Started May 12 01:32:58 PM PDT 24
Finished May 12 01:33:00 PM PDT 24
Peak memory 218012 kb
Host smart-a2dfa58d-c5b9-428e-b03c-45e0c589da40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113316600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2113316600
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.550317381
Short name T350
Test name
Test status
Simulation time 5444056112 ps
CPU time 13.75 seconds
Started May 12 01:32:58 PM PDT 24
Finished May 12 01:33:12 PM PDT 24
Peak memory 220116 kb
Host smart-409bd58f-1144-4648-b405-3b4bde213215
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550317381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.550317381
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.813922349
Short name T456
Test name
Test status
Simulation time 1299668414 ps
CPU time 10.89 seconds
Started May 12 01:32:58 PM PDT 24
Finished May 12 01:33:10 PM PDT 24
Peak memory 218012 kb
Host smart-93b53abf-61f4-495e-9b11-ce23c932346f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813922349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.813922349
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3367381611
Short name T807
Test name
Test status
Simulation time 249296056 ps
CPU time 7.69 seconds
Started May 12 01:32:55 PM PDT 24
Finished May 12 01:33:03 PM PDT 24
Peak memory 217908 kb
Host smart-401aeb7b-03af-40db-9d5c-bb9c4febf50c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367381611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3367381611
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3938765657
Short name T832
Test name
Test status
Simulation time 1099189493 ps
CPU time 12.1 seconds
Started May 12 01:32:53 PM PDT 24
Finished May 12 01:33:05 PM PDT 24
Peak memory 218056 kb
Host smart-dcfa9f1a-69bf-4e05-93f9-2d453fdc667b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938765657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3938765657
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.540347835
Short name T446
Test name
Test status
Simulation time 320764877 ps
CPU time 1.41 seconds
Started May 12 01:32:54 PM PDT 24
Finished May 12 01:32:56 PM PDT 24
Peak memory 213396 kb
Host smart-06a6e79d-a038-4f50-a2a9-b68285b52113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540347835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.540347835
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3732704294
Short name T586
Test name
Test status
Simulation time 1417271394 ps
CPU time 29.36 seconds
Started May 12 01:32:58 PM PDT 24
Finished May 12 01:33:27 PM PDT 24
Peak memory 250828 kb
Host smart-9725be19-71a8-42c5-9092-8ef5bac22d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732704294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3732704294
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2407325215
Short name T534
Test name
Test status
Simulation time 129033012 ps
CPU time 7.85 seconds
Started May 12 01:32:58 PM PDT 24
Finished May 12 01:33:06 PM PDT 24
Peak memory 250712 kb
Host smart-57e284e4-09b5-4f9e-a4dd-110511766faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407325215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2407325215
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1520228551
Short name T751
Test name
Test status
Simulation time 8422826254 ps
CPU time 115.61 seconds
Started May 12 01:32:58 PM PDT 24
Finished May 12 01:34:54 PM PDT 24
Peak memory 281588 kb
Host smart-51ec2c10-7c30-4724-b039-234dee710b14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520228551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1520228551
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.838358074
Short name T443
Test name
Test status
Simulation time 46740381 ps
CPU time 0.95 seconds
Started May 12 01:32:50 PM PDT 24
Finished May 12 01:32:52 PM PDT 24
Peak memory 211540 kb
Host smart-c43a1d35-816b-4a47-a807-44cd1d4a14d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838358074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.838358074
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.330244779
Short name T511
Test name
Test status
Simulation time 12894807 ps
CPU time 0.83 seconds
Started May 12 01:32:59 PM PDT 24
Finished May 12 01:33:01 PM PDT 24
Peak memory 209380 kb
Host smart-30cf643f-8c70-4fd1-a637-c527024ed693
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330244779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.330244779
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.3340950036
Short name T275
Test name
Test status
Simulation time 6332124306 ps
CPU time 16.91 seconds
Started May 12 01:32:55 PM PDT 24
Finished May 12 01:33:13 PM PDT 24
Peak memory 218504 kb
Host smart-03257b31-8c65-4506-a194-bd0c8bf297f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340950036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.3340950036
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.481171105
Short name T27
Test name
Test status
Simulation time 404793845 ps
CPU time 2.86 seconds
Started May 12 01:33:00 PM PDT 24
Finished May 12 01:33:04 PM PDT 24
Peak memory 209372 kb
Host smart-5bb13156-8b29-49ea-816d-7b3ec87657c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481171105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.481171105
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.571274938
Short name T224
Test name
Test status
Simulation time 84279418 ps
CPU time 4.18 seconds
Started May 12 01:32:55 PM PDT 24
Finished May 12 01:32:59 PM PDT 24
Peak memory 218068 kb
Host smart-add6ef64-3e60-4213-843f-a53ed7940f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571274938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.571274938
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.119125335
Short name T433
Test name
Test status
Simulation time 484226656 ps
CPU time 14.33 seconds
Started May 12 01:32:57 PM PDT 24
Finished May 12 01:33:11 PM PDT 24
Peak memory 226096 kb
Host smart-23e53917-8759-4018-97d3-c746fcf08528
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119125335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.119125335
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2880882097
Short name T640
Test name
Test status
Simulation time 1216020110 ps
CPU time 11.08 seconds
Started May 12 01:33:00 PM PDT 24
Finished May 12 01:33:11 PM PDT 24
Peak memory 217972 kb
Host smart-12955e7c-30c0-4088-a810-2dbf100dc114
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880882097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.2880882097
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3013640886
Short name T566
Test name
Test status
Simulation time 2340314755 ps
CPU time 8.84 seconds
Started May 12 01:32:55 PM PDT 24
Finished May 12 01:33:04 PM PDT 24
Peak memory 218008 kb
Host smart-c892b84c-61b9-434e-8908-ace7fb766e16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013640886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3013640886
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1042483581
Short name T384
Test name
Test status
Simulation time 1014071329 ps
CPU time 10.22 seconds
Started May 12 01:32:55 PM PDT 24
Finished May 12 01:33:05 PM PDT 24
Peak memory 218304 kb
Host smart-d0991abf-f454-4390-a5dc-b98d1147c325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042483581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1042483581
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3271307051
Short name T558
Test name
Test status
Simulation time 77934035 ps
CPU time 1.35 seconds
Started May 12 01:33:00 PM PDT 24
Finished May 12 01:33:02 PM PDT 24
Peak memory 217740 kb
Host smart-a1efa547-56f2-4ce0-9d80-d89d7257b6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271307051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3271307051
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1793539635
Short name T731
Test name
Test status
Simulation time 216972414 ps
CPU time 23.54 seconds
Started May 12 01:32:58 PM PDT 24
Finished May 12 01:33:22 PM PDT 24
Peak memory 250700 kb
Host smart-cdd20c19-c5cb-4b1f-b023-48094b90160d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793539635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1793539635
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1940645879
Short name T743
Test name
Test status
Simulation time 542942473 ps
CPU time 7.52 seconds
Started May 12 01:32:57 PM PDT 24
Finished May 12 01:33:05 PM PDT 24
Peak memory 247152 kb
Host smart-9a4966ec-fe19-42be-90cf-24746d0a3c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940645879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1940645879
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2402531646
Short name T732
Test name
Test status
Simulation time 11219419079 ps
CPU time 160.99 seconds
Started May 12 01:32:59 PM PDT 24
Finished May 12 01:35:40 PM PDT 24
Peak memory 251108 kb
Host smart-6b9ffab5-42ee-4ec5-9d45-074bb096292b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402531646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2402531646
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.362749786
Short name T616
Test name
Test status
Simulation time 70872445 ps
CPU time 1.34 seconds
Started May 12 01:32:56 PM PDT 24
Finished May 12 01:32:58 PM PDT 24
Peak memory 213172 kb
Host smart-1fc44e5f-28d4-4f2c-9c34-783c216ef514
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362749786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct
rl_volatile_unlock_smoke.362749786
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.220405281
Short name T493
Test name
Test status
Simulation time 71145457 ps
CPU time 0.95 seconds
Started May 12 01:33:05 PM PDT 24
Finished May 12 01:33:07 PM PDT 24
Peak memory 209524 kb
Host smart-0b622361-7120-4761-b003-2ac92576cbe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220405281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.220405281
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.4054005097
Short name T523
Test name
Test status
Simulation time 1047262922 ps
CPU time 12.66 seconds
Started May 12 01:33:00 PM PDT 24
Finished May 12 01:33:13 PM PDT 24
Peak memory 217940 kb
Host smart-5a596a68-7c86-4316-aadc-1cc24ec8e79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054005097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.4054005097
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1661453181
Short name T30
Test name
Test status
Simulation time 1923701466 ps
CPU time 7.3 seconds
Started May 12 01:33:00 PM PDT 24
Finished May 12 01:33:08 PM PDT 24
Peak memory 209500 kb
Host smart-5a85bdc3-baf7-4e0e-8365-b2f02b716930
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661453181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1661453181
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3813200792
Short name T607
Test name
Test status
Simulation time 112022278 ps
CPU time 2.68 seconds
Started May 12 01:33:00 PM PDT 24
Finished May 12 01:33:03 PM PDT 24
Peak memory 217936 kb
Host smart-ae64ad95-9d1b-450c-9317-7d477ec3a337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813200792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3813200792
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.1349071379
Short name T848
Test name
Test status
Simulation time 265432215 ps
CPU time 14.16 seconds
Started May 12 01:33:03 PM PDT 24
Finished May 12 01:33:18 PM PDT 24
Peak memory 226080 kb
Host smart-a5d58dcf-43da-4a21-8875-da3572a339c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349071379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1349071379
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.863661619
Short name T868
Test name
Test status
Simulation time 726132325 ps
CPU time 22.44 seconds
Started May 12 01:32:59 PM PDT 24
Finished May 12 01:33:22 PM PDT 24
Peak memory 217964 kb
Host smart-6a25844f-18e2-4e5b-8dd3-7def1cafe1a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863661619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.863661619
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2110654210
Short name T713
Test name
Test status
Simulation time 3451549640 ps
CPU time 10.79 seconds
Started May 12 01:33:00 PM PDT 24
Finished May 12 01:33:11 PM PDT 24
Peak memory 218016 kb
Host smart-7e28ddeb-b740-4ad6-8565-fec6a24723a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110654210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2110654210
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.384695027
Short name T870
Test name
Test status
Simulation time 1037715571 ps
CPU time 9.4 seconds
Started May 12 01:33:00 PM PDT 24
Finished May 12 01:33:10 PM PDT 24
Peak memory 218104 kb
Host smart-577dfe51-dc79-4743-856b-85115a7d6518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384695027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.384695027
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.3634217348
Short name T717
Test name
Test status
Simulation time 233914668 ps
CPU time 4.43 seconds
Started May 12 01:33:01 PM PDT 24
Finished May 12 01:33:06 PM PDT 24
Peak memory 217704 kb
Host smart-f3ed9e1c-2d0d-43ea-9e6a-e6b5c691aaec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634217348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.3634217348
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3020299440
Short name T279
Test name
Test status
Simulation time 1007297983 ps
CPU time 25.55 seconds
Started May 12 01:33:00 PM PDT 24
Finished May 12 01:33:26 PM PDT 24
Peak memory 251048 kb
Host smart-2c87e156-9e89-464c-b2d3-2f959f6ab9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020299440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3020299440
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.2480246617
Short name T662
Test name
Test status
Simulation time 146958887 ps
CPU time 3.15 seconds
Started May 12 01:33:02 PM PDT 24
Finished May 12 01:33:05 PM PDT 24
Peak memory 222304 kb
Host smart-c0caf3b6-040e-4852-a544-d972e3b848f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480246617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2480246617
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3218847723
Short name T762
Test name
Test status
Simulation time 14437100387 ps
CPU time 111.73 seconds
Started May 12 01:32:59 PM PDT 24
Finished May 12 01:34:51 PM PDT 24
Peak memory 251072 kb
Host smart-356acf5b-f37c-471c-809d-22463e8ac456
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218847723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3218847723
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.179721628
Short name T93
Test name
Test status
Simulation time 2052591558 ps
CPU time 71.1 seconds
Started May 12 01:33:00 PM PDT 24
Finished May 12 01:34:12 PM PDT 24
Peak memory 275980 kb
Host smart-da32f4f9-a63d-40d4-a455-54b3e08b6028
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=179721628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.179721628
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3185965509
Short name T325
Test name
Test status
Simulation time 23142406 ps
CPU time 1.13 seconds
Started May 12 01:33:01 PM PDT 24
Finished May 12 01:33:02 PM PDT 24
Peak memory 212692 kb
Host smart-14d9f825-eef9-40e4-8d3f-5876e6742aa5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185965509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3185965509
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1207572622
Short name T359
Test name
Test status
Simulation time 14102641 ps
CPU time 1 seconds
Started May 12 01:30:58 PM PDT 24
Finished May 12 01:30:59 PM PDT 24
Peak memory 209544 kb
Host smart-f815421a-8cba-4068-be70-3ee7ff8b58d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207572622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1207572622
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1593279747
Short name T205
Test name
Test status
Simulation time 20687768 ps
CPU time 0.86 seconds
Started May 12 01:30:56 PM PDT 24
Finished May 12 01:30:58 PM PDT 24
Peak memory 209336 kb
Host smart-afc4aba5-e277-416b-b228-09c0fa187318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593279747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1593279747
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.331656391
Short name T514
Test name
Test status
Simulation time 4397435150 ps
CPU time 14.48 seconds
Started May 12 01:30:56 PM PDT 24
Finished May 12 01:31:12 PM PDT 24
Peak memory 219052 kb
Host smart-81d7a364-c9b5-42bf-b8e9-6bb41beda7f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331656391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.331656391
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3716052910
Short name T9
Test name
Test status
Simulation time 617658613 ps
CPU time 6.6 seconds
Started May 12 01:30:58 PM PDT 24
Finished May 12 01:31:05 PM PDT 24
Peak memory 209548 kb
Host smart-2cb1cff0-d4e8-41aa-ad73-9e1aa7d1e602
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716052910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3716052910
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.3614161171
Short name T457
Test name
Test status
Simulation time 4071206358 ps
CPU time 31.33 seconds
Started May 12 01:30:58 PM PDT 24
Finished May 12 01:31:30 PM PDT 24
Peak memory 218008 kb
Host smart-a29ace84-d918-4fbf-90b6-54317a4a6b18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614161171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.3614161171
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2847048119
Short name T339
Test name
Test status
Simulation time 89855141 ps
CPU time 1.78 seconds
Started May 12 01:30:59 PM PDT 24
Finished May 12 01:31:01 PM PDT 24
Peak memory 217060 kb
Host smart-01fec3cd-70e5-4a45-bcee-8dc86a8387d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847048119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
847048119
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3195671398
Short name T874
Test name
Test status
Simulation time 1442406782 ps
CPU time 12.26 seconds
Started May 12 01:30:55 PM PDT 24
Finished May 12 01:31:08 PM PDT 24
Peak memory 218020 kb
Host smart-49fd2679-3f07-40ac-81d0-c0db0f02680f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195671398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3195671398
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2998796428
Short name T783
Test name
Test status
Simulation time 911990982 ps
CPU time 24.45 seconds
Started May 12 01:30:58 PM PDT 24
Finished May 12 01:31:23 PM PDT 24
Peak memory 213288 kb
Host smart-79860eab-7cf9-42c3-9a46-6ab5125ed72e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998796428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2998796428
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.2062817147
Short name T150
Test name
Test status
Simulation time 827707773 ps
CPU time 11.49 seconds
Started May 12 01:30:59 PM PDT 24
Finished May 12 01:31:11 PM PDT 24
Peak memory 214020 kb
Host smart-2b65ed15-8e97-4351-ade8-e86356fcecb7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062817147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
2062817147
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2287649467
Short name T165
Test name
Test status
Simulation time 2196675288 ps
CPU time 41.19 seconds
Started May 12 01:30:59 PM PDT 24
Finished May 12 01:31:41 PM PDT 24
Peak memory 267928 kb
Host smart-b6e8fe62-edd7-4486-827a-a187a2464224
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287649467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2287649467
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3653090671
Short name T217
Test name
Test status
Simulation time 667094208 ps
CPU time 22.66 seconds
Started May 12 01:30:59 PM PDT 24
Finished May 12 01:31:22 PM PDT 24
Peak memory 250952 kb
Host smart-2dd49d27-eee8-4dc4-83dd-30f26349bfe1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653090671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3653090671
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3819030425
Short name T495
Test name
Test status
Simulation time 62129515 ps
CPU time 1.63 seconds
Started May 12 01:30:58 PM PDT 24
Finished May 12 01:31:00 PM PDT 24
Peak memory 217920 kb
Host smart-258b3d06-27bf-4b99-a975-ee8e96f87fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819030425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3819030425
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.4241145369
Short name T612
Test name
Test status
Simulation time 314556185 ps
CPU time 12.04 seconds
Started May 12 01:31:00 PM PDT 24
Finished May 12 01:31:13 PM PDT 24
Peak memory 217920 kb
Host smart-3c410680-f8ad-486d-9c7e-6ab3c56f9322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241145369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.4241145369
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2345306795
Short name T212
Test name
Test status
Simulation time 633880702 ps
CPU time 17.87 seconds
Started May 12 01:30:58 PM PDT 24
Finished May 12 01:31:17 PM PDT 24
Peak memory 225568 kb
Host smart-3aac9150-33a9-4b7c-ae0e-6cd9d046bfd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345306795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2345306795
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2899509643
Short name T711
Test name
Test status
Simulation time 876874373 ps
CPU time 10.74 seconds
Started May 12 01:30:58 PM PDT 24
Finished May 12 01:31:09 PM PDT 24
Peak memory 218012 kb
Host smart-b4654a50-f707-4e6b-92d4-0ff566bb5395
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899509643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2899509643
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.382937232
Short name T237
Test name
Test status
Simulation time 1133707569 ps
CPU time 10.1 seconds
Started May 12 01:30:57 PM PDT 24
Finished May 12 01:31:07 PM PDT 24
Peak memory 217992 kb
Host smart-27cfacd6-cb60-4c26-8818-6092afc5840a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382937232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.382937232
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.3125414527
Short name T691
Test name
Test status
Simulation time 250615704 ps
CPU time 10.02 seconds
Started May 12 01:30:57 PM PDT 24
Finished May 12 01:31:08 PM PDT 24
Peak memory 218032 kb
Host smart-037e5362-b2ba-4461-af2b-f98c030b9667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125414527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.3125414527
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2521275083
Short name T51
Test name
Test status
Simulation time 16173226 ps
CPU time 1.05 seconds
Started May 12 01:30:56 PM PDT 24
Finished May 12 01:30:57 PM PDT 24
Peak memory 212040 kb
Host smart-9b04ca94-05ea-47da-bbfa-c37ec7c603ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521275083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2521275083
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.1115454244
Short name T825
Test name
Test status
Simulation time 439682202 ps
CPU time 20.21 seconds
Started May 12 01:30:56 PM PDT 24
Finished May 12 01:31:16 PM PDT 24
Peak memory 250844 kb
Host smart-9ee1fe25-c8a8-4946-89a5-c1bd0127099d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115454244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.1115454244
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2822156944
Short name T539
Test name
Test status
Simulation time 46912078 ps
CPU time 3.04 seconds
Started May 12 01:30:55 PM PDT 24
Finished May 12 01:30:59 PM PDT 24
Peak memory 222512 kb
Host smart-7f0e86ee-10c4-4f78-9b7e-de2291b4154e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822156944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2822156944
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.485493855
Short name T68
Test name
Test status
Simulation time 2328267643 ps
CPU time 73.09 seconds
Started May 12 01:30:56 PM PDT 24
Finished May 12 01:32:10 PM PDT 24
Peak memory 249820 kb
Host smart-ab232abf-eb30-43d4-ae19-0f4cc1605f7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485493855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.485493855
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2505737841
Short name T500
Test name
Test status
Simulation time 29377270 ps
CPU time 0.8 seconds
Started May 12 01:31:00 PM PDT 24
Finished May 12 01:31:02 PM PDT 24
Peak memory 211584 kb
Host smart-c13be38c-56c0-4fb8-931b-47c662ad8d09
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505737841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2505737841
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.2695421469
Short name T531
Test name
Test status
Simulation time 73313848 ps
CPU time 0.93 seconds
Started May 12 01:31:06 PM PDT 24
Finished May 12 01:31:07 PM PDT 24
Peak memory 209508 kb
Host smart-d37b64d8-3e46-4646-8818-c878acf49267
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695421469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.2695421469
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.4210888580
Short name T338
Test name
Test status
Simulation time 29800204 ps
CPU time 0.76 seconds
Started May 12 01:30:57 PM PDT 24
Finished May 12 01:30:58 PM PDT 24
Peak memory 209220 kb
Host smart-e52ad5bd-2ef7-496e-8d31-c0095ebd6654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210888580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.4210888580
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2159509626
Short name T38
Test name
Test status
Simulation time 5968460724 ps
CPU time 15.55 seconds
Started May 12 01:30:56 PM PDT 24
Finished May 12 01:31:13 PM PDT 24
Peak memory 218020 kb
Host smart-e0d5c5dc-f348-4cac-adb1-ec22ef10c9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159509626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2159509626
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.134884137
Short name T736
Test name
Test status
Simulation time 2934943113 ps
CPU time 7.7 seconds
Started May 12 01:30:56 PM PDT 24
Finished May 12 01:31:04 PM PDT 24
Peak memory 209608 kb
Host smart-8421d119-558f-45e8-b515-064c04efab4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134884137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.134884137
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3061735890
Short name T766
Test name
Test status
Simulation time 3861285039 ps
CPU time 54.33 seconds
Started May 12 01:30:56 PM PDT 24
Finished May 12 01:31:52 PM PDT 24
Peak memory 218564 kb
Host smart-435bfe53-bf11-46ae-8b74-009d0ef4fb75
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061735890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3061735890
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1192634210
Short name T613
Test name
Test status
Simulation time 79847154 ps
CPU time 2.82 seconds
Started May 12 01:31:01 PM PDT 24
Finished May 12 01:31:05 PM PDT 24
Peak memory 217056 kb
Host smart-0e279058-1d89-43f9-8074-5397d30652cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192634210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
192634210
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2438560045
Short name T537
Test name
Test status
Simulation time 214818430 ps
CPU time 7.24 seconds
Started May 12 01:31:01 PM PDT 24
Finished May 12 01:31:09 PM PDT 24
Peak memory 217892 kb
Host smart-5da1ac08-5633-4bfa-bf35-596499f637ff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438560045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2438560045
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.634103138
Short name T65
Test name
Test status
Simulation time 586585657 ps
CPU time 16.23 seconds
Started May 12 01:31:03 PM PDT 24
Finished May 12 01:31:20 PM PDT 24
Peak memory 213176 kb
Host smart-d87ab490-0cfb-4cac-adb2-b9422ae79825
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634103138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_regwen_during_op.634103138
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.846529363
Short name T355
Test name
Test status
Simulation time 1037513411 ps
CPU time 5.28 seconds
Started May 12 01:30:59 PM PDT 24
Finished May 12 01:31:04 PM PDT 24
Peak memory 213480 kb
Host smart-887211b7-3599-4389-bcf0-f19ad7ed0575
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846529363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.846529363
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.3387219391
Short name T370
Test name
Test status
Simulation time 1845689949 ps
CPU time 31.87 seconds
Started May 12 01:30:58 PM PDT 24
Finished May 12 01:31:30 PM PDT 24
Peak memory 250884 kb
Host smart-232a6e59-1359-4e4a-bcf8-b97494bafc1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387219391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.3387219391
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.4206355978
Short name T699
Test name
Test status
Simulation time 1161533342 ps
CPU time 11.9 seconds
Started May 12 01:30:58 PM PDT 24
Finished May 12 01:31:10 PM PDT 24
Peak memory 250908 kb
Host smart-22abbe53-076e-4823-bcee-7354b6b4f7b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206355978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.4206355978
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3092471640
Short name T259
Test name
Test status
Simulation time 63914240 ps
CPU time 3.4 seconds
Started May 12 01:30:56 PM PDT 24
Finished May 12 01:31:01 PM PDT 24
Peak memory 218052 kb
Host smart-9c738945-f03d-4b72-aead-00fad0eb3f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092471640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3092471640
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3808074197
Short name T786
Test name
Test status
Simulation time 417843141 ps
CPU time 12.13 seconds
Started May 12 01:30:58 PM PDT 24
Finished May 12 01:31:11 PM PDT 24
Peak memory 217820 kb
Host smart-2ddbae8f-a46c-4d40-aa72-2c92f680619f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808074197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3808074197
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1170167558
Short name T159
Test name
Test status
Simulation time 326798826 ps
CPU time 13.83 seconds
Started May 12 01:31:03 PM PDT 24
Finished May 12 01:31:17 PM PDT 24
Peak memory 226032 kb
Host smart-cf5b33f4-6b13-4c56-be58-6fdfaae18293
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170167558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1170167558
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.177017133
Short name T430
Test name
Test status
Simulation time 6275895858 ps
CPU time 12.84 seconds
Started May 12 01:31:05 PM PDT 24
Finished May 12 01:31:19 PM PDT 24
Peak memory 218136 kb
Host smart-9a5d359e-f775-4611-a83d-df9d0cc42021
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177017133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.177017133
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1873064112
Short name T651
Test name
Test status
Simulation time 6167292890 ps
CPU time 12.18 seconds
Started May 12 01:31:01 PM PDT 24
Finished May 12 01:31:14 PM PDT 24
Peak memory 218128 kb
Host smart-15591b35-9e23-449c-8696-08d83d178b22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873064112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
873064112
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.351447890
Short name T813
Test name
Test status
Simulation time 1183285898 ps
CPU time 11.79 seconds
Started May 12 01:31:00 PM PDT 24
Finished May 12 01:31:13 PM PDT 24
Peak memory 217980 kb
Host smart-617cfb74-ab71-438e-992c-a5a0f3def31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351447890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.351447890
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1775751058
Short name T392
Test name
Test status
Simulation time 144105559 ps
CPU time 2.05 seconds
Started May 12 01:31:00 PM PDT 24
Finished May 12 01:31:03 PM PDT 24
Peak memory 218144 kb
Host smart-aa2effdd-3325-4565-85dc-f4ab52907efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775751058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1775751058
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3219427157
Short name T375
Test name
Test status
Simulation time 4404823970 ps
CPU time 30.24 seconds
Started May 12 01:30:58 PM PDT 24
Finished May 12 01:31:29 PM PDT 24
Peak memory 247116 kb
Host smart-9c69deb9-2a4f-466b-9857-958391a0e7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219427157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3219427157
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2209204091
Short name T34
Test name
Test status
Simulation time 180332323 ps
CPU time 8.88 seconds
Started May 12 01:30:56 PM PDT 24
Finished May 12 01:31:05 PM PDT 24
Peak memory 251204 kb
Host smart-bc482d3d-f209-4cb0-9672-83ec62f6bdf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209204091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2209204091
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.3059884090
Short name T79
Test name
Test status
Simulation time 10704586281 ps
CPU time 184.94 seconds
Started May 12 01:31:00 PM PDT 24
Finished May 12 01:34:06 PM PDT 24
Peak memory 248348 kb
Host smart-d0b44277-7529-4638-83b4-97e0cbad4b14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059884090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.3059884090
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.1404540145
Short name T157
Test name
Test status
Simulation time 167146796402 ps
CPU time 2291.69 seconds
Started May 12 01:31:01 PM PDT 24
Finished May 12 02:09:14 PM PDT 24
Peak memory 1513380 kb
Host smart-b331e027-166b-4f03-863d-413f72bcae51
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1404540145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.1404540145
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2129835478
Short name T486
Test name
Test status
Simulation time 14155984 ps
CPU time 0.88 seconds
Started May 12 01:30:59 PM PDT 24
Finished May 12 01:31:01 PM PDT 24
Peak memory 211696 kb
Host smart-333adf0e-0404-44a2-98c5-efdd576f866a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129835478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2129835478
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3399804770
Short name T530
Test name
Test status
Simulation time 20849655 ps
CPU time 0.99 seconds
Started May 12 01:31:02 PM PDT 24
Finished May 12 01:31:04 PM PDT 24
Peak memory 209524 kb
Host smart-50a6c306-8f8f-4554-a859-97d4a0566d7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399804770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3399804770
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.1337502698
Short name T207
Test name
Test status
Simulation time 14105352 ps
CPU time 0.99 seconds
Started May 12 01:31:05 PM PDT 24
Finished May 12 01:31:06 PM PDT 24
Peak memory 209512 kb
Host smart-43cb4cd9-a21a-4b2a-b371-0c4776620b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337502698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.1337502698
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3565655422
Short name T298
Test name
Test status
Simulation time 365504953 ps
CPU time 15.02 seconds
Started May 12 01:31:00 PM PDT 24
Finished May 12 01:31:16 PM PDT 24
Peak memory 217896 kb
Host smart-8e3360e7-9077-4921-b3eb-32320728ee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565655422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3565655422
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.1475620279
Short name T641
Test name
Test status
Simulation time 589096912 ps
CPU time 8.47 seconds
Started May 12 01:31:02 PM PDT 24
Finished May 12 01:31:11 PM PDT 24
Peak memory 209504 kb
Host smart-f21d1f4f-917b-4664-90f0-b29184f6f441
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475620279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.1475620279
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1393147902
Short name T449
Test name
Test status
Simulation time 1595116533 ps
CPU time 24 seconds
Started May 12 01:31:03 PM PDT 24
Finished May 12 01:31:27 PM PDT 24
Peak memory 218032 kb
Host smart-733fdc24-dc51-4ad8-8741-9e2c0879d5ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393147902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1393147902
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.80150611
Short name T850
Test name
Test status
Simulation time 575113994 ps
CPU time 5.82 seconds
Started May 12 01:31:02 PM PDT 24
Finished May 12 01:31:09 PM PDT 24
Peak memory 217696 kb
Host smart-555eb72e-eeac-4797-a251-8006d3b8c74e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80150611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.80150611
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.779985405
Short name T597
Test name
Test status
Simulation time 690941872 ps
CPU time 2.03 seconds
Started May 12 01:31:08 PM PDT 24
Finished May 12 01:31:11 PM PDT 24
Peak memory 218092 kb
Host smart-79b8bc1c-2bcc-4bdc-8fee-f69271e4d31c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779985405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_
prog_failure.779985405
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2247968882
Short name T494
Test name
Test status
Simulation time 1491564028 ps
CPU time 20.06 seconds
Started May 12 01:31:05 PM PDT 24
Finished May 12 01:31:26 PM PDT 24
Peak memory 213224 kb
Host smart-3f900daf-91d5-4352-96d4-251f881bdba9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247968882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2247968882
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3631563137
Short name T741
Test name
Test status
Simulation time 704564744 ps
CPU time 5.01 seconds
Started May 12 01:31:01 PM PDT 24
Finished May 12 01:31:06 PM PDT 24
Peak memory 213648 kb
Host smart-695e544d-3d10-4a58-b817-ad5b33edd790
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631563137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3631563137
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.702340564
Short name T234
Test name
Test status
Simulation time 3638355344 ps
CPU time 42.47 seconds
Started May 12 01:31:05 PM PDT 24
Finished May 12 01:31:48 PM PDT 24
Peak memory 273660 kb
Host smart-7e6203a3-1d0a-42c8-b2f2-13edf5569cf4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702340564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.702340564
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2358856076
Short name T552
Test name
Test status
Simulation time 397573985 ps
CPU time 7.58 seconds
Started May 12 01:31:01 PM PDT 24
Finished May 12 01:31:09 PM PDT 24
Peak memory 225564 kb
Host smart-20e35414-4517-4ca2-a2b7-98723342061c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358856076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2358856076
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3604326243
Short name T843
Test name
Test status
Simulation time 210233938 ps
CPU time 4.8 seconds
Started May 12 01:31:02 PM PDT 24
Finished May 12 01:31:07 PM PDT 24
Peak memory 217960 kb
Host smart-11b70ce6-e323-41c1-bc93-0ea3936a13da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604326243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3604326243
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.210416160
Short name T35
Test name
Test status
Simulation time 649600316 ps
CPU time 11.81 seconds
Started May 12 01:31:04 PM PDT 24
Finished May 12 01:31:17 PM PDT 24
Peak memory 214296 kb
Host smart-47a696f6-20ec-4490-814c-9cb36e9c2d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210416160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.210416160
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3386516241
Short name T712
Test name
Test status
Simulation time 295998605 ps
CPU time 12.23 seconds
Started May 12 01:31:03 PM PDT 24
Finished May 12 01:31:16 PM PDT 24
Peak memory 218028 kb
Host smart-6ca48ad5-3c86-4e0b-8eab-7998dbd24fc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386516241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3386516241
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.512495163
Short name T264
Test name
Test status
Simulation time 839388132 ps
CPU time 10.67 seconds
Started May 12 01:31:06 PM PDT 24
Finished May 12 01:31:17 PM PDT 24
Peak memory 217940 kb
Host smart-9c7277fd-be89-46a8-8f64-87ab8b08b55b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512495163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.512495163
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1843053750
Short name T455
Test name
Test status
Simulation time 384351418 ps
CPU time 8.38 seconds
Started May 12 01:31:02 PM PDT 24
Finished May 12 01:31:11 PM PDT 24
Peak memory 217936 kb
Host smart-cb058bbd-a470-479e-a0a4-96e0e1755316
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843053750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
843053750
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.746015446
Short name T340
Test name
Test status
Simulation time 297582255 ps
CPU time 10.43 seconds
Started May 12 01:31:01 PM PDT 24
Finished May 12 01:31:12 PM PDT 24
Peak memory 218036 kb
Host smart-09fba076-492c-4e7f-ba7f-efb3579f9f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746015446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.746015446
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1644454859
Short name T542
Test name
Test status
Simulation time 28661698 ps
CPU time 0.99 seconds
Started May 12 01:31:05 PM PDT 24
Finished May 12 01:31:07 PM PDT 24
Peak memory 212888 kb
Host smart-e121ef70-1ee2-4038-9421-444bbab8fa4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644454859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1644454859
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3611409908
Short name T221
Test name
Test status
Simulation time 327006143 ps
CPU time 34.4 seconds
Started May 12 01:31:00 PM PDT 24
Finished May 12 01:31:35 PM PDT 24
Peak memory 247720 kb
Host smart-135784b1-cad2-4a8c-a640-0f3c2bf45912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611409908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3611409908
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.1285186892
Short name T609
Test name
Test status
Simulation time 74533177 ps
CPU time 6.91 seconds
Started May 12 01:31:01 PM PDT 24
Finished May 12 01:31:08 PM PDT 24
Peak memory 247012 kb
Host smart-ba17a953-8cb2-4419-be5b-7e4f7a9ce1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285186892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.1285186892
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1050570001
Short name T728
Test name
Test status
Simulation time 1594415448 ps
CPU time 53.32 seconds
Started May 12 01:31:05 PM PDT 24
Finished May 12 01:31:59 PM PDT 24
Peak memory 270244 kb
Host smart-dbc92c2f-0ddf-4797-8def-075992d47984
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050570001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1050570001
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.1859156846
Short name T414
Test name
Test status
Simulation time 143585422954 ps
CPU time 578.46 seconds
Started May 12 01:31:01 PM PDT 24
Finished May 12 01:40:40 PM PDT 24
Peak memory 316704 kb
Host smart-f309daf5-602b-4827-a912-3316b1861fda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1859156846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.1859156846
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2876688545
Short name T475
Test name
Test status
Simulation time 27412854 ps
CPU time 0.89 seconds
Started May 12 01:31:01 PM PDT 24
Finished May 12 01:31:03 PM PDT 24
Peak memory 212800 kb
Host smart-d9640fdc-803a-4a65-bd30-0a981e1836c3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876688545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.2876688545
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3966172812
Short name T854
Test name
Test status
Simulation time 18675864 ps
CPU time 1.13 seconds
Started May 12 01:31:03 PM PDT 24
Finished May 12 01:31:05 PM PDT 24
Peak memory 209460 kb
Host smart-07d61676-d8fd-4b14-8420-988f41c7ecb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966172812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3966172812
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2199301845
Short name T12
Test name
Test status
Simulation time 14974562 ps
CPU time 0.74 seconds
Started May 12 01:31:05 PM PDT 24
Finished May 12 01:31:07 PM PDT 24
Peak memory 209268 kb
Host smart-4669d933-1077-49a0-a8b5-f65bc5003c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2199301845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2199301845
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1038943606
Short name T337
Test name
Test status
Simulation time 954226713 ps
CPU time 9.09 seconds
Started May 12 01:31:02 PM PDT 24
Finished May 12 01:31:12 PM PDT 24
Peak memory 217888 kb
Host smart-0c06e08b-8194-467c-be19-dc91805e2c7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1038943606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1038943606
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1630172392
Short name T6
Test name
Test status
Simulation time 1592954961 ps
CPU time 5.01 seconds
Started May 12 01:31:04 PM PDT 24
Finished May 12 01:31:10 PM PDT 24
Peak memory 217244 kb
Host smart-36faf20c-c133-4171-a3f8-6ebe663aef15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630172392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1630172392
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1235243411
Short name T300
Test name
Test status
Simulation time 1465293883 ps
CPU time 41.97 seconds
Started May 12 01:31:05 PM PDT 24
Finished May 12 01:31:48 PM PDT 24
Peak memory 218008 kb
Host smart-fb7c327f-ef4b-412b-863a-6ec374d8bf7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235243411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1235243411
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1617579933
Short name T574
Test name
Test status
Simulation time 298491505 ps
CPU time 4.44 seconds
Started May 12 01:31:05 PM PDT 24
Finished May 12 01:31:10 PM PDT 24
Peak memory 217276 kb
Host smart-7835502d-8f9c-447a-a309-6a9e33e5a937
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617579933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
617579933
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2969635109
Short name T23
Test name
Test status
Simulation time 771869350 ps
CPU time 5.9 seconds
Started May 12 01:31:02 PM PDT 24
Finished May 12 01:31:09 PM PDT 24
Peak memory 217984 kb
Host smart-7eaaa0b9-2ec7-46b8-9a0d-cead9345f803
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969635109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2969635109
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2557382753
Short name T820
Test name
Test status
Simulation time 4742214875 ps
CPU time 35.27 seconds
Started May 12 01:31:04 PM PDT 24
Finished May 12 01:31:40 PM PDT 24
Peak memory 214216 kb
Host smart-614c9f85-df73-46cc-bad2-aa5b285724df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557382753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2557382753
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.724137229
Short name T683
Test name
Test status
Simulation time 604517984 ps
CPU time 2.79 seconds
Started May 12 01:31:02 PM PDT 24
Finished May 12 01:31:06 PM PDT 24
Peak memory 213160 kb
Host smart-3a690958-2c8a-4d93-9f55-5b824b90de1f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724137229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.724137229
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1291928157
Short name T227
Test name
Test status
Simulation time 3972478341 ps
CPU time 47.55 seconds
Started May 12 01:31:03 PM PDT 24
Finished May 12 01:31:51 PM PDT 24
Peak memory 268312 kb
Host smart-bba53ac1-f086-42a7-8962-145474bc5540
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291928157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1291928157
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.713661608
Short name T744
Test name
Test status
Simulation time 888195933 ps
CPU time 13.15 seconds
Started May 12 01:31:07 PM PDT 24
Finished May 12 01:31:21 PM PDT 24
Peak memory 250904 kb
Host smart-1198132e-54e6-4b71-9092-3159f9b22535
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713661608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.713661608
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.3990889000
Short name T605
Test name
Test status
Simulation time 227481928 ps
CPU time 1.73 seconds
Started May 12 01:31:02 PM PDT 24
Finished May 12 01:31:04 PM PDT 24
Peak memory 218008 kb
Host smart-98a26b62-6c09-4e61-bcc1-331866a256c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990889000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.3990889000
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2354371235
Short name T509
Test name
Test status
Simulation time 3215749794 ps
CPU time 4.43 seconds
Started May 12 01:31:03 PM PDT 24
Finished May 12 01:31:08 PM PDT 24
Peak memory 213640 kb
Host smart-7f4d13dd-03a8-4bd5-b169-04fca9351da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354371235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2354371235
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.235242588
Short name T788
Test name
Test status
Simulation time 8167889956 ps
CPU time 17.88 seconds
Started May 12 01:31:05 PM PDT 24
Finished May 12 01:31:23 PM PDT 24
Peak memory 218392 kb
Host smart-f2a8ac02-5e78-478c-92b4-50a5e85dcacd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235242588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.235242588
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2607316463
Short name T705
Test name
Test status
Simulation time 1176827725 ps
CPU time 9.75 seconds
Started May 12 01:31:04 PM PDT 24
Finished May 12 01:31:15 PM PDT 24
Peak memory 217988 kb
Host smart-cc2fff5b-9c65-41d2-a377-582e08c85900
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607316463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2607316463
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.3210195923
Short name T394
Test name
Test status
Simulation time 514130659 ps
CPU time 11.11 seconds
Started May 12 01:31:06 PM PDT 24
Finished May 12 01:31:17 PM PDT 24
Peak memory 218048 kb
Host smart-118dc636-8ff1-47fe-a1f2-46fbf019dae1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210195923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.3
210195923
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2270716387
Short name T671
Test name
Test status
Simulation time 746308958 ps
CPU time 13.06 seconds
Started May 12 01:31:01 PM PDT 24
Finished May 12 01:31:14 PM PDT 24
Peak memory 218060 kb
Host smart-3dcb48ec-0b4a-41c0-b489-78ee30899866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270716387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2270716387
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3508539279
Short name T639
Test name
Test status
Simulation time 61140384 ps
CPU time 2.85 seconds
Started May 12 01:31:02 PM PDT 24
Finished May 12 01:31:06 PM PDT 24
Peak memory 217752 kb
Host smart-32ab8102-2079-4be8-91de-332c14e70ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508539279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3508539279
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2450252950
Short name T92
Test name
Test status
Simulation time 1359447759 ps
CPU time 31.64 seconds
Started May 12 01:31:05 PM PDT 24
Finished May 12 01:31:37 PM PDT 24
Peak memory 248540 kb
Host smart-9d737c65-7d4f-4043-8c91-2d7f2bc23926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450252950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2450252950
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.1926413488
Short name T518
Test name
Test status
Simulation time 109509142 ps
CPU time 6.3 seconds
Started May 12 01:31:04 PM PDT 24
Finished May 12 01:31:10 PM PDT 24
Peak memory 250952 kb
Host smart-3c833974-4ff5-4aaa-abef-580f05050aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926413488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1926413488
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1053968244
Short name T535
Test name
Test status
Simulation time 8956240073 ps
CPU time 302.4 seconds
Started May 12 01:31:01 PM PDT 24
Finished May 12 01:36:05 PM PDT 24
Peak memory 277444 kb
Host smart-2d1af430-ddd7-4626-b792-e5d026919148
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053968244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1053968244
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.353535425
Short name T131
Test name
Test status
Simulation time 45451334161 ps
CPU time 449.01 seconds
Started May 12 01:31:04 PM PDT 24
Finished May 12 01:38:33 PM PDT 24
Peak memory 283768 kb
Host smart-ed37a959-1ad2-4664-82e7-fe4defad6f1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=353535425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.353535425
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1409574487
Short name T396
Test name
Test status
Simulation time 30150941 ps
CPU time 0.96 seconds
Started May 12 01:31:02 PM PDT 24
Finished May 12 01:31:04 PM PDT 24
Peak memory 211656 kb
Host smart-00f0f822-85fd-4614-94df-7487c81051a3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409574487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1409574487
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.1948834171
Short name T618
Test name
Test status
Simulation time 64816861 ps
CPU time 0.93 seconds
Started May 12 01:31:08 PM PDT 24
Finished May 12 01:31:10 PM PDT 24
Peak memory 209540 kb
Host smart-1eb9febe-9797-4d19-bde7-029009223922
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948834171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.1948834171
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3208685313
Short name T690
Test name
Test status
Simulation time 1956085854 ps
CPU time 15.07 seconds
Started May 12 01:31:08 PM PDT 24
Finished May 12 01:31:23 PM PDT 24
Peak memory 218084 kb
Host smart-2077de11-0879-44fd-bb09-d8692178a1fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208685313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3208685313
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.1449466000
Short name T425
Test name
Test status
Simulation time 1244187848 ps
CPU time 1.51 seconds
Started May 12 01:31:10 PM PDT 24
Finished May 12 01:31:12 PM PDT 24
Peak memory 209508 kb
Host smart-f815ad19-d297-41d5-8805-def3e2bcc8ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449466000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.1449466000
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.2163651346
Short name T816
Test name
Test status
Simulation time 8692810183 ps
CPU time 69.17 seconds
Started May 12 01:31:07 PM PDT 24
Finished May 12 01:32:16 PM PDT 24
Peak memory 219080 kb
Host smart-1dbbbe7b-18b1-41e6-be98-bc7f882d2d49
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163651346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.2163651346
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.550431999
Short name T463
Test name
Test status
Simulation time 746507079 ps
CPU time 7.21 seconds
Started May 12 01:31:08 PM PDT 24
Finished May 12 01:31:16 PM PDT 24
Peak memory 217720 kb
Host smart-28220d94-b12d-4b90-8d37-2d80578a5ea0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550431999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.550431999
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2125063589
Short name T295
Test name
Test status
Simulation time 719282532 ps
CPU time 6.27 seconds
Started May 12 01:31:07 PM PDT 24
Finished May 12 01:31:14 PM PDT 24
Peak memory 217948 kb
Host smart-17318100-d28d-4f65-9a09-16bccb4e2408
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125063589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2125063589
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1816987651
Short name T873
Test name
Test status
Simulation time 2268750385 ps
CPU time 22.21 seconds
Started May 12 01:31:10 PM PDT 24
Finished May 12 01:31:33 PM PDT 24
Peak memory 213452 kb
Host smart-d05a3781-77af-499c-92fd-542ec05b04bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816987651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1816987651
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1822637125
Short name T617
Test name
Test status
Simulation time 451601038 ps
CPU time 11.54 seconds
Started May 12 01:31:08 PM PDT 24
Finished May 12 01:31:20 PM PDT 24
Peak memory 213840 kb
Host smart-88e31350-a4f3-4520-8e5c-a2fd84da7cff
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822637125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1822637125
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.860265047
Short name T866
Test name
Test status
Simulation time 8530057129 ps
CPU time 73.15 seconds
Started May 12 01:31:06 PM PDT 24
Finished May 12 01:32:20 PM PDT 24
Peak memory 276316 kb
Host smart-24026114-7c49-46aa-9a4e-dec156a1d631
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860265047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.860265047
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3673259625
Short name T476
Test name
Test status
Simulation time 1639865870 ps
CPU time 11.53 seconds
Started May 12 01:31:05 PM PDT 24
Finished May 12 01:31:18 PM PDT 24
Peak memory 226304 kb
Host smart-3ab17420-8c47-4f1b-95be-d6f00311ef0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673259625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3673259625
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.662304253
Short name T603
Test name
Test status
Simulation time 68549785 ps
CPU time 2.63 seconds
Started May 12 01:31:05 PM PDT 24
Finished May 12 01:31:09 PM PDT 24
Peak memory 218076 kb
Host smart-7193d91b-f039-4cce-883c-52f5cd4b6a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662304253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.662304253
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3966099085
Short name T584
Test name
Test status
Simulation time 199481424 ps
CPU time 7.87 seconds
Started May 12 01:31:05 PM PDT 24
Finished May 12 01:31:14 PM PDT 24
Peak memory 214184 kb
Host smart-ad3aee41-8834-4181-832c-67d628061410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966099085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3966099085
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.3973984341
Short name T388
Test name
Test status
Simulation time 281513849 ps
CPU time 11.67 seconds
Started May 12 01:31:16 PM PDT 24
Finished May 12 01:31:28 PM PDT 24
Peak memory 226036 kb
Host smart-a48c41eb-8793-412e-9b09-994f20449ba9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973984341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3973984341
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3025146532
Short name T327
Test name
Test status
Simulation time 375564624 ps
CPU time 10.82 seconds
Started May 12 01:31:16 PM PDT 24
Finished May 12 01:31:27 PM PDT 24
Peak memory 218000 kb
Host smart-b7c5eb99-e760-4fa6-b0f9-b1ef1b619dd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025146532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3025146532
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1778684839
Short name T594
Test name
Test status
Simulation time 2273019813 ps
CPU time 13.08 seconds
Started May 12 01:31:07 PM PDT 24
Finished May 12 01:31:21 PM PDT 24
Peak memory 218040 kb
Host smart-4c57da8d-679e-45ae-af9c-28b2177d045c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778684839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
778684839
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.3529401075
Short name T347
Test name
Test status
Simulation time 658528702 ps
CPU time 9.4 seconds
Started May 12 01:31:05 PM PDT 24
Finished May 12 01:31:15 PM PDT 24
Peak memory 218064 kb
Host smart-0b1a4bb3-bd0a-45cf-932e-2200db9c1590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529401075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.3529401075
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1886105896
Short name T440
Test name
Test status
Simulation time 28479049 ps
CPU time 1.29 seconds
Started May 12 01:31:07 PM PDT 24
Finished May 12 01:31:09 PM PDT 24
Peak memory 213388 kb
Host smart-9c37a400-5af2-45cd-88c4-5b36a3f2c224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886105896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1886105896
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.4126756946
Short name T769
Test name
Test status
Simulation time 484344863 ps
CPU time 29.93 seconds
Started May 12 01:31:05 PM PDT 24
Finished May 12 01:31:35 PM PDT 24
Peak memory 247644 kb
Host smart-7afe87ab-32b1-48e6-aa30-9a539884db67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126756946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.4126756946
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1894061123
Short name T863
Test name
Test status
Simulation time 59055531 ps
CPU time 6.28 seconds
Started May 12 01:31:08 PM PDT 24
Finished May 12 01:31:14 PM PDT 24
Peak memory 246756 kb
Host smart-ada6df83-a77d-43d0-867d-ac5bc6b5e8bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894061123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1894061123
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.2358198649
Short name T714
Test name
Test status
Simulation time 4402101783 ps
CPU time 114.67 seconds
Started May 12 01:31:08 PM PDT 24
Finished May 12 01:33:04 PM PDT 24
Peak memory 268116 kb
Host smart-cc8f609b-4167-4beb-9251-363b466a77ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358198649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.2358198649
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.3339348343
Short name T615
Test name
Test status
Simulation time 33213130216 ps
CPU time 784.09 seconds
Started May 12 01:31:09 PM PDT 24
Finished May 12 01:44:13 PM PDT 24
Peak memory 496968 kb
Host smart-8f828e53-4de4-4c55-9896-966f96e47cd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3339348343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.3339348343
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3361079214
Short name T582
Test name
Test status
Simulation time 33522664 ps
CPU time 0.92 seconds
Started May 12 01:31:04 PM PDT 24
Finished May 12 01:31:06 PM PDT 24
Peak memory 211588 kb
Host smart-2df4dc93-bc8e-40c6-aa1e-0048dae77564
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361079214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3361079214
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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