Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50990 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[1] |
1859 |
1 |
|
|
T17 |
9 |
|
T18 |
12 |
|
T19 |
6 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52091 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
80 |
auto[1] |
758 |
1 |
|
|
T3 |
16 |
|
T38 |
14 |
|
T54 |
12 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51121 |
1 |
|
|
T1 |
82 |
|
T2 |
65 |
|
T3 |
96 |
auto[1] |
1728 |
1 |
|
|
T1 |
10 |
|
T2 |
7 |
|
T26 |
6 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51141 |
1 |
|
|
T1 |
85 |
|
T2 |
64 |
|
T3 |
96 |
auto[1] |
1708 |
1 |
|
|
T1 |
7 |
|
T2 |
8 |
|
T26 |
9 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51093 |
1 |
|
|
T1 |
81 |
|
T2 |
68 |
|
T3 |
96 |
auto[1] |
1756 |
1 |
|
|
T1 |
11 |
|
T2 |
4 |
|
T26 |
8 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
48044 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
no_err_inj |
4805 |
1 |
|
|
T6 |
8 |
|
T28 |
9 |
|
T18 |
21 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51007 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[1] |
1842 |
1 |
|
|
T17 |
12 |
|
T18 |
10 |
|
T19 |
6 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52068 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
80 |
auto[1] |
781 |
1 |
|
|
T3 |
16 |
|
T38 |
16 |
|
T54 |
12 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37058 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[1] |
15791 |
1 |
|
|
T5 |
6 |
|
T6 |
8 |
|
T17 |
92 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51141 |
1 |
|
|
T1 |
83 |
|
T2 |
63 |
|
T3 |
96 |
auto[1] |
1708 |
1 |
|
|
T1 |
9 |
|
T2 |
9 |
|
T26 |
12 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51120 |
1 |
|
|
T1 |
78 |
|
T2 |
66 |
|
T3 |
96 |
auto[1] |
1729 |
1 |
|
|
T1 |
14 |
|
T2 |
6 |
|
T26 |
15 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51118 |
1 |
|
|
T1 |
81 |
|
T2 |
66 |
|
T3 |
96 |
auto[1] |
1731 |
1 |
|
|
T1 |
11 |
|
T2 |
6 |
|
T26 |
8 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50951 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[1] |
1898 |
1 |
|
|
T17 |
18 |
|
T18 |
13 |
|
T19 |
13 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50543 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[1] |
2306 |
1 |
|
|
T5 |
6 |
|
T53 |
4 |
|
T18 |
54 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52098 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
74 |
auto[1] |
751 |
1 |
|
|
T3 |
22 |
|
T38 |
21 |
|
T54 |
11 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52084 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
72 |
auto[1] |
765 |
1 |
|
|
T3 |
24 |
|
T38 |
11 |
|
T54 |
12 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52085 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
78 |
auto[1] |
764 |
1 |
|
|
T3 |
18 |
|
T38 |
13 |
|
T54 |
12 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50391 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[1] |
2458 |
1 |
|
|
T28 |
15 |
|
T18 |
13 |
|
T66 |
13 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48987 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[1] |
3862 |
1 |
|
|
T15 |
71 |
|
T20 |
83 |
|
T22 |
98 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51062 |
1 |
|
|
T1 |
81 |
|
T2 |
64 |
|
T3 |
96 |
auto[1] |
1787 |
1 |
|
|
T1 |
11 |
|
T2 |
8 |
|
T26 |
15 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51118 |
1 |
|
|
T1 |
81 |
|
T2 |
60 |
|
T3 |
96 |
auto[1] |
1731 |
1 |
|
|
T1 |
11 |
|
T2 |
12 |
|
T26 |
8 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51109 |
1 |
|
|
T1 |
84 |
|
T2 |
60 |
|
T3 |
96 |
auto[1] |
1740 |
1 |
|
|
T1 |
8 |
|
T2 |
12 |
|
T26 |
16 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51036 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[1] |
1813 |
1 |
|
|
T17 |
4 |
|
T18 |
13 |
|
T19 |
14 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47347 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[1] |
5502 |
1 |
|
|
T12 |
65 |
|
T23 |
81 |
|
T17 |
10 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48921 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[1] |
3928 |
1 |
|
|
T13 |
56 |
|
T14 |
60 |
|
T16 |
66 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52849 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50956 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[1] |
1893 |
1 |
|
|
T17 |
10 |
|
T18 |
9 |
|
T19 |
11 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50989 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[1] |
1860 |
1 |
|
|
T17 |
16 |
|
T18 |
12 |
|
T19 |
9 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51005 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[1] |
1844 |
1 |
|
|
T17 |
13 |
|
T18 |
9 |
|
T19 |
8 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
46790 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[0] |
no_err_inj |
3601 |
1 |
|
|
T6 |
8 |
|
T18 |
15 |
|
T51 |
6 |
auto[1] |
err_inj |
1254 |
1 |
|
|
T28 |
6 |
|
T18 |
7 |
|
T66 |
9 |
auto[1] |
no_err_inj |
1204 |
1 |
|
|
T28 |
9 |
|
T18 |
6 |
|
T66 |
4 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48801 |
1 |
|
|
T1 |
81 |
|
T2 |
60 |
|
T3 |
96 |
auto[0] |
auto[1] |
1590 |
1 |
|
|
T1 |
11 |
|
T2 |
12 |
|
T26 |
8 |
auto[1] |
auto[0] |
2317 |
1 |
|
|
T28 |
15 |
|
T18 |
12 |
|
T66 |
12 |
auto[1] |
auto[1] |
141 |
1 |
|
|
T18 |
1 |
|
T66 |
1 |
|
T21 |
3 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48808 |
1 |
|
|
T1 |
78 |
|
T2 |
66 |
|
T3 |
96 |
auto[0] |
auto[1] |
1583 |
1 |
|
|
T1 |
14 |
|
T2 |
6 |
|
T26 |
15 |
auto[1] |
auto[0] |
2312 |
1 |
|
|
T28 |
14 |
|
T18 |
12 |
|
T66 |
13 |
auto[1] |
auto[1] |
146 |
1 |
|
|
T28 |
1 |
|
T18 |
1 |
|
T21 |
5 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48790 |
1 |
|
|
T1 |
84 |
|
T2 |
60 |
|
T3 |
96 |
auto[0] |
auto[1] |
1601 |
1 |
|
|
T1 |
8 |
|
T2 |
12 |
|
T26 |
16 |
auto[1] |
auto[0] |
2319 |
1 |
|
|
T28 |
14 |
|
T18 |
12 |
|
T66 |
13 |
auto[1] |
auto[1] |
139 |
1 |
|
|
T28 |
1 |
|
T18 |
1 |
|
T21 |
3 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48814 |
1 |
|
|
T1 |
85 |
|
T2 |
64 |
|
T3 |
96 |
auto[0] |
auto[1] |
1577 |
1 |
|
|
T1 |
7 |
|
T2 |
8 |
|
T26 |
9 |
auto[1] |
auto[0] |
2327 |
1 |
|
|
T28 |
15 |
|
T18 |
13 |
|
T66 |
11 |
auto[1] |
auto[1] |
131 |
1 |
|
|
T66 |
2 |
|
T21 |
1 |
|
T138 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48760 |
1 |
|
|
T1 |
81 |
|
T2 |
68 |
|
T3 |
96 |
auto[0] |
auto[1] |
1631 |
1 |
|
|
T1 |
11 |
|
T2 |
4 |
|
T26 |
8 |
auto[1] |
auto[0] |
2333 |
1 |
|
|
T28 |
15 |
|
T18 |
12 |
|
T66 |
10 |
auto[1] |
auto[1] |
125 |
1 |
|
|
T18 |
1 |
|
T66 |
3 |
|
T138 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
48808 |
1 |
|
|
T1 |
82 |
|
T2 |
65 |
|
T3 |
96 |
auto[0] |
auto[1] |
1583 |
1 |
|
|
T1 |
10 |
|
T2 |
7 |
|
T26 |
6 |
auto[1] |
auto[0] |
2313 |
1 |
|
|
T28 |
12 |
|
T18 |
13 |
|
T66 |
13 |
auto[1] |
auto[1] |
145 |
1 |
|
|
T28 |
3 |
|
T21 |
5 |
|
T138 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35960 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[0] |
auto[1] |
1098 |
1 |
|
|
T18 |
12 |
|
T177 |
5 |
|
T21 |
12 |
auto[1] |
auto[0] |
15030 |
1 |
|
|
T5 |
6 |
|
T6 |
8 |
|
T17 |
83 |
auto[1] |
auto[1] |
761 |
1 |
|
|
T17 |
9 |
|
T19 |
6 |
|
T21 |
14 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35949 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[0] |
auto[1] |
1109 |
1 |
|
|
T18 |
10 |
|
T177 |
7 |
|
T21 |
8 |
auto[1] |
auto[0] |
15058 |
1 |
|
|
T5 |
6 |
|
T6 |
8 |
|
T17 |
80 |
auto[1] |
auto[1] |
733 |
1 |
|
|
T17 |
12 |
|
T19 |
6 |
|
T21 |
16 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35738 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[0] |
auto[1] |
1320 |
1 |
|
|
T53 |
4 |
|
T18 |
18 |
|
T178 |
10 |
auto[1] |
auto[0] |
14805 |
1 |
|
|
T6 |
8 |
|
T17 |
92 |
|
T24 |
90 |
auto[1] |
auto[1] |
986 |
1 |
|
|
T5 |
6 |
|
T18 |
36 |
|
T21 |
68 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35949 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[0] |
auto[1] |
1109 |
1 |
|
|
T18 |
13 |
|
T177 |
6 |
|
T21 |
7 |
auto[1] |
auto[0] |
15002 |
1 |
|
|
T5 |
6 |
|
T6 |
8 |
|
T17 |
74 |
auto[1] |
auto[1] |
789 |
1 |
|
|
T17 |
18 |
|
T19 |
13 |
|
T21 |
12 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32311 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[0] |
auto[1] |
4747 |
1 |
|
|
T12 |
65 |
|
T23 |
81 |
|
T18 |
12 |
auto[1] |
auto[0] |
15036 |
1 |
|
|
T5 |
6 |
|
T6 |
8 |
|
T17 |
82 |
auto[1] |
auto[1] |
755 |
1 |
|
|
T17 |
10 |
|
T19 |
12 |
|
T21 |
11 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36060 |
1 |
|
|
T1 |
81 |
|
T2 |
60 |
|
T3 |
96 |
auto[0] |
auto[1] |
998 |
1 |
|
|
T1 |
11 |
|
T2 |
12 |
|
T26 |
8 |
auto[1] |
auto[0] |
15058 |
1 |
|
|
T5 |
6 |
|
T6 |
8 |
|
T17 |
92 |
auto[1] |
auto[1] |
733 |
1 |
|
|
T24 |
11 |
|
T21 |
16 |
|
T57 |
7 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36006 |
1 |
|
|
T1 |
81 |
|
T2 |
64 |
|
T3 |
96 |
auto[0] |
auto[1] |
1052 |
1 |
|
|
T1 |
11 |
|
T2 |
8 |
|
T26 |
15 |
auto[1] |
auto[0] |
15056 |
1 |
|
|
T5 |
6 |
|
T6 |
8 |
|
T17 |
92 |
auto[1] |
auto[1] |
735 |
1 |
|
|
T24 |
8 |
|
T21 |
17 |
|
T57 |
7 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36044 |
1 |
|
|
T1 |
78 |
|
T2 |
66 |
|
T3 |
96 |
auto[0] |
auto[1] |
1014 |
1 |
|
|
T1 |
14 |
|
T2 |
6 |
|
T26 |
15 |
auto[1] |
auto[0] |
15076 |
1 |
|
|
T5 |
6 |
|
T6 |
8 |
|
T17 |
92 |
auto[1] |
auto[1] |
715 |
1 |
|
|
T24 |
7 |
|
T21 |
14 |
|
T57 |
7 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36045 |
1 |
|
|
T1 |
83 |
|
T2 |
63 |
|
T3 |
96 |
auto[0] |
auto[1] |
1013 |
1 |
|
|
T1 |
9 |
|
T2 |
9 |
|
T26 |
12 |
auto[1] |
auto[0] |
15096 |
1 |
|
|
T5 |
6 |
|
T6 |
8 |
|
T17 |
92 |
auto[1] |
auto[1] |
695 |
1 |
|
|
T24 |
10 |
|
T21 |
15 |
|
T57 |
7 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36094 |
1 |
|
|
T1 |
85 |
|
T2 |
64 |
|
T3 |
96 |
auto[0] |
auto[1] |
964 |
1 |
|
|
T1 |
7 |
|
T2 |
8 |
|
T26 |
9 |
auto[1] |
auto[0] |
15047 |
1 |
|
|
T5 |
6 |
|
T6 |
8 |
|
T17 |
92 |
auto[1] |
auto[1] |
744 |
1 |
|
|
T24 |
7 |
|
T21 |
8 |
|
T57 |
13 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36059 |
1 |
|
|
T1 |
82 |
|
T2 |
65 |
|
T3 |
96 |
auto[0] |
auto[1] |
999 |
1 |
|
|
T1 |
10 |
|
T2 |
7 |
|
T26 |
6 |
auto[1] |
auto[0] |
15062 |
1 |
|
|
T5 |
6 |
|
T6 |
8 |
|
T17 |
92 |
auto[1] |
auto[1] |
729 |
1 |
|
|
T24 |
14 |
|
T21 |
15 |
|
T57 |
6 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36034 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[0] |
auto[1] |
1024 |
1 |
|
|
T18 |
9 |
|
T177 |
8 |
|
T21 |
15 |
auto[1] |
auto[0] |
14971 |
1 |
|
|
T5 |
6 |
|
T6 |
8 |
|
T17 |
79 |
auto[1] |
auto[1] |
820 |
1 |
|
|
T17 |
13 |
|
T19 |
8 |
|
T21 |
13 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35963 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[0] |
auto[1] |
1095 |
1 |
|
|
T18 |
12 |
|
T177 |
11 |
|
T21 |
9 |
auto[1] |
auto[0] |
15026 |
1 |
|
|
T5 |
6 |
|
T6 |
8 |
|
T17 |
76 |
auto[1] |
auto[1] |
765 |
1 |
|
|
T17 |
16 |
|
T19 |
9 |
|
T21 |
14 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35744 |
1 |
|
|
T1 |
92 |
|
T2 |
72 |
|
T3 |
96 |
auto[0] |
auto[1] |
1314 |
1 |
|
|
T28 |
15 |
|
T18 |
13 |
|
T66 |
13 |
auto[1] |
auto[0] |
14647 |
1 |
|
|
T5 |
6 |
|
T6 |
8 |
|
T17 |
92 |
auto[1] |
auto[1] |
1144 |
1 |
|
|
T21 |
49 |
|
T57 |
10 |
|
T214 |
13 |