Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105149294

1

T1

27212

T2

21989

T3

35803

auto[1]

1380026

1

T1

3663

T2

2970

T3

1881

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

105175578

1

T1

27311

T2

22583

T3

35605

auto[1]

1353742

1

T1

3564

T2

2376

T3

2079

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7259707	1			T1	9180		T2	7237		T3	8887
auto[IdleSt]	20742331	1			T1	1442		T2	1222		T3	2431
auto[ClkMuxSt]	36111	1			T3	72		T12	65		T13	56
auto[CntIncrSt]	35768	1			T3	72		T12	65		T13	56
auto[CntProgSt]	1776503	1			T3	2274		T12	1617		T13	12868
auto[TransCheckSt]	27844	1			T3	56		T12	65		T13	56
auto[TokenHashSt]	45783108	1			T3	5482		T12	5301		T13	2848
auto[FlashRmaSt]	29709	1			T3	188		T13	65		T14	59
auto[TokenCheck0St]	12960	1			T3	48		T13	22		T14	24
auto[TokenCheck1St]	9559	1			T3	35		T13	7		T14	8
auto[TransProgSt]	419475	1			T3	1524		T15	66		T6	717
auto[PostTransSt]	12545871	1			T3	9623		T12	11383		T13	8668
auto[ScrapSt]	285277	1			T11	1174		T15	3		T18	2985
auto[EscalateSt]	6517728	1			T1	10242		T2	7505		T3	5109
auto[InvalidSt]	11045558	1			T1	9997		T2	8989		T3	1883

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1811	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11045558	1			T1	9997		T2	8989		T3	1883
EscalateSt	6517728	1			T1	10242		T2	7505		T3	5109
ScrapSt	285277	1			T11	1174		T15	3		T18	2985
PostTransSt	12545871	1			T3	9623		T12	11383		T13	8668
TransProgSt	419475	1			T3	1524		T15	66		T6	717
TokenCheck1St	9559	1			T3	35		T13	7		T14	8
TokenCheck0St	12960	1			T3	48		T13	22		T14	24
FlashRmaSt	29709	1			T3	188		T13	65		T14	59
TokenHashSt	45783108	1			T3	5482		T12	5301		T13	2848
TransCheckSt	27844	1			T3	56		T12	65		T13	56
CntProgSt	1776503	1			T3	2274		T12	1617		T13	12868
CntIncrSt	35768	1			T3	72		T12	65		T13	56
ClkMuxSt	36111	1			T3	72		T12	65		T13	56
IdleSt	20742331	1			T1	1442		T2	1222		T3	2431
ResetSt	7259707	1			T1	9180		T2	7237		T3	8887
arcs[ResetSt=>IdleSt]	53323	1			T1	82		T2	67		T3	97
arcs[IdleSt=>ScrapSt]	302	1			T11	1		T15	1		T18	2
arcs[IdleSt=>ClkMuxSt]	35824	1			T3	72		T12	65		T13	56
arcs[ClkMuxSt=>CntIncrSt]	35768	1			T3	72		T12	65		T13	56
arcs[CntIncrSt=>PostTransSt]	1861	1			T17	16		T18	12		T19	9
arcs[CntIncrSt=>CntProgSt]	33838	1			T3	72		T12	65		T13	56
arcs[CntProgSt=>PostTransSt]	4880	1			T3	16		T5	6		T17	7
arcs[CntProgSt=>TransCheckSt]	27844	1			T3	56		T12	65		T13	56
arcs[TransCheckSt=>PostTransSt]	3746	1			T13	27		T14	31		T16	35
arcs[TransCheckSt=>TokenHashSt]	23976	1			T3	56		T12	65		T13	29
arcs[TokenHashSt=>PostTransSt]	10220	1			T3	8		T12	65		T13	7
arcs[TokenHashSt=>FlashRmaSt]	13054	1			T3	48		T13	22		T14	24
arcs[FlashRmaSt=>TokenCheck0St]	12960	1			T3	48		T13	22		T14	24
arcs[TokenCheck0St=>PostTransSt]	3376	1			T3	13		T13	15		T14	16
arcs[TokenCheck0St=>TokenCheck1St]	9559	1			T3	35		T13	7		T14	8
arcs[TokenCheck1St=>PostTransSt]	692	1			T3	3		T13	7		T14	8
arcs[TransProgSt=>PostTransSt]	7996	1			T3	32		T15	1		T6	8
arcs[IdleSt=>EscalateSt]	262	1			T15	7		T20	5		T22	7
arcs[ClkMuxSt=>EscalateSt]	56	1			T15	1		T20	2		T22	1
arcs[CntIncrSt=>EscalateSt]	69	1			T15	2		T22	1		T44	2
arcs[CntProgSt=>EscalateSt]	1114	1			T15	23		T20	30		T22	24
arcs[TransCheckSt=>EscalateSt]	122	1			T20	2		T22	4		T49	2
arcs[TokenHashSt=>EscalateSt]	702	1			T15	9		T20	11		T22	22
arcs[FlashRmaSt=>EscalateSt]	94	1			T20	4		T22	3		T45	2
arcs[TokenCheck0St=>EscalateSt]	25	1			T22	2		T45	1		T49	1
arcs[TokenCheck1St=>EscalateSt]	131	1			T15	1		T20	2		T22	4
arcs[TransProgSt=>EscalateSt]	740	1			T15	23		T20	19		T22	22
arcs[PostTransSt=>EscalateSt]	5177	1			T3	16		T15	1		T5	6
arcs[InvalidSt=>EscalateSt]	12925	1			T1	73		T2	54		T3	24

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7259539	1			T1	9180		T2	7237		T3	8887
auto[0]	auto[IdleSt]	20742167	1			T1	1442		T2	1222		T3	2431
auto[0]	auto[ClkMuxSt]	36071	1			T3	72		T12	65		T13	56
auto[0]	auto[CntIncrSt]	35716	1			T3	72		T12	65		T13	56
auto[0]	auto[CntProgSt]	1775761	1			T3	2274		T12	1617		T13	12868
auto[0]	auto[TransCheckSt]	27759	1			T3	56		T12	65		T13	56
auto[0]	auto[TokenHashSt]	45782651	1			T3	5482		T12	5301		T13	2848
auto[0]	auto[FlashRmaSt]	29651	1			T3	188		T13	65		T14	59
auto[0]	auto[TokenCheck0St]	12944	1			T3	48		T13	22		T14	24
auto[0]	auto[TokenCheck1St]	9470	1			T3	35		T13	7		T14	8
auto[0]	auto[TransProgSt]	418995	1			T3	1524		T15	51		T6	717
auto[0]	auto[PostTransSt]	12543211	1			T3	9613		T12	11383		T13	8668
auto[0]	auto[ScrapSt]	285232	1			T11	1174		T15	2		T18	2985
auto[0]	auto[EscalateSt]	5149283	1			T1	6616		T2	4565		T3	3247
auto[0]	auto[InvalidSt]	11039033	1			T1	9960		T2	8959		T3	1874
auto[1]	auto[ResetSt]	168	1			T15	3		T20	2		T22	4
auto[1]	auto[IdleSt]	164	1			T15	5		T20	1		T22	1
auto[1]	auto[ClkMuxSt]	40	1			T15	1		T49	1		T44	1
auto[1]	auto[CntIncrSt]	52	1			T15	2		T22	1		T44	1
auto[1]	auto[CntProgSt]	742	1			T15	17		T20	21		T22	16
auto[1]	auto[TransCheckSt]	85	1			T20	2		T22	2		T49	1
auto[1]	auto[TokenHashSt]	457	1			T15	6		T20	8		T22	15
auto[1]	auto[FlashRmaSt]	58	1			T20	2		T22	2		T45	1
auto[1]	auto[TokenCheck0St]	16	1			T22	1		T45	1		T211	1
auto[1]	auto[TokenCheck1St]	89	1			T15	1		T20	2		T22	4
auto[1]	auto[TransProgSt]	480	1			T15	15		T20	10		T22	16
auto[1]	auto[PostTransSt]	2660	1			T3	10		T15	1		T5	4
auto[1]	auto[ScrapSt]	45	1			T15	1		T44	1		T211	1
auto[1]	auto[EscalateSt]	1368445	1			T1	3626		T2	2940		T3	1862
auto[1]	auto[InvalidSt]	6525	1			T1	37		T2	30		T3	9

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7259559	1			T1	9180		T2	7237		T3	8887
auto[0]	auto[IdleSt]	20742148	1			T1	1442		T2	1222		T3	2431
auto[0]	auto[ClkMuxSt]	36081	1			T3	72		T12	65		T13	56
auto[0]	auto[CntIncrSt]	35726	1			T3	72		T12	65		T13	56
auto[0]	auto[CntProgSt]	1775786	1			T3	2274		T12	1617		T13	12868
auto[0]	auto[TransCheckSt]	27770	1			T3	56		T12	65		T13	56
auto[0]	auto[TokenHashSt]	45782645	1			T3	5482		T12	5301		T13	2848
auto[0]	auto[FlashRmaSt]	29642	1			T3	188		T13	65		T14	59
auto[0]	auto[TokenCheck0St]	12942	1			T3	48		T13	22		T14	24
auto[0]	auto[TokenCheck1St]	9474	1			T3	35		T13	7		T14	8
auto[0]	auto[TransProgSt]	418990	1			T3	1524		T15	48		T6	717
auto[0]	auto[PostTransSt]	12543267	1			T3	9617		T12	11383		T13	8668
auto[0]	auto[ScrapSt]	285243	1			T11	1174		T15	3		T18	2985
auto[0]	auto[EscalateSt]	5175336	1			T1	6714		T2	5153		T3	3051
auto[0]	auto[InvalidSt]	11039158	1			T1	9961		T2	8965		T3	1868
auto[1]	auto[ResetSt]	148	1			T20	2		T22	1		T45	4
auto[1]	auto[IdleSt]	183	1			T15	6		T20	4		T22	7
auto[1]	auto[ClkMuxSt]	30	1			T20	2		T22	1		T45	1
auto[1]	auto[CntIncrSt]	42	1			T15	1		T44	1		T212	1
auto[1]	auto[CntProgSt]	717	1			T15	14		T20	20		T22	17
auto[1]	auto[TransCheckSt]	74	1			T22	3		T49	2		T44	1
auto[1]	auto[TokenHashSt]	463	1			T15	6		T20	9		T22	16
auto[1]	auto[FlashRmaSt]	67	1			T20	3		T22	2		T45	1
auto[1]	auto[TokenCheck0St]	18	1			T22	2		T49	1		T213	2
auto[1]	auto[TokenCheck1St]	85	1			T15	1		T20	1		T22	3
auto[1]	auto[TransProgSt]	485	1			T15	18		T20	11		T22	12
auto[1]	auto[PostTransSt]	2604	1			T3	6		T15	1		T5	2
auto[1]	auto[ScrapSt]	34	1			T20	2		T22	1		T45	1
auto[1]	auto[EscalateSt]	1342392	1			T1	3528		T2	2352		T3	2058
auto[1]	auto[InvalidSt]	6400	1			T1	36		T2	24		T3	15