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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.86 97.82 95.93 93.31 97.62 98.52 98.51 96.29


Total test records in report: 1000
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T811 /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2258116708 May 14 01:37:14 PM PDT 24 May 14 01:38:07 PM PDT 24 2757313658 ps
T812 /workspace/coverage/default/41.lc_ctrl_errors.3644233805 May 14 01:39:57 PM PDT 24 May 14 01:40:08 PM PDT 24 1369417281 ps
T813 /workspace/coverage/default/3.lc_ctrl_state_failure.3171074147 May 14 01:36:44 PM PDT 24 May 14 01:37:07 PM PDT 24 3667758693 ps
T814 /workspace/coverage/default/14.lc_ctrl_errors.353117772 May 14 01:38:03 PM PDT 24 May 14 01:38:16 PM PDT 24 1469209567 ps
T815 /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1314727449 May 14 01:38:49 PM PDT 24 May 14 01:38:50 PM PDT 24 60775134 ps
T816 /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3227610172 May 14 01:40:07 PM PDT 24 May 14 01:40:09 PM PDT 24 25526450 ps
T817 /workspace/coverage/default/29.lc_ctrl_state_failure.984676619 May 14 01:39:10 PM PDT 24 May 14 01:39:43 PM PDT 24 478694810 ps
T818 /workspace/coverage/default/14.lc_ctrl_security_escalation.1552936561 May 14 01:38:02 PM PDT 24 May 14 01:38:11 PM PDT 24 245658017 ps
T819 /workspace/coverage/default/35.lc_ctrl_stress_all.811552869 May 14 01:39:36 PM PDT 24 May 14 01:41:05 PM PDT 24 12915680130 ps
T145 /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.1560920028 May 14 01:37:15 PM PDT 24 May 14 01:48:41 PM PDT 24 61151103097 ps
T820 /workspace/coverage/default/4.lc_ctrl_security_escalation.1848558850 May 14 01:36:51 PM PDT 24 May 14 01:37:04 PM PDT 24 330391023 ps
T821 /workspace/coverage/default/43.lc_ctrl_prog_failure.3634952790 May 14 01:40:04 PM PDT 24 May 14 01:40:10 PM PDT 24 91141548 ps
T822 /workspace/coverage/default/18.lc_ctrl_jtag_errors.4184619579 May 14 01:38:28 PM PDT 24 May 14 01:38:58 PM PDT 24 7783259378 ps
T823 /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3286918383 May 14 01:37:46 PM PDT 24 May 14 01:38:04 PM PDT 24 3049074128 ps
T158 /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3739245104 May 14 01:38:35 PM PDT 24 May 14 01:55:51 PM PDT 24 126005137837 ps
T824 /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3859080006 May 14 01:36:34 PM PDT 24 May 14 01:36:52 PM PDT 24 344315678 ps
T825 /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3141213531 May 14 01:37:08 PM PDT 24 May 14 01:38:02 PM PDT 24 1194779392 ps
T826 /workspace/coverage/default/24.lc_ctrl_jtag_access.3717821791 May 14 01:38:51 PM PDT 24 May 14 01:38:58 PM PDT 24 1979089025 ps
T827 /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3101868965 May 14 01:40:21 PM PDT 24 May 14 01:40:24 PM PDT 24 39483154 ps
T828 /workspace/coverage/default/48.lc_ctrl_smoke.4068864037 May 14 01:40:30 PM PDT 24 May 14 01:40:34 PM PDT 24 47229104 ps
T146 /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.3606110556 May 14 01:37:34 PM PDT 24 May 14 01:42:06 PM PDT 24 30081616984 ps
T829 /workspace/coverage/default/1.lc_ctrl_state_post_trans.3534049083 May 14 01:36:33 PM PDT 24 May 14 01:36:44 PM PDT 24 74533855 ps
T830 /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1129793913 May 14 01:38:20 PM PDT 24 May 14 01:38:26 PM PDT 24 376681724 ps
T831 /workspace/coverage/default/37.lc_ctrl_state_post_trans.3287558927 May 14 01:39:43 PM PDT 24 May 14 01:39:50 PM PDT 24 97279657 ps
T832 /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3289104221 May 14 01:39:46 PM PDT 24 May 14 01:39:49 PM PDT 24 121430038 ps
T833 /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.124984929 May 14 01:38:43 PM PDT 24 May 14 01:38:45 PM PDT 24 33633200 ps
T834 /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2944042208 May 14 01:39:22 PM PDT 24 May 14 01:39:33 PM PDT 24 887365502 ps
T159 /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.654810639 May 14 01:40:13 PM PDT 24 May 14 02:04:11 PM PDT 24 37024682109 ps
T835 /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3167160355 May 14 01:37:47 PM PDT 24 May 14 01:38:04 PM PDT 24 3159711777 ps
T836 /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1768749359 May 14 01:39:05 PM PDT 24 May 14 01:39:27 PM PDT 24 762708368 ps
T65 /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.370408738 May 14 01:37:31 PM PDT 24 May 14 01:38:06 PM PDT 24 5606484649 ps
T837 /workspace/coverage/default/15.lc_ctrl_alert_test.2985872561 May 14 01:38:11 PM PDT 24 May 14 01:38:13 PM PDT 24 46604024 ps
T838 /workspace/coverage/default/4.lc_ctrl_state_post_trans.4030110932 May 14 01:36:50 PM PDT 24 May 14 01:36:57 PM PDT 24 72079195 ps
T839 /workspace/coverage/default/12.lc_ctrl_jtag_errors.4210694908 May 14 01:37:56 PM PDT 24 May 14 01:38:49 PM PDT 24 1578685260 ps
T840 /workspace/coverage/default/17.lc_ctrl_state_post_trans.2561338638 May 14 01:38:20 PM PDT 24 May 14 01:38:28 PM PDT 24 176888073 ps
T841 /workspace/coverage/default/34.lc_ctrl_errors.1055493876 May 14 01:39:43 PM PDT 24 May 14 01:39:59 PM PDT 24 348248924 ps
T842 /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1310900060 May 14 01:38:21 PM PDT 24 May 14 01:38:24 PM PDT 24 22258223 ps
T843 /workspace/coverage/default/19.lc_ctrl_stress_all.971098957 May 14 01:38:29 PM PDT 24 May 14 01:39:28 PM PDT 24 12517186486 ps
T844 /workspace/coverage/default/28.lc_ctrl_prog_failure.3622397147 May 14 01:39:16 PM PDT 24 May 14 01:39:20 PM PDT 24 117168989 ps
T845 /workspace/coverage/default/7.lc_ctrl_jtag_access.3386137380 May 14 01:37:22 PM PDT 24 May 14 01:37:26 PM PDT 24 263596319 ps
T846 /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2701673730 May 14 01:38:21 PM PDT 24 May 14 01:38:37 PM PDT 24 1219400813 ps
T847 /workspace/coverage/default/40.lc_ctrl_stress_all.1025680536 May 14 01:39:57 PM PDT 24 May 14 01:40:24 PM PDT 24 2443614725 ps
T848 /workspace/coverage/default/5.lc_ctrl_jtag_errors.893027891 May 14 01:37:10 PM PDT 24 May 14 01:38:06 PM PDT 24 35981837133 ps
T849 /workspace/coverage/default/44.lc_ctrl_smoke.2385232148 May 14 01:40:12 PM PDT 24 May 14 01:40:15 PM PDT 24 21090920 ps
T850 /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1071956737 May 14 01:37:13 PM PDT 24 May 14 01:37:15 PM PDT 24 12196012 ps
T851 /workspace/coverage/default/5.lc_ctrl_regwen_during_op.810643047 May 14 01:37:02 PM PDT 24 May 14 01:37:09 PM PDT 24 953156731 ps
T852 /workspace/coverage/default/1.lc_ctrl_smoke.2195874974 May 14 01:36:31 PM PDT 24 May 14 01:36:34 PM PDT 24 161570200 ps
T853 /workspace/coverage/default/15.lc_ctrl_errors.4172331610 May 14 01:38:12 PM PDT 24 May 14 01:38:29 PM PDT 24 612823845 ps
T854 /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2400844215 May 14 01:36:55 PM PDT 24 May 14 01:37:18 PM PDT 24 528851703 ps
T855 /workspace/coverage/default/26.lc_ctrl_state_post_trans.633111225 May 14 01:38:57 PM PDT 24 May 14 01:39:06 PM PDT 24 69701017 ps
T856 /workspace/coverage/default/10.lc_ctrl_alert_test.2605976399 May 14 01:37:41 PM PDT 24 May 14 01:37:43 PM PDT 24 30316578 ps
T857 /workspace/coverage/default/9.lc_ctrl_jtag_priority.2278456876 May 14 01:37:33 PM PDT 24 May 14 01:37:36 PM PDT 24 573465359 ps
T858 /workspace/coverage/default/35.lc_ctrl_jtag_access.3470985586 May 14 01:39:35 PM PDT 24 May 14 01:39:41 PM PDT 24 163442286 ps
T859 /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2546506003 May 14 01:38:43 PM PDT 24 May 14 01:38:53 PM PDT 24 198437921 ps
T860 /workspace/coverage/default/2.lc_ctrl_security_escalation.681819843 May 14 01:36:38 PM PDT 24 May 14 01:36:48 PM PDT 24 263275460 ps
T861 /workspace/coverage/default/28.lc_ctrl_stress_all.2755438215 May 14 01:39:16 PM PDT 24 May 14 01:39:34 PM PDT 24 340921806 ps
T862 /workspace/coverage/default/43.lc_ctrl_state_failure.3173654428 May 14 01:40:04 PM PDT 24 May 14 01:40:38 PM PDT 24 2318455187 ps
T863 /workspace/coverage/default/0.lc_ctrl_jtag_priority.4170364431 May 14 01:36:32 PM PDT 24 May 14 01:36:38 PM PDT 24 151178050 ps
T864 /workspace/coverage/default/14.lc_ctrl_state_post_trans.250925489 May 14 01:38:04 PM PDT 24 May 14 01:38:14 PM PDT 24 154224184 ps
T865 /workspace/coverage/default/11.lc_ctrl_state_failure.938451511 May 14 01:37:39 PM PDT 24 May 14 01:38:13 PM PDT 24 458393137 ps
T866 /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3440874157 May 14 01:37:32 PM PDT 24 May 14 01:38:00 PM PDT 24 1951927884 ps
T867 /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2216364655 May 14 01:40:05 PM PDT 24 May 14 01:40:23 PM PDT 24 2981105843 ps
T868 /workspace/coverage/default/35.lc_ctrl_security_escalation.178318276 May 14 01:39:43 PM PDT 24 May 14 01:39:56 PM PDT 24 1354025499 ps
T869 /workspace/coverage/default/10.lc_ctrl_sec_mubi.157165180 May 14 01:37:39 PM PDT 24 May 14 01:37:55 PM PDT 24 509995281 ps
T870 /workspace/coverage/default/14.lc_ctrl_stress_all.1191075473 May 14 01:38:01 PM PDT 24 May 14 01:40:54 PM PDT 24 19775511429 ps
T97 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2472420368 May 14 01:35:09 PM PDT 24 May 14 01:35:12 PM PDT 24 99743354 ps
T106 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.671740145 May 14 01:34:40 PM PDT 24 May 14 01:34:44 PM PDT 24 346198757 ps
T111 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1082255975 May 14 01:34:57 PM PDT 24 May 14 01:34:59 PM PDT 24 28623147 ps
T107 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1676495276 May 14 01:34:42 PM PDT 24 May 14 01:34:46 PM PDT 24 63171210 ps
T98 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3826691138 May 14 01:34:37 PM PDT 24 May 14 01:34:42 PM PDT 24 737782476 ps
T99 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1188778780 May 14 01:34:43 PM PDT 24 May 14 01:34:47 PM PDT 24 53628559 ps
T108 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1043173289 May 14 01:34:04 PM PDT 24 May 14 01:34:07 PM PDT 24 49282105 ps
T131 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2468147362 May 14 01:34:26 PM PDT 24 May 14 01:34:31 PM PDT 24 1124293469 ps
T133 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2339864708 May 14 01:34:49 PM PDT 24 May 14 01:34:51 PM PDT 24 57301645 ps
T132 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1261280695 May 14 01:34:12 PM PDT 24 May 14 01:34:14 PM PDT 24 41218013 ps
T103 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1609672572 May 14 01:34:42 PM PDT 24 May 14 01:34:46 PM PDT 24 58998573 ps
T109 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.376136638 May 14 01:33:52 PM PDT 24 May 14 01:33:56 PM PDT 24 588071330 ps
T147 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.236463580 May 14 01:34:50 PM PDT 24 May 14 01:34:52 PM PDT 24 84415778 ps
T871 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.203911777 May 14 01:34:04 PM PDT 24 May 14 01:34:07 PM PDT 24 63996207 ps
T872 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3594558937 May 14 01:34:48 PM PDT 24 May 14 01:34:50 PM PDT 24 17361654 ps
T110 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4205053302 May 14 01:34:17 PM PDT 24 May 14 01:34:24 PM PDT 24 625460711 ps
T201 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.238313031 May 14 01:34:34 PM PDT 24 May 14 01:34:45 PM PDT 24 4295727258 ps
T195 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1353046026 May 14 01:34:10 PM PDT 24 May 14 01:34:12 PM PDT 24 152723514 ps
T873 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1110399725 May 14 01:34:40 PM PDT 24 May 14 01:34:42 PM PDT 24 261229928 ps
T874 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4070068588 May 14 01:34:42 PM PDT 24 May 14 01:34:46 PM PDT 24 57720180 ps
T104 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2975360919 May 14 01:34:44 PM PDT 24 May 14 01:34:48 PM PDT 24 292293588 ps
T105 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.591398272 May 14 01:34:34 PM PDT 24 May 14 01:34:37 PM PDT 24 78521288 ps
T875 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2451721973 May 14 01:33:51 PM PDT 24 May 14 01:34:06 PM PDT 24 1082184317 ps
T182 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.275507873 May 14 01:34:11 PM PDT 24 May 14 01:34:13 PM PDT 24 59424837 ps
T876 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1587193098 May 14 01:34:43 PM PDT 24 May 14 01:35:09 PM PDT 24 2011444174 ps
T183 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2392709003 May 14 01:34:11 PM PDT 24 May 14 01:34:13 PM PDT 24 15484418 ps
T196 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2109054675 May 14 01:35:05 PM PDT 24 May 14 01:35:07 PM PDT 24 31185061 ps
T184 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.932367669 May 14 01:35:05 PM PDT 24 May 14 01:35:07 PM PDT 24 33415021 ps
T148 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2601934792 May 14 01:34:48 PM PDT 24 May 14 01:34:51 PM PDT 24 30884590 ps
T877 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2415826702 May 14 01:34:50 PM PDT 24 May 14 01:34:52 PM PDT 24 29931771 ps
T197 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2653280369 May 14 01:34:42 PM PDT 24 May 14 01:34:45 PM PDT 24 16194220 ps
T198 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3504500912 May 14 01:34:19 PM PDT 24 May 14 01:34:21 PM PDT 24 49767735 ps
T878 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3449556533 May 14 01:34:47 PM PDT 24 May 14 01:34:50 PM PDT 24 45880021 ps
T199 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2559565321 May 14 01:34:48 PM PDT 24 May 14 01:34:51 PM PDT 24 25213856 ps
T127 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.4202455711 May 14 01:35:09 PM PDT 24 May 14 01:35:13 PM PDT 24 121491113 ps
T116 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2185299608 May 14 01:34:48 PM PDT 24 May 14 01:34:54 PM PDT 24 159326484 ps
T879 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3079762709 May 14 01:34:34 PM PDT 24 May 14 01:34:37 PM PDT 24 55461988 ps
T880 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.269316136 May 14 01:34:55 PM PDT 24 May 14 01:34:57 PM PDT 24 57117124 ps
T881 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.936308117 May 14 01:33:59 PM PDT 24 May 14 01:34:02 PM PDT 24 239793143 ps
T114 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.931904135 May 14 01:34:49 PM PDT 24 May 14 01:34:54 PM PDT 24 78769371 ps
T121 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1346466286 May 14 01:33:57 PM PDT 24 May 14 01:33:59 PM PDT 24 30675038 ps
T882 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2684060884 May 14 01:35:04 PM PDT 24 May 14 01:35:08 PM PDT 24 96225617 ps
T883 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3549605767 May 14 01:34:34 PM PDT 24 May 14 01:34:37 PM PDT 24 207842600 ps
T884 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1498688920 May 14 01:35:02 PM PDT 24 May 14 01:35:04 PM PDT 24 92109330 ps
T885 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1244393546 May 14 01:34:50 PM PDT 24 May 14 01:34:53 PM PDT 24 20969623 ps
T886 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3808314395 May 14 01:34:42 PM PDT 24 May 14 01:34:46 PM PDT 24 47110409 ps
T887 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2300449835 May 14 01:35:09 PM PDT 24 May 14 01:35:11 PM PDT 24 54602114 ps
T888 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2727811419 May 14 01:34:50 PM PDT 24 May 14 01:35:13 PM PDT 24 2002438792 ps
T889 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1006018384 May 14 01:34:27 PM PDT 24 May 14 01:34:31 PM PDT 24 290698442 ps
T890 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2504741144 May 14 01:34:28 PM PDT 24 May 14 01:34:30 PM PDT 24 43600701 ps
T891 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3618740318 May 14 01:34:35 PM PDT 24 May 14 01:34:40 PM PDT 24 723142658 ps
T126 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2302281452 May 14 01:34:26 PM PDT 24 May 14 01:34:30 PM PDT 24 312043785 ps
T892 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3015544715 May 14 01:35:12 PM PDT 24 May 14 01:35:14 PM PDT 24 50656369 ps
T893 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1341148377 May 14 01:34:48 PM PDT 24 May 14 01:34:50 PM PDT 24 27077640 ps
T894 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2927366000 May 14 01:34:24 PM PDT 24 May 14 01:34:26 PM PDT 24 19242016 ps
T895 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1807631749 May 14 01:33:56 PM PDT 24 May 14 01:34:10 PM PDT 24 14781593642 ps
T896 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3000032665 May 14 01:34:35 PM PDT 24 May 14 01:34:40 PM PDT 24 961849704 ps
T897 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3289282712 May 14 01:34:28 PM PDT 24 May 14 01:34:30 PM PDT 24 23611832 ps
T898 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1023274364 May 14 01:33:53 PM PDT 24 May 14 01:33:55 PM PDT 24 84754567 ps
T899 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3970963173 May 14 01:34:36 PM PDT 24 May 14 01:34:39 PM PDT 24 21630242 ps
T900 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.43747209 May 14 01:34:18 PM PDT 24 May 14 01:34:20 PM PDT 24 227694221 ps
T901 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.760487517 May 14 01:34:38 PM PDT 24 May 14 01:34:40 PM PDT 24 15731674 ps
T902 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.476528303 May 14 01:34:41 PM PDT 24 May 14 01:34:45 PM PDT 24 42514567 ps
T903 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3684584047 May 14 01:34:21 PM PDT 24 May 14 01:34:23 PM PDT 24 312708994 ps
T904 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2424255182 May 14 01:34:34 PM PDT 24 May 14 01:34:36 PM PDT 24 344941882 ps
T905 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1605655137 May 14 01:34:11 PM PDT 24 May 14 01:34:21 PM PDT 24 2826178391 ps
T906 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2661521909 May 14 01:34:41 PM PDT 24 May 14 01:34:45 PM PDT 24 302286677 ps
T907 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1160644690 May 14 01:34:04 PM PDT 24 May 14 01:34:11 PM PDT 24 541733675 ps
T185 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.998188414 May 14 01:33:58 PM PDT 24 May 14 01:34:00 PM PDT 24 26784233 ps
T908 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3145797761 May 14 01:33:54 PM PDT 24 May 14 01:34:01 PM PDT 24 569102167 ps
T909 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1769972321 May 14 01:34:04 PM PDT 24 May 14 01:34:07 PM PDT 24 72082599 ps
T910 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2349238487 May 14 01:34:27 PM PDT 24 May 14 01:34:31 PM PDT 24 70061021 ps
T911 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2629752030 May 14 01:34:50 PM PDT 24 May 14 01:34:54 PM PDT 24 412936810 ps
T186 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4203296098 May 14 01:34:37 PM PDT 24 May 14 01:34:40 PM PDT 24 169304089 ps
T912 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2154155229 May 14 01:34:05 PM PDT 24 May 14 01:34:07 PM PDT 24 108193274 ps
T130 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1147176781 May 14 01:34:34 PM PDT 24 May 14 01:34:37 PM PDT 24 35242439 ps
T913 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.4083899219 May 14 01:35:10 PM PDT 24 May 14 01:35:12 PM PDT 24 181141055 ps
T914 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3181758847 May 14 01:34:11 PM PDT 24 May 14 01:34:14 PM PDT 24 388613159 ps
T915 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2145525703 May 14 01:34:41 PM PDT 24 May 14 01:34:43 PM PDT 24 201695539 ps
T916 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3981905288 May 14 01:33:44 PM PDT 24 May 14 01:33:47 PM PDT 24 242345971 ps
T917 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2251694067 May 14 01:34:40 PM PDT 24 May 14 01:34:42 PM PDT 24 497111434 ps
T918 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.803265569 May 14 01:35:02 PM PDT 24 May 14 01:35:04 PM PDT 24 25297262 ps
T187 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3715074886 May 14 01:34:56 PM PDT 24 May 14 01:34:58 PM PDT 24 37163222 ps
T919 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1652224479 May 14 01:34:03 PM PDT 24 May 14 01:34:05 PM PDT 24 16371652 ps
T920 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2275858237 May 14 01:34:03 PM PDT 24 May 14 01:34:05 PM PDT 24 18049615 ps
T921 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.510165712 May 14 01:34:25 PM PDT 24 May 14 01:34:29 PM PDT 24 408650713 ps
T922 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1335113889 May 14 01:34:41 PM PDT 24 May 14 01:34:44 PM PDT 24 17971173 ps
T119 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.696308323 May 14 01:33:57 PM PDT 24 May 14 01:34:00 PM PDT 24 80732071 ps
T923 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3400872637 May 14 01:34:04 PM PDT 24 May 14 01:34:07 PM PDT 24 41973318 ps
T924 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4101680806 May 14 01:34:43 PM PDT 24 May 14 01:34:45 PM PDT 24 154932993 ps
T925 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.992958782 May 14 01:34:11 PM PDT 24 May 14 01:34:14 PM PDT 24 89750803 ps
T112 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1352082261 May 14 01:34:57 PM PDT 24 May 14 01:35:00 PM PDT 24 156478223 ps
T926 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3392471519 May 14 01:34:41 PM PDT 24 May 14 01:34:44 PM PDT 24 114697143 ps
T927 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1853346288 May 14 01:34:56 PM PDT 24 May 14 01:34:58 PM PDT 24 18998252 ps
T928 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.4162958509 May 14 01:34:49 PM PDT 24 May 14 01:34:53 PM PDT 24 1543363897 ps
T123 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2262637180 May 14 01:34:09 PM PDT 24 May 14 01:34:13 PM PDT 24 89716998 ps
T929 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3811794027 May 14 01:35:02 PM PDT 24 May 14 01:35:05 PM PDT 24 43850762 ps
T930 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3322940697 May 14 01:33:58 PM PDT 24 May 14 01:34:03 PM PDT 24 82072445 ps
T931 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.482304389 May 14 01:33:51 PM PDT 24 May 14 01:33:53 PM PDT 24 612913775 ps
T932 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3523312371 May 14 01:34:48 PM PDT 24 May 14 01:34:50 PM PDT 24 75158093 ps
T933 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3219522299 May 14 01:34:41 PM PDT 24 May 14 01:34:44 PM PDT 24 105092157 ps
T934 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.680951918 May 14 01:34:40 PM PDT 24 May 14 01:34:42 PM PDT 24 98571969 ps
T113 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.803211487 May 14 01:35:10 PM PDT 24 May 14 01:35:14 PM PDT 24 635195354 ps
T935 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1994326943 May 14 01:34:28 PM PDT 24 May 14 01:34:32 PM PDT 24 130750272 ps
T936 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3683846465 May 14 01:34:51 PM PDT 24 May 14 01:34:56 PM PDT 24 117251084 ps
T188 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.626478067 May 14 01:34:11 PM PDT 24 May 14 01:34:13 PM PDT 24 26758884 ps
T937 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2926031557 May 14 01:35:10 PM PDT 24 May 14 01:35:12 PM PDT 24 30315044 ps
T938 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.168147517 May 14 01:33:52 PM PDT 24 May 14 01:33:54 PM PDT 24 28088385 ps
T939 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3805161455 May 14 01:34:17 PM PDT 24 May 14 01:34:30 PM PDT 24 1074908096 ps
T940 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3618248000 May 14 01:34:42 PM PDT 24 May 14 01:34:46 PM PDT 24 173588645 ps
T941 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.4048415976 May 14 01:34:26 PM PDT 24 May 14 01:34:41 PM PDT 24 10504851328 ps
T942 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3758035874 May 14 01:34:26 PM PDT 24 May 14 01:34:29 PM PDT 24 53944564 ps
T943 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3380088980 May 14 01:34:13 PM PDT 24 May 14 01:34:16 PM PDT 24 466687923 ps
T944 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1178102385 May 14 01:34:27 PM PDT 24 May 14 01:34:30 PM PDT 24 40602963 ps
T945 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1152191430 May 14 01:34:50 PM PDT 24 May 14 01:34:53 PM PDT 24 57528485 ps
T946 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2574452679 May 14 01:34:42 PM PDT 24 May 14 01:34:45 PM PDT 24 18589644 ps
T947 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.4003987732 May 14 01:34:42 PM PDT 24 May 14 01:34:52 PM PDT 24 1410476187 ps
T124 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4260694454 May 14 01:34:56 PM PDT 24 May 14 01:34:59 PM PDT 24 152422002 ps
T948 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3834542173 May 14 01:34:56 PM PDT 24 May 14 01:34:58 PM PDT 24 150436131 ps
T189 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.770598590 May 14 01:34:34 PM PDT 24 May 14 01:34:36 PM PDT 24 20304119 ps
T949 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.76105163 May 14 01:34:34 PM PDT 24 May 14 01:34:37 PM PDT 24 49506741 ps
T950 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2856140370 May 14 01:34:40 PM PDT 24 May 14 01:34:43 PM PDT 24 28704749 ps
T951 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3161027863 May 14 01:34:26 PM PDT 24 May 14 01:34:28 PM PDT 24 254438977 ps
T952 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3846384238 May 14 01:34:59 PM PDT 24 May 14 01:35:02 PM PDT 24 27535616 ps
T953 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3603432814 May 14 01:33:52 PM PDT 24 May 14 01:33:54 PM PDT 24 46883855 ps
T954 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1621034774 May 14 01:34:02 PM PDT 24 May 14 01:34:04 PM PDT 24 157955936 ps
T190 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1150711600 May 14 01:33:57 PM PDT 24 May 14 01:33:59 PM PDT 24 15457373 ps
T955 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1177925646 May 14 01:34:10 PM PDT 24 May 14 01:34:13 PM PDT 24 229701674 ps
T956 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2269555036 May 14 01:34:43 PM PDT 24 May 14 01:34:46 PM PDT 24 18167451 ps
T957 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.4078942523 May 14 01:34:26 PM PDT 24 May 14 01:34:29 PM PDT 24 16507674 ps
T958 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1496353768 May 14 01:34:26 PM PDT 24 May 14 01:34:48 PM PDT 24 3115835818 ps
T959 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3354220531 May 14 01:34:56 PM PDT 24 May 14 01:35:00 PM PDT 24 53219491 ps
T960 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1279205416 May 14 01:34:19 PM PDT 24 May 14 01:34:21 PM PDT 24 52378716 ps
T129 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3117622614 May 14 01:34:56 PM PDT 24 May 14 01:34:59 PM PDT 24 598135687 ps
T961 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.710656805 May 14 01:34:43 PM PDT 24 May 14 01:34:48 PM PDT 24 507857050 ps
T962 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.181779728 May 14 01:34:49 PM PDT 24 May 14 01:34:54 PM PDT 24 105957004 ps
T963 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4100333637 May 14 01:34:02 PM PDT 24 May 14 01:34:04 PM PDT 24 22157425 ps
T964 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.4099736989 May 14 01:34:25 PM PDT 24 May 14 01:34:29 PM PDT 24 94609387 ps
T965 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1110449153 May 14 01:34:35 PM PDT 24 May 14 01:34:51 PM PDT 24 2147473433 ps
T966 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1458480543 May 14 01:34:27 PM PDT 24 May 14 01:34:30 PM PDT 24 17333485 ps
T191 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4079938840 May 14 01:34:49 PM PDT 24 May 14 01:34:51 PM PDT 24 18648220 ps
T967 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.753555849 May 14 01:34:55 PM PDT 24 May 14 01:34:57 PM PDT 24 150783763 ps
T968 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1921773778 May 14 01:34:11 PM PDT 24 May 14 01:34:21 PM PDT 24 361852645 ps
T969 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3837268038 May 14 01:35:05 PM PDT 24 May 14 01:35:07 PM PDT 24 40888710 ps
T970 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3383334242 May 14 01:34:41 PM PDT 24 May 14 01:34:45 PM PDT 24 523357375 ps
T194 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.640899318 May 14 01:34:26 PM PDT 24 May 14 01:34:29 PM PDT 24 19777482 ps
T971 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2915289104 May 14 01:34:57 PM PDT 24 May 14 01:34:59 PM PDT 24 100861128 ps
T972 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1161578335 May 14 01:34:56 PM PDT 24 May 14 01:35:00 PM PDT 24 642405926 ps
T973 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3790154961 May 14 01:34:56 PM PDT 24 May 14 01:35:00 PM PDT 24 251605491 ps
T974 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1464900063 May 14 01:34:43 PM PDT 24 May 14 01:35:01 PM PDT 24 2914606137 ps
T975 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2809367354 May 14 01:35:10 PM PDT 24 May 14 01:35:13 PM PDT 24 16363360 ps
T976 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.993183206 May 14 01:34:42 PM PDT 24 May 14 01:34:45 PM PDT 24 29157169 ps
T977 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.989098772 May 14 01:35:10 PM PDT 24 May 14 01:35:13 PM PDT 24 88298369 ps
T978 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1767339434 May 14 01:35:08 PM PDT 24 May 14 01:35:10 PM PDT 24 12776276 ps
T979 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2734866747 May 14 01:34:41 PM PDT 24 May 14 01:34:44 PM PDT 24 186752957 ps
T115 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3519358675 May 14 01:34:02 PM PDT 24 May 14 01:34:06 PM PDT 24 150755837 ps
T120 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.844222632 May 14 01:34:44 PM PDT 24 May 14 01:34:47 PM PDT 24 240847608 ps
T980 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3428267621 May 14 01:34:41 PM PDT 24 May 14 01:34:54 PM PDT 24 430601366 ps
T981 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3851300876 May 14 01:34:11 PM PDT 24 May 14 01:34:13 PM PDT 24 21139458 ps
T982 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.450511380 May 14 01:34:35 PM PDT 24 May 14 01:34:39 PM PDT 24 87155837 ps
T983 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1097516275 May 14 01:34:46 PM PDT 24 May 14 01:34:48 PM PDT 24 259373042 ps
T984 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.361430650 May 14 01:34:49 PM PDT 24 May 14 01:34:51 PM PDT 24 15648041 ps
T192 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3472457693 May 14 01:34:03 PM PDT 24 May 14 01:34:05 PM PDT 24 15612004 ps
T985 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4156501259 May 14 01:34:18 PM PDT 24 May 14 01:34:22 PM PDT 24 2253580477 ps
T986 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.823015507 May 14 01:34:49 PM PDT 24 May 14 01:35:02 PM PDT 24 494200226 ps
T987 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1797685766 May 14 01:33:57 PM PDT 24 May 14 01:34:05 PM PDT 24 1082075993 ps
T125 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1238936291 May 14 01:34:49 PM PDT 24 May 14 01:34:53 PM PDT 24 122614174 ps
T988 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1477340563 May 14 01:34:27 PM PDT 24 May 14 01:34:30 PM PDT 24 34811608 ps
T118 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1763379456 May 14 01:35:04 PM PDT 24 May 14 01:35:08 PM PDT 24 62452587 ps
T989 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2777874890 May 14 01:34:55 PM PDT 24 May 14 01:34:56 PM PDT 24 14019974 ps
T990 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.810190953 May 14 01:34:42 PM PDT 24 May 14 01:34:45 PM PDT 24 15443764 ps
T991 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3918246744 May 14 01:34:50 PM PDT 24 May 14 01:34:53 PM PDT 24 25227287 ps
T992 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3223585163 May 14 01:34:34 PM PDT 24 May 14 01:34:37 PM PDT 24 36534826 ps
T128 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2290443845 May 14 01:34:25 PM PDT 24 May 14 01:34:29 PM PDT 24 109822284 ps
T993 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.382511583 May 14 01:34:34 PM PDT 24 May 14 01:34:36 PM PDT 24 12681775 ps
T994 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3923720037 May 14 01:33:57 PM PDT 24 May 14 01:33:59 PM PDT 24 19207574 ps
T193 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1468069502 May 14 01:34:25 PM PDT 24 May 14 01:34:28 PM PDT 24 71013593 ps
T122 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1412775162 May 14 01:34:51 PM PDT 24 May 14 01:34:55 PM PDT 24 117821419 ps
T995 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1020761190 May 14 01:34:43 PM PDT 24 May 14 01:34:48 PM PDT 24 468833161 ps
T996 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.704869355 May 14 01:34:33 PM PDT 24 May 14 01:34:47 PM PDT 24 570273837 ps
T997 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3246248640 May 14 01:33:56 PM PDT 24 May 14 01:33:58 PM PDT 24 56305209 ps
T117 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2575342123 May 14 01:34:33 PM PDT 24 May 14 01:34:37 PM PDT 24 65378988 ps
T998 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2546058482 May 14 01:34:55 PM PDT 24 May 14 01:34:57 PM PDT 24 121814771 ps
T999 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3611610691 May 14 01:33:58 PM PDT 24 May 14 01:34:00 PM PDT 24 91186260 ps
T1000 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1952807014 May 14 01:34:40 PM PDT 24 May 14 01:34:42 PM PDT 24 25808439 ps

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.291048453
Short name T15
Test name
Test status
Simulation time 854325562 ps
CPU time 9.37 seconds
Started May 14 01:37:38 PM PDT 24
Finished May 14 01:37:48 PM PDT 24
Peak memory 218296 kb
Host smart-5af5254d-1bb5-4b38-8106-0cb14713f78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291048453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.291048453
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.1854823372
Short name T21
Test name
Test status
Simulation time 88982258323 ps
CPU time 452.36 seconds
Started May 14 01:38:14 PM PDT 24
Finished May 14 01:45:47 PM PDT 24
Peak memory 349528 kb
Host smart-6fc5f692-d915-4740-8819-8b4e7e0937ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1854823372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.1854823372
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.4154394185
Short name T3
Test name
Test status
Simulation time 380669903 ps
CPU time 14.59 seconds
Started May 14 01:38:22 PM PDT 24
Finished May 14 01:38:38 PM PDT 24
Peak memory 225696 kb
Host smart-53b2b131-1687-4538-839b-cec0ff2a2f20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154394185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.4154394185
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.762204454
Short name T213
Test name
Test status
Simulation time 346588669 ps
CPU time 12.99 seconds
Started May 14 01:39:15 PM PDT 24
Finished May 14 01:39:29 PM PDT 24
Peak memory 218188 kb
Host smart-057998d3-c7d6-4e27-8539-e44f2f5dd952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762204454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.762204454
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.2294071937
Short name T36
Test name
Test status
Simulation time 172681334837 ps
CPU time 1433.58 seconds
Started May 14 01:37:54 PM PDT 24
Finished May 14 02:01:49 PM PDT 24
Peak memory 283984 kb
Host smart-2533edc1-a499-4463-9c8d-b9cea890fff5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2294071937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.2294071937
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3385299130
Short name T14
Test name
Test status
Simulation time 491691985 ps
CPU time 12.22 seconds
Started May 14 01:37:08 PM PDT 24
Finished May 14 01:37:21 PM PDT 24
Peak memory 218052 kb
Host smart-d09d14ed-b7d5-43b3-a590-e69375b333c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385299130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
385299130
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.3739245104
Short name T158
Test name
Test status
Simulation time 126005137837 ps
CPU time 1035.57 seconds
Started May 14 01:38:35 PM PDT 24
Finished May 14 01:55:51 PM PDT 24
Peak memory 422252 kb
Host smart-51b2cf80-a80b-4c77-aa77-ba33c9a8b3fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3739245104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.3739245104
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1890705271
Short name T46
Test name
Test status
Simulation time 4159165295 ps
CPU time 34.91 seconds
Started May 14 01:36:42 PM PDT 24
Finished May 14 01:37:19 PM PDT 24
Peak memory 268752 kb
Host smart-20cf8a5f-5dc8-448a-9b3a-3e803003c50c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890705271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1890705271
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1609672572
Short name T103
Test name
Test status
Simulation time 58998573 ps
CPU time 2.4 seconds
Started May 14 01:34:42 PM PDT 24
Finished May 14 01:34:46 PM PDT 24
Peak memory 221868 kb
Host smart-6e2ec591-51c5-447c-94f1-6829fe41ba4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609672572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.1609672572
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1652941760
Short name T9
Test name
Test status
Simulation time 1019570728 ps
CPU time 4.18 seconds
Started May 14 01:38:58 PM PDT 24
Finished May 14 01:39:03 PM PDT 24
Peak memory 209716 kb
Host smart-aa3b42b7-6873-4fcc-b5ed-2c65bc3d7648
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652941760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1652941760
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.671740145
Short name T106
Test name
Test status
Simulation time 346198757 ps
CPU time 3.23 seconds
Started May 14 01:34:40 PM PDT 24
Finished May 14 01:34:44 PM PDT 24
Peak memory 221036 kb
Host smart-8948f7bf-e16c-4971-8f89-0eeff03f185d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671740
145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.671740145
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.4017406697
Short name T11
Test name
Test status
Simulation time 52775106 ps
CPU time 0.88 seconds
Started May 14 01:37:30 PM PDT 24
Finished May 14 01:37:32 PM PDT 24
Peak memory 209728 kb
Host smart-f01bddfe-6551-4d10-a9b8-11a2c587b9a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017406697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.4017406697
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.932367669
Short name T184
Test name
Test status
Simulation time 33415021 ps
CPU time 0.86 seconds
Started May 14 01:35:05 PM PDT 24
Finished May 14 01:35:07 PM PDT 24
Peak memory 208936 kb
Host smart-2dec4298-9fa3-4998-8c84-d2b22d42e5bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932367669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.932367669
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.376136638
Short name T109
Test name
Test status
Simulation time 588071330 ps
CPU time 3.05 seconds
Started May 14 01:33:52 PM PDT 24
Finished May 14 01:33:56 PM PDT 24
Peak memory 217556 kb
Host smart-25db968e-5b34-4fbf-9dbf-4d4ac66280e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376136638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.376136638
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.931904135
Short name T114
Test name
Test status
Simulation time 78769371 ps
CPU time 3.69 seconds
Started May 14 01:34:49 PM PDT 24
Finished May 14 01:34:54 PM PDT 24
Peak memory 217432 kb
Host smart-ac7b4a30-3e09-4920-b693-a1fec59028b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931904135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.931904135
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.567833688
Short name T18
Test name
Test status
Simulation time 1640363346 ps
CPU time 48.28 seconds
Started May 14 01:39:25 PM PDT 24
Finished May 14 01:40:14 PM PDT 24
Peak memory 254568 kb
Host smart-55418435-c891-4ea3-a56e-771f03a6aa31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567833688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.567833688
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1763379456
Short name T118
Test name
Test status
Simulation time 62452587 ps
CPU time 2.05 seconds
Started May 14 01:35:04 PM PDT 24
Finished May 14 01:35:08 PM PDT 24
Peak memory 221900 kb
Host smart-d39d8de9-d85e-4191-97d0-66a1ea73f72b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763379456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1763379456
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1599836686
Short name T19
Test name
Test status
Simulation time 9426381401 ps
CPU time 66.88 seconds
Started May 14 01:37:22 PM PDT 24
Finished May 14 01:38:30 PM PDT 24
Peak memory 219132 kb
Host smart-e508a1cc-aeee-4c0a-9198-2c62227c4f86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599836686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1599836686
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2185299608
Short name T116
Test name
Test status
Simulation time 159326484 ps
CPU time 5 seconds
Started May 14 01:34:48 PM PDT 24
Finished May 14 01:34:54 PM PDT 24
Peak memory 217372 kb
Host smart-4b9ab8a6-5530-4206-a006-ff50497dd5a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185299608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.2185299608
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1352082261
Short name T112
Test name
Test status
Simulation time 156478223 ps
CPU time 2.18 seconds
Started May 14 01:34:57 PM PDT 24
Finished May 14 01:35:00 PM PDT 24
Peak memory 221700 kb
Host smart-4ff2b72a-922a-47b3-9d1a-8ca695136d9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352082261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1352082261
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2975360919
Short name T104
Test name
Test status
Simulation time 292293588 ps
CPU time 2.82 seconds
Started May 14 01:34:44 PM PDT 24
Finished May 14 01:34:48 PM PDT 24
Peak memory 221856 kb
Host smart-bee994b1-72a9-403a-8c00-8dde6d381976
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975360919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.2975360919
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.625292602
Short name T6
Test name
Test status
Simulation time 1232005584 ps
CPU time 3.84 seconds
Started May 14 01:37:54 PM PDT 24
Finished May 14 01:37:59 PM PDT 24
Peak memory 213452 kb
Host smart-55873bb6-abaa-44ef-b2ea-4347be7b105a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625292602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
625292602
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.1545114313
Short name T82
Test name
Test status
Simulation time 39254272 ps
CPU time 1 seconds
Started May 14 01:40:35 PM PDT 24
Finished May 14 01:40:37 PM PDT 24
Peak memory 212844 kb
Host smart-318ab282-d358-4910-8282-d133e8af8520
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545114313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.1545114313
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1412775162
Short name T122
Test name
Test status
Simulation time 117821419 ps
CPU time 3.41 seconds
Started May 14 01:34:51 PM PDT 24
Finished May 14 01:34:55 PM PDT 24
Peak memory 222040 kb
Host smart-0395110a-2ea7-41ad-a4ce-8dbafe20712c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412775162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1412775162
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.803211487
Short name T113
Test name
Test status
Simulation time 635195354 ps
CPU time 3.57 seconds
Started May 14 01:35:10 PM PDT 24
Finished May 14 01:35:14 PM PDT 24
Peak memory 217356 kb
Host smart-5d54d1d6-1918-41f9-9cf6-9474a09a0a8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803211487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg_
err.803211487
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2980183053
Short name T207
Test name
Test status
Simulation time 48222077 ps
CPU time 0.82 seconds
Started May 14 01:36:33 PM PDT 24
Finished May 14 01:36:37 PM PDT 24
Peak memory 209424 kb
Host smart-4152eb74-9778-4417-872e-1157135733e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980183053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2980183053
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1963504078
Short name T205
Test name
Test status
Simulation time 28179567 ps
CPU time 0.82 seconds
Started May 14 01:36:31 PM PDT 24
Finished May 14 01:36:32 PM PDT 24
Peak memory 209528 kb
Host smart-b72e7338-73f8-4d47-8987-9a7b5b7f2ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963504078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1963504078
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1639717578
Short name T208
Test name
Test status
Simulation time 16857418 ps
CPU time 0.9 seconds
Started May 14 01:36:46 PM PDT 24
Finished May 14 01:36:48 PM PDT 24
Peak memory 209700 kb
Host smart-f39369b6-6be9-4373-b740-6c2ee2c20fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639717578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1639717578
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2751680615
Short name T210
Test name
Test status
Simulation time 13179194 ps
CPU time 0.85 seconds
Started May 14 01:37:29 PM PDT 24
Finished May 14 01:37:31 PM PDT 24
Peak memory 209544 kb
Host smart-164788b1-492b-4040-baae-1bd9e61bcfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751680615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2751680615
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.696308323
Short name T119
Test name
Test status
Simulation time 80732071 ps
CPU time 2.36 seconds
Started May 14 01:33:57 PM PDT 24
Finished May 14 01:34:00 PM PDT 24
Peak memory 221744 kb
Host smart-bd535257-ddd0-4924-a0cb-55c6e0ec287b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696308323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.696308323
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1160644690
Short name T907
Test name
Test status
Simulation time 541733675 ps
CPU time 5.31 seconds
Started May 14 01:34:04 PM PDT 24
Finished May 14 01:34:11 PM PDT 24
Peak memory 217440 kb
Host smart-86e21676-4cc5-4acd-a4a1-62379d871eaa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160644690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1160644690
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.4202455711
Short name T127
Test name
Test status
Simulation time 121491113 ps
CPU time 2.71 seconds
Started May 14 01:35:09 PM PDT 24
Finished May 14 01:35:13 PM PDT 24
Peak memory 217376 kb
Host smart-13e90539-a15d-4ce4-a128-bbc916cfcced
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202455711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.4202455711
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2262637180
Short name T123
Test name
Test status
Simulation time 89716998 ps
CPU time 3.62 seconds
Started May 14 01:34:09 PM PDT 24
Finished May 14 01:34:13 PM PDT 24
Peak memory 217384 kb
Host smart-3cbcd42e-9d9c-43b6-8ba5-e4a6c05dddc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262637180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2262637180
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2302281452
Short name T126
Test name
Test status
Simulation time 312043785 ps
CPU time 2.74 seconds
Started May 14 01:34:26 PM PDT 24
Finished May 14 01:34:30 PM PDT 24
Peak memory 221532 kb
Host smart-fef5acaa-bd82-4615-a39f-3db28b7fd7f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302281452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2302281452
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.591398272
Short name T105
Test name
Test status
Simulation time 78521288 ps
CPU time 2.42 seconds
Started May 14 01:34:34 PM PDT 24
Finished May 14 01:34:37 PM PDT 24
Peak memory 221704 kb
Host smart-0ec43795-98d2-4213-9fdf-a29e2a5723a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591398272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e
rr.591398272
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2439248348
Short name T42
Test name
Test status
Simulation time 4723610663 ps
CPU time 79.11 seconds
Started May 14 01:36:39 PM PDT 24
Finished May 14 01:37:59 PM PDT 24
Peak memory 268412 kb
Host smart-7a2fba08-8d7c-4c09-b20e-77bf1efff0a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439248348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2439248348
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.2786266335
Short name T24
Test name
Test status
Simulation time 23173551852 ps
CPU time 47.98 seconds
Started May 14 01:38:11 PM PDT 24
Finished May 14 01:39:00 PM PDT 24
Peak memory 270936 kb
Host smart-f072bb8f-aa97-4bd7-b641-e4601592058e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786266335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.2786266335
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2507993115
Short name T144
Test name
Test status
Simulation time 327823717 ps
CPU time 32.58 seconds
Started May 14 01:39:23 PM PDT 24
Finished May 14 01:39:57 PM PDT 24
Peak memory 251052 kb
Host smart-712fa0d1-6893-4262-9961-4c2bb00e75b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507993115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2507993115
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.998188414
Short name T185
Test name
Test status
Simulation time 26784233 ps
CPU time 1.18 seconds
Started May 14 01:33:58 PM PDT 24
Finished May 14 01:34:00 PM PDT 24
Peak memory 209236 kb
Host smart-eace58cd-3335-4a90-8632-43c4c405eb89
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998188414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.998188414
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3322940697
Short name T930
Test name
Test status
Simulation time 82072445 ps
CPU time 3.03 seconds
Started May 14 01:33:58 PM PDT 24
Finished May 14 01:34:03 PM PDT 24
Peak memory 207796 kb
Host smart-5f6e8734-6b1e-4f88-9acd-2c677ae31d9f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322940697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3322940697
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1150711600
Short name T190
Test name
Test status
Simulation time 15457373 ps
CPU time 1.2 seconds
Started May 14 01:33:57 PM PDT 24
Finished May 14 01:33:59 PM PDT 24
Peak memory 217916 kb
Host smart-5f81d761-183f-4e16-9217-c71cbf9b2648
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150711600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1150711600
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1346466286
Short name T121
Test name
Test status
Simulation time 30675038 ps
CPU time 1.38 seconds
Started May 14 01:33:57 PM PDT 24
Finished May 14 01:33:59 PM PDT 24
Peak memory 217444 kb
Host smart-414bb431-cf2d-4cfb-9733-9ffeee470ec2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346466286 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1346466286
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3923720037
Short name T994
Test name
Test status
Simulation time 19207574 ps
CPU time 0.83 seconds
Started May 14 01:33:57 PM PDT 24
Finished May 14 01:33:59 PM PDT 24
Peak memory 208456 kb
Host smart-4d628244-7b41-40a5-bda9-79833fb5d08d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923720037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3923720037
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.482304389
Short name T931
Test name
Test status
Simulation time 612913775 ps
CPU time 1.08 seconds
Started May 14 01:33:51 PM PDT 24
Finished May 14 01:33:53 PM PDT 24
Peak memory 208948 kb
Host smart-9fd2397a-1ad7-45b5-913a-d48895d0799b
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482304389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 0.lc_ctrl_jtag_alert_test.482304389
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3145797761
Short name T908
Test name
Test status
Simulation time 569102167 ps
CPU time 5.79 seconds
Started May 14 01:33:54 PM PDT 24
Finished May 14 01:34:01 PM PDT 24
Peak memory 208760 kb
Host smart-93190c42-b949-45f0-95a4-4f9bc0b4684a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145797761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3145797761
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2451721973
Short name T875
Test name
Test status
Simulation time 1082184317 ps
CPU time 13.63 seconds
Started May 14 01:33:51 PM PDT 24
Finished May 14 01:34:06 PM PDT 24
Peak memory 209036 kb
Host smart-82378ebc-0aa7-4f05-be08-e0c9ec34ac60
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451721973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2451721973
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3981905288
Short name T916
Test name
Test status
Simulation time 242345971 ps
CPU time 1.68 seconds
Started May 14 01:33:44 PM PDT 24
Finished May 14 01:33:47 PM PDT 24
Peak memory 210460 kb
Host smart-4193d93b-6639-4f9d-8ca0-c60f099b38e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981905288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3981905288
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1023274364
Short name T898
Test name
Test status
Simulation time 84754567 ps
CPU time 1.62 seconds
Started May 14 01:33:53 PM PDT 24
Finished May 14 01:33:55 PM PDT 24
Peak memory 217420 kb
Host smart-b2a9c0f0-43b1-418e-b0a9-3660c5e0bc66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102327
4364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1023274364
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3603432814
Short name T953
Test name
Test status
Simulation time 46883855 ps
CPU time 1.77 seconds
Started May 14 01:33:52 PM PDT 24
Finished May 14 01:33:54 PM PDT 24
Peak memory 209012 kb
Host smart-9d5c6291-9103-460f-a5b3-ac94c6bdde03
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603432814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3603432814
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.168147517
Short name T938
Test name
Test status
Simulation time 28088385 ps
CPU time 1.44 seconds
Started May 14 01:33:52 PM PDT 24
Finished May 14 01:33:54 PM PDT 24
Peak memory 209220 kb
Host smart-05344f58-ccb2-43db-889d-0251a6656c30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168147517 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.168147517
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3246248640
Short name T997
Test name
Test status
Simulation time 56305209 ps
CPU time 1.17 seconds
Started May 14 01:33:56 PM PDT 24
Finished May 14 01:33:58 PM PDT 24
Peak memory 209232 kb
Host smart-bb66178d-7b4c-430b-9f8a-7cd4f7b8668d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246248640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3246248640
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.4100333637
Short name T963
Test name
Test status
Simulation time 22157425 ps
CPU time 1.06 seconds
Started May 14 01:34:02 PM PDT 24
Finished May 14 01:34:04 PM PDT 24
Peak memory 208444 kb
Host smart-2072ac99-bb6f-4068-a614-62c4b7336224
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100333637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.4100333637
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.203911777
Short name T871
Test name
Test status
Simulation time 63996207 ps
CPU time 1.29 seconds
Started May 14 01:34:04 PM PDT 24
Finished May 14 01:34:07 PM PDT 24
Peak memory 208200 kb
Host smart-5f2e1164-a53d-44e8-ae46-9c1fb1e37e1b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203911777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.203911777
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.3472457693
Short name T192
Test name
Test status
Simulation time 15612004 ps
CPU time 0.99 seconds
Started May 14 01:34:03 PM PDT 24
Finished May 14 01:34:05 PM PDT 24
Peak memory 209708 kb
Host smart-0f549698-824b-4848-996b-e8c5566e864c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472457693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.3472457693
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2275858237
Short name T920
Test name
Test status
Simulation time 18049615 ps
CPU time 1.29 seconds
Started May 14 01:34:03 PM PDT 24
Finished May 14 01:34:05 PM PDT 24
Peak memory 217436 kb
Host smart-9f62b040-82ee-4e76-9e09-6a6da9e85f32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2275858237 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2275858237
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1652224479
Short name T919
Test name
Test status
Simulation time 16371652 ps
CPU time 0.91 seconds
Started May 14 01:34:03 PM PDT 24
Finished May 14 01:34:05 PM PDT 24
Peak memory 209100 kb
Host smart-0ab8739c-58d7-4a18-acbb-c4b8c949199c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652224479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1652224479
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3400872637
Short name T923
Test name
Test status
Simulation time 41973318 ps
CPU time 1.75 seconds
Started May 14 01:34:04 PM PDT 24
Finished May 14 01:34:07 PM PDT 24
Peak memory 209016 kb
Host smart-91281a9e-4b14-44cd-8b0a-5282fb9896a9
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400872637 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.3400872637
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1797685766
Short name T987
Test name
Test status
Simulation time 1082075993 ps
CPU time 7 seconds
Started May 14 01:33:57 PM PDT 24
Finished May 14 01:34:05 PM PDT 24
Peak memory 208848 kb
Host smart-8a30e9f6-fd2a-439c-97ae-22976486ff55
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797685766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.1797685766
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1807631749
Short name T895
Test name
Test status
Simulation time 14781593642 ps
CPU time 13.29 seconds
Started May 14 01:33:56 PM PDT 24
Finished May 14 01:34:10 PM PDT 24
Peak memory 209072 kb
Host smart-30e1107f-9d63-47b2-b4d9-67ed20c287b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807631749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1807631749
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.936308117
Short name T881
Test name
Test status
Simulation time 239793143 ps
CPU time 2.03 seconds
Started May 14 01:33:59 PM PDT 24
Finished May 14 01:34:02 PM PDT 24
Peak memory 210488 kb
Host smart-9914b28e-fa61-45e1-9f45-ba4e76442108
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936308117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.936308117
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1769972321
Short name T909
Test name
Test status
Simulation time 72082599 ps
CPU time 1.63 seconds
Started May 14 01:34:04 PM PDT 24
Finished May 14 01:34:07 PM PDT 24
Peak memory 217760 kb
Host smart-12df4584-63bc-4cf7-9646-41f1cd5b3d3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176997
2321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1769972321
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3611610691
Short name T999
Test name
Test status
Simulation time 91186260 ps
CPU time 1.56 seconds
Started May 14 01:33:58 PM PDT 24
Finished May 14 01:34:00 PM PDT 24
Peak memory 209072 kb
Host smart-102166bb-007e-44b6-914e-236cca32de5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611610691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3611610691
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1043173289
Short name T108
Test name
Test status
Simulation time 49282105 ps
CPU time 2.17 seconds
Started May 14 01:34:04 PM PDT 24
Finished May 14 01:34:07 PM PDT 24
Peak memory 211104 kb
Host smart-8e26cd5e-42cf-4919-8252-f779b6e6b1e3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043173289 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1043173289
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2154155229
Short name T912
Test name
Test status
Simulation time 108193274 ps
CPU time 1.12 seconds
Started May 14 01:34:05 PM PDT 24
Finished May 14 01:34:07 PM PDT 24
Peak memory 209172 kb
Host smart-1f7169bc-65ea-42b7-ad15-5e754dd50112
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154155229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2154155229
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3519358675
Short name T115
Test name
Test status
Simulation time 150755837 ps
CPU time 3.55 seconds
Started May 14 01:34:02 PM PDT 24
Finished May 14 01:34:06 PM PDT 24
Peak memory 221884 kb
Host smart-6b8517e9-55e7-4e0c-8e6c-0414bc033200
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519358675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3519358675
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3449556533
Short name T878
Test name
Test status
Simulation time 45880021 ps
CPU time 1.7 seconds
Started May 14 01:34:47 PM PDT 24
Finished May 14 01:34:50 PM PDT 24
Peak memory 217484 kb
Host smart-8d7b24c7-afec-431b-b553-f0a4eef867e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449556533 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3449556533
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2415826702
Short name T877
Test name
Test status
Simulation time 29931771 ps
CPU time 0.97 seconds
Started May 14 01:34:50 PM PDT 24
Finished May 14 01:34:52 PM PDT 24
Peak memory 209196 kb
Host smart-721cd0ec-83e3-4f64-842c-6fcb6438aead
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415826702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2415826702
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.236463580
Short name T147
Test name
Test status
Simulation time 84415778 ps
CPU time 1.42 seconds
Started May 14 01:34:50 PM PDT 24
Finished May 14 01:34:52 PM PDT 24
Peak memory 211184 kb
Host smart-82fe28af-b861-4d2c-af96-161b9524866a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236463580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.236463580
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.4162958509
Short name T928
Test name
Test status
Simulation time 1543363897 ps
CPU time 3 seconds
Started May 14 01:34:49 PM PDT 24
Finished May 14 01:34:53 PM PDT 24
Peak memory 217700 kb
Host smart-19d2f061-582a-40e7-a826-7c27e0a2d36b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162958509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.4162958509
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3523312371
Short name T932
Test name
Test status
Simulation time 75158093 ps
CPU time 1.51 seconds
Started May 14 01:34:48 PM PDT 24
Finished May 14 01:34:50 PM PDT 24
Peak memory 217576 kb
Host smart-1eec19ae-295d-42cf-851d-e2387541dae6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523312371 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3523312371
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.361430650
Short name T984
Test name
Test status
Simulation time 15648041 ps
CPU time 0.91 seconds
Started May 14 01:34:49 PM PDT 24
Finished May 14 01:34:51 PM PDT 24
Peak memory 209116 kb
Host smart-a53f10b0-52b2-4c94-92ff-9e318ae7dd78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361430650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.361430650
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1097516275
Short name T983
Test name
Test status
Simulation time 259373042 ps
CPU time 1.52 seconds
Started May 14 01:34:46 PM PDT 24
Finished May 14 01:34:48 PM PDT 24
Peak memory 211108 kb
Host smart-c6cf7ec3-c782-406c-859b-288e7db00a2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097516275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1097516275
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.3683846465
Short name T936
Test name
Test status
Simulation time 117251084 ps
CPU time 4.36 seconds
Started May 14 01:34:51 PM PDT 24
Finished May 14 01:34:56 PM PDT 24
Peak memory 217436 kb
Host smart-588b785e-fbd0-4a13-b2ee-bce97a9321cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683846465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.3683846465
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1238936291
Short name T125
Test name
Test status
Simulation time 122614174 ps
CPU time 2.74 seconds
Started May 14 01:34:49 PM PDT 24
Finished May 14 01:34:53 PM PDT 24
Peak memory 217600 kb
Host smart-fa2345e0-74aa-4a3c-a385-8b48b21e58de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238936291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1238936291
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3918246744
Short name T991
Test name
Test status
Simulation time 25227287 ps
CPU time 1.91 seconds
Started May 14 01:34:50 PM PDT 24
Finished May 14 01:34:53 PM PDT 24
Peak memory 219800 kb
Host smart-c4b025b5-cb50-4466-9593-68ba13b2d421
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918246744 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3918246744
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3594558937
Short name T872
Test name
Test status
Simulation time 17361654 ps
CPU time 0.94 seconds
Started May 14 01:34:48 PM PDT 24
Finished May 14 01:34:50 PM PDT 24
Peak memory 209124 kb
Host smart-e31546d5-357e-41e5-82ce-3e54def73924
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594558937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3594558937
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1341148377
Short name T893
Test name
Test status
Simulation time 27077640 ps
CPU time 1.48 seconds
Started May 14 01:34:48 PM PDT 24
Finished May 14 01:34:50 PM PDT 24
Peak memory 209196 kb
Host smart-bc3e6b31-3ac2-4d3d-896a-29058937eee5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341148377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1341148377
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1161578335
Short name T972
Test name
Test status
Simulation time 642405926 ps
CPU time 3.42 seconds
Started May 14 01:34:56 PM PDT 24
Finished May 14 01:35:00 PM PDT 24
Peak memory 217444 kb
Host smart-d9ca52c2-f6d6-425f-9b81-affdf9afa4b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161578335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1161578335
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.2546058482
Short name T998
Test name
Test status
Simulation time 121814771 ps
CPU time 1.42 seconds
Started May 14 01:34:55 PM PDT 24
Finished May 14 01:34:57 PM PDT 24
Peak memory 218560 kb
Host smart-80588781-0f47-48c2-9b48-1c731d96148b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546058482 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.2546058482
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.269316136
Short name T880
Test name
Test status
Simulation time 57117124 ps
CPU time 1.07 seconds
Started May 14 01:34:55 PM PDT 24
Finished May 14 01:34:57 PM PDT 24
Peak memory 217368 kb
Host smart-495af477-1541-4735-95e3-4d88850ade48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269316136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.269316136
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.753555849
Short name T967
Test name
Test status
Simulation time 150783763 ps
CPU time 1.36 seconds
Started May 14 01:34:55 PM PDT 24
Finished May 14 01:34:57 PM PDT 24
Peak memory 209164 kb
Host smart-6399021e-3db6-43be-875c-bf4f70552b2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753555849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_same_csr_outstanding.753555849
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.181779728
Short name T962
Test name
Test status
Simulation time 105957004 ps
CPU time 4.05 seconds
Started May 14 01:34:49 PM PDT 24
Finished May 14 01:34:54 PM PDT 24
Peak memory 217400 kb
Host smart-e9676835-ecf8-437c-aae9-0b44469a0034
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181779728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.181779728
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3834542173
Short name T948
Test name
Test status
Simulation time 150436131 ps
CPU time 1.62 seconds
Started May 14 01:34:56 PM PDT 24
Finished May 14 01:34:58 PM PDT 24
Peak memory 217424 kb
Host smart-0a27e29d-bbe5-446f-a629-ba4d6743491f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834542173 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3834542173
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2777874890
Short name T989
Test name
Test status
Simulation time 14019974 ps
CPU time 1.05 seconds
Started May 14 01:34:55 PM PDT 24
Finished May 14 01:34:56 PM PDT 24
Peak memory 209192 kb
Host smart-263c29e0-e193-45e4-b53a-b13794bd7bfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777874890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2777874890
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2915289104
Short name T971
Test name
Test status
Simulation time 100861128 ps
CPU time 1.33 seconds
Started May 14 01:34:57 PM PDT 24
Finished May 14 01:34:59 PM PDT 24
Peak memory 209076 kb
Host smart-7b96f96f-2693-4782-b441-513a09898341
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915289104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2915289104
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.3790154961
Short name T973
Test name
Test status
Simulation time 251605491 ps
CPU time 2.81 seconds
Started May 14 01:34:56 PM PDT 24
Finished May 14 01:35:00 PM PDT 24
Peak memory 217420 kb
Host smart-6e6d51dc-0817-401f-95a4-803af08a0cce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790154961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.3790154961
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3117622614
Short name T129
Test name
Test status
Simulation time 598135687 ps
CPU time 1.97 seconds
Started May 14 01:34:56 PM PDT 24
Finished May 14 01:34:59 PM PDT 24
Peak memory 221880 kb
Host smart-8c25d152-ce41-4b43-a387-dbd17e6c0d99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117622614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.3117622614
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1082255975
Short name T111
Test name
Test status
Simulation time 28623147 ps
CPU time 1.28 seconds
Started May 14 01:34:57 PM PDT 24
Finished May 14 01:34:59 PM PDT 24
Peak memory 218464 kb
Host smart-14099112-4c4b-4518-afc1-534501cb9a81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082255975 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1082255975
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3715074886
Short name T187
Test name
Test status
Simulation time 37163222 ps
CPU time 0.99 seconds
Started May 14 01:34:56 PM PDT 24
Finished May 14 01:34:58 PM PDT 24
Peak memory 209140 kb
Host smart-f8721d0e-7843-4801-b4a8-74c117ddb897
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715074886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3715074886
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1853346288
Short name T927
Test name
Test status
Simulation time 18998252 ps
CPU time 1.47 seconds
Started May 14 01:34:56 PM PDT 24
Finished May 14 01:34:58 PM PDT 24
Peak memory 209192 kb
Host smart-656bdb1b-81bc-4363-b767-5bbb2aef1af1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853346288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1853346288
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3354220531
Short name T959
Test name
Test status
Simulation time 53219491 ps
CPU time 2.93 seconds
Started May 14 01:34:56 PM PDT 24
Finished May 14 01:35:00 PM PDT 24
Peak memory 218444 kb
Host smart-e360ec83-bf25-4811-a1bf-b81614612aec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354220531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3354220531
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4260694454
Short name T124
Test name
Test status
Simulation time 152422002 ps
CPU time 2.75 seconds
Started May 14 01:34:56 PM PDT 24
Finished May 14 01:34:59 PM PDT 24
Peak memory 222048 kb
Host smart-6f0062fa-0f18-468a-b3b8-23e3187e233e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260694454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.4260694454
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1498688920
Short name T884
Test name
Test status
Simulation time 92109330 ps
CPU time 1.29 seconds
Started May 14 01:35:02 PM PDT 24
Finished May 14 01:35:04 PM PDT 24
Peak memory 217524 kb
Host smart-0cbb903a-e88f-4d25-b5fc-e15b9b5d7021
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498688920 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1498688920
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.803265569
Short name T918
Test name
Test status
Simulation time 25297262 ps
CPU time 1.05 seconds
Started May 14 01:35:02 PM PDT 24
Finished May 14 01:35:04 PM PDT 24
Peak memory 209132 kb
Host smart-d66f2564-ebc6-4d62-83aa-7363ed77872c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803265569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.803265569
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3811794027
Short name T929
Test name
Test status
Simulation time 43850762 ps
CPU time 1.4 seconds
Started May 14 01:35:02 PM PDT 24
Finished May 14 01:35:05 PM PDT 24
Peak memory 209248 kb
Host smart-f4933044-0330-4214-bbc2-4abc9b9a62a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811794027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3811794027
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3846384238
Short name T952
Test name
Test status
Simulation time 27535616 ps
CPU time 2.24 seconds
Started May 14 01:34:59 PM PDT 24
Finished May 14 01:35:02 PM PDT 24
Peak memory 217464 kb
Host smart-ecdb5f52-ea63-45b0-9979-615793423852
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846384238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3846384238
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3837268038
Short name T969
Test name
Test status
Simulation time 40888710 ps
CPU time 1.52 seconds
Started May 14 01:35:05 PM PDT 24
Finished May 14 01:35:07 PM PDT 24
Peak memory 217552 kb
Host smart-5989518f-db87-4c4d-97b7-b3f3f538fab1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837268038 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3837268038
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2109054675
Short name T196
Test name
Test status
Simulation time 31185061 ps
CPU time 1.18 seconds
Started May 14 01:35:05 PM PDT 24
Finished May 14 01:35:07 PM PDT 24
Peak memory 209020 kb
Host smart-1ba1a18d-cb05-47d3-b4c4-42576caef9fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109054675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2109054675
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2684060884
Short name T882
Test name
Test status
Simulation time 96225617 ps
CPU time 3.6 seconds
Started May 14 01:35:04 PM PDT 24
Finished May 14 01:35:08 PM PDT 24
Peak memory 217500 kb
Host smart-89fdf45e-c6e7-4f01-ac76-ab1385109686
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684060884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2684060884
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.4083899219
Short name T913
Test name
Test status
Simulation time 181141055 ps
CPU time 1 seconds
Started May 14 01:35:10 PM PDT 24
Finished May 14 01:35:12 PM PDT 24
Peak memory 218464 kb
Host smart-5e3e3c5b-9663-4fae-bc88-e4580160b9cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083899219 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.4083899219
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1767339434
Short name T978
Test name
Test status
Simulation time 12776276 ps
CPU time 0.99 seconds
Started May 14 01:35:08 PM PDT 24
Finished May 14 01:35:10 PM PDT 24
Peak memory 209140 kb
Host smart-ac698c02-c0f8-4d31-a980-46708c29cf94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767339434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1767339434
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2926031557
Short name T937
Test name
Test status
Simulation time 30315044 ps
CPU time 1.22 seconds
Started May 14 01:35:10 PM PDT 24
Finished May 14 01:35:12 PM PDT 24
Peak memory 209188 kb
Host smart-f6a70e1c-e9f4-4602-addb-26b3eb40a0dc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926031557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2926031557
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2472420368
Short name T97
Test name
Test status
Simulation time 99743354 ps
CPU time 2.53 seconds
Started May 14 01:35:09 PM PDT 24
Finished May 14 01:35:12 PM PDT 24
Peak memory 217992 kb
Host smart-02f1e8fa-16d1-4384-aa30-865ea86d4d62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472420368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2472420368
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.989098772
Short name T977
Test name
Test status
Simulation time 88298369 ps
CPU time 1.45 seconds
Started May 14 01:35:10 PM PDT 24
Finished May 14 01:35:13 PM PDT 24
Peak memory 217424 kb
Host smart-7e2f63e2-45b0-4fc3-99aa-78972f020cba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989098772 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.989098772
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3015544715
Short name T892
Test name
Test status
Simulation time 50656369 ps
CPU time 1 seconds
Started May 14 01:35:12 PM PDT 24
Finished May 14 01:35:14 PM PDT 24
Peak memory 208616 kb
Host smart-3a6103b1-959d-4748-8bd9-956ae9e07ffe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015544715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3015544715
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2809367354
Short name T975
Test name
Test status
Simulation time 16363360 ps
CPU time 1.18 seconds
Started May 14 01:35:10 PM PDT 24
Finished May 14 01:35:13 PM PDT 24
Peak memory 209216 kb
Host smart-47350dc0-b75e-4169-a9c2-838a15006aed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809367354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2809367354
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2300449835
Short name T887
Test name
Test status
Simulation time 54602114 ps
CPU time 1.79 seconds
Started May 14 01:35:09 PM PDT 24
Finished May 14 01:35:11 PM PDT 24
Peak memory 217508 kb
Host smart-791b0807-d795-4dff-8b29-1b4efb29ca00
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300449835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2300449835
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.626478067
Short name T188
Test name
Test status
Simulation time 26758884 ps
CPU time 1.01 seconds
Started May 14 01:34:11 PM PDT 24
Finished May 14 01:34:13 PM PDT 24
Peak memory 209184 kb
Host smart-d6fb715a-c219-4ceb-ab2d-0f4b2f4a1808
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626478067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.626478067
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.3851300876
Short name T981
Test name
Test status
Simulation time 21139458 ps
CPU time 1.25 seconds
Started May 14 01:34:11 PM PDT 24
Finished May 14 01:34:13 PM PDT 24
Peak memory 209152 kb
Host smart-88dc975b-06a0-46d2-a09e-dbec84b2f375
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851300876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.3851300876
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.275507873
Short name T182
Test name
Test status
Simulation time 59424837 ps
CPU time 1.06 seconds
Started May 14 01:34:11 PM PDT 24
Finished May 14 01:34:13 PM PDT 24
Peak memory 209628 kb
Host smart-3e72cfc3-a1af-4e5e-bbb6-249ecf9bc737
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275507873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset
.275507873
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2927366000
Short name T894
Test name
Test status
Simulation time 19242016 ps
CPU time 1.15 seconds
Started May 14 01:34:24 PM PDT 24
Finished May 14 01:34:26 PM PDT 24
Peak memory 218856 kb
Host smart-4b94626c-d154-46ad-b4f6-0e37a965e2f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927366000 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2927366000
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2392709003
Short name T183
Test name
Test status
Simulation time 15484418 ps
CPU time 1.18 seconds
Started May 14 01:34:11 PM PDT 24
Finished May 14 01:34:13 PM PDT 24
Peak memory 209196 kb
Host smart-0696d95d-5df7-42ec-b2bb-eac028cd45fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392709003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2392709003
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3181758847
Short name T914
Test name
Test status
Simulation time 388613159 ps
CPU time 1.56 seconds
Started May 14 01:34:11 PM PDT 24
Finished May 14 01:34:14 PM PDT 24
Peak memory 209040 kb
Host smart-f863969e-6910-4b4b-ad16-34a5efd732c4
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181758847 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3181758847
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1921773778
Short name T968
Test name
Test status
Simulation time 361852645 ps
CPU time 9.21 seconds
Started May 14 01:34:11 PM PDT 24
Finished May 14 01:34:21 PM PDT 24
Peak memory 208896 kb
Host smart-4b3d8c91-fc0a-49c3-a387-767d74b0857d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921773778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1921773778
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1605655137
Short name T905
Test name
Test status
Simulation time 2826178391 ps
CPU time 8.43 seconds
Started May 14 01:34:11 PM PDT 24
Finished May 14 01:34:21 PM PDT 24
Peak memory 209120 kb
Host smart-942232c1-299b-46e6-a50a-202efb98bb6d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605655137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1605655137
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1621034774
Short name T954
Test name
Test status
Simulation time 157955936 ps
CPU time 1.23 seconds
Started May 14 01:34:02 PM PDT 24
Finished May 14 01:34:04 PM PDT 24
Peak memory 210188 kb
Host smart-0758f199-b9bd-4fe4-9e88-24465daecaa8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621034774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1621034774
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3380088980
Short name T943
Test name
Test status
Simulation time 466687923 ps
CPU time 2.34 seconds
Started May 14 01:34:13 PM PDT 24
Finished May 14 01:34:16 PM PDT 24
Peak memory 218652 kb
Host smart-a174902a-b0fd-452e-8812-40ffe1dcc6d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338008
8980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3380088980
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.992958782
Short name T925
Test name
Test status
Simulation time 89750803 ps
CPU time 1.58 seconds
Started May 14 01:34:11 PM PDT 24
Finished May 14 01:34:14 PM PDT 24
Peak memory 209008 kb
Host smart-202220cb-f796-4279-b57f-2c97f1a6a4d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992958782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.992958782
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1261280695
Short name T132
Test name
Test status
Simulation time 41218013 ps
CPU time 1.51 seconds
Started May 14 01:34:12 PM PDT 24
Finished May 14 01:34:14 PM PDT 24
Peak memory 211248 kb
Host smart-1299ecb4-1098-4821-88d8-87e946b3c5da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261280695 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1261280695
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1353046026
Short name T195
Test name
Test status
Simulation time 152723514 ps
CPU time 1.47 seconds
Started May 14 01:34:10 PM PDT 24
Finished May 14 01:34:12 PM PDT 24
Peak memory 211240 kb
Host smart-337e0257-abd2-4a67-b0fe-25270955bf08
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353046026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1353046026
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1177925646
Short name T955
Test name
Test status
Simulation time 229701674 ps
CPU time 2.2 seconds
Started May 14 01:34:10 PM PDT 24
Finished May 14 01:34:13 PM PDT 24
Peak memory 217420 kb
Host smart-9bb676bc-9c1c-460e-85d8-52cc3ac047ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177925646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1177925646
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3289282712
Short name T897
Test name
Test status
Simulation time 23611832 ps
CPU time 1.37 seconds
Started May 14 01:34:28 PM PDT 24
Finished May 14 01:34:30 PM PDT 24
Peak memory 209196 kb
Host smart-3ddc0e97-d905-4be6-9114-2775b00d0fc2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289282712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3289282712
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3758035874
Short name T942
Test name
Test status
Simulation time 53944564 ps
CPU time 1.12 seconds
Started May 14 01:34:26 PM PDT 24
Finished May 14 01:34:29 PM PDT 24
Peak memory 208312 kb
Host smart-f676fb4a-631e-4755-85db-02db46020eec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758035874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3758035874
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1952807014
Short name T1000
Test name
Test status
Simulation time 25808439 ps
CPU time 1.1 seconds
Started May 14 01:34:40 PM PDT 24
Finished May 14 01:34:42 PM PDT 24
Peak memory 209196 kb
Host smart-18d1bff1-e4d2-4dbb-af57-86f842f28ec6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952807014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1952807014
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.4078942523
Short name T957
Test name
Test status
Simulation time 16507674 ps
CPU time 1.34 seconds
Started May 14 01:34:26 PM PDT 24
Finished May 14 01:34:29 PM PDT 24
Peak memory 219240 kb
Host smart-e9718a68-0d3e-4ad5-94cc-314bc1fa2424
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078942523 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.4078942523
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.640899318
Short name T194
Test name
Test status
Simulation time 19777482 ps
CPU time 0.87 seconds
Started May 14 01:34:26 PM PDT 24
Finished May 14 01:34:29 PM PDT 24
Peak memory 208780 kb
Host smart-1b28d8f1-a4d9-433f-9593-75e61142b2bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640899318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.640899318
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3684584047
Short name T903
Test name
Test status
Simulation time 312708994 ps
CPU time 1.1 seconds
Started May 14 01:34:21 PM PDT 24
Finished May 14 01:34:23 PM PDT 24
Peak memory 209048 kb
Host smart-d76ee2c6-fbc6-4c74-bd8c-bf2a5af41eb5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684584047 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3684584047
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.4156501259
Short name T985
Test name
Test status
Simulation time 2253580477 ps
CPU time 3.42 seconds
Started May 14 01:34:18 PM PDT 24
Finished May 14 01:34:22 PM PDT 24
Peak memory 208308 kb
Host smart-f0ff8d11-42aa-4bf5-b99f-6fb5977e4ebf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156501259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.4156501259
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3805161455
Short name T939
Test name
Test status
Simulation time 1074908096 ps
CPU time 12.12 seconds
Started May 14 01:34:17 PM PDT 24
Finished May 14 01:34:30 PM PDT 24
Peak memory 208776 kb
Host smart-825ede8f-418b-4665-a90a-fd4729f50a27
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805161455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3805161455
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1279205416
Short name T960
Test name
Test status
Simulation time 52378716 ps
CPU time 1.39 seconds
Started May 14 01:34:19 PM PDT 24
Finished May 14 01:34:21 PM PDT 24
Peak memory 210484 kb
Host smart-ee85f22c-2bca-4dea-a6af-0ecba6e0ef72
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279205416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1279205416
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.43747209
Short name T900
Test name
Test status
Simulation time 227694221 ps
CPU time 1.59 seconds
Started May 14 01:34:18 PM PDT 24
Finished May 14 01:34:20 PM PDT 24
Peak memory 219252 kb
Host smart-60147afd-47f8-4713-a9cc-47930523bd76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437472
09 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.43747209
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2349238487
Short name T910
Test name
Test status
Simulation time 70061021 ps
CPU time 1.7 seconds
Started May 14 01:34:27 PM PDT 24
Finished May 14 01:34:31 PM PDT 24
Peak memory 209044 kb
Host smart-1adec273-8277-4f7d-a589-2da581ba79f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349238487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2349238487
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3504500912
Short name T198
Test name
Test status
Simulation time 49767735 ps
CPU time 1.4 seconds
Started May 14 01:34:19 PM PDT 24
Finished May 14 01:34:21 PM PDT 24
Peak memory 209172 kb
Host smart-ce52f868-a853-4ee2-af3d-8cf73fbcade7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504500912 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3504500912
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1477340563
Short name T988
Test name
Test status
Simulation time 34811608 ps
CPU time 1.14 seconds
Started May 14 01:34:27 PM PDT 24
Finished May 14 01:34:30 PM PDT 24
Peak memory 209152 kb
Host smart-4e456c47-c2e4-4e09-bfe0-bb538c344200
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477340563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1477340563
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4205053302
Short name T110
Test name
Test status
Simulation time 625460711 ps
CPU time 5.98 seconds
Started May 14 01:34:17 PM PDT 24
Finished May 14 01:34:24 PM PDT 24
Peak memory 217428 kb
Host smart-3dac3839-669a-4aed-8f0d-cfdfdf3d72f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205053302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.4205053302
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2290443845
Short name T128
Test name
Test status
Simulation time 109822284 ps
CPU time 3.23 seconds
Started May 14 01:34:25 PM PDT 24
Finished May 14 01:34:29 PM PDT 24
Peak memory 221868 kb
Host smart-a04e27b6-3ad2-423f-9cd7-dc1788e792c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290443845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2290443845
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.4203296098
Short name T186
Test name
Test status
Simulation time 169304089 ps
CPU time 1.32 seconds
Started May 14 01:34:37 PM PDT 24
Finished May 14 01:34:40 PM PDT 24
Peak memory 209224 kb
Host smart-de5afa6c-e241-45c3-9edf-95781ba11eee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203296098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.4203296098
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.510165712
Short name T921
Test name
Test status
Simulation time 408650713 ps
CPU time 2.3 seconds
Started May 14 01:34:25 PM PDT 24
Finished May 14 01:34:29 PM PDT 24
Peak memory 209176 kb
Host smart-7df4f6f2-9ede-460a-ac11-c3cf2e3fe0f2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510165712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.510165712
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.1468069502
Short name T193
Test name
Test status
Simulation time 71013593 ps
CPU time 1.05 seconds
Started May 14 01:34:25 PM PDT 24
Finished May 14 01:34:28 PM PDT 24
Peak memory 211060 kb
Host smart-b0c79b1a-ce05-4b27-9c53-54bc4513a5be
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468069502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.1468069502
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.4099736989
Short name T964
Test name
Test status
Simulation time 94609387 ps
CPU time 1.89 seconds
Started May 14 01:34:25 PM PDT 24
Finished May 14 01:34:29 PM PDT 24
Peak memory 219500 kb
Host smart-3141ab7b-324d-4e89-b8c1-a43390a56930
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099736989 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.4099736989
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2504741144
Short name T890
Test name
Test status
Simulation time 43600701 ps
CPU time 1.05 seconds
Started May 14 01:34:28 PM PDT 24
Finished May 14 01:34:30 PM PDT 24
Peak memory 208724 kb
Host smart-25b4c98d-c515-4958-a157-a4236a4c7067
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504741144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2504741144
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3161027863
Short name T951
Test name
Test status
Simulation time 254438977 ps
CPU time 1.23 seconds
Started May 14 01:34:26 PM PDT 24
Finished May 14 01:34:28 PM PDT 24
Peak memory 207732 kb
Host smart-f4af0319-8c77-4286-a297-65d0450c35ec
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161027863 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3161027863
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.4048415976
Short name T941
Test name
Test status
Simulation time 10504851328 ps
CPU time 13.93 seconds
Started May 14 01:34:26 PM PDT 24
Finished May 14 01:34:41 PM PDT 24
Peak memory 209176 kb
Host smart-cef92738-86fc-4fa9-a05d-9dcc365bdabc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048415976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.4048415976
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1496353768
Short name T958
Test name
Test status
Simulation time 3115835818 ps
CPU time 20.3 seconds
Started May 14 01:34:26 PM PDT 24
Finished May 14 01:34:48 PM PDT 24
Peak memory 208392 kb
Host smart-0282f4dc-0225-459f-8cb7-fc17d0462b28
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496353768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1496353768
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2251694067
Short name T917
Test name
Test status
Simulation time 497111434 ps
CPU time 1.89 seconds
Started May 14 01:34:40 PM PDT 24
Finished May 14 01:34:42 PM PDT 24
Peak memory 210676 kb
Host smart-5ab5d889-174c-4f37-82e2-4d215f759199
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251694067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2251694067
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1994326943
Short name T935
Test name
Test status
Simulation time 130750272 ps
CPU time 2.38 seconds
Started May 14 01:34:28 PM PDT 24
Finished May 14 01:34:32 PM PDT 24
Peak memory 209080 kb
Host smart-56c4ee69-521d-4c7a-bc6a-650ccefa96eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994326943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1994326943
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.1458480543
Short name T966
Test name
Test status
Simulation time 17333485 ps
CPU time 1.27 seconds
Started May 14 01:34:27 PM PDT 24
Finished May 14 01:34:30 PM PDT 24
Peak memory 209212 kb
Host smart-ec5c2625-0f5a-4339-a927-b0510a06bedf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458480543 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.1458480543
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1178102385
Short name T944
Test name
Test status
Simulation time 40602963 ps
CPU time 1.35 seconds
Started May 14 01:34:27 PM PDT 24
Finished May 14 01:34:30 PM PDT 24
Peak memory 211324 kb
Host smart-b6143004-6888-4003-9dbf-5099d2db97c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178102385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1178102385
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1006018384
Short name T889
Test name
Test status
Simulation time 290698442 ps
CPU time 2.25 seconds
Started May 14 01:34:27 PM PDT 24
Finished May 14 01:34:31 PM PDT 24
Peak memory 217476 kb
Host smart-ba5b69ce-3afe-4610-a528-7acb9a1efdc3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006018384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1006018384
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3970963173
Short name T899
Test name
Test status
Simulation time 21630242 ps
CPU time 1.05 seconds
Started May 14 01:34:36 PM PDT 24
Finished May 14 01:34:39 PM PDT 24
Peak memory 218512 kb
Host smart-9d9e3995-51f4-4a02-a79e-54bd15ee847d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970963173 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3970963173
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.382511583
Short name T993
Test name
Test status
Simulation time 12681775 ps
CPU time 0.9 seconds
Started May 14 01:34:34 PM PDT 24
Finished May 14 01:34:36 PM PDT 24
Peak memory 208924 kb
Host smart-c863651e-a90a-4053-a273-ea6fa6867681
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382511583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.382511583
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2145525703
Short name T915
Test name
Test status
Simulation time 201695539 ps
CPU time 1.61 seconds
Started May 14 01:34:41 PM PDT 24
Finished May 14 01:34:43 PM PDT 24
Peak memory 209036 kb
Host smart-5247d887-f0eb-4f1f-b4e6-02c11a8159bc
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145525703 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2145525703
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3618740318
Short name T891
Test name
Test status
Simulation time 723142658 ps
CPU time 4.18 seconds
Started May 14 01:34:35 PM PDT 24
Finished May 14 01:34:40 PM PDT 24
Peak memory 207448 kb
Host smart-a7fc2857-5caf-49ad-9172-696e96475e3b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618740318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3618740318
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1110449153
Short name T965
Test name
Test status
Simulation time 2147473433 ps
CPU time 15.42 seconds
Started May 14 01:34:35 PM PDT 24
Finished May 14 01:34:51 PM PDT 24
Peak memory 209280 kb
Host smart-137b8588-29a2-423e-81d7-837d97300788
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110449153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1110449153
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2468147362
Short name T131
Test name
Test status
Simulation time 1124293469 ps
CPU time 3.56 seconds
Started May 14 01:34:26 PM PDT 24
Finished May 14 01:34:31 PM PDT 24
Peak memory 210656 kb
Host smart-2c5bf8c8-7f63-4295-a2c1-40b0cfa59f5b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468147362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2468147362
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.450511380
Short name T982
Test name
Test status
Simulation time 87155837 ps
CPU time 3.39 seconds
Started May 14 01:34:35 PM PDT 24
Finished May 14 01:34:39 PM PDT 24
Peak memory 218440 kb
Host smart-41d0e17d-6cdf-488d-bf1c-d08f2282abfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450511
380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.450511380
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1147176781
Short name T130
Test name
Test status
Simulation time 35242439 ps
CPU time 1.55 seconds
Started May 14 01:34:34 PM PDT 24
Finished May 14 01:34:37 PM PDT 24
Peak memory 209088 kb
Host smart-c9205291-b456-4e24-8094-067b4a7aaa2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147176781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1147176781
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.760487517
Short name T901
Test name
Test status
Simulation time 15731674 ps
CPU time 1.23 seconds
Started May 14 01:34:38 PM PDT 24
Finished May 14 01:34:40 PM PDT 24
Peak memory 209164 kb
Host smart-7cdbb5c3-3bf1-4781-9367-4cb8bd6a99e5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760487517 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.760487517
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.680951918
Short name T934
Test name
Test status
Simulation time 98571969 ps
CPU time 1.41 seconds
Started May 14 01:34:40 PM PDT 24
Finished May 14 01:34:42 PM PDT 24
Peak memory 209188 kb
Host smart-85c68350-113a-4adc-9f90-a3192a4018fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680951918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.680951918
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3826691138
Short name T98
Test name
Test status
Simulation time 737782476 ps
CPU time 4.56 seconds
Started May 14 01:34:37 PM PDT 24
Finished May 14 01:34:42 PM PDT 24
Peak memory 217436 kb
Host smart-963d5c13-44d0-4635-b520-c97d83e456a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826691138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3826691138
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2856140370
Short name T950
Test name
Test status
Simulation time 28704749 ps
CPU time 1.24 seconds
Started May 14 01:34:40 PM PDT 24
Finished May 14 01:34:43 PM PDT 24
Peak memory 217524 kb
Host smart-8e47eee4-5ba8-4914-ac77-0bd1618189bc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856140370 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2856140370
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.770598590
Short name T189
Test name
Test status
Simulation time 20304119 ps
CPU time 1.21 seconds
Started May 14 01:34:34 PM PDT 24
Finished May 14 01:34:36 PM PDT 24
Peak memory 209156 kb
Host smart-7ba653a4-606d-4d17-be26-6cccaa08b2a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770598590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.770598590
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3079762709
Short name T879
Test name
Test status
Simulation time 55461988 ps
CPU time 1.33 seconds
Started May 14 01:34:34 PM PDT 24
Finished May 14 01:34:37 PM PDT 24
Peak memory 209092 kb
Host smart-b45f26f9-b512-4e87-93f9-4de8f8ef7765
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079762709 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3079762709
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.704869355
Short name T996
Test name
Test status
Simulation time 570273837 ps
CPU time 12.58 seconds
Started May 14 01:34:33 PM PDT 24
Finished May 14 01:34:47 PM PDT 24
Peak memory 208820 kb
Host smart-4ed0f9dc-d6c8-4eb5-a33d-51b933826603
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704869355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.704869355
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.238313031
Short name T201
Test name
Test status
Simulation time 4295727258 ps
CPU time 10.07 seconds
Started May 14 01:34:34 PM PDT 24
Finished May 14 01:34:45 PM PDT 24
Peak memory 209136 kb
Host smart-aff1e2ad-d5bf-4c5e-80a0-53d432e3df64
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238313031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.238313031
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3383334242
Short name T970
Test name
Test status
Simulation time 523357375 ps
CPU time 3.81 seconds
Started May 14 01:34:41 PM PDT 24
Finished May 14 01:34:45 PM PDT 24
Peak memory 210772 kb
Host smart-bb872bc2-c79e-415f-803b-b1e5d31fe4eb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383334242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.3383334242
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3000032665
Short name T896
Test name
Test status
Simulation time 961849704 ps
CPU time 3.62 seconds
Started May 14 01:34:35 PM PDT 24
Finished May 14 01:34:40 PM PDT 24
Peak memory 217440 kb
Host smart-4e8acfca-2d88-498d-9ed2-d289346ff51f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300003
2665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3000032665
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.76105163
Short name T949
Test name
Test status
Simulation time 49506741 ps
CPU time 1.16 seconds
Started May 14 01:34:34 PM PDT 24
Finished May 14 01:34:37 PM PDT 24
Peak memory 208064 kb
Host smart-f8252932-7c6c-4735-942d-211212e62aa5
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76105163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 6.lc_ctrl_jtag_csr_rw.76105163
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3549605767
Short name T883
Test name
Test status
Simulation time 207842600 ps
CPU time 1.4 seconds
Started May 14 01:34:34 PM PDT 24
Finished May 14 01:34:37 PM PDT 24
Peak memory 209212 kb
Host smart-22275643-045b-40f3-a81c-318b796affcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549605767 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3549605767
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3223585163
Short name T992
Test name
Test status
Simulation time 36534826 ps
CPU time 1.37 seconds
Started May 14 01:34:34 PM PDT 24
Finished May 14 01:34:37 PM PDT 24
Peak memory 209144 kb
Host smart-0a046db7-c067-4e63-a1ec-6758b59c293e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223585163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3223585163
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2424255182
Short name T904
Test name
Test status
Simulation time 344941882 ps
CPU time 1.46 seconds
Started May 14 01:34:34 PM PDT 24
Finished May 14 01:34:36 PM PDT 24
Peak memory 217460 kb
Host smart-e60af7c6-8b94-440f-9927-16216445c184
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424255182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2424255182
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2575342123
Short name T117
Test name
Test status
Simulation time 65378988 ps
CPU time 2.68 seconds
Started May 14 01:34:33 PM PDT 24
Finished May 14 01:34:37 PM PDT 24
Peak memory 217344 kb
Host smart-aa5400df-8050-40d9-afd0-67794d7dfcd9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575342123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2575342123
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2574452679
Short name T946
Test name
Test status
Simulation time 18589644 ps
CPU time 1.19 seconds
Started May 14 01:34:42 PM PDT 24
Finished May 14 01:34:45 PM PDT 24
Peak memory 217468 kb
Host smart-d8d15c96-33ba-46aa-bb44-8f930de15a2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574452679 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2574452679
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4079938840
Short name T191
Test name
Test status
Simulation time 18648220 ps
CPU time 0.78 seconds
Started May 14 01:34:49 PM PDT 24
Finished May 14 01:34:51 PM PDT 24
Peak memory 209092 kb
Host smart-e61e0e49-767e-4426-a4ed-ac080d904e87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079938840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.4079938840
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.476528303
Short name T902
Test name
Test status
Simulation time 42514567 ps
CPU time 1.67 seconds
Started May 14 01:34:41 PM PDT 24
Finished May 14 01:34:45 PM PDT 24
Peak memory 209016 kb
Host smart-abd91b36-f105-4371-ba25-beb28b8acf4d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476528303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.lc_ctrl_jtag_alert_test.476528303
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.823015507
Short name T986
Test name
Test status
Simulation time 494200226 ps
CPU time 10.97 seconds
Started May 14 01:34:49 PM PDT 24
Finished May 14 01:35:02 PM PDT 24
Peak memory 208268 kb
Host smart-bc441613-207c-4670-beb7-cca95ec3cc4b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823015507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.823015507
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.4003987732
Short name T947
Test name
Test status
Simulation time 1410476187 ps
CPU time 8.51 seconds
Started May 14 01:34:42 PM PDT 24
Finished May 14 01:34:52 PM PDT 24
Peak memory 207680 kb
Host smart-1bbcf752-7516-46d9-8507-d69410e0474a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003987732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.4003987732
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2734866747
Short name T979
Test name
Test status
Simulation time 186752957 ps
CPU time 1.25 seconds
Started May 14 01:34:41 PM PDT 24
Finished May 14 01:34:44 PM PDT 24
Peak memory 209060 kb
Host smart-f3f1b0bb-b190-4656-a899-ac35414b8fcc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734866747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2734866747
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1020761190
Short name T995
Test name
Test status
Simulation time 468833161 ps
CPU time 3.75 seconds
Started May 14 01:34:43 PM PDT 24
Finished May 14 01:34:48 PM PDT 24
Peak memory 217532 kb
Host smart-4790f1e2-a46d-4379-9f2a-2c5e0bcd07b6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102076
1190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1020761190
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1676495276
Short name T107
Test name
Test status
Simulation time 63171210 ps
CPU time 2.4 seconds
Started May 14 01:34:42 PM PDT 24
Finished May 14 01:34:46 PM PDT 24
Peak memory 209084 kb
Host smart-72566b99-88a1-4b02-a182-b3b66d160caf
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676495276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1676495276
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2653280369
Short name T197
Test name
Test status
Simulation time 16194220 ps
CPU time 1.06 seconds
Started May 14 01:34:42 PM PDT 24
Finished May 14 01:34:45 PM PDT 24
Peak memory 217440 kb
Host smart-33aec308-0b7c-401c-baee-fa0b0b098bfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653280369 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2653280369
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1335113889
Short name T922
Test name
Test status
Simulation time 17971173 ps
CPU time 1.05 seconds
Started May 14 01:34:41 PM PDT 24
Finished May 14 01:34:44 PM PDT 24
Peak memory 209272 kb
Host smart-2a834ed4-aed2-4830-afbf-99ed08be6374
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335113889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1335113889
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1244393546
Short name T885
Test name
Test status
Simulation time 20969623 ps
CPU time 1.56 seconds
Started May 14 01:34:50 PM PDT 24
Finished May 14 01:34:53 PM PDT 24
Peak memory 217524 kb
Host smart-221c275f-e832-47b0-8ef3-6cbded496cfc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244393546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.1244393546
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.4101680806
Short name T924
Test name
Test status
Simulation time 154932993 ps
CPU time 1.15 seconds
Started May 14 01:34:43 PM PDT 24
Finished May 14 01:34:45 PM PDT 24
Peak memory 220552 kb
Host smart-a48341f6-32f6-4f5a-9390-8cd0dab5c3cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101680806 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.4101680806
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.810190953
Short name T990
Test name
Test status
Simulation time 15443764 ps
CPU time 0.93 seconds
Started May 14 01:34:42 PM PDT 24
Finished May 14 01:34:45 PM PDT 24
Peak memory 209196 kb
Host smart-a91e2a16-b5ff-4677-ad2c-1359affba89e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810190953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.810190953
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.4070068588
Short name T874
Test name
Test status
Simulation time 57720180 ps
CPU time 2.12 seconds
Started May 14 01:34:42 PM PDT 24
Finished May 14 01:34:46 PM PDT 24
Peak memory 207772 kb
Host smart-57905529-76be-4900-afc6-44acbfda7587
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070068588 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.4070068588
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3428267621
Short name T980
Test name
Test status
Simulation time 430601366 ps
CPU time 11.6 seconds
Started May 14 01:34:41 PM PDT 24
Finished May 14 01:34:54 PM PDT 24
Peak memory 208204 kb
Host smart-0421874f-bf37-4976-84aa-52470e990891
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428267621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3428267621
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2727811419
Short name T888
Test name
Test status
Simulation time 2002438792 ps
CPU time 22.26 seconds
Started May 14 01:34:50 PM PDT 24
Finished May 14 01:35:13 PM PDT 24
Peak memory 208852 kb
Host smart-60ad43f3-f416-41a2-8b74-1e46f5c4cda0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727811419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2727811419
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2661521909
Short name T906
Test name
Test status
Simulation time 302286677 ps
CPU time 2.67 seconds
Started May 14 01:34:41 PM PDT 24
Finished May 14 01:34:45 PM PDT 24
Peak memory 210716 kb
Host smart-1b6d549f-dcec-45bb-914b-3f82f87d30b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661521909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2661521909
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1152191430
Short name T945
Test name
Test status
Simulation time 57528485 ps
CPU time 2.21 seconds
Started May 14 01:34:50 PM PDT 24
Finished May 14 01:34:53 PM PDT 24
Peak memory 217524 kb
Host smart-010057dd-7119-4689-be14-272fdc79837c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115219
1430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1152191430
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3219522299
Short name T933
Test name
Test status
Simulation time 105092157 ps
CPU time 1.79 seconds
Started May 14 01:34:41 PM PDT 24
Finished May 14 01:34:44 PM PDT 24
Peak memory 209088 kb
Host smart-715c3fe2-b054-4613-9834-757607a36450
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219522299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.3219522299
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3808314395
Short name T886
Test name
Test status
Simulation time 47110409 ps
CPU time 1.48 seconds
Started May 14 01:34:42 PM PDT 24
Finished May 14 01:34:46 PM PDT 24
Peak memory 209164 kb
Host smart-736ab9df-26ac-4cf8-8dab-3603d32519ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808314395 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3808314395
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.993183206
Short name T976
Test name
Test status
Simulation time 29157169 ps
CPU time 1.2 seconds
Started May 14 01:34:42 PM PDT 24
Finished May 14 01:34:45 PM PDT 24
Peak memory 209204 kb
Host smart-d76b9acc-e911-4105-9914-d125ec8c8d55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993183206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.993183206
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1188778780
Short name T99
Test name
Test status
Simulation time 53628559 ps
CPU time 2.28 seconds
Started May 14 01:34:43 PM PDT 24
Finished May 14 01:34:47 PM PDT 24
Peak memory 217436 kb
Host smart-e2ea2f61-fdaa-4681-86a7-f62fee73e3e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188778780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1188778780
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.844222632
Short name T120
Test name
Test status
Simulation time 240847608 ps
CPU time 2.03 seconds
Started May 14 01:34:44 PM PDT 24
Finished May 14 01:34:47 PM PDT 24
Peak memory 221220 kb
Host smart-ab30d5ef-540e-4320-8fc0-b2df90e51f22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844222632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_e
rr.844222632
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2601934792
Short name T148
Test name
Test status
Simulation time 30884590 ps
CPU time 1.72 seconds
Started May 14 01:34:48 PM PDT 24
Finished May 14 01:34:51 PM PDT 24
Peak memory 217420 kb
Host smart-7c073c09-cac5-48ea-a1be-8d58974010bb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601934792 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2601934792
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2339864708
Short name T133
Test name
Test status
Simulation time 57301645 ps
CPU time 0.93 seconds
Started May 14 01:34:49 PM PDT 24
Finished May 14 01:34:51 PM PDT 24
Peak memory 208716 kb
Host smart-4ede3d26-f359-4c7a-aef8-fa9a3aa43792
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339864708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2339864708
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1110399725
Short name T873
Test name
Test status
Simulation time 261229928 ps
CPU time 1.15 seconds
Started May 14 01:34:40 PM PDT 24
Finished May 14 01:34:42 PM PDT 24
Peak memory 207644 kb
Host smart-ed41cd0f-73ad-476f-9627-c54e2dc222a6
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110399725 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1110399725
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1464900063
Short name T974
Test name
Test status
Simulation time 2914606137 ps
CPU time 16.1 seconds
Started May 14 01:34:43 PM PDT 24
Finished May 14 01:35:01 PM PDT 24
Peak memory 209212 kb
Host smart-cc5bc0a9-6d12-44f9-8816-17bdb233b967
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464900063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1464900063
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1587193098
Short name T876
Test name
Test status
Simulation time 2011444174 ps
CPU time 23.89 seconds
Started May 14 01:34:43 PM PDT 24
Finished May 14 01:35:09 PM PDT 24
Peak memory 208876 kb
Host smart-b6ce7051-7715-4160-8593-06f818fde6dd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587193098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1587193098
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.710656805
Short name T961
Test name
Test status
Simulation time 507857050 ps
CPU time 3.62 seconds
Started May 14 01:34:43 PM PDT 24
Finished May 14 01:34:48 PM PDT 24
Peak memory 210564 kb
Host smart-148d9cdc-933e-4588-a5de-c89f0d59cb10
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710656805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.710656805
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2629752030
Short name T911
Test name
Test status
Simulation time 412936810 ps
CPU time 3.28 seconds
Started May 14 01:34:50 PM PDT 24
Finished May 14 01:34:54 PM PDT 24
Peak memory 219864 kb
Host smart-04df51f8-249e-493c-929d-6ec3cf88b025
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262975
2030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2629752030
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3392471519
Short name T926
Test name
Test status
Simulation time 114697143 ps
CPU time 1.24 seconds
Started May 14 01:34:41 PM PDT 24
Finished May 14 01:34:44 PM PDT 24
Peak memory 208244 kb
Host smart-31589d9b-c62b-42bc-93ff-dbb111f02e16
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392471519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3392471519
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2269555036
Short name T956
Test name
Test status
Simulation time 18167451 ps
CPU time 1.08 seconds
Started May 14 01:34:43 PM PDT 24
Finished May 14 01:34:46 PM PDT 24
Peak memory 217336 kb
Host smart-256626a7-1a1e-45ee-b822-1e0c89c9a4f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269555036 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2269555036
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2559565321
Short name T199
Test name
Test status
Simulation time 25213856 ps
CPU time 1.11 seconds
Started May 14 01:34:48 PM PDT 24
Finished May 14 01:34:51 PM PDT 24
Peak memory 209180 kb
Host smart-41ff963f-a0cc-45f9-8f89-dac9d5d23bdc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559565321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2559565321
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3618248000
Short name T940
Test name
Test status
Simulation time 173588645 ps
CPU time 2.41 seconds
Started May 14 01:34:42 PM PDT 24
Finished May 14 01:34:46 PM PDT 24
Peak memory 217516 kb
Host smart-8d2b4dc4-3e39-4d59-8fa1-33f384243a1d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618248000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3618248000
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.4163406409
Short name T332
Test name
Test status
Simulation time 17991838 ps
CPU time 1.12 seconds
Started May 14 01:36:34 PM PDT 24
Finished May 14 01:36:38 PM PDT 24
Peak memory 209688 kb
Host smart-1e4ee0f5-566b-4df4-ab56-8b884ce058a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163406409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.4163406409
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1521133869
Short name T694
Test name
Test status
Simulation time 410258807 ps
CPU time 11.94 seconds
Started May 14 01:36:33 PM PDT 24
Finished May 14 01:36:47 PM PDT 24
Peak memory 218124 kb
Host smart-27c96adf-d323-4df9-a3fb-4a318392fc75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521133869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1521133869
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2763071517
Short name T8
Test name
Test status
Simulation time 89809112 ps
CPU time 1.26 seconds
Started May 14 01:36:32 PM PDT 24
Finished May 14 01:36:34 PM PDT 24
Peak memory 217020 kb
Host smart-d55cbceb-7820-46f5-a088-79d7daf4a4df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763071517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2763071517
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.1706827872
Short name T492
Test name
Test status
Simulation time 2936431728 ps
CPU time 84.64 seconds
Started May 14 01:36:33 PM PDT 24
Finished May 14 01:38:00 PM PDT 24
Peak memory 219156 kb
Host smart-4c8671c0-3df2-4071-9945-f11279bc17d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706827872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.1706827872
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.4170364431
Short name T863
Test name
Test status
Simulation time 151178050 ps
CPU time 4.46 seconds
Started May 14 01:36:32 PM PDT 24
Finished May 14 01:36:38 PM PDT 24
Peak memory 217216 kb
Host smart-369dce9b-0e26-42ad-9df8-7dfbefbb3fcf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170364431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.4
170364431
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1418969268
Short name T362
Test name
Test status
Simulation time 609409455 ps
CPU time 8.97 seconds
Started May 14 01:36:34 PM PDT 24
Finished May 14 01:36:46 PM PDT 24
Peak memory 218144 kb
Host smart-7689d193-3ee6-4954-981d-295948e4c803
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418969268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1418969268
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.4007908281
Short name T437
Test name
Test status
Simulation time 2719088988 ps
CPU time 14.01 seconds
Started May 14 01:36:33 PM PDT 24
Finished May 14 01:36:50 PM PDT 24
Peak memory 213672 kb
Host smart-40969380-9895-46aa-8a18-3cbb8e5ade29
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007908281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.4007908281
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2036490461
Short name T413
Test name
Test status
Simulation time 201383252 ps
CPU time 2.43 seconds
Started May 14 01:36:32 PM PDT 24
Finished May 14 01:36:37 PM PDT 24
Peak memory 213340 kb
Host smart-422a87fb-cbe4-4bbe-87ed-a3bd5f744b20
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036490461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2036490461
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.2689306765
Short name T94
Test name
Test status
Simulation time 6412207566 ps
CPU time 44.35 seconds
Started May 14 01:36:34 PM PDT 24
Finished May 14 01:37:21 PM PDT 24
Peak memory 277496 kb
Host smart-69474f09-cc9b-43e8-8e29-fd0baf56e955
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689306765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.2689306765
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1585034044
Short name T675
Test name
Test status
Simulation time 731139540 ps
CPU time 11.91 seconds
Started May 14 01:36:33 PM PDT 24
Finished May 14 01:36:48 PM PDT 24
Peak memory 251104 kb
Host smart-6cc8b268-cf54-4e1f-8ee1-8062d3a8b44c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585034044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1585034044
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1465104653
Short name T802
Test name
Test status
Simulation time 67895299 ps
CPU time 1.53 seconds
Started May 14 01:36:34 PM PDT 24
Finished May 14 01:36:38 PM PDT 24
Peak memory 218156 kb
Host smart-a6b8ee6f-2db4-40fc-8c91-84a288b6f03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465104653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1465104653
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2800861149
Short name T801
Test name
Test status
Simulation time 552381698 ps
CPU time 10.44 seconds
Started May 14 01:36:32 PM PDT 24
Finished May 14 01:36:45 PM PDT 24
Peak memory 218088 kb
Host smart-39dc53cf-df1b-47c1-9f30-0f48b0df9a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800861149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2800861149
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2111254718
Short name T47
Test name
Test status
Simulation time 455072279 ps
CPU time 24.22 seconds
Started May 14 01:36:34 PM PDT 24
Finished May 14 01:37:01 PM PDT 24
Peak memory 269012 kb
Host smart-1ce129ca-aa85-4f6e-b852-cf2d6a2870e5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111254718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2111254718
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.454436227
Short name T701
Test name
Test status
Simulation time 2245308822 ps
CPU time 11.82 seconds
Started May 14 01:36:32 PM PDT 24
Finished May 14 01:36:45 PM PDT 24
Peak memory 226292 kb
Host smart-dd29f9f3-a511-44ae-bcc3-96dada403dbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454436227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.454436227
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3859080006
Short name T824
Test name
Test status
Simulation time 344315678 ps
CPU time 14.77 seconds
Started May 14 01:36:34 PM PDT 24
Finished May 14 01:36:52 PM PDT 24
Peak memory 218116 kb
Host smart-5fd0248f-d75a-4e37-8e14-33f3de315d7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859080006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3859080006
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2463398253
Short name T742
Test name
Test status
Simulation time 622553142 ps
CPU time 11.65 seconds
Started May 14 01:36:33 PM PDT 24
Finished May 14 01:36:48 PM PDT 24
Peak memory 218236 kb
Host smart-fe657293-4987-4a95-9243-a579a5e6c272
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463398253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
463398253
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.641292726
Short name T307
Test name
Test status
Simulation time 704024121 ps
CPU time 13.97 seconds
Started May 14 01:36:33 PM PDT 24
Finished May 14 01:36:50 PM PDT 24
Peak memory 218132 kb
Host smart-3f7986c6-af62-4ce5-a5c2-ff09cc153644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641292726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.641292726
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.202685270
Short name T436
Test name
Test status
Simulation time 17214893 ps
CPU time 1.08 seconds
Started May 14 01:36:33 PM PDT 24
Finished May 14 01:36:37 PM PDT 24
Peak memory 212072 kb
Host smart-4b6db17f-01ea-42f9-aa1a-4aafccd7c68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202685270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.202685270
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1462189290
Short name T318
Test name
Test status
Simulation time 2067034413 ps
CPU time 23.69 seconds
Started May 14 01:36:34 PM PDT 24
Finished May 14 01:37:00 PM PDT 24
Peak memory 251136 kb
Host smart-8efff2c3-cd69-4448-9923-b5d154b226e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462189290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1462189290
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.399759820
Short name T629
Test name
Test status
Simulation time 158206393 ps
CPU time 3.43 seconds
Started May 14 01:36:32 PM PDT 24
Finished May 14 01:36:38 PM PDT 24
Peak memory 223968 kb
Host smart-10323104-8351-4290-8396-e0bb2ea16585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399759820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.399759820
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.825386967
Short name T504
Test name
Test status
Simulation time 11575858073 ps
CPU time 233.12 seconds
Started May 14 01:36:35 PM PDT 24
Finished May 14 01:40:30 PM PDT 24
Peak memory 405196 kb
Host smart-f3ff9a8c-e2b7-4bec-9078-a3a23eee3512
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825386967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.825386967
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3595144616
Short name T202
Test name
Test status
Simulation time 135124227 ps
CPU time 0.82 seconds
Started May 14 01:36:32 PM PDT 24
Finished May 14 01:36:33 PM PDT 24
Peak memory 211756 kb
Host smart-ccf74e0f-63ee-475d-8f5a-1b6ab25c1ffa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595144616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3595144616
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2186486243
Short name T386
Test name
Test status
Simulation time 89026932 ps
CPU time 1.24 seconds
Started May 14 01:36:44 PM PDT 24
Finished May 14 01:36:47 PM PDT 24
Peak memory 209740 kb
Host smart-7b3e30f6-059b-4baa-bcf9-9525699cc527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186486243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2186486243
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3443622217
Short name T783
Test name
Test status
Simulation time 1255804888 ps
CPU time 14.15 seconds
Started May 14 01:36:33 PM PDT 24
Finished May 14 01:36:51 PM PDT 24
Peak memory 218180 kb
Host smart-ce7b1a8c-1363-4286-a0c0-a4c7a1c364f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443622217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3443622217
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.3379066996
Short name T31
Test name
Test status
Simulation time 626992195 ps
CPU time 15.92 seconds
Started May 14 01:36:33 PM PDT 24
Finished May 14 01:36:52 PM PDT 24
Peak memory 209708 kb
Host smart-06990976-17cb-4d3e-b2ad-5285a8f2ad84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379066996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.3379066996
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.791923306
Short name T380
Test name
Test status
Simulation time 11382261823 ps
CPU time 40 seconds
Started May 14 01:36:33 PM PDT 24
Finished May 14 01:37:16 PM PDT 24
Peak memory 218932 kb
Host smart-9d87617d-ce4b-45d9-bd23-a7338331fd76
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791923306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.791923306
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.2636785436
Short name T428
Test name
Test status
Simulation time 6277396397 ps
CPU time 31.92 seconds
Started May 14 01:36:34 PM PDT 24
Finished May 14 01:37:09 PM PDT 24
Peak memory 218080 kb
Host smart-fa47fa93-63e0-44ea-a477-6fc1a8f80a46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636785436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.2
636785436
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.22695699
Short name T642
Test name
Test status
Simulation time 261217668 ps
CPU time 2.37 seconds
Started May 14 01:36:31 PM PDT 24
Finished May 14 01:36:34 PM PDT 24
Peak memory 218172 kb
Host smart-98a0d2c7-1311-4dc3-98ae-492eb790d805
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22695699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_p
rog_failure.22695699
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.4011255955
Short name T538
Test name
Test status
Simulation time 1139200516 ps
CPU time 17.62 seconds
Started May 14 01:36:33 PM PDT 24
Finished May 14 01:36:54 PM PDT 24
Peak memory 213428 kb
Host smart-2c81bffe-aee6-4213-a184-1b27279ecc26
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011255955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.4011255955
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.127508954
Short name T655
Test name
Test status
Simulation time 681071459 ps
CPU time 2.06 seconds
Started May 14 01:36:33 PM PDT 24
Finished May 14 01:36:38 PM PDT 24
Peak memory 213040 kb
Host smart-8bdca43c-e7ee-466b-9873-a98b3de67307
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127508954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.127508954
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.3182686682
Short name T368
Test name
Test status
Simulation time 6721336320 ps
CPU time 63.98 seconds
Started May 14 01:36:33 PM PDT 24
Finished May 14 01:37:40 PM PDT 24
Peak memory 273020 kb
Host smart-607493f8-6dc5-4021-b40d-0813deab18c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182686682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.3182686682
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1702292898
Short name T692
Test name
Test status
Simulation time 1233905671 ps
CPU time 11.94 seconds
Started May 14 01:36:35 PM PDT 24
Finished May 14 01:36:50 PM PDT 24
Peak memory 248044 kb
Host smart-1eb3984f-c9ea-467c-a26d-5d1268c3f97b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702292898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1702292898
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.3437261335
Short name T303
Test name
Test status
Simulation time 268276719 ps
CPU time 2.68 seconds
Started May 14 01:36:32 PM PDT 24
Finished May 14 01:36:36 PM PDT 24
Peak memory 218148 kb
Host smart-e3e9270f-b573-4f82-81a9-bb73aa772d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437261335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3437261335
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.3069433605
Short name T169
Test name
Test status
Simulation time 256752540 ps
CPU time 17.68 seconds
Started May 14 01:36:33 PM PDT 24
Finished May 14 01:36:54 PM PDT 24
Peak memory 217860 kb
Host smart-67c3ff5e-0bbc-428b-9a09-ec0a8a3483d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069433605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.3069433605
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2579519578
Short name T48
Test name
Test status
Simulation time 891756203 ps
CPU time 38.52 seconds
Started May 14 01:36:39 PM PDT 24
Finished May 14 01:37:19 PM PDT 24
Peak memory 270772 kb
Host smart-b62eb040-5a20-48e0-82d1-1b38ff4a713f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579519578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2579519578
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1861754543
Short name T360
Test name
Test status
Simulation time 2528692452 ps
CPU time 14.01 seconds
Started May 14 01:36:31 PM PDT 24
Finished May 14 01:36:45 PM PDT 24
Peak memory 226304 kb
Host smart-bd774a24-5b27-4ad8-bd16-a7c33a619b2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861754543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1861754543
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.295883831
Short name T347
Test name
Test status
Simulation time 3309314325 ps
CPU time 15.27 seconds
Started May 14 01:36:35 PM PDT 24
Finished May 14 01:36:53 PM PDT 24
Peak memory 218224 kb
Host smart-ba8c7d9a-9658-401d-b932-286a3882ff04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295883831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.295883831
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.2587777484
Short name T376
Test name
Test status
Simulation time 492416407 ps
CPU time 15.65 seconds
Started May 14 01:36:33 PM PDT 24
Finished May 14 01:36:51 PM PDT 24
Peak memory 218124 kb
Host smart-54f3c055-642c-4d8f-8d15-cd273ada8f60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587777484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.2
587777484
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2866609888
Short name T645
Test name
Test status
Simulation time 438297167 ps
CPU time 10.79 seconds
Started May 14 01:36:33 PM PDT 24
Finished May 14 01:36:46 PM PDT 24
Peak memory 218436 kb
Host smart-15949750-9101-4187-8fa9-7c80bbf80eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866609888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2866609888
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2195874974
Short name T852
Test name
Test status
Simulation time 161570200 ps
CPU time 2.33 seconds
Started May 14 01:36:31 PM PDT 24
Finished May 14 01:36:34 PM PDT 24
Peak memory 214228 kb
Host smart-3efbb910-1133-418a-89ab-7985cceb7d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195874974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2195874974
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2721507637
Short name T560
Test name
Test status
Simulation time 452938496 ps
CPU time 30.86 seconds
Started May 14 01:36:33 PM PDT 24
Finished May 14 01:37:07 PM PDT 24
Peak memory 251048 kb
Host smart-25b30e69-1a55-44d8-b081-c46d622ce4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721507637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2721507637
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3534049083
Short name T829
Test name
Test status
Simulation time 74533855 ps
CPU time 7.62 seconds
Started May 14 01:36:33 PM PDT 24
Finished May 14 01:36:44 PM PDT 24
Peak memory 250512 kb
Host smart-7f2acfd5-de5b-4181-ae56-85ecd90636db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534049083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3534049083
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.4047745094
Short name T773
Test name
Test status
Simulation time 12387669732 ps
CPU time 262.35 seconds
Started May 14 01:36:41 PM PDT 24
Finished May 14 01:41:05 PM PDT 24
Peak memory 512828 kb
Host smart-a9369e54-79df-40b1-a796-77782c0d23bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4047745094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.4047745094
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.927952301
Short name T480
Test name
Test status
Simulation time 44354775 ps
CPU time 0.99 seconds
Started May 14 01:36:34 PM PDT 24
Finished May 14 01:36:38 PM PDT 24
Peak memory 211780 kb
Host smart-e095cd08-44c4-4994-9303-ceedd2c7a10e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927952301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr
l_volatile_unlock_smoke.927952301
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2605976399
Short name T856
Test name
Test status
Simulation time 30316578 ps
CPU time 0.92 seconds
Started May 14 01:37:41 PM PDT 24
Finished May 14 01:37:43 PM PDT 24
Peak memory 209752 kb
Host smart-9b5f4c4c-acd0-410a-a40a-33ac270f667c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605976399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2605976399
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.1590943398
Short name T466
Test name
Test status
Simulation time 542965659 ps
CPU time 11.6 seconds
Started May 14 01:37:38 PM PDT 24
Finished May 14 01:37:50 PM PDT 24
Peak memory 218124 kb
Host smart-b7ebd2eb-0546-4cf2-958d-5adaa1402189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590943398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.1590943398
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.759876077
Short name T550
Test name
Test status
Simulation time 2207821635 ps
CPU time 13.27 seconds
Started May 14 01:37:42 PM PDT 24
Finished May 14 01:37:56 PM PDT 24
Peak memory 209812 kb
Host smart-e51bec4c-d092-4004-870c-5e79776c1bcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759876077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.759876077
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1940062430
Short name T530
Test name
Test status
Simulation time 1483447520 ps
CPU time 25.66 seconds
Started May 14 01:37:39 PM PDT 24
Finished May 14 01:38:05 PM PDT 24
Peak memory 218120 kb
Host smart-5eb7035f-4859-4ce5-b7bf-c6dab83b6487
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940062430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1940062430
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.1862239789
Short name T716
Test name
Test status
Simulation time 549667057 ps
CPU time 8.79 seconds
Started May 14 01:37:41 PM PDT 24
Finished May 14 01:37:51 PM PDT 24
Peak memory 218044 kb
Host smart-759c6750-473d-41c9-a31a-52095a9fd5d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862239789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.1862239789
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1042054186
Short name T628
Test name
Test status
Simulation time 143935157 ps
CPU time 2.51 seconds
Started May 14 01:37:36 PM PDT 24
Finished May 14 01:37:39 PM PDT 24
Peak memory 213104 kb
Host smart-3f8ea03a-12f6-4a0f-9b7c-7fe6524e40c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042054186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1042054186
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1782121068
Short name T274
Test name
Test status
Simulation time 14495218165 ps
CPU time 119.61 seconds
Started May 14 01:37:40 PM PDT 24
Finished May 14 01:39:40 PM PDT 24
Peak memory 284004 kb
Host smart-a8945fd7-daaf-4937-9504-01c489b74040
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782121068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1782121068
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.819356792
Short name T511
Test name
Test status
Simulation time 513854067 ps
CPU time 20.4 seconds
Started May 14 01:37:38 PM PDT 24
Finished May 14 01:37:59 PM PDT 24
Peak memory 247912 kb
Host smart-87e4b1fe-21a6-46f1-8544-12f2e907f337
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819356792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.819356792
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.1139071444
Short name T349
Test name
Test status
Simulation time 78429180 ps
CPU time 1.7 seconds
Started May 14 01:37:41 PM PDT 24
Finished May 14 01:37:44 PM PDT 24
Peak memory 218148 kb
Host smart-81c56f6e-e026-4ece-bef2-147ff208a30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139071444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.1139071444
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.157165180
Short name T869
Test name
Test status
Simulation time 509995281 ps
CPU time 15.56 seconds
Started May 14 01:37:39 PM PDT 24
Finished May 14 01:37:55 PM PDT 24
Peak memory 225940 kb
Host smart-88ef464f-bb1b-4d2c-a318-80067fb9d8c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157165180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.157165180
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1466120150
Short name T410
Test name
Test status
Simulation time 896852134 ps
CPU time 13.19 seconds
Started May 14 01:37:39 PM PDT 24
Finished May 14 01:37:53 PM PDT 24
Peak memory 218088 kb
Host smart-f4ae63c7-1879-4cf2-abb8-06e39175abac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466120150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1466120150
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1176736116
Short name T13
Test name
Test status
Simulation time 3168841075 ps
CPU time 8.63 seconds
Started May 14 01:37:39 PM PDT 24
Finished May 14 01:37:48 PM PDT 24
Peak memory 218280 kb
Host smart-951385bb-5c32-43ab-bd15-a36285009bb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176736116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1176736116
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.4200284534
Short name T521
Test name
Test status
Simulation time 3036894174 ps
CPU time 6.16 seconds
Started May 14 01:37:38 PM PDT 24
Finished May 14 01:37:45 PM PDT 24
Peak memory 218284 kb
Host smart-9cb76776-711f-4481-a202-e03936f37f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200284534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.4200284534
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.725719343
Short name T52
Test name
Test status
Simulation time 59030914 ps
CPU time 3.16 seconds
Started May 14 01:37:32 PM PDT 24
Finished May 14 01:37:36 PM PDT 24
Peak memory 213896 kb
Host smart-109bac49-a130-4288-baa5-568c09e272a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725719343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.725719343
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2456968757
Short name T408
Test name
Test status
Simulation time 257049144 ps
CPU time 19.89 seconds
Started May 14 01:37:33 PM PDT 24
Finished May 14 01:37:54 PM PDT 24
Peak memory 251076 kb
Host smart-a48306a7-1a56-44a9-bf91-c44060f7a277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456968757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2456968757
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.682012196
Short name T454
Test name
Test status
Simulation time 317711222 ps
CPU time 7.48 seconds
Started May 14 01:37:40 PM PDT 24
Finished May 14 01:37:48 PM PDT 24
Peak memory 247596 kb
Host smart-173c8ac0-7e5c-4121-9f3c-958183368317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682012196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.682012196
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2281602909
Short name T738
Test name
Test status
Simulation time 4499144583 ps
CPU time 36.92 seconds
Started May 14 01:37:38 PM PDT 24
Finished May 14 01:38:16 PM PDT 24
Peak memory 217988 kb
Host smart-98ef758a-5dff-463b-a8c5-fb14f33c3237
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281602909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2281602909
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.1397155196
Short name T96
Test name
Test status
Simulation time 59639828743 ps
CPU time 1112.6 seconds
Started May 14 01:37:41 PM PDT 24
Finished May 14 01:56:14 PM PDT 24
Peak memory 284032 kb
Host smart-35becddf-14d4-4145-baca-71c195bebb40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1397155196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.1397155196
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1779353952
Short name T744
Test name
Test status
Simulation time 37374698 ps
CPU time 0.81 seconds
Started May 14 01:37:30 PM PDT 24
Finished May 14 01:37:33 PM PDT 24
Peak memory 211764 kb
Host smart-3160f852-c032-4ee7-8fe3-afe4ad02eae9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779353952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1779353952
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2133280428
Short name T80
Test name
Test status
Simulation time 18903091 ps
CPU time 0.93 seconds
Started May 14 01:37:47 PM PDT 24
Finished May 14 01:37:49 PM PDT 24
Peak memory 209712 kb
Host smart-812e69bd-128e-4682-a971-241c9fd66618
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133280428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2133280428
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.174269281
Short name T310
Test name
Test status
Simulation time 1223722692 ps
CPU time 10.09 seconds
Started May 14 01:37:41 PM PDT 24
Finished May 14 01:37:51 PM PDT 24
Peak memory 218180 kb
Host smart-13a49c2d-54d6-45e0-842d-cb5822e9ac67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174269281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.174269281
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2876159611
Short name T420
Test name
Test status
Simulation time 1792522196 ps
CPU time 5.25 seconds
Started May 14 01:37:47 PM PDT 24
Finished May 14 01:37:53 PM PDT 24
Peak memory 217220 kb
Host smart-3ca92c93-1211-4e10-96fd-eff79795a1ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876159611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2876159611
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1207839194
Short name T172
Test name
Test status
Simulation time 13350496773 ps
CPU time 21.86 seconds
Started May 14 01:37:48 PM PDT 24
Finished May 14 01:38:11 PM PDT 24
Peak memory 218244 kb
Host smart-277e7fce-7935-4f7f-b9fe-f21244cc0b16
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207839194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1207839194
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3476905673
Short name T696
Test name
Test status
Simulation time 551840871 ps
CPU time 5.34 seconds
Started May 14 01:37:46 PM PDT 24
Finished May 14 01:37:52 PM PDT 24
Peak memory 218132 kb
Host smart-117b2788-dc7b-498a-b5e7-0cbc2d9b7f70
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476905673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.3476905673
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.3308437288
Short name T535
Test name
Test status
Simulation time 424469057 ps
CPU time 11.77 seconds
Started May 14 01:37:41 PM PDT 24
Finished May 14 01:37:54 PM PDT 24
Peak memory 213844 kb
Host smart-3c827a1d-d3dc-455e-9ce0-b84126e10249
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308437288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.3308437288
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3404132084
Short name T520
Test name
Test status
Simulation time 959075027 ps
CPU time 50.84 seconds
Started May 14 01:37:46 PM PDT 24
Finished May 14 01:38:38 PM PDT 24
Peak memory 251160 kb
Host smart-9c0acc51-a06a-489f-a154-375e1195e81c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404132084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3404132084
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.911750766
Short name T248
Test name
Test status
Simulation time 496338900 ps
CPU time 14.88 seconds
Started May 14 01:37:45 PM PDT 24
Finished May 14 01:38:01 PM PDT 24
Peak memory 251020 kb
Host smart-8570ea76-1d7d-454b-b2fc-08fb22ae619e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911750766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_
jtag_state_post_trans.911750766
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1137511238
Short name T233
Test name
Test status
Simulation time 107217122 ps
CPU time 2.43 seconds
Started May 14 01:37:41 PM PDT 24
Finished May 14 01:37:44 PM PDT 24
Peak memory 218028 kb
Host smart-5156550e-9deb-4798-a995-867fc8bcd053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137511238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1137511238
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2718816650
Short name T417
Test name
Test status
Simulation time 970256391 ps
CPU time 13.57 seconds
Started May 14 01:37:47 PM PDT 24
Finished May 14 01:38:02 PM PDT 24
Peak memory 218080 kb
Host smart-8a2bf161-0253-402e-aaa0-39c52b3e38bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718816650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2718816650
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.3286918383
Short name T823
Test name
Test status
Simulation time 3049074128 ps
CPU time 16.23 seconds
Started May 14 01:37:46 PM PDT 24
Finished May 14 01:38:04 PM PDT 24
Peak memory 218324 kb
Host smart-7ffb2e1f-29e4-4a8c-b46b-e63e1a444536
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286918383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.3286918383
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2217395505
Short name T228
Test name
Test status
Simulation time 854115166 ps
CPU time 6.31 seconds
Started May 14 01:37:47 PM PDT 24
Finished May 14 01:37:54 PM PDT 24
Peak memory 218208 kb
Host smart-5d7fcbcc-c15b-40c0-85e6-68315bc199a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217395505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2217395505
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.906549033
Short name T89
Test name
Test status
Simulation time 111425782 ps
CPU time 2.14 seconds
Started May 14 01:37:37 PM PDT 24
Finished May 14 01:37:40 PM PDT 24
Peak memory 214040 kb
Host smart-f4a8dfe2-4300-4fc3-8338-e35076e814b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906549033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.906549033
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.938451511
Short name T865
Test name
Test status
Simulation time 458393137 ps
CPU time 33.27 seconds
Started May 14 01:37:39 PM PDT 24
Finished May 14 01:38:13 PM PDT 24
Peak memory 251076 kb
Host smart-3522b136-bf57-4d0a-9240-ad7843d5ea05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938451511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.938451511
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.2733495732
Short name T138
Test name
Test status
Simulation time 142873227 ps
CPU time 7.52 seconds
Started May 14 01:37:42 PM PDT 24
Finished May 14 01:37:50 PM PDT 24
Peak memory 247272 kb
Host smart-3d163bb8-ed23-4da8-82d1-875d78fc8d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733495732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.2733495732
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.4082013176
Short name T754
Test name
Test status
Simulation time 14030355848 ps
CPU time 124.88 seconds
Started May 14 01:37:43 PM PDT 24
Finished May 14 01:39:48 PM PDT 24
Peak memory 279164 kb
Host smart-6800b9ce-f4e1-49d7-80ec-f3cf492edd8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082013176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.4082013176
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.2906973560
Short name T102
Test name
Test status
Simulation time 381839892224 ps
CPU time 1927.7 seconds
Started May 14 01:37:45 PM PDT 24
Finished May 14 02:09:54 PM PDT 24
Peak memory 368000 kb
Host smart-f9961d9a-1578-402a-b5b2-529d82beb337
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2906973560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.2906973560
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2771958756
Short name T570
Test name
Test status
Simulation time 18634262 ps
CPU time 0.97 seconds
Started May 14 01:37:41 PM PDT 24
Finished May 14 01:37:43 PM PDT 24
Peak memory 211772 kb
Host smart-c5afe118-adf1-4675-9521-2830ecb1a738
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771958756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2771958756
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1272402768
Short name T522
Test name
Test status
Simulation time 22690778 ps
CPU time 0.99 seconds
Started May 14 01:37:56 PM PDT 24
Finished May 14 01:37:58 PM PDT 24
Peak memory 209664 kb
Host smart-a6449947-9bf5-414b-ba10-a2fe3507bb4b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272402768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1272402768
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1846557289
Short name T221
Test name
Test status
Simulation time 344561784 ps
CPU time 11.55 seconds
Started May 14 01:37:48 PM PDT 24
Finished May 14 01:38:01 PM PDT 24
Peak memory 218192 kb
Host smart-6237794c-b7bd-46c6-ba92-8caee2d5af56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846557289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1846557289
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.3551542384
Short name T608
Test name
Test status
Simulation time 87513742 ps
CPU time 1.23 seconds
Started May 14 01:37:54 PM PDT 24
Finished May 14 01:37:57 PM PDT 24
Peak memory 209724 kb
Host smart-95228df1-d376-4df0-9428-e0cfe6be615b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551542384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.3551542384
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.4210694908
Short name T839
Test name
Test status
Simulation time 1578685260 ps
CPU time 52.32 seconds
Started May 14 01:37:56 PM PDT 24
Finished May 14 01:38:49 PM PDT 24
Peak memory 219104 kb
Host smart-11322c5e-7b1f-4a23-bae5-3c2379395ac5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210694908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.4210694908
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2966140880
Short name T457
Test name
Test status
Simulation time 1292009089 ps
CPU time 6.99 seconds
Started May 14 01:37:48 PM PDT 24
Finished May 14 01:37:56 PM PDT 24
Peak memory 218140 kb
Host smart-7d928fe8-5576-4433-ae2c-c89b43589dc2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966140880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2966140880
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.974786365
Short name T668
Test name
Test status
Simulation time 138827825 ps
CPU time 2.59 seconds
Started May 14 01:37:48 PM PDT 24
Finished May 14 01:37:52 PM PDT 24
Peak memory 213180 kb
Host smart-aa07792c-b1c0-48bf-a5ae-4a89621f3962
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974786365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke.
974786365
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2724984739
Short name T683
Test name
Test status
Simulation time 1042882861 ps
CPU time 50.41 seconds
Started May 14 01:37:47 PM PDT 24
Finished May 14 01:38:39 PM PDT 24
Peak memory 251064 kb
Host smart-7c343853-433f-48f0-a7c2-6ff72562904c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724984739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2724984739
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3167160355
Short name T835
Test name
Test status
Simulation time 3159711777 ps
CPU time 15.31 seconds
Started May 14 01:37:47 PM PDT 24
Finished May 14 01:38:04 PM PDT 24
Peak memory 251132 kb
Host smart-2ef11a01-2a01-4ab5-9172-fa089fb5ced0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167160355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3167160355
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2396807343
Short name T647
Test name
Test status
Simulation time 102878204 ps
CPU time 3.42 seconds
Started May 14 01:37:46 PM PDT 24
Finished May 14 01:37:50 PM PDT 24
Peak memory 218180 kb
Host smart-eb733580-645b-4ec0-90d3-e6f77a86f5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396807343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2396807343
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2186282767
Short name T382
Test name
Test status
Simulation time 756929435 ps
CPU time 17.56 seconds
Started May 14 01:37:54 PM PDT 24
Finished May 14 01:38:13 PM PDT 24
Peak memory 219332 kb
Host smart-c6753635-3593-438c-8e48-802c4bb95361
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186282767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2186282767
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.645875616
Short name T478
Test name
Test status
Simulation time 1316640779 ps
CPU time 12.23 seconds
Started May 14 01:37:54 PM PDT 24
Finished May 14 01:38:07 PM PDT 24
Peak memory 218104 kb
Host smart-e7ff8390-48cc-4ac0-9f40-f527fd90b7eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645875616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.645875616
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3719574730
Short name T402
Test name
Test status
Simulation time 443900722 ps
CPU time 11.69 seconds
Started May 14 01:37:58 PM PDT 24
Finished May 14 01:38:11 PM PDT 24
Peak memory 218164 kb
Host smart-b8d3e0c3-24c8-4b31-8803-9b606788b89c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719574730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3719574730
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2676852948
Short name T760
Test name
Test status
Simulation time 567304423 ps
CPU time 11.93 seconds
Started May 14 01:37:45 PM PDT 24
Finished May 14 01:37:58 PM PDT 24
Peak memory 218228 kb
Host smart-29a49864-60f2-4d21-9fcc-870e58496ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676852948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2676852948
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2034855510
Short name T553
Test name
Test status
Simulation time 156311397 ps
CPU time 3.17 seconds
Started May 14 01:37:47 PM PDT 24
Finished May 14 01:37:51 PM PDT 24
Peak memory 214812 kb
Host smart-b9ec0e79-7622-44dd-b79c-c8f77079fe6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034855510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2034855510
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.3671149180
Short name T510
Test name
Test status
Simulation time 254743348 ps
CPU time 28.66 seconds
Started May 14 01:37:46 PM PDT 24
Finished May 14 01:38:15 PM PDT 24
Peak memory 249892 kb
Host smart-c335a103-a3dc-43ba-96e4-c4cd1f56e35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671149180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3671149180
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.3111860161
Short name T412
Test name
Test status
Simulation time 97475651 ps
CPU time 7.21 seconds
Started May 14 01:37:47 PM PDT 24
Finished May 14 01:37:56 PM PDT 24
Peak memory 250736 kb
Host smart-87649e13-217a-4462-a8a9-e3b77511dba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111860161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.3111860161
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.3305024495
Short name T257
Test name
Test status
Simulation time 2582676780 ps
CPU time 74.44 seconds
Started May 14 01:37:54 PM PDT 24
Finished May 14 01:39:10 PM PDT 24
Peak memory 267436 kb
Host smart-2a05fe21-41d1-4d78-a978-b53a93054739
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305024495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.3305024495
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2963855515
Short name T618
Test name
Test status
Simulation time 30567232 ps
CPU time 0.91 seconds
Started May 14 01:37:45 PM PDT 24
Finished May 14 01:37:47 PM PDT 24
Peak memory 211732 kb
Host smart-e7021b6a-4817-412d-826e-a31c497e1d8b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963855515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.2963855515
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.1704638454
Short name T241
Test name
Test status
Simulation time 20417007 ps
CPU time 1.25 seconds
Started May 14 01:38:02 PM PDT 24
Finished May 14 01:38:05 PM PDT 24
Peak memory 209804 kb
Host smart-e4d40a34-22be-44ff-a002-e6dd5e8a7573
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704638454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1704638454
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3802121152
Short name T294
Test name
Test status
Simulation time 1072312263 ps
CPU time 13.18 seconds
Started May 14 01:37:55 PM PDT 24
Finished May 14 01:38:09 PM PDT 24
Peak memory 218096 kb
Host smart-59c1d0fd-b87e-4f8c-b08f-ba8e8a380092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802121152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3802121152
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2263804422
Short name T455
Test name
Test status
Simulation time 1093957184 ps
CPU time 27.23 seconds
Started May 14 01:37:54 PM PDT 24
Finished May 14 01:38:23 PM PDT 24
Peak memory 209752 kb
Host smart-e7a0e5f7-64fc-42ca-934b-ce40dea62a5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263804422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2263804422
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.1362856678
Short name T384
Test name
Test status
Simulation time 3216708891 ps
CPU time 88.8 seconds
Started May 14 01:37:58 PM PDT 24
Finished May 14 01:39:28 PM PDT 24
Peak memory 220824 kb
Host smart-5f12ee08-5f4d-467f-9bc6-a37483cc7fd9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362856678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.1362856678
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1825446412
Short name T698
Test name
Test status
Simulation time 1873901920 ps
CPU time 5.33 seconds
Started May 14 01:37:54 PM PDT 24
Finished May 14 01:38:00 PM PDT 24
Peak memory 218164 kb
Host smart-37385075-744b-458f-bd78-4e8239d6beb4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825446412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1825446412
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.2248356017
Short name T740
Test name
Test status
Simulation time 14029511855 ps
CPU time 101.15 seconds
Started May 14 01:37:54 PM PDT 24
Finished May 14 01:39:36 PM PDT 24
Peak memory 271104 kb
Host smart-a8691dd0-6ce5-4f6f-8337-c9b20fde0f58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248356017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.2248356017
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.1082028906
Short name T167
Test name
Test status
Simulation time 340930373 ps
CPU time 15.82 seconds
Started May 14 01:37:54 PM PDT 24
Finished May 14 01:38:11 PM PDT 24
Peak memory 251060 kb
Host smart-f953b784-41ca-44af-bf25-a30c504317f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082028906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.1082028906
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.956697977
Short name T791
Test name
Test status
Simulation time 352819513 ps
CPU time 4.19 seconds
Started May 14 01:37:54 PM PDT 24
Finished May 14 01:38:00 PM PDT 24
Peak memory 218240 kb
Host smart-a9e0e777-6ac5-4020-8a6e-4fc12bc2c0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956697977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.956697977
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.678973959
Short name T243
Test name
Test status
Simulation time 447045911 ps
CPU time 19.77 seconds
Started May 14 01:37:56 PM PDT 24
Finished May 14 01:38:17 PM PDT 24
Peak memory 225816 kb
Host smart-676e569a-8cab-42c2-90a5-d71479882daf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678973959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.678973959
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2565984234
Short name T23
Test name
Test status
Simulation time 849835344 ps
CPU time 13.59 seconds
Started May 14 01:38:02 PM PDT 24
Finished May 14 01:38:16 PM PDT 24
Peak memory 218188 kb
Host smart-fe5c3a07-d6d3-4dbe-a18a-2f57ba957ad8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565984234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2565984234
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.3646436344
Short name T676
Test name
Test status
Simulation time 280585146 ps
CPU time 10.85 seconds
Started May 14 01:37:54 PM PDT 24
Finished May 14 01:38:06 PM PDT 24
Peak memory 218212 kb
Host smart-8e85dbcc-7fa5-4720-8cde-bfa7534d13bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646436344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
3646436344
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2935297669
Short name T367
Test name
Test status
Simulation time 255310088 ps
CPU time 11.09 seconds
Started May 14 01:37:56 PM PDT 24
Finished May 14 01:38:08 PM PDT 24
Peak memory 218212 kb
Host smart-a39ad52a-b681-41bd-93e7-9c5aa3ed625b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935297669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2935297669
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1826610330
Short name T392
Test name
Test status
Simulation time 68792033 ps
CPU time 2.07 seconds
Started May 14 01:37:55 PM PDT 24
Finished May 14 01:37:59 PM PDT 24
Peak memory 214052 kb
Host smart-afcddf46-b506-4e01-9076-30b2093ed8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826610330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1826610330
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2128373586
Short name T235
Test name
Test status
Simulation time 825756338 ps
CPU time 25.52 seconds
Started May 14 01:37:55 PM PDT 24
Finished May 14 01:38:22 PM PDT 24
Peak memory 246196 kb
Host smart-833f42bc-9e81-491e-8420-5c0e636872c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128373586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2128373586
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1999780859
Short name T250
Test name
Test status
Simulation time 390525671 ps
CPU time 8.21 seconds
Started May 14 01:37:53 PM PDT 24
Finished May 14 01:38:02 PM PDT 24
Peak memory 251104 kb
Host smart-1c395f3f-43c7-4f20-92db-b75e849a8e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999780859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1999780859
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3344423153
Short name T612
Test name
Test status
Simulation time 5673561687 ps
CPU time 240.76 seconds
Started May 14 01:37:59 PM PDT 24
Finished May 14 01:42:01 PM PDT 24
Peak memory 421376 kb
Host smart-aa753557-a718-486d-a137-48b2d97b4e6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344423153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3344423153
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3808652580
Short name T157
Test name
Test status
Simulation time 13563593 ps
CPU time 0.94 seconds
Started May 14 01:37:54 PM PDT 24
Finished May 14 01:37:56 PM PDT 24
Peak memory 211804 kb
Host smart-d99ca3ac-6ba9-4b1e-992e-9be5713f6ce9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808652580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3808652580
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3877535479
Short name T734
Test name
Test status
Simulation time 37060723 ps
CPU time 1.05 seconds
Started May 14 01:38:03 PM PDT 24
Finished May 14 01:38:06 PM PDT 24
Peak memory 209736 kb
Host smart-04f4d48a-9c75-4de0-b126-62574ede7174
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877535479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3877535479
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.353117772
Short name T814
Test name
Test status
Simulation time 1469209567 ps
CPU time 12.58 seconds
Started May 14 01:38:03 PM PDT 24
Finished May 14 01:38:16 PM PDT 24
Peak memory 218212 kb
Host smart-ef43601a-e22d-4802-b571-c7cfa15850d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353117772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.353117772
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2888324396
Short name T262
Test name
Test status
Simulation time 832646927 ps
CPU time 4.44 seconds
Started May 14 01:38:03 PM PDT 24
Finished May 14 01:38:09 PM PDT 24
Peak memory 217316 kb
Host smart-e8fe5e7a-cf0a-4375-bdf8-0f070fd683aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888324396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2888324396
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1796806014
Short name T37
Test name
Test status
Simulation time 3019289668 ps
CPU time 25.16 seconds
Started May 14 01:38:03 PM PDT 24
Finished May 14 01:38:29 PM PDT 24
Peak memory 219212 kb
Host smart-ae1a60e3-9ab1-4e9b-b972-6dacedb8681f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796806014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1796806014
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2983232798
Short name T679
Test name
Test status
Simulation time 378514792 ps
CPU time 10.3 seconds
Started May 14 01:38:00 PM PDT 24
Finished May 14 01:38:11 PM PDT 24
Peak memory 218180 kb
Host smart-25242937-2175-411f-b4d7-7997437b5039
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983232798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2983232798
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2055153289
Short name T151
Test name
Test status
Simulation time 427452695 ps
CPU time 2.31 seconds
Started May 14 01:38:02 PM PDT 24
Finished May 14 01:38:05 PM PDT 24
Peak memory 213248 kb
Host smart-8c70a429-57e5-4547-9388-870932a12fa6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055153289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2055153289
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2777388969
Short name T361
Test name
Test status
Simulation time 12617354423 ps
CPU time 101.29 seconds
Started May 14 01:38:04 PM PDT 24
Finished May 14 01:39:46 PM PDT 24
Peak memory 283756 kb
Host smart-56de586f-026e-40db-ae30-f4d0dfca37e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777388969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2777388969
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2723044845
Short name T603
Test name
Test status
Simulation time 1547182111 ps
CPU time 9.64 seconds
Started May 14 01:38:02 PM PDT 24
Finished May 14 01:38:13 PM PDT 24
Peak memory 249452 kb
Host smart-981c2c30-a396-4f9c-bcb1-0555f7ee14f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723044845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2723044845
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3707348726
Short name T807
Test name
Test status
Simulation time 244801998 ps
CPU time 2.66 seconds
Started May 14 01:38:04 PM PDT 24
Finished May 14 01:38:08 PM PDT 24
Peak memory 218020 kb
Host smart-0cff3647-ad64-4b59-9562-a34562964b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707348726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3707348726
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2259910697
Short name T397
Test name
Test status
Simulation time 4464153751 ps
CPU time 10.4 seconds
Started May 14 01:38:01 PM PDT 24
Finished May 14 01:38:13 PM PDT 24
Peak memory 226340 kb
Host smart-0483f888-9325-4105-824c-1ded79ecb650
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259910697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2259910697
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.999984578
Short name T326
Test name
Test status
Simulation time 184731688 ps
CPU time 6.66 seconds
Started May 14 01:38:02 PM PDT 24
Finished May 14 01:38:10 PM PDT 24
Peak memory 218212 kb
Host smart-278d9c44-912c-4658-9326-0f809c6e7545
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999984578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.999984578
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.935179689
Short name T472
Test name
Test status
Simulation time 378513389 ps
CPU time 9.31 seconds
Started May 14 01:38:02 PM PDT 24
Finished May 14 01:38:12 PM PDT 24
Peak memory 218192 kb
Host smart-d123a618-aa49-4d63-a752-d4ed76797ab4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935179689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.935179689
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.1552936561
Short name T818
Test name
Test status
Simulation time 245658017 ps
CPU time 7.86 seconds
Started May 14 01:38:02 PM PDT 24
Finished May 14 01:38:11 PM PDT 24
Peak memory 218224 kb
Host smart-6e680a72-bb97-4e9b-9220-92af5f4874a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552936561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.1552936561
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.1380651215
Short name T624
Test name
Test status
Simulation time 24314237 ps
CPU time 1.91 seconds
Started May 14 01:38:01 PM PDT 24
Finished May 14 01:38:04 PM PDT 24
Peak memory 214016 kb
Host smart-14e077eb-e990-4972-af3d-7bf5b1ded3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380651215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.1380651215
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.4283609722
Short name T297
Test name
Test status
Simulation time 1380531454 ps
CPU time 23.15 seconds
Started May 14 01:38:01 PM PDT 24
Finished May 14 01:38:25 PM PDT 24
Peak memory 251084 kb
Host smart-507f9953-470a-47c7-a526-9f56b624b31e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283609722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.4283609722
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.250925489
Short name T864
Test name
Test status
Simulation time 154224184 ps
CPU time 8.62 seconds
Started May 14 01:38:04 PM PDT 24
Finished May 14 01:38:14 PM PDT 24
Peak memory 248688 kb
Host smart-a4773b00-aa94-48af-8c24-68cd76b7f86c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250925489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.250925489
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1191075473
Short name T870
Test name
Test status
Simulation time 19775511429 ps
CPU time 171.77 seconds
Started May 14 01:38:01 PM PDT 24
Finished May 14 01:40:54 PM PDT 24
Peak memory 284068 kb
Host smart-645961ff-b2a9-42ce-8c5a-a967d4b54e44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191075473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1191075473
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3252920069
Short name T441
Test name
Test status
Simulation time 65155188 ps
CPU time 1.12 seconds
Started May 14 01:38:02 PM PDT 24
Finished May 14 01:38:04 PM PDT 24
Peak memory 212804 kb
Host smart-90bb7dc7-b11d-4ccc-b4fc-c976616631fa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252920069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3252920069
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2985872561
Short name T837
Test name
Test status
Simulation time 46604024 ps
CPU time 1.04 seconds
Started May 14 01:38:11 PM PDT 24
Finished May 14 01:38:13 PM PDT 24
Peak memory 209664 kb
Host smart-fbda1efc-01f0-4b9c-890f-471b3d5a970e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985872561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2985872561
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.4172331610
Short name T853
Test name
Test status
Simulation time 612823845 ps
CPU time 16.07 seconds
Started May 14 01:38:12 PM PDT 24
Finished May 14 01:38:29 PM PDT 24
Peak memory 218148 kb
Host smart-4ea5d4e1-eb51-4a66-b166-35d90b02f248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172331610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.4172331610
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1073577326
Short name T30
Test name
Test status
Simulation time 1111948881 ps
CPU time 7 seconds
Started May 14 01:38:10 PM PDT 24
Finished May 14 01:38:19 PM PDT 24
Peak memory 217292 kb
Host smart-108a3319-885f-4c49-9eac-8f7b9989bf95
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073577326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1073577326
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2655983707
Short name T264
Test name
Test status
Simulation time 1849372193 ps
CPU time 55.55 seconds
Started May 14 01:38:11 PM PDT 24
Finished May 14 01:39:08 PM PDT 24
Peak memory 218248 kb
Host smart-fd61fea1-1bcc-4509-92b4-8e0fc84f7b7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655983707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2655983707
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3305024498
Short name T517
Test name
Test status
Simulation time 5846413954 ps
CPU time 9.01 seconds
Started May 14 01:38:11 PM PDT 24
Finished May 14 01:38:21 PM PDT 24
Peak memory 218204 kb
Host smart-ed9aff2f-2362-4c70-b270-c27c71389976
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305024498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3305024498
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1233795355
Short name T401
Test name
Test status
Simulation time 85443034 ps
CPU time 1.44 seconds
Started May 14 01:38:14 PM PDT 24
Finished May 14 01:38:16 PM PDT 24
Peak memory 212732 kb
Host smart-9a1be01c-cb9a-4a9a-b0af-ddc413e74853
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233795355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1233795355
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2047296226
Short name T635
Test name
Test status
Simulation time 1123538535 ps
CPU time 9.58 seconds
Started May 14 01:38:10 PM PDT 24
Finished May 14 01:38:21 PM PDT 24
Peak memory 251104 kb
Host smart-a6f174bf-cccd-4191-82f6-fb36ceacee92
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047296226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2047296226
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1856491896
Short name T481
Test name
Test status
Simulation time 223812894 ps
CPU time 2.66 seconds
Started May 14 01:38:12 PM PDT 24
Finished May 14 01:38:16 PM PDT 24
Peak memory 218244 kb
Host smart-3d279b81-c767-4dd7-bd47-7a1b83137333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856491896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1856491896
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1329536687
Short name T453
Test name
Test status
Simulation time 293707615 ps
CPU time 14.45 seconds
Started May 14 01:38:10 PM PDT 24
Finished May 14 01:38:26 PM PDT 24
Peak memory 226264 kb
Host smart-db718ba1-6b88-41b6-89f1-33f2ab6c1769
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329536687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1329536687
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3150456318
Short name T581
Test name
Test status
Simulation time 609588750 ps
CPU time 10.99 seconds
Started May 14 01:38:12 PM PDT 24
Finished May 14 01:38:25 PM PDT 24
Peak memory 218104 kb
Host smart-6c2116aa-e5de-43d4-8b02-2963f1f5f792
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150456318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3150456318
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.677385345
Short name T615
Test name
Test status
Simulation time 232626800 ps
CPU time 6.32 seconds
Started May 14 01:38:13 PM PDT 24
Finished May 14 01:38:20 PM PDT 24
Peak memory 218196 kb
Host smart-d1df3678-3617-49f6-bb59-e5a844c977b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677385345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.677385345
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2428724682
Short name T653
Test name
Test status
Simulation time 800490637 ps
CPU time 14.79 seconds
Started May 14 01:38:12 PM PDT 24
Finished May 14 01:38:28 PM PDT 24
Peak memory 218208 kb
Host smart-f87b45cd-147b-4e13-817a-a8d5dfccd473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428724682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2428724682
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.4208439877
Short name T533
Test name
Test status
Simulation time 71768341 ps
CPU time 1.86 seconds
Started May 14 01:38:02 PM PDT 24
Finished May 14 01:38:05 PM PDT 24
Peak memory 213776 kb
Host smart-b3871315-bf63-4ca0-948a-766ace574e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208439877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.4208439877
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1703934337
Short name T311
Test name
Test status
Simulation time 1279731045 ps
CPU time 26.79 seconds
Started May 14 01:38:12 PM PDT 24
Finished May 14 01:38:40 PM PDT 24
Peak memory 251144 kb
Host smart-a4daf667-d37e-42e0-809b-9880bdda01a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703934337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1703934337
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1112592952
Short name T438
Test name
Test status
Simulation time 106999010 ps
CPU time 7.64 seconds
Started May 14 01:38:11 PM PDT 24
Finished May 14 01:38:20 PM PDT 24
Peak memory 242936 kb
Host smart-8eaa3e33-5dda-469e-8b3d-260e4022edb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112592952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1112592952
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3568252929
Short name T71
Test name
Test status
Simulation time 6582024967 ps
CPU time 33.96 seconds
Started May 14 01:38:12 PM PDT 24
Finished May 14 01:38:47 PM PDT 24
Peak memory 267592 kb
Host smart-53262dc2-3567-4a98-8f66-f553ee8efdec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568252929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3568252929
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3427289603
Short name T678
Test name
Test status
Simulation time 42024611 ps
CPU time 0.89 seconds
Started May 14 01:38:15 PM PDT 24
Finished May 14 01:38:17 PM PDT 24
Peak memory 211736 kb
Host smart-70c4b80d-fd92-4b08-a4fe-ce17a5fa6978
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427289603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3427289603
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2102362122
Short name T748
Test name
Test status
Simulation time 19209381 ps
CPU time 1.21 seconds
Started May 14 01:38:19 PM PDT 24
Finished May 14 01:38:22 PM PDT 24
Peak memory 209708 kb
Host smart-52d2a762-d9c7-48fe-b6e9-ec90dbbc79ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102362122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2102362122
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3160488223
Short name T139
Test name
Test status
Simulation time 1197942901 ps
CPU time 13.37 seconds
Started May 14 01:38:10 PM PDT 24
Finished May 14 01:38:24 PM PDT 24
Peak memory 218124 kb
Host smart-4a502f83-884b-4c3e-a723-6b2ff3b08f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160488223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3160488223
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1214536818
Short name T632
Test name
Test status
Simulation time 1154848106 ps
CPU time 4.06 seconds
Started May 14 01:38:20 PM PDT 24
Finished May 14 01:38:26 PM PDT 24
Peak memory 209764 kb
Host smart-9fdbf037-2fae-493e-a29d-7e61d841839a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214536818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1214536818
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1678257812
Short name T499
Test name
Test status
Simulation time 5083762690 ps
CPU time 39.63 seconds
Started May 14 01:38:19 PM PDT 24
Finished May 14 01:39:00 PM PDT 24
Peak memory 218540 kb
Host smart-b49b4504-6f0d-41ef-97dd-c498fbb8902c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678257812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1678257812
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.821822303
Short name T715
Test name
Test status
Simulation time 375487738 ps
CPU time 10.84 seconds
Started May 14 01:38:19 PM PDT 24
Finished May 14 01:38:31 PM PDT 24
Peak memory 218192 kb
Host smart-5cb104da-1d81-43a5-9c16-bc5a879a9324
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821822303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag
_prog_failure.821822303
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2019958839
Short name T328
Test name
Test status
Simulation time 296607130 ps
CPU time 2.69 seconds
Started May 14 01:38:11 PM PDT 24
Finished May 14 01:38:15 PM PDT 24
Peak memory 213160 kb
Host smart-9a4ef9e1-be70-421b-aae7-f77f312f9cc2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019958839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2019958839
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2898490349
Short name T751
Test name
Test status
Simulation time 4930220114 ps
CPU time 54.61 seconds
Started May 14 01:38:11 PM PDT 24
Finished May 14 01:39:07 PM PDT 24
Peak memory 252744 kb
Host smart-77bad1a7-5825-4e71-a8bb-e899587fa537
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898490349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2898490349
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3787003333
Short name T547
Test name
Test status
Simulation time 468112615 ps
CPU time 14.79 seconds
Started May 14 01:38:11 PM PDT 24
Finished May 14 01:38:27 PM PDT 24
Peak memory 224196 kb
Host smart-b4c568cc-7944-45b6-b637-58d246fae2cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3787003333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3787003333
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1352685793
Short name T657
Test name
Test status
Simulation time 32914306 ps
CPU time 2.36 seconds
Started May 14 01:38:12 PM PDT 24
Finished May 14 01:38:16 PM PDT 24
Peak memory 218148 kb
Host smart-7fc29f61-ab9f-40ff-8f60-adfc13db3820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352685793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1352685793
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.1577611348
Short name T658
Test name
Test status
Simulation time 2160399317 ps
CPU time 14.96 seconds
Started May 14 01:38:20 PM PDT 24
Finished May 14 01:38:37 PM PDT 24
Peak memory 226340 kb
Host smart-56131e23-b539-4039-a505-4973f0937230
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577611348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.1577611348
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.3216445069
Short name T284
Test name
Test status
Simulation time 835001666 ps
CPU time 12.63 seconds
Started May 14 01:38:26 PM PDT 24
Finished May 14 01:38:39 PM PDT 24
Peak memory 218192 kb
Host smart-c3418336-6aaf-453e-98c5-245a7866dd17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216445069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.3216445069
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.3757602364
Short name T16
Test name
Test status
Simulation time 915509311 ps
CPU time 6.92 seconds
Started May 14 01:38:23 PM PDT 24
Finished May 14 01:38:30 PM PDT 24
Peak memory 218160 kb
Host smart-6439492d-6136-4d14-ac1d-0b644d05281d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757602364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
3757602364
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.2571790073
Short name T761
Test name
Test status
Simulation time 3491863734 ps
CPU time 13.58 seconds
Started May 14 01:38:14 PM PDT 24
Finished May 14 01:38:28 PM PDT 24
Peak memory 218248 kb
Host smart-83cacee4-501b-44d0-a964-6e00fa481379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571790073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.2571790073
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3284107386
Short name T486
Test name
Test status
Simulation time 100325341 ps
CPU time 1.52 seconds
Started May 14 01:38:13 PM PDT 24
Finished May 14 01:38:15 PM PDT 24
Peak memory 218008 kb
Host smart-872b040c-124c-44fa-a74f-c77fa9e05c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284107386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3284107386
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.302332246
Short name T686
Test name
Test status
Simulation time 806700122 ps
CPU time 21.09 seconds
Started May 14 01:38:10 PM PDT 24
Finished May 14 01:38:33 PM PDT 24
Peak memory 251116 kb
Host smart-5e975345-f71c-400e-9e65-e3faa3182b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302332246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.302332246
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.1640678619
Short name T720
Test name
Test status
Simulation time 183818721 ps
CPU time 6.47 seconds
Started May 14 01:38:11 PM PDT 24
Finished May 14 01:38:19 PM PDT 24
Peak memory 251008 kb
Host smart-07e8e2a8-78b7-40e0-9092-daf5c678a20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640678619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1640678619
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2853574107
Short name T793
Test name
Test status
Simulation time 21065770292 ps
CPU time 69.24 seconds
Started May 14 01:38:19 PM PDT 24
Finished May 14 01:39:29 PM PDT 24
Peak memory 265440 kb
Host smart-e7a3b81a-f064-4c02-9a12-af7b08d87349
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853574107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2853574107
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2103978344
Short name T203
Test name
Test status
Simulation time 48209342 ps
CPU time 1.02 seconds
Started May 14 01:38:11 PM PDT 24
Finished May 14 01:38:13 PM PDT 24
Peak memory 213156 kb
Host smart-dc349193-8b4c-4cb9-a750-41ee0394bf81
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103978344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.2103978344
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.591080081
Short name T549
Test name
Test status
Simulation time 17542575 ps
CPU time 1.13 seconds
Started May 14 01:38:29 PM PDT 24
Finished May 14 01:38:32 PM PDT 24
Peak memory 209696 kb
Host smart-40049360-5621-40d8-b51d-c4ed78027cb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591080081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.591080081
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2782744022
Short name T610
Test name
Test status
Simulation time 790606635 ps
CPU time 13.53 seconds
Started May 14 01:38:21 PM PDT 24
Finished May 14 01:38:35 PM PDT 24
Peak memory 218132 kb
Host smart-184b3b10-eb76-4e7a-b966-e2dc2cc8c8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782744022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2782744022
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.4027474
Short name T418
Test name
Test status
Simulation time 2477984399 ps
CPU time 25.56 seconds
Started May 14 01:38:20 PM PDT 24
Finished May 14 01:38:47 PM PDT 24
Peak memory 217544 kb
Host smart-153129fb-a7c5-409b-b4ff-dc07d305e108
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.4027474
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3018793833
Short name T17
Test name
Test status
Simulation time 3495750921 ps
CPU time 50.85 seconds
Started May 14 01:38:22 PM PDT 24
Finished May 14 01:39:14 PM PDT 24
Peak memory 219160 kb
Host smart-dd7c06e5-11c3-4a74-b4b9-5f7d798efd9e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018793833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3018793833
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2140747468
Short name T477
Test name
Test status
Simulation time 1525188982 ps
CPU time 7.54 seconds
Started May 14 01:38:20 PM PDT 24
Finished May 14 01:38:28 PM PDT 24
Peak memory 218020 kb
Host smart-a966a2bd-6e42-4758-895a-424d8b57ba7d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140747468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2140747468
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.1129793913
Short name T830
Test name
Test status
Simulation time 376681724 ps
CPU time 4.82 seconds
Started May 14 01:38:20 PM PDT 24
Finished May 14 01:38:26 PM PDT 24
Peak memory 213380 kb
Host smart-19d63d26-b7d1-41c0-a370-c76d315c2fcf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129793913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.1129793913
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1997003845
Short name T574
Test name
Test status
Simulation time 11633352143 ps
CPU time 48.11 seconds
Started May 14 01:38:21 PM PDT 24
Finished May 14 01:39:10 PM PDT 24
Peak memory 251140 kb
Host smart-d797c629-f436-4ba0-83f4-e1cb1ce71dc7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997003845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1997003845
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2701673730
Short name T846
Test name
Test status
Simulation time 1219400813 ps
CPU time 14.71 seconds
Started May 14 01:38:21 PM PDT 24
Finished May 14 01:38:37 PM PDT 24
Peak memory 250260 kb
Host smart-1da12c06-106b-477b-b939-fc62de7cb826
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701673730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2701673730
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3436756924
Short name T452
Test name
Test status
Simulation time 85661153 ps
CPU time 4.2 seconds
Started May 14 01:38:19 PM PDT 24
Finished May 14 01:38:24 PM PDT 24
Peak memory 218188 kb
Host smart-427915ca-45e5-4b14-a11a-cd7b1a973d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436756924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3436756924
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2807568806
Short name T269
Test name
Test status
Simulation time 2004772409 ps
CPU time 13.81 seconds
Started May 14 01:38:19 PM PDT 24
Finished May 14 01:38:33 PM PDT 24
Peak memory 218128 kb
Host smart-6101df38-e374-41a9-a260-45a2c9b1aafc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807568806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2807568806
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1096477147
Short name T750
Test name
Test status
Simulation time 378331674 ps
CPU time 13.64 seconds
Started May 14 01:38:20 PM PDT 24
Finished May 14 01:38:36 PM PDT 24
Peak memory 218164 kb
Host smart-6160f27f-e6e8-4583-9d29-564c32b23104
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096477147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
1096477147
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.238719703
Short name T451
Test name
Test status
Simulation time 1159393492 ps
CPU time 7.43 seconds
Started May 14 01:38:20 PM PDT 24
Finished May 14 01:38:29 PM PDT 24
Peak memory 224840 kb
Host smart-dc8c0c01-1752-4eb6-b073-883ebbceba85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238719703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.238719703
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.612111943
Short name T443
Test name
Test status
Simulation time 112338255 ps
CPU time 2.58 seconds
Started May 14 01:38:22 PM PDT 24
Finished May 14 01:38:25 PM PDT 24
Peak memory 214488 kb
Host smart-f2fcf0b5-98cc-47d9-8e34-8b2185fbb851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612111943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.612111943
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.3880877912
Short name T324
Test name
Test status
Simulation time 274826209 ps
CPU time 33.33 seconds
Started May 14 01:38:21 PM PDT 24
Finished May 14 01:38:55 PM PDT 24
Peak memory 250820 kb
Host smart-2b86cbd1-0d52-48bd-af41-f518d5a41def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880877912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.3880877912
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2561338638
Short name T840
Test name
Test status
Simulation time 176888073 ps
CPU time 6.78 seconds
Started May 14 01:38:20 PM PDT 24
Finished May 14 01:38:28 PM PDT 24
Peak memory 246868 kb
Host smart-86663a2f-8de4-4be2-98d1-4ee4b92446c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561338638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2561338638
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.1866619346
Short name T525
Test name
Test status
Simulation time 23067418965 ps
CPU time 189.8 seconds
Started May 14 01:38:21 PM PDT 24
Finished May 14 01:41:32 PM PDT 24
Peak memory 316124 kb
Host smart-72271d59-41d8-4431-99e7-12142a4916e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866619346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.1866619346
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.1310900060
Short name T842
Test name
Test status
Simulation time 22258223 ps
CPU time 1.57 seconds
Started May 14 01:38:21 PM PDT 24
Finished May 14 01:38:24 PM PDT 24
Peak memory 213132 kb
Host smart-8d5dde78-528c-45fe-b31a-2afbb092722a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310900060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.1310900060
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1114973564
Short name T276
Test name
Test status
Simulation time 109323040 ps
CPU time 1.17 seconds
Started May 14 01:38:35 PM PDT 24
Finished May 14 01:38:37 PM PDT 24
Peak memory 209728 kb
Host smart-dfb2c167-c1a7-4699-a0cc-121423599223
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114973564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1114973564
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.536043516
Short name T506
Test name
Test status
Simulation time 2466672318 ps
CPU time 11.36 seconds
Started May 14 01:38:31 PM PDT 24
Finished May 14 01:38:43 PM PDT 24
Peak memory 218164 kb
Host smart-8a524482-e484-4cd5-92d7-a93edd8e956f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536043516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.536043516
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.2289720054
Short name T749
Test name
Test status
Simulation time 3045151537 ps
CPU time 14.64 seconds
Started May 14 01:38:28 PM PDT 24
Finished May 14 01:38:44 PM PDT 24
Peak memory 209780 kb
Host smart-982ae91d-5708-4063-9553-980b899fb752
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289720054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2289720054
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.4184619579
Short name T822
Test name
Test status
Simulation time 7783259378 ps
CPU time 28.68 seconds
Started May 14 01:38:28 PM PDT 24
Finished May 14 01:38:58 PM PDT 24
Peak memory 218752 kb
Host smart-d487257f-37fc-4386-856c-9d0f397490cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184619579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.4184619579
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.4160314669
Short name T672
Test name
Test status
Simulation time 1647978855 ps
CPU time 6.18 seconds
Started May 14 01:38:31 PM PDT 24
Finished May 14 01:38:38 PM PDT 24
Peak memory 218224 kb
Host smart-9215a048-357c-4fcb-a158-01b248da0482
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160314669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.4160314669
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.488877414
Short name T239
Test name
Test status
Simulation time 386064425 ps
CPU time 3.94 seconds
Started May 14 01:38:29 PM PDT 24
Finished May 14 01:38:34 PM PDT 24
Peak memory 213808 kb
Host smart-b7af0b67-a338-43c5-9f7a-319ef6de5af0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488877414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
488877414
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1061445930
Short name T502
Test name
Test status
Simulation time 2981498562 ps
CPU time 65.05 seconds
Started May 14 01:38:28 PM PDT 24
Finished May 14 01:39:34 PM PDT 24
Peak memory 276088 kb
Host smart-2804567a-8fae-4939-afca-9a6b0553fc48
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061445930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1061445930
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3355930199
Short name T336
Test name
Test status
Simulation time 499163021 ps
CPU time 21.24 seconds
Started May 14 01:38:32 PM PDT 24
Finished May 14 01:38:54 PM PDT 24
Peak memory 251344 kb
Host smart-2e777f3c-7672-41b0-8636-a8d722f765ae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355930199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3355930199
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3487419993
Short name T564
Test name
Test status
Simulation time 69096973 ps
CPU time 2.55 seconds
Started May 14 01:38:29 PM PDT 24
Finished May 14 01:38:33 PM PDT 24
Peak memory 218124 kb
Host smart-0c8fd2af-5b97-4daa-b9ea-65fb23908d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487419993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3487419993
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2908833042
Short name T806
Test name
Test status
Simulation time 1279533433 ps
CPU time 13.5 seconds
Started May 14 01:38:29 PM PDT 24
Finished May 14 01:38:44 PM PDT 24
Peak memory 226232 kb
Host smart-ed15041b-0aa6-440e-b344-efb11e91a112
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908833042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2908833042
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3274631778
Short name T462
Test name
Test status
Simulation time 755913821 ps
CPU time 14.14 seconds
Started May 14 01:38:31 PM PDT 24
Finished May 14 01:38:46 PM PDT 24
Peak memory 218152 kb
Host smart-bcc05fd1-2df1-4746-9102-3895ce2b9c49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274631778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3274631778
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2166539297
Short name T320
Test name
Test status
Simulation time 751647729 ps
CPU time 13.33 seconds
Started May 14 01:38:32 PM PDT 24
Finished May 14 01:38:46 PM PDT 24
Peak memory 218244 kb
Host smart-8f2d4b80-f8ce-4239-9281-d4a1dd8f18ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166539297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2166539297
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.215267192
Short name T741
Test name
Test status
Simulation time 2370423449 ps
CPU time 7.63 seconds
Started May 14 01:38:32 PM PDT 24
Finished May 14 01:38:40 PM PDT 24
Peak memory 218144 kb
Host smart-9d0d0130-fc89-4333-980d-fb9e33a9b0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215267192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.215267192
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3143783134
Short name T370
Test name
Test status
Simulation time 652034522 ps
CPU time 3.33 seconds
Started May 14 01:38:29 PM PDT 24
Finished May 14 01:38:34 PM PDT 24
Peak memory 214224 kb
Host smart-38bb4bbd-ba02-474a-9f00-d61ec204b611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143783134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3143783134
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.532672015
Short name T390
Test name
Test status
Simulation time 244319114 ps
CPU time 19.68 seconds
Started May 14 01:38:28 PM PDT 24
Finished May 14 01:38:49 PM PDT 24
Peak memory 251108 kb
Host smart-4f8fc934-95b7-4056-949c-32caccb8b8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532672015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.532672015
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.918894016
Short name T66
Test name
Test status
Simulation time 264798671 ps
CPU time 3.61 seconds
Started May 14 01:38:33 PM PDT 24
Finished May 14 01:38:37 PM PDT 24
Peak memory 226784 kb
Host smart-9b9736ce-bce7-41d8-8799-9dbb04da35b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918894016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.918894016
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.201553719
Short name T56
Test name
Test status
Simulation time 8743930621 ps
CPU time 51.75 seconds
Started May 14 01:38:29 PM PDT 24
Finished May 14 01:39:22 PM PDT 24
Peak memory 226324 kb
Host smart-cc6ede0d-545d-47ff-97ee-eb07fd70e879
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201553719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.201553719
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.297010468
Short name T134
Test name
Test status
Simulation time 70329953043 ps
CPU time 1154.53 seconds
Started May 14 01:38:31 PM PDT 24
Finished May 14 01:57:46 PM PDT 24
Peak memory 447808 kb
Host smart-6c091aad-4e0e-4cc5-965f-4fc9d5b00302
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=297010468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.297010468
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2734037719
Short name T379
Test name
Test status
Simulation time 14073087 ps
CPU time 1.13 seconds
Started May 14 01:38:40 PM PDT 24
Finished May 14 01:38:43 PM PDT 24
Peak memory 211820 kb
Host smart-bbcd06d6-7cda-4b59-a9b8-61afab88bd88
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734037719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2734037719
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2198536720
Short name T804
Test name
Test status
Simulation time 47519919 ps
CPU time 1.09 seconds
Started May 14 01:38:40 PM PDT 24
Finished May 14 01:38:41 PM PDT 24
Peak memory 209760 kb
Host smart-bbb28d73-1a81-4151-9323-496f186cf35d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198536720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2198536720
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1465859853
Short name T416
Test name
Test status
Simulation time 282578097 ps
CPU time 11.49 seconds
Started May 14 01:38:34 PM PDT 24
Finished May 14 01:38:47 PM PDT 24
Peak memory 218148 kb
Host smart-4636df81-915c-48d9-bd21-9a4bcdcbc1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465859853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1465859853
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.545221701
Short name T179
Test name
Test status
Simulation time 1460657241 ps
CPU time 3.61 seconds
Started May 14 01:38:40 PM PDT 24
Finished May 14 01:38:45 PM PDT 24
Peak memory 217212 kb
Host smart-bad9d5a3-43f6-44a6-88d1-4c158efd92b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545221701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.545221701
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2477424305
Short name T601
Test name
Test status
Simulation time 9192472022 ps
CPU time 33.21 seconds
Started May 14 01:38:32 PM PDT 24
Finished May 14 01:39:06 PM PDT 24
Peak memory 218288 kb
Host smart-b263f6d6-03f8-42ab-8881-26511b1c2e89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477424305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2477424305
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1760163625
Short name T487
Test name
Test status
Simulation time 679688362 ps
CPU time 20.05 seconds
Started May 14 01:38:34 PM PDT 24
Finished May 14 01:38:55 PM PDT 24
Peak memory 218148 kb
Host smart-2ea0f702-31f2-4e81-bb01-f8f4d266c2cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760163625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1760163625
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.3444893408
Short name T74
Test name
Test status
Simulation time 1120196687 ps
CPU time 8.19 seconds
Started May 14 01:38:40 PM PDT 24
Finished May 14 01:38:49 PM PDT 24
Peak memory 213824 kb
Host smart-6057c42d-ff2c-4d5e-83bd-be56e74979f5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444893408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.3444893408
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1558203119
Short name T664
Test name
Test status
Simulation time 1635242102 ps
CPU time 39.93 seconds
Started May 14 01:38:40 PM PDT 24
Finished May 14 01:39:21 PM PDT 24
Peak memory 276032 kb
Host smart-f05efa6d-3efa-4bf7-83cd-f43e3552b84d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558203119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1558203119
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.922621393
Short name T319
Test name
Test status
Simulation time 283531088 ps
CPU time 9.98 seconds
Started May 14 01:38:29 PM PDT 24
Finished May 14 01:38:40 PM PDT 24
Peak memory 245284 kb
Host smart-703b0e6b-dbac-4f9e-a202-204a12dba788
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922621393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.922621393
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3990300862
Short name T291
Test name
Test status
Simulation time 63737534 ps
CPU time 3.29 seconds
Started May 14 01:38:30 PM PDT 24
Finished May 14 01:38:35 PM PDT 24
Peak memory 218152 kb
Host smart-a3362602-46ce-4679-b9c9-cc963eb3dd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990300862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3990300862
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.1808981534
Short name T251
Test name
Test status
Simulation time 643929967 ps
CPU time 12.77 seconds
Started May 14 01:38:40 PM PDT 24
Finished May 14 01:38:54 PM PDT 24
Peak memory 226172 kb
Host smart-6a592bb2-2d9c-419e-a949-ca62555b8b0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808981534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.1808981534
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2398023227
Short name T282
Test name
Test status
Simulation time 757788337 ps
CPU time 17.05 seconds
Started May 14 01:38:40 PM PDT 24
Finished May 14 01:38:58 PM PDT 24
Peak memory 218196 kb
Host smart-9c15aa93-b3de-48e7-ab63-d9e81251c2f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398023227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2398023227
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.4044517267
Short name T237
Test name
Test status
Simulation time 1323496013 ps
CPU time 10.07 seconds
Started May 14 01:38:29 PM PDT 24
Finished May 14 01:38:41 PM PDT 24
Peak memory 218032 kb
Host smart-f4748d8e-9183-4a01-9034-5a1cdafc0dee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044517267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
4044517267
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.692068420
Short name T45
Test name
Test status
Simulation time 800142032 ps
CPU time 9.47 seconds
Started May 14 01:38:30 PM PDT 24
Finished May 14 01:38:41 PM PDT 24
Peak memory 226236 kb
Host smart-66c8c8a3-a6dc-4b24-aaf3-2b6654b8954f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692068420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.692068420
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1401559249
Short name T394
Test name
Test status
Simulation time 57274843 ps
CPU time 1.59 seconds
Started May 14 01:38:30 PM PDT 24
Finished May 14 01:38:33 PM PDT 24
Peak memory 218376 kb
Host smart-674d46e4-61b6-4910-8039-edf507359d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401559249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1401559249
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1118089852
Short name T1
Test name
Test status
Simulation time 308770866 ps
CPU time 30.27 seconds
Started May 14 01:38:29 PM PDT 24
Finished May 14 01:39:01 PM PDT 24
Peak memory 251028 kb
Host smart-8effa36c-d7e6-4a08-a6c0-20b951b4a150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118089852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1118089852
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.1067362097
Short name T141
Test name
Test status
Simulation time 387014658 ps
CPU time 6.18 seconds
Started May 14 01:38:32 PM PDT 24
Finished May 14 01:38:39 PM PDT 24
Peak memory 244960 kb
Host smart-f1f51760-215f-4ae9-a4d5-d14594d881bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067362097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.1067362097
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.971098957
Short name T843
Test name
Test status
Simulation time 12517186486 ps
CPU time 57.55 seconds
Started May 14 01:38:29 PM PDT 24
Finished May 14 01:39:28 PM PDT 24
Peak memory 239236 kb
Host smart-a0dd149e-3095-485f-a6df-9247ca96bf81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971098957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.971098957
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3122909263
Short name T650
Test name
Test status
Simulation time 39111578 ps
CPU time 0.82 seconds
Started May 14 01:38:29 PM PDT 24
Finished May 14 01:38:32 PM PDT 24
Peak memory 211740 kb
Host smart-0dc55bf1-bc01-4e3c-83c6-2ed19c07be2d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122909263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3122909263
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3158411993
Short name T559
Test name
Test status
Simulation time 69029002 ps
CPU time 0.94 seconds
Started May 14 01:36:40 PM PDT 24
Finished May 14 01:36:42 PM PDT 24
Peak memory 209704 kb
Host smart-01c67cec-a156-4895-ac3f-1a6f22ea3403
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158411993 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3158411993
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.732556712
Short name T249
Test name
Test status
Simulation time 954928702 ps
CPU time 15.37 seconds
Started May 14 01:36:39 PM PDT 24
Finished May 14 01:36:56 PM PDT 24
Peak memory 218032 kb
Host smart-81958461-41ce-48ef-845a-5ad58ad815f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732556712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.732556712
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.783096084
Short name T181
Test name
Test status
Simulation time 1530142112 ps
CPU time 4.4 seconds
Started May 14 01:36:42 PM PDT 24
Finished May 14 01:36:48 PM PDT 24
Peak memory 209728 kb
Host smart-79802658-320b-4b1f-93e3-2efb0c240bb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783096084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.783096084
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.3206489177
Short name T794
Test name
Test status
Simulation time 2071507061 ps
CPU time 48.6 seconds
Started May 14 01:36:39 PM PDT 24
Finished May 14 01:37:29 PM PDT 24
Peak memory 218000 kb
Host smart-fa784145-4257-4175-afd7-cd51aa9e590f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206489177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.3206489177
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.191952632
Short name T743
Test name
Test status
Simulation time 1096777331 ps
CPU time 3.41 seconds
Started May 14 01:36:41 PM PDT 24
Finished May 14 01:36:46 PM PDT 24
Peak memory 217320 kb
Host smart-3d72bb29-e281-497b-83e9-2e189c849835
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191952632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.191952632
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2631440501
Short name T770
Test name
Test status
Simulation time 4706897110 ps
CPU time 10.26 seconds
Started May 14 01:36:41 PM PDT 24
Finished May 14 01:36:53 PM PDT 24
Peak memory 218200 kb
Host smart-dd9e864e-212f-4263-87ac-532b6de11a61
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631440501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2631440501
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3177589687
Short name T25
Test name
Test status
Simulation time 5066660129 ps
CPU time 30.45 seconds
Started May 14 01:36:42 PM PDT 24
Finished May 14 01:37:14 PM PDT 24
Peak memory 214060 kb
Host smart-8331ce5b-5b56-41be-a425-335f72acd7e9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177589687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.3177589687
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.274475665
Short name T699
Test name
Test status
Simulation time 427148458 ps
CPU time 6.18 seconds
Started May 14 01:36:40 PM PDT 24
Finished May 14 01:36:47 PM PDT 24
Peak memory 213732 kb
Host smart-dd4ab377-8ce1-4925-b9b7-1b8ffb83103d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274475665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.274475665
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.1919768451
Short name T348
Test name
Test status
Simulation time 2653843748 ps
CPU time 52.37 seconds
Started May 14 01:36:41 PM PDT 24
Finished May 14 01:37:35 PM PDT 24
Peak memory 251196 kb
Host smart-0a8714e5-19e9-43e1-bcfa-8bcf5f3b717b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919768451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.1919768451
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.318879486
Short name T214
Test name
Test status
Simulation time 822596479 ps
CPU time 10.93 seconds
Started May 14 01:36:44 PM PDT 24
Finished May 14 01:36:56 PM PDT 24
Peak memory 247928 kb
Host smart-5e5ecbe8-65c9-4396-bacc-b84bc699a7ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318879486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_state_post_trans.318879486
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2971668951
Short name T513
Test name
Test status
Simulation time 178116379 ps
CPU time 3.35 seconds
Started May 14 01:36:42 PM PDT 24
Finished May 14 01:36:48 PM PDT 24
Peak memory 218212 kb
Host smart-079bafee-be65-41bb-8240-eabba83f1170
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971668951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2971668951
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.532854799
Short name T62
Test name
Test status
Simulation time 1344696195 ps
CPU time 16.15 seconds
Started May 14 01:36:43 PM PDT 24
Finished May 14 01:37:01 PM PDT 24
Peak memory 218140 kb
Host smart-18915219-5bb7-44dd-86b2-fd749b99c8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532854799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.532854799
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2618793039
Short name T799
Test name
Test status
Simulation time 232226687 ps
CPU time 8.91 seconds
Started May 14 01:36:39 PM PDT 24
Finished May 14 01:36:49 PM PDT 24
Peak memory 219104 kb
Host smart-a7491766-bc8d-490d-af75-37cf4351af9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618793039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2618793039
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1752609307
Short name T372
Test name
Test status
Simulation time 1713734545 ps
CPU time 15.39 seconds
Started May 14 01:36:42 PM PDT 24
Finished May 14 01:37:00 PM PDT 24
Peak memory 218152 kb
Host smart-00bc5059-d730-41f3-967c-0810ce57f7e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752609307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1752609307
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3617526549
Short name T163
Test name
Test status
Simulation time 402748617 ps
CPU time 9.52 seconds
Started May 14 01:36:42 PM PDT 24
Finished May 14 01:36:53 PM PDT 24
Peak memory 218140 kb
Host smart-475dbf0d-52be-42fe-a04c-32c7f18b8815
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617526549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
617526549
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.681819843
Short name T860
Test name
Test status
Simulation time 263275460 ps
CPU time 8 seconds
Started May 14 01:36:38 PM PDT 24
Finished May 14 01:36:48 PM PDT 24
Peak memory 225212 kb
Host smart-ee9f8512-167c-4b72-8ceb-d0afdc006bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681819843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.681819843
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.2154378701
Short name T710
Test name
Test status
Simulation time 35856792 ps
CPU time 1.26 seconds
Started May 14 01:36:41 PM PDT 24
Finished May 14 01:36:44 PM PDT 24
Peak memory 213552 kb
Host smart-c972a930-dd67-43ee-b21a-b1ff21f5168f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154378701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.2154378701
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.459530781
Short name T220
Test name
Test status
Simulation time 252786081 ps
CPU time 21.3 seconds
Started May 14 01:36:42 PM PDT 24
Finished May 14 01:37:05 PM PDT 24
Peak memory 251108 kb
Host smart-be34ca1a-205b-4aef-89cf-1d014eba67dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459530781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.459530781
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.251317858
Short name T548
Test name
Test status
Simulation time 113504873 ps
CPU time 8.25 seconds
Started May 14 01:36:44 PM PDT 24
Finished May 14 01:36:53 PM PDT 24
Peak memory 251072 kb
Host smart-1c842c90-875f-4e1d-a0fc-2ab052611d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251317858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.251317858
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1201249405
Short name T558
Test name
Test status
Simulation time 26230922929 ps
CPU time 209.06 seconds
Started May 14 01:36:45 PM PDT 24
Finished May 14 01:40:15 PM PDT 24
Peak memory 272292 kb
Host smart-eb630165-2243-4f3a-85c9-2403014cda5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201249405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1201249405
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.4269272625
Short name T447
Test name
Test status
Simulation time 18785768 ps
CPU time 1.12 seconds
Started May 14 01:36:39 PM PDT 24
Finished May 14 01:36:41 PM PDT 24
Peak memory 212896 kb
Host smart-a92a94b6-ace9-46f7-81b3-de624d96a322
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269272625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.4269272625
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1045171430
Short name T434
Test name
Test status
Simulation time 22794548 ps
CPU time 0.99 seconds
Started May 14 01:38:45 PM PDT 24
Finished May 14 01:38:46 PM PDT 24
Peak memory 209748 kb
Host smart-f539322b-652e-461c-b35e-5aebab8876f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045171430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1045171430
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3014174998
Short name T226
Test name
Test status
Simulation time 993242415 ps
CPU time 14.9 seconds
Started May 14 01:38:42 PM PDT 24
Finished May 14 01:38:59 PM PDT 24
Peak memory 218148 kb
Host smart-46de8e3c-62fa-44f3-976a-ca5baba3d7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014174998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3014174998
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3893084688
Short name T774
Test name
Test status
Simulation time 1747186513 ps
CPU time 5.73 seconds
Started May 14 01:38:41 PM PDT 24
Finished May 14 01:38:47 PM PDT 24
Peak memory 209732 kb
Host smart-28524615-cc84-4198-b523-03fc4b94f553
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893084688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3893084688
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1110245008
Short name T164
Test name
Test status
Simulation time 67516316 ps
CPU time 3.84 seconds
Started May 14 01:38:43 PM PDT 24
Finished May 14 01:38:48 PM PDT 24
Peak memory 218148 kb
Host smart-37b23719-5cc9-42c1-b5c1-500e38cfff8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110245008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1110245008
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.3569387789
Short name T607
Test name
Test status
Simulation time 530160034 ps
CPU time 13.76 seconds
Started May 14 01:38:41 PM PDT 24
Finished May 14 01:38:55 PM PDT 24
Peak memory 218172 kb
Host smart-7a1770b3-9d34-4e60-9da3-890d35d4bb7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569387789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3569387789
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.2546506003
Short name T859
Test name
Test status
Simulation time 198437921 ps
CPU time 8.64 seconds
Started May 14 01:38:43 PM PDT 24
Finished May 14 01:38:53 PM PDT 24
Peak memory 218052 kb
Host smart-c1588840-7e68-4850-9a0d-c63f12d380b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546506003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.2546506003
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1563078607
Short name T756
Test name
Test status
Simulation time 776871681 ps
CPU time 14.56 seconds
Started May 14 01:38:43 PM PDT 24
Finished May 14 01:38:59 PM PDT 24
Peak memory 218248 kb
Host smart-be361eaf-8b3a-465e-844a-3485a4f055de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563078607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1563078607
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1214657600
Short name T611
Test name
Test status
Simulation time 1888665526 ps
CPU time 9.04 seconds
Started May 14 01:38:41 PM PDT 24
Finished May 14 01:38:51 PM PDT 24
Peak memory 218192 kb
Host smart-0caa9c9c-8afc-4cd0-a90c-35542928536a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214657600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1214657600
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1306052373
Short name T70
Test name
Test status
Simulation time 663697630 ps
CPU time 11.46 seconds
Started May 14 01:38:43 PM PDT 24
Finished May 14 01:38:56 PM PDT 24
Peak memory 214456 kb
Host smart-ae9f18cc-47ff-45fa-9bab-13fc4a5ceb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306052373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1306052373
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.1165143525
Short name T484
Test name
Test status
Simulation time 173828282 ps
CPU time 20.03 seconds
Started May 14 01:38:42 PM PDT 24
Finished May 14 01:39:03 PM PDT 24
Peak memory 245176 kb
Host smart-ec9e0820-b797-4c57-9af7-8f608bd2b607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165143525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.1165143525
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1554096615
Short name T142
Test name
Test status
Simulation time 87514258 ps
CPU time 9.79 seconds
Started May 14 01:38:41 PM PDT 24
Finished May 14 01:38:52 PM PDT 24
Peak memory 251092 kb
Host smart-067ca39a-5990-4142-9c3c-11063ed58aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554096615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1554096615
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3678166695
Short name T527
Test name
Test status
Simulation time 10002908109 ps
CPU time 357.23 seconds
Started May 14 01:38:42 PM PDT 24
Finished May 14 01:44:40 PM PDT 24
Peak memory 227684 kb
Host smart-acc254cd-c8f3-445d-8641-b345da42d6c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678166695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3678166695
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.373730148
Short name T432
Test name
Test status
Simulation time 14516372 ps
CPU time 1.1 seconds
Started May 14 01:38:41 PM PDT 24
Finished May 14 01:38:44 PM PDT 24
Peak memory 211788 kb
Host smart-185befee-7452-419c-be91-29eacc15b026
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373730148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ct
rl_volatile_unlock_smoke.373730148
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.372138783
Short name T633
Test name
Test status
Simulation time 19048924 ps
CPU time 0.98 seconds
Started May 14 01:38:42 PM PDT 24
Finished May 14 01:38:44 PM PDT 24
Peak memory 209624 kb
Host smart-2c2635d2-d877-4693-ae54-36f4c00d3879
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372138783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.372138783
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.192629114
Short name T776
Test name
Test status
Simulation time 276697624 ps
CPU time 11.95 seconds
Started May 14 01:38:43 PM PDT 24
Finished May 14 01:38:56 PM PDT 24
Peak memory 218156 kb
Host smart-2b4ae705-3f2d-4e77-80b2-28e50e2c3922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192629114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.192629114
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.307318088
Short name T32
Test name
Test status
Simulation time 2005338938 ps
CPU time 4.83 seconds
Started May 14 01:38:41 PM PDT 24
Finished May 14 01:38:47 PM PDT 24
Peak memory 209740 kb
Host smart-085655fd-957f-4682-ad12-098a0f12e97b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307318088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.307318088
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1963603075
Short name T755
Test name
Test status
Simulation time 80725405 ps
CPU time 2.65 seconds
Started May 14 01:38:42 PM PDT 24
Finished May 14 01:38:46 PM PDT 24
Peak memory 218152 kb
Host smart-7f24a431-7da5-4930-b1bf-02c0d4887494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963603075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1963603075
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3354339424
Short name T563
Test name
Test status
Simulation time 1571686951 ps
CPU time 16.46 seconds
Started May 14 01:38:41 PM PDT 24
Finished May 14 01:38:59 PM PDT 24
Peak memory 226204 kb
Host smart-98bf3436-2099-4896-9d5c-1a8f88e856dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354339424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3354339424
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.3805849731
Short name T459
Test name
Test status
Simulation time 2109491037 ps
CPU time 13.1 seconds
Started May 14 01:38:43 PM PDT 24
Finished May 14 01:38:57 PM PDT 24
Peak memory 218188 kb
Host smart-e0361a32-2bc0-46cc-8792-e94891b589e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805849731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.3805849731
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.2354832464
Short name T727
Test name
Test status
Simulation time 1062933155 ps
CPU time 11.03 seconds
Started May 14 01:38:42 PM PDT 24
Finished May 14 01:38:54 PM PDT 24
Peak memory 218224 kb
Host smart-117ed021-6be7-4acd-8144-49c9c3d8d44a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354832464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
2354832464
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.288965011
Short name T393
Test name
Test status
Simulation time 887052937 ps
CPU time 7.71 seconds
Started May 14 01:38:42 PM PDT 24
Finished May 14 01:38:51 PM PDT 24
Peak memory 218200 kb
Host smart-bf22641b-8128-4a4b-aeec-42cad3af9744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288965011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.288965011
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1528370736
Short name T562
Test name
Test status
Simulation time 25402360 ps
CPU time 1.82 seconds
Started May 14 01:38:40 PM PDT 24
Finished May 14 01:38:43 PM PDT 24
Peak memory 213696 kb
Host smart-42395609-c99f-4962-9845-6cabce548cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528370736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1528370736
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.780620248
Short name T528
Test name
Test status
Simulation time 552252540 ps
CPU time 32.01 seconds
Started May 14 01:38:41 PM PDT 24
Finished May 14 01:39:14 PM PDT 24
Peak memory 248580 kb
Host smart-73476a43-057b-47bf-8dbc-cc064bd778d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780620248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.780620248
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1657741959
Short name T571
Test name
Test status
Simulation time 207265059 ps
CPU time 7.03 seconds
Started May 14 01:38:43 PM PDT 24
Finished May 14 01:38:51 PM PDT 24
Peak memory 244376 kb
Host smart-6550eb64-bf1b-419e-b3f5-f6057eeeba57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657741959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1657741959
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3601207790
Short name T723
Test name
Test status
Simulation time 5358918268 ps
CPU time 41.92 seconds
Started May 14 01:38:41 PM PDT 24
Finished May 14 01:39:24 PM PDT 24
Peak memory 251200 kb
Host smart-1b16e85f-0dd0-447e-ae6d-f19651c8540a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601207790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3601207790
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.124984929
Short name T833
Test name
Test status
Simulation time 33633200 ps
CPU time 0.87 seconds
Started May 14 01:38:43 PM PDT 24
Finished May 14 01:38:45 PM PDT 24
Peak memory 211820 kb
Host smart-43b69044-1cdb-41f9-881f-805389ec8cd6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124984929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.124984929
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1578219309
Short name T256
Test name
Test status
Simulation time 117665953 ps
CPU time 1.35 seconds
Started May 14 01:38:50 PM PDT 24
Finished May 14 01:38:52 PM PDT 24
Peak memory 209760 kb
Host smart-bac55a53-de19-46db-b4d1-ec77146e2705
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578219309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1578219309
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.4138131956
Short name T711
Test name
Test status
Simulation time 600346952 ps
CPU time 14.91 seconds
Started May 14 01:38:55 PM PDT 24
Finished May 14 01:39:12 PM PDT 24
Peak memory 218128 kb
Host smart-b511156e-4375-4bc5-9481-acbe1cccc1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138131956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.4138131956
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.653025632
Short name T180
Test name
Test status
Simulation time 310520199 ps
CPU time 8.35 seconds
Started May 14 01:38:52 PM PDT 24
Finished May 14 01:39:02 PM PDT 24
Peak memory 209712 kb
Host smart-a76fca71-1e0f-482d-984c-69f4823f1ccd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653025632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.653025632
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2790115264
Short name T638
Test name
Test status
Simulation time 76842870 ps
CPU time 1.95 seconds
Started May 14 01:38:50 PM PDT 24
Finished May 14 01:38:53 PM PDT 24
Peak memory 218200 kb
Host smart-e3b5a1d7-3bfb-44cb-9572-d9fc994e3c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790115264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2790115264
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.4023734734
Short name T90
Test name
Test status
Simulation time 386930550 ps
CPU time 17.91 seconds
Started May 14 01:38:50 PM PDT 24
Finished May 14 01:39:09 PM PDT 24
Peak memory 218360 kb
Host smart-0e41fb40-c6f6-4ef4-9ec1-6783b5352613
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023734734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.4023734734
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1631392192
Short name T555
Test name
Test status
Simulation time 2124641878 ps
CPU time 15.1 seconds
Started May 14 01:38:51 PM PDT 24
Finished May 14 01:39:07 PM PDT 24
Peak memory 218096 kb
Host smart-797c4c46-7977-400a-89c2-40ada3f0f83f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631392192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1631392192
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.171276970
Short name T160
Test name
Test status
Simulation time 389743902 ps
CPU time 8.93 seconds
Started May 14 01:38:51 PM PDT 24
Finished May 14 01:39:02 PM PDT 24
Peak memory 218052 kb
Host smart-9aa2931e-a9fc-45e4-928d-1bd857c12790
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171276970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.171276970
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.452779359
Short name T579
Test name
Test status
Simulation time 582078849 ps
CPU time 11.21 seconds
Started May 14 01:38:55 PM PDT 24
Finished May 14 01:39:08 PM PDT 24
Peak memory 218312 kb
Host smart-05df6f99-72fe-463a-aa45-4c895e1496ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452779359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.452779359
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3477882408
Short name T275
Test name
Test status
Simulation time 76799409 ps
CPU time 2.6 seconds
Started May 14 01:38:53 PM PDT 24
Finished May 14 01:38:57 PM PDT 24
Peak memory 218444 kb
Host smart-720ef514-eeb6-46e8-afc9-fa3afda35dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477882408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3477882408
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3638743463
Short name T501
Test name
Test status
Simulation time 479847269 ps
CPU time 31.08 seconds
Started May 14 01:38:49 PM PDT 24
Finished May 14 01:39:21 PM PDT 24
Peak memory 251176 kb
Host smart-8a014e3c-ad08-4fdb-93e7-972cf49ef353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638743463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3638743463
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.306530179
Short name T809
Test name
Test status
Simulation time 158233179 ps
CPU time 10 seconds
Started May 14 01:38:49 PM PDT 24
Finished May 14 01:38:59 PM PDT 24
Peak memory 251136 kb
Host smart-79058fa0-1b0f-4d82-a010-42d6ba81b740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306530179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.306530179
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2786079109
Short name T656
Test name
Test status
Simulation time 2229744299 ps
CPU time 70.31 seconds
Started May 14 01:38:51 PM PDT 24
Finished May 14 01:40:03 PM PDT 24
Peak memory 270740 kb
Host smart-4d203072-9269-40c3-9c05-1f5a7432ac04
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786079109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2786079109
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.4000675721
Short name T404
Test name
Test status
Simulation time 27777221 ps
CPU time 1 seconds
Started May 14 01:38:51 PM PDT 24
Finished May 14 01:38:53 PM PDT 24
Peak memory 211768 kb
Host smart-73c6be8b-fe50-4b23-9228-65c64e642ab2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000675721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.4000675721
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3700316001
Short name T797
Test name
Test status
Simulation time 24200558 ps
CPU time 1.28 seconds
Started May 14 01:38:51 PM PDT 24
Finished May 14 01:38:54 PM PDT 24
Peak memory 209724 kb
Host smart-5eafe0fc-c2c9-4c27-a7f2-97e94af7ea9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700316001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3700316001
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2058076759
Short name T557
Test name
Test status
Simulation time 376193385 ps
CPU time 17.08 seconds
Started May 14 01:38:52 PM PDT 24
Finished May 14 01:39:11 PM PDT 24
Peak memory 218028 kb
Host smart-add802be-0669-4e8e-bfae-1d7d71e7c1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058076759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2058076759
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.757636118
Short name T719
Test name
Test status
Simulation time 513697170 ps
CPU time 3.64 seconds
Started May 14 01:38:54 PM PDT 24
Finished May 14 01:39:00 PM PDT 24
Peak memory 209720 kb
Host smart-50bdd0c7-ef6e-42e7-969c-ab5e7248e39d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757636118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.757636118
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.1552434648
Short name T405
Test name
Test status
Simulation time 1129688994 ps
CPU time 2.77 seconds
Started May 14 01:38:50 PM PDT 24
Finished May 14 01:38:54 PM PDT 24
Peak memory 218212 kb
Host smart-75d648b4-45d0-42f8-aed1-681eb73dcddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552434648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.1552434648
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2115810271
Short name T772
Test name
Test status
Simulation time 4674922548 ps
CPU time 12.32 seconds
Started May 14 01:38:51 PM PDT 24
Finished May 14 01:39:05 PM PDT 24
Peak memory 219144 kb
Host smart-52cfb4f9-8cfd-43c8-9963-335df475239b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115810271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2115810271
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.2126523009
Short name T313
Test name
Test status
Simulation time 603569233 ps
CPU time 11.76 seconds
Started May 14 01:38:52 PM PDT 24
Finished May 14 01:39:05 PM PDT 24
Peak memory 218128 kb
Host smart-15ac476d-c956-4863-87f3-3f52cdaa0149
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126523009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.2126523009
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1295973645
Short name T374
Test name
Test status
Simulation time 416478535 ps
CPU time 10.3 seconds
Started May 14 01:38:53 PM PDT 24
Finished May 14 01:39:04 PM PDT 24
Peak memory 218108 kb
Host smart-73b520fc-ce4c-4229-81cf-a975a4a9c133
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295973645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1295973645
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.352245680
Short name T331
Test name
Test status
Simulation time 2842245241 ps
CPU time 12.47 seconds
Started May 14 01:38:53 PM PDT 24
Finished May 14 01:39:07 PM PDT 24
Peak memory 224892 kb
Host smart-b835b9d8-23c6-4c08-9e90-e4d4f4558c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352245680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.352245680
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1736857959
Short name T569
Test name
Test status
Simulation time 39735872 ps
CPU time 2.37 seconds
Started May 14 01:38:49 PM PDT 24
Finished May 14 01:38:52 PM PDT 24
Peak memory 213768 kb
Host smart-d5b4daef-7cf1-4bb1-b546-692d45e66725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736857959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1736857959
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.2523711697
Short name T91
Test name
Test status
Simulation time 251758692 ps
CPU time 29.4 seconds
Started May 14 01:38:51 PM PDT 24
Finished May 14 01:39:23 PM PDT 24
Peak memory 248768 kb
Host smart-bf597f40-b95b-45bc-b0b7-e681b25c0ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523711697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2523711697
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.1750569067
Short name T425
Test name
Test status
Simulation time 222518504 ps
CPU time 7.41 seconds
Started May 14 01:38:51 PM PDT 24
Finished May 14 01:39:01 PM PDT 24
Peak memory 242948 kb
Host smart-4099fe8b-2e18-4f94-b819-8f62b74a24fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750569067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.1750569067
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3915192612
Short name T41
Test name
Test status
Simulation time 5422292867 ps
CPU time 193.55 seconds
Started May 14 01:38:52 PM PDT 24
Finished May 14 01:42:07 PM PDT 24
Peak memory 251160 kb
Host smart-8d60d9a6-76d8-4118-bba8-d9bdf92e3965
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915192612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3915192612
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3470442028
Short name T305
Test name
Test status
Simulation time 40834647 ps
CPU time 0.97 seconds
Started May 14 01:38:50 PM PDT 24
Finished May 14 01:38:52 PM PDT 24
Peak memory 213000 kb
Host smart-388e3b60-5525-4215-acba-6c90a62e0a2d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470442028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.3470442028
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.581271666
Short name T449
Test name
Test status
Simulation time 21919626 ps
CPU time 1.2 seconds
Started May 14 01:39:02 PM PDT 24
Finished May 14 01:39:04 PM PDT 24
Peak memory 209732 kb
Host smart-45fdaf95-cf63-46e1-b72e-b167e614bd93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581271666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.581271666
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3584913069
Short name T43
Test name
Test status
Simulation time 658301476 ps
CPU time 14.1 seconds
Started May 14 01:38:51 PM PDT 24
Finished May 14 01:39:06 PM PDT 24
Peak memory 218164 kb
Host smart-21720f41-a8a1-4ffc-9b70-e2814b8757ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584913069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3584913069
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.3717821791
Short name T826
Test name
Test status
Simulation time 1979089025 ps
CPU time 5.79 seconds
Started May 14 01:38:51 PM PDT 24
Finished May 14 01:38:58 PM PDT 24
Peak memory 209832 kb
Host smart-e856671b-d4a1-4ed9-b9cc-a90e1fb0eb76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717821791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.3717821791
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1918670065
Short name T649
Test name
Test status
Simulation time 475862233 ps
CPU time 3.43 seconds
Started May 14 01:38:50 PM PDT 24
Finished May 14 01:38:54 PM PDT 24
Peak memory 218124 kb
Host smart-4090b411-8234-4b19-ab3d-4e79ed01c4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918670065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1918670065
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2814646284
Short name T287
Test name
Test status
Simulation time 353065347 ps
CPU time 9.69 seconds
Started May 14 01:38:56 PM PDT 24
Finished May 14 01:39:07 PM PDT 24
Peak memory 226236 kb
Host smart-eabf4c5d-cbcf-41a5-a3f5-e4afc092cd80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814646284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2814646284
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.4222937161
Short name T168
Test name
Test status
Simulation time 737873640 ps
CPU time 20.13 seconds
Started May 14 01:38:49 PM PDT 24
Finished May 14 01:39:10 PM PDT 24
Peak memory 218232 kb
Host smart-fd8ec090-603f-416a-8035-cecb3101e759
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222937161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.4222937161
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1054805598
Short name T240
Test name
Test status
Simulation time 534084852 ps
CPU time 10.64 seconds
Started May 14 01:38:51 PM PDT 24
Finished May 14 01:39:03 PM PDT 24
Peak memory 218308 kb
Host smart-153a3086-7806-49d9-a469-87045aa767bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054805598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1054805598
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3510892478
Short name T505
Test name
Test status
Simulation time 399451565 ps
CPU time 6.25 seconds
Started May 14 01:38:48 PM PDT 24
Finished May 14 01:38:55 PM PDT 24
Peak memory 218208 kb
Host smart-ccadba07-887f-434f-b9c5-d076b8aafdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510892478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3510892478
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.1487622020
Short name T225
Test name
Test status
Simulation time 48553872 ps
CPU time 3.16 seconds
Started May 14 01:38:50 PM PDT 24
Finished May 14 01:38:55 PM PDT 24
Peak memory 218084 kb
Host smart-c15e700e-2eb3-4df2-b718-3e144aa9f972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487622020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.1487622020
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1521458781
Short name T617
Test name
Test status
Simulation time 202041482 ps
CPU time 20.71 seconds
Started May 14 01:38:51 PM PDT 24
Finished May 14 01:39:14 PM PDT 24
Peak memory 249696 kb
Host smart-e2e8c4d7-de03-4cd2-b725-69bc99fc87e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521458781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1521458781
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.960878356
Short name T491
Test name
Test status
Simulation time 435583862 ps
CPU time 9.1 seconds
Started May 14 01:38:51 PM PDT 24
Finished May 14 01:39:01 PM PDT 24
Peak memory 251360 kb
Host smart-b371bc04-167a-4589-a4be-d5375d991302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960878356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.960878356
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.1850709064
Short name T356
Test name
Test status
Simulation time 8809446701 ps
CPU time 54.27 seconds
Started May 14 01:38:51 PM PDT 24
Finished May 14 01:39:47 PM PDT 24
Peak memory 251060 kb
Host smart-fe7b76bf-7a14-40b8-9547-af1975100498
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850709064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.1850709064
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3368664664
Short name T136
Test name
Test status
Simulation time 23232780562 ps
CPU time 337.99 seconds
Started May 14 01:38:51 PM PDT 24
Finished May 14 01:44:31 PM PDT 24
Peak memory 282948 kb
Host smart-c4470d60-a707-4bbf-8d4f-ecc620221571
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3368664664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3368664664
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1314727449
Short name T815
Test name
Test status
Simulation time 60775134 ps
CPU time 0.93 seconds
Started May 14 01:38:49 PM PDT 24
Finished May 14 01:38:50 PM PDT 24
Peak memory 211780 kb
Host smart-b8b9a499-d73e-4ddb-b251-31a443f4c270
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314727449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.1314727449
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2995096511
Short name T315
Test name
Test status
Simulation time 12062823 ps
CPU time 0.97 seconds
Started May 14 01:38:58 PM PDT 24
Finished May 14 01:39:00 PM PDT 24
Peak memory 209744 kb
Host smart-f229197a-4d52-4b8c-8cd2-17da598ca56f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995096511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2995096511
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.832653366
Short name T497
Test name
Test status
Simulation time 481144134 ps
CPU time 13.25 seconds
Started May 14 01:38:57 PM PDT 24
Finished May 14 01:39:12 PM PDT 24
Peak memory 218056 kb
Host smart-c6ce9872-9e5e-4dfc-b811-6fdc129716ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832653366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.832653366
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2044719094
Short name T552
Test name
Test status
Simulation time 244772539 ps
CPU time 2.99 seconds
Started May 14 01:38:58 PM PDT 24
Finished May 14 01:39:02 PM PDT 24
Peak memory 218128 kb
Host smart-8302e1aa-98d0-4ce5-b984-9a9a1c22a416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044719094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2044719094
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2117015580
Short name T673
Test name
Test status
Simulation time 356032810 ps
CPU time 12 seconds
Started May 14 01:39:02 PM PDT 24
Finished May 14 01:39:15 PM PDT 24
Peak memory 219108 kb
Host smart-ef016d80-04ae-4f82-ae3d-52b91683c559
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117015580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2117015580
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2265700921
Short name T173
Test name
Test status
Simulation time 1053131460 ps
CPU time 9.83 seconds
Started May 14 01:38:56 PM PDT 24
Finished May 14 01:39:08 PM PDT 24
Peak memory 218104 kb
Host smart-b3615b03-9353-419a-8d3a-42086dee1e59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265700921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2265700921
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1260140047
Short name T396
Test name
Test status
Simulation time 1109801204 ps
CPU time 8.53 seconds
Started May 14 01:39:01 PM PDT 24
Finished May 14 01:39:10 PM PDT 24
Peak memory 218216 kb
Host smart-8e87d0d0-7aeb-4f1b-a878-501bd08ded4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260140047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1260140047
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.4104145898
Short name T304
Test name
Test status
Simulation time 418515897 ps
CPU time 7.74 seconds
Started May 14 01:38:57 PM PDT 24
Finished May 14 01:39:06 PM PDT 24
Peak memory 224724 kb
Host smart-93024a2c-f871-47c3-bad5-e16685fd0844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104145898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.4104145898
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3396436786
Short name T706
Test name
Test status
Simulation time 291963521 ps
CPU time 3.8 seconds
Started May 14 01:38:56 PM PDT 24
Finished May 14 01:39:01 PM PDT 24
Peak memory 214672 kb
Host smart-567880bb-e67d-410f-89ae-4dffa0928628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396436786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3396436786
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3262391505
Short name T532
Test name
Test status
Simulation time 452964679 ps
CPU time 20.03 seconds
Started May 14 01:38:57 PM PDT 24
Finished May 14 01:39:18 PM PDT 24
Peak memory 250968 kb
Host smart-3b14d95d-025a-4a71-b6b3-3016bec05f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262391505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3262391505
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.32589228
Short name T652
Test name
Test status
Simulation time 73441822 ps
CPU time 8.26 seconds
Started May 14 01:38:56 PM PDT 24
Finished May 14 01:39:06 PM PDT 24
Peak memory 251064 kb
Host smart-d6edfee1-7c10-420f-8d09-98756dba8f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32589228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.32589228
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2726018543
Short name T92
Test name
Test status
Simulation time 37441502185 ps
CPU time 151.03 seconds
Started May 14 01:38:57 PM PDT 24
Finished May 14 01:41:30 PM PDT 24
Peak memory 279652 kb
Host smart-0b985652-6fff-4117-8d76-c62cb1765e18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726018543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2726018543
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.4242692755
Short name T314
Test name
Test status
Simulation time 109576468 ps
CPU time 0.86 seconds
Started May 14 01:38:57 PM PDT 24
Finished May 14 01:39:00 PM PDT 24
Peak memory 211728 kb
Host smart-a6ffddb9-a04d-45c1-bbd1-8aa54314a632
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242692755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.4242692755
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2690174056
Short name T473
Test name
Test status
Simulation time 53729203 ps
CPU time 0.88 seconds
Started May 14 01:39:04 PM PDT 24
Finished May 14 01:39:06 PM PDT 24
Peak memory 209740 kb
Host smart-54e03f0b-6882-4d89-bb14-c5f6d1d60cb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690174056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2690174056
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1313457023
Short name T355
Test name
Test status
Simulation time 1285354469 ps
CPU time 14.25 seconds
Started May 14 01:38:57 PM PDT 24
Finished May 14 01:39:13 PM PDT 24
Peak memory 218096 kb
Host smart-219c651d-9f29-42a4-81eb-97184a1b8bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313457023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1313457023
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1132156897
Short name T669
Test name
Test status
Simulation time 1288079851 ps
CPU time 10.03 seconds
Started May 14 01:38:57 PM PDT 24
Finished May 14 01:39:09 PM PDT 24
Peak memory 209700 kb
Host smart-f1aec20e-32e8-43af-a967-e118e8a2b622
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132156897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1132156897
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1050405442
Short name T568
Test name
Test status
Simulation time 247998345 ps
CPU time 4.66 seconds
Started May 14 01:39:02 PM PDT 24
Finished May 14 01:39:07 PM PDT 24
Peak memory 218148 kb
Host smart-956d6bb0-3947-40bb-b086-293823390996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050405442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1050405442
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.3111937617
Short name T50
Test name
Test status
Simulation time 268045449 ps
CPU time 13.99 seconds
Started May 14 01:38:58 PM PDT 24
Finished May 14 01:39:13 PM PDT 24
Peak memory 219136 kb
Host smart-8c22d4c5-9063-4d27-aa38-0b44b9219edd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111937617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3111937617
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.4091594198
Short name T474
Test name
Test status
Simulation time 900821237 ps
CPU time 18.69 seconds
Started May 14 01:39:07 PM PDT 24
Finished May 14 01:39:27 PM PDT 24
Peak memory 218192 kb
Host smart-6d1d771b-edd3-460f-9949-b5b5ec8b3926
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091594198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.4091594198
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1328007313
Short name T691
Test name
Test status
Simulation time 1032709044 ps
CPU time 18.49 seconds
Started May 14 01:39:06 PM PDT 24
Finished May 14 01:39:26 PM PDT 24
Peak memory 218096 kb
Host smart-3b38bfeb-3f30-491c-b606-d0e0a7377e67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328007313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1328007313
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.3783402518
Short name T364
Test name
Test status
Simulation time 1778708269 ps
CPU time 9.46 seconds
Started May 14 01:38:56 PM PDT 24
Finished May 14 01:39:07 PM PDT 24
Peak memory 226196 kb
Host smart-b5b24bc5-abc3-407f-9dd9-eee033945b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783402518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.3783402518
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3339441960
Short name T61
Test name
Test status
Simulation time 20877041 ps
CPU time 1.5 seconds
Started May 14 01:39:02 PM PDT 24
Finished May 14 01:39:04 PM PDT 24
Peak memory 213664 kb
Host smart-06a8dea0-d129-42b9-a163-9dbf6ab7456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339441960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3339441960
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1665499198
Short name T463
Test name
Test status
Simulation time 1103018588 ps
CPU time 25.46 seconds
Started May 14 01:38:57 PM PDT 24
Finished May 14 01:39:24 PM PDT 24
Peak memory 251124 kb
Host smart-145db827-4983-413f-b161-62fdd9b2178a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665499198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1665499198
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.633111225
Short name T855
Test name
Test status
Simulation time 69701017 ps
CPU time 7.32 seconds
Started May 14 01:38:57 PM PDT 24
Finished May 14 01:39:06 PM PDT 24
Peak memory 250832 kb
Host smart-3b1a15ed-860b-4c50-a224-7e5e294df66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633111225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.633111225
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.4277863387
Short name T573
Test name
Test status
Simulation time 25162048727 ps
CPU time 97.2 seconds
Started May 14 01:39:05 PM PDT 24
Finished May 14 01:40:44 PM PDT 24
Peak memory 268284 kb
Host smart-e0dc7103-fb79-4af2-9236-c08399b3203f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277863387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.4277863387
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.766560538
Short name T383
Test name
Test status
Simulation time 26116118 ps
CPU time 0.84 seconds
Started May 14 01:38:56 PM PDT 24
Finished May 14 01:38:58 PM PDT 24
Peak memory 211836 kb
Host smart-fc6116bf-eb36-416a-9566-978180c7c032
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766560538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.766560538
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.4179641175
Short name T289
Test name
Test status
Simulation time 45923788 ps
CPU time 1.05 seconds
Started May 14 01:39:05 PM PDT 24
Finished May 14 01:39:08 PM PDT 24
Peak memory 209644 kb
Host smart-cb985e12-f017-4fd6-bcc1-d7d32e2e9ca5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179641175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.4179641175
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2105072023
Short name T566
Test name
Test status
Simulation time 7370911399 ps
CPU time 21.66 seconds
Started May 14 01:39:05 PM PDT 24
Finished May 14 01:39:28 PM PDT 24
Peak memory 218520 kb
Host smart-f70a1e29-679a-4fab-bb4d-ca78792883f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105072023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2105072023
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.3497798846
Short name T10
Test name
Test status
Simulation time 3680556613 ps
CPU time 4.39 seconds
Started May 14 01:39:08 PM PDT 24
Finished May 14 01:39:13 PM PDT 24
Peak memory 217548 kb
Host smart-5e0329ee-2190-4a4b-80e1-6f8b2af12130
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497798846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.3497798846
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3427051191
Short name T660
Test name
Test status
Simulation time 82842514 ps
CPU time 2.9 seconds
Started May 14 01:39:05 PM PDT 24
Finished May 14 01:39:11 PM PDT 24
Peak memory 218064 kb
Host smart-60f3993b-76d0-4c43-9d31-c18d89abeeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427051191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3427051191
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.223997471
Short name T456
Test name
Test status
Simulation time 325599206 ps
CPU time 13.88 seconds
Started May 14 01:39:04 PM PDT 24
Finished May 14 01:39:20 PM PDT 24
Peak memory 226240 kb
Host smart-1ab27694-e558-4bc8-ba08-652afa38f27b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223997471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.223997471
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1768749359
Short name T836
Test name
Test status
Simulation time 762708368 ps
CPU time 20.01 seconds
Started May 14 01:39:05 PM PDT 24
Finished May 14 01:39:27 PM PDT 24
Peak memory 218164 kb
Host smart-61320476-ec35-4ad2-b183-df53ea8ff0cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768749359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1768749359
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.3308286402
Short name T309
Test name
Test status
Simulation time 3385820416 ps
CPU time 13.86 seconds
Started May 14 01:39:05 PM PDT 24
Finished May 14 01:39:21 PM PDT 24
Peak memory 218272 kb
Host smart-f93fe3cc-9289-4d1c-992b-179892f4d938
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308286402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
3308286402
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1777848951
Short name T598
Test name
Test status
Simulation time 962850331 ps
CPU time 11.93 seconds
Started May 14 01:39:05 PM PDT 24
Finished May 14 01:39:19 PM PDT 24
Peak memory 218184 kb
Host smart-e16bac97-131f-486b-9229-edd7dd5d73b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777848951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1777848951
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.2925717406
Short name T539
Test name
Test status
Simulation time 64105536 ps
CPU time 3.12 seconds
Started May 14 01:39:04 PM PDT 24
Finished May 14 01:39:09 PM PDT 24
Peak memory 213676 kb
Host smart-af680c29-643e-40fd-9495-61820fb6bde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925717406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.2925717406
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2138149353
Short name T634
Test name
Test status
Simulation time 624280880 ps
CPU time 18.58 seconds
Started May 14 01:39:06 PM PDT 24
Finished May 14 01:39:26 PM PDT 24
Peak memory 248464 kb
Host smart-31d761d1-52e3-4f25-a4e8-4cc2b8e5b629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138149353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2138149353
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.4121522113
Short name T28
Test name
Test status
Simulation time 100576942 ps
CPU time 9.61 seconds
Started May 14 01:39:09 PM PDT 24
Finished May 14 01:39:19 PM PDT 24
Peak memory 250772 kb
Host smart-0bfafe05-7806-487f-be79-120824f5c5cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121522113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.4121522113
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.909198379
Short name T614
Test name
Test status
Simulation time 4362829491 ps
CPU time 85.81 seconds
Started May 14 01:39:05 PM PDT 24
Finished May 14 01:40:33 PM PDT 24
Peak memory 251056 kb
Host smart-de492318-1a29-40d5-8e64-590d32ab42c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909198379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.909198379
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2948857777
Short name T537
Test name
Test status
Simulation time 36200741 ps
CPU time 0.87 seconds
Started May 14 01:39:05 PM PDT 24
Finished May 14 01:39:08 PM PDT 24
Peak memory 213028 kb
Host smart-fdf09b30-a459-4b69-b856-82fddc530072
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948857777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2948857777
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2652578607
Short name T693
Test name
Test status
Simulation time 69839291 ps
CPU time 1.22 seconds
Started May 14 01:39:15 PM PDT 24
Finished May 14 01:39:17 PM PDT 24
Peak memory 209708 kb
Host smart-01764dbc-83e2-4196-907f-a6d94544b65d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652578607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2652578607
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3027368539
Short name T85
Test name
Test status
Simulation time 303692683 ps
CPU time 12.99 seconds
Started May 14 01:39:14 PM PDT 24
Finished May 14 01:39:28 PM PDT 24
Peak memory 218320 kb
Host smart-91b12874-a633-404e-b68d-4ae881189109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027368539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3027368539
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1771108539
Short name T33
Test name
Test status
Simulation time 645958572 ps
CPU time 2.4 seconds
Started May 14 01:39:16 PM PDT 24
Finished May 14 01:39:20 PM PDT 24
Peak memory 209768 kb
Host smart-b418e9e1-9f03-479a-9018-b48430902024
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771108539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1771108539
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.3622397147
Short name T844
Test name
Test status
Simulation time 117168989 ps
CPU time 2.07 seconds
Started May 14 01:39:16 PM PDT 24
Finished May 14 01:39:20 PM PDT 24
Peak memory 218372 kb
Host smart-b392dcaa-6595-42fa-9a84-c912cadfd8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622397147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.3622397147
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.54875205
Short name T38
Test name
Test status
Simulation time 263706914 ps
CPU time 14.1 seconds
Started May 14 01:39:16 PM PDT 24
Finished May 14 01:39:31 PM PDT 24
Peak memory 218348 kb
Host smart-041f3e1e-d4f6-42e5-a71f-d7693c205aef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54875205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.54875205
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1837581286
Short name T597
Test name
Test status
Simulation time 1040807584 ps
CPU time 11.54 seconds
Started May 14 01:39:14 PM PDT 24
Finished May 14 01:39:27 PM PDT 24
Peak memory 218156 kb
Host smart-e6897d7a-4843-4d2c-a800-1bd24fdf173e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837581286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1837581286
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.373833374
Short name T259
Test name
Test status
Simulation time 178716480 ps
CPU time 7.99 seconds
Started May 14 01:39:15 PM PDT 24
Finished May 14 01:39:24 PM PDT 24
Peak memory 218020 kb
Host smart-721398eb-6904-4c59-82b2-458a3726f04f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373833374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.373833374
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.604877810
Short name T236
Test name
Test status
Simulation time 54316650 ps
CPU time 2.34 seconds
Started May 14 01:39:05 PM PDT 24
Finished May 14 01:39:09 PM PDT 24
Peak memory 214404 kb
Host smart-06f5d8c7-255c-4d6c-a371-a78d755d3161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604877810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.604877810
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2241082966
Short name T643
Test name
Test status
Simulation time 372563071 ps
CPU time 26.15 seconds
Started May 14 01:39:05 PM PDT 24
Finished May 14 01:39:33 PM PDT 24
Peak memory 248572 kb
Host smart-68a8e3ae-3f47-4eb6-a613-35e62c7ab042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241082966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2241082966
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2550342517
Short name T543
Test name
Test status
Simulation time 188132842 ps
CPU time 5.17 seconds
Started May 14 01:39:06 PM PDT 24
Finished May 14 01:39:13 PM PDT 24
Peak memory 226568 kb
Host smart-4122228f-df75-4df5-95b8-af52c6e1c1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550342517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2550342517
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2755438215
Short name T861
Test name
Test status
Simulation time 340921806 ps
CPU time 16.33 seconds
Started May 14 01:39:16 PM PDT 24
Finished May 14 01:39:34 PM PDT 24
Peak memory 242992 kb
Host smart-43db8144-1a2a-40cc-9fff-03b0bef51724
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755438215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2755438215
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1268720316
Short name T585
Test name
Test status
Simulation time 12676944430 ps
CPU time 437.64 seconds
Started May 14 01:39:15 PM PDT 24
Finished May 14 01:46:34 PM PDT 24
Peak memory 259312 kb
Host smart-3939f539-b36e-4de3-8182-8c6701265001
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1268720316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.1268720316
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1714046564
Short name T512
Test name
Test status
Simulation time 55420617 ps
CPU time 1.01 seconds
Started May 14 01:39:05 PM PDT 24
Finished May 14 01:39:08 PM PDT 24
Peak memory 212976 kb
Host smart-d412714d-e9c3-44f9-8ecb-396727084866
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714046564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1714046564
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3849038868
Short name T778
Test name
Test status
Simulation time 183081434 ps
CPU time 1.09 seconds
Started May 14 01:39:16 PM PDT 24
Finished May 14 01:39:18 PM PDT 24
Peak memory 209728 kb
Host smart-1adbbe5f-38b7-4cf7-a892-7178b857bcb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849038868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3849038868
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2828477831
Short name T278
Test name
Test status
Simulation time 313090896 ps
CPU time 11.98 seconds
Started May 14 01:39:15 PM PDT 24
Finished May 14 01:39:28 PM PDT 24
Peak memory 218144 kb
Host smart-d5e1c64f-a568-4eaf-9707-327dab849fb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828477831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2828477831
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.3212872730
Short name T341
Test name
Test status
Simulation time 3522056717 ps
CPU time 3.74 seconds
Started May 14 01:39:15 PM PDT 24
Finished May 14 01:39:21 PM PDT 24
Peak memory 209704 kb
Host smart-50c3e8cd-02b9-4275-b6c3-335b7a6e453a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212872730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3212872730
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3710739039
Short name T400
Test name
Test status
Simulation time 612455650 ps
CPU time 2.28 seconds
Started May 14 01:39:16 PM PDT 24
Finished May 14 01:39:20 PM PDT 24
Peak memory 218164 kb
Host smart-1ac79c3a-c0df-4a79-9dea-756d62f3eb0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710739039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3710739039
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.3536866173
Short name T39
Test name
Test status
Simulation time 1266516265 ps
CPU time 15.78 seconds
Started May 14 01:39:16 PM PDT 24
Finished May 14 01:39:34 PM PDT 24
Peak memory 219060 kb
Host smart-fd1c83a2-f943-48a1-99df-80d42540abca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536866173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.3536866173
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2068186008
Short name T153
Test name
Test status
Simulation time 449633143 ps
CPU time 11.27 seconds
Started May 14 01:39:14 PM PDT 24
Finished May 14 01:39:27 PM PDT 24
Peak memory 218156 kb
Host smart-822e7ad2-b4c9-418a-9014-ac52d4b026a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068186008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2068186008
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3328936029
Short name T215
Test name
Test status
Simulation time 232341795 ps
CPU time 9.88 seconds
Started May 14 01:39:15 PM PDT 24
Finished May 14 01:39:26 PM PDT 24
Peak memory 218272 kb
Host smart-9a1500be-0cd1-4e11-a09c-ab6c8c30e6f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328936029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3328936029
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.1003061789
Short name T507
Test name
Test status
Simulation time 3226990908 ps
CPU time 12.13 seconds
Started May 14 01:39:15 PM PDT 24
Finished May 14 01:39:29 PM PDT 24
Peak memory 218304 kb
Host smart-5f36ab60-e6e5-41ec-b2e4-f937079eb619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003061789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.1003061789
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.4281889578
Short name T387
Test name
Test status
Simulation time 137591604 ps
CPU time 2.8 seconds
Started May 14 01:39:15 PM PDT 24
Finished May 14 01:39:19 PM PDT 24
Peak memory 213920 kb
Host smart-8d98c304-59c6-4ce8-ad2b-079e08fa98dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281889578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.4281889578
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.984676619
Short name T817
Test name
Test status
Simulation time 478694810 ps
CPU time 32.21 seconds
Started May 14 01:39:10 PM PDT 24
Finished May 14 01:39:43 PM PDT 24
Peak memory 246872 kb
Host smart-c55124fd-dada-4224-9cfd-580a9ff82909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984676619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.984676619
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2531462974
Short name T589
Test name
Test status
Simulation time 144375113 ps
CPU time 3.43 seconds
Started May 14 01:39:15 PM PDT 24
Finished May 14 01:39:20 PM PDT 24
Peak memory 222424 kb
Host smart-3df3b9cc-5331-4036-9909-cff0fbfb7a60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531462974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2531462974
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1823461377
Short name T666
Test name
Test status
Simulation time 5425702702 ps
CPU time 50.5 seconds
Started May 14 01:39:17 PM PDT 24
Finished May 14 01:40:08 PM PDT 24
Peak memory 251196 kb
Host smart-027c4780-91dd-4779-9a83-a6d4e6ed12c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823461377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1823461377
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1261159534
Short name T351
Test name
Test status
Simulation time 13573388 ps
CPU time 1.1 seconds
Started May 14 01:39:17 PM PDT 24
Finished May 14 01:39:19 PM PDT 24
Peak memory 211748 kb
Host smart-03f3244a-b5a0-476b-90c8-d56219cccfeb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261159534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1261159534
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3052774354
Short name T232
Test name
Test status
Simulation time 18311696 ps
CPU time 0.9 seconds
Started May 14 01:36:50 PM PDT 24
Finished May 14 01:36:52 PM PDT 24
Peak memory 209736 kb
Host smart-36399132-128b-4257-8bc8-99b047144a9b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052774354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3052774354
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3854005127
Short name T340
Test name
Test status
Simulation time 19981930 ps
CPU time 0.84 seconds
Started May 14 01:36:42 PM PDT 24
Finished May 14 01:36:45 PM PDT 24
Peak memory 209484 kb
Host smart-5e54f6bb-d590-4231-8ed0-991daaf96ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854005127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3854005127
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1464161410
Short name T306
Test name
Test status
Simulation time 1143200221 ps
CPU time 13.95 seconds
Started May 14 01:36:42 PM PDT 24
Finished May 14 01:36:57 PM PDT 24
Peak memory 218140 kb
Host smart-bf93b0ce-ebf2-4c41-a057-f98ff9ac0d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464161410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1464161410
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3649371709
Short name T35
Test name
Test status
Simulation time 2601802490 ps
CPU time 4.45 seconds
Started May 14 01:36:46 PM PDT 24
Finished May 14 01:36:52 PM PDT 24
Peak memory 209812 kb
Host smart-2d5c8e88-d38b-43c7-98df-727e2204f822
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649371709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3649371709
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.541634893
Short name T375
Test name
Test status
Simulation time 535253162 ps
CPU time 4.2 seconds
Started May 14 01:36:50 PM PDT 24
Finished May 14 01:36:55 PM PDT 24
Peak memory 217032 kb
Host smart-059b81b4-6328-47e8-9451-9cd412e6a1c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541634893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.541634893
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.94173940
Short name T495
Test name
Test status
Simulation time 1652875862 ps
CPU time 12.63 seconds
Started May 14 01:36:42 PM PDT 24
Finished May 14 01:36:57 PM PDT 24
Peak memory 218248 kb
Host smart-36b19884-962d-4539-9015-9d1dc1f6d578
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94173940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_p
rog_failure.94173940
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2320846437
Short name T591
Test name
Test status
Simulation time 10148431144 ps
CPU time 36.86 seconds
Started May 14 01:36:51 PM PDT 24
Finished May 14 01:37:28 PM PDT 24
Peak memory 214176 kb
Host smart-3d7a72e8-829c-4eaf-8067-80c25b57762e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320846437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2320846437
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.880051918
Short name T255
Test name
Test status
Simulation time 1146368524 ps
CPU time 8.32 seconds
Started May 14 01:36:42 PM PDT 24
Finished May 14 01:36:53 PM PDT 24
Peak memory 213912 kb
Host smart-39317cf8-ab7b-4e5c-b3ef-231178dbfba4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880051918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.880051918
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3190961723
Short name T450
Test name
Test status
Simulation time 5889322851 ps
CPU time 64.83 seconds
Started May 14 01:36:42 PM PDT 24
Finished May 14 01:37:49 PM PDT 24
Peak memory 252312 kb
Host smart-d2d5cff7-1480-4cc4-b71e-4b4cd3ba5939
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190961723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3190961723
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.2048919316
Short name T246
Test name
Test status
Simulation time 2552782836 ps
CPU time 23.94 seconds
Started May 14 01:36:39 PM PDT 24
Finished May 14 01:37:04 PM PDT 24
Peak memory 250748 kb
Host smart-59678d1f-763d-4870-8267-f45d474346fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048919316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.2048919316
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3422472168
Short name T366
Test name
Test status
Simulation time 603733713 ps
CPU time 2.81 seconds
Started May 14 01:36:38 PM PDT 24
Finished May 14 01:36:42 PM PDT 24
Peak memory 218176 kb
Host smart-5115f021-fe64-4a2b-aa79-e1a30e1fe904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422472168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3422472168
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.3518361952
Short name T541
Test name
Test status
Simulation time 1311935138 ps
CPU time 16.45 seconds
Started May 14 01:36:42 PM PDT 24
Finished May 14 01:37:00 PM PDT 24
Peak memory 217992 kb
Host smart-3ad2e838-b59b-4315-b489-3a299b7f0759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518361952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.3518361952
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.891897457
Short name T78
Test name
Test status
Simulation time 1685426417 ps
CPU time 24.22 seconds
Started May 14 01:36:45 PM PDT 24
Finished May 14 01:37:10 PM PDT 24
Peak memory 282180 kb
Host smart-92369e75-ea58-469a-b9b0-f8e39be3629e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891897457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.891897457
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.3886212238
Short name T365
Test name
Test status
Simulation time 210743625 ps
CPU time 10.53 seconds
Started May 14 01:36:47 PM PDT 24
Finished May 14 01:36:59 PM PDT 24
Peak memory 218152 kb
Host smart-a0830744-06be-471f-a5ba-75d0caddf7f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886212238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.3886212238
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.96248983
Short name T343
Test name
Test status
Simulation time 1318077883 ps
CPU time 12.37 seconds
Started May 14 01:36:47 PM PDT 24
Finished May 14 01:37:00 PM PDT 24
Peak memory 218152 kb
Host smart-42fad4a5-71b2-40f3-83f2-cf3b94743dcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96248983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dige
st.96248983
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3433692727
Short name T329
Test name
Test status
Simulation time 230588834 ps
CPU time 7.18 seconds
Started May 14 01:36:47 PM PDT 24
Finished May 14 01:36:56 PM PDT 24
Peak memory 218124 kb
Host smart-25b4e1b5-11b9-4044-91f7-08b95b3cde54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433692727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3
433692727
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3725892824
Short name T688
Test name
Test status
Simulation time 216137994 ps
CPU time 8.07 seconds
Started May 14 01:36:43 PM PDT 24
Finished May 14 01:36:53 PM PDT 24
Peak memory 224548 kb
Host smart-6385ac4e-ebf6-4a5a-bd57-eb554f68edf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725892824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3725892824
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1843137302
Short name T55
Test name
Test status
Simulation time 123121199 ps
CPU time 3.97 seconds
Started May 14 01:36:41 PM PDT 24
Finished May 14 01:36:47 PM PDT 24
Peak memory 217908 kb
Host smart-8ed7ee10-0013-4d11-b901-2bc81974bf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843137302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1843137302
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3171074147
Short name T813
Test name
Test status
Simulation time 3667758693 ps
CPU time 21.92 seconds
Started May 14 01:36:44 PM PDT 24
Finished May 14 01:37:07 PM PDT 24
Peak memory 251220 kb
Host smart-7f70bfc2-6844-4561-9497-070a72cef507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171074147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3171074147
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2914575777
Short name T433
Test name
Test status
Simulation time 75771895 ps
CPU time 3.29 seconds
Started May 14 01:36:42 PM PDT 24
Finished May 14 01:36:47 PM PDT 24
Peak memory 223788 kb
Host smart-1ff6e2fd-456b-4c99-86c2-c627b073886b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914575777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2914575777
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1957777700
Short name T152
Test name
Test status
Simulation time 3243153013 ps
CPU time 59.06 seconds
Started May 14 01:36:46 PM PDT 24
Finished May 14 01:37:47 PM PDT 24
Peak memory 237388 kb
Host smart-64867769-5785-4caf-8bdf-d02c3f083b72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957777700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1957777700
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2414893291
Short name T707
Test name
Test status
Simulation time 24187936 ps
CPU time 0.86 seconds
Started May 14 01:36:42 PM PDT 24
Finished May 14 01:36:45 PM PDT 24
Peak memory 208312 kb
Host smart-eb2bf185-0834-4a37-b462-abccccb620d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414893291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2414893291
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.257798833
Short name T79
Test name
Test status
Simulation time 15678261 ps
CPU time 1.12 seconds
Started May 14 01:39:23 PM PDT 24
Finished May 14 01:39:25 PM PDT 24
Peak memory 209760 kb
Host smart-f7e75ba0-984d-4a87-baa3-45a480588cc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257798833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.257798833
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2318196315
Short name T758
Test name
Test status
Simulation time 1320687700 ps
CPU time 8.94 seconds
Started May 14 01:39:22 PM PDT 24
Finished May 14 01:39:32 PM PDT 24
Peak memory 218128 kb
Host smart-038f98b9-e916-47dd-94e8-8df0c580f0d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318196315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2318196315
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.3890802937
Short name T681
Test name
Test status
Simulation time 4978448254 ps
CPU time 3.38 seconds
Started May 14 01:39:23 PM PDT 24
Finished May 14 01:39:28 PM PDT 24
Peak memory 217484 kb
Host smart-59dea581-4b79-4cd7-ba10-cb6e751a26df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890802937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.3890802937
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.800841510
Short name T768
Test name
Test status
Simulation time 76805825 ps
CPU time 1.55 seconds
Started May 14 01:39:23 PM PDT 24
Finished May 14 01:39:26 PM PDT 24
Peak memory 218136 kb
Host smart-7efca2b3-6c71-4cf7-bfe4-965221d7d7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800841510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.800841510
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1984013262
Short name T567
Test name
Test status
Simulation time 1160873972 ps
CPU time 8.73 seconds
Started May 14 01:39:20 PM PDT 24
Finished May 14 01:39:30 PM PDT 24
Peak memory 218104 kb
Host smart-7f34477a-aedf-422b-94f1-68ce1ecac536
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984013262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1984013262
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2944042208
Short name T834
Test name
Test status
Simulation time 887365502 ps
CPU time 10.51 seconds
Started May 14 01:39:22 PM PDT 24
Finished May 14 01:39:33 PM PDT 24
Peak memory 218216 kb
Host smart-4c89dbfa-da28-4b81-9b56-1e57c0677497
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944042208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2944042208
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1859235692
Short name T301
Test name
Test status
Simulation time 652460313 ps
CPU time 7.18 seconds
Started May 14 01:39:22 PM PDT 24
Finished May 14 01:39:31 PM PDT 24
Peak memory 218124 kb
Host smart-b22d6933-4d6c-4e45-8774-98af1cacc9f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859235692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1859235692
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.3626882290
Short name T604
Test name
Test status
Simulation time 318908098 ps
CPU time 8.9 seconds
Started May 14 01:39:27 PM PDT 24
Finished May 14 01:39:37 PM PDT 24
Peak memory 218180 kb
Host smart-1721a3ce-98b4-4e78-841a-4e1c4c42b2ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626882290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.3626882290
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1773271913
Short name T496
Test name
Test status
Simulation time 68046442 ps
CPU time 2.41 seconds
Started May 14 01:39:23 PM PDT 24
Finished May 14 01:39:27 PM PDT 24
Peak memory 214180 kb
Host smart-31df7693-d621-4a24-96bc-7350dbe62677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773271913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1773271913
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.825675823
Short name T369
Test name
Test status
Simulation time 1294435073 ps
CPU time 26.66 seconds
Started May 14 01:39:22 PM PDT 24
Finished May 14 01:39:51 PM PDT 24
Peak memory 251100 kb
Host smart-827d4229-a09a-45f8-8a06-00ab2182624a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825675823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.825675823
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2700227792
Short name T752
Test name
Test status
Simulation time 78498012 ps
CPU time 8.35 seconds
Started May 14 01:39:24 PM PDT 24
Finished May 14 01:39:34 PM PDT 24
Peak memory 247328 kb
Host smart-b9d57740-37d3-4807-9845-6d2ca284e9a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700227792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2700227792
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3969802410
Short name T427
Test name
Test status
Simulation time 29453235158 ps
CPU time 497.2 seconds
Started May 14 01:39:24 PM PDT 24
Finished May 14 01:47:43 PM PDT 24
Peak memory 283888 kb
Host smart-c1d5716a-3d8e-43a5-b6d9-e0b9ab2244f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969802410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3969802410
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.1811499409
Short name T101
Test name
Test status
Simulation time 453964907681 ps
CPU time 1898 seconds
Started May 14 01:39:20 PM PDT 24
Finished May 14 02:10:59 PM PDT 24
Peak memory 726460 kb
Host smart-8f53a640-e97c-4f7f-91f9-e255d444b1ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1811499409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.1811499409
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.317931934
Short name T623
Test name
Test status
Simulation time 39176659 ps
CPU time 1.02 seconds
Started May 14 01:39:21 PM PDT 24
Finished May 14 01:39:23 PM PDT 24
Peak memory 211648 kb
Host smart-456193a0-3633-473a-ab33-3be409cbf1fd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317931934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.317931934
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1317039727
Short name T697
Test name
Test status
Simulation time 135701181 ps
CPU time 0.89 seconds
Started May 14 01:39:24 PM PDT 24
Finished May 14 01:39:26 PM PDT 24
Peak memory 209760 kb
Host smart-376466e1-eedb-4829-89bb-c446c8bb1f11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317039727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1317039727
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1677851106
Short name T327
Test name
Test status
Simulation time 13318163250 ps
CPU time 21.6 seconds
Started May 14 01:39:26 PM PDT 24
Finished May 14 01:39:49 PM PDT 24
Peak memory 218584 kb
Host smart-61cc35ef-b268-446f-a9a3-0a5232b0541d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677851106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1677851106
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3814161865
Short name T714
Test name
Test status
Simulation time 142284385 ps
CPU time 1.66 seconds
Started May 14 01:39:21 PM PDT 24
Finished May 14 01:39:24 PM PDT 24
Peak memory 209796 kb
Host smart-f9644bcf-5d92-4bba-b075-15ee2c0b6cf8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814161865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3814161865
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.1420830118
Short name T746
Test name
Test status
Simulation time 71094911 ps
CPU time 3.9 seconds
Started May 14 01:39:22 PM PDT 24
Finished May 14 01:39:27 PM PDT 24
Peak memory 218248 kb
Host smart-8bc97460-bcf8-41fb-881f-aef538bad2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420830118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1420830118
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.782818678
Short name T536
Test name
Test status
Simulation time 1070787176 ps
CPU time 16.63 seconds
Started May 14 01:39:22 PM PDT 24
Finished May 14 01:39:41 PM PDT 24
Peak memory 219076 kb
Host smart-4aeb59c5-7c3b-4e86-bd11-e7d62d8d33b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782818678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.782818678
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3896091630
Short name T280
Test name
Test status
Simulation time 255838384 ps
CPU time 9.83 seconds
Started May 14 01:39:23 PM PDT 24
Finished May 14 01:39:34 PM PDT 24
Peak memory 218148 kb
Host smart-0a2ec982-39ce-4501-9904-615400031dd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896091630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3896091630
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.1598609452
Short name T554
Test name
Test status
Simulation time 1444553349 ps
CPU time 10.16 seconds
Started May 14 01:39:24 PM PDT 24
Finished May 14 01:39:36 PM PDT 24
Peak memory 218248 kb
Host smart-988073b2-6853-4271-be9e-53da3a0e2a9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598609452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
1598609452
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2923539576
Short name T44
Test name
Test status
Simulation time 345982454 ps
CPU time 13.16 seconds
Started May 14 01:39:22 PM PDT 24
Finished May 14 01:39:37 PM PDT 24
Peak memory 218196 kb
Host smart-9aaf7a0e-5b8b-47bf-b94e-6fcbfff47c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923539576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2923539576
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3809782434
Short name T509
Test name
Test status
Simulation time 64365839 ps
CPU time 1.21 seconds
Started May 14 01:39:20 PM PDT 24
Finished May 14 01:39:23 PM PDT 24
Peak memory 213544 kb
Host smart-43720da6-acf3-4379-ad89-42b8d969e7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809782434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3809782434
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3110865066
Short name T302
Test name
Test status
Simulation time 158608488 ps
CPU time 3.31 seconds
Started May 14 01:39:23 PM PDT 24
Finished May 14 01:39:27 PM PDT 24
Peak memory 222520 kb
Host smart-f152ab27-e98f-4d33-bdc4-6e68d55692cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110865066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3110865066
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.1189204571
Short name T423
Test name
Test status
Simulation time 57733663 ps
CPU time 0.93 seconds
Started May 14 01:39:23 PM PDT 24
Finished May 14 01:39:25 PM PDT 24
Peak memory 211736 kb
Host smart-9474993c-72b0-4e45-a1db-82d1e1560eeb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189204571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.1189204571
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1266236570
Short name T377
Test name
Test status
Simulation time 27802247 ps
CPU time 1.26 seconds
Started May 14 01:39:30 PM PDT 24
Finished May 14 01:39:32 PM PDT 24
Peak memory 209704 kb
Host smart-3d0859c1-3d9a-46e2-b18c-cf50213f8a21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266236570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1266236570
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2166467950
Short name T482
Test name
Test status
Simulation time 381113506 ps
CPU time 10.33 seconds
Started May 14 01:39:30 PM PDT 24
Finished May 14 01:39:42 PM PDT 24
Peak memory 218076 kb
Host smart-a4684d1f-a387-4c09-9b5f-12fb30818431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166467950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2166467950
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2697279746
Short name T702
Test name
Test status
Simulation time 479597708 ps
CPU time 3.65 seconds
Started May 14 01:39:29 PM PDT 24
Finished May 14 01:39:34 PM PDT 24
Peak memory 217212 kb
Host smart-a748650c-936b-48c3-bfe3-cb7d8f246f8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697279746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2697279746
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.4085687070
Short name T422
Test name
Test status
Simulation time 220641158 ps
CPU time 2.65 seconds
Started May 14 01:39:30 PM PDT 24
Finished May 14 01:39:34 PM PDT 24
Peak memory 218160 kb
Host smart-be21f0db-8ae0-4ef5-a14c-5e7521a71064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085687070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.4085687070
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3356196914
Short name T435
Test name
Test status
Simulation time 756185889 ps
CPU time 13.63 seconds
Started May 14 01:39:29 PM PDT 24
Finished May 14 01:39:44 PM PDT 24
Peak memory 219092 kb
Host smart-b89a6080-2ae4-4e18-8199-04f82baf35e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356196914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3356196914
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.4147748551
Short name T295
Test name
Test status
Simulation time 1800712065 ps
CPU time 14.27 seconds
Started May 14 01:39:29 PM PDT 24
Finished May 14 01:39:44 PM PDT 24
Peak memory 218140 kb
Host smart-e5a7e70b-40e9-4b3f-9ca8-cd5532174bac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147748551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.4147748551
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.641472792
Short name T231
Test name
Test status
Simulation time 318481514 ps
CPU time 8.6 seconds
Started May 14 01:39:32 PM PDT 24
Finished May 14 01:39:42 PM PDT 24
Peak memory 218148 kb
Host smart-11541db7-148e-4685-9663-a52ff6d6c3bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641472792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.641472792
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1200667795
Short name T687
Test name
Test status
Simulation time 925436300 ps
CPU time 15.73 seconds
Started May 14 01:39:29 PM PDT 24
Finished May 14 01:39:46 PM PDT 24
Peak memory 226204 kb
Host smart-1892c8b3-aaf9-48ff-ad5f-cec0924daa66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200667795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1200667795
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.785570766
Short name T285
Test name
Test status
Simulation time 1410334493 ps
CPU time 4.61 seconds
Started May 14 01:39:26 PM PDT 24
Finished May 14 01:39:31 PM PDT 24
Peak memory 217904 kb
Host smart-1cbf8a58-4154-44d7-8177-ef31aaf35704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785570766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.785570766
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3092203826
Short name T2
Test name
Test status
Simulation time 304391743 ps
CPU time 26.76 seconds
Started May 14 01:39:22 PM PDT 24
Finished May 14 01:39:50 PM PDT 24
Peak memory 246576 kb
Host smart-78561898-9a1d-4ace-b0ad-3fe550b2f6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092203826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3092203826
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1396911872
Short name T350
Test name
Test status
Simulation time 63797592 ps
CPU time 7.36 seconds
Started May 14 01:39:30 PM PDT 24
Finished May 14 01:39:39 PM PDT 24
Peak memory 251032 kb
Host smart-1067122f-c783-4fd3-a44f-e39e58fc81fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396911872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1396911872
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1610465132
Short name T762
Test name
Test status
Simulation time 19011698399 ps
CPU time 160.6 seconds
Started May 14 01:39:28 PM PDT 24
Finished May 14 01:42:10 PM PDT 24
Peak memory 226220 kb
Host smart-5971fd7a-856b-4927-9ea9-0fd64c76de15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610465132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1610465132
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.825126848
Short name T100
Test name
Test status
Simulation time 16509623431 ps
CPU time 640.15 seconds
Started May 14 01:39:28 PM PDT 24
Finished May 14 01:50:09 PM PDT 24
Peak memory 259464 kb
Host smart-d2dfefde-24e6-4de3-8328-ac006f70f937
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=825126848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.825126848
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2139213054
Short name T641
Test name
Test status
Simulation time 14170455 ps
CPU time 1.07 seconds
Started May 14 01:39:25 PM PDT 24
Finished May 14 01:39:27 PM PDT 24
Peak memory 211748 kb
Host smart-4a6d6915-a415-4d26-b099-4378d925327f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139213054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2139213054
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.2136847566
Short name T322
Test name
Test status
Simulation time 27431202 ps
CPU time 1.24 seconds
Started May 14 01:39:38 PM PDT 24
Finished May 14 01:39:41 PM PDT 24
Peak memory 209688 kb
Host smart-696fc433-fd77-41b2-82f6-45730f12c75e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136847566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2136847566
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.2861936892
Short name T171
Test name
Test status
Simulation time 608627583 ps
CPU time 17.69 seconds
Started May 14 01:39:29 PM PDT 24
Finished May 14 01:39:48 PM PDT 24
Peak memory 218148 kb
Host smart-e18f27e2-8718-4cda-836f-9b37232daf45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861936892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.2861936892
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.4013740801
Short name T29
Test name
Test status
Simulation time 1343034397 ps
CPU time 12.78 seconds
Started May 14 01:39:29 PM PDT 24
Finished May 14 01:39:42 PM PDT 24
Peak memory 209752 kb
Host smart-c43f758c-f373-4281-b8e7-e14d4b1ea39e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013740801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.4013740801
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1516485825
Short name T556
Test name
Test status
Simulation time 211501053 ps
CPU time 2.82 seconds
Started May 14 01:39:27 PM PDT 24
Finished May 14 01:39:31 PM PDT 24
Peak memory 218160 kb
Host smart-ef6222ae-61d6-4f22-94c1-df73068893c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516485825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1516485825
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2923693711
Short name T54
Test name
Test status
Simulation time 1292152239 ps
CPU time 13.71 seconds
Started May 14 01:39:30 PM PDT 24
Finished May 14 01:39:45 PM PDT 24
Peak memory 219108 kb
Host smart-5a5d5550-d2d4-46ac-a499-472b18860a49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923693711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2923693711
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3851607129
Short name T808
Test name
Test status
Simulation time 319559315 ps
CPU time 10.05 seconds
Started May 14 01:39:29 PM PDT 24
Finished May 14 01:39:40 PM PDT 24
Peak memory 218220 kb
Host smart-e4695cee-3a1e-49bf-bfca-2ac55e6b975b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851607129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3851607129
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.657754664
Short name T788
Test name
Test status
Simulation time 201472411 ps
CPU time 8.54 seconds
Started May 14 01:39:29 PM PDT 24
Finished May 14 01:39:38 PM PDT 24
Peak memory 218200 kb
Host smart-e8fb69ad-9a76-455d-98fd-2bb6b235f42a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657754664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.657754664
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2451291969
Short name T20
Test name
Test status
Simulation time 1329887036 ps
CPU time 13.08 seconds
Started May 14 01:39:32 PM PDT 24
Finished May 14 01:39:46 PM PDT 24
Peak memory 218208 kb
Host smart-c827a5b2-fd65-4c7f-9e49-99f536e3a3f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451291969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2451291969
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1299113500
Short name T51
Test name
Test status
Simulation time 25535766 ps
CPU time 1.92 seconds
Started May 14 01:39:29 PM PDT 24
Finished May 14 01:39:32 PM PDT 24
Peak memory 213924 kb
Host smart-f49d8c17-bb2c-44c7-8056-5b13a334f36b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299113500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1299113500
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3207841350
Short name T485
Test name
Test status
Simulation time 192659432 ps
CPU time 19.16 seconds
Started May 14 01:39:33 PM PDT 24
Finished May 14 01:39:53 PM PDT 24
Peak memory 251120 kb
Host smart-064bbe2b-37da-4b23-9930-2f72a5e107dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207841350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3207841350
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1196520123
Short name T616
Test name
Test status
Simulation time 312963175 ps
CPU time 9.99 seconds
Started May 14 01:39:28 PM PDT 24
Finished May 14 01:39:39 PM PDT 24
Peak memory 251132 kb
Host smart-dbad2091-9560-4086-b662-6ce0e27b6e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196520123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1196520123
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.3167975258
Short name T671
Test name
Test status
Simulation time 5983581207 ps
CPU time 111.03 seconds
Started May 14 01:39:37 PM PDT 24
Finished May 14 01:41:30 PM PDT 24
Peak memory 251212 kb
Host smart-159aafb7-985e-4851-8bb3-31cd53fa652a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167975258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.3167975258
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all_with_rand_reset.672251999
Short name T73
Test name
Test status
Simulation time 39402349986 ps
CPU time 704.95 seconds
Started May 14 01:39:43 PM PDT 24
Finished May 14 01:51:29 PM PDT 24
Peak memory 316708 kb
Host smart-d543461a-d609-49dd-8ae9-4d969a244979
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=672251999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_stress_all_with_rand_reset.672251999
Directory /workspace/33.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2875242110
Short name T767
Test name
Test status
Simulation time 47691324 ps
CPU time 0.91 seconds
Started May 14 01:39:30 PM PDT 24
Finished May 14 01:39:32 PM PDT 24
Peak memory 211976 kb
Host smart-4c442929-8b60-42db-8c45-f9c14214707a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875242110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2875242110
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1746303098
Short name T665
Test name
Test status
Simulation time 32411616 ps
CPU time 0.99 seconds
Started May 14 01:39:36 PM PDT 24
Finished May 14 01:39:38 PM PDT 24
Peak memory 209672 kb
Host smart-b8a003c9-3b21-492e-a459-233a7695a41c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746303098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1746303098
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1055493876
Short name T841
Test name
Test status
Simulation time 348248924 ps
CPU time 14.61 seconds
Started May 14 01:39:43 PM PDT 24
Finished May 14 01:39:59 PM PDT 24
Peak memory 218160 kb
Host smart-4dc65ed1-22a1-4cbe-978e-9c4f56eaf11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055493876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1055493876
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.447161534
Short name T592
Test name
Test status
Simulation time 80291640 ps
CPU time 1.82 seconds
Started May 14 01:39:39 PM PDT 24
Finished May 14 01:39:42 PM PDT 24
Peak memory 209764 kb
Host smart-e3c4ccd6-7787-4767-b5bc-e22025d361c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447161534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.447161534
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2471722348
Short name T170
Test name
Test status
Simulation time 331965028 ps
CPU time 2.99 seconds
Started May 14 01:39:37 PM PDT 24
Finished May 14 01:39:42 PM PDT 24
Peak memory 218144 kb
Host smart-7a677024-a074-4331-b4d0-73fd8c0293a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471722348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2471722348
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.2348710163
Short name T551
Test name
Test status
Simulation time 601626899 ps
CPU time 14.34 seconds
Started May 14 01:39:38 PM PDT 24
Finished May 14 01:39:54 PM PDT 24
Peak memory 219056 kb
Host smart-0e98305d-bcb0-488f-88df-cd31d85d530b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348710163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2348710163
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3140193034
Short name T578
Test name
Test status
Simulation time 1401952465 ps
CPU time 10.79 seconds
Started May 14 01:39:38 PM PDT 24
Finished May 14 01:39:50 PM PDT 24
Peak memory 218176 kb
Host smart-0b1d3ae0-e244-44ee-8bf8-4f7b1b325a70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140193034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3140193034
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1613856838
Short name T222
Test name
Test status
Simulation time 1415184487 ps
CPU time 9.19 seconds
Started May 14 01:39:35 PM PDT 24
Finished May 14 01:39:45 PM PDT 24
Peak memory 218124 kb
Host smart-c4bfc6b6-3736-47bd-8569-72db79d266d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613856838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
1613856838
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1620756231
Short name T333
Test name
Test status
Simulation time 672768925 ps
CPU time 10.17 seconds
Started May 14 01:39:37 PM PDT 24
Finished May 14 01:39:49 PM PDT 24
Peak memory 218436 kb
Host smart-2bcdc998-7191-4927-959a-28249435a324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620756231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1620756231
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3836386975
Short name T58
Test name
Test status
Simulation time 66975751 ps
CPU time 3.66 seconds
Started May 14 01:39:39 PM PDT 24
Finished May 14 01:39:43 PM PDT 24
Peak memory 217916 kb
Host smart-840504c2-bf7d-4c14-bab5-3a504beb9f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836386975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3836386975
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.434752676
Short name T605
Test name
Test status
Simulation time 1447972477 ps
CPU time 24.03 seconds
Started May 14 01:39:37 PM PDT 24
Finished May 14 01:40:02 PM PDT 24
Peak memory 249672 kb
Host smart-100e7cf0-db6e-49d8-827b-2a95e13676cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434752676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.434752676
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1515069348
Short name T705
Test name
Test status
Simulation time 45394091 ps
CPU time 2.76 seconds
Started May 14 01:39:36 PM PDT 24
Finished May 14 01:39:41 PM PDT 24
Peak memory 222120 kb
Host smart-e6ce9187-998b-4044-8e9d-6b22bcbd1687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515069348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1515069348
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2074431324
Short name T242
Test name
Test status
Simulation time 31651416641 ps
CPU time 168.07 seconds
Started May 14 01:39:37 PM PDT 24
Finished May 14 01:42:26 PM PDT 24
Peak memory 292072 kb
Host smart-5a4e7c2c-f837-43ef-b097-3f666f4bc08c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074431324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2074431324
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.1495369963
Short name T176
Test name
Test status
Simulation time 79002393564 ps
CPU time 503.41 seconds
Started May 14 01:39:36 PM PDT 24
Finished May 14 01:48:01 PM PDT 24
Peak memory 290264 kb
Host smart-9773fab8-0dfc-4c15-88c4-1f08dd2dd073
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1495369963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.1495369963
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.120469464
Short name T317
Test name
Test status
Simulation time 20529445 ps
CPU time 0.99 seconds
Started May 14 01:39:36 PM PDT 24
Finished May 14 01:39:38 PM PDT 24
Peak memory 211716 kb
Host smart-453470f5-a253-4237-959b-f38e4ec6be31
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120469464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ct
rl_volatile_unlock_smoke.120469464
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.990473861
Short name T84
Test name
Test status
Simulation time 198869641 ps
CPU time 1.42 seconds
Started May 14 01:39:39 PM PDT 24
Finished May 14 01:39:41 PM PDT 24
Peak memory 209732 kb
Host smart-8f697e32-993a-40a5-b8f4-7d6987078d08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990473861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.990473861
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.239311975
Short name T582
Test name
Test status
Simulation time 436542237 ps
CPU time 12.04 seconds
Started May 14 01:39:36 PM PDT 24
Finished May 14 01:39:50 PM PDT 24
Peak memory 218024 kb
Host smart-6f22ba2d-a183-45ef-a35f-f060bc06aaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239311975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.239311975
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3470985586
Short name T858
Test name
Test status
Simulation time 163442286 ps
CPU time 5.05 seconds
Started May 14 01:39:35 PM PDT 24
Finished May 14 01:39:41 PM PDT 24
Peak memory 209756 kb
Host smart-8304ed83-77f3-4916-9f17-58f711e58eba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470985586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3470985586
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2097424331
Short name T677
Test name
Test status
Simulation time 28408173 ps
CPU time 1.46 seconds
Started May 14 01:39:36 PM PDT 24
Finished May 14 01:39:39 PM PDT 24
Peak memory 218160 kb
Host smart-b8072cc7-084f-438c-bbaa-ad623903b39e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097424331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2097424331
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1751017214
Short name T787
Test name
Test status
Simulation time 1187189196 ps
CPU time 15.56 seconds
Started May 14 01:39:36 PM PDT 24
Finished May 14 01:39:54 PM PDT 24
Peak memory 219088 kb
Host smart-fe5e4456-eb68-47b1-b7ae-f9347791646f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751017214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1751017214
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.174230576
Short name T514
Test name
Test status
Simulation time 232079477 ps
CPU time 6.9 seconds
Started May 14 01:39:37 PM PDT 24
Finished May 14 01:39:46 PM PDT 24
Peak memory 218224 kb
Host smart-8414513f-61e0-476b-9c50-697ec37de98b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174230576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.174230576
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1747702129
Short name T469
Test name
Test status
Simulation time 1888055800 ps
CPU time 8.83 seconds
Started May 14 01:39:36 PM PDT 24
Finished May 14 01:39:46 PM PDT 24
Peak memory 218176 kb
Host smart-4ff8b4b8-76d6-4a72-95f6-732e3cc8b64a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747702129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1747702129
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.178318276
Short name T868
Test name
Test status
Simulation time 1354025499 ps
CPU time 11.98 seconds
Started May 14 01:39:43 PM PDT 24
Finished May 14 01:39:56 PM PDT 24
Peak memory 226264 kb
Host smart-46e362e1-7ccd-4fe8-8d00-0017bdcf8348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178318276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.178318276
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.949413203
Short name T88
Test name
Test status
Simulation time 486378511 ps
CPU time 4.69 seconds
Started May 14 01:39:37 PM PDT 24
Finished May 14 01:39:43 PM PDT 24
Peak memory 218088 kb
Host smart-d7d42893-81fe-43a9-b980-539f48d27db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949413203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.949413203
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.1502981458
Short name T465
Test name
Test status
Simulation time 292818596 ps
CPU time 31.82 seconds
Started May 14 01:39:43 PM PDT 24
Finished May 14 01:40:16 PM PDT 24
Peak memory 251148 kb
Host smart-4c63a342-f280-451e-8a6b-47a3b94557ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502981458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.1502981458
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.444506992
Short name T385
Test name
Test status
Simulation time 229404916 ps
CPU time 6.4 seconds
Started May 14 01:39:36 PM PDT 24
Finished May 14 01:39:43 PM PDT 24
Peak memory 251008 kb
Host smart-03d66e08-0a8e-47e6-b808-58d5192c1e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444506992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.444506992
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.811552869
Short name T819
Test name
Test status
Simulation time 12915680130 ps
CPU time 86.81 seconds
Started May 14 01:39:36 PM PDT 24
Finished May 14 01:41:05 PM PDT 24
Peak memory 269756 kb
Host smart-edd0934d-59c9-4894-af8c-e787a739440a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811552869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.811552869
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2274979267
Short name T354
Test name
Test status
Simulation time 31006591 ps
CPU time 0.93 seconds
Started May 14 01:39:36 PM PDT 24
Finished May 14 01:39:39 PM PDT 24
Peak memory 211856 kb
Host smart-522381f8-00c0-442b-abcc-4c3ccdec814d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274979267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2274979267
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.2119152277
Short name T780
Test name
Test status
Simulation time 27330280 ps
CPU time 0.87 seconds
Started May 14 01:39:45 PM PDT 24
Finished May 14 01:39:48 PM PDT 24
Peak memory 209520 kb
Host smart-155ba609-77c9-4302-9558-0c600fabb3e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119152277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2119152277
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3672927853
Short name T781
Test name
Test status
Simulation time 1761546958 ps
CPU time 13.88 seconds
Started May 14 01:39:51 PM PDT 24
Finished May 14 01:40:06 PM PDT 24
Peak memory 218144 kb
Host smart-3f90dad8-7924-444f-867e-e5cfb24d9ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672927853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3672927853
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1529799351
Short name T726
Test name
Test status
Simulation time 35541246 ps
CPU time 1.19 seconds
Started May 14 01:39:44 PM PDT 24
Finished May 14 01:39:47 PM PDT 24
Peak memory 209716 kb
Host smart-9ac58ec0-fe3d-4d95-be2b-ec239909568d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529799351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1529799351
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.86912300
Short name T178
Test name
Test status
Simulation time 230046071 ps
CPU time 3.15 seconds
Started May 14 01:39:43 PM PDT 24
Finished May 14 01:39:48 PM PDT 24
Peak memory 218156 kb
Host smart-227f9312-1c77-4805-88b4-60187279f2b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86912300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.86912300
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.2455778644
Short name T730
Test name
Test status
Simulation time 503193179 ps
CPU time 11.6 seconds
Started May 14 01:39:43 PM PDT 24
Finished May 14 01:39:55 PM PDT 24
Peak memory 218236 kb
Host smart-5963ddd5-d83b-4f4b-96ef-15e58adf86a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455778644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.2455778644
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.2636464190
Short name T626
Test name
Test status
Simulation time 522611991 ps
CPU time 14.72 seconds
Started May 14 01:39:46 PM PDT 24
Finished May 14 01:40:03 PM PDT 24
Peak memory 218128 kb
Host smart-4efee06f-702a-451c-90fe-918f098b5a18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636464190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.2636464190
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.977259021
Short name T685
Test name
Test status
Simulation time 548943697 ps
CPU time 11.44 seconds
Started May 14 01:39:45 PM PDT 24
Finished May 14 01:39:58 PM PDT 24
Peak memory 218164 kb
Host smart-bcabd53e-3f3c-47aa-970c-0ed0b7a3267e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977259021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.977259021
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.1529989458
Short name T406
Test name
Test status
Simulation time 456716649 ps
CPU time 10.74 seconds
Started May 14 01:39:44 PM PDT 24
Finished May 14 01:39:57 PM PDT 24
Peak memory 218172 kb
Host smart-d72070ca-cfd6-4fd8-9001-959d57517c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529989458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.1529989458
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1454726866
Short name T271
Test name
Test status
Simulation time 259225411 ps
CPU time 1.77 seconds
Started May 14 01:39:44 PM PDT 24
Finished May 14 01:39:47 PM PDT 24
Peak memory 213696 kb
Host smart-2bcdd2d3-28e5-4e23-9a4c-f22c7aba694f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454726866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1454726866
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.1252973379
Short name T713
Test name
Test status
Simulation time 3291019496 ps
CPU time 30.28 seconds
Started May 14 01:39:47 PM PDT 24
Finished May 14 01:40:19 PM PDT 24
Peak memory 250944 kb
Host smart-f92666d5-54b2-4d15-be74-9f6cbd43af12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252973379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.1252973379
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2236773767
Short name T247
Test name
Test status
Simulation time 123062238 ps
CPU time 7.28 seconds
Started May 14 01:39:46 PM PDT 24
Finished May 14 01:39:55 PM PDT 24
Peak memory 248464 kb
Host smart-a71e747e-85c1-4871-a7ba-54c6ab59ca89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236773767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2236773767
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2832942350
Short name T75
Test name
Test status
Simulation time 14630174290 ps
CPU time 74.35 seconds
Started May 14 01:39:43 PM PDT 24
Finished May 14 01:40:59 PM PDT 24
Peak memory 218132 kb
Host smart-548cd648-2d5e-4764-b5a8-4edaa5e7c7bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832942350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2832942350
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.1713370906
Short name T93
Test name
Test status
Simulation time 17047112828 ps
CPU time 621.62 seconds
Started May 14 01:39:45 PM PDT 24
Finished May 14 01:50:09 PM PDT 24
Peak memory 342580 kb
Host smart-71f23998-f4e4-4829-a0c0-a61f91e831f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1713370906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.1713370906
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3038966605
Short name T155
Test name
Test status
Simulation time 53987632 ps
CPU time 0.97 seconds
Started May 14 01:39:44 PM PDT 24
Finished May 14 01:39:46 PM PDT 24
Peak memory 212764 kb
Host smart-4cbcf2e1-32f9-4cb9-b078-1a227d8c8e86
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038966605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.3038966605
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2209279036
Short name T63
Test name
Test status
Simulation time 27102235 ps
CPU time 1.09 seconds
Started May 14 01:39:51 PM PDT 24
Finished May 14 01:39:53 PM PDT 24
Peak memory 209712 kb
Host smart-81f6b71f-f9bb-4644-a24e-3cbc3c315caf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209279036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2209279036
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.885002619
Short name T426
Test name
Test status
Simulation time 1434913457 ps
CPU time 17.87 seconds
Started May 14 01:39:45 PM PDT 24
Finished May 14 01:40:04 PM PDT 24
Peak memory 218232 kb
Host smart-6602253e-fc71-46d2-ae64-0b7c16968eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885002619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.885002619
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1365549515
Short name T572
Test name
Test status
Simulation time 840005878 ps
CPU time 3.3 seconds
Started May 14 01:39:44 PM PDT 24
Finished May 14 01:39:50 PM PDT 24
Peak memory 209736 kb
Host smart-d4d5822f-74ea-4b40-9f9e-b08541df1dcb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365549515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1365549515
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.1965461356
Short name T782
Test name
Test status
Simulation time 211586573 ps
CPU time 4.11 seconds
Started May 14 01:39:46 PM PDT 24
Finished May 14 01:39:52 PM PDT 24
Peak memory 218376 kb
Host smart-ee31378f-d4ec-4851-a2c3-2c9e925bc9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965461356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1965461356
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2729091167
Short name T737
Test name
Test status
Simulation time 1035517512 ps
CPU time 10.38 seconds
Started May 14 01:39:45 PM PDT 24
Finished May 14 01:39:58 PM PDT 24
Peak memory 218156 kb
Host smart-e4bf38f6-5ea6-4e64-9cea-ba98f2081db2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729091167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2729091167
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.536794504
Short name T800
Test name
Test status
Simulation time 1699085145 ps
CPU time 11.49 seconds
Started May 14 01:39:44 PM PDT 24
Finished May 14 01:39:57 PM PDT 24
Peak memory 218124 kb
Host smart-7f31563b-80cb-44df-bea5-0205228e3009
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536794504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.536794504
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.549073916
Short name T414
Test name
Test status
Simulation time 524333421 ps
CPU time 16.91 seconds
Started May 14 01:39:45 PM PDT 24
Finished May 14 01:40:04 PM PDT 24
Peak memory 218116 kb
Host smart-47dc3e4f-7793-43b0-abd3-752cebad70a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549073916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.549073916
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3239823227
Short name T211
Test name
Test status
Simulation time 1156667362 ps
CPU time 10.07 seconds
Started May 14 01:39:45 PM PDT 24
Finished May 14 01:39:57 PM PDT 24
Peak memory 218192 kb
Host smart-ddd22a4f-3740-422f-85bc-b81fbe0ee7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239823227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3239823227
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.4073401498
Short name T149
Test name
Test status
Simulation time 700644183 ps
CPU time 7.66 seconds
Started May 14 01:39:47 PM PDT 24
Finished May 14 01:39:56 PM PDT 24
Peak memory 217928 kb
Host smart-2db2f9d6-926e-4c97-94d4-3f8f1c529bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073401498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.4073401498
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.2653478616
Short name T565
Test name
Test status
Simulation time 508245608 ps
CPU time 31.7 seconds
Started May 14 01:39:44 PM PDT 24
Finished May 14 01:40:18 PM PDT 24
Peak memory 248744 kb
Host smart-f76f2790-acb8-42cc-a646-0e446a68a907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653478616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.2653478616
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3287558927
Short name T831
Test name
Test status
Simulation time 97279657 ps
CPU time 6.52 seconds
Started May 14 01:39:43 PM PDT 24
Finished May 14 01:39:50 PM PDT 24
Peak memory 246568 kb
Host smart-4b0fcb30-e9eb-4e50-8fb4-31f502838aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287558927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3287558927
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2746374973
Short name T771
Test name
Test status
Simulation time 1249626245 ps
CPU time 14.46 seconds
Started May 14 01:39:51 PM PDT 24
Finished May 14 01:40:07 PM PDT 24
Peak memory 226248 kb
Host smart-79505a2f-0857-4827-869c-ecdfedb34ea0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746374973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2746374973
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3526785912
Short name T622
Test name
Test status
Simulation time 43702419 ps
CPU time 1.02 seconds
Started May 14 01:39:44 PM PDT 24
Finished May 14 01:39:46 PM PDT 24
Peak memory 211816 kb
Host smart-212ccdd4-53e8-450f-b8ce-6d60adaaa194
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526785912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3526785912
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3789105885
Short name T81
Test name
Test status
Simulation time 14134656 ps
CPU time 1.06 seconds
Started May 14 01:39:52 PM PDT 24
Finished May 14 01:39:54 PM PDT 24
Peak memory 209692 kb
Host smart-57b7d81f-1dfe-43a7-8bd7-f25e351378c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789105885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3789105885
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.3147236268
Short name T342
Test name
Test status
Simulation time 624136944 ps
CPU time 17.77 seconds
Started May 14 01:39:51 PM PDT 24
Finished May 14 01:40:10 PM PDT 24
Peak memory 218148 kb
Host smart-69e6723e-9fb3-42a6-82cd-f55f86269e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147236268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.3147236268
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1854591190
Short name T174
Test name
Test status
Simulation time 512471085 ps
CPU time 1.95 seconds
Started May 14 01:39:51 PM PDT 24
Finished May 14 01:39:54 PM PDT 24
Peak memory 217000 kb
Host smart-8836fa8f-6ffc-4dd5-8a69-0533abb3eefc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854591190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1854591190
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3130033134
Short name T398
Test name
Test status
Simulation time 119014153 ps
CPU time 1.89 seconds
Started May 14 01:39:47 PM PDT 24
Finished May 14 01:39:50 PM PDT 24
Peak memory 218072 kb
Host smart-746c6946-81c8-43b5-80c6-55230e3220b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130033134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3130033134
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1256731618
Short name T156
Test name
Test status
Simulation time 583917165 ps
CPU time 14.46 seconds
Started May 14 01:39:51 PM PDT 24
Finished May 14 01:40:07 PM PDT 24
Peak memory 219052 kb
Host smart-b07e2e70-dc4f-494f-ace2-5108d6fd2c08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256731618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1256731618
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.4149826001
Short name T588
Test name
Test status
Simulation time 1117864271 ps
CPU time 9.08 seconds
Started May 14 01:39:51 PM PDT 24
Finished May 14 01:40:01 PM PDT 24
Peak memory 218256 kb
Host smart-f2b97e83-1ce9-47b4-92a5-3c175e30b750
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149826001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.4149826001
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.771879475
Short name T690
Test name
Test status
Simulation time 1785923796 ps
CPU time 10.12 seconds
Started May 14 01:39:51 PM PDT 24
Finished May 14 01:40:02 PM PDT 24
Peak memory 218176 kb
Host smart-334aec4a-d5c1-4293-b31e-28082b4d7cf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771879475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.771879475
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.3949253802
Short name T735
Test name
Test status
Simulation time 1373114497 ps
CPU time 6.7 seconds
Started May 14 01:39:47 PM PDT 24
Finished May 14 01:39:55 PM PDT 24
Peak memory 224736 kb
Host smart-7a5e56bc-63b2-49ed-8e4a-aba36f8f48f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949253802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.3949253802
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.877110532
Short name T86
Test name
Test status
Simulation time 24943874 ps
CPU time 1.62 seconds
Started May 14 01:39:45 PM PDT 24
Finished May 14 01:39:48 PM PDT 24
Peak memory 213532 kb
Host smart-a563b396-6ae1-4ac2-aecb-ca7637cac473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877110532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.877110532
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1725001040
Short name T786
Test name
Test status
Simulation time 431139929 ps
CPU time 34.05 seconds
Started May 14 01:39:46 PM PDT 24
Finished May 14 01:40:22 PM PDT 24
Peak memory 250944 kb
Host smart-391aacbc-05f3-4e0b-a8c7-cdec4e5fb86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725001040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1725001040
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3298141000
Short name T253
Test name
Test status
Simulation time 231490933 ps
CPU time 6.27 seconds
Started May 14 01:39:44 PM PDT 24
Finished May 14 01:39:52 PM PDT 24
Peak memory 251096 kb
Host smart-e3b8141d-5871-4c34-a581-ed1cd2c1c697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298141000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3298141000
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3130186514
Short name T503
Test name
Test status
Simulation time 8371568654 ps
CPU time 144.88 seconds
Started May 14 01:39:54 PM PDT 24
Finished May 14 01:42:20 PM PDT 24
Peak memory 280580 kb
Host smart-b8ead5d2-d1fd-4e1e-b384-123b5eba9ffd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130186514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3130186514
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.2752453091
Short name T95
Test name
Test status
Simulation time 139018259100 ps
CPU time 1461.9 seconds
Started May 14 01:39:53 PM PDT 24
Finished May 14 02:04:17 PM PDT 24
Peak memory 497000 kb
Host smart-951ba8d2-d5b9-441f-a74e-3d29d8267da0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2752453091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.2752453091
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3289104221
Short name T832
Test name
Test status
Simulation time 121430038 ps
CPU time 0.85 seconds
Started May 14 01:39:46 PM PDT 24
Finished May 14 01:39:49 PM PDT 24
Peak memory 211724 kb
Host smart-6c667923-fa55-491a-8899-9ffb83ad310b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289104221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3289104221
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.220217404
Short name T587
Test name
Test status
Simulation time 19951125 ps
CPU time 1.21 seconds
Started May 14 01:39:58 PM PDT 24
Finished May 14 01:40:01 PM PDT 24
Peak memory 209752 kb
Host smart-7c7538a4-23ae-4ef5-8ad9-0a3a123dc639
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220217404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.220217404
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3888870810
Short name T286
Test name
Test status
Simulation time 845332586 ps
CPU time 10.76 seconds
Started May 14 01:39:50 PM PDT 24
Finished May 14 01:40:01 PM PDT 24
Peak memory 218060 kb
Host smart-efd52301-0b66-43a5-8860-4e67ef98fa5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888870810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3888870810
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3649107325
Short name T640
Test name
Test status
Simulation time 151614724 ps
CPU time 2.73 seconds
Started May 14 01:39:52 PM PDT 24
Finished May 14 01:39:56 PM PDT 24
Peak memory 209772 kb
Host smart-5bc884f6-c72a-40fb-8dbe-df93c48d8eaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649107325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3649107325
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.4170994913
Short name T261
Test name
Test status
Simulation time 71727506 ps
CPU time 3.55 seconds
Started May 14 01:39:51 PM PDT 24
Finished May 14 01:39:56 PM PDT 24
Peak memory 218144 kb
Host smart-01095625-03f6-4c7f-9c61-745b0aeee09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170994913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.4170994913
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.1920708946
Short name T321
Test name
Test status
Simulation time 3119913325 ps
CPU time 18.89 seconds
Started May 14 01:39:51 PM PDT 24
Finished May 14 01:40:11 PM PDT 24
Peak memory 226240 kb
Host smart-788f0910-ea1b-45a8-b68a-cf6fc25500a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920708946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.1920708946
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1882653091
Short name T288
Test name
Test status
Simulation time 1266011875 ps
CPU time 10.58 seconds
Started May 14 01:39:57 PM PDT 24
Finished May 14 01:40:09 PM PDT 24
Peak memory 218144 kb
Host smart-041ea7da-3a07-4537-938e-b81fcc7b29f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882653091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.1882653091
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2655546318
Short name T161
Test name
Test status
Simulation time 474644326 ps
CPU time 16.8 seconds
Started May 14 01:39:51 PM PDT 24
Finished May 14 01:40:08 PM PDT 24
Peak memory 218196 kb
Host smart-2f90d2fe-e3ac-43aa-a0bc-194fd14e9c06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655546318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2655546318
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.2857812241
Short name T728
Test name
Test status
Simulation time 594727657 ps
CPU time 11.63 seconds
Started May 14 01:39:52 PM PDT 24
Finished May 14 01:40:05 PM PDT 24
Peak memory 218212 kb
Host smart-495d328d-8edb-473f-a000-553baa5d2d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857812241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.2857812241
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.721832512
Short name T700
Test name
Test status
Simulation time 74808216 ps
CPU time 2.82 seconds
Started May 14 01:39:54 PM PDT 24
Finished May 14 01:39:58 PM PDT 24
Peak memory 214076 kb
Host smart-a85f3b18-ad15-47a1-8ea0-85a1b34c90f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721832512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.721832512
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2279103700
Short name T667
Test name
Test status
Simulation time 1550012636 ps
CPU time 23.42 seconds
Started May 14 01:39:51 PM PDT 24
Finished May 14 01:40:16 PM PDT 24
Peak memory 249336 kb
Host smart-8e5e55c0-578a-4991-a4ab-b532eb89b50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279103700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2279103700
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.529701468
Short name T440
Test name
Test status
Simulation time 95687787 ps
CPU time 3.66 seconds
Started May 14 01:39:51 PM PDT 24
Finished May 14 01:39:56 PM PDT 24
Peak memory 222572 kb
Host smart-c9e4b7d1-bea8-4a6b-bb0c-561d06ec052b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529701468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.529701468
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3533930601
Short name T358
Test name
Test status
Simulation time 17955875765 ps
CPU time 275.45 seconds
Started May 14 01:40:00 PM PDT 24
Finished May 14 01:44:36 PM PDT 24
Peak memory 251200 kb
Host smart-f761b4af-a4ec-4bc7-9587-6f918e1ffd2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533930601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3533930601
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.2350288992
Short name T135
Test name
Test status
Simulation time 120450320082 ps
CPU time 561.45 seconds
Started May 14 01:39:58 PM PDT 24
Finished May 14 01:49:21 PM PDT 24
Peak memory 496944 kb
Host smart-49ddd53b-c58c-48fa-a3e4-68fbd2fa8f3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2350288992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.2350288992
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1544915521
Short name T639
Test name
Test status
Simulation time 31291771 ps
CPU time 0.94 seconds
Started May 14 01:39:52 PM PDT 24
Finished May 14 01:39:54 PM PDT 24
Peak memory 211812 kb
Host smart-255b9aad-beb7-4fb5-8a05-3199a5760abc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544915521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1544915521
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2155881784
Short name T296
Test name
Test status
Simulation time 105138110 ps
CPU time 0.97 seconds
Started May 14 01:36:54 PM PDT 24
Finished May 14 01:36:56 PM PDT 24
Peak memory 209740 kb
Host smart-b3e492b3-8dab-4ee4-886e-02e3afdc3160
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155881784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2155881784
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.4262172974
Short name T252
Test name
Test status
Simulation time 139880304 ps
CPU time 0.91 seconds
Started May 14 01:36:50 PM PDT 24
Finished May 14 01:36:52 PM PDT 24
Peak memory 209312 kb
Host smart-dbb35512-d8d2-4b06-94f1-3dfefef45112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262172974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.4262172974
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3298471098
Short name T373
Test name
Test status
Simulation time 321860601 ps
CPU time 8.77 seconds
Started May 14 01:36:48 PM PDT 24
Finished May 14 01:36:58 PM PDT 24
Peak memory 218128 kb
Host smart-bfbee20a-1081-4162-a668-7a52610e9436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298471098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3298471098
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.2317790345
Short name T200
Test name
Test status
Simulation time 133234878 ps
CPU time 1.15 seconds
Started May 14 01:36:54 PM PDT 24
Finished May 14 01:36:56 PM PDT 24
Peak memory 217012 kb
Host smart-fdced042-07a7-45bc-b0ee-916fd0482d0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317790345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.2317790345
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.1574282213
Short name T273
Test name
Test status
Simulation time 2452602380 ps
CPU time 40.14 seconds
Started May 14 01:36:54 PM PDT 24
Finished May 14 01:37:35 PM PDT 24
Peak memory 218288 kb
Host smart-d69f029b-8b23-489f-a4fc-bed2bc4bf66d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574282213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.1574282213
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.2916193050
Short name T763
Test name
Test status
Simulation time 1229110524 ps
CPU time 12.65 seconds
Started May 14 01:36:57 PM PDT 24
Finished May 14 01:37:10 PM PDT 24
Peak memory 217740 kb
Host smart-c8b3d046-fbcd-4618-812d-b8ea3ed8c86a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916193050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.2
916193050
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.4082819276
Short name T389
Test name
Test status
Simulation time 471581612 ps
CPU time 14.61 seconds
Started May 14 01:36:54 PM PDT 24
Finished May 14 01:37:09 PM PDT 24
Peak memory 218176 kb
Host smart-ee64413a-f7d6-4d0d-91c2-b9aa51d1db43
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082819276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.4082819276
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.320317815
Short name T263
Test name
Test status
Simulation time 876502202 ps
CPU time 15.25 seconds
Started May 14 01:36:57 PM PDT 24
Finished May 14 01:37:13 PM PDT 24
Peak memory 213456 kb
Host smart-d5a9f3d4-4851-43e1-92a9-1c91a1555bcf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320317815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.320317815
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3792580371
Short name T77
Test name
Test status
Simulation time 3460143479 ps
CPU time 7.1 seconds
Started May 14 01:36:46 PM PDT 24
Finished May 14 01:36:54 PM PDT 24
Peak memory 214340 kb
Host smart-08d859e7-cf51-4399-a94c-50699d757d47
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792580371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3792580371
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1238894188
Short name T759
Test name
Test status
Simulation time 1040679477 ps
CPU time 23.62 seconds
Started May 14 01:36:46 PM PDT 24
Finished May 14 01:37:11 PM PDT 24
Peak memory 251144 kb
Host smart-8c5b8f74-d695-4fb1-befd-28f3f08f2e55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238894188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1238894188
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2400844215
Short name T854
Test name
Test status
Simulation time 528851703 ps
CPU time 21.32 seconds
Started May 14 01:36:55 PM PDT 24
Finished May 14 01:37:18 PM PDT 24
Peak memory 247920 kb
Host smart-99e22734-e936-4f85-8a93-1e3ad1c165d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400844215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2400844215
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.479319445
Short name T219
Test name
Test status
Simulation time 111500176 ps
CPU time 3.32 seconds
Started May 14 01:36:45 PM PDT 24
Finished May 14 01:36:49 PM PDT 24
Peak memory 218144 kb
Host smart-194cb417-502b-4a95-901d-832e81c7b23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479319445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.479319445
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.690930241
Short name T60
Test name
Test status
Simulation time 192692969 ps
CPU time 10.73 seconds
Started May 14 01:36:50 PM PDT 24
Finished May 14 01:37:02 PM PDT 24
Peak memory 214328 kb
Host smart-94919015-4922-4670-9a7c-b5490b6a0b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690930241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.690930241
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1479245303
Short name T83
Test name
Test status
Simulation time 396464524 ps
CPU time 37.3 seconds
Started May 14 01:36:55 PM PDT 24
Finished May 14 01:37:34 PM PDT 24
Peak memory 281944 kb
Host smart-3224863f-0add-437c-873c-190961e714e0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479245303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1479245303
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.738760911
Short name T446
Test name
Test status
Simulation time 341288570 ps
CPU time 16.5 seconds
Started May 14 01:36:54 PM PDT 24
Finished May 14 01:37:11 PM PDT 24
Peak memory 219100 kb
Host smart-4d477b2a-5a46-455d-a32b-2db50804765b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738760911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.738760911
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.4090671502
Short name T442
Test name
Test status
Simulation time 2239207943 ps
CPU time 16.93 seconds
Started May 14 01:36:54 PM PDT 24
Finished May 14 01:37:12 PM PDT 24
Peak memory 218240 kb
Host smart-aab6c0aa-9484-4d59-b312-b3a0246b8d6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090671502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.4090671502
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.616291574
Short name T731
Test name
Test status
Simulation time 1143470361 ps
CPU time 11.73 seconds
Started May 14 01:36:55 PM PDT 24
Finished May 14 01:37:08 PM PDT 24
Peak memory 218140 kb
Host smart-59f7c39c-0838-4112-8d6d-bcfb422b3522
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616291574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.616291574
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1848558850
Short name T820
Test name
Test status
Simulation time 330391023 ps
CPU time 12.57 seconds
Started May 14 01:36:51 PM PDT 24
Finished May 14 01:37:04 PM PDT 24
Peak memory 225644 kb
Host smart-ce8b7553-bfa9-4313-8c6a-94246505ce5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848558850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1848558850
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.2869042004
Short name T490
Test name
Test status
Simulation time 199120527 ps
CPU time 8.1 seconds
Started May 14 01:36:48 PM PDT 24
Finished May 14 01:36:57 PM PDT 24
Peak memory 218080 kb
Host smart-b32f86ca-d72d-451e-9959-24cc6e62dc06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869042004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.2869042004
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.1003053271
Short name T298
Test name
Test status
Simulation time 728139056 ps
CPU time 23.76 seconds
Started May 14 01:36:49 PM PDT 24
Finished May 14 01:37:13 PM PDT 24
Peak memory 246984 kb
Host smart-155b86aa-2c2e-47eb-a73b-985b23a203ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003053271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.1003053271
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.4030110932
Short name T838
Test name
Test status
Simulation time 72079195 ps
CPU time 6.53 seconds
Started May 14 01:36:50 PM PDT 24
Finished May 14 01:36:57 PM PDT 24
Peak memory 247092 kb
Host smart-1feeb00a-4491-42c1-9d13-6c0703bbe77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030110932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.4030110932
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3941833460
Short name T540
Test name
Test status
Simulation time 6182053394 ps
CPU time 196.06 seconds
Started May 14 01:36:53 PM PDT 24
Finished May 14 01:40:10 PM PDT 24
Peak memory 267564 kb
Host smart-77d96156-7cf8-4a70-a8cf-e5f15adb1283
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941833460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3941833460
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.32914581
Short name T663
Test name
Test status
Simulation time 79099371 ps
CPU time 1 seconds
Started May 14 01:36:46 PM PDT 24
Finished May 14 01:36:48 PM PDT 24
Peak memory 211684 kb
Host smart-ed386844-5d44-4dbf-896f-a3cdf5322334
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32914581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_volatile_unlock_smoke.32914581
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1812637380
Short name T166
Test name
Test status
Simulation time 34629935 ps
CPU time 0.98 seconds
Started May 14 01:39:57 PM PDT 24
Finished May 14 01:39:59 PM PDT 24
Peak memory 209740 kb
Host smart-284f2bb9-9717-4343-af63-6c62a9bfbc57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812637380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1812637380
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1081440835
Short name T779
Test name
Test status
Simulation time 1353425147 ps
CPU time 12.39 seconds
Started May 14 01:39:58 PM PDT 24
Finished May 14 01:40:12 PM PDT 24
Peak memory 218132 kb
Host smart-92978d73-94c1-4ec2-b574-b5621c873324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081440835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1081440835
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2683110594
Short name T724
Test name
Test status
Simulation time 738494921 ps
CPU time 7.24 seconds
Started May 14 01:39:57 PM PDT 24
Finished May 14 01:40:05 PM PDT 24
Peak memory 217220 kb
Host smart-e6cea9ed-0852-4c25-b818-975b40dd2b69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683110594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2683110594
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3990335056
Short name T431
Test name
Test status
Simulation time 44852580 ps
CPU time 2.69 seconds
Started May 14 01:39:58 PM PDT 24
Finished May 14 01:40:02 PM PDT 24
Peak memory 218164 kb
Host smart-085e85e5-3a1e-445c-a205-a681b59281db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990335056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3990335056
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.3616592508
Short name T795
Test name
Test status
Simulation time 996218310 ps
CPU time 15.98 seconds
Started May 14 01:39:58 PM PDT 24
Finished May 14 01:40:16 PM PDT 24
Peak memory 226232 kb
Host smart-046ca5e1-d193-4745-8228-0cd8d5c7dd08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616592508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3616592508
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3891561945
Short name T508
Test name
Test status
Simulation time 854485454 ps
CPU time 7.05 seconds
Started May 14 01:39:57 PM PDT 24
Finished May 14 01:40:06 PM PDT 24
Peak memory 218160 kb
Host smart-f473146b-0b79-4c59-8eba-261f7a9b43ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891561945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3891561945
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1855800187
Short name T344
Test name
Test status
Simulation time 1317151748 ps
CPU time 8.32 seconds
Started May 14 01:39:57 PM PDT 24
Finished May 14 01:40:06 PM PDT 24
Peak memory 218072 kb
Host smart-2b0e7d0e-144a-4e45-b321-675a6539ccba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855800187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1855800187
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.4025823638
Short name T518
Test name
Test status
Simulation time 325530016 ps
CPU time 6.31 seconds
Started May 14 01:39:57 PM PDT 24
Finished May 14 01:40:05 PM PDT 24
Peak memory 224868 kb
Host smart-f80dc5b9-0142-49e7-97c6-b880938e1eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025823638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.4025823638
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3809404231
Short name T245
Test name
Test status
Simulation time 2013902434 ps
CPU time 4.54 seconds
Started May 14 01:39:59 PM PDT 24
Finished May 14 01:40:05 PM PDT 24
Peak memory 214756 kb
Host smart-59652711-4a2f-49b0-8ccb-5eceab4e9365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809404231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3809404231
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.2912098909
Short name T230
Test name
Test status
Simulation time 338356305 ps
CPU time 22.42 seconds
Started May 14 01:39:57 PM PDT 24
Finished May 14 01:40:21 PM PDT 24
Peak memory 251096 kb
Host smart-b0f59df1-cd19-4901-b494-87561aa6c099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912098909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2912098909
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3702505357
Short name T545
Test name
Test status
Simulation time 91201741 ps
CPU time 9.87 seconds
Started May 14 01:39:58 PM PDT 24
Finished May 14 01:40:10 PM PDT 24
Peak memory 243824 kb
Host smart-feb76552-536e-495b-a58a-fff533d71921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702505357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3702505357
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1025680536
Short name T847
Test name
Test status
Simulation time 2443614725 ps
CPU time 26.08 seconds
Started May 14 01:39:57 PM PDT 24
Finished May 14 01:40:24 PM PDT 24
Peak memory 247508 kb
Host smart-33fe20ab-d77f-4135-82aa-2565259d7a0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025680536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1025680536
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3027640847
Short name T515
Test name
Test status
Simulation time 24390091 ps
CPU time 0.92 seconds
Started May 14 01:39:57 PM PDT 24
Finished May 14 01:40:00 PM PDT 24
Peak memory 211844 kb
Host smart-1f907d47-a1cc-4179-b93e-839755c45559
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027640847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3027640847
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1676088492
Short name T165
Test name
Test status
Simulation time 35122534 ps
CPU time 1.65 seconds
Started May 14 01:40:05 PM PDT 24
Finished May 14 01:40:09 PM PDT 24
Peak memory 209664 kb
Host smart-7829ef2f-236c-4a53-aabb-ad2858528bee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676088492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1676088492
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3644233805
Short name T812
Test name
Test status
Simulation time 1369417281 ps
CPU time 9.77 seconds
Started May 14 01:39:57 PM PDT 24
Finished May 14 01:40:08 PM PDT 24
Peak memory 218064 kb
Host smart-207ff7ca-fe55-44e3-b126-dc5a9c38fc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644233805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3644233805
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2566196760
Short name T429
Test name
Test status
Simulation time 560602570 ps
CPU time 4.54 seconds
Started May 14 01:40:05 PM PDT 24
Finished May 14 01:40:12 PM PDT 24
Peak memory 209684 kb
Host smart-4a767028-52c5-482e-961c-c4de1ef7cddc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566196760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2566196760
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.319778562
Short name T316
Test name
Test status
Simulation time 126440682 ps
CPU time 3.29 seconds
Started May 14 01:39:59 PM PDT 24
Finished May 14 01:40:04 PM PDT 24
Peak memory 218096 kb
Host smart-b4e82d5c-b8e4-4882-9d9d-d5a6b79fdfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319778562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.319778562
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.557328291
Short name T277
Test name
Test status
Simulation time 610489323 ps
CPU time 14.34 seconds
Started May 14 01:40:05 PM PDT 24
Finished May 14 01:40:21 PM PDT 24
Peak memory 218232 kb
Host smart-5f97f022-dfaf-47d1-b3b4-b96050ad9929
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557328291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.557328291
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2197437868
Short name T395
Test name
Test status
Simulation time 926782263 ps
CPU time 17.66 seconds
Started May 14 01:40:06 PM PDT 24
Finished May 14 01:40:26 PM PDT 24
Peak memory 218192 kb
Host smart-300ce0d1-658c-4d90-9be5-7cd3d6c7d0f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197437868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2197437868
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3059233080
Short name T695
Test name
Test status
Simulation time 224675707 ps
CPU time 6.1 seconds
Started May 14 01:40:05 PM PDT 24
Finished May 14 01:40:13 PM PDT 24
Peak memory 218180 kb
Host smart-5e019699-e02e-42ca-a8f3-72d02289ecbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059233080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3059233080
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.72429033
Short name T212
Test name
Test status
Simulation time 568129122 ps
CPU time 10.88 seconds
Started May 14 01:40:06 PM PDT 24
Finished May 14 01:40:19 PM PDT 24
Peak memory 218180 kb
Host smart-9a3d5397-d505-4bca-9b76-fe7eedbb1ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72429033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.72429033
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2430202144
Short name T785
Test name
Test status
Simulation time 143818057 ps
CPU time 2.76 seconds
Started May 14 01:39:58 PM PDT 24
Finished May 14 01:40:02 PM PDT 24
Peak memory 217908 kb
Host smart-743d0622-018d-42a0-9b54-29b002e8e74e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430202144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2430202144
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.2028063673
Short name T576
Test name
Test status
Simulation time 667053381 ps
CPU time 22.68 seconds
Started May 14 01:39:59 PM PDT 24
Finished May 14 01:40:23 PM PDT 24
Peak memory 251080 kb
Host smart-3b34eeb6-1175-4b2f-8de0-4d346b8b28ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028063673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.2028063673
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.643214012
Short name T722
Test name
Test status
Simulation time 109435496 ps
CPU time 7.95 seconds
Started May 14 01:39:58 PM PDT 24
Finished May 14 01:40:08 PM PDT 24
Peak memory 251152 kb
Host smart-d7f15e65-d269-40b2-afb1-27eed92dbfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643214012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.643214012
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.21191516
Short name T338
Test name
Test status
Simulation time 10666459005 ps
CPU time 171.06 seconds
Started May 14 01:40:05 PM PDT 24
Finished May 14 01:42:58 PM PDT 24
Peak memory 254320 kb
Host smart-ccffaa24-76d5-4e4c-b4f0-37c9872da2f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21191516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
1.lc_ctrl_stress_all.21191516
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.3137908452
Short name T523
Test name
Test status
Simulation time 87725085 ps
CPU time 0.89 seconds
Started May 14 01:39:58 PM PDT 24
Finished May 14 01:40:00 PM PDT 24
Peak memory 211804 kb
Host smart-68d77113-7d04-4919-b63f-469e988536c8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137908452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.3137908452
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1754725696
Short name T154
Test name
Test status
Simulation time 96166726 ps
CPU time 0.96 seconds
Started May 14 01:40:05 PM PDT 24
Finished May 14 01:40:08 PM PDT 24
Peak memory 209708 kb
Host smart-cb2bc453-9869-4d9f-8215-e900f429ad0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754725696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1754725696
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3386158025
Short name T631
Test name
Test status
Simulation time 479644566 ps
CPU time 19.9 seconds
Started May 14 01:40:06 PM PDT 24
Finished May 14 01:40:28 PM PDT 24
Peak memory 218156 kb
Host smart-5ffdc457-8c76-4428-a4f4-3554100233a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386158025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3386158025
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.3621662581
Short name T323
Test name
Test status
Simulation time 774540295 ps
CPU time 10.34 seconds
Started May 14 01:40:06 PM PDT 24
Finished May 14 01:40:18 PM PDT 24
Peak memory 209732 kb
Host smart-7bafbe5b-ab7d-4dc0-ab11-4148a9a6d8b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621662581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.3621662581
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.484139867
Short name T769
Test name
Test status
Simulation time 189461524 ps
CPU time 2.89 seconds
Started May 14 01:40:05 PM PDT 24
Finished May 14 01:40:10 PM PDT 24
Peak memory 218076 kb
Host smart-37005c00-4341-4f12-a6ec-ddb405a20522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484139867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.484139867
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1623833675
Short name T606
Test name
Test status
Simulation time 3014679823 ps
CPU time 18.14 seconds
Started May 14 01:40:06 PM PDT 24
Finished May 14 01:40:26 PM PDT 24
Peak memory 226352 kb
Host smart-390cba6c-034b-41eb-8a02-a77a1e455466
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623833675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1623833675
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.466947510
Short name T488
Test name
Test status
Simulation time 939076598 ps
CPU time 19.54 seconds
Started May 14 01:40:04 PM PDT 24
Finished May 14 01:40:25 PM PDT 24
Peak memory 218140 kb
Host smart-fc64aaff-c987-4670-ad52-d6be8883c6d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466947510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_di
gest.466947510
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2216364655
Short name T867
Test name
Test status
Simulation time 2981105843 ps
CPU time 15.02 seconds
Started May 14 01:40:05 PM PDT 24
Finished May 14 01:40:23 PM PDT 24
Peak memory 218236 kb
Host smart-7a0fd81f-d74c-4d4d-ae16-12a40b1e2e77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216364655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2216364655
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1960853419
Short name T448
Test name
Test status
Simulation time 406127889 ps
CPU time 9.7 seconds
Started May 14 01:40:04 PM PDT 24
Finished May 14 01:40:17 PM PDT 24
Peak memory 224488 kb
Host smart-89f21d79-3ab5-40bd-b84b-1959f8e2cba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960853419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1960853419
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2903031392
Short name T59
Test name
Test status
Simulation time 91392301 ps
CPU time 1.67 seconds
Started May 14 01:40:05 PM PDT 24
Finished May 14 01:40:09 PM PDT 24
Peak memory 218136 kb
Host smart-dfdf270f-b92d-4e5d-bd6a-e366a5d17bf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903031392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2903031392
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.4252853126
Short name T534
Test name
Test status
Simulation time 220559560 ps
CPU time 25.31 seconds
Started May 14 01:40:05 PM PDT 24
Finished May 14 01:40:32 PM PDT 24
Peak memory 251000 kb
Host smart-918e1f42-ee9a-4908-9844-ef9689d2e2ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252853126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.4252853126
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3625756313
Short name T300
Test name
Test status
Simulation time 192337942 ps
CPU time 10.24 seconds
Started May 14 01:40:04 PM PDT 24
Finished May 14 01:40:17 PM PDT 24
Peak memory 251136 kb
Host smart-b1b3901d-cc87-4d43-a052-a3441ee6ab98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625756313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3625756313
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.374578279
Short name T357
Test name
Test status
Simulation time 9679535839 ps
CPU time 281.71 seconds
Started May 14 01:40:07 PM PDT 24
Finished May 14 01:44:50 PM PDT 24
Peak memory 283964 kb
Host smart-4a9a0c0d-3222-4699-b4d5-34dd4371227b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374578279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.374578279
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.1947709110
Short name T57
Test name
Test status
Simulation time 20430609010 ps
CPU time 206.3 seconds
Started May 14 01:40:06 PM PDT 24
Finished May 14 01:43:34 PM PDT 24
Peak memory 283716 kb
Host smart-0d7f698b-d768-4286-a63b-2c07def087ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1947709110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.1947709110
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3227610172
Short name T816
Test name
Test status
Simulation time 25526450 ps
CPU time 0.89 seconds
Started May 14 01:40:07 PM PDT 24
Finished May 14 01:40:09 PM PDT 24
Peak memory 212904 kb
Host smart-84af849d-fed8-40bb-a800-98403334f88e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227610172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.3227610172
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2912483858
Short name T798
Test name
Test status
Simulation time 79180855 ps
CPU time 0.96 seconds
Started May 14 01:40:12 PM PDT 24
Finished May 14 01:40:14 PM PDT 24
Peak memory 209760 kb
Host smart-a5696582-e59b-4621-9475-13c8754e8a50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912483858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2912483858
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1051837908
Short name T790
Test name
Test status
Simulation time 1256626377 ps
CPU time 13.03 seconds
Started May 14 01:40:06 PM PDT 24
Finished May 14 01:40:21 PM PDT 24
Peak memory 218148 kb
Host smart-cfcc3a2d-3422-41d9-bdd8-3e7b419641f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051837908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1051837908
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.924799290
Short name T493
Test name
Test status
Simulation time 4066300792 ps
CPU time 7.6 seconds
Started May 14 01:40:04 PM PDT 24
Finished May 14 01:40:13 PM PDT 24
Peak memory 209888 kb
Host smart-4e4ab72e-265f-42c3-a276-a3723aedf5b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924799290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.924799290
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3634952790
Short name T821
Test name
Test status
Simulation time 91141548 ps
CPU time 3.14 seconds
Started May 14 01:40:04 PM PDT 24
Finished May 14 01:40:10 PM PDT 24
Peak memory 218140 kb
Host smart-a24ca2fb-25c0-4438-b54d-b1239eb3a40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634952790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3634952790
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2879905013
Short name T637
Test name
Test status
Simulation time 653723278 ps
CPU time 17.84 seconds
Started May 14 01:40:03 PM PDT 24
Finished May 14 01:40:22 PM PDT 24
Peak memory 226272 kb
Host smart-d3cc938b-5abb-477b-a40d-5c2c41b63e34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879905013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2879905013
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3560092620
Short name T476
Test name
Test status
Simulation time 687907596 ps
CPU time 15.92 seconds
Started May 14 01:40:04 PM PDT 24
Finished May 14 01:40:21 PM PDT 24
Peak memory 218124 kb
Host smart-a3c0a639-c16f-44ad-99b0-144778c9c8a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560092620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3560092620
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1021252766
Short name T244
Test name
Test status
Simulation time 376005039 ps
CPU time 9.51 seconds
Started May 14 01:40:04 PM PDT 24
Finished May 14 01:40:14 PM PDT 24
Peak memory 218044 kb
Host smart-b661d33f-fab3-44ae-8170-8abbedfa4c12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021252766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1021252766
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2502450308
Short name T444
Test name
Test status
Simulation time 1333973257 ps
CPU time 8.91 seconds
Started May 14 01:40:05 PM PDT 24
Finished May 14 01:40:16 PM PDT 24
Peak memory 226200 kb
Host smart-9669dceb-3da8-4814-b832-9d7cf8d5c03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502450308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2502450308
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1118451706
Short name T784
Test name
Test status
Simulation time 62630622 ps
CPU time 1.01 seconds
Started May 14 01:40:04 PM PDT 24
Finished May 14 01:40:07 PM PDT 24
Peak memory 217948 kb
Host smart-ab1ceacb-67c8-4e55-b04c-e5f1870ed1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118451706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1118451706
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3173654428
Short name T862
Test name
Test status
Simulation time 2318455187 ps
CPU time 31.68 seconds
Started May 14 01:40:04 PM PDT 24
Finished May 14 01:40:38 PM PDT 24
Peak memory 251268 kb
Host smart-728d2514-f8f6-4ae1-b9c9-b8c0027d9430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173654428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3173654428
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2406467510
Short name T625
Test name
Test status
Simulation time 56083370 ps
CPU time 8.09 seconds
Started May 14 01:40:04 PM PDT 24
Finished May 14 01:40:15 PM PDT 24
Peak memory 250928 kb
Host smart-78e62dd8-8af5-48c1-a4ff-388563e9be16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406467510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2406467510
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1158680866
Short name T659
Test name
Test status
Simulation time 4028497502 ps
CPU time 22.31 seconds
Started May 14 01:40:14 PM PDT 24
Finished May 14 01:40:38 PM PDT 24
Peak memory 215588 kb
Host smart-06a4803f-e049-4ebf-8a7d-73717df3caad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158680866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1158680866
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.654810639
Short name T159
Test name
Test status
Simulation time 37024682109 ps
CPU time 1436.93 seconds
Started May 14 01:40:13 PM PDT 24
Finished May 14 02:04:11 PM PDT 24
Peak memory 291040 kb
Host smart-2fb02934-d043-40e6-876f-1d8649fe2263
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=654810639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.654810639
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.4175678877
Short name T308
Test name
Test status
Simulation time 39399223 ps
CPU time 0.87 seconds
Started May 14 01:40:04 PM PDT 24
Finished May 14 01:40:06 PM PDT 24
Peak memory 211768 kb
Host smart-0fc11096-cfd9-4fb3-9384-341c39a0cf57
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175678877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.4175678877
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.690561523
Short name T363
Test name
Test status
Simulation time 66305608 ps
CPU time 1.1 seconds
Started May 14 01:40:14 PM PDT 24
Finished May 14 01:40:16 PM PDT 24
Peak memory 209716 kb
Host smart-d79ae60a-4c87-43b7-8ccf-4a0a6e4ba960
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690561523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.690561523
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2290743633
Short name T789
Test name
Test status
Simulation time 587635497 ps
CPU time 13.25 seconds
Started May 14 01:40:12 PM PDT 24
Finished May 14 01:40:26 PM PDT 24
Peak memory 218184 kb
Host smart-bb13d6d5-be0a-4ff5-b1b9-589e12854baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290743633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2290743633
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.858271727
Short name T561
Test name
Test status
Simulation time 129157152 ps
CPU time 3.96 seconds
Started May 14 01:40:14 PM PDT 24
Finished May 14 01:40:19 PM PDT 24
Peak memory 209724 kb
Host smart-6f0cf6e8-26f6-497c-b973-b3e611daaff8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858271727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.858271727
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3587386134
Short name T292
Test name
Test status
Simulation time 26554650 ps
CPU time 2.24 seconds
Started May 14 01:40:14 PM PDT 24
Finished May 14 01:40:18 PM PDT 24
Peak memory 218228 kb
Host smart-b2ef39ee-ab83-402d-afbb-dd3c10380dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587386134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3587386134
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1133653853
Short name T468
Test name
Test status
Simulation time 164018445 ps
CPU time 8.88 seconds
Started May 14 01:40:14 PM PDT 24
Finished May 14 01:40:24 PM PDT 24
Peak memory 226204 kb
Host smart-f1d7bae2-0783-4f27-826d-88f6191535ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133653853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1133653853
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2189023633
Short name T544
Test name
Test status
Simulation time 1110995544 ps
CPU time 8.76 seconds
Started May 14 01:40:13 PM PDT 24
Finished May 14 01:40:24 PM PDT 24
Peak memory 218196 kb
Host smart-fc257b89-9ce7-479f-aa81-6ded8ce67d42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189023633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2189023633
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1620702233
Short name T430
Test name
Test status
Simulation time 360956778 ps
CPU time 13.57 seconds
Started May 14 01:40:13 PM PDT 24
Finished May 14 01:40:28 PM PDT 24
Peak memory 218120 kb
Host smart-18c510e6-44ec-462c-9dfd-df9f6fcc0b10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620702233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1620702233
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1481166099
Short name T445
Test name
Test status
Simulation time 1130541917 ps
CPU time 10.62 seconds
Started May 14 01:40:12 PM PDT 24
Finished May 14 01:40:23 PM PDT 24
Peak memory 225056 kb
Host smart-a5e425a0-4071-4e24-850d-7cb5bcc9a547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481166099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1481166099
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2385232148
Short name T849
Test name
Test status
Simulation time 21090920 ps
CPU time 1.19 seconds
Started May 14 01:40:12 PM PDT 24
Finished May 14 01:40:15 PM PDT 24
Peak memory 217848 kb
Host smart-3cf8aa8a-94f0-4c67-93f5-a0826a2bde80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385232148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2385232148
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3769857549
Short name T704
Test name
Test status
Simulation time 354044681 ps
CPU time 22.35 seconds
Started May 14 01:40:17 PM PDT 24
Finished May 14 01:40:40 PM PDT 24
Peak memory 251112 kb
Host smart-19e961b6-5bcb-4ec8-93f8-10890af0b538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769857549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3769857549
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.256099964
Short name T175
Test name
Test status
Simulation time 70953721 ps
CPU time 8.03 seconds
Started May 14 01:40:13 PM PDT 24
Finished May 14 01:40:22 PM PDT 24
Peak memory 250872 kb
Host smart-88e28784-60fa-4238-8050-8f4f3af10313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256099964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.256099964
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2920594034
Short name T234
Test name
Test status
Simulation time 3728236083 ps
CPU time 102.24 seconds
Started May 14 01:40:15 PM PDT 24
Finished May 14 01:41:58 PM PDT 24
Peak memory 240892 kb
Host smart-e6f00a90-b61c-444d-ab08-2e57918e353e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920594034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2920594034
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.4277013444
Short name T583
Test name
Test status
Simulation time 26152564 ps
CPU time 0.9 seconds
Started May 14 01:40:13 PM PDT 24
Finished May 14 01:40:16 PM PDT 24
Peak memory 211752 kb
Host smart-ae0677c3-5cd3-4303-9e55-45500a039c75
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277013444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.4277013444
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2365566807
Short name T531
Test name
Test status
Simulation time 32640042 ps
CPU time 1.43 seconds
Started May 14 01:40:21 PM PDT 24
Finished May 14 01:40:24 PM PDT 24
Peak memory 209704 kb
Host smart-6b9c06ce-6104-472b-85ab-2a589a6e1fa0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365566807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2365566807
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3978323536
Short name T177
Test name
Test status
Simulation time 361430576 ps
CPU time 9.57 seconds
Started May 14 01:40:20 PM PDT 24
Finished May 14 01:40:31 PM PDT 24
Peak memory 218004 kb
Host smart-b308edce-a453-47d9-86b1-f5b69fbe4563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978323536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3978323536
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2665976401
Short name T4
Test name
Test status
Simulation time 491988805 ps
CPU time 12.53 seconds
Started May 14 01:40:21 PM PDT 24
Finished May 14 01:40:36 PM PDT 24
Peak memory 209716 kb
Host smart-137503e2-65a9-4774-b19f-729db39745a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665976401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2665976401
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2604912969
Short name T421
Test name
Test status
Simulation time 336267686 ps
CPU time 2.76 seconds
Started May 14 01:40:12 PM PDT 24
Finished May 14 01:40:16 PM PDT 24
Peak memory 218076 kb
Host smart-809daf7e-5855-4351-bd6d-9b35302b059a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604912969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2604912969
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2141786848
Short name T467
Test name
Test status
Simulation time 695224517 ps
CPU time 13.1 seconds
Started May 14 01:40:21 PM PDT 24
Finished May 14 01:40:36 PM PDT 24
Peak memory 217144 kb
Host smart-c4ba19b8-d2cd-4e36-b7a2-5ce41961065c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141786848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2141786848
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.892759713
Short name T765
Test name
Test status
Simulation time 475677873 ps
CPU time 11.54 seconds
Started May 14 01:40:20 PM PDT 24
Finished May 14 01:40:34 PM PDT 24
Peak memory 218160 kb
Host smart-58e07476-10a5-4979-a048-bd507d42eefa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892759713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.892759713
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1661162460
Short name T272
Test name
Test status
Simulation time 1088318543 ps
CPU time 8.47 seconds
Started May 14 01:40:21 PM PDT 24
Finished May 14 01:40:32 PM PDT 24
Peak memory 218188 kb
Host smart-903aa0cb-5578-4990-bc6c-b8582a1183a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661162460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1661162460
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1346418037
Short name T399
Test name
Test status
Simulation time 642513239 ps
CPU time 8.73 seconds
Started May 14 01:40:21 PM PDT 24
Finished May 14 01:40:32 PM PDT 24
Peak memory 218128 kb
Host smart-0a9eb4fb-4fb7-42da-b2ce-d327aa33a751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346418037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1346418037
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3584538692
Short name T150
Test name
Test status
Simulation time 177242474 ps
CPU time 1.5 seconds
Started May 14 01:40:14 PM PDT 24
Finished May 14 01:40:17 PM PDT 24
Peak memory 213520 kb
Host smart-05954dc5-14fc-48eb-8589-fe1a15e58008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584538692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3584538692
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.263012874
Short name T26
Test name
Test status
Simulation time 325878984 ps
CPU time 32.88 seconds
Started May 14 01:40:13 PM PDT 24
Finished May 14 01:40:48 PM PDT 24
Peak memory 251140 kb
Host smart-ed93c987-ea74-4cfb-90e3-6a19c98ce587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263012874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.263012874
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.1284508556
Short name T281
Test name
Test status
Simulation time 362732320 ps
CPU time 6.71 seconds
Started May 14 01:40:13 PM PDT 24
Finished May 14 01:40:22 PM PDT 24
Peak memory 247188 kb
Host smart-6c29ea60-dc65-4c7d-9037-79208655de86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284508556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.1284508556
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.365476018
Short name T594
Test name
Test status
Simulation time 77739106892 ps
CPU time 493.42 seconds
Started May 14 01:40:23 PM PDT 24
Finished May 14 01:48:38 PM PDT 24
Peak memory 529504 kb
Host smart-7bdc7592-c57d-4616-b506-9bc9637eaf20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365476018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.365476018
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.4077942175
Short name T590
Test name
Test status
Simulation time 42968777 ps
CPU time 0.86 seconds
Started May 14 01:40:12 PM PDT 24
Finished May 14 01:40:14 PM PDT 24
Peak memory 211708 kb
Host smart-ab6e1be0-3b63-4854-b23e-11eca69ef6bf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077942175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.4077942175
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.2086315295
Short name T609
Test name
Test status
Simulation time 193452871 ps
CPU time 1.03 seconds
Started May 14 01:40:30 PM PDT 24
Finished May 14 01:40:32 PM PDT 24
Peak memory 209636 kb
Host smart-0446ed38-6e08-47aa-9fa9-168a39bb8e02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086315295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.2086315295
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3932222488
Short name T529
Test name
Test status
Simulation time 1807251909 ps
CPU time 9.13 seconds
Started May 14 01:40:21 PM PDT 24
Finished May 14 01:40:32 PM PDT 24
Peak memory 218064 kb
Host smart-4233c1de-0a4d-4073-a14f-0ff30884ad17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932222488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3932222488
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1501220559
Short name T7
Test name
Test status
Simulation time 1006703485 ps
CPU time 7.43 seconds
Started May 14 01:40:22 PM PDT 24
Finished May 14 01:40:31 PM PDT 24
Peak memory 217144 kb
Host smart-13912f9e-63a8-484b-9f3b-dccd1c5bacbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501220559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1501220559
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3396364391
Short name T736
Test name
Test status
Simulation time 75316809 ps
CPU time 3.17 seconds
Started May 14 01:40:20 PM PDT 24
Finished May 14 01:40:25 PM PDT 24
Peak memory 218136 kb
Host smart-8420a247-fcd6-4eeb-855a-c040ab9ff35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396364391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3396364391
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2936664037
Short name T757
Test name
Test status
Simulation time 863899526 ps
CPU time 12.47 seconds
Started May 14 01:40:22 PM PDT 24
Finished May 14 01:40:36 PM PDT 24
Peak memory 226304 kb
Host smart-bf40830c-656e-4192-9e7b-58c19d207363
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936664037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2936664037
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.4252128901
Short name T519
Test name
Test status
Simulation time 4145205243 ps
CPU time 11.59 seconds
Started May 14 01:40:22 PM PDT 24
Finished May 14 01:40:35 PM PDT 24
Peak memory 218216 kb
Host smart-479e1f98-16f4-4559-bada-3ca19506ea45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252128901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.4252128901
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.1220610335
Short name T312
Test name
Test status
Simulation time 330273147 ps
CPU time 10.06 seconds
Started May 14 01:40:23 PM PDT 24
Finished May 14 01:40:34 PM PDT 24
Peak memory 218144 kb
Host smart-ef6db2bc-56e3-40d3-8f18-8244179291af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220610335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
1220610335
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3023436364
Short name T662
Test name
Test status
Simulation time 519210168 ps
CPU time 10.44 seconds
Started May 14 01:40:20 PM PDT 24
Finished May 14 01:40:32 PM PDT 24
Peak memory 218260 kb
Host smart-03508e7d-cce6-4b7a-91e8-e7fc0d0821bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023436364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3023436364
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.513010760
Short name T270
Test name
Test status
Simulation time 24789863 ps
CPU time 2.2 seconds
Started May 14 01:40:20 PM PDT 24
Finished May 14 01:40:24 PM PDT 24
Peak memory 214216 kb
Host smart-08cd0e70-07a4-4049-b2f0-f586c2ba4db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513010760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.513010760
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2197279737
Short name T293
Test name
Test status
Simulation time 171163949 ps
CPU time 23.36 seconds
Started May 14 01:40:21 PM PDT 24
Finished May 14 01:40:46 PM PDT 24
Peak memory 251144 kb
Host smart-86bdb5d2-7318-486f-8bad-4e0f5c60f9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197279737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2197279737
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1633230459
Short name T279
Test name
Test status
Simulation time 206142902 ps
CPU time 6.22 seconds
Started May 14 01:40:22 PM PDT 24
Finished May 14 01:40:30 PM PDT 24
Peak memory 247876 kb
Host smart-5bc9a4aa-b8e2-4d0b-bfcc-e3e1f0e65f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633230459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1633230459
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3227987178
Short name T584
Test name
Test status
Simulation time 5703894680 ps
CPU time 44.74 seconds
Started May 14 01:40:20 PM PDT 24
Finished May 14 01:41:07 PM PDT 24
Peak memory 251200 kb
Host smart-71c1b3b7-b4b6-4608-98bc-35313e3f8faa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227987178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3227987178
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3101868965
Short name T827
Test name
Test status
Simulation time 39483154 ps
CPU time 0.97 seconds
Started May 14 01:40:21 PM PDT 24
Finished May 14 01:40:24 PM PDT 24
Peak memory 211732 kb
Host smart-bee88838-fdd5-4e32-8e3e-b4c8285b7d9f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101868965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3101868965
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1388561251
Short name T630
Test name
Test status
Simulation time 14094250 ps
CPU time 0.87 seconds
Started May 14 01:40:37 PM PDT 24
Finished May 14 01:40:39 PM PDT 24
Peak memory 209712 kb
Host smart-d6deaa16-5675-4e62-9b81-608a4d216382
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388561251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1388561251
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.493017352
Short name T258
Test name
Test status
Simulation time 1707234723 ps
CPU time 13.54 seconds
Started May 14 01:40:32 PM PDT 24
Finished May 14 01:40:48 PM PDT 24
Peak memory 218192 kb
Host smart-47a85898-42da-4944-91a5-7e9fa64a3820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493017352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.493017352
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3617353954
Short name T651
Test name
Test status
Simulation time 491428064 ps
CPU time 2.89 seconds
Started May 14 01:40:37 PM PDT 24
Finished May 14 01:40:41 PM PDT 24
Peak memory 217156 kb
Host smart-ded1290a-53fb-4c33-a414-149d642e9b9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617353954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3617353954
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2738913947
Short name T53
Test name
Test status
Simulation time 59561122 ps
CPU time 2.29 seconds
Started May 14 01:40:32 PM PDT 24
Finished May 14 01:40:36 PM PDT 24
Peak memory 218120 kb
Host smart-51ad96f2-fad1-469c-b093-4199aa72eeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738913947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2738913947
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.87441254
Short name T500
Test name
Test status
Simulation time 666512418 ps
CPU time 11.77 seconds
Started May 14 01:40:31 PM PDT 24
Finished May 14 01:40:45 PM PDT 24
Peak memory 219016 kb
Host smart-62310559-6fa1-4b84-9fe9-1c0c6f3d277b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87441254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.87441254
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2653112864
Short name T613
Test name
Test status
Simulation time 3589505260 ps
CPU time 18.51 seconds
Started May 14 01:40:29 PM PDT 24
Finished May 14 01:40:49 PM PDT 24
Peak memory 219172 kb
Host smart-d3b007b5-ddda-4a45-8b8b-3e938a43cdd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653112864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2653112864
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1836860552
Short name T712
Test name
Test status
Simulation time 390629018 ps
CPU time 10.62 seconds
Started May 14 01:40:37 PM PDT 24
Finished May 14 01:40:48 PM PDT 24
Peak memory 218152 kb
Host smart-69c3248c-fa5e-4f20-b6dd-35b22834c229
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836860552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1836860552
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3079160146
Short name T725
Test name
Test status
Simulation time 394910069 ps
CPU time 7.37 seconds
Started May 14 01:40:33 PM PDT 24
Finished May 14 01:40:42 PM PDT 24
Peak memory 218192 kb
Host smart-f3930d89-4cbb-4489-af43-3ec0c114f579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079160146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3079160146
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1148369446
Short name T388
Test name
Test status
Simulation time 61791542 ps
CPU time 1.69 seconds
Started May 14 01:40:30 PM PDT 24
Finished May 14 01:40:33 PM PDT 24
Peak memory 213580 kb
Host smart-080ead64-4ab8-416b-a8ab-0f3b7611c677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148369446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1148369446
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1360761905
Short name T346
Test name
Test status
Simulation time 459547058 ps
CPU time 22.87 seconds
Started May 14 01:40:32 PM PDT 24
Finished May 14 01:40:56 PM PDT 24
Peak memory 247388 kb
Host smart-1568cf19-8a62-4f24-8c5d-fde79dab7855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360761905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1360761905
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3313263878
Short name T229
Test name
Test status
Simulation time 162324748 ps
CPU time 6.89 seconds
Started May 14 01:40:33 PM PDT 24
Finished May 14 01:40:42 PM PDT 24
Peak memory 250308 kb
Host smart-496c18e8-cc4d-4fb6-b38d-ba44e2c14459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313263878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3313263878
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.931726302
Short name T475
Test name
Test status
Simulation time 44616544802 ps
CPU time 182.99 seconds
Started May 14 01:40:32 PM PDT 24
Finished May 14 01:43:37 PM PDT 24
Peak memory 283884 kb
Host smart-84f2524a-a6a8-456a-a899-18b04c81d57f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931726302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.931726302
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.112114542
Short name T267
Test name
Test status
Simulation time 26239964 ps
CPU time 0.95 seconds
Started May 14 01:40:33 PM PDT 24
Finished May 14 01:40:36 PM PDT 24
Peak memory 213028 kb
Host smart-f38356aa-ad2a-4fd3-a3b8-a2cee2031b40
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112114542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.112114542
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2305751058
Short name T708
Test name
Test status
Simulation time 26483759 ps
CPU time 1.05 seconds
Started May 14 01:40:32 PM PDT 24
Finished May 14 01:40:34 PM PDT 24
Peak memory 209948 kb
Host smart-bacd7f7a-db12-4782-9735-27f332afea43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305751058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2305751058
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1877791133
Short name T283
Test name
Test status
Simulation time 259221525 ps
CPU time 9.57 seconds
Started May 14 01:40:30 PM PDT 24
Finished May 14 01:40:40 PM PDT 24
Peak memory 218084 kb
Host smart-32e9a0d9-5d0a-4943-a3fc-b4d63268af0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877791133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1877791133
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2831691639
Short name T34
Test name
Test status
Simulation time 544265966 ps
CPU time 2.19 seconds
Started May 14 01:40:31 PM PDT 24
Finished May 14 01:40:35 PM PDT 24
Peak memory 209740 kb
Host smart-25929f94-b320-422c-8e28-9096fca55617
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831691639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2831691639
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3982787131
Short name T721
Test name
Test status
Simulation time 422161478 ps
CPU time 4.85 seconds
Started May 14 01:40:32 PM PDT 24
Finished May 14 01:40:38 PM PDT 24
Peak memory 218116 kb
Host smart-4fb216f3-cdd3-4dc8-99da-c03936353d3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982787131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3982787131
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.3810232182
Short name T753
Test name
Test status
Simulation time 4108052474 ps
CPU time 12.56 seconds
Started May 14 01:40:30 PM PDT 24
Finished May 14 01:40:44 PM PDT 24
Peak memory 219168 kb
Host smart-03106495-6eff-4b7c-bb5a-5ca92f54d468
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810232182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.3810232182
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.4230566587
Short name T345
Test name
Test status
Simulation time 806730454 ps
CPU time 9.89 seconds
Started May 14 01:40:30 PM PDT 24
Finished May 14 01:40:41 PM PDT 24
Peak memory 218144 kb
Host smart-239f8440-cfac-40d4-8d1b-4109fb20e6ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230566587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.4230566587
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.2165857304
Short name T299
Test name
Test status
Simulation time 249250728 ps
CPU time 10.67 seconds
Started May 14 01:40:30 PM PDT 24
Finished May 14 01:40:42 PM PDT 24
Peak memory 218160 kb
Host smart-81ade824-c82d-471f-a2b6-82186512fba8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165857304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
2165857304
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.1077790643
Short name T575
Test name
Test status
Simulation time 1424353721 ps
CPU time 14.66 seconds
Started May 14 01:40:29 PM PDT 24
Finished May 14 01:40:45 PM PDT 24
Peak memory 225824 kb
Host smart-f239a220-e5e5-42e4-88f9-d778c63d6307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077790643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.1077790643
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.4068864037
Short name T828
Test name
Test status
Simulation time 47229104 ps
CPU time 2.48 seconds
Started May 14 01:40:30 PM PDT 24
Finished May 14 01:40:34 PM PDT 24
Peak memory 214108 kb
Host smart-a15f84d3-9af8-48ab-b4cb-842cf1fa0c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068864037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.4068864037
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.905004187
Short name T27
Test name
Test status
Simulation time 1484829757 ps
CPU time 36.9 seconds
Started May 14 01:40:28 PM PDT 24
Finished May 14 01:41:06 PM PDT 24
Peak memory 251036 kb
Host smart-88f547a7-3b04-42e8-82f6-93ff9eca04ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905004187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.905004187
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3711294100
Short name T796
Test name
Test status
Simulation time 69702331 ps
CPU time 8.04 seconds
Started May 14 01:40:34 PM PDT 24
Finished May 14 01:40:43 PM PDT 24
Peak memory 250960 kb
Host smart-6a10a7ed-4692-46cd-acf6-1feadf0752f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711294100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3711294100
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1760330495
Short name T684
Test name
Test status
Simulation time 5822602268 ps
CPU time 124.83 seconds
Started May 14 01:40:35 PM PDT 24
Finished May 14 01:42:41 PM PDT 24
Peak memory 275968 kb
Host smart-1e440d7c-8bfe-4a74-971b-a03fdc45f1ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760330495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1760330495
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3030473869
Short name T620
Test name
Test status
Simulation time 83888579 ps
CPU time 0.99 seconds
Started May 14 01:40:46 PM PDT 24
Finished May 14 01:40:48 PM PDT 24
Peak memory 209676 kb
Host smart-b73f2a42-406c-4a1c-810e-8be52898c4c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030473869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3030473869
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3814315438
Short name T381
Test name
Test status
Simulation time 282985474 ps
CPU time 11.55 seconds
Started May 14 01:40:36 PM PDT 24
Finished May 14 01:40:48 PM PDT 24
Peak memory 218220 kb
Host smart-c2298629-724e-45bf-a449-a236f88339f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814315438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3814315438
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.636003318
Short name T766
Test name
Test status
Simulation time 448331686 ps
CPU time 11.7 seconds
Started May 14 01:40:42 PM PDT 24
Finished May 14 01:40:56 PM PDT 24
Peak memory 209660 kb
Host smart-5443ee9e-b2b1-4f2f-8bd6-d8bec34526cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636003318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.636003318
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.3339104329
Short name T661
Test name
Test status
Simulation time 70627935 ps
CPU time 1.53 seconds
Started May 14 01:40:34 PM PDT 24
Finished May 14 01:40:37 PM PDT 24
Peak memory 218096 kb
Host smart-1d57611a-b3b8-4d2a-8dc7-37a419c9e6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339104329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.3339104329
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2169616583
Short name T580
Test name
Test status
Simulation time 1259072145 ps
CPU time 10.16 seconds
Started May 14 01:40:43 PM PDT 24
Finished May 14 01:40:55 PM PDT 24
Peak memory 226200 kb
Host smart-be0f259d-5fe5-4834-9bb4-1ff9d4d052d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169616583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2169616583
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1544830848
Short name T352
Test name
Test status
Simulation time 1409967955 ps
CPU time 9.41 seconds
Started May 14 01:40:46 PM PDT 24
Finished May 14 01:40:57 PM PDT 24
Peak memory 218188 kb
Host smart-f1a7bf16-dfde-4bbc-9c39-797d2fc83c46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544830848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1544830848
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1045044275
Short name T636
Test name
Test status
Simulation time 2693280492 ps
CPU time 15.84 seconds
Started May 14 01:40:44 PM PDT 24
Finished May 14 01:41:02 PM PDT 24
Peak memory 218236 kb
Host smart-aa4d0ead-b7ed-497e-a2c1-2d0848e21f6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045044275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1045044275
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.234916873
Short name T334
Test name
Test status
Simulation time 1503575770 ps
CPU time 13.19 seconds
Started May 14 01:40:42 PM PDT 24
Finished May 14 01:40:57 PM PDT 24
Peak memory 218192 kb
Host smart-da8e78b2-4196-4278-a498-e4a16a5a6895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234916873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.234916873
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.565328252
Short name T524
Test name
Test status
Simulation time 42255074 ps
CPU time 2.88 seconds
Started May 14 01:40:31 PM PDT 24
Finished May 14 01:40:35 PM PDT 24
Peak memory 214288 kb
Host smart-3cd37783-33d2-4e9e-bf89-600519655b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565328252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.565328252
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.4052879036
Short name T411
Test name
Test status
Simulation time 219617915 ps
CPU time 22.88 seconds
Started May 14 01:40:33 PM PDT 24
Finished May 14 01:40:57 PM PDT 24
Peak memory 248968 kb
Host smart-e6553b66-912f-42bc-a246-8da5a0673057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052879036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.4052879036
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.300506382
Short name T224
Test name
Test status
Simulation time 338366825 ps
CPU time 10.96 seconds
Started May 14 01:40:31 PM PDT 24
Finished May 14 01:40:43 PM PDT 24
Peak memory 251064 kb
Host smart-26789f1b-afbd-4477-8529-4ca5ab1fa5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300506382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.300506382
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3175367126
Short name T516
Test name
Test status
Simulation time 1181657010 ps
CPU time 32.64 seconds
Started May 14 01:40:43 PM PDT 24
Finished May 14 01:41:18 PM PDT 24
Peak memory 251040 kb
Host smart-d57cb1b8-4943-4425-8a7d-4bd941557d7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175367126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3175367126
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.1871656518
Short name T137
Test name
Test status
Simulation time 59850390312 ps
CPU time 327.97 seconds
Started May 14 01:40:43 PM PDT 24
Finished May 14 01:46:13 PM PDT 24
Peak memory 283912 kb
Host smart-27ac7c5e-88f0-4f47-9dd9-64f2e8e17398
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1871656518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.1871656518
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3676402205
Short name T391
Test name
Test status
Simulation time 14036338 ps
CPU time 1.06 seconds
Started May 14 01:40:30 PM PDT 24
Finished May 14 01:40:33 PM PDT 24
Peak memory 211740 kb
Host smart-a38ff55f-dcdd-4dbe-a281-fb45f2e2081c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676402205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3676402205
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1966569346
Short name T260
Test name
Test status
Simulation time 35087728 ps
CPU time 0.97 seconds
Started May 14 01:37:16 PM PDT 24
Finished May 14 01:37:19 PM PDT 24
Peak memory 209720 kb
Host smart-3d24819d-8cb7-46c2-ae94-91b55cdefbfd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966569346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1966569346
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3328353745
Short name T596
Test name
Test status
Simulation time 14517038 ps
CPU time 0.9 seconds
Started May 14 01:37:08 PM PDT 24
Finished May 14 01:37:10 PM PDT 24
Peak memory 209724 kb
Host smart-14322c25-7b28-4f4f-ba23-b8bdfd4f3118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328353745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3328353745
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2532360500
Short name T470
Test name
Test status
Simulation time 962999531 ps
CPU time 9.74 seconds
Started May 14 01:37:01 PM PDT 24
Finished May 14 01:37:11 PM PDT 24
Peak memory 218208 kb
Host smart-91e11918-9f7b-473b-93c0-e099be1fb217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532360500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2532360500
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3778532127
Short name T471
Test name
Test status
Simulation time 1140911826 ps
CPU time 7.66 seconds
Started May 14 01:37:10 PM PDT 24
Finished May 14 01:37:19 PM PDT 24
Peak memory 217136 kb
Host smart-a6961517-baec-4436-ba49-a4176521fc84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778532127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3778532127
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.893027891
Short name T848
Test name
Test status
Simulation time 35981837133 ps
CPU time 55.21 seconds
Started May 14 01:37:10 PM PDT 24
Finished May 14 01:38:06 PM PDT 24
Peak memory 219104 kb
Host smart-33bb95b8-204c-4395-9095-01b333045c09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893027891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.893027891
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2571179288
Short name T424
Test name
Test status
Simulation time 338654292 ps
CPU time 5.04 seconds
Started May 14 01:37:08 PM PDT 24
Finished May 14 01:37:15 PM PDT 24
Peak memory 217472 kb
Host smart-f2754261-e9c0-4e24-b39e-bc7a4c3e2a46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571179288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
571179288
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3961401450
Short name T718
Test name
Test status
Simulation time 94243627 ps
CPU time 2.15 seconds
Started May 14 01:37:08 PM PDT 24
Finished May 14 01:37:11 PM PDT 24
Peak memory 218080 kb
Host smart-f05d5a3a-d3e4-41f0-904c-7a4e90bbe2e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961401450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3961401450
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2096767261
Short name T654
Test name
Test status
Simulation time 4607411690 ps
CPU time 33.74 seconds
Started May 14 01:37:10 PM PDT 24
Finished May 14 01:37:45 PM PDT 24
Peak memory 214184 kb
Host smart-c7376d33-06ee-4dc7-b191-b83ed334dcaf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096767261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2096767261
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3485899337
Short name T619
Test name
Test status
Simulation time 1903556608 ps
CPU time 5.81 seconds
Started May 14 01:37:08 PM PDT 24
Finished May 14 01:37:15 PM PDT 24
Peak memory 213624 kb
Host smart-b3b14593-a2ac-47a4-896f-960e49d3327e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485899337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3485899337
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3141213531
Short name T825
Test name
Test status
Simulation time 1194779392 ps
CPU time 52.44 seconds
Started May 14 01:37:08 PM PDT 24
Finished May 14 01:38:02 PM PDT 24
Peak memory 268056 kb
Host smart-23d2f18b-0937-494d-a22d-8d5e1d06805f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141213531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3141213531
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1366724015
Short name T461
Test name
Test status
Simulation time 377684182 ps
CPU time 11.49 seconds
Started May 14 01:37:08 PM PDT 24
Finished May 14 01:37:21 PM PDT 24
Peak memory 250520 kb
Host smart-b707fcc9-2cb4-4729-a8e4-5250694ce712
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366724015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.1366724015
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3431641298
Short name T682
Test name
Test status
Simulation time 92033555 ps
CPU time 3.41 seconds
Started May 14 01:37:00 PM PDT 24
Finished May 14 01:37:04 PM PDT 24
Peak memory 218072 kb
Host smart-a57375cb-7fb7-4ccd-baf1-7b6ca898e6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3431641298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3431641298
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.810643047
Short name T851
Test name
Test status
Simulation time 953156731 ps
CPU time 6.92 seconds
Started May 14 01:37:02 PM PDT 24
Finished May 14 01:37:09 PM PDT 24
Peak memory 217976 kb
Host smart-31ef187e-9444-421c-8465-83e67f92daa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810643047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.810643047
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2288230650
Short name T586
Test name
Test status
Simulation time 934751450 ps
CPU time 10.34 seconds
Started May 14 01:37:08 PM PDT 24
Finished May 14 01:37:20 PM PDT 24
Peak memory 226264 kb
Host smart-00317ee0-1409-4175-ba56-7a6e22cab145
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288230650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2288230650
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.107355087
Short name T12
Test name
Test status
Simulation time 1349004484 ps
CPU time 10.17 seconds
Started May 14 01:37:05 PM PDT 24
Finished May 14 01:37:16 PM PDT 24
Peak memory 218148 kb
Host smart-349326b6-e343-4bd5-bf70-d9a15a4e8e3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107355087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.107355087
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.589482203
Short name T22
Test name
Test status
Simulation time 1528188534 ps
CPU time 15.07 seconds
Started May 14 01:37:04 PM PDT 24
Finished May 14 01:37:20 PM PDT 24
Peak memory 218164 kb
Host smart-99cce01f-7a1e-460f-9cc3-a87c289c5a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589482203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.589482203
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.4013955427
Short name T162
Test name
Test status
Simulation time 1087291379 ps
CPU time 6.93 seconds
Started May 14 01:36:53 PM PDT 24
Finished May 14 01:37:01 PM PDT 24
Peak memory 217876 kb
Host smart-cfd63a42-18a4-4c38-9938-d6946da8b713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013955427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.4013955427
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.720200543
Short name T709
Test name
Test status
Simulation time 802339321 ps
CPU time 16.18 seconds
Started May 14 01:37:00 PM PDT 24
Finished May 14 01:37:17 PM PDT 24
Peak memory 251068 kb
Host smart-0a7a8182-7cd6-4410-ab71-52f9f553c0c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720200543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.720200543
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2856077766
Short name T378
Test name
Test status
Simulation time 773176836 ps
CPU time 7.21 seconds
Started May 14 01:37:01 PM PDT 24
Finished May 14 01:37:08 PM PDT 24
Peak memory 248444 kb
Host smart-6bc85af7-fc83-4253-8ac7-68515dcee421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856077766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2856077766
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1756628638
Short name T67
Test name
Test status
Simulation time 22928167191 ps
CPU time 203.39 seconds
Started May 14 01:37:07 PM PDT 24
Finished May 14 01:40:31 PM PDT 24
Peak memory 281800 kb
Host smart-31442655-49ac-482c-a988-e728a65022f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756628638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1756628638
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.3207128005
Short name T717
Test name
Test status
Simulation time 27845870 ps
CPU time 1.14 seconds
Started May 14 01:37:01 PM PDT 24
Finished May 14 01:37:03 PM PDT 24
Peak memory 212928 kb
Host smart-58d75541-abf8-4ef8-b85b-7374cf74f2e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207128005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.3207128005
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3342503752
Short name T644
Test name
Test status
Simulation time 73264245 ps
CPU time 0.83 seconds
Started May 14 01:37:15 PM PDT 24
Finished May 14 01:37:18 PM PDT 24
Peak memory 209580 kb
Host smart-bd3aed37-f252-4684-8b30-e00459542750
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342503752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3342503752
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.1278471167
Short name T206
Test name
Test status
Simulation time 34808746 ps
CPU time 0.85 seconds
Started May 14 01:37:15 PM PDT 24
Finished May 14 01:37:18 PM PDT 24
Peak memory 209528 kb
Host smart-638279eb-3af8-4fc1-92a6-0c392e7464d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278471167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.1278471167
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3033438840
Short name T777
Test name
Test status
Simulation time 358125594 ps
CPU time 11.19 seconds
Started May 14 01:37:15 PM PDT 24
Finished May 14 01:37:28 PM PDT 24
Peak memory 218156 kb
Host smart-357db2fe-e1fe-41da-9a99-942e9ad5a027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033438840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3033438840
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2724372039
Short name T353
Test name
Test status
Simulation time 572228571 ps
CPU time 6.83 seconds
Started May 14 01:37:16 PM PDT 24
Finished May 14 01:37:25 PM PDT 24
Peak memory 209700 kb
Host smart-de7ffa31-3b4f-4ba0-b18c-58792337c919
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724372039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2724372039
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3578642720
Short name T648
Test name
Test status
Simulation time 1790300490 ps
CPU time 43.66 seconds
Started May 14 01:37:15 PM PDT 24
Finished May 14 01:38:01 PM PDT 24
Peak memory 218124 kb
Host smart-11dfb377-177f-48a6-884f-3d4360c3cd46
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578642720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3578642720
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.383009794
Short name T409
Test name
Test status
Simulation time 820419404 ps
CPU time 9.39 seconds
Started May 14 01:37:15 PM PDT 24
Finished May 14 01:37:27 PM PDT 24
Peak memory 217840 kb
Host smart-f3af06c0-3580-452e-a771-8b43f17d1448
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383009794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.383009794
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2671314707
Short name T464
Test name
Test status
Simulation time 3004623165 ps
CPU time 4.7 seconds
Started May 14 01:37:19 PM PDT 24
Finished May 14 01:37:25 PM PDT 24
Peak memory 218176 kb
Host smart-bf9d38f1-ec2b-4a88-a1f0-6303fa2c77bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671314707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2671314707
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2136205812
Short name T339
Test name
Test status
Simulation time 793218388 ps
CPU time 23.22 seconds
Started May 14 01:37:16 PM PDT 24
Finished May 14 01:37:41 PM PDT 24
Peak memory 213356 kb
Host smart-6d476d67-54cb-4ad8-885d-14b2814e640e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136205812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2136205812
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.4117297355
Short name T577
Test name
Test status
Simulation time 429140857 ps
CPU time 4.66 seconds
Started May 14 01:37:14 PM PDT 24
Finished May 14 01:37:21 PM PDT 24
Peak memory 213896 kb
Host smart-d963d1a2-74d8-4653-818d-4ba993704545
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117297355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
4117297355
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2258116708
Short name T811
Test name
Test status
Simulation time 2757313658 ps
CPU time 50.18 seconds
Started May 14 01:37:14 PM PDT 24
Finished May 14 01:38:07 PM PDT 24
Peak memory 267584 kb
Host smart-ae0d0324-080e-4b73-9eec-707d840d4b4e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258116708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2258116708
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1385648750
Short name T254
Test name
Test status
Simulation time 370771034 ps
CPU time 16.54 seconds
Started May 14 01:37:14 PM PDT 24
Finished May 14 01:37:33 PM PDT 24
Peak memory 250588 kb
Host smart-3d62f44f-32ba-4220-ac8b-a86d7e4235f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385648750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1385648750
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.2024346779
Short name T600
Test name
Test status
Simulation time 142570831 ps
CPU time 3.72 seconds
Started May 14 01:37:13 PM PDT 24
Finished May 14 01:37:17 PM PDT 24
Peak memory 218208 kb
Host smart-0fc710e7-014c-4cc8-9d14-06e6907e8f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024346779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2024346779
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1500901445
Short name T689
Test name
Test status
Simulation time 1104468654 ps
CPU time 15.73 seconds
Started May 14 01:37:14 PM PDT 24
Finished May 14 01:37:31 PM PDT 24
Peak memory 214516 kb
Host smart-a904e195-7b9a-4c3e-990a-9ce8a05a74b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500901445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1500901445
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.776935715
Short name T546
Test name
Test status
Simulation time 2141268284 ps
CPU time 20.75 seconds
Started May 14 01:37:15 PM PDT 24
Finished May 14 01:37:38 PM PDT 24
Peak memory 219104 kb
Host smart-d4b5d059-9ad4-46ff-8086-125ccf00d801
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776935715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.776935715
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.392695856
Short name T542
Test name
Test status
Simulation time 303439121 ps
CPU time 12.38 seconds
Started May 14 01:37:15 PM PDT 24
Finished May 14 01:37:30 PM PDT 24
Peak memory 218140 kb
Host smart-21e55637-5967-4015-915a-0022ce54fcef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392695856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.392695856
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.2916852345
Short name T494
Test name
Test status
Simulation time 649562980 ps
CPU time 8.61 seconds
Started May 14 01:37:15 PM PDT 24
Finished May 14 01:37:26 PM PDT 24
Peak memory 218248 kb
Host smart-e97cae27-3949-4fb5-9f90-275683454b86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916852345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.2
916852345
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2671134688
Short name T599
Test name
Test status
Simulation time 372130640 ps
CPU time 13.94 seconds
Started May 14 01:37:14 PM PDT 24
Finished May 14 01:37:29 PM PDT 24
Peak memory 225000 kb
Host smart-fbd4cdac-ce33-4fd7-847d-7509cf0aee46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671134688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2671134688
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1665890863
Short name T627
Test name
Test status
Simulation time 38813659 ps
CPU time 2.26 seconds
Started May 14 01:37:15 PM PDT 24
Finished May 14 01:37:19 PM PDT 24
Peak memory 218084 kb
Host smart-6962b47a-cdc9-4409-87f2-2340faf10834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665890863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1665890863
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1608504173
Short name T216
Test name
Test status
Simulation time 292236524 ps
CPU time 28.47 seconds
Started May 14 01:37:18 PM PDT 24
Finished May 14 01:37:48 PM PDT 24
Peak memory 246992 kb
Host smart-3b9911a9-b681-4429-a69e-1ab5c06b8f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608504173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1608504173
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.325871782
Short name T359
Test name
Test status
Simulation time 213147436 ps
CPU time 6.63 seconds
Started May 14 01:37:15 PM PDT 24
Finished May 14 01:37:24 PM PDT 24
Peak memory 250680 kb
Host smart-fee983c5-9bc0-46e2-b16a-bf344ff9b724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325871782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.325871782
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.730092265
Short name T739
Test name
Test status
Simulation time 13611837395 ps
CPU time 125.55 seconds
Started May 14 01:37:15 PM PDT 24
Finished May 14 01:39:23 PM PDT 24
Peak memory 247664 kb
Host smart-a5e841b0-8ed7-4585-87fe-886f7ac145f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730092265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.730092265
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.1560920028
Short name T145
Test name
Test status
Simulation time 61151103097 ps
CPU time 684.32 seconds
Started May 14 01:37:15 PM PDT 24
Finished May 14 01:48:41 PM PDT 24
Peak memory 447708 kb
Host smart-94290aa7-7437-4cb2-a747-95c05c5a0f19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1560920028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_stress_all_with_rand_reset.1560920028
Directory /workspace/6.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1071956737
Short name T850
Test name
Test status
Simulation time 12196012 ps
CPU time 0.75 seconds
Started May 14 01:37:13 PM PDT 24
Finished May 14 01:37:15 PM PDT 24
Peak memory 208112 kb
Host smart-8d34165e-0b23-496b-80de-e49e2fae5c91
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071956737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.1071956737
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.1035223888
Short name T670
Test name
Test status
Simulation time 20713232 ps
CPU time 1.16 seconds
Started May 14 01:37:31 PM PDT 24
Finished May 14 01:37:34 PM PDT 24
Peak memory 209704 kb
Host smart-fc0bfe55-1501-40fb-8a6c-f5a6df9e8303
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035223888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.1035223888
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3084223232
Short name T204
Test name
Test status
Simulation time 17729361 ps
CPU time 0.87 seconds
Started May 14 01:37:15 PM PDT 24
Finished May 14 01:37:18 PM PDT 24
Peak memory 209408 kb
Host smart-06caf5e7-88c0-4050-98f0-cb94bb989faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084223232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3084223232
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.669420198
Short name T40
Test name
Test status
Simulation time 235930539 ps
CPU time 10.69 seconds
Started May 14 01:37:13 PM PDT 24
Finished May 14 01:37:25 PM PDT 24
Peak memory 218156 kb
Host smart-d2d9b5ce-7530-4e99-9dbf-31552fdb4f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669420198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.669420198
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3386137380
Short name T845
Test name
Test status
Simulation time 263596319 ps
CPU time 4.03 seconds
Started May 14 01:37:22 PM PDT 24
Finished May 14 01:37:26 PM PDT 24
Peak memory 217176 kb
Host smart-3a38a595-9092-4291-9b9d-2a723f88f3d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386137380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3386137380
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1826893698
Short name T764
Test name
Test status
Simulation time 8218038155 ps
CPU time 31.03 seconds
Started May 14 01:37:24 PM PDT 24
Finished May 14 01:37:56 PM PDT 24
Peak memory 218584 kb
Host smart-97c55d6f-fdc0-4f12-a9c4-42f2a6b959e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826893698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1826893698
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2421535474
Short name T403
Test name
Test status
Simulation time 3533957782 ps
CPU time 19.96 seconds
Started May 14 01:37:24 PM PDT 24
Finished May 14 01:37:46 PM PDT 24
Peak memory 218064 kb
Host smart-f489df69-3684-44d1-8b2b-e67b7e6a613d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421535474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
421535474
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3926445055
Short name T371
Test name
Test status
Simulation time 2995048748 ps
CPU time 4.69 seconds
Started May 14 01:37:25 PM PDT 24
Finished May 14 01:37:31 PM PDT 24
Peak memory 218312 kb
Host smart-86490473-12c8-44b4-a0f6-bb48cebb9d82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926445055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.3926445055
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.370408738
Short name T65
Test name
Test status
Simulation time 5606484649 ps
CPU time 32.95 seconds
Started May 14 01:37:31 PM PDT 24
Finished May 14 01:38:06 PM PDT 24
Peak memory 214228 kb
Host smart-368c119f-966d-4c44-8353-d29543a5b296
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370408738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.370408738
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.385925386
Short name T415
Test name
Test status
Simulation time 1969584787 ps
CPU time 7.45 seconds
Started May 14 01:37:16 PM PDT 24
Finished May 14 01:37:26 PM PDT 24
Peak memory 214008 kb
Host smart-29f5cfa6-df5d-438f-8878-6fa64b5f5e6a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385925386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.385925386
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2228153667
Short name T646
Test name
Test status
Simulation time 9313535462 ps
CPU time 58.26 seconds
Started May 14 01:37:15 PM PDT 24
Finished May 14 01:38:16 PM PDT 24
Peak memory 281460 kb
Host smart-13fef408-2454-484c-a454-27c6e8a30e45
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228153667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2228153667
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2089583629
Short name T87
Test name
Test status
Simulation time 432713662 ps
CPU time 17.45 seconds
Started May 14 01:37:24 PM PDT 24
Finished May 14 01:37:42 PM PDT 24
Peak memory 250764 kb
Host smart-a4310c75-53ae-44a7-b68c-41b791955ebd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089583629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2089583629
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1181919363
Short name T747
Test name
Test status
Simulation time 78127854 ps
CPU time 2.96 seconds
Started May 14 01:37:14 PM PDT 24
Finished May 14 01:37:19 PM PDT 24
Peak memory 218120 kb
Host smart-e86d87c7-4a0e-4a6a-90ad-df5f507bf569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181919363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1181919363
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3761025989
Short name T792
Test name
Test status
Simulation time 567261715 ps
CPU time 16.15 seconds
Started May 14 01:37:15 PM PDT 24
Finished May 14 01:37:33 PM PDT 24
Peak memory 218180 kb
Host smart-246acbed-617d-4f82-9d14-07d02a0311f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761025989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3761025989
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.1082019425
Short name T775
Test name
Test status
Simulation time 6747145062 ps
CPU time 17.76 seconds
Started May 14 01:37:31 PM PDT 24
Finished May 14 01:37:50 PM PDT 24
Peak memory 220496 kb
Host smart-87c17f73-edb4-4e4a-838b-0b8c488d4271
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082019425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.1082019425
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.181448345
Short name T602
Test name
Test status
Simulation time 1482980907 ps
CPU time 14.32 seconds
Started May 14 01:37:31 PM PDT 24
Finished May 14 01:37:47 PM PDT 24
Peak memory 218120 kb
Host smart-d67a0b17-7431-4bba-9f2b-e9a544d85154
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181448345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.181448345
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3616856613
Short name T733
Test name
Test status
Simulation time 409557024 ps
CPU time 9.48 seconds
Started May 14 01:37:24 PM PDT 24
Finished May 14 01:37:35 PM PDT 24
Peak memory 218152 kb
Host smart-0512c5a0-adaa-4748-95cc-00dda7daab86
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616856613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
616856613
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1916574118
Short name T479
Test name
Test status
Simulation time 737773265 ps
CPU time 16.38 seconds
Started May 14 01:37:14 PM PDT 24
Finished May 14 01:37:33 PM PDT 24
Peak memory 225564 kb
Host smart-15a50e36-7d4c-42cb-857a-3bb8789fd673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916574118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1916574118
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.3618181743
Short name T217
Test name
Test status
Simulation time 29239086 ps
CPU time 1.16 seconds
Started May 14 01:37:15 PM PDT 24
Finished May 14 01:37:18 PM PDT 24
Peak memory 213192 kb
Host smart-8a93763a-9e4a-444f-b8fd-2487218f9f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618181743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3618181743
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.108024819
Short name T498
Test name
Test status
Simulation time 1405918379 ps
CPU time 26.42 seconds
Started May 14 01:37:14 PM PDT 24
Finished May 14 01:37:41 PM PDT 24
Peak memory 251144 kb
Host smart-f7faff2a-47f2-45a6-b634-36bb78ea5133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108024819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.108024819
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2463705915
Short name T595
Test name
Test status
Simulation time 205187549 ps
CPU time 8.89 seconds
Started May 14 01:37:15 PM PDT 24
Finished May 14 01:37:26 PM PDT 24
Peak memory 246920 kb
Host smart-9fa94766-a190-4400-b067-8c1147938a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463705915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2463705915
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.39295077
Short name T265
Test name
Test status
Simulation time 28016259781 ps
CPU time 226.84 seconds
Started May 14 01:37:21 PM PDT 24
Finished May 14 01:41:09 PM PDT 24
Peak memory 259400 kb
Host smart-d034eac2-5463-419a-a924-c5f6cd20f8e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39295077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7
.lc_ctrl_stress_all.39295077
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.256710165
Short name T526
Test name
Test status
Simulation time 15438588 ps
CPU time 0.91 seconds
Started May 14 01:37:14 PM PDT 24
Finished May 14 01:37:16 PM PDT 24
Peak memory 211744 kb
Host smart-c2f0101a-29eb-4d07-bf20-c5d9dafb4f39
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256710165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.256710165
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2257803282
Short name T209
Test name
Test status
Simulation time 40559034 ps
CPU time 0.95 seconds
Started May 14 01:37:23 PM PDT 24
Finished May 14 01:37:25 PM PDT 24
Peak memory 209740 kb
Host smart-8af02a02-60b2-47ba-8a6c-0bfdc03edab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257803282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2257803282
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.2300513012
Short name T483
Test name
Test status
Simulation time 1111844875 ps
CPU time 14.58 seconds
Started May 14 01:37:23 PM PDT 24
Finished May 14 01:37:39 PM PDT 24
Peak memory 218148 kb
Host smart-53eb4291-09a6-4edb-adb4-9702f9b617a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300513012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2300513012
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1320228914
Short name T268
Test name
Test status
Simulation time 427047924 ps
CPU time 4.87 seconds
Started May 14 01:37:23 PM PDT 24
Finished May 14 01:37:30 PM PDT 24
Peak memory 217156 kb
Host smart-8a124ef1-2299-40fc-b715-e5641cf2ad4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320228914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1320228914
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2007406867
Short name T745
Test name
Test status
Simulation time 139847150 ps
CPU time 4.25 seconds
Started May 14 01:37:23 PM PDT 24
Finished May 14 01:37:28 PM PDT 24
Peak memory 217256 kb
Host smart-60284116-432c-4798-9cc9-0545650b55c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007406867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
007406867
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3839685850
Short name T266
Test name
Test status
Simulation time 532183661 ps
CPU time 6.53 seconds
Started May 14 01:37:22 PM PDT 24
Finished May 14 01:37:30 PM PDT 24
Peak memory 218176 kb
Host smart-872ca725-6842-4b6a-b99a-bdd1f8e0e6ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839685850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3839685850
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3819826613
Short name T407
Test name
Test status
Simulation time 5308189585 ps
CPU time 20.37 seconds
Started May 14 01:37:23 PM PDT 24
Finished May 14 01:37:45 PM PDT 24
Peak memory 214136 kb
Host smart-59b3adeb-b806-4580-88d6-f662d383f49a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819826613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3819826613
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2230363005
Short name T330
Test name
Test status
Simulation time 152240078 ps
CPU time 2.83 seconds
Started May 14 01:37:24 PM PDT 24
Finished May 14 01:37:29 PM PDT 24
Peak memory 213168 kb
Host smart-72fcb488-8138-4d87-928f-09863805f3d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230363005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2230363005
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2573647085
Short name T703
Test name
Test status
Simulation time 1202504497 ps
CPU time 53.31 seconds
Started May 14 01:37:23 PM PDT 24
Finished May 14 01:38:18 PM PDT 24
Peak memory 265884 kb
Host smart-b3a7ed07-184e-47f0-8533-7252b186df6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573647085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2573647085
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.577434630
Short name T458
Test name
Test status
Simulation time 2026282335 ps
CPU time 20.77 seconds
Started May 14 01:37:31 PM PDT 24
Finished May 14 01:37:53 PM PDT 24
Peak memory 250976 kb
Host smart-3341aa9b-836f-4acb-ae4e-f9de3d945e33
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577434630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.577434630
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1352266064
Short name T325
Test name
Test status
Simulation time 29116751 ps
CPU time 1.6 seconds
Started May 14 01:37:24 PM PDT 24
Finished May 14 01:37:27 PM PDT 24
Peak memory 218136 kb
Host smart-064b6bc0-4f42-4c40-9403-87cd043a86bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352266064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1352266064
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1733543147
Short name T68
Test name
Test status
Simulation time 1367322086 ps
CPU time 13.88 seconds
Started May 14 01:37:25 PM PDT 24
Finished May 14 01:37:40 PM PDT 24
Peak memory 218000 kb
Host smart-5f3d6edd-8c9b-4b8a-86c6-b48ee5b0f6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733543147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1733543147
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.344757899
Short name T439
Test name
Test status
Simulation time 1640800010 ps
CPU time 13.89 seconds
Started May 14 01:37:30 PM PDT 24
Finished May 14 01:37:44 PM PDT 24
Peak memory 226044 kb
Host smart-26d60838-3da8-4e80-94e1-b1aaac7aaae3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344757899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.344757899
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2395603630
Short name T460
Test name
Test status
Simulation time 2043864823 ps
CPU time 19.92 seconds
Started May 14 01:37:30 PM PDT 24
Finished May 14 01:37:51 PM PDT 24
Peak memory 218228 kb
Host smart-1ff9f1d3-600b-4796-972b-8a8626eb49d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395603630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2395603630
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.2937772691
Short name T238
Test name
Test status
Simulation time 316529177 ps
CPU time 11.68 seconds
Started May 14 01:37:31 PM PDT 24
Finished May 14 01:37:44 PM PDT 24
Peak memory 218196 kb
Host smart-6794e0f1-bb93-4c0f-84f9-486eb7133343
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937772691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.2
937772691
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2051656429
Short name T49
Test name
Test status
Simulation time 274094159 ps
CPU time 10.45 seconds
Started May 14 01:37:23 PM PDT 24
Finished May 14 01:37:34 PM PDT 24
Peak memory 226200 kb
Host smart-7192b5ab-a507-4a86-a1cc-a504d2311777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051656429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2051656429
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1234985442
Short name T69
Test name
Test status
Simulation time 67426332 ps
CPU time 2.52 seconds
Started May 14 01:37:24 PM PDT 24
Finished May 14 01:37:28 PM PDT 24
Peak memory 218304 kb
Host smart-bbeec838-c4c1-45ff-82c9-a8e1eb8fd1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234985442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1234985442
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.1476565901
Short name T143
Test name
Test status
Simulation time 891066751 ps
CPU time 28.09 seconds
Started May 14 01:37:22 PM PDT 24
Finished May 14 01:37:51 PM PDT 24
Peak memory 249220 kb
Host smart-c417bca0-36db-4663-bb6f-316088b32d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476565901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.1476565901
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.1653030593
Short name T227
Test name
Test status
Simulation time 81890145 ps
CPU time 8.54 seconds
Started May 14 01:37:26 PM PDT 24
Finished May 14 01:37:36 PM PDT 24
Peak memory 246824 kb
Host smart-0a1f7144-87ec-4ac7-9ed1-cd80af5e11c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653030593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.1653030593
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3209936641
Short name T72
Test name
Test status
Simulation time 1072199398 ps
CPU time 48.88 seconds
Started May 14 01:37:30 PM PDT 24
Finished May 14 01:38:21 PM PDT 24
Peak memory 251044 kb
Host smart-abb27590-493c-4f74-88d3-d4ada83b50fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209936641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3209936641
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.814217644
Short name T621
Test name
Test status
Simulation time 52653535 ps
CPU time 0.97 seconds
Started May 14 01:37:23 PM PDT 24
Finished May 14 01:37:25 PM PDT 24
Peak memory 211756 kb
Host smart-7e1fae94-a146-476e-9afd-ff2e4b577d28
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814217644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.814217644
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2272068211
Short name T680
Test name
Test status
Simulation time 19201852 ps
CPU time 1.03 seconds
Started May 14 01:37:33 PM PDT 24
Finished May 14 01:37:35 PM PDT 24
Peak memory 209748 kb
Host smart-d3de13e6-29bd-469e-b5f5-74095cb417d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272068211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2272068211
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1485839178
Short name T805
Test name
Test status
Simulation time 1979413761 ps
CPU time 11.3 seconds
Started May 14 01:37:31 PM PDT 24
Finished May 14 01:37:44 PM PDT 24
Peak memory 218188 kb
Host smart-08f5b416-c7fb-4438-b510-8cb8736f821d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485839178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1485839178
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.987885468
Short name T593
Test name
Test status
Simulation time 808032365 ps
CPU time 5.64 seconds
Started May 14 01:37:30 PM PDT 24
Finished May 14 01:37:36 PM PDT 24
Peak memory 217304 kb
Host smart-a01c8c1b-02d7-4aab-b9c0-cfa13940ba0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987885468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.987885468
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1214925879
Short name T803
Test name
Test status
Simulation time 6889358034 ps
CPU time 81.64 seconds
Started May 14 01:37:31 PM PDT 24
Finished May 14 01:38:55 PM PDT 24
Peak memory 219624 kb
Host smart-e2eb6adf-701a-4e4d-a56a-d82ccb2151de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214925879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1214925879
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2278456876
Short name T857
Test name
Test status
Simulation time 573465359 ps
CPU time 2.06 seconds
Started May 14 01:37:33 PM PDT 24
Finished May 14 01:37:36 PM PDT 24
Peak memory 217224 kb
Host smart-ec78cb86-f0ed-44e5-8fcc-a3320ad03d89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278456876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
278456876
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.371736093
Short name T5
Test name
Test status
Simulation time 2943277644 ps
CPU time 5.34 seconds
Started May 14 01:37:34 PM PDT 24
Finished May 14 01:37:41 PM PDT 24
Peak memory 218148 kb
Host smart-337cc240-67c2-468f-b14c-468e6fc70ab5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371736093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_
prog_failure.371736093
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.1290577654
Short name T218
Test name
Test status
Simulation time 5261977439 ps
CPU time 20.84 seconds
Started May 14 01:37:30 PM PDT 24
Finished May 14 01:37:52 PM PDT 24
Peak memory 214196 kb
Host smart-e9586ce9-0d79-4020-8a5f-a974ef52c1f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290577654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.1290577654
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.4203725662
Short name T76
Test name
Test status
Simulation time 176125968 ps
CPU time 2.04 seconds
Started May 14 01:37:29 PM PDT 24
Finished May 14 01:37:32 PM PDT 24
Peak memory 213264 kb
Host smart-9bf4d3ec-c2fd-4a7e-8b92-a33d55df5f20
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203725662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
4203725662
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3440874157
Short name T866
Test name
Test status
Simulation time 1951927884 ps
CPU time 26.05 seconds
Started May 14 01:37:32 PM PDT 24
Finished May 14 01:38:00 PM PDT 24
Peak memory 251064 kb
Host smart-22d9f1fa-7ccb-45a1-92f9-680911dd4aef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440874157 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3440874157
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2221628986
Short name T729
Test name
Test status
Simulation time 3183975466 ps
CPU time 21.5 seconds
Started May 14 01:37:30 PM PDT 24
Finished May 14 01:37:53 PM PDT 24
Peak memory 251160 kb
Host smart-d65dfef5-2ef8-45ec-9b9e-845dc10f69db
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221628986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2221628986
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.4082751275
Short name T140
Test name
Test status
Simulation time 49066783 ps
CPU time 2.46 seconds
Started May 14 01:37:31 PM PDT 24
Finished May 14 01:37:35 PM PDT 24
Peak memory 218292 kb
Host smart-d4d4c193-016f-49a2-8422-df9cf7e01616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082751275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.4082751275
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1084682358
Short name T732
Test name
Test status
Simulation time 427439744 ps
CPU time 11.82 seconds
Started May 14 01:37:31 PM PDT 24
Finished May 14 01:37:44 PM PDT 24
Peak memory 218152 kb
Host smart-d5afbdbd-579f-441c-8d0e-3f833300af6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084682358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1084682358
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.2544038352
Short name T335
Test name
Test status
Simulation time 533995824 ps
CPU time 15.9 seconds
Started May 14 01:37:32 PM PDT 24
Finished May 14 01:37:50 PM PDT 24
Peak memory 226268 kb
Host smart-e075c146-182c-4441-afd5-b1eabea15f88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544038352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2544038352
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.311603777
Short name T223
Test name
Test status
Simulation time 7000688825 ps
CPU time 19.18 seconds
Started May 14 01:37:31 PM PDT 24
Finished May 14 01:37:52 PM PDT 24
Peak memory 218460 kb
Host smart-3dbe3b2a-a55c-45e7-ac58-9748e56ed16b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311603777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.311603777
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.1310003656
Short name T810
Test name
Test status
Simulation time 448902212 ps
CPU time 10.59 seconds
Started May 14 01:37:30 PM PDT 24
Finished May 14 01:37:42 PM PDT 24
Peak memory 218136 kb
Host smart-727bdc88-dae4-4e50-aa96-1abbe324937e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310003656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.1
310003656
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2308969855
Short name T419
Test name
Test status
Simulation time 1400991969 ps
CPU time 9.53 seconds
Started May 14 01:37:33 PM PDT 24
Finished May 14 01:37:44 PM PDT 24
Peak memory 225164 kb
Host smart-a2dae62b-ec32-43ef-9732-5a5ee6c2c124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308969855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2308969855
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1542641511
Short name T64
Test name
Test status
Simulation time 59338730 ps
CPU time 2.77 seconds
Started May 14 01:37:30 PM PDT 24
Finished May 14 01:37:34 PM PDT 24
Peak memory 214432 kb
Host smart-dddd1cd0-98f6-4664-8613-8110351421d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542641511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1542641511
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.1344297009
Short name T290
Test name
Test status
Simulation time 905047540 ps
CPU time 24.72 seconds
Started May 14 01:37:30 PM PDT 24
Finished May 14 01:37:56 PM PDT 24
Peak memory 251020 kb
Host smart-6e7206aa-a57a-4824-9fd3-34cb90a32126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344297009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.1344297009
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.664471137
Short name T674
Test name
Test status
Simulation time 60138085 ps
CPU time 6.53 seconds
Started May 14 01:37:32 PM PDT 24
Finished May 14 01:37:40 PM PDT 24
Peak memory 244184 kb
Host smart-80e699c9-72de-422a-9832-14296716ffbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664471137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.664471137
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.775552999
Short name T337
Test name
Test status
Simulation time 8240060122 ps
CPU time 70.5 seconds
Started May 14 01:37:32 PM PDT 24
Finished May 14 01:38:44 PM PDT 24
Peak memory 269444 kb
Host smart-dae1c700-9d09-4540-ae24-cd6b85da115f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775552999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.775552999
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.3606110556
Short name T146
Test name
Test status
Simulation time 30081616984 ps
CPU time 270.24 seconds
Started May 14 01:37:34 PM PDT 24
Finished May 14 01:42:06 PM PDT 24
Peak memory 280200 kb
Host smart-986d3787-cd10-42ed-ac02-db2a6564d1fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3606110556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.3606110556
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1331854634
Short name T489
Test name
Test status
Simulation time 12150318 ps
CPU time 1.03 seconds
Started May 14 01:37:30 PM PDT 24
Finished May 14 01:37:33 PM PDT 24
Peak memory 211720 kb
Host smart-b0f2ffab-8ef0-44d2-8e3d-c66f774ea2c0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331854634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1331854634
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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