Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116440844

1

T1

72283

T2

981

T3

29114

auto[1]

1422000

1

T1

196

T3

2772

T11

1386

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

116424201

1

T1

72381

T2

981

T3

28322

auto[1]

1438643

1

T1

98

T3

3564

T11

1386

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7454403	1			T1	1249		T2	144		T3	9467
auto[IdleSt]	22262916	1			T1	23450		T2	69		T3	1297
auto[ClkMuxSt]	36840	1			T1	9		T2	1		T4	76
auto[CntIncrSt]	36529	1			T1	9		T2	1		T4	76
auto[CntProgSt]	1664056	1			T1	193		T2	60		T4	2176
auto[TransCheckSt]	28576	1			T1	9		T2	1		T4	76
auto[TokenHashSt]	52547427	1			T1	209		T2	12		T4	855
auto[FlashRmaSt]	28869	1			T1	29		T4	63		T5	6
auto[TokenCheck0St]	12926	1			T1	9		T4	37		T5	6
auto[TokenCheck1St]	9405	1			T1	9		T4	11		T5	6
auto[TransProgSt]	430776	1			T1	199		T5	110		T11	1544
auto[PostTransSt]	13677347	1			T1	31843		T2	693		T4	12289
auto[ScrapSt]	271781	1			T22	723		T21	401		T42	6
auto[EscalateSt]	7033683	1			T1	8133		T3	9461		T11	3570
auto[InvalidSt]	12365200	1			T1	7129		T3	11652		T11	1274

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2110	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12365200	1			T1	7129		T3	11652		T11	1274
EscalateSt	7033683	1			T1	8133		T3	9461		T11	3570
ScrapSt	271781	1			T22	723		T21	401		T42	6
PostTransSt	13677347	1			T1	31843		T2	693		T4	12289
TransProgSt	430776	1			T1	199		T5	110		T11	1544
TokenCheck1St	9405	1			T1	9		T4	11		T5	6
TokenCheck0St	12926	1			T1	9		T4	37		T5	6
FlashRmaSt	28869	1			T1	29		T4	63		T5	6
TokenHashSt	52547427	1			T1	209		T2	12		T4	855
TransCheckSt	28576	1			T1	9		T2	1		T4	76
CntProgSt	1664056	1			T1	193		T2	60		T4	2176
CntIncrSt	36529	1			T1	9		T2	1		T4	76
ClkMuxSt	36840	1			T1	9		T2	1		T4	76
IdleSt	22262916	1			T1	23450		T2	69		T3	1297
ResetSt	7454403	1			T1	1249		T2	144		T3	9467
arcs[ResetSt=>IdleSt]	55787	1			T1	13		T2	1		T3	78
arcs[IdleSt=>ScrapSt]	307	1			T22	1		T21	1		T42	2
arcs[IdleSt=>ClkMuxSt]	36604	1			T1	9		T2	1		T4	76
arcs[ClkMuxSt=>CntIncrSt]	36529	1			T1	9		T2	1		T4	76
arcs[CntIncrSt=>PostTransSt]	2031	1			T15	8		T16	4		T17	8
arcs[CntIncrSt=>CntProgSt]	34424	1			T1	9		T2	1		T4	76
arcs[CntProgSt=>PostTransSt]	4774	1			T11	11		T12	20		T13	14
arcs[CntProgSt=>TransCheckSt]	28576	1			T1	9		T2	1		T4	76
arcs[TransCheckSt=>PostTransSt]	3974	1			T4	32		T15	16		T16	3
arcs[TransCheckSt=>TokenHashSt]	24474	1			T1	9		T2	1		T4	44
arcs[TokenHashSt=>PostTransSt]	10762	1			T2	1		T4	7		T11	9
arcs[TokenHashSt=>FlashRmaSt]	13014	1			T1	9		T4	37		T5	6
arcs[FlashRmaSt=>TokenCheck0St]	12926	1			T1	9		T4	37		T5	6
arcs[TokenCheck0St=>PostTransSt]	3500	1			T4	26		T11	14		T20	15
arcs[TokenCheck0St=>TokenCheck1St]	9405	1			T1	9		T4	11		T5	6
arcs[TokenCheck1St=>PostTransSt]	649	1			T4	11		T11	2		T25	3
arcs[TransProgSt=>PostTransSt]	7907	1			T1	9		T5	6		T11	34
arcs[IdleSt=>EscalateSt]	225	1			T47	5		T48	10		T50	6
arcs[ClkMuxSt=>EscalateSt]	75	1			T42	3		T47	3		T48	2
arcs[CntIncrSt=>EscalateSt]	74	1			T42	2		T47	1		T48	1
arcs[CntProgSt=>EscalateSt]	1074	1			T42	26		T47	35		T48	4
arcs[TransCheckSt=>EscalateSt]	128	1			T48	7		T50	1		T49	5
arcs[TokenHashSt=>EscalateSt]	698	1			T42	11		T47	6		T48	26
arcs[FlashRmaSt=>EscalateSt]	88	1			T47	2		T48	2		T49	2
arcs[TokenCheck0St=>EscalateSt]	21	1			T42	1		T54	1		T55	1
arcs[TokenCheck1St=>EscalateSt]	153	1			T42	4		T47	2		T48	4
arcs[TransProgSt=>EscalateSt]	696	1			T42	13		T47	16		T48	3
arcs[PostTransSt=>EscalateSt]	5038	1			T11	11		T12	20		T13	14
arcs[InvalidSt=>EscalateSt]	14360	1			T1	3		T3	64		T11	17

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7454237	1			T1	1249		T2	144		T3	9467
auto[0]	auto[IdleSt]	22262763	1			T1	23450		T2	69		T3	1297
auto[0]	auto[ClkMuxSt]	36790	1			T1	9		T2	1		T4	76
auto[0]	auto[CntIncrSt]	36482	1			T1	9		T2	1		T4	76
auto[0]	auto[CntProgSt]	1663331	1			T1	193		T2	60		T4	2176
auto[0]	auto[TransCheckSt]	28491	1			T1	9		T2	1		T4	76
auto[0]	auto[TokenHashSt]	52546974	1			T1	209		T2	12		T4	855
auto[0]	auto[FlashRmaSt]	28806	1			T1	29		T4	63		T5	6
auto[0]	auto[TokenCheck0St]	12911	1			T1	9		T4	37		T5	6
auto[0]	auto[TokenCheck1St]	9296	1			T1	9		T4	11		T5	6
auto[0]	auto[TransProgSt]	430304	1			T1	199		T5	110		T11	1544
auto[0]	auto[PostTransSt]	13674847	1			T1	31843		T2	693		T4	12289
auto[0]	auto[ScrapSt]	271738	1			T22	723		T21	401		T42	5
auto[0]	auto[EscalateSt]	5623715	1			T1	7939		T3	6717		T11	2198
auto[0]	auto[InvalidSt]	12358049	1			T1	7127		T3	11624		T11	1265
auto[1]	auto[ResetSt]	166	1			T42	7		T47	5		T48	6
auto[1]	auto[IdleSt]	153	1			T47	5		T48	6		T50	2
auto[1]	auto[ClkMuxSt]	50	1			T42	1		T47	2		T48	1
auto[1]	auto[CntIncrSt]	47	1			T42	2		T54	1		T230	2
auto[1]	auto[CntProgSt]	725	1			T42	12		T47	24		T48	4
auto[1]	auto[TransCheckSt]	85	1			T48	5		T49	3		T54	5
auto[1]	auto[TokenHashSt]	453	1			T42	10		T47	4		T48	19
auto[1]	auto[FlashRmaSt]	63	1			T47	2		T48	2		T49	1
auto[1]	auto[TokenCheck0St]	15	1			T42	1		T54	1		T55	1
auto[1]	auto[TokenCheck1St]	109	1			T42	3		T47	1		T48	3
auto[1]	auto[TransProgSt]	472	1			T42	7		T47	11		T48	3
auto[1]	auto[PostTransSt]	2500	1			T11	5		T12	11		T13	9
auto[1]	auto[ScrapSt]	43	1			T42	1		T50	1		T49	2
auto[1]	auto[EscalateSt]	1409968	1			T1	194		T3	2744		T11	1372
auto[1]	auto[InvalidSt]	7151	1			T1	2		T3	28		T11	9

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7454240	1			T1	1249		T2	144		T3	9467
auto[0]	auto[IdleSt]	22262770	1			T1	23450		T2	69		T3	1297
auto[0]	auto[ClkMuxSt]	36789	1			T1	9		T2	1		T4	76
auto[0]	auto[CntIncrSt]	36481	1			T1	9		T2	1		T4	76
auto[0]	auto[CntProgSt]	1663295	1			T1	193		T2	60		T4	2176
auto[0]	auto[TransCheckSt]	28492	1			T1	9		T2	1		T4	76
auto[0]	auto[TokenHashSt]	52546971	1			T1	209		T2	12		T4	855
auto[0]	auto[FlashRmaSt]	28822	1			T1	29		T4	63		T5	6
auto[0]	auto[TokenCheck0St]	12912	1			T1	9		T4	37		T5	6
auto[0]	auto[TokenCheck1St]	9306	1			T1	9		T4	11		T5	6
auto[0]	auto[TransProgSt]	430298	1			T1	199		T5	110		T11	1544
auto[0]	auto[PostTransSt]	13674740	1			T1	31843		T2	693		T4	12289
auto[0]	auto[ScrapSt]	271732	1			T22	723		T21	401		T42	5
auto[0]	auto[EscalateSt]	5607252	1			T1	8036		T3	5933		T11	2198
auto[0]	auto[InvalidSt]	12357991	1			T1	7128		T3	11616		T11	1266
auto[1]	auto[ResetSt]	163	1			T42	4		T47	3		T48	3
auto[1]	auto[IdleSt]	146	1			T47	4		T48	6		T50	4
auto[1]	auto[ClkMuxSt]	51	1			T42	3		T47	2		T48	2
auto[1]	auto[CntIncrSt]	48	1			T42	1		T47	1		T48	1
auto[1]	auto[CntProgSt]	761	1			T42	21		T47	27		T48	2
auto[1]	auto[TransCheckSt]	84	1			T48	4		T50	1		T49	5
auto[1]	auto[TokenHashSt]	456	1			T42	4		T47	4		T48	16
auto[1]	auto[FlashRmaSt]	47	1			T49	1		T54	3		T230	2
auto[1]	auto[TokenCheck0St]	14	1			T42	1		T231	1		T100	1
auto[1]	auto[TokenCheck1St]	99	1			T42	2		T47	1		T48	3
auto[1]	auto[TransProgSt]	478	1			T42	10		T47	10		T48	2
auto[1]	auto[PostTransSt]	2607	1			T11	6		T12	9		T13	5
auto[1]	auto[ScrapSt]	49	1			T42	1		T50	1		T49	1
auto[1]	auto[EscalateSt]	1426431	1			T1	97		T3	3528		T11	1372
auto[1]	auto[InvalidSt]	7209	1			T1	1		T3	36		T11	8