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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.92 97.82 96.12 93.31 97.62 98.52 98.76 96.29


Total test records in report: 1000
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T818 /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3997702720 May 16 03:30:11 PM PDT 24 May 16 03:30:35 PM PDT 24 1041847207 ps
T819 /workspace/coverage/default/3.lc_ctrl_state_failure.760252166 May 16 03:29:31 PM PDT 24 May 16 03:29:59 PM PDT 24 207806375 ps
T820 /workspace/coverage/default/26.lc_ctrl_smoke.748579307 May 16 03:30:58 PM PDT 24 May 16 03:31:08 PM PDT 24 144758852 ps
T821 /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.357923588 May 16 03:30:32 PM PDT 24 May 16 03:30:42 PM PDT 24 18959385 ps
T822 /workspace/coverage/default/10.lc_ctrl_sec_token_mux.87846758 May 16 03:30:00 PM PDT 24 May 16 03:30:17 PM PDT 24 456552300 ps
T823 /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1240773685 May 16 03:31:07 PM PDT 24 May 16 03:31:20 PM PDT 24 238752748 ps
T824 /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.384684282 May 16 03:31:45 PM PDT 24 May 16 03:31:52 PM PDT 24 14507035 ps
T825 /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2785922524 May 16 03:30:12 PM PDT 24 May 16 03:30:34 PM PDT 24 1439801985 ps
T826 /workspace/coverage/default/17.lc_ctrl_jtag_smoke.380549730 May 16 03:30:33 PM PDT 24 May 16 03:30:53 PM PDT 24 412011361 ps
T827 /workspace/coverage/default/41.lc_ctrl_prog_failure.153214123 May 16 03:31:32 PM PDT 24 May 16 03:31:41 PM PDT 24 30467247 ps
T828 /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2128175515 May 16 03:30:46 PM PDT 24 May 16 03:31:04 PM PDT 24 188870321 ps
T829 /workspace/coverage/default/7.lc_ctrl_state_post_trans.2707759079 May 16 03:29:47 PM PDT 24 May 16 03:30:04 PM PDT 24 95671220 ps
T830 /workspace/coverage/default/44.lc_ctrl_prog_failure.2983351246 May 16 03:31:45 PM PDT 24 May 16 03:31:53 PM PDT 24 75855428 ps
T831 /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2757773544 May 16 03:29:42 PM PDT 24 May 16 03:29:55 PM PDT 24 1254898021 ps
T183 /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.1037620167 May 16 03:30:23 PM PDT 24 May 16 03:52:09 PM PDT 24 149208897135 ps
T832 /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1635952113 May 16 03:30:00 PM PDT 24 May 16 03:30:19 PM PDT 24 304086692 ps
T833 /workspace/coverage/default/30.lc_ctrl_state_failure.2358275264 May 16 03:31:06 PM PDT 24 May 16 03:31:39 PM PDT 24 520809197 ps
T834 /workspace/coverage/default/35.lc_ctrl_sec_mubi.1869278869 May 16 03:31:24 PM PDT 24 May 16 03:31:47 PM PDT 24 1895736380 ps
T835 /workspace/coverage/default/2.lc_ctrl_errors.3130368559 May 16 03:29:31 PM PDT 24 May 16 03:29:55 PM PDT 24 2450140586 ps
T836 /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1200212962 May 16 03:31:18 PM PDT 24 May 16 03:31:40 PM PDT 24 6117497122 ps
T837 /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1410200228 May 16 03:30:00 PM PDT 24 May 16 03:30:17 PM PDT 24 1097882281 ps
T838 /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3367100677 May 16 03:30:08 PM PDT 24 May 16 03:30:27 PM PDT 24 5784700435 ps
T839 /workspace/coverage/default/20.lc_ctrl_sec_token_mux.4128061423 May 16 03:30:39 PM PDT 24 May 16 03:30:58 PM PDT 24 2120350033 ps
T840 /workspace/coverage/default/1.lc_ctrl_jtag_priority.3137702268 May 16 03:29:25 PM PDT 24 May 16 03:29:45 PM PDT 24 564773557 ps
T841 /workspace/coverage/default/11.lc_ctrl_errors.2255494657 May 16 03:29:57 PM PDT 24 May 16 03:30:18 PM PDT 24 759296335 ps
T842 /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2623525175 May 16 03:31:34 PM PDT 24 May 16 03:31:52 PM PDT 24 7744793633 ps
T843 /workspace/coverage/default/38.lc_ctrl_sec_token_mux.31929561 May 16 03:31:35 PM PDT 24 May 16 03:31:57 PM PDT 24 2420133976 ps
T844 /workspace/coverage/default/29.lc_ctrl_errors.3393740478 May 16 03:31:08 PM PDT 24 May 16 03:31:29 PM PDT 24 368129760 ps
T845 /workspace/coverage/default/43.lc_ctrl_state_failure.4137779264 May 16 03:31:45 PM PDT 24 May 16 03:32:18 PM PDT 24 458936379 ps
T846 /workspace/coverage/default/8.lc_ctrl_sec_mubi.2603254630 May 16 03:29:54 PM PDT 24 May 16 03:30:14 PM PDT 24 453679042 ps
T847 /workspace/coverage/default/35.lc_ctrl_state_post_trans.2498300197 May 16 03:31:15 PM PDT 24 May 16 03:31:27 PM PDT 24 185784477 ps
T848 /workspace/coverage/default/3.lc_ctrl_jtag_errors.2076964948 May 16 03:29:33 PM PDT 24 May 16 03:30:05 PM PDT 24 1416400132 ps
T849 /workspace/coverage/default/3.lc_ctrl_sec_token_mux.543189752 May 16 03:29:35 PM PDT 24 May 16 03:29:53 PM PDT 24 567478328 ps
T850 /workspace/coverage/default/2.lc_ctrl_state_post_trans.530985352 May 16 03:29:31 PM PDT 24 May 16 03:29:47 PM PDT 24 865762993 ps
T851 /workspace/coverage/default/29.lc_ctrl_alert_test.3309668149 May 16 03:31:09 PM PDT 24 May 16 03:31:16 PM PDT 24 43283445 ps
T852 /workspace/coverage/default/16.lc_ctrl_stress_all.2234920579 May 16 03:30:33 PM PDT 24 May 16 03:31:32 PM PDT 24 1553314101 ps
T853 /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.731073771 May 16 03:30:49 PM PDT 24 May 16 03:30:59 PM PDT 24 44399986 ps
T854 /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1225448618 May 16 03:29:46 PM PDT 24 May 16 03:30:01 PM PDT 24 385973575 ps
T855 /workspace/coverage/default/23.lc_ctrl_smoke.3512654291 May 16 03:30:48 PM PDT 24 May 16 03:30:59 PM PDT 24 43501311 ps
T856 /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2999447883 May 16 03:31:07 PM PDT 24 May 16 03:31:35 PM PDT 24 643988116 ps
T857 /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.960966153 May 16 03:29:24 PM PDT 24 May 16 03:29:31 PM PDT 24 18107218 ps
T858 /workspace/coverage/default/29.lc_ctrl_prog_failure.4058113459 May 16 03:31:05 PM PDT 24 May 16 03:31:13 PM PDT 24 196503481 ps
T859 /workspace/coverage/default/49.lc_ctrl_state_failure.149984101 May 16 03:31:57 PM PDT 24 May 16 03:32:35 PM PDT 24 835480732 ps
T860 /workspace/coverage/default/21.lc_ctrl_smoke.861317884 May 16 03:30:37 PM PDT 24 May 16 03:30:47 PM PDT 24 23250038 ps
T861 /workspace/coverage/default/21.lc_ctrl_jtag_access.726431208 May 16 03:30:43 PM PDT 24 May 16 03:30:54 PM PDT 24 228474300 ps
T862 /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3094006976 May 16 03:31:09 PM PDT 24 May 16 03:31:30 PM PDT 24 887867843 ps
T863 /workspace/coverage/default/2.lc_ctrl_sec_mubi.2360551580 May 16 03:29:30 PM PDT 24 May 16 03:29:54 PM PDT 24 324415634 ps
T864 /workspace/coverage/default/30.lc_ctrl_alert_test.3373152543 May 16 03:31:08 PM PDT 24 May 16 03:31:15 PM PDT 24 83880291 ps
T865 /workspace/coverage/default/45.lc_ctrl_prog_failure.411341286 May 16 03:31:44 PM PDT 24 May 16 03:31:52 PM PDT 24 54277714 ps
T866 /workspace/coverage/default/48.lc_ctrl_sec_token_digest.258620406 May 16 03:31:59 PM PDT 24 May 16 03:32:17 PM PDT 24 271553123 ps
T867 /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.699878093 May 16 03:29:48 PM PDT 24 May 16 03:30:14 PM PDT 24 2464562343 ps
T868 /workspace/coverage/default/48.lc_ctrl_alert_test.3659745648 May 16 03:31:56 PM PDT 24 May 16 03:32:06 PM PDT 24 19054437 ps
T869 /workspace/coverage/default/20.lc_ctrl_state_post_trans.1414750129 May 16 03:30:44 PM PDT 24 May 16 03:30:57 PM PDT 24 106869412 ps
T870 /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.3827690858 May 16 03:31:15 PM PDT 24 May 16 03:39:33 PM PDT 24 99179020207 ps
T871 /workspace/coverage/default/0.lc_ctrl_sec_mubi.3879395853 May 16 03:29:27 PM PDT 24 May 16 03:29:44 PM PDT 24 625923059 ps
T872 /workspace/coverage/default/5.lc_ctrl_prog_failure.1920496296 May 16 03:29:47 PM PDT 24 May 16 03:29:58 PM PDT 24 290461080 ps
T873 /workspace/coverage/default/12.lc_ctrl_smoke.527445231 May 16 03:30:01 PM PDT 24 May 16 03:30:13 PM PDT 24 55209043 ps
T874 /workspace/coverage/default/46.lc_ctrl_stress_all.4239377873 May 16 03:31:55 PM PDT 24 May 16 03:33:23 PM PDT 24 2097705060 ps
T875 /workspace/coverage/default/30.lc_ctrl_sec_mubi.3609830738 May 16 03:31:08 PM PDT 24 May 16 03:31:39 PM PDT 24 580042972 ps
T876 /workspace/coverage/default/20.lc_ctrl_jtag_access.1506506305 May 16 03:30:43 PM PDT 24 May 16 03:31:03 PM PDT 24 1670911366 ps
T877 /workspace/coverage/default/23.lc_ctrl_prog_failure.4081355043 May 16 03:30:47 PM PDT 24 May 16 03:30:58 PM PDT 24 148334216 ps
T878 /workspace/coverage/default/24.lc_ctrl_jtag_access.1803741594 May 16 03:30:48 PM PDT 24 May 16 03:31:01 PM PDT 24 878690182 ps
T879 /workspace/coverage/default/3.lc_ctrl_alert_test.2077013504 May 16 03:29:30 PM PDT 24 May 16 03:29:39 PM PDT 24 24210870 ps
T880 /workspace/coverage/default/44.lc_ctrl_stress_all.3207012950 May 16 03:31:47 PM PDT 24 May 16 03:43:01 PM PDT 24 734065266040 ps
T881 /workspace/coverage/default/5.lc_ctrl_stress_all.1375091005 May 16 03:29:46 PM PDT 24 May 16 03:36:15 PM PDT 24 16093917024 ps
T118 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2849465739 May 16 03:28:46 PM PDT 24 May 16 03:28:57 PM PDT 24 53092727 ps
T126 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2321716696 May 16 03:29:10 PM PDT 24 May 16 03:29:18 PM PDT 24 60512792 ps
T119 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3645885744 May 16 03:29:08 PM PDT 24 May 16 03:29:14 PM PDT 24 39692992 ps
T120 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3827967496 May 16 03:29:09 PM PDT 24 May 16 03:29:16 PM PDT 24 61963685 ps
T146 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1276039054 May 16 03:28:57 PM PDT 24 May 16 03:29:08 PM PDT 24 117195897 ps
T163 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1007728555 May 16 03:28:48 PM PDT 24 May 16 03:29:00 PM PDT 24 72109206 ps
T180 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.553883744 May 16 03:29:12 PM PDT 24 May 16 03:29:19 PM PDT 24 24143169 ps
T110 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.374188806 May 16 03:28:48 PM PDT 24 May 16 03:29:00 PM PDT 24 96355380 ps
T114 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1405394806 May 16 03:29:08 PM PDT 24 May 16 03:29:15 PM PDT 24 24258045 ps
T217 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1175865380 May 16 03:29:13 PM PDT 24 May 16 03:29:20 PM PDT 24 48787234 ps
T218 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2910491814 May 16 03:28:46 PM PDT 24 May 16 03:28:57 PM PDT 24 58414316 ps
T882 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2804746785 May 16 03:29:14 PM PDT 24 May 16 03:29:22 PM PDT 24 47624428 ps
T181 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3155391786 May 16 03:29:10 PM PDT 24 May 16 03:29:17 PM PDT 24 84065819 ps
T111 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.882421275 May 16 03:29:09 PM PDT 24 May 16 03:29:18 PM PDT 24 776778927 ps
T164 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2097039380 May 16 03:29:16 PM PDT 24 May 16 03:29:24 PM PDT 24 21944241 ps
T149 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1187061978 May 16 03:29:08 PM PDT 24 May 16 03:29:20 PM PDT 24 4856299652 ps
T165 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3067789184 May 16 03:28:46 PM PDT 24 May 16 03:28:57 PM PDT 24 19784067 ps
T112 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.789759305 May 16 03:29:11 PM PDT 24 May 16 03:29:19 PM PDT 24 23801463 ps
T883 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1495876140 May 16 03:29:17 PM PDT 24 May 16 03:29:25 PM PDT 24 51348974 ps
T884 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1403150677 May 16 03:28:44 PM PDT 24 May 16 03:28:56 PM PDT 24 96525805 ps
T885 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1691906615 May 16 03:28:49 PM PDT 24 May 16 03:29:01 PM PDT 24 112111468 ps
T166 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.4053613678 May 16 03:28:46 PM PDT 24 May 16 03:28:59 PM PDT 24 56341879 ps
T147 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2850681006 May 16 03:29:02 PM PDT 24 May 16 03:29:12 PM PDT 24 220355301 ps
T886 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3978791822 May 16 03:28:42 PM PDT 24 May 16 03:29:07 PM PDT 24 3884537651 ps
T115 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1248868091 May 16 03:29:13 PM PDT 24 May 16 03:29:24 PM PDT 24 1508320115 ps
T887 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3171699603 May 16 03:28:54 PM PDT 24 May 16 03:29:06 PM PDT 24 145511328 ps
T888 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3290473122 May 16 03:28:48 PM PDT 24 May 16 03:29:03 PM PDT 24 1478887798 ps
T167 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3334918480 May 16 03:28:39 PM PDT 24 May 16 03:28:51 PM PDT 24 46869876 ps
T116 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3324310374 May 16 03:28:40 PM PDT 24 May 16 03:28:53 PM PDT 24 77323272 ps
T889 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1666536350 May 16 03:28:48 PM PDT 24 May 16 03:29:01 PM PDT 24 74337169 ps
T219 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1784992796 May 16 03:28:44 PM PDT 24 May 16 03:28:56 PM PDT 24 44410381 ps
T168 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.957417004 May 16 03:28:38 PM PDT 24 May 16 03:28:50 PM PDT 24 27151461 ps
T220 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.608418840 May 16 03:28:50 PM PDT 24 May 16 03:29:01 PM PDT 24 86789656 ps
T169 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.605883912 May 16 03:28:44 PM PDT 24 May 16 03:28:56 PM PDT 24 153524071 ps
T890 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1915463221 May 16 03:28:49 PM PDT 24 May 16 03:29:21 PM PDT 24 3876272257 ps
T121 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1596651827 May 16 03:29:08 PM PDT 24 May 16 03:29:16 PM PDT 24 58459551 ps
T221 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2963713712 May 16 03:28:53 PM PDT 24 May 16 03:29:05 PM PDT 24 16674591 ps
T891 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2665361365 May 16 03:28:49 PM PDT 24 May 16 03:29:01 PM PDT 24 382430318 ps
T216 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2984721719 May 16 03:28:41 PM PDT 24 May 16 03:28:53 PM PDT 24 157183579 ps
T141 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.851200954 May 16 03:29:12 PM PDT 24 May 16 03:29:19 PM PDT 24 33655518 ps
T222 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.4153510027 May 16 03:28:45 PM PDT 24 May 16 03:28:57 PM PDT 24 26984063 ps
T122 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2835558486 May 16 03:29:13 PM PDT 24 May 16 03:29:21 PM PDT 24 26497373 ps
T117 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1819874116 May 16 03:29:11 PM PDT 24 May 16 03:29:20 PM PDT 24 57876577 ps
T123 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1290906283 May 16 03:29:13 PM PDT 24 May 16 03:29:23 PM PDT 24 311829153 ps
T148 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.338496494 May 16 03:28:59 PM PDT 24 May 16 03:29:09 PM PDT 24 208488306 ps
T892 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3729068079 May 16 03:28:47 PM PDT 24 May 16 03:29:04 PM PDT 24 2615443828 ps
T129 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4066121794 May 16 03:28:56 PM PDT 24 May 16 03:29:09 PM PDT 24 115113300 ps
T893 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1821883075 May 16 03:29:10 PM PDT 24 May 16 03:29:17 PM PDT 24 161620656 ps
T223 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.245674385 May 16 03:28:52 PM PDT 24 May 16 03:29:03 PM PDT 24 15430442 ps
T134 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2611148196 May 16 03:29:03 PM PDT 24 May 16 03:29:12 PM PDT 24 33503604 ps
T142 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3072042652 May 16 03:29:09 PM PDT 24 May 16 03:29:16 PM PDT 24 72209632 ps
T894 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3383138483 May 16 03:29:19 PM PDT 24 May 16 03:29:26 PM PDT 24 15617836 ps
T895 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3192800744 May 16 03:28:54 PM PDT 24 May 16 03:29:39 PM PDT 24 1473855923 ps
T896 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2895391504 May 16 03:29:02 PM PDT 24 May 16 03:29:10 PM PDT 24 65953185 ps
T137 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1156602726 May 16 03:29:10 PM PDT 24 May 16 03:29:18 PM PDT 24 42570111 ps
T127 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2643538720 May 16 03:29:15 PM PDT 24 May 16 03:29:25 PM PDT 24 269599458 ps
T897 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1275740715 May 16 03:28:49 PM PDT 24 May 16 03:29:03 PM PDT 24 777721494 ps
T139 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4192783848 May 16 03:29:10 PM PDT 24 May 16 03:29:17 PM PDT 24 26268921 ps
T898 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2437261308 May 16 03:28:50 PM PDT 24 May 16 03:29:04 PM PDT 24 263830061 ps
T899 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.29050474 May 16 03:29:01 PM PDT 24 May 16 03:29:10 PM PDT 24 27436123 ps
T900 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1500021794 May 16 03:28:55 PM PDT 24 May 16 03:29:07 PM PDT 24 152150239 ps
T901 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2577795101 May 16 03:28:45 PM PDT 24 May 16 03:28:57 PM PDT 24 93884032 ps
T902 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.635719023 May 16 03:29:11 PM PDT 24 May 16 03:29:21 PM PDT 24 587247140 ps
T903 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2436431115 May 16 03:28:42 PM PDT 24 May 16 03:28:53 PM PDT 24 12898922 ps
T904 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3055894985 May 16 03:28:53 PM PDT 24 May 16 03:29:10 PM PDT 24 1344613375 ps
T905 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2302520401 May 16 03:28:53 PM PDT 24 May 16 03:29:04 PM PDT 24 21748587 ps
T906 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2925399295 May 16 03:28:45 PM PDT 24 May 16 03:28:56 PM PDT 24 51974582 ps
T907 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.553275270 May 16 03:28:42 PM PDT 24 May 16 03:28:58 PM PDT 24 1851779087 ps
T128 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2779419950 May 16 03:28:47 PM PDT 24 May 16 03:29:00 PM PDT 24 49784644 ps
T206 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1420002944 May 16 03:28:37 PM PDT 24 May 16 03:28:49 PM PDT 24 16638057 ps
T135 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2321050313 May 16 03:28:43 PM PDT 24 May 16 03:28:57 PM PDT 24 170905026 ps
T908 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3361637097 May 16 03:29:11 PM PDT 24 May 16 03:29:19 PM PDT 24 62650459 ps
T909 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.410024969 May 16 03:29:10 PM PDT 24 May 16 03:29:18 PM PDT 24 63420334 ps
T125 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2653352862 May 16 03:29:12 PM PDT 24 May 16 03:29:19 PM PDT 24 206299068 ps
T910 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1488476557 May 16 03:28:44 PM PDT 24 May 16 03:28:56 PM PDT 24 15178415 ps
T911 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1057042769 May 16 03:28:54 PM PDT 24 May 16 03:29:06 PM PDT 24 41411932 ps
T124 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2628775969 May 16 03:29:05 PM PDT 24 May 16 03:29:13 PM PDT 24 83465094 ps
T912 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1045527261 May 16 03:28:48 PM PDT 24 May 16 03:29:00 PM PDT 24 18008448 ps
T913 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.766565596 May 16 03:29:12 PM PDT 24 May 16 03:29:19 PM PDT 24 57990359 ps
T914 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.427003519 May 16 03:28:53 PM PDT 24 May 16 03:29:06 PM PDT 24 28951675 ps
T915 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.719728976 May 16 03:28:46 PM PDT 24 May 16 03:28:57 PM PDT 24 81811392 ps
T916 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3190709050 May 16 03:29:09 PM PDT 24 May 16 03:29:16 PM PDT 24 27604788 ps
T917 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.70041937 May 16 03:28:52 PM PDT 24 May 16 03:29:21 PM PDT 24 6294959851 ps
T918 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1367274619 May 16 03:28:54 PM PDT 24 May 16 03:29:05 PM PDT 24 41322702 ps
T919 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.4141118450 May 16 03:28:51 PM PDT 24 May 16 03:29:03 PM PDT 24 53415824 ps
T207 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.950586271 May 16 03:28:42 PM PDT 24 May 16 03:28:53 PM PDT 24 19085479 ps
T920 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3771696638 May 16 03:29:09 PM PDT 24 May 16 03:29:17 PM PDT 24 286338342 ps
T208 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.748211897 May 16 03:28:55 PM PDT 24 May 16 03:29:06 PM PDT 24 204555860 ps
T921 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.768745300 May 16 03:28:37 PM PDT 24 May 16 03:28:49 PM PDT 24 110040149 ps
T922 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1176915598 May 16 03:28:52 PM PDT 24 May 16 03:29:04 PM PDT 24 19699204 ps
T923 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2421036770 May 16 03:28:48 PM PDT 24 May 16 03:29:00 PM PDT 24 531616646 ps
T924 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.220260774 May 16 03:28:44 PM PDT 24 May 16 03:28:56 PM PDT 24 21991762 ps
T136 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2815945830 May 16 03:28:50 PM PDT 24 May 16 03:29:03 PM PDT 24 145072744 ps
T209 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1614770945 May 16 03:29:10 PM PDT 24 May 16 03:29:16 PM PDT 24 40130780 ps
T925 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2916151261 May 16 03:29:10 PM PDT 24 May 16 03:29:18 PM PDT 24 46158476 ps
T926 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3702033129 May 16 03:28:52 PM PDT 24 May 16 03:29:04 PM PDT 24 248865219 ps
T927 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.340601424 May 16 03:28:49 PM PDT 24 May 16 03:29:00 PM PDT 24 76816661 ps
T928 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1942600550 May 16 03:29:10 PM PDT 24 May 16 03:29:17 PM PDT 24 14530654 ps
T929 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2781722434 May 16 03:28:54 PM PDT 24 May 16 03:29:06 PM PDT 24 90278717 ps
T930 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3326193914 May 16 03:29:10 PM PDT 24 May 16 03:29:17 PM PDT 24 36201132 ps
T931 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1880619839 May 16 03:28:50 PM PDT 24 May 16 03:29:02 PM PDT 24 66758617 ps
T210 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2676612747 May 16 03:29:01 PM PDT 24 May 16 03:29:09 PM PDT 24 28055047 ps
T211 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.96410167 May 16 03:28:54 PM PDT 24 May 16 03:29:05 PM PDT 24 62524709 ps
T140 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3162402921 May 16 03:28:51 PM PDT 24 May 16 03:29:05 PM PDT 24 501553438 ps
T932 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3822629703 May 16 03:29:12 PM PDT 24 May 16 03:29:19 PM PDT 24 17576626 ps
T933 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3759751126 May 16 03:28:49 PM PDT 24 May 16 03:29:01 PM PDT 24 77275468 ps
T934 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.359554695 May 16 03:29:04 PM PDT 24 May 16 03:29:24 PM PDT 24 3644040501 ps
T935 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3549694813 May 16 03:29:01 PM PDT 24 May 16 03:29:13 PM PDT 24 605168296 ps
T936 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.4152095894 May 16 03:29:07 PM PDT 24 May 16 03:29:14 PM PDT 24 85131219 ps
T937 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2183744087 May 16 03:29:03 PM PDT 24 May 16 03:29:11 PM PDT 24 21802870 ps
T938 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3807472510 May 16 03:28:46 PM PDT 24 May 16 03:29:03 PM PDT 24 403311876 ps
T143 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4202754187 May 16 03:28:54 PM PDT 24 May 16 03:29:07 PM PDT 24 76570153 ps
T939 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.404491412 May 16 03:28:49 PM PDT 24 May 16 03:29:01 PM PDT 24 112241974 ps
T940 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1506121552 May 16 03:29:05 PM PDT 24 May 16 03:29:13 PM PDT 24 1110817644 ps
T212 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2401372748 May 16 03:28:43 PM PDT 24 May 16 03:28:54 PM PDT 24 27983494 ps
T941 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.13082636 May 16 03:28:37 PM PDT 24 May 16 03:28:48 PM PDT 24 2456211652 ps
T942 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1406621802 May 16 03:28:37 PM PDT 24 May 16 03:28:49 PM PDT 24 142387107 ps
T943 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1193232151 May 16 03:29:16 PM PDT 24 May 16 03:29:24 PM PDT 24 29568855 ps
T944 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1592710161 May 16 03:29:17 PM PDT 24 May 16 03:29:28 PM PDT 24 49499243 ps
T945 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3444055322 May 16 03:28:58 PM PDT 24 May 16 03:29:11 PM PDT 24 130045952 ps
T138 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.413866734 May 16 03:29:12 PM PDT 24 May 16 03:29:20 PM PDT 24 155545038 ps
T946 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.174563092 May 16 03:29:10 PM PDT 24 May 16 03:29:17 PM PDT 24 27127336 ps
T947 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1447854789 May 16 03:28:38 PM PDT 24 May 16 03:28:51 PM PDT 24 64818100 ps
T948 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2496370276 May 16 03:29:16 PM PDT 24 May 16 03:29:24 PM PDT 24 24013473 ps
T949 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1556194523 May 16 03:29:09 PM PDT 24 May 16 03:29:16 PM PDT 24 55874520 ps
T950 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1710572276 May 16 03:28:38 PM PDT 24 May 16 03:29:00 PM PDT 24 1329477196 ps
T213 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.645651695 May 16 03:28:44 PM PDT 24 May 16 03:28:56 PM PDT 24 66169466 ps
T951 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4197668479 May 16 03:28:55 PM PDT 24 May 16 03:29:09 PM PDT 24 1362322412 ps
T952 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3490822861 May 16 03:29:08 PM PDT 24 May 16 03:29:16 PM PDT 24 95929669 ps
T953 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.252908161 May 16 03:29:12 PM PDT 24 May 16 03:29:20 PM PDT 24 50638273 ps
T144 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1889862456 May 16 03:28:55 PM PDT 24 May 16 03:29:08 PM PDT 24 268146421 ps
T954 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.960706074 May 16 03:29:10 PM PDT 24 May 16 03:29:18 PM PDT 24 43445075 ps
T214 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.394743392 May 16 03:28:46 PM PDT 24 May 16 03:28:58 PM PDT 24 14417443 ps
T955 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2645911389 May 16 03:28:56 PM PDT 24 May 16 03:29:08 PM PDT 24 605631710 ps
T956 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1417270676 May 16 03:28:52 PM PDT 24 May 16 03:29:04 PM PDT 24 996991522 ps
T957 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.767835653 May 16 03:28:51 PM PDT 24 May 16 03:29:19 PM PDT 24 673428096 ps
T958 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.219452013 May 16 03:28:44 PM PDT 24 May 16 03:28:58 PM PDT 24 57110713 ps
T215 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.346588082 May 16 03:28:49 PM PDT 24 May 16 03:29:01 PM PDT 24 16015774 ps
T959 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1230868653 May 16 03:28:54 PM PDT 24 May 16 03:29:04 PM PDT 24 16349735 ps
T960 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3949039987 May 16 03:28:52 PM PDT 24 May 16 03:29:04 PM PDT 24 25382933 ps
T961 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1536279162 May 16 03:29:14 PM PDT 24 May 16 03:29:22 PM PDT 24 81233715 ps
T962 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2103362256 May 16 03:28:54 PM PDT 24 May 16 03:29:05 PM PDT 24 46167466 ps
T963 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.706361051 May 16 03:28:53 PM PDT 24 May 16 03:29:05 PM PDT 24 163871270 ps
T964 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2536970493 May 16 03:28:38 PM PDT 24 May 16 03:28:50 PM PDT 24 232284241 ps
T965 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2584680068 May 16 03:28:48 PM PDT 24 May 16 03:28:59 PM PDT 24 99895513 ps
T966 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2131063607 May 16 03:29:08 PM PDT 24 May 16 03:29:15 PM PDT 24 47276048 ps
T967 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2929084576 May 16 03:29:01 PM PDT 24 May 16 03:29:10 PM PDT 24 70470989 ps
T968 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1043407595 May 16 03:28:45 PM PDT 24 May 16 03:28:56 PM PDT 24 247217871 ps
T969 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2959565452 May 16 03:28:46 PM PDT 24 May 16 03:29:04 PM PDT 24 273656814 ps
T970 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1418153426 May 16 03:28:38 PM PDT 24 May 16 03:28:50 PM PDT 24 158065407 ps
T971 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.702384000 May 16 03:28:55 PM PDT 24 May 16 03:29:13 PM PDT 24 468100458 ps
T972 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1673025848 May 16 03:29:02 PM PDT 24 May 16 03:29:10 PM PDT 24 75325504 ps
T973 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1833442507 May 16 03:28:59 PM PDT 24 May 16 03:29:09 PM PDT 24 95167535 ps
T974 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.288126345 May 16 03:28:54 PM PDT 24 May 16 03:29:05 PM PDT 24 65081902 ps
T975 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2051167317 May 16 03:28:54 PM PDT 24 May 16 03:29:06 PM PDT 24 39704057 ps
T145 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3270477628 May 16 03:29:13 PM PDT 24 May 16 03:29:23 PM PDT 24 117566072 ps
T976 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2613881584 May 16 03:29:11 PM PDT 24 May 16 03:29:19 PM PDT 24 403089004 ps
T977 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2432255866 May 16 03:29:21 PM PDT 24 May 16 03:29:28 PM PDT 24 17057292 ps
T978 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.808740427 May 16 03:29:08 PM PDT 24 May 16 03:29:15 PM PDT 24 16197611 ps
T979 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2574313728 May 16 03:28:46 PM PDT 24 May 16 03:29:00 PM PDT 24 568098909 ps
T980 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.592631689 May 16 03:29:03 PM PDT 24 May 16 03:29:12 PM PDT 24 35419359 ps
T981 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.963580215 May 16 03:28:48 PM PDT 24 May 16 03:29:02 PM PDT 24 374759471 ps
T982 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1278115862 May 16 03:29:10 PM PDT 24 May 16 03:29:18 PM PDT 24 116839321 ps
T983 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1869810371 May 16 03:29:10 PM PDT 24 May 16 03:29:17 PM PDT 24 49021621 ps
T984 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3913878138 May 16 03:28:53 PM PDT 24 May 16 03:29:15 PM PDT 24 480764019 ps
T985 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3992768840 May 16 03:28:37 PM PDT 24 May 16 03:28:49 PM PDT 24 72061567 ps
T130 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.4137696085 May 16 03:29:12 PM PDT 24 May 16 03:29:22 PM PDT 24 413225028 ps
T986 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2824926735 May 16 03:28:43 PM PDT 24 May 16 03:28:55 PM PDT 24 63015064 ps
T132 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1911702573 May 16 03:29:09 PM PDT 24 May 16 03:29:17 PM PDT 24 81578714 ps
T987 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2562577905 May 16 03:29:11 PM PDT 24 May 16 03:29:19 PM PDT 24 48792654 ps
T988 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.342931119 May 16 03:28:45 PM PDT 24 May 16 03:29:09 PM PDT 24 571972415 ps
T989 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4008187205 May 16 03:28:42 PM PDT 24 May 16 03:28:55 PM PDT 24 363735179 ps
T990 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1083833745 May 16 03:29:11 PM PDT 24 May 16 03:29:18 PM PDT 24 18075573 ps
T991 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.27683579 May 16 03:28:43 PM PDT 24 May 16 03:28:56 PM PDT 24 502605430 ps
T992 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2602551394 May 16 03:29:11 PM PDT 24 May 16 03:29:19 PM PDT 24 79791737 ps
T993 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.725895805 May 16 03:29:02 PM PDT 24 May 16 03:29:10 PM PDT 24 81360765 ps
T994 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3404554978 May 16 03:29:09 PM PDT 24 May 16 03:29:17 PM PDT 24 28025511 ps
T995 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4048896166 May 16 03:28:55 PM PDT 24 May 16 03:29:08 PM PDT 24 69181616 ps
T996 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3643521961 May 16 03:28:52 PM PDT 24 May 16 03:29:04 PM PDT 24 28803670 ps
T131 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2153898945 May 16 03:29:12 PM PDT 24 May 16 03:29:24 PM PDT 24 847546498 ps
T997 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.674002751 May 16 03:28:37 PM PDT 24 May 16 03:28:48 PM PDT 24 37496773 ps
T998 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2468753917 May 16 03:28:45 PM PDT 24 May 16 03:28:58 PM PDT 24 512054348 ps
T999 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2444590662 May 16 03:29:10 PM PDT 24 May 16 03:29:19 PM PDT 24 151780698 ps
T1000 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.525462335 May 16 03:28:48 PM PDT 24 May 16 03:29:00 PM PDT 24 15124563 ps
T133 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1052962166 May 16 03:29:12 PM PDT 24 May 16 03:29:22 PM PDT 24 212417509 ps

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.843233041
Short name T11
Test name
Test status
Simulation time 1260239720 ps
CPU time 15.63 seconds
Started May 16 03:31:45 PM PDT 24
Finished May 16 03:32:07 PM PDT 24
Peak memory 218812 kb
Host smart-db5d3195-ab58-4e2c-85be-e66d2562c421
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843233041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.843233041
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.122854561
Short name T22
Test name
Test status
Simulation time 1045756311 ps
CPU time 51.7 seconds
Started May 16 03:31:07 PM PDT 24
Finished May 16 03:32:05 PM PDT 24
Peak memory 246124 kb
Host smart-f1d6021d-26d1-4f91-83d2-0acacc5da51f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122854561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.122854561
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3394597840
Short name T48
Test name
Test status
Simulation time 1290774873 ps
CPU time 12.14 seconds
Started May 16 03:30:47 PM PDT 24
Finished May 16 03:31:08 PM PDT 24
Peak memory 225488 kb
Host smart-e11ba534-4687-459d-aa86-f3f0a769612c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394597840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3394597840
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.1002890946
Short name T63
Test name
Test status
Simulation time 24189865814 ps
CPU time 273.33 seconds
Started May 16 03:29:31 PM PDT 24
Finished May 16 03:34:12 PM PDT 24
Peak memory 421992 kb
Host smart-53932bdc-dc39-439b-9763-f8ceaf0d9eee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1002890946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.1002890946
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2849465739
Short name T118
Test name
Test status
Simulation time 53092727 ps
CPU time 1.17 seconds
Started May 16 03:28:46 PM PDT 24
Finished May 16 03:28:57 PM PDT 24
Peak memory 217856 kb
Host smart-ea68c6f5-34ae-4e39-90a6-4ed14e9d9df7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849465739 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2849465739
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.948442615
Short name T42
Test name
Test status
Simulation time 2018887318 ps
CPU time 7.07 seconds
Started May 16 03:31:15 PM PDT 24
Finished May 16 03:31:30 PM PDT 24
Peak memory 217932 kb
Host smart-25fa214d-ad81-4370-9c79-2eac3ad8fef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948442615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.948442615
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.3376758178
Short name T51
Test name
Test status
Simulation time 244918838 ps
CPU time 39.59 seconds
Started May 16 03:29:28 PM PDT 24
Finished May 16 03:30:16 PM PDT 24
Peak memory 281936 kb
Host smart-07d1e295-6378-40fc-a74f-4d4b06a5e719
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376758178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.3376758178
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.2586472784
Short name T59
Test name
Test status
Simulation time 54468445966 ps
CPU time 259.82 seconds
Started May 16 03:30:00 PM PDT 24
Finished May 16 03:34:29 PM PDT 24
Peak memory 301628 kb
Host smart-ea365491-361c-4491-9584-6c0afd233ba0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2586472784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.2586472784
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.2658134873
Short name T10
Test name
Test status
Simulation time 291073500 ps
CPU time 4.56 seconds
Started May 16 03:30:27 PM PDT 24
Finished May 16 03:30:42 PM PDT 24
Peak memory 216888 kb
Host smart-5b63b750-56be-4034-a2c0-99fadfb1e171
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658134873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.2658134873
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.318094767
Short name T4
Test name
Test status
Simulation time 336199530 ps
CPU time 11.78 seconds
Started May 16 03:30:57 PM PDT 24
Finished May 16 03:31:16 PM PDT 24
Peak memory 217864 kb
Host smart-dd1a2d80-0245-4fcc-b8a5-6198034846c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318094767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.318094767
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3324310374
Short name T116
Test name
Test status
Simulation time 77323272 ps
CPU time 2.83 seconds
Started May 16 03:28:40 PM PDT 24
Finished May 16 03:28:53 PM PDT 24
Peak memory 222432 kb
Host smart-a8fcc7a0-4591-4bff-b234-27b6d2a75564
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324310374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3324310374
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.330848789
Short name T91
Test name
Test status
Simulation time 46957201873 ps
CPU time 334.91 seconds
Started May 16 03:31:34 PM PDT 24
Finished May 16 03:37:16 PM PDT 24
Peak memory 405032 kb
Host smart-aa55185f-f91e-4a03-b928-70746c68b397
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=330848789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.330848789
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1276039054
Short name T146
Test name
Test status
Simulation time 117195897 ps
CPU time 1.78 seconds
Started May 16 03:28:57 PM PDT 24
Finished May 16 03:29:08 PM PDT 24
Peak memory 209364 kb
Host smart-d0eb0c37-ee8b-408c-a63e-9330cac54aee
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276039054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1276039054
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1248868091
Short name T115
Test name
Test status
Simulation time 1508320115 ps
CPU time 5.07 seconds
Started May 16 03:29:13 PM PDT 24
Finished May 16 03:29:24 PM PDT 24
Peak memory 217696 kb
Host smart-dfc74b27-d3c1-46b5-a3bd-f30fa33db394
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248868091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.1248868091
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.394743392
Short name T214
Test name
Test status
Simulation time 14417443 ps
CPU time 0.97 seconds
Started May 16 03:28:46 PM PDT 24
Finished May 16 03:28:58 PM PDT 24
Peak memory 209328 kb
Host smart-3fe22ee0-a98d-48f7-a9f5-bbee17ee1950
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394743392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.394743392
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1866233045
Short name T88
Test name
Test status
Simulation time 142157689 ps
CPU time 1.2 seconds
Started May 16 03:31:34 PM PDT 24
Finished May 16 03:31:42 PM PDT 24
Peak memory 209448 kb
Host smart-552b634e-4b09-4976-a4bc-94ed9e15feb6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866233045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1866233045
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1372313670
Short name T2
Test name
Test status
Simulation time 39275712 ps
CPU time 0.97 seconds
Started May 16 03:31:32 PM PDT 24
Finished May 16 03:31:40 PM PDT 24
Peak memory 211576 kb
Host smart-54193601-0ad9-48b7-b697-40d8447e53f0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372313670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1372313670
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.1752968550
Short name T151
Test name
Test status
Simulation time 85671229032 ps
CPU time 543.21 seconds
Started May 16 03:30:36 PM PDT 24
Finished May 16 03:39:48 PM PDT 24
Peak memory 261908 kb
Host smart-1222425d-c09d-45ee-8812-93f10caee282
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1752968550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.1752968550
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1290906283
Short name T123
Test name
Test status
Simulation time 311829153 ps
CPU time 3.5 seconds
Started May 16 03:29:13 PM PDT 24
Finished May 16 03:29:23 PM PDT 24
Peak memory 217684 kb
Host smart-3a260a65-e337-43cf-99a6-cfb98f452dc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290906283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1290906283
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1526674931
Short name T15
Test name
Test status
Simulation time 434805467 ps
CPU time 15.59 seconds
Started May 16 03:31:32 PM PDT 24
Finished May 16 03:31:54 PM PDT 24
Peak memory 217888 kb
Host smart-874ca069-08fe-49c3-89ca-cbdc69bccea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526674931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1526674931
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3334918480
Short name T167
Test name
Test status
Simulation time 46869876 ps
CPU time 1.52 seconds
Started May 16 03:28:39 PM PDT 24
Finished May 16 03:28:51 PM PDT 24
Peak memory 209464 kb
Host smart-c7ce2b79-ad7c-4716-8ab1-d60c8421b46d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334918480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3334918480
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2153898945
Short name T131
Test name
Test status
Simulation time 847546498 ps
CPU time 5.87 seconds
Started May 16 03:29:12 PM PDT 24
Finished May 16 03:29:24 PM PDT 24
Peak memory 217628 kb
Host smart-df95b28d-e73d-4934-a98f-8dda837fbb1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153898945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2153898945
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.4074050004
Short name T108
Test name
Test status
Simulation time 270633260 ps
CPU time 24.99 seconds
Started May 16 03:31:18 PM PDT 24
Finished May 16 03:31:53 PM PDT 24
Peak memory 250824 kb
Host smart-4356a375-a0d1-43c0-9795-ce13ab4d846f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074050004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.4074050004
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1052962166
Short name T133
Test name
Test status
Simulation time 212417509 ps
CPU time 4.24 seconds
Started May 16 03:29:12 PM PDT 24
Finished May 16 03:29:22 PM PDT 24
Peak memory 217748 kb
Host smart-28e4a4eb-699f-43db-a18d-1e7bc2205941
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052962166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1052962166
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3072042652
Short name T142
Test name
Test status
Simulation time 72209632 ps
CPU time 2.22 seconds
Started May 16 03:29:09 PM PDT 24
Finished May 16 03:29:16 PM PDT 24
Peak memory 217608 kb
Host smart-8d203517-f511-42b8-938d-72f71eab2e9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072042652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.3072042652
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.719357646
Short name T49
Test name
Test status
Simulation time 671714579 ps
CPU time 6.1 seconds
Started May 16 03:31:33 PM PDT 24
Finished May 16 03:31:45 PM PDT 24
Peak memory 217908 kb
Host smart-1a13b70d-5991-4a82-a7d7-a35604452ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719357646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.719357646
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3162402921
Short name T140
Test name
Test status
Simulation time 501553438 ps
CPU time 4.11 seconds
Started May 16 03:28:51 PM PDT 24
Finished May 16 03:29:05 PM PDT 24
Peak memory 217652 kb
Host smart-a98ef5aa-3390-48af-9608-fbc47df5c43d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162402921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3162402921
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2815945830
Short name T136
Test name
Test status
Simulation time 145072744 ps
CPU time 2.58 seconds
Started May 16 03:28:50 PM PDT 24
Finished May 16 03:29:03 PM PDT 24
Peak memory 221832 kb
Host smart-10c9c06b-515d-4354-9d18-2ac049cf2f31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815945830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2815945830
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2809532686
Short name T228
Test name
Test status
Simulation time 11690277 ps
CPU time 0.84 seconds
Started May 16 03:29:25 PM PDT 24
Finished May 16 03:29:32 PM PDT 24
Peak memory 209224 kb
Host smart-da5ec362-508d-459c-aa19-b636c0050c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809532686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2809532686
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3132315849
Short name T226
Test name
Test status
Simulation time 29260891 ps
CPU time 0.89 seconds
Started May 16 03:29:32 PM PDT 24
Finished May 16 03:29:40 PM PDT 24
Peak memory 209440 kb
Host smart-1dbd6817-b0f8-4713-8e3b-be848a3617a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132315849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3132315849
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.4224170265
Short name T157
Test name
Test status
Simulation time 10489933 ps
CPU time 0.83 seconds
Started May 16 03:29:44 PM PDT 24
Finished May 16 03:29:52 PM PDT 24
Peak memory 209340 kb
Host smart-c7bd3cf4-a0a8-4a41-81fe-d665647a6a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224170265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.4224170265
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2863060442
Short name T229
Test name
Test status
Simulation time 17176537 ps
CPU time 0.91 seconds
Started May 16 03:29:45 PM PDT 24
Finished May 16 03:29:53 PM PDT 24
Peak memory 209376 kb
Host smart-25a1bde1-0ab3-46fe-bed9-94b769172a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863060442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2863060442
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.509284770
Short name T5
Test name
Test status
Simulation time 1649659606 ps
CPU time 3.65 seconds
Started May 16 03:29:50 PM PDT 24
Finished May 16 03:30:01 PM PDT 24
Peak memory 212960 kb
Host smart-570f37fe-aeda-4232-a091-6286eb8b0ea8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=509284770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.509284770
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1156602726
Short name T137
Test name
Test status
Simulation time 42570111 ps
CPU time 2.33 seconds
Started May 16 03:29:10 PM PDT 24
Finished May 16 03:29:18 PM PDT 24
Peak memory 222048 kb
Host smart-b04d91d0-f970-4f6d-a2f9-8d6d64bbefe9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156602726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1156602726
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.1911702573
Short name T132
Test name
Test status
Simulation time 81578714 ps
CPU time 1.97 seconds
Started May 16 03:29:09 PM PDT 24
Finished May 16 03:29:17 PM PDT 24
Peak memory 222160 kb
Host smart-346423e9-2b46-4eb9-bae4-4a2950a07ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911702573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.1911702573
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.4137696085
Short name T130
Test name
Test status
Simulation time 413225028 ps
CPU time 4.06 seconds
Started May 16 03:29:12 PM PDT 24
Finished May 16 03:29:22 PM PDT 24
Peak memory 217692 kb
Host smart-d1b4a45a-92b8-4026-b542-4a2cf9b1b29f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137696085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.4137696085
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.4202754187
Short name T143
Test name
Test status
Simulation time 76570153 ps
CPU time 2.74 seconds
Started May 16 03:28:54 PM PDT 24
Finished May 16 03:29:07 PM PDT 24
Peak memory 222320 kb
Host smart-175218ac-3c0e-4dcd-8fdd-95803d98ee93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202754187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.4202754187
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.4280646039
Short name T45
Test name
Test status
Simulation time 529677991 ps
CPU time 13.75 seconds
Started May 16 03:30:59 PM PDT 24
Finished May 16 03:31:19 PM PDT 24
Peak memory 217880 kb
Host smart-fe0acd94-8008-478f-b2e6-0f1fa5fb1f50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280646039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.4280646039
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.2664572510
Short name T46
Test name
Test status
Simulation time 495417874 ps
CPU time 8.65 seconds
Started May 16 03:29:39 PM PDT 24
Finished May 16 03:29:52 PM PDT 24
Peak memory 217776 kb
Host smart-7635f78d-9dc5-451e-85a5-55ca8648e85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664572510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2664572510
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.3653311431
Short name T27
Test name
Test status
Simulation time 483754891 ps
CPU time 5.05 seconds
Started May 16 03:30:35 PM PDT 24
Finished May 16 03:30:49 PM PDT 24
Peak memory 217788 kb
Host smart-3a21be1c-05cf-4fb4-ab09-ad219dac4783
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653311431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.3653311431
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.957417004
Short name T168
Test name
Test status
Simulation time 27151461 ps
CPU time 1.35 seconds
Started May 16 03:28:38 PM PDT 24
Finished May 16 03:28:50 PM PDT 24
Peak memory 209452 kb
Host smart-66a09b5e-9894-475e-9d49-45e97a7a3ab6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957417004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.957417004
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2984721719
Short name T216
Test name
Test status
Simulation time 157183579 ps
CPU time 2.91 seconds
Started May 16 03:28:41 PM PDT 24
Finished May 16 03:28:53 PM PDT 24
Peak memory 209460 kb
Host smart-2c81f70c-a99a-4620-bd1f-0933714fe7df
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984721719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2984721719
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1420002944
Short name T206
Test name
Test status
Simulation time 16638057 ps
CPU time 1.07 seconds
Started May 16 03:28:37 PM PDT 24
Finished May 16 03:28:49 PM PDT 24
Peak memory 209900 kb
Host smart-4bd8c1db-236c-4783-b302-7dfa6988b474
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420002944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.1420002944
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3067789184
Short name T165
Test name
Test status
Simulation time 19784067 ps
CPU time 1.01 seconds
Started May 16 03:28:46 PM PDT 24
Finished May 16 03:28:57 PM PDT 24
Peak memory 218696 kb
Host smart-98c61ba2-5e3f-4bd8-8d0a-8e0df2d2a42c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067789184 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3067789184
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2436431115
Short name T903
Test name
Test status
Simulation time 12898922 ps
CPU time 0.85 seconds
Started May 16 03:28:42 PM PDT 24
Finished May 16 03:28:53 PM PDT 24
Peak memory 209320 kb
Host smart-41c4cfa9-4bd2-44f0-9ca5-402c02508c2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436431115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2436431115
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1418153426
Short name T970
Test name
Test status
Simulation time 158065407 ps
CPU time 1.61 seconds
Started May 16 03:28:38 PM PDT 24
Finished May 16 03:28:50 PM PDT 24
Peak memory 209312 kb
Host smart-48dad1dc-7f79-4048-b5d0-af86d7f2cede
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418153426 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1418153426
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3807472510
Short name T938
Test name
Test status
Simulation time 403311876 ps
CPU time 7.19 seconds
Started May 16 03:28:46 PM PDT 24
Finished May 16 03:29:03 PM PDT 24
Peak memory 207996 kb
Host smart-9dde3900-fae0-4c84-a178-44d643f643e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807472510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3807472510
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1710572276
Short name T950
Test name
Test status
Simulation time 1329477196 ps
CPU time 12.37 seconds
Started May 16 03:28:38 PM PDT 24
Finished May 16 03:29:00 PM PDT 24
Peak memory 209316 kb
Host smart-038f0598-a2fb-4f36-93e0-8681eb57f873
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710572276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1710572276
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1447854789
Short name T947
Test name
Test status
Simulation time 64818100 ps
CPU time 2.31 seconds
Started May 16 03:28:38 PM PDT 24
Finished May 16 03:28:51 PM PDT 24
Peak memory 210816 kb
Host smart-1c435570-aefe-4a83-8105-aa32bace10f3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447854789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1447854789
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.13082636
Short name T941
Test name
Test status
Simulation time 2456211652 ps
CPU time 1.82 seconds
Started May 16 03:28:37 PM PDT 24
Finished May 16 03:28:48 PM PDT 24
Peak memory 218780 kb
Host smart-f5fbb5b7-a200-4cc6-b46c-adb9ab9fcf40
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130826
36 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.13082636
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.1406621802
Short name T942
Test name
Test status
Simulation time 142387107 ps
CPU time 2.72 seconds
Started May 16 03:28:37 PM PDT 24
Finished May 16 03:28:49 PM PDT 24
Peak memory 209276 kb
Host smart-5ae46f57-2209-4322-ab36-50f43c6d3a1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406621802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.1406621802
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3992768840
Short name T985
Test name
Test status
Simulation time 72061567 ps
CPU time 1.48 seconds
Started May 16 03:28:37 PM PDT 24
Finished May 16 03:28:49 PM PDT 24
Peak memory 217612 kb
Host smart-a567933a-934b-4524-9ae3-5b2f4d6d0699
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992768840 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3992768840
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.768745300
Short name T921
Test name
Test status
Simulation time 110040149 ps
CPU time 2.04 seconds
Started May 16 03:28:37 PM PDT 24
Finished May 16 03:28:49 PM PDT 24
Peak memory 217744 kb
Host smart-2240ba43-4f8b-438a-89a3-82759816a5d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768745300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.768745300
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3759751126
Short name T933
Test name
Test status
Simulation time 77275468 ps
CPU time 1.8 seconds
Started May 16 03:28:49 PM PDT 24
Finished May 16 03:29:01 PM PDT 24
Peak memory 209436 kb
Host smart-fdd402fc-d11a-47fe-a46e-43d0cdeb3f2d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759751126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3759751126
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2401372748
Short name T212
Test name
Test status
Simulation time 27983494 ps
CPU time 1.14 seconds
Started May 16 03:28:43 PM PDT 24
Finished May 16 03:28:54 PM PDT 24
Peak memory 218316 kb
Host smart-3f5c45d6-a432-457b-9ccd-2f38ce3b6c7e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401372748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2401372748
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1403150677
Short name T884
Test name
Test status
Simulation time 96525805 ps
CPU time 1.56 seconds
Started May 16 03:28:44 PM PDT 24
Finished May 16 03:28:56 PM PDT 24
Peak memory 217728 kb
Host smart-033a14bb-b2df-4cca-b492-d6bdf1e962d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403150677 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1403150677
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2925399295
Short name T906
Test name
Test status
Simulation time 51974582 ps
CPU time 0.91 seconds
Started May 16 03:28:45 PM PDT 24
Finished May 16 03:28:56 PM PDT 24
Peak memory 209444 kb
Host smart-612aa49c-1c40-4a70-93ac-b6f26f955a77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925399295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2925399295
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.719728976
Short name T915
Test name
Test status
Simulation time 81811392 ps
CPU time 0.99 seconds
Started May 16 03:28:46 PM PDT 24
Finished May 16 03:28:57 PM PDT 24
Peak memory 207952 kb
Host smart-65a07349-fa82-4a68-ad01-2ab350c761b6
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719728976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.719728976
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.342931119
Short name T988
Test name
Test status
Simulation time 571972415 ps
CPU time 13.84 seconds
Started May 16 03:28:45 PM PDT 24
Finished May 16 03:29:09 PM PDT 24
Peak memory 209160 kb
Host smart-80a76b5a-6188-4a77-b601-048962beae78
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342931119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.342931119
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3978791822
Short name T886
Test name
Test status
Simulation time 3884537651 ps
CPU time 15.62 seconds
Started May 16 03:28:42 PM PDT 24
Finished May 16 03:29:07 PM PDT 24
Peak memory 209404 kb
Host smart-3cf8aca7-eb87-4cca-9d63-eccbf7cf8f2d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978791822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3978791822
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2536970493
Short name T964
Test name
Test status
Simulation time 232284241 ps
CPU time 1.27 seconds
Started May 16 03:28:38 PM PDT 24
Finished May 16 03:28:50 PM PDT 24
Peak memory 210456 kb
Host smart-b9797064-fac3-4812-a422-db525469115e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536970493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2536970493
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1880619839
Short name T931
Test name
Test status
Simulation time 66758617 ps
CPU time 1.56 seconds
Started May 16 03:28:50 PM PDT 24
Finished May 16 03:29:02 PM PDT 24
Peak memory 218880 kb
Host smart-d9d3f683-92d4-432b-af9f-196315f0ee32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188061
9839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1880619839
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.674002751
Short name T997
Test name
Test status
Simulation time 37496773 ps
CPU time 1.55 seconds
Started May 16 03:28:37 PM PDT 24
Finished May 16 03:28:48 PM PDT 24
Peak memory 209380 kb
Host smart-0ca2bdc7-2529-4534-b370-5cea0e868820
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674002751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.674002751
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.4053613678
Short name T166
Test name
Test status
Simulation time 56341879 ps
CPU time 2.09 seconds
Started May 16 03:28:46 PM PDT 24
Finished May 16 03:28:59 PM PDT 24
Peak memory 217664 kb
Host smart-30647479-29a5-4c70-ba7c-05e80bd21293
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053613678 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.4053613678
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.4153510027
Short name T222
Test name
Test status
Simulation time 26984063 ps
CPU time 1.45 seconds
Started May 16 03:28:45 PM PDT 24
Finished May 16 03:28:57 PM PDT 24
Peak memory 209464 kb
Host smart-66e478e6-c8c2-4329-a579-545667c4935e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153510027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.4153510027
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2824926735
Short name T986
Test name
Test status
Simulation time 63015064 ps
CPU time 2.32 seconds
Started May 16 03:28:43 PM PDT 24
Finished May 16 03:28:55 PM PDT 24
Peak memory 217796 kb
Host smart-c089cdea-436c-4a04-a51b-9ef416a099ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824926735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2824926735
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2779419950
Short name T128
Test name
Test status
Simulation time 49784644 ps
CPU time 1.93 seconds
Started May 16 03:28:47 PM PDT 24
Finished May 16 03:29:00 PM PDT 24
Peak memory 221608 kb
Host smart-f9667c63-fb36-4c1b-8ba6-859c3c6dff71
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779419950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2779419950
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.553883744
Short name T180
Test name
Test status
Simulation time 24143169 ps
CPU time 1.56 seconds
Started May 16 03:29:12 PM PDT 24
Finished May 16 03:29:19 PM PDT 24
Peak memory 217724 kb
Host smart-6905fd3f-e4ba-45d8-b637-52d3bd1fc73a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553883744 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.553883744
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1614770945
Short name T209
Test name
Test status
Simulation time 40130780 ps
CPU time 0.94 seconds
Started May 16 03:29:10 PM PDT 24
Finished May 16 03:29:16 PM PDT 24
Peak memory 209048 kb
Host smart-9aa08b4d-d907-46f6-be9a-6315be5a2ab7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614770945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1614770945
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.252908161
Short name T953
Test name
Test status
Simulation time 50638273 ps
CPU time 1.53 seconds
Started May 16 03:29:12 PM PDT 24
Finished May 16 03:29:20 PM PDT 24
Peak memory 209528 kb
Host smart-64b90aba-b6db-42db-816b-607e6b8e8f92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252908161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.252908161
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2835558486
Short name T122
Test name
Test status
Simulation time 26497373 ps
CPU time 1.66 seconds
Started May 16 03:29:13 PM PDT 24
Finished May 16 03:29:21 PM PDT 24
Peak memory 219160 kb
Host smart-bea942f0-51b0-41c4-a751-56ec921fffd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835558486 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2835558486
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.2804746785
Short name T882
Test name
Test status
Simulation time 47624428 ps
CPU time 0.86 seconds
Started May 16 03:29:14 PM PDT 24
Finished May 16 03:29:22 PM PDT 24
Peak memory 208728 kb
Host smart-c98de0e9-62b3-4ebe-adcb-ffb6fb90de10
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804746785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.2804746785
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1175865380
Short name T217
Test name
Test status
Simulation time 48787234 ps
CPU time 1.33 seconds
Started May 16 03:29:13 PM PDT 24
Finished May 16 03:29:20 PM PDT 24
Peak memory 209484 kb
Host smart-dd54c0ed-d09f-4f5a-8576-143685d350f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175865380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1175865380
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1536279162
Short name T961
Test name
Test status
Simulation time 81233715 ps
CPU time 1.7 seconds
Started May 16 03:29:14 PM PDT 24
Finished May 16 03:29:22 PM PDT 24
Peak memory 217800 kb
Host smart-0bc2ce96-2f15-4ac3-b047-425730c5723e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536279162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1536279162
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.851200954
Short name T141
Test name
Test status
Simulation time 33655518 ps
CPU time 1.32 seconds
Started May 16 03:29:12 PM PDT 24
Finished May 16 03:29:19 PM PDT 24
Peak memory 222664 kb
Host smart-c06ea87e-a534-4601-9e7e-a6aa1f76e833
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851200954 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.851200954
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.1083833745
Short name T990
Test name
Test status
Simulation time 18075573 ps
CPU time 1.16 seconds
Started May 16 03:29:11 PM PDT 24
Finished May 16 03:29:18 PM PDT 24
Peak memory 217264 kb
Host smart-b5323b9d-cd25-4a3f-b9f2-e10d45fd9f95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083833745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.1083833745
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3326193914
Short name T930
Test name
Test status
Simulation time 36201132 ps
CPU time 1.25 seconds
Started May 16 03:29:10 PM PDT 24
Finished May 16 03:29:17 PM PDT 24
Peak memory 209460 kb
Host smart-54cca683-2447-46e8-910b-1e033ff3e444
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326193914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3326193914
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1278115862
Short name T982
Test name
Test status
Simulation time 116839321 ps
CPU time 2.16 seconds
Started May 16 03:29:10 PM PDT 24
Finished May 16 03:29:18 PM PDT 24
Peak memory 218252 kb
Host smart-2f5cafb1-b894-4f69-a356-2258bbd8c7a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278115862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1278115862
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3270477628
Short name T145
Test name
Test status
Simulation time 117566072 ps
CPU time 2.84 seconds
Started May 16 03:29:13 PM PDT 24
Finished May 16 03:29:23 PM PDT 24
Peak memory 222080 kb
Host smart-f714b5a6-bc08-4eb4-8b9d-443e2aa74307
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270477628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3270477628
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1405394806
Short name T114
Test name
Test status
Simulation time 24258045 ps
CPU time 1.14 seconds
Started May 16 03:29:08 PM PDT 24
Finished May 16 03:29:15 PM PDT 24
Peak memory 218796 kb
Host smart-287ab0a9-d7f2-4e8c-8420-f90e4f345e56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405394806 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1405394806
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1942600550
Short name T928
Test name
Test status
Simulation time 14530654 ps
CPU time 1.05 seconds
Started May 16 03:29:10 PM PDT 24
Finished May 16 03:29:17 PM PDT 24
Peak memory 209448 kb
Host smart-813fedaf-dc87-4fb3-93d1-5be455e05039
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942600550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1942600550
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3827967496
Short name T120
Test name
Test status
Simulation time 61963685 ps
CPU time 1.19 seconds
Started May 16 03:29:09 PM PDT 24
Finished May 16 03:29:16 PM PDT 24
Peak memory 209436 kb
Host smart-a0e073fe-f3b5-4d04-8255-98cb7d2bbff4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827967496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3827967496
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.410024969
Short name T909
Test name
Test status
Simulation time 63420334 ps
CPU time 2.26 seconds
Started May 16 03:29:10 PM PDT 24
Finished May 16 03:29:18 PM PDT 24
Peak memory 218324 kb
Host smart-3a125220-5104-40e8-8ca8-68fbe4be5f80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410024969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.410024969
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.882421275
Short name T111
Test name
Test status
Simulation time 776778927 ps
CPU time 3.22 seconds
Started May 16 03:29:09 PM PDT 24
Finished May 16 03:29:18 PM PDT 24
Peak memory 217664 kb
Host smart-d63ed255-87d3-4780-9228-3cd3f57d5cb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882421275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.882421275
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.3361637097
Short name T908
Test name
Test status
Simulation time 62650459 ps
CPU time 2.33 seconds
Started May 16 03:29:11 PM PDT 24
Finished May 16 03:29:19 PM PDT 24
Peak memory 217672 kb
Host smart-42e023a7-cb53-4396-bc8d-5b85183f341b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361637097 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.3361637097
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.766565596
Short name T913
Test name
Test status
Simulation time 57990359 ps
CPU time 1.1 seconds
Started May 16 03:29:12 PM PDT 24
Finished May 16 03:29:19 PM PDT 24
Peak memory 209488 kb
Host smart-636ff848-b132-46a0-a506-e449843d2770
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766565596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.766565596
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.174563092
Short name T946
Test name
Test status
Simulation time 27127336 ps
CPU time 0.99 seconds
Started May 16 03:29:10 PM PDT 24
Finished May 16 03:29:17 PM PDT 24
Peak memory 209536 kb
Host smart-992aca90-f956-45d6-bf0a-255085d2cce6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174563092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.174563092
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.4192783848
Short name T139
Test name
Test status
Simulation time 26268921 ps
CPU time 1.66 seconds
Started May 16 03:29:10 PM PDT 24
Finished May 16 03:29:17 PM PDT 24
Peak memory 217764 kb
Host smart-6ea40443-3a91-4db9-864c-45072008218b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4192783848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.4192783848
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.413866734
Short name T138
Test name
Test status
Simulation time 155545038 ps
CPU time 2.18 seconds
Started May 16 03:29:12 PM PDT 24
Finished May 16 03:29:20 PM PDT 24
Peak memory 221980 kb
Host smart-3ae196e3-7367-4fd4-89f3-873666c1dfd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413866734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.413866734
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.789759305
Short name T112
Test name
Test status
Simulation time 23801463 ps
CPU time 1.77 seconds
Started May 16 03:29:11 PM PDT 24
Finished May 16 03:29:19 PM PDT 24
Peak memory 225632 kb
Host smart-6369284f-15a8-4af8-9a36-5207a247d335
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789759305 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.789759305
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3645885744
Short name T119
Test name
Test status
Simulation time 39692992 ps
CPU time 1.03 seconds
Started May 16 03:29:08 PM PDT 24
Finished May 16 03:29:14 PM PDT 24
Peak memory 209036 kb
Host smart-01c67adb-0fbf-488e-925f-55f2103dd4d7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645885744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3645885744
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2131063607
Short name T966
Test name
Test status
Simulation time 47276048 ps
CPU time 1.32 seconds
Started May 16 03:29:08 PM PDT 24
Finished May 16 03:29:15 PM PDT 24
Peak memory 209420 kb
Host smart-02952618-e87e-444f-aef7-96b25b46aba1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131063607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2131063607
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2916151261
Short name T925
Test name
Test status
Simulation time 46158476 ps
CPU time 2.51 seconds
Started May 16 03:29:10 PM PDT 24
Finished May 16 03:29:18 PM PDT 24
Peak memory 217924 kb
Host smart-4791f91e-43b0-46a1-887c-5842f03b5563
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916151261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2916151261
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2653352862
Short name T125
Test name
Test status
Simulation time 206299068 ps
CPU time 1.42 seconds
Started May 16 03:29:12 PM PDT 24
Finished May 16 03:29:19 PM PDT 24
Peak memory 217880 kb
Host smart-3f7bbbf1-ccd6-49fb-9b34-102650416126
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653352862 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2653352862
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1556194523
Short name T949
Test name
Test status
Simulation time 55874520 ps
CPU time 0.89 seconds
Started May 16 03:29:09 PM PDT 24
Finished May 16 03:29:16 PM PDT 24
Peak memory 209500 kb
Host smart-8379660e-bdfc-48d1-9d71-6f0fa2538231
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556194523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1556194523
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3404554978
Short name T994
Test name
Test status
Simulation time 28025511 ps
CPU time 1.13 seconds
Started May 16 03:29:09 PM PDT 24
Finished May 16 03:29:17 PM PDT 24
Peak memory 209392 kb
Host smart-bf969df5-2b3e-4792-a6a4-ad92ef7dbd33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404554978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3404554978
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3771696638
Short name T920
Test name
Test status
Simulation time 286338342 ps
CPU time 2.52 seconds
Started May 16 03:29:09 PM PDT 24
Finished May 16 03:29:17 PM PDT 24
Peak memory 217748 kb
Host smart-1a92d157-c1ab-40f2-9139-3fd0240f703d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771696638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3771696638
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3190709050
Short name T916
Test name
Test status
Simulation time 27604788 ps
CPU time 1.19 seconds
Started May 16 03:29:09 PM PDT 24
Finished May 16 03:29:16 PM PDT 24
Peak memory 219300 kb
Host smart-f0c4ff4e-0bfe-4fbb-a2e0-22bee0d8acf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190709050 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3190709050
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.808740427
Short name T978
Test name
Test status
Simulation time 16197611 ps
CPU time 0.92 seconds
Started May 16 03:29:08 PM PDT 24
Finished May 16 03:29:15 PM PDT 24
Peak memory 209460 kb
Host smart-81b2f1b8-ef09-4328-8be1-7f05642deb48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808740427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.808740427
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2602551394
Short name T992
Test name
Test status
Simulation time 79791737 ps
CPU time 1.9 seconds
Started May 16 03:29:11 PM PDT 24
Finished May 16 03:29:19 PM PDT 24
Peak memory 209484 kb
Host smart-4af95f03-7131-4769-8062-f1e6fc9453bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602551394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2602551394
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.960706074
Short name T954
Test name
Test status
Simulation time 43445075 ps
CPU time 2.98 seconds
Started May 16 03:29:10 PM PDT 24
Finished May 16 03:29:18 PM PDT 24
Peak memory 218856 kb
Host smart-ee884c8b-f45d-4678-b4da-5d9285fc0186
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960706074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.960706074
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1495876140
Short name T883
Test name
Test status
Simulation time 51348974 ps
CPU time 1.29 seconds
Started May 16 03:29:17 PM PDT 24
Finished May 16 03:29:25 PM PDT 24
Peak memory 217876 kb
Host smart-48eb170d-665c-4c3b-adb6-2589a82e032b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495876140 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1495876140
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3383138483
Short name T894
Test name
Test status
Simulation time 15617836 ps
CPU time 0.91 seconds
Started May 16 03:29:19 PM PDT 24
Finished May 16 03:29:26 PM PDT 24
Peak memory 209412 kb
Host smart-e06ec4a7-685a-4392-af8d-f5afc1bd5481
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383138483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3383138483
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1193232151
Short name T943
Test name
Test status
Simulation time 29568855 ps
CPU time 1.46 seconds
Started May 16 03:29:16 PM PDT 24
Finished May 16 03:29:24 PM PDT 24
Peak memory 209492 kb
Host smart-fb89fad3-9de6-4444-a377-3ba667143c91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193232151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1193232151
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1596651827
Short name T121
Test name
Test status
Simulation time 58459551 ps
CPU time 2.01 seconds
Started May 16 03:29:08 PM PDT 24
Finished May 16 03:29:16 PM PDT 24
Peak memory 217668 kb
Host smart-90869df3-75b5-475e-950a-f69673539b40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596651827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1596651827
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2097039380
Short name T164
Test name
Test status
Simulation time 21944241 ps
CPU time 1.34 seconds
Started May 16 03:29:16 PM PDT 24
Finished May 16 03:29:24 PM PDT 24
Peak memory 217780 kb
Host smart-60b10282-64d1-4292-9a43-24341843993b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097039380 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2097039380
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2496370276
Short name T948
Test name
Test status
Simulation time 24013473 ps
CPU time 0.82 seconds
Started May 16 03:29:16 PM PDT 24
Finished May 16 03:29:24 PM PDT 24
Peak memory 208772 kb
Host smart-633792d7-e152-48ef-81e0-facd8d2b3f75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496370276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2496370276
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2432255866
Short name T977
Test name
Test status
Simulation time 17057292 ps
CPU time 1.21 seconds
Started May 16 03:29:21 PM PDT 24
Finished May 16 03:29:28 PM PDT 24
Peak memory 209472 kb
Host smart-ebba7781-3d2f-4d32-a7b8-dbf691fdbffc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432255866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2432255866
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1592710161
Short name T944
Test name
Test status
Simulation time 49499243 ps
CPU time 3.38 seconds
Started May 16 03:29:17 PM PDT 24
Finished May 16 03:29:28 PM PDT 24
Peak memory 218676 kb
Host smart-118c4df5-f228-45fa-b865-a1e1da7fb227
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592710161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1592710161
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2643538720
Short name T127
Test name
Test status
Simulation time 269599458 ps
CPU time 2.88 seconds
Started May 16 03:29:15 PM PDT 24
Finished May 16 03:29:25 PM PDT 24
Peak memory 222500 kb
Host smart-0e0fd51f-4684-440c-b0e9-4587d84a0b65
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643538720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2643538720
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.220260774
Short name T924
Test name
Test status
Simulation time 21991762 ps
CPU time 1.36 seconds
Started May 16 03:28:44 PM PDT 24
Finished May 16 03:28:56 PM PDT 24
Peak memory 209388 kb
Host smart-4cf4db52-020b-4a9b-bb51-5cdc11f06b30
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220260774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.220260774
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2421036770
Short name T923
Test name
Test status
Simulation time 531616646 ps
CPU time 1.92 seconds
Started May 16 03:28:48 PM PDT 24
Finished May 16 03:29:00 PM PDT 24
Peak memory 208828 kb
Host smart-2d95b001-151c-4ca8-bca4-64cd04781457
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421036770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2421036770
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.645651695
Short name T213
Test name
Test status
Simulation time 66169466 ps
CPU time 1.12 seconds
Started May 16 03:28:44 PM PDT 24
Finished May 16 03:28:56 PM PDT 24
Peak memory 218200 kb
Host smart-b4a7d58c-f2a6-4b42-94a9-e7543441840d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645651695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset
.645651695
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1007728555
Short name T163
Test name
Test status
Simulation time 72109206 ps
CPU time 1.11 seconds
Started May 16 03:28:48 PM PDT 24
Finished May 16 03:29:00 PM PDT 24
Peak memory 209448 kb
Host smart-e8136674-37e5-4568-bfec-6ff76faccbb7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007728555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1007728555
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.27683579
Short name T991
Test name
Test status
Simulation time 502605430 ps
CPU time 2.19 seconds
Started May 16 03:28:43 PM PDT 24
Finished May 16 03:28:56 PM PDT 24
Peak memory 209284 kb
Host smart-563aa1ec-1a7c-4278-a880-3591c23367ab
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27683579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_alert_test.27683579
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.553275270
Short name T907
Test name
Test status
Simulation time 1851779087 ps
CPU time 5.44 seconds
Started May 16 03:28:42 PM PDT 24
Finished May 16 03:28:58 PM PDT 24
Peak memory 209192 kb
Host smart-1e360471-d918-4afe-a3f2-dcab65923fcd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553275270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.553275270
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.767835653
Short name T957
Test name
Test status
Simulation time 673428096 ps
CPU time 17.56 seconds
Started May 16 03:28:51 PM PDT 24
Finished May 16 03:29:19 PM PDT 24
Peak memory 208564 kb
Host smart-f395219c-bff1-4509-8541-e40dd2aa8aaf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767835653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.767835653
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1275740715
Short name T897
Test name
Test status
Simulation time 777721494 ps
CPU time 3.55 seconds
Started May 16 03:28:49 PM PDT 24
Finished May 16 03:29:03 PM PDT 24
Peak memory 209728 kb
Host smart-8a363c1f-4e1f-4259-aba4-ff3714e92121
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275740715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1275740715
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2574313728
Short name T979
Test name
Test status
Simulation time 568098909 ps
CPU time 4.06 seconds
Started May 16 03:28:46 PM PDT 24
Finished May 16 03:29:00 PM PDT 24
Peak memory 218636 kb
Host smart-e93866df-084f-41cd-a364-20d39768cea4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257431
3728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2574313728
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.340601424
Short name T927
Test name
Test status
Simulation time 76816661 ps
CPU time 1.06 seconds
Started May 16 03:28:49 PM PDT 24
Finished May 16 03:29:00 PM PDT 24
Peak memory 209356 kb
Host smart-7fe15d1a-27f6-4fa2-b5ea-5e84fe6cdbbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340601424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.340601424
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.608418840
Short name T220
Test name
Test status
Simulation time 86789656 ps
CPU time 1.07 seconds
Started May 16 03:28:50 PM PDT 24
Finished May 16 03:29:01 PM PDT 24
Peak memory 209512 kb
Host smart-fd0270f4-75b1-403f-aa51-fc3afff3b459
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608418840 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.608418840
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1784992796
Short name T219
Test name
Test status
Simulation time 44410381 ps
CPU time 1.07 seconds
Started May 16 03:28:44 PM PDT 24
Finished May 16 03:28:56 PM PDT 24
Peak memory 209556 kb
Host smart-1a67f589-9b45-44f1-8130-6df7b0cd16ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784992796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1784992796
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.963580215
Short name T981
Test name
Test status
Simulation time 374759471 ps
CPU time 3.19 seconds
Started May 16 03:28:48 PM PDT 24
Finished May 16 03:29:02 PM PDT 24
Peak memory 217668 kb
Host smart-27bdf7f1-1877-4cbd-ba97-04b9638f7880
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963580215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.963580215
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.404491412
Short name T939
Test name
Test status
Simulation time 112241974 ps
CPU time 1.25 seconds
Started May 16 03:28:49 PM PDT 24
Finished May 16 03:29:01 PM PDT 24
Peak memory 209460 kb
Host smart-3440cd5f-6188-4bf5-b337-4f9ffe85319c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404491412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.404491412
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.1691906615
Short name T885
Test name
Test status
Simulation time 112111468 ps
CPU time 1.76 seconds
Started May 16 03:28:49 PM PDT 24
Finished May 16 03:29:01 PM PDT 24
Peak memory 208720 kb
Host smart-ac788a81-7b28-47f8-b635-e4d4f3a7ba71
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691906615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.1691906615
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1488476557
Short name T910
Test name
Test status
Simulation time 15178415 ps
CPU time 1.1 seconds
Started May 16 03:28:44 PM PDT 24
Finished May 16 03:28:56 PM PDT 24
Peak memory 209732 kb
Host smart-2c9abd8a-a4ce-4ebd-895b-c1b72b6cac6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488476557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1488476557
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.605883912
Short name T169
Test name
Test status
Simulation time 153524071 ps
CPU time 1.1 seconds
Started May 16 03:28:44 PM PDT 24
Finished May 16 03:28:56 PM PDT 24
Peak memory 218660 kb
Host smart-c45c3fe6-3b72-4c62-8006-b8441c3261d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605883912 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.605883912
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.950586271
Short name T207
Test name
Test status
Simulation time 19085479 ps
CPU time 1.16 seconds
Started May 16 03:28:42 PM PDT 24
Finished May 16 03:28:53 PM PDT 24
Peak memory 217628 kb
Host smart-4bbdd303-44e3-4953-a7b7-cec1fc1f8f5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950586271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.950586271
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2584680068
Short name T965
Test name
Test status
Simulation time 99895513 ps
CPU time 0.93 seconds
Started May 16 03:28:48 PM PDT 24
Finished May 16 03:28:59 PM PDT 24
Peak memory 209404 kb
Host smart-85c7c6d5-18cb-4e41-9560-745aa4052888
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584680068 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2584680068
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2468753917
Short name T998
Test name
Test status
Simulation time 512054348 ps
CPU time 2.97 seconds
Started May 16 03:28:45 PM PDT 24
Finished May 16 03:28:58 PM PDT 24
Peak memory 209156 kb
Host smart-89a4cfb6-96a2-47d1-9919-a8d4a5454014
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468753917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2468753917
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3290473122
Short name T888
Test name
Test status
Simulation time 1478887798 ps
CPU time 4.99 seconds
Started May 16 03:28:48 PM PDT 24
Finished May 16 03:29:03 PM PDT 24
Peak memory 209464 kb
Host smart-9278d457-af7e-45b4-96d1-17b48f52aa0a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290473122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3290473122
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1043407595
Short name T968
Test name
Test status
Simulation time 247217871 ps
CPU time 1.43 seconds
Started May 16 03:28:45 PM PDT 24
Finished May 16 03:28:56 PM PDT 24
Peak memory 210832 kb
Host smart-47cdfda9-6173-4b44-b9a0-be109b84363a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043407595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1043407595
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4008187205
Short name T989
Test name
Test status
Simulation time 363735179 ps
CPU time 3.11 seconds
Started May 16 03:28:42 PM PDT 24
Finished May 16 03:28:55 PM PDT 24
Peak memory 219496 kb
Host smart-59a44faa-04d7-4b3e-8933-ec42ecf62c43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400818
7205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4008187205
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.2437261308
Short name T898
Test name
Test status
Simulation time 263830061 ps
CPU time 3.65 seconds
Started May 16 03:28:50 PM PDT 24
Finished May 16 03:29:04 PM PDT 24
Peak memory 209392 kb
Host smart-6acdd7fb-723f-454e-8c25-ddf7fb84d9bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437261308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.2437261308
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1045527261
Short name T912
Test name
Test status
Simulation time 18008448 ps
CPU time 1.19 seconds
Started May 16 03:28:48 PM PDT 24
Finished May 16 03:29:00 PM PDT 24
Peak memory 209312 kb
Host smart-8dd3fbf0-9ccd-4294-abd9-41f0ba5a4246
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045527261 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1045527261
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2910491814
Short name T218
Test name
Test status
Simulation time 58414316 ps
CPU time 0.97 seconds
Started May 16 03:28:46 PM PDT 24
Finished May 16 03:28:57 PM PDT 24
Peak memory 209400 kb
Host smart-1e4f2e3f-efce-40b9-9075-00d13d990a5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910491814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.2910491814
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.219452013
Short name T958
Test name
Test status
Simulation time 57110713 ps
CPU time 4.11 seconds
Started May 16 03:28:44 PM PDT 24
Finished May 16 03:28:58 PM PDT 24
Peak memory 217700 kb
Host smart-c003843a-7dca-4a98-9579-e5540ba83302
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219452013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.219452013
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2321050313
Short name T135
Test name
Test status
Simulation time 170905026 ps
CPU time 3.54 seconds
Started May 16 03:28:43 PM PDT 24
Finished May 16 03:28:57 PM PDT 24
Peak memory 222632 kb
Host smart-c4e83a07-eca1-418a-a9da-31efe5f85bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321050313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2321050313
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2302520401
Short name T905
Test name
Test status
Simulation time 21748587 ps
CPU time 1.31 seconds
Started May 16 03:28:53 PM PDT 24
Finished May 16 03:29:04 PM PDT 24
Peak memory 209508 kb
Host smart-ce64dc8d-d997-401f-9843-a66a84399b3a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302520401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2302520401
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1500021794
Short name T900
Test name
Test status
Simulation time 152150239 ps
CPU time 1.76 seconds
Started May 16 03:28:55 PM PDT 24
Finished May 16 03:29:07 PM PDT 24
Peak memory 209448 kb
Host smart-053995e5-53a2-4da0-bfd6-a3eb750e91ab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500021794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1500021794
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.346588082
Short name T215
Test name
Test status
Simulation time 16015774 ps
CPU time 1.06 seconds
Started May 16 03:28:49 PM PDT 24
Finished May 16 03:29:01 PM PDT 24
Peak memory 210348 kb
Host smart-222d0e8c-bc7e-46a7-91fe-aa5ecd52b9de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346588082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.346588082
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2103362256
Short name T962
Test name
Test status
Simulation time 46167466 ps
CPU time 1.68 seconds
Started May 16 03:28:54 PM PDT 24
Finished May 16 03:29:05 PM PDT 24
Peak memory 219640 kb
Host smart-088f0c53-f8ac-46f8-b09e-be6dfde82a1c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103362256 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2103362256
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.96410167
Short name T211
Test name
Test status
Simulation time 62524709 ps
CPU time 0.96 seconds
Started May 16 03:28:54 PM PDT 24
Finished May 16 03:29:05 PM PDT 24
Peak memory 209468 kb
Host smart-61f89d14-0f3a-4bb0-b720-56bac65258aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96410167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.96410167
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2665361365
Short name T891
Test name
Test status
Simulation time 382430318 ps
CPU time 1.72 seconds
Started May 16 03:28:49 PM PDT 24
Finished May 16 03:29:01 PM PDT 24
Peak memory 208308 kb
Host smart-e7350961-edaf-4b28-91f1-3dd8f29732f2
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665361365 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2665361365
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3729068079
Short name T892
Test name
Test status
Simulation time 2615443828 ps
CPU time 6.25 seconds
Started May 16 03:28:47 PM PDT 24
Finished May 16 03:29:04 PM PDT 24
Peak memory 209352 kb
Host smart-d3435d83-20ae-40d8-abc0-00df97d19301
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729068079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3729068079
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1915463221
Short name T890
Test name
Test status
Simulation time 3876272257 ps
CPU time 21.56 seconds
Started May 16 03:28:49 PM PDT 24
Finished May 16 03:29:21 PM PDT 24
Peak memory 208648 kb
Host smart-ff5a48a2-a795-4182-85f6-7b2d3453e58a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915463221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1915463221
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.2577795101
Short name T901
Test name
Test status
Simulation time 93884032 ps
CPU time 1.8 seconds
Started May 16 03:28:45 PM PDT 24
Finished May 16 03:28:57 PM PDT 24
Peak memory 211000 kb
Host smart-7b828673-4d4a-44c7-8961-af659109e6ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577795101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.2577795101
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2959565452
Short name T969
Test name
Test status
Simulation time 273656814 ps
CPU time 7.03 seconds
Started May 16 03:28:46 PM PDT 24
Finished May 16 03:29:04 PM PDT 24
Peak memory 217916 kb
Host smart-e8b828a7-0314-48e4-94d5-2a72754746c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295956
5452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2959565452
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1666536350
Short name T889
Test name
Test status
Simulation time 74337169 ps
CPU time 2.43 seconds
Started May 16 03:28:48 PM PDT 24
Finished May 16 03:29:01 PM PDT 24
Peak memory 209376 kb
Host smart-574b8d7c-99f4-4223-993c-d3b5a3094299
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666536350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1666536350
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.525462335
Short name T1000
Test name
Test status
Simulation time 15124563 ps
CPU time 1 seconds
Started May 16 03:28:48 PM PDT 24
Finished May 16 03:29:00 PM PDT 24
Peak memory 209352 kb
Host smart-bdfcf182-1b6e-4611-82d5-c613565d6e6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525462335 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.525462335
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3949039987
Short name T960
Test name
Test status
Simulation time 25382933 ps
CPU time 1.15 seconds
Started May 16 03:28:52 PM PDT 24
Finished May 16 03:29:04 PM PDT 24
Peak memory 209428 kb
Host smart-7f8d10ba-273d-44a9-a10c-3b90e3e683a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949039987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3949039987
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.374188806
Short name T110
Test name
Test status
Simulation time 96355380 ps
CPU time 2.04 seconds
Started May 16 03:28:48 PM PDT 24
Finished May 16 03:29:00 PM PDT 24
Peak memory 218932 kb
Host smart-63def9e1-04a0-447c-a606-d02434d108d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374188806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.374188806
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.288126345
Short name T974
Test name
Test status
Simulation time 65081902 ps
CPU time 1.53 seconds
Started May 16 03:28:54 PM PDT 24
Finished May 16 03:29:05 PM PDT 24
Peak memory 219496 kb
Host smart-8b50326d-2340-476a-b13f-eb01cf045ce9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288126345 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.288126345
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1230868653
Short name T959
Test name
Test status
Simulation time 16349735 ps
CPU time 0.92 seconds
Started May 16 03:28:54 PM PDT 24
Finished May 16 03:29:04 PM PDT 24
Peak memory 209120 kb
Host smart-26fd3a15-0060-4b5d-a2f7-bac6354c4e48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230868653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.1230868653
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1367274619
Short name T918
Test name
Test status
Simulation time 41322702 ps
CPU time 1.73 seconds
Started May 16 03:28:54 PM PDT 24
Finished May 16 03:29:05 PM PDT 24
Peak memory 209228 kb
Host smart-d49e90b6-d0ff-4e54-a1bb-10b266b519c8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367274619 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1367274619
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4197668479
Short name T951
Test name
Test status
Simulation time 1362322412 ps
CPU time 3.76 seconds
Started May 16 03:28:55 PM PDT 24
Finished May 16 03:29:09 PM PDT 24
Peak memory 209176 kb
Host smart-da3e32d3-1376-4229-8e94-9b10f0f20d87
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197668479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.4197668479
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.70041937
Short name T917
Test name
Test status
Simulation time 6294959851 ps
CPU time 18.77 seconds
Started May 16 03:28:52 PM PDT 24
Finished May 16 03:29:21 PM PDT 24
Peak memory 209440 kb
Host smart-a704789e-437b-4ede-b5ff-fe2127489465
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70041937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.70041937
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3171699603
Short name T887
Test name
Test status
Simulation time 145511328 ps
CPU time 1.99 seconds
Started May 16 03:28:54 PM PDT 24
Finished May 16 03:29:06 PM PDT 24
Peak memory 210956 kb
Host smart-2ea7bd19-9d4f-4f9c-ae5c-49e8ded0352b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171699603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3171699603
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3444055322
Short name T945
Test name
Test status
Simulation time 130045952 ps
CPU time 3.92 seconds
Started May 16 03:28:58 PM PDT 24
Finished May 16 03:29:11 PM PDT 24
Peak memory 217724 kb
Host smart-9eb0fed5-1362-488c-b3ae-a2f712509875
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344405
5322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3444055322
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3702033129
Short name T926
Test name
Test status
Simulation time 248865219 ps
CPU time 1.45 seconds
Started May 16 03:28:52 PM PDT 24
Finished May 16 03:29:04 PM PDT 24
Peak memory 211696 kb
Host smart-c8a98992-9e4d-42a6-bfe3-fe87be218713
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702033129 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3702033129
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2963713712
Short name T221
Test name
Test status
Simulation time 16674591 ps
CPU time 1.21 seconds
Started May 16 03:28:53 PM PDT 24
Finished May 16 03:29:05 PM PDT 24
Peak memory 209448 kb
Host smart-4d0a15c2-dbcf-4a9f-b247-235822c13f5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963713712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.2963713712
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.427003519
Short name T914
Test name
Test status
Simulation time 28951675 ps
CPU time 2.12 seconds
Started May 16 03:28:53 PM PDT 24
Finished May 16 03:29:06 PM PDT 24
Peak memory 217796 kb
Host smart-a20e8f7f-1592-434a-a293-91af037213cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427003519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.427003519
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1889862456
Short name T144
Test name
Test status
Simulation time 268146421 ps
CPU time 2.73 seconds
Started May 16 03:28:55 PM PDT 24
Finished May 16 03:29:08 PM PDT 24
Peak memory 217708 kb
Host smart-8d98ba05-2ded-441e-9635-70fd4d3606fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889862456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1889862456
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2781722434
Short name T929
Test name
Test status
Simulation time 90278717 ps
CPU time 1.47 seconds
Started May 16 03:28:54 PM PDT 24
Finished May 16 03:29:06 PM PDT 24
Peak memory 217676 kb
Host smart-ee994256-fa1a-47f2-a5fe-28f1d5d49852
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781722434 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2781722434
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.748211897
Short name T208
Test name
Test status
Simulation time 204555860 ps
CPU time 0.86 seconds
Started May 16 03:28:55 PM PDT 24
Finished May 16 03:29:06 PM PDT 24
Peak memory 209320 kb
Host smart-f8f94821-2a22-4586-b0b6-9b3462abf885
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748211897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.748211897
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.4141118450
Short name T919
Test name
Test status
Simulation time 53415824 ps
CPU time 1.22 seconds
Started May 16 03:28:51 PM PDT 24
Finished May 16 03:29:03 PM PDT 24
Peak memory 209292 kb
Host smart-8217faf7-973c-4d05-825b-4b5c6f23813c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141118450 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.4141118450
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.702384000
Short name T971
Test name
Test status
Simulation time 468100458 ps
CPU time 7.65 seconds
Started May 16 03:28:55 PM PDT 24
Finished May 16 03:29:13 PM PDT 24
Peak memory 209084 kb
Host smart-e8b1a7e1-7593-4865-9e12-0ebf8d757a4c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702384000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.702384000
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3913878138
Short name T984
Test name
Test status
Simulation time 480764019 ps
CPU time 11.27 seconds
Started May 16 03:28:53 PM PDT 24
Finished May 16 03:29:15 PM PDT 24
Peak memory 208584 kb
Host smart-2beb94fa-5b9e-48ce-be2b-9096eb49295d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913878138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3913878138
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1417270676
Short name T956
Test name
Test status
Simulation time 996991522 ps
CPU time 1.57 seconds
Started May 16 03:28:52 PM PDT 24
Finished May 16 03:29:04 PM PDT 24
Peak memory 210744 kb
Host smart-45af6b8a-6e2d-4dc7-a62f-89d728829d0d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417270676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1417270676
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4066121794
Short name T129
Test name
Test status
Simulation time 115113300 ps
CPU time 2.39 seconds
Started May 16 03:28:56 PM PDT 24
Finished May 16 03:29:09 PM PDT 24
Peak memory 218756 kb
Host smart-6e76e1cc-91c0-4783-acdc-8ba8cc3be8b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406612
1794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4066121794
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.338496494
Short name T148
Test name
Test status
Simulation time 208488306 ps
CPU time 1.94 seconds
Started May 16 03:28:59 PM PDT 24
Finished May 16 03:29:09 PM PDT 24
Peak memory 209388 kb
Host smart-70647256-3e70-4c1c-a892-ce3d27fa06ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338496494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.338496494
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1176915598
Short name T922
Test name
Test status
Simulation time 19699204 ps
CPU time 1.51 seconds
Started May 16 03:28:52 PM PDT 24
Finished May 16 03:29:04 PM PDT 24
Peak memory 211468 kb
Host smart-19de2534-70ae-45a6-9795-51f5cbff637b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176915598 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1176915598
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.245674385
Short name T223
Test name
Test status
Simulation time 15430442 ps
CPU time 1 seconds
Started May 16 03:28:52 PM PDT 24
Finished May 16 03:29:03 PM PDT 24
Peak memory 209420 kb
Host smart-55d9ba93-0724-4f73-b387-d3d0af9d80fd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245674385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.245674385
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.3643521961
Short name T996
Test name
Test status
Simulation time 28803670 ps
CPU time 1.84 seconds
Started May 16 03:28:52 PM PDT 24
Finished May 16 03:29:04 PM PDT 24
Peak memory 217856 kb
Host smart-b0b58026-78f3-4eb2-913f-caa232f201e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643521961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.3643521961
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.592631689
Short name T980
Test name
Test status
Simulation time 35419359 ps
CPU time 1.92 seconds
Started May 16 03:29:03 PM PDT 24
Finished May 16 03:29:12 PM PDT 24
Peak memory 217704 kb
Host smart-188a1327-5725-4915-815b-466cec3a965d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592631689 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.592631689
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.29050474
Short name T899
Test name
Test status
Simulation time 27436123 ps
CPU time 1 seconds
Started May 16 03:29:01 PM PDT 24
Finished May 16 03:29:10 PM PDT 24
Peak memory 209068 kb
Host smart-ec12fd8f-9ff3-4684-b892-c32b5c6f108b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29050474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.29050474
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1833442507
Short name T973
Test name
Test status
Simulation time 95167535 ps
CPU time 1.51 seconds
Started May 16 03:28:59 PM PDT 24
Finished May 16 03:29:09 PM PDT 24
Peak memory 209300 kb
Host smart-467dc379-64e2-411d-8470-50dc12015153
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833442507 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1833442507
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3055894985
Short name T904
Test name
Test status
Simulation time 1344613375 ps
CPU time 6.84 seconds
Started May 16 03:28:53 PM PDT 24
Finished May 16 03:29:10 PM PDT 24
Peak memory 209112 kb
Host smart-6a352b58-e7d0-4eb2-9dc5-63c577b537a6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055894985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.3055894985
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3192800744
Short name T895
Test name
Test status
Simulation time 1473855923 ps
CPU time 34.27 seconds
Started May 16 03:28:54 PM PDT 24
Finished May 16 03:29:39 PM PDT 24
Peak memory 208584 kb
Host smart-60d736d5-08f1-47c1-af1d-1ea05a4de2ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192800744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3192800744
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.706361051
Short name T963
Test name
Test status
Simulation time 163871270 ps
CPU time 1.22 seconds
Started May 16 03:28:53 PM PDT 24
Finished May 16 03:29:05 PM PDT 24
Peak memory 210756 kb
Host smart-9b8a9632-81a8-4623-9be9-04fa2877effd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706361051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.706361051
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2645911389
Short name T955
Test name
Test status
Simulation time 605631710 ps
CPU time 2.24 seconds
Started May 16 03:28:56 PM PDT 24
Finished May 16 03:29:08 PM PDT 24
Peak memory 222060 kb
Host smart-ae6834e4-6ca5-4f50-95b5-7e70de193051
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264591
1389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2645911389
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1057042769
Short name T911
Test name
Test status
Simulation time 41411932 ps
CPU time 1.74 seconds
Started May 16 03:28:54 PM PDT 24
Finished May 16 03:29:06 PM PDT 24
Peak memory 209368 kb
Host smart-54186090-97e1-4a36-b7a3-d57c97522ecf
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057042769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.1057042769
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2051167317
Short name T975
Test name
Test status
Simulation time 39704057 ps
CPU time 1.54 seconds
Started May 16 03:28:54 PM PDT 24
Finished May 16 03:29:06 PM PDT 24
Peak memory 217648 kb
Host smart-1d5cc9a3-d930-4a87-9736-d117637c44f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051167317 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2051167317
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2183744087
Short name T937
Test name
Test status
Simulation time 21802870 ps
CPU time 1.33 seconds
Started May 16 03:29:03 PM PDT 24
Finished May 16 03:29:11 PM PDT 24
Peak memory 217688 kb
Host smart-39e82273-174d-4115-9637-2e1a0b2a8ddc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183744087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.2183744087
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.4048896166
Short name T995
Test name
Test status
Simulation time 69181616 ps
CPU time 2.66 seconds
Started May 16 03:28:55 PM PDT 24
Finished May 16 03:29:08 PM PDT 24
Peak memory 217732 kb
Host smart-eeb634e4-d0aa-460a-8e93-63496a3c1c60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048896166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.4048896166
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3490822861
Short name T952
Test name
Test status
Simulation time 95929669 ps
CPU time 1.51 seconds
Started May 16 03:29:08 PM PDT 24
Finished May 16 03:29:16 PM PDT 24
Peak memory 217748 kb
Host smart-4a3dea23-1c92-4431-ace1-e8ab952efd58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490822861 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3490822861
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2676612747
Short name T210
Test name
Test status
Simulation time 28055047 ps
CPU time 0.89 seconds
Started May 16 03:29:01 PM PDT 24
Finished May 16 03:29:09 PM PDT 24
Peak memory 208920 kb
Host smart-d2ddc6b3-5e17-4c89-b084-c608dd9c2470
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676612747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2676612747
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2895391504
Short name T896
Test name
Test status
Simulation time 65953185 ps
CPU time 1.56 seconds
Started May 16 03:29:02 PM PDT 24
Finished May 16 03:29:10 PM PDT 24
Peak memory 209292 kb
Host smart-6895288a-ae0e-42d2-b1ee-803fab9becab
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895391504 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2895391504
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.2850681006
Short name T147
Test name
Test status
Simulation time 220355301 ps
CPU time 3.07 seconds
Started May 16 03:29:02 PM PDT 24
Finished May 16 03:29:12 PM PDT 24
Peak memory 209200 kb
Host smart-05fc4f4b-e3f6-4b0d-8fb9-d04bb00d21a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850681006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.2850681006
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.359554695
Short name T934
Test name
Test status
Simulation time 3644040501 ps
CPU time 13.75 seconds
Started May 16 03:29:04 PM PDT 24
Finished May 16 03:29:24 PM PDT 24
Peak memory 209412 kb
Host smart-43e8febb-0d97-47d2-8f8f-d5cec592713c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359554695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.359554695
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.635719023
Short name T902
Test name
Test status
Simulation time 587247140 ps
CPU time 4.58 seconds
Started May 16 03:29:11 PM PDT 24
Finished May 16 03:29:21 PM PDT 24
Peak memory 210928 kb
Host smart-bad7de43-6bff-412e-ba16-ab33dd4420d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635719023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.635719023
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3549694813
Short name T935
Test name
Test status
Simulation time 605168296 ps
CPU time 4.37 seconds
Started May 16 03:29:01 PM PDT 24
Finished May 16 03:29:13 PM PDT 24
Peak memory 218448 kb
Host smart-2d9d8986-f2e0-4179-ba6b-86f3cf5687de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354969
4813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3549694813
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.2929084576
Short name T967
Test name
Test status
Simulation time 70470989 ps
CPU time 1.41 seconds
Started May 16 03:29:01 PM PDT 24
Finished May 16 03:29:10 PM PDT 24
Peak memory 208528 kb
Host smart-5ba315f1-dbc1-4743-8941-635bf1807adf
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929084576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.2929084576
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.725895805
Short name T993
Test name
Test status
Simulation time 81360765 ps
CPU time 1.41 seconds
Started May 16 03:29:02 PM PDT 24
Finished May 16 03:29:10 PM PDT 24
Peak memory 211476 kb
Host smart-bef1b1a9-6de6-4611-ac21-d97c82b8db61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725895805 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.725895805
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1673025848
Short name T972
Test name
Test status
Simulation time 75325504 ps
CPU time 1.4 seconds
Started May 16 03:29:02 PM PDT 24
Finished May 16 03:29:10 PM PDT 24
Peak memory 209444 kb
Host smart-68871fb4-5bc9-4fb9-bd9d-2e54fa360e30
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673025848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1673025848
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2611148196
Short name T134
Test name
Test status
Simulation time 33503604 ps
CPU time 2.5 seconds
Started May 16 03:29:03 PM PDT 24
Finished May 16 03:29:12 PM PDT 24
Peak memory 217896 kb
Host smart-e6d25cfb-0d25-40fb-9328-5d95c835c495
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611148196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.2611148196
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2628775969
Short name T124
Test name
Test status
Simulation time 83465094 ps
CPU time 2.39 seconds
Started May 16 03:29:05 PM PDT 24
Finished May 16 03:29:13 PM PDT 24
Peak memory 221764 kb
Host smart-fc3330d8-5d72-4bf5-b070-15f6fb6ed6ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628775969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.2628775969
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3155391786
Short name T181
Test name
Test status
Simulation time 84065819 ps
CPU time 1.47 seconds
Started May 16 03:29:10 PM PDT 24
Finished May 16 03:29:17 PM PDT 24
Peak memory 220036 kb
Host smart-46c04da2-4fa1-4994-bf9b-000b91be680a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155391786 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3155391786
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.1869810371
Short name T983
Test name
Test status
Simulation time 49021621 ps
CPU time 0.95 seconds
Started May 16 03:29:10 PM PDT 24
Finished May 16 03:29:17 PM PDT 24
Peak memory 209452 kb
Host smart-39f43a62-48f4-4955-b834-4a173df65d07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869810371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.1869810371
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1821883075
Short name T893
Test name
Test status
Simulation time 161620656 ps
CPU time 1.23 seconds
Started May 16 03:29:10 PM PDT 24
Finished May 16 03:29:17 PM PDT 24
Peak memory 208032 kb
Host smart-6c1f1e28-51e0-471f-9a43-cfd24d676d30
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821883075 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.1821883075
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.2613881584
Short name T976
Test name
Test status
Simulation time 403089004 ps
CPU time 2.93 seconds
Started May 16 03:29:11 PM PDT 24
Finished May 16 03:29:19 PM PDT 24
Peak memory 209152 kb
Host smart-472de1a6-baf4-424c-9b6e-7cd66ccb7925
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613881584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.2613881584
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1187061978
Short name T149
Test name
Test status
Simulation time 4856299652 ps
CPU time 7.92 seconds
Started May 16 03:29:08 PM PDT 24
Finished May 16 03:29:20 PM PDT 24
Peak memory 208656 kb
Host smart-105348eb-4a39-4ecc-a1e3-536c46ce804b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187061978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1187061978
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1506121552
Short name T940
Test name
Test status
Simulation time 1110817644 ps
CPU time 2.29 seconds
Started May 16 03:29:05 PM PDT 24
Finished May 16 03:29:13 PM PDT 24
Peak memory 211096 kb
Host smart-cea5c74e-45e4-4e5b-b49b-45bf1e99c22a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506121552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1506121552
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2321716696
Short name T126
Test name
Test status
Simulation time 60512792 ps
CPU time 2.12 seconds
Started May 16 03:29:10 PM PDT 24
Finished May 16 03:29:18 PM PDT 24
Peak memory 217764 kb
Host smart-eec38d99-b3f3-408e-b11d-5e306d78a537
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232171
6696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2321716696
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.4152095894
Short name T936
Test name
Test status
Simulation time 85131219 ps
CPU time 1.46 seconds
Started May 16 03:29:07 PM PDT 24
Finished May 16 03:29:14 PM PDT 24
Peak memory 209308 kb
Host smart-652bf7b4-8c09-433e-bf80-0d2b6f504dbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152095894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.4152095894
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3822629703
Short name T932
Test name
Test status
Simulation time 17576626 ps
CPU time 1.25 seconds
Started May 16 03:29:12 PM PDT 24
Finished May 16 03:29:19 PM PDT 24
Peak memory 209516 kb
Host smart-926939a3-2fca-4610-b447-e8439a30d1ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822629703 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3822629703
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2562577905
Short name T987
Test name
Test status
Simulation time 48792654 ps
CPU time 1.93 seconds
Started May 16 03:29:11 PM PDT 24
Finished May 16 03:29:19 PM PDT 24
Peak memory 209496 kb
Host smart-9d69e958-b8ba-4630-ace3-eb5a82a8876f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562577905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.2562577905
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2444590662
Short name T999
Test name
Test status
Simulation time 151780698 ps
CPU time 2.99 seconds
Started May 16 03:29:10 PM PDT 24
Finished May 16 03:29:19 PM PDT 24
Peak memory 218792 kb
Host smart-3982409e-b2de-4b1a-84b7-985deaffd8d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2444590662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2444590662
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1819874116
Short name T117
Test name
Test status
Simulation time 57876577 ps
CPU time 2.64 seconds
Started May 16 03:29:11 PM PDT 24
Finished May 16 03:29:20 PM PDT 24
Peak memory 217736 kb
Host smart-6fe232f1-b6cb-4ae5-9c01-3fb25e3178ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819874116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1819874116
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1970309355
Short name T90
Test name
Test status
Simulation time 19033102 ps
CPU time 1.18 seconds
Started May 16 03:29:25 PM PDT 24
Finished May 16 03:29:31 PM PDT 24
Peak memory 209408 kb
Host smart-ca0dc8ee-b0c4-49ae-8019-d6bb0ccd4a84
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970309355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1970309355
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.503994631
Short name T411
Test name
Test status
Simulation time 13678011 ps
CPU time 0.94 seconds
Started May 16 03:29:18 PM PDT 24
Finished May 16 03:29:26 PM PDT 24
Peak memory 209432 kb
Host smart-d2936ec1-f700-499a-92bc-b0d7da2e4aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503994631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.503994631
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1125553799
Short name T358
Test name
Test status
Simulation time 241469519 ps
CPU time 10.95 seconds
Started May 16 03:29:15 PM PDT 24
Finished May 16 03:29:33 PM PDT 24
Peak memory 217912 kb
Host smart-ffcc24ae-de8d-4581-92e2-7b09cbb876b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125553799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1125553799
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3775846094
Short name T474
Test name
Test status
Simulation time 703690966 ps
CPU time 9.28 seconds
Started May 16 03:29:17 PM PDT 24
Finished May 16 03:29:33 PM PDT 24
Peak memory 209468 kb
Host smart-ef0039bf-98f8-4828-ac6d-fddee3a206a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775846094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3775846094
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2245507833
Short name T509
Test name
Test status
Simulation time 6489117249 ps
CPU time 22.7 seconds
Started May 16 03:29:18 PM PDT 24
Finished May 16 03:29:48 PM PDT 24
Peak memory 218800 kb
Host smart-348048ec-5292-409d-9353-e809b927550f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245507833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2245507833
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.2289926412
Short name T205
Test name
Test status
Simulation time 186392068 ps
CPU time 2.86 seconds
Started May 16 03:29:19 PM PDT 24
Finished May 16 03:29:28 PM PDT 24
Peak memory 217096 kb
Host smart-41705f38-2246-41ed-b26a-a7e166ef74ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289926412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.2
289926412
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.1303693446
Short name T327
Test name
Test status
Simulation time 1919647444 ps
CPU time 10.35 seconds
Started May 16 03:29:17 PM PDT 24
Finished May 16 03:29:34 PM PDT 24
Peak memory 217836 kb
Host smart-f10a9c04-2026-4d8a-9b18-55b4966c433f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303693446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.1303693446
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.109708830
Short name T72
Test name
Test status
Simulation time 7615005861 ps
CPU time 16.71 seconds
Started May 16 03:29:33 PM PDT 24
Finished May 16 03:29:57 PM PDT 24
Peak memory 213656 kb
Host smart-7c7b1be7-26f3-4cb2-a5cb-ba6197daa194
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109708830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_regwen_during_op.109708830
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.2264387191
Short name T405
Test name
Test status
Simulation time 1626938113 ps
CPU time 2.8 seconds
Started May 16 03:29:17 PM PDT 24
Finished May 16 03:29:27 PM PDT 24
Peak memory 212872 kb
Host smart-ed1a53fe-4e98-4b1a-8f91-826256fa4fb1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264387191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
2264387191
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1813887687
Short name T321
Test name
Test status
Simulation time 2365042485 ps
CPU time 48.29 seconds
Started May 16 03:29:17 PM PDT 24
Finished May 16 03:30:12 PM PDT 24
Peak memory 252540 kb
Host smart-f08c927d-422b-435b-862d-afbd1843c42a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813887687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1813887687
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.983666959
Short name T441
Test name
Test status
Simulation time 1025145845 ps
CPU time 10.05 seconds
Started May 16 03:29:16 PM PDT 24
Finished May 16 03:29:33 PM PDT 24
Peak memory 226192 kb
Host smart-b9a0c537-154c-470e-8d08-0802f0baa5cc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983666959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.983666959
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.594394012
Short name T711
Test name
Test status
Simulation time 168766804 ps
CPU time 2.2 seconds
Started May 16 03:29:17 PM PDT 24
Finished May 16 03:29:26 PM PDT 24
Peak memory 217792 kb
Host smart-e7a585bb-c698-4b59-993d-f1d03ce30e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594394012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.594394012
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3781824938
Short name T203
Test name
Test status
Simulation time 1410976867 ps
CPU time 22.92 seconds
Started May 16 03:29:19 PM PDT 24
Finished May 16 03:29:48 PM PDT 24
Peak memory 217632 kb
Host smart-63908d56-ead8-4c63-a296-ac6a50ab4c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781824938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3781824938
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.4271250230
Short name T102
Test name
Test status
Simulation time 228890287 ps
CPU time 37.39 seconds
Started May 16 03:29:24 PM PDT 24
Finished May 16 03:30:07 PM PDT 24
Peak memory 281600 kb
Host smart-a9dacde5-586a-4372-af97-1cf80b353304
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271250230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.4271250230
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3879395853
Short name T871
Test name
Test status
Simulation time 625923059 ps
CPU time 10.44 seconds
Started May 16 03:29:27 PM PDT 24
Finished May 16 03:29:44 PM PDT 24
Peak memory 225988 kb
Host smart-dd19b4d2-9616-4223-b34d-66c5288fbde0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879395853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3879395853
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.540188237
Short name T524
Test name
Test status
Simulation time 611680868 ps
CPU time 12.61 seconds
Started May 16 03:29:24 PM PDT 24
Finished May 16 03:29:42 PM PDT 24
Peak memory 217880 kb
Host smart-4d299681-80c2-425c-b53c-aa349e345bd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540188237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_dig
est.540188237
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2616023335
Short name T630
Test name
Test status
Simulation time 269089616 ps
CPU time 11.07 seconds
Started May 16 03:29:24 PM PDT 24
Finished May 16 03:29:41 PM PDT 24
Peak memory 217788 kb
Host smart-8229e2da-c164-41dc-a279-dc414133ec46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616023335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
616023335
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3660881408
Short name T430
Test name
Test status
Simulation time 260690717 ps
CPU time 10.28 seconds
Started May 16 03:29:19 PM PDT 24
Finished May 16 03:29:36 PM PDT 24
Peak memory 217984 kb
Host smart-f58bb5af-1a77-40c3-95ec-761ddcf47282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660881408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3660881408
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2920115235
Short name T254
Test name
Test status
Simulation time 251932887 ps
CPU time 3.19 seconds
Started May 16 03:29:16 PM PDT 24
Finished May 16 03:29:26 PM PDT 24
Peak memory 217720 kb
Host smart-60821481-3d86-4442-b5eb-8848ccdceb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920115235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2920115235
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2025217026
Short name T692
Test name
Test status
Simulation time 265284067 ps
CPU time 29.53 seconds
Started May 16 03:29:16 PM PDT 24
Finished May 16 03:29:53 PM PDT 24
Peak memory 250876 kb
Host smart-3f64e950-fc63-486f-924c-9b1204e79d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025217026 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2025217026
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3689089987
Short name T232
Test name
Test status
Simulation time 200669930 ps
CPU time 3.19 seconds
Started May 16 03:29:19 PM PDT 24
Finished May 16 03:29:29 PM PDT 24
Peak memory 222240 kb
Host smart-73aff1e5-1dd7-43c7-b65d-2b517cc9d053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689089987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3689089987
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.1216662424
Short name T436
Test name
Test status
Simulation time 3094556433 ps
CPU time 78.98 seconds
Started May 16 03:29:26 PM PDT 24
Finished May 16 03:30:51 PM PDT 24
Peak memory 250948 kb
Host smart-20788e61-5d28-49f7-86e5-c62180c0d1bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216662424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.1216662424
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3943471320
Short name T39
Test name
Test status
Simulation time 15404885 ps
CPU time 0.92 seconds
Started May 16 03:29:18 PM PDT 24
Finished May 16 03:29:26 PM PDT 24
Peak memory 211472 kb
Host smart-870fd4cd-147d-4e6b-a6d1-295e337e93e8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943471320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3943471320
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2066361073
Short name T764
Test name
Test status
Simulation time 26841114 ps
CPU time 1.02 seconds
Started May 16 03:29:33 PM PDT 24
Finished May 16 03:29:41 PM PDT 24
Peak memory 209420 kb
Host smart-d871dd83-3081-44f9-8c53-25fd8f1aef97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066361073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2066361073
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3929595409
Short name T757
Test name
Test status
Simulation time 1037062067 ps
CPU time 17.58 seconds
Started May 16 03:29:22 PM PDT 24
Finished May 16 03:29:45 PM PDT 24
Peak memory 217800 kb
Host smart-03773810-1f48-4b4a-afd5-77f4260647ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929595409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3929595409
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2648394764
Short name T386
Test name
Test status
Simulation time 308059011 ps
CPU time 2.78 seconds
Started May 16 03:29:22 PM PDT 24
Finished May 16 03:29:31 PM PDT 24
Peak memory 209400 kb
Host smart-4f91949e-d309-46f4-a83f-9644542ece69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648394764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2648394764
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.4074648330
Short name T469
Test name
Test status
Simulation time 3980236596 ps
CPU time 60.95 seconds
Started May 16 03:29:25 PM PDT 24
Finished May 16 03:30:32 PM PDT 24
Peak memory 218832 kb
Host smart-1e3f7e92-04c1-45a4-b062-9e9a98c0c04c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074648330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.4074648330
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3137702268
Short name T840
Test name
Test status
Simulation time 564773557 ps
CPU time 13.81 seconds
Started May 16 03:29:25 PM PDT 24
Finished May 16 03:29:45 PM PDT 24
Peak memory 217148 kb
Host smart-d0ae206b-282e-46e6-8db3-d45b576abcfd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137702268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3
137702268
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.851675524
Short name T258
Test name
Test status
Simulation time 2059429509 ps
CPU time 10 seconds
Started May 16 03:29:33 PM PDT 24
Finished May 16 03:29:50 PM PDT 24
Peak memory 217772 kb
Host smart-39a262b6-09c0-4736-88d8-01fd102b0f16
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851675524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.851675524
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2857714376
Short name T785
Test name
Test status
Simulation time 3227822506 ps
CPU time 34.47 seconds
Started May 16 03:29:27 PM PDT 24
Finished May 16 03:30:08 PM PDT 24
Peak memory 213692 kb
Host smart-ec6bee41-5078-467c-8812-814d93d61f94
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857714376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2857714376
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2751617935
Short name T73
Test name
Test status
Simulation time 1083627397 ps
CPU time 3.74 seconds
Started May 16 03:29:23 PM PDT 24
Finished May 16 03:29:33 PM PDT 24
Peak memory 213064 kb
Host smart-2244729a-aa05-4585-ab8e-addebabc5a67
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751617935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2751617935
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2059869997
Short name T791
Test name
Test status
Simulation time 9603085635 ps
CPU time 52.6 seconds
Started May 16 03:29:24 PM PDT 24
Finished May 16 03:30:22 PM PDT 24
Peak memory 269076 kb
Host smart-e87ed5a5-f19c-4bd1-ab4f-5cbe4ebad5a3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059869997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2059869997
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3618823917
Short name T783
Test name
Test status
Simulation time 671488375 ps
CPU time 11.4 seconds
Started May 16 03:29:25 PM PDT 24
Finished May 16 03:29:42 PM PDT 24
Peak memory 217724 kb
Host smart-da8e5a29-ac99-4a82-8443-9c3dd8eada4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618823917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3618823917
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.3208338402
Short name T331
Test name
Test status
Simulation time 214354242 ps
CPU time 2.19 seconds
Started May 16 03:29:28 PM PDT 24
Finished May 16 03:29:36 PM PDT 24
Peak memory 217824 kb
Host smart-f24db6c2-8460-4d91-ab48-faf0adb8a26b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208338402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3208338402
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.380492515
Short name T71
Test name
Test status
Simulation time 364210369 ps
CPU time 10.39 seconds
Started May 16 03:29:22 PM PDT 24
Finished May 16 03:29:38 PM PDT 24
Peak memory 214280 kb
Host smart-8b7ce951-b1d6-4628-8348-b2f7b5b06e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380492515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.380492515
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2431397328
Short name T87
Test name
Test status
Simulation time 830185437 ps
CPU time 37.14 seconds
Started May 16 03:29:24 PM PDT 24
Finished May 16 03:30:07 PM PDT 24
Peak memory 270524 kb
Host smart-94b670e9-db62-403b-8f55-b65cd56cbc66
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431397328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2431397328
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.831344658
Short name T20
Test name
Test status
Simulation time 2491751001 ps
CPU time 17.04 seconds
Started May 16 03:29:33 PM PDT 24
Finished May 16 03:29:57 PM PDT 24
Peak memory 225940 kb
Host smart-c8d6fada-3922-48fa-aa3c-c5393bb89f1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831344658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.831344658
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1396184477
Short name T486
Test name
Test status
Simulation time 422556871 ps
CPU time 9.26 seconds
Started May 16 03:29:33 PM PDT 24
Finished May 16 03:29:49 PM PDT 24
Peak memory 217832 kb
Host smart-cbfb3cf7-a15e-4841-bf8c-bc73439e5c14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396184477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1396184477
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3731938817
Short name T576
Test name
Test status
Simulation time 250967717 ps
CPU time 10.2 seconds
Started May 16 03:29:24 PM PDT 24
Finished May 16 03:29:40 PM PDT 24
Peak memory 217952 kb
Host smart-2d13f882-e5e0-4c90-aa92-14ba66364a60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731938817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
731938817
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3986402925
Short name T670
Test name
Test status
Simulation time 248573229 ps
CPU time 6.97 seconds
Started May 16 03:29:23 PM PDT 24
Finished May 16 03:29:35 PM PDT 24
Peak memory 217928 kb
Host smart-c0a2a588-fed8-4d2c-b18c-32a99a9f45ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986402925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3986402925
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2468532405
Short name T334
Test name
Test status
Simulation time 43550001 ps
CPU time 3 seconds
Started May 16 03:29:23 PM PDT 24
Finished May 16 03:29:32 PM PDT 24
Peak memory 214336 kb
Host smart-175e2d2a-c92a-4270-ba51-a18a70c9b643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468532405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2468532405
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1132530187
Short name T366
Test name
Test status
Simulation time 707493300 ps
CPU time 22.2 seconds
Started May 16 03:29:24 PM PDT 24
Finished May 16 03:29:52 PM PDT 24
Peak memory 250876 kb
Host smart-a8daf44a-7215-4e27-873e-efa4e0334bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132530187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1132530187
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2942800268
Short name T653
Test name
Test status
Simulation time 100687726 ps
CPU time 7.73 seconds
Started May 16 03:29:22 PM PDT 24
Finished May 16 03:29:36 PM PDT 24
Peak memory 250836 kb
Host smart-ef8a0495-f5d8-45f7-9321-7e693bb89f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942800268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2942800268
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3895321756
Short name T281
Test name
Test status
Simulation time 11253970546 ps
CPU time 254.28 seconds
Started May 16 03:29:25 PM PDT 24
Finished May 16 03:33:44 PM PDT 24
Peak memory 267384 kb
Host smart-3f5fcf05-f231-4654-90a8-fbdac5c8e4eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895321756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3895321756
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.960966153
Short name T857
Test name
Test status
Simulation time 18107218 ps
CPU time 1 seconds
Started May 16 03:29:24 PM PDT 24
Finished May 16 03:29:31 PM PDT 24
Peak memory 211532 kb
Host smart-23d14062-b981-4230-9b8f-111d87dd8841
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960966153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctr
l_volatile_unlock_smoke.960966153
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3938185636
Short name T350
Test name
Test status
Simulation time 21899442 ps
CPU time 0.81 seconds
Started May 16 03:30:00 PM PDT 24
Finished May 16 03:30:10 PM PDT 24
Peak memory 209360 kb
Host smart-7ba7ed69-a59f-46e9-8235-921d004eac52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938185636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3938185636
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.709430692
Short name T802
Test name
Test status
Simulation time 205874280 ps
CPU time 11.62 seconds
Started May 16 03:30:00 PM PDT 24
Finished May 16 03:30:21 PM PDT 24
Peak memory 217872 kb
Host smart-285a0a89-7244-4518-8486-86f52abf8c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709430692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.709430692
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.4025644362
Short name T204
Test name
Test status
Simulation time 43710577 ps
CPU time 1.26 seconds
Started May 16 03:30:05 PM PDT 24
Finished May 16 03:30:17 PM PDT 24
Peak memory 216712 kb
Host smart-79de41f8-324a-4f71-9662-b5722c6234c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025644362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.4025644362
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.1103645340
Short name T197
Test name
Test status
Simulation time 1306226237 ps
CPU time 39.26 seconds
Started May 16 03:30:05 PM PDT 24
Finished May 16 03:30:55 PM PDT 24
Peak memory 217908 kb
Host smart-9b85477a-bca2-4b39-a5e2-83f1a6496376
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103645340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.1103645340
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2137884573
Short name T428
Test name
Test status
Simulation time 2697189288 ps
CPU time 12.04 seconds
Started May 16 03:30:05 PM PDT 24
Finished May 16 03:30:27 PM PDT 24
Peak memory 217840 kb
Host smart-d21386b1-a993-4591-aed5-a98af56c50bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137884573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2137884573
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2263027260
Short name T404
Test name
Test status
Simulation time 2146648607 ps
CPU time 7.14 seconds
Started May 16 03:30:03 PM PDT 24
Finished May 16 03:30:20 PM PDT 24
Peak memory 213600 kb
Host smart-3a31b0c5-d33c-4993-adcd-ba173413a219
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263027260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2263027260
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.843905021
Short name T817
Test name
Test status
Simulation time 4857558942 ps
CPU time 67.04 seconds
Started May 16 03:30:05 PM PDT 24
Finished May 16 03:31:22 PM PDT 24
Peak memory 283476 kb
Host smart-a816805c-670f-4a4f-b292-f2fe9b406caa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843905021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_state_failure.843905021
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3345417983
Short name T253
Test name
Test status
Simulation time 729496381 ps
CPU time 11.23 seconds
Started May 16 03:29:57 PM PDT 24
Finished May 16 03:30:16 PM PDT 24
Peak memory 223992 kb
Host smart-46a14ec2-575a-4da5-8975-01e0d493a23c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345417983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3345417983
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.4075653262
Short name T309
Test name
Test status
Simulation time 36075532 ps
CPU time 2.47 seconds
Started May 16 03:30:00 PM PDT 24
Finished May 16 03:30:11 PM PDT 24
Peak memory 217876 kb
Host smart-2bb690b9-d9a4-495e-8273-4fb992e9b479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075653262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.4075653262
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.2475559643
Short name T685
Test name
Test status
Simulation time 287546723 ps
CPU time 14.56 seconds
Started May 16 03:30:03 PM PDT 24
Finished May 16 03:30:28 PM PDT 24
Peak memory 218812 kb
Host smart-5220a0f8-46cb-4e67-ad3b-ef48ee684c3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475559643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2475559643
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3432835291
Short name T680
Test name
Test status
Simulation time 1391421219 ps
CPU time 12.28 seconds
Started May 16 03:29:57 PM PDT 24
Finished May 16 03:30:18 PM PDT 24
Peak memory 217788 kb
Host smart-044f7b60-832b-40d2-966e-4957b6ce4bc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432835291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3432835291
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.87846758
Short name T822
Test name
Test status
Simulation time 456552300 ps
CPU time 8.12 seconds
Started May 16 03:30:00 PM PDT 24
Finished May 16 03:30:17 PM PDT 24
Peak memory 217856 kb
Host smart-dedd59e7-9011-4400-8d02-b232a7fd78fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87846758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.87846758
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.1478324309
Short name T596
Test name
Test status
Simulation time 263540210 ps
CPU time 10.32 seconds
Started May 16 03:29:58 PM PDT 24
Finished May 16 03:30:16 PM PDT 24
Peak memory 217856 kb
Host smart-558f8e9a-b502-4549-b601-5aad15eab2f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478324309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.1478324309
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3726300273
Short name T192
Test name
Test status
Simulation time 55577598 ps
CPU time 2.37 seconds
Started May 16 03:30:00 PM PDT 24
Finished May 16 03:30:12 PM PDT 24
Peak memory 214120 kb
Host smart-a36e47bb-162a-42f1-a125-58c9fe1a78dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726300273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3726300273
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.398931346
Short name T261
Test name
Test status
Simulation time 450617007 ps
CPU time 30.2 seconds
Started May 16 03:29:57 PM PDT 24
Finished May 16 03:30:35 PM PDT 24
Peak memory 250936 kb
Host smart-524020be-7571-4eef-9b2d-41c75ccdfbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398931346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.398931346
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1566925358
Short name T508
Test name
Test status
Simulation time 60328047 ps
CPU time 8.32 seconds
Started May 16 03:30:01 PM PDT 24
Finished May 16 03:30:19 PM PDT 24
Peak memory 250832 kb
Host smart-49384f77-be60-4897-a157-366274b3776c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566925358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1566925358
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2290446909
Short name T607
Test name
Test status
Simulation time 16658997372 ps
CPU time 502.34 seconds
Started May 16 03:30:00 PM PDT 24
Finished May 16 03:38:31 PM PDT 24
Peak memory 221044 kb
Host smart-014059ce-0b07-41ee-a8e7-da7cd441a710
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290446909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2290446909
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.3201600917
Short name T153
Test name
Test status
Simulation time 66248315463 ps
CPU time 976.14 seconds
Started May 16 03:30:02 PM PDT 24
Finished May 16 03:46:29 PM PDT 24
Peak memory 316516 kb
Host smart-35f5cf5e-e509-4cfa-8ee5-20865ed1dcd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3201600917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.3201600917
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.674746557
Short name T563
Test name
Test status
Simulation time 11629832 ps
CPU time 1.02 seconds
Started May 16 03:30:03 PM PDT 24
Finished May 16 03:30:14 PM PDT 24
Peak memory 211520 kb
Host smart-9ebb5226-6364-47e8-b0ba-53bf24acdfdd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674746557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ct
rl_volatile_unlock_smoke.674746557
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3942730420
Short name T399
Test name
Test status
Simulation time 15168994 ps
CPU time 1.01 seconds
Started May 16 03:30:05 PM PDT 24
Finished May 16 03:30:16 PM PDT 24
Peak memory 209416 kb
Host smart-c7b33d86-8daf-4c1e-ac89-9fdc6694ffad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942730420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3942730420
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2255494657
Short name T841
Test name
Test status
Simulation time 759296335 ps
CPU time 13.81 seconds
Started May 16 03:29:57 PM PDT 24
Finished May 16 03:30:18 PM PDT 24
Peak memory 217788 kb
Host smart-c319e30b-ef8e-4b66-8df4-57210bf361f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255494657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2255494657
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3856941430
Short name T683
Test name
Test status
Simulation time 658177668 ps
CPU time 14.83 seconds
Started May 16 03:30:03 PM PDT 24
Finished May 16 03:30:28 PM PDT 24
Peak memory 216892 kb
Host smart-7ad98a3d-52ff-4f59-a2b5-875309432837
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856941430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3856941430
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.285582337
Short name T503
Test name
Test status
Simulation time 7898983986 ps
CPU time 25.04 seconds
Started May 16 03:29:57 PM PDT 24
Finished May 16 03:30:29 PM PDT 24
Peak memory 218772 kb
Host smart-116330e3-11da-4af6-92b2-71fad787970e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285582337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er
rors.285582337
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.768117924
Short name T174
Test name
Test status
Simulation time 1133992667 ps
CPU time 9.5 seconds
Started May 16 03:30:00 PM PDT 24
Finished May 16 03:30:19 PM PDT 24
Peak memory 217864 kb
Host smart-a5366233-f0af-444c-b7e0-5dbc4aa8022c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768117924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.768117924
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.1239140638
Short name T68
Test name
Test status
Simulation time 660951478 ps
CPU time 3.33 seconds
Started May 16 03:30:03 PM PDT 24
Finished May 16 03:30:17 PM PDT 24
Peak memory 213044 kb
Host smart-f7e0acd3-3e99-4e6b-9e4e-563b8903aad6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239140638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.1239140638
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2354116814
Short name T233
Test name
Test status
Simulation time 1012707215 ps
CPU time 48.84 seconds
Started May 16 03:30:01 PM PDT 24
Finished May 16 03:31:00 PM PDT 24
Peak memory 250744 kb
Host smart-e6f53def-3fea-4cfb-a8ec-fac0b291137b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354116814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2354116814
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3340521536
Short name T544
Test name
Test status
Simulation time 242944800 ps
CPU time 8.75 seconds
Started May 16 03:30:00 PM PDT 24
Finished May 16 03:30:18 PM PDT 24
Peak memory 245668 kb
Host smart-14051cf7-8377-49e7-88d4-583099e1880e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340521536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3340521536
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.4166170380
Short name T703
Test name
Test status
Simulation time 74881466 ps
CPU time 2.21 seconds
Started May 16 03:30:05 PM PDT 24
Finished May 16 03:30:18 PM PDT 24
Peak memory 217840 kb
Host smart-6741ab7a-3205-4b5e-894f-cffbab27af38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166170380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.4166170380
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.713600970
Short name T567
Test name
Test status
Simulation time 257162994 ps
CPU time 10.34 seconds
Started May 16 03:30:04 PM PDT 24
Finished May 16 03:30:25 PM PDT 24
Peak memory 225896 kb
Host smart-7e0ff473-9923-4c49-8daf-da694d9bc737
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713600970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.713600970
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1635952113
Short name T832
Test name
Test status
Simulation time 304086692 ps
CPU time 10.01 seconds
Started May 16 03:30:00 PM PDT 24
Finished May 16 03:30:19 PM PDT 24
Peak memory 217840 kb
Host smart-ef31ed87-b90c-4934-8a27-d5b769ac73da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635952113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1635952113
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2182102084
Short name T62
Test name
Test status
Simulation time 214008744 ps
CPU time 6.61 seconds
Started May 16 03:30:00 PM PDT 24
Finished May 16 03:30:16 PM PDT 24
Peak memory 217848 kb
Host smart-f6d45bae-135e-479f-882d-0ba5397c3d57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182102084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2182102084
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.1642300177
Short name T645
Test name
Test status
Simulation time 1772238025 ps
CPU time 6.38 seconds
Started May 16 03:29:58 PM PDT 24
Finished May 16 03:30:13 PM PDT 24
Peak memory 217824 kb
Host smart-fc2cd1e3-e4cc-4524-b216-65fb5bc7b9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642300177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.1642300177
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3971190430
Short name T265
Test name
Test status
Simulation time 55418699 ps
CPU time 2.93 seconds
Started May 16 03:30:03 PM PDT 24
Finished May 16 03:30:16 PM PDT 24
Peak memory 217784 kb
Host smart-bfcea310-6028-4c14-bdc7-790eb93797e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971190430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3971190430
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.2580708758
Short name T398
Test name
Test status
Simulation time 780276951 ps
CPU time 25.19 seconds
Started May 16 03:30:05 PM PDT 24
Finished May 16 03:30:41 PM PDT 24
Peak memory 250880 kb
Host smart-bbab100e-a026-46a6-bf4a-f1413cc80243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580708758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.2580708758
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3694693041
Short name T713
Test name
Test status
Simulation time 85553046 ps
CPU time 7.32 seconds
Started May 16 03:30:03 PM PDT 24
Finished May 16 03:30:21 PM PDT 24
Peak memory 250788 kb
Host smart-1a55b0a7-adc1-4d21-afb6-e70b75bcc0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694693041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3694693041
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.447106367
Short name T367
Test name
Test status
Simulation time 11053421939 ps
CPU time 224.03 seconds
Started May 16 03:30:04 PM PDT 24
Finished May 16 03:33:59 PM PDT 24
Peak memory 267996 kb
Host smart-59ec7bd8-cb9d-4be8-ae12-25a27798c495
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447106367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.447106367
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1879967933
Short name T426
Test name
Test status
Simulation time 17850320 ps
CPU time 1.04 seconds
Started May 16 03:30:01 PM PDT 24
Finished May 16 03:30:12 PM PDT 24
Peak memory 211588 kb
Host smart-7f3c5eb9-39e3-4705-bf47-80648d7ad2c2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879967933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1879967933
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1777482063
Short name T489
Test name
Test status
Simulation time 42071068 ps
CPU time 0.97 seconds
Started May 16 03:30:08 PM PDT 24
Finished May 16 03:30:20 PM PDT 24
Peak memory 209408 kb
Host smart-2d88ed86-b09f-494d-bac7-7d4696c2c7c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777482063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1777482063
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3154816649
Short name T351
Test name
Test status
Simulation time 1508996958 ps
CPU time 11.63 seconds
Started May 16 03:30:03 PM PDT 24
Finished May 16 03:30:26 PM PDT 24
Peak memory 217828 kb
Host smart-64518db6-b5d9-4ff4-bc24-cc6a75579255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154816649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3154816649
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2593943548
Short name T185
Test name
Test status
Simulation time 288734620 ps
CPU time 4.09 seconds
Started May 16 03:30:08 PM PDT 24
Finished May 16 03:30:23 PM PDT 24
Peak memory 216164 kb
Host smart-6f3ad763-f17b-4031-bcc3-f65a506b80b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593943548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2593943548
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1886146184
Short name T98
Test name
Test status
Simulation time 1390041234 ps
CPU time 43.76 seconds
Started May 16 03:30:06 PM PDT 24
Finished May 16 03:31:01 PM PDT 24
Peak memory 218040 kb
Host smart-11ecc28f-bbb1-4416-acc2-d0bb99c6de87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886146184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1886146184
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2742806295
Short name T651
Test name
Test status
Simulation time 3534368001 ps
CPU time 8.43 seconds
Started May 16 03:30:05 PM PDT 24
Finished May 16 03:30:24 PM PDT 24
Peak memory 217952 kb
Host smart-aed6b622-1b47-4396-b80f-67aff1925325
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742806295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2742806295
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2734014004
Short name T66
Test name
Test status
Simulation time 163820921 ps
CPU time 4.52 seconds
Started May 16 03:30:04 PM PDT 24
Finished May 16 03:30:19 PM PDT 24
Peak memory 212760 kb
Host smart-5f9968a8-69b8-49ac-a0e6-33d07b682603
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734014004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2734014004
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.628939003
Short name T429
Test name
Test status
Simulation time 1375553882 ps
CPU time 45 seconds
Started May 16 03:30:08 PM PDT 24
Finished May 16 03:31:03 PM PDT 24
Peak memory 250752 kb
Host smart-60752d94-85ae-4995-b8a9-6f4c020dd6f3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628939003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_state_failure.628939003
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2393277085
Short name T394
Test name
Test status
Simulation time 549457069 ps
CPU time 23.59 seconds
Started May 16 03:30:02 PM PDT 24
Finished May 16 03:30:36 PM PDT 24
Peak memory 250760 kb
Host smart-4b171111-c20d-46d2-aab6-af49ecd8af44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393277085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2393277085
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1810313330
Short name T578
Test name
Test status
Simulation time 112831205 ps
CPU time 2.33 seconds
Started May 16 03:30:06 PM PDT 24
Finished May 16 03:30:19 PM PDT 24
Peak memory 217848 kb
Host smart-0f818274-e889-4894-b836-a9424fb07199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810313330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1810313330
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.6709778
Short name T625
Test name
Test status
Simulation time 228052170 ps
CPU time 8.2 seconds
Started May 16 03:30:08 PM PDT 24
Finished May 16 03:30:27 PM PDT 24
Peak memory 225940 kb
Host smart-9eb2188a-f78e-43d6-9481-168f975c735e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6709778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.6709778
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2785922524
Short name T825
Test name
Test status
Simulation time 1439801985 ps
CPU time 10.36 seconds
Started May 16 03:30:12 PM PDT 24
Finished May 16 03:30:34 PM PDT 24
Peak memory 217832 kb
Host smart-cf7c20dd-7105-4f69-92d8-d410f03a5db6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785922524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2785922524
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.3367100677
Short name T838
Test name
Test status
Simulation time 5784700435 ps
CPU time 7.89 seconds
Started May 16 03:30:08 PM PDT 24
Finished May 16 03:30:27 PM PDT 24
Peak memory 218040 kb
Host smart-cc77e5d9-396a-49ac-aaee-ec7f797bc1a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367100677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
3367100677
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2418777180
Short name T453
Test name
Test status
Simulation time 779879081 ps
CPU time 9.52 seconds
Started May 16 03:30:13 PM PDT 24
Finished May 16 03:30:33 PM PDT 24
Peak memory 217900 kb
Host smart-f896795c-ee9b-43da-bfee-8e045a5042af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418777180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2418777180
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.527445231
Short name T873
Test name
Test status
Simulation time 55209043 ps
CPU time 2.64 seconds
Started May 16 03:30:01 PM PDT 24
Finished May 16 03:30:13 PM PDT 24
Peak memory 213948 kb
Host smart-8794d933-510c-4fbc-b972-e6d79e4cdc34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527445231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.527445231
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.1839915455
Short name T662
Test name
Test status
Simulation time 1458893981 ps
CPU time 23.44 seconds
Started May 16 03:30:02 PM PDT 24
Finished May 16 03:30:36 PM PDT 24
Peak memory 250784 kb
Host smart-e6a32dbf-597b-4690-a2b5-a080515f1bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839915455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.1839915455
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1852592107
Short name T355
Test name
Test status
Simulation time 54125611 ps
CPU time 3.13 seconds
Started May 16 03:30:06 PM PDT 24
Finished May 16 03:30:20 PM PDT 24
Peak memory 222456 kb
Host smart-0ed4ad00-af3f-45f7-8049-0f71c325ea8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852592107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1852592107
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.3693784447
Short name T421
Test name
Test status
Simulation time 3075753741 ps
CPU time 72.01 seconds
Started May 16 03:30:12 PM PDT 24
Finished May 16 03:31:35 PM PDT 24
Peak memory 275636 kb
Host smart-ee1be599-46b6-4b78-8be9-a4f5f2727bd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693784447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.3693784447
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1702142741
Short name T236
Test name
Test status
Simulation time 21395252 ps
CPU time 0.86 seconds
Started May 16 03:30:02 PM PDT 24
Finished May 16 03:30:13 PM PDT 24
Peak memory 211572 kb
Host smart-d4d13987-f190-41d6-a431-971c01e2cdd0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702142741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1702142741
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.1792863315
Short name T69
Test name
Test status
Simulation time 37549076 ps
CPU time 1.58 seconds
Started May 16 03:30:09 PM PDT 24
Finished May 16 03:30:22 PM PDT 24
Peak memory 209476 kb
Host smart-753ddb4b-f445-4f90-afcb-0ea0acad79dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792863315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.1792863315
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3981007786
Short name T58
Test name
Test status
Simulation time 876844917 ps
CPU time 18.48 seconds
Started May 16 03:30:04 PM PDT 24
Finished May 16 03:30:33 PM PDT 24
Peak memory 217920 kb
Host smart-ec12aa18-52ee-4570-901c-339522f0d933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981007786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3981007786
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1739530512
Short name T31
Test name
Test status
Simulation time 536448048 ps
CPU time 2.7 seconds
Started May 16 03:30:05 PM PDT 24
Finished May 16 03:30:18 PM PDT 24
Peak memory 209528 kb
Host smart-a11a16fe-dcc1-4505-b3de-67dd430573f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739530512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1739530512
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.749550418
Short name T343
Test name
Test status
Simulation time 2878529588 ps
CPU time 82.35 seconds
Started May 16 03:30:06 PM PDT 24
Finished May 16 03:31:39 PM PDT 24
Peak memory 219984 kb
Host smart-68e3f4e9-155a-450b-8931-7d55668e9a14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749550418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.749550418
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3715179187
Short name T560
Test name
Test status
Simulation time 2538048793 ps
CPU time 12.73 seconds
Started May 16 03:30:06 PM PDT 24
Finished May 16 03:30:30 PM PDT 24
Peak memory 217956 kb
Host smart-668b496c-0992-4886-b03d-b8794b532b14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3715179187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3715179187
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2610766669
Short name T64
Test name
Test status
Simulation time 148208115 ps
CPU time 2.74 seconds
Started May 16 03:30:12 PM PDT 24
Finished May 16 03:30:26 PM PDT 24
Peak memory 212956 kb
Host smart-933b7a9e-6f7b-4b88-8324-9f4d1a9bcc8c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610766669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2610766669
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3409832673
Short name T591
Test name
Test status
Simulation time 5944646256 ps
CPU time 41.34 seconds
Started May 16 03:30:03 PM PDT 24
Finished May 16 03:30:54 PM PDT 24
Peak memory 267268 kb
Host smart-3f1fb548-2715-4e45-9436-0cfc1970cb0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409832673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3409832673
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.2950337264
Short name T1
Test name
Test status
Simulation time 771048343 ps
CPU time 25.73 seconds
Started May 16 03:30:02 PM PDT 24
Finished May 16 03:30:37 PM PDT 24
Peak memory 245924 kb
Host smart-0fae8f20-eded-41a8-a1a0-fa90841fe38b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950337264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.2950337264
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.1218018258
Short name T813
Test name
Test status
Simulation time 428830044 ps
CPU time 3.51 seconds
Started May 16 03:30:12 PM PDT 24
Finished May 16 03:30:27 PM PDT 24
Peak memory 217832 kb
Host smart-36ea351e-d189-441a-81c8-9497def069f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218018258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.1218018258
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.8559502
Short name T527
Test name
Test status
Simulation time 1523093942 ps
CPU time 17.84 seconds
Started May 16 03:30:05 PM PDT 24
Finished May 16 03:30:33 PM PDT 24
Peak memory 225956 kb
Host smart-73a8e80c-67f9-40a7-9e71-84600f6787de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8559502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.8559502
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2232691492
Short name T423
Test name
Test status
Simulation time 257156145 ps
CPU time 9.64 seconds
Started May 16 03:30:10 PM PDT 24
Finished May 16 03:30:30 PM PDT 24
Peak memory 217836 kb
Host smart-4cf1d867-8d13-48aa-b94a-73fb83c96f29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232691492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2232691492
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2405372093
Short name T752
Test name
Test status
Simulation time 1738104494 ps
CPU time 10.14 seconds
Started May 16 03:30:04 PM PDT 24
Finished May 16 03:30:25 PM PDT 24
Peak memory 217804 kb
Host smart-0b786123-456a-4326-bbba-8d6d37fa6e4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405372093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2405372093
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2718044371
Short name T722
Test name
Test status
Simulation time 3950300344 ps
CPU time 11.73 seconds
Started May 16 03:30:08 PM PDT 24
Finished May 16 03:30:31 PM PDT 24
Peak memory 217296 kb
Host smart-4a6270fe-5bf1-4c3e-8c31-5ecd4b9af2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718044371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2718044371
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2545006667
Short name T313
Test name
Test status
Simulation time 17708642 ps
CPU time 1.21 seconds
Started May 16 03:30:05 PM PDT 24
Finished May 16 03:30:16 PM PDT 24
Peak memory 213072 kb
Host smart-f8f59eba-05d6-4352-8c5c-5e1c35699f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545006667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2545006667
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.3299252078
Short name T250
Test name
Test status
Simulation time 1101959543 ps
CPU time 28.94 seconds
Started May 16 03:30:09 PM PDT 24
Finished May 16 03:30:49 PM PDT 24
Peak memory 250824 kb
Host smart-428c8fbc-262a-4747-9947-c431a6a85510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299252078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.3299252078
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2603979079
Short name T784
Test name
Test status
Simulation time 143678176 ps
CPU time 8.97 seconds
Started May 16 03:30:08 PM PDT 24
Finished May 16 03:30:28 PM PDT 24
Peak memory 250920 kb
Host smart-cf686958-b67d-4c12-96a9-ba69cbb29b4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603979079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2603979079
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3899121441
Short name T628
Test name
Test status
Simulation time 11471760424 ps
CPU time 181.83 seconds
Started May 16 03:30:10 PM PDT 24
Finished May 16 03:33:24 PM PDT 24
Peak memory 272748 kb
Host smart-9f259be0-ffab-49e5-bd98-85a83b36dab6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899121441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3899121441
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.581720607
Short name T154
Test name
Test status
Simulation time 103615475011 ps
CPU time 985.3 seconds
Started May 16 03:30:09 PM PDT 24
Finished May 16 03:46:45 PM PDT 24
Peak memory 292556 kb
Host smart-376b4d3e-ad95-41a3-8870-d244a789fd3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=581720607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.581720607
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2212104665
Short name T676
Test name
Test status
Simulation time 21139777 ps
CPU time 0.9 seconds
Started May 16 03:30:02 PM PDT 24
Finished May 16 03:30:13 PM PDT 24
Peak memory 211496 kb
Host smart-3328704a-f234-4811-8f46-f23126f1ef10
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212104665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2212104665
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.1595770932
Short name T389
Test name
Test status
Simulation time 29488544 ps
CPU time 0.99 seconds
Started May 16 03:30:18 PM PDT 24
Finished May 16 03:30:30 PM PDT 24
Peak memory 209432 kb
Host smart-e7dff60c-184b-4091-9918-5e26b75180ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595770932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.1595770932
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3924230557
Short name T706
Test name
Test status
Simulation time 236785693 ps
CPU time 10.29 seconds
Started May 16 03:30:09 PM PDT 24
Finished May 16 03:30:30 PM PDT 24
Peak memory 217768 kb
Host smart-b10e1216-8d2a-4142-80ee-f790d593624d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924230557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3924230557
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.836903753
Short name T540
Test name
Test status
Simulation time 383482008 ps
CPU time 9.73 seconds
Started May 16 03:30:13 PM PDT 24
Finished May 16 03:30:33 PM PDT 24
Peak memory 209372 kb
Host smart-17b541be-6679-4603-a8d3-629177f86bda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836903753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.836903753
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.886979086
Short name T529
Test name
Test status
Simulation time 5681649711 ps
CPU time 40.89 seconds
Started May 16 03:30:10 PM PDT 24
Finished May 16 03:31:03 PM PDT 24
Peak memory 218860 kb
Host smart-684606ed-8176-4b65-83c4-645c53476d96
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886979086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.886979086
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2552561238
Short name T794
Test name
Test status
Simulation time 309432896 ps
CPU time 6.37 seconds
Started May 16 03:30:10 PM PDT 24
Finished May 16 03:30:28 PM PDT 24
Peak memory 217844 kb
Host smart-0de674fd-9091-4801-b109-17dcef8e96d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552561238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2552561238
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3997702720
Short name T818
Test name
Test status
Simulation time 1041847207 ps
CPU time 13.41 seconds
Started May 16 03:30:11 PM PDT 24
Finished May 16 03:30:35 PM PDT 24
Peak memory 213436 kb
Host smart-50428145-5822-4ad8-b215-fe6bcf113d18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997702720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.3997702720
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.217540657
Short name T543
Test name
Test status
Simulation time 6694934398 ps
CPU time 55.09 seconds
Started May 16 03:30:10 PM PDT 24
Finished May 16 03:31:16 PM PDT 24
Peak memory 267288 kb
Host smart-5999f898-48c9-468d-b90e-d078df80e62a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217540657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_state_failure.217540657
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.3293262093
Short name T507
Test name
Test status
Simulation time 7911402960 ps
CPU time 18.27 seconds
Started May 16 03:30:13 PM PDT 24
Finished May 16 03:30:42 PM PDT 24
Peak memory 250176 kb
Host smart-7f29c73b-ae1b-4bdd-8f99-ec83db60f2a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293262093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.3293262093
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3712924689
Short name T593
Test name
Test status
Simulation time 166981849 ps
CPU time 1.57 seconds
Started May 16 03:30:10 PM PDT 24
Finished May 16 03:30:23 PM PDT 24
Peak memory 217844 kb
Host smart-429ecf1f-6915-4983-973e-8fdae25e03fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712924689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3712924689
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1560666725
Short name T652
Test name
Test status
Simulation time 830346563 ps
CPU time 12.77 seconds
Started May 16 03:30:11 PM PDT 24
Finished May 16 03:30:36 PM PDT 24
Peak memory 225956 kb
Host smart-121e17ed-6dcd-482e-ba44-6dd84a821d8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560666725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1560666725
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.4225165899
Short name T642
Test name
Test status
Simulation time 788198693 ps
CPU time 11.41 seconds
Started May 16 03:30:09 PM PDT 24
Finished May 16 03:30:31 PM PDT 24
Peak memory 217856 kb
Host smart-2624ab1a-ab2e-4eef-8d03-358a3d52d93d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225165899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.4225165899
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.517862693
Short name T771
Test name
Test status
Simulation time 1137483396 ps
CPU time 8.21 seconds
Started May 16 03:30:10 PM PDT 24
Finished May 16 03:30:30 PM PDT 24
Peak memory 217848 kb
Host smart-044fd501-00bf-432e-92c8-be6e08e2a955
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517862693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.517862693
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.479808410
Short name T689
Test name
Test status
Simulation time 887827946 ps
CPU time 15.33 seconds
Started May 16 03:30:10 PM PDT 24
Finished May 16 03:30:37 PM PDT 24
Peak memory 217880 kb
Host smart-960cc8ca-ced2-4c5a-a2fb-e6fe5a03add0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479808410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.479808410
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.280498582
Short name T70
Test name
Test status
Simulation time 68847241 ps
CPU time 2.49 seconds
Started May 16 03:30:09 PM PDT 24
Finished May 16 03:30:22 PM PDT 24
Peak memory 214032 kb
Host smart-eb74fd2e-2800-4aa8-8760-9dec5d12f3fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280498582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.280498582
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3844495198
Short name T626
Test name
Test status
Simulation time 2546006672 ps
CPU time 28.3 seconds
Started May 16 03:30:10 PM PDT 24
Finished May 16 03:30:50 PM PDT 24
Peak memory 250960 kb
Host smart-ca66d0cb-00ce-409c-bca7-6d031c615f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844495198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3844495198
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.4126313366
Short name T77
Test name
Test status
Simulation time 114123893 ps
CPU time 6.4 seconds
Started May 16 03:30:11 PM PDT 24
Finished May 16 03:30:30 PM PDT 24
Peak memory 247476 kb
Host smart-eb5e0b61-db03-4075-bd27-05847ea2a9fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126313366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.4126313366
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1950498245
Short name T558
Test name
Test status
Simulation time 6061196524 ps
CPU time 107.67 seconds
Started May 16 03:30:12 PM PDT 24
Finished May 16 03:32:11 PM PDT 24
Peak memory 247324 kb
Host smart-d1edc74e-e3d2-4549-8087-b2a13c0c358e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950498245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1950498245
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.3689850802
Short name T199
Test name
Test status
Simulation time 81971871 ps
CPU time 0.89 seconds
Started May 16 03:30:12 PM PDT 24
Finished May 16 03:30:24 PM PDT 24
Peak memory 211488 kb
Host smart-8e798591-88ae-4c43-9df0-034e03296bb7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689850802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.3689850802
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.3506704185
Short name T379
Test name
Test status
Simulation time 76153831 ps
CPU time 1 seconds
Started May 16 03:30:17 PM PDT 24
Finished May 16 03:30:28 PM PDT 24
Peak memory 209524 kb
Host smart-be86709c-fdbe-48ea-ba77-a7a8933136d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506704185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.3506704185
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3726737125
Short name T719
Test name
Test status
Simulation time 621733016 ps
CPU time 9.1 seconds
Started May 16 03:30:17 PM PDT 24
Finished May 16 03:30:37 PM PDT 24
Peak memory 217892 kb
Host smart-b0e0d589-0adf-469e-a4c1-74c223b264d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726737125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3726737125
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.921363861
Short name T537
Test name
Test status
Simulation time 252280624 ps
CPU time 2.18 seconds
Started May 16 03:30:17 PM PDT 24
Finished May 16 03:30:31 PM PDT 24
Peak memory 209412 kb
Host smart-dcae7b3e-da9b-4aea-aee0-d295c4fa3fb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921363861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.921363861
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2278466159
Short name T494
Test name
Test status
Simulation time 1045123639 ps
CPU time 31.3 seconds
Started May 16 03:30:17 PM PDT 24
Finished May 16 03:30:59 PM PDT 24
Peak memory 217764 kb
Host smart-93f876a0-5aa6-40b6-9f97-c6ca9b7f978d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278466159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2278466159
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3452101310
Short name T716
Test name
Test status
Simulation time 828523065 ps
CPU time 5.56 seconds
Started May 16 03:30:17 PM PDT 24
Finished May 16 03:30:33 PM PDT 24
Peak memory 217860 kb
Host smart-79465ea0-f39e-4111-9fde-449b3107fb57
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452101310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3452101310
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.428074949
Short name T632
Test name
Test status
Simulation time 1424282219 ps
CPU time 5.36 seconds
Started May 16 03:30:16 PM PDT 24
Finished May 16 03:30:32 PM PDT 24
Peak memory 213532 kb
Host smart-8fea7fa3-5921-40b6-bdda-3598abd4d61f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428074949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.
428074949
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3900335545
Short name T667
Test name
Test status
Simulation time 1747596198 ps
CPU time 43.91 seconds
Started May 16 03:30:17 PM PDT 24
Finished May 16 03:31:11 PM PDT 24
Peak memory 275360 kb
Host smart-bc4c0231-7380-4ad4-a7fa-22847103fb4d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900335545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3900335545
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2360183351
Short name T294
Test name
Test status
Simulation time 1147750513 ps
CPU time 18.16 seconds
Started May 16 03:30:18 PM PDT 24
Finished May 16 03:30:47 PM PDT 24
Peak memory 222992 kb
Host smart-ff53f954-573f-42e5-9484-03427c27ddb5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360183351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2360183351
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.438867788
Short name T457
Test name
Test status
Simulation time 647954387 ps
CPU time 2.66 seconds
Started May 16 03:30:15 PM PDT 24
Finished May 16 03:30:29 PM PDT 24
Peak memory 217876 kb
Host smart-8ff01540-5d9e-4d4f-affc-fa42ae654448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438867788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.438867788
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.973424479
Short name T249
Test name
Test status
Simulation time 861902803 ps
CPU time 15.1 seconds
Started May 16 03:30:17 PM PDT 24
Finished May 16 03:30:43 PM PDT 24
Peak memory 225884 kb
Host smart-fb5fbfd3-5f74-4149-abed-d9a9b03c2484
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973424479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.973424479
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1053157427
Short name T635
Test name
Test status
Simulation time 337076224 ps
CPU time 12.71 seconds
Started May 16 03:30:19 PM PDT 24
Finished May 16 03:30:42 PM PDT 24
Peak memory 225916 kb
Host smart-6bb90368-8d60-4a98-8935-53a7b66ecb3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053157427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.1053157427
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3477287495
Short name T455
Test name
Test status
Simulation time 452034555 ps
CPU time 10.62 seconds
Started May 16 03:30:20 PM PDT 24
Finished May 16 03:30:41 PM PDT 24
Peak memory 217852 kb
Host smart-4e038297-75f4-46af-9737-2ffec08d968a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477287495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3477287495
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.2692492601
Short name T55
Test name
Test status
Simulation time 1551932221 ps
CPU time 12.19 seconds
Started May 16 03:30:17 PM PDT 24
Finished May 16 03:30:40 PM PDT 24
Peak memory 217840 kb
Host smart-20950d2f-4675-4d35-8711-895e021b366b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692492601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.2692492601
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.221533081
Short name T95
Test name
Test status
Simulation time 45198123 ps
CPU time 1.66 seconds
Started May 16 03:30:18 PM PDT 24
Finished May 16 03:30:31 PM PDT 24
Peak memory 213096 kb
Host smart-033f44f6-57cd-4a92-8693-155ad79d2222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221533081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.221533081
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.3416733471
Short name T803
Test name
Test status
Simulation time 1433808839 ps
CPU time 29.27 seconds
Started May 16 03:30:17 PM PDT 24
Finished May 16 03:30:58 PM PDT 24
Peak memory 250720 kb
Host smart-91040c3c-8513-4641-8404-500127c00028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416733471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.3416733471
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3728514892
Short name T514
Test name
Test status
Simulation time 180376201 ps
CPU time 2.93 seconds
Started May 16 03:30:19 PM PDT 24
Finished May 16 03:30:32 PM PDT 24
Peak memory 226260 kb
Host smart-dacdb55f-e2cb-4ea3-8a4a-bc8d9685b05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728514892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3728514892
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.351407513
Short name T781
Test name
Test status
Simulation time 17482949095 ps
CPU time 127.41 seconds
Started May 16 03:30:19 PM PDT 24
Finished May 16 03:32:37 PM PDT 24
Peak memory 283320 kb
Host smart-ea5fbd07-8dc1-475b-860d-67c1e2107e0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351407513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.351407513
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2078289767
Short name T640
Test name
Test status
Simulation time 77711802 ps
CPU time 1.01 seconds
Started May 16 03:30:19 PM PDT 24
Finished May 16 03:30:30 PM PDT 24
Peak memory 211468 kb
Host smart-cf77fe2f-307d-4d24-8759-777b6a27cc1a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078289767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2078289767
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.3248413725
Short name T492
Test name
Test status
Simulation time 44955084 ps
CPU time 1.28 seconds
Started May 16 03:30:24 PM PDT 24
Finished May 16 03:30:36 PM PDT 24
Peak memory 209448 kb
Host smart-8e4a83ed-9463-42ee-bb37-24ffabb0dbc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248413725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.3248413725
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3472481130
Short name T290
Test name
Test status
Simulation time 3665733554 ps
CPU time 12.42 seconds
Started May 16 03:30:16 PM PDT 24
Finished May 16 03:30:39 PM PDT 24
Peak memory 218084 kb
Host smart-484bd581-7178-42a8-9fad-5e143e426980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472481130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3472481130
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2280186631
Short name T776
Test name
Test status
Simulation time 3028102568 ps
CPU time 47.9 seconds
Started May 16 03:30:23 PM PDT 24
Finished May 16 03:31:21 PM PDT 24
Peak memory 218848 kb
Host smart-f655a351-08b5-4dd8-aaa3-d484cb0f012c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280186631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2280186631
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.3600023918
Short name T248
Test name
Test status
Simulation time 658973605 ps
CPU time 9.43 seconds
Started May 16 03:30:23 PM PDT 24
Finished May 16 03:30:43 PM PDT 24
Peak memory 217772 kb
Host smart-034c48ec-19e1-4d52-a24f-6ba239382cbe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600023918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.3600023918
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.4032937639
Short name T85
Test name
Test status
Simulation time 622330657 ps
CPU time 4.27 seconds
Started May 16 03:30:18 PM PDT 24
Finished May 16 03:30:33 PM PDT 24
Peak memory 213464 kb
Host smart-dcda9fb1-5546-4d79-95cf-6b3760b2a98c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032937639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.4032937639
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3765773929
Short name T26
Test name
Test status
Simulation time 1777644887 ps
CPU time 48.07 seconds
Started May 16 03:30:17 PM PDT 24
Finished May 16 03:31:16 PM PDT 24
Peak memory 275352 kb
Host smart-a917e260-4c18-4159-a39e-2606e586c206
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765773929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3765773929
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.370278388
Short name T595
Test name
Test status
Simulation time 787863313 ps
CPU time 13.61 seconds
Started May 16 03:30:18 PM PDT 24
Finished May 16 03:30:42 PM PDT 24
Peak memory 250788 kb
Host smart-12ac9f70-4b6d-472d-9526-256b10791ec2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370278388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_
jtag_state_post_trans.370278388
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3552508553
Short name T13
Test name
Test status
Simulation time 232484828 ps
CPU time 3.18 seconds
Started May 16 03:30:20 PM PDT 24
Finished May 16 03:30:34 PM PDT 24
Peak memory 217916 kb
Host smart-d00855e4-adc6-4048-b08d-84d374c24e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552508553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3552508553
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3482152388
Short name T267
Test name
Test status
Simulation time 1283970700 ps
CPU time 11.17 seconds
Started May 16 03:30:25 PM PDT 24
Finished May 16 03:30:47 PM PDT 24
Peak memory 225620 kb
Host smart-39376729-ae40-4b7d-ad2f-9b1353af90c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482152388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3482152388
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.3597765635
Short name T564
Test name
Test status
Simulation time 1194110847 ps
CPU time 11.02 seconds
Started May 16 03:30:24 PM PDT 24
Finished May 16 03:30:45 PM PDT 24
Peak memory 217772 kb
Host smart-94ef3ec3-de65-4c44-aed6-176d4cbe99ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597765635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.3597765635
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.4149850391
Short name T551
Test name
Test status
Simulation time 2699840881 ps
CPU time 12.73 seconds
Started May 16 03:30:24 PM PDT 24
Finished May 16 03:30:47 PM PDT 24
Peak memory 218048 kb
Host smart-f9251c85-ed92-40d2-ac41-5fbf3cb6e364
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149850391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
4149850391
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1151936950
Short name T598
Test name
Test status
Simulation time 1577770104 ps
CPU time 11.04 seconds
Started May 16 03:30:18 PM PDT 24
Finished May 16 03:30:40 PM PDT 24
Peak memory 218004 kb
Host smart-29fbdc83-4182-49d3-b8a5-8af8ef3a8a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151936950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1151936950
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1346114841
Short name T387
Test name
Test status
Simulation time 107472061 ps
CPU time 1.58 seconds
Started May 16 03:30:18 PM PDT 24
Finished May 16 03:30:31 PM PDT 24
Peak memory 213588 kb
Host smart-078d8871-da58-4d5e-950d-4fac0869d92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346114841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1346114841
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1434147976
Short name T311
Test name
Test status
Simulation time 393434476 ps
CPU time 25.5 seconds
Started May 16 03:30:18 PM PDT 24
Finished May 16 03:30:54 PM PDT 24
Peak memory 250864 kb
Host smart-3e29f09a-7e96-46d0-84db-e436154052ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434147976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1434147976
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.89169475
Short name T678
Test name
Test status
Simulation time 68563391 ps
CPU time 6.72 seconds
Started May 16 03:30:19 PM PDT 24
Finished May 16 03:30:36 PM PDT 24
Peak memory 246556 kb
Host smart-789cc7fc-0619-4a00-b758-1a0811f4de33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89169475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.89169475
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2234920579
Short name T852
Test name
Test status
Simulation time 1553314101 ps
CPU time 49.89 seconds
Started May 16 03:30:33 PM PDT 24
Finished May 16 03:31:32 PM PDT 24
Peak memory 250636 kb
Host smart-101d5d8b-4a65-4cb5-9c74-8635eff199cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234920579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2234920579
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.1037620167
Short name T183
Test name
Test status
Simulation time 149208897135 ps
CPU time 1295.96 seconds
Started May 16 03:30:23 PM PDT 24
Finished May 16 03:52:09 PM PDT 24
Peak memory 300100 kb
Host smart-b88917ec-9c48-495d-8601-f6f0240c00d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1037620167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.1037620167
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2476664682
Short name T279
Test name
Test status
Simulation time 20956156 ps
CPU time 0.97 seconds
Started May 16 03:30:16 PM PDT 24
Finished May 16 03:30:28 PM PDT 24
Peak memory 211488 kb
Host smart-75b24d7c-21a1-4770-8b18-b4f6a77ab820
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476664682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.2476664682
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.736300477
Short name T381
Test name
Test status
Simulation time 56721487 ps
CPU time 1.09 seconds
Started May 16 03:30:29 PM PDT 24
Finished May 16 03:30:41 PM PDT 24
Peak memory 209460 kb
Host smart-2f5a5dc6-5abd-4c3b-b9e9-d5dfc848bf08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736300477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.736300477
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1275167774
Short name T622
Test name
Test status
Simulation time 1012240731 ps
CPU time 14.44 seconds
Started May 16 03:30:25 PM PDT 24
Finished May 16 03:30:50 PM PDT 24
Peak memory 217772 kb
Host smart-d7a3a3b8-26cb-41a7-873e-5cdb2c84ff96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275167774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1275167774
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.554059940
Short name T354
Test name
Test status
Simulation time 288966497 ps
CPU time 4.1 seconds
Started May 16 03:30:24 PM PDT 24
Finished May 16 03:30:39 PM PDT 24
Peak memory 209420 kb
Host smart-f06eb1f6-4408-4f4a-ae91-b300aa590eda
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554059940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.554059940
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1052007609
Short name T360
Test name
Test status
Simulation time 2228155079 ps
CPU time 31.64 seconds
Started May 16 03:30:22 PM PDT 24
Finished May 16 03:31:04 PM PDT 24
Peak memory 217924 kb
Host smart-3fd89c9d-164b-4dd6-b8f1-fa5c5d36f484
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052007609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1052007609
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.911268794
Short name T606
Test name
Test status
Simulation time 150744182 ps
CPU time 3.86 seconds
Started May 16 03:30:24 PM PDT 24
Finished May 16 03:30:38 PM PDT 24
Peak memory 217896 kb
Host smart-b0808e31-3c6d-486f-921e-affc16bc94b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911268794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag
_prog_failure.911268794
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.380549730
Short name T826
Test name
Test status
Simulation time 412011361 ps
CPU time 10.4 seconds
Started May 16 03:30:33 PM PDT 24
Finished May 16 03:30:53 PM PDT 24
Peak memory 213304 kb
Host smart-c5077bfe-0374-42cc-8b02-71e3a145baae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380549730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
380549730
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2105074149
Short name T562
Test name
Test status
Simulation time 5979034528 ps
CPU time 32.16 seconds
Started May 16 03:30:20 PM PDT 24
Finished May 16 03:31:02 PM PDT 24
Peak memory 253724 kb
Host smart-9d482772-38e6-4c7d-99b0-df8b6be238ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105074149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2105074149
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.2153405672
Short name T589
Test name
Test status
Simulation time 2496874016 ps
CPU time 12.25 seconds
Started May 16 03:30:23 PM PDT 24
Finished May 16 03:30:45 PM PDT 24
Peak memory 245308 kb
Host smart-37d3dc74-0fe9-4764-875c-344c3bb27ba0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153405672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.2153405672
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1435773630
Short name T547
Test name
Test status
Simulation time 69496657 ps
CPU time 1.51 seconds
Started May 16 03:30:22 PM PDT 24
Finished May 16 03:30:34 PM PDT 24
Peak memory 217868 kb
Host smart-77e64363-ce1c-49c2-bc3f-51363d0c34b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435773630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1435773630
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.1592738146
Short name T325
Test name
Test status
Simulation time 974861021 ps
CPU time 16.33 seconds
Started May 16 03:30:24 PM PDT 24
Finished May 16 03:30:51 PM PDT 24
Peak memory 225976 kb
Host smart-ffe703a8-3b2d-45c8-ad8e-eab0b487dc1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592738146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.1592738146
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1477724423
Short name T340
Test name
Test status
Simulation time 1875313610 ps
CPU time 12.51 seconds
Started May 16 03:30:23 PM PDT 24
Finished May 16 03:30:46 PM PDT 24
Peak memory 217896 kb
Host smart-360f112a-6842-4579-aee8-d0febcc62499
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477724423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1477724423
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.559849699
Short name T274
Test name
Test status
Simulation time 305311466 ps
CPU time 10.11 seconds
Started May 16 03:30:23 PM PDT 24
Finished May 16 03:30:44 PM PDT 24
Peak memory 217816 kb
Host smart-27dbf98f-d29f-4147-bb51-32fc3316f407
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559849699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.559849699
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3508074421
Short name T47
Test name
Test status
Simulation time 1258939118 ps
CPU time 8.18 seconds
Started May 16 03:30:26 PM PDT 24
Finished May 16 03:30:45 PM PDT 24
Peak memory 217932 kb
Host smart-d90ea50e-c032-48ef-8ab5-e8b61013dfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508074421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3508074421
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.4053057244
Short name T407
Test name
Test status
Simulation time 27633965 ps
CPU time 2.37 seconds
Started May 16 03:30:23 PM PDT 24
Finished May 16 03:30:36 PM PDT 24
Peak memory 214196 kb
Host smart-19066120-7d6e-49ae-93eb-2e3c23fdc97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053057244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.4053057244
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2122624487
Short name T735
Test name
Test status
Simulation time 7305919415 ps
CPU time 30.04 seconds
Started May 16 03:30:33 PM PDT 24
Finished May 16 03:31:12 PM PDT 24
Peak memory 250964 kb
Host smart-a4ee793a-5e4b-433c-9bb3-7b7724a0fb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122624487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2122624487
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3898965140
Short name T545
Test name
Test status
Simulation time 58293496 ps
CPU time 8.43 seconds
Started May 16 03:30:22 PM PDT 24
Finished May 16 03:30:41 PM PDT 24
Peak memory 250840 kb
Host smart-caea9291-39cf-4d18-909f-597e0c738c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898965140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3898965140
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.1159803553
Short name T89
Test name
Test status
Simulation time 9775738356 ps
CPU time 203.76 seconds
Started May 16 03:30:32 PM PDT 24
Finished May 16 03:34:05 PM PDT 24
Peak memory 283736 kb
Host smart-1c989e4a-4ac0-40db-bf78-7de679e6a078
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159803553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.1159803553
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.4187953246
Short name T408
Test name
Test status
Simulation time 14026583 ps
CPU time 1.06 seconds
Started May 16 03:30:25 PM PDT 24
Finished May 16 03:30:37 PM PDT 24
Peak memory 211536 kb
Host smart-e9c98dc5-3fc5-4297-8503-d1d580336204
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187953246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.4187953246
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3735575772
Short name T759
Test name
Test status
Simulation time 17211498 ps
CPU time 0.95 seconds
Started May 16 03:30:32 PM PDT 24
Finished May 16 03:30:42 PM PDT 24
Peak memory 209448 kb
Host smart-f61e96fa-c57d-4181-9a44-662a3d767003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735575772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3735575772
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3042931569
Short name T280
Test name
Test status
Simulation time 5068553787 ps
CPU time 19.91 seconds
Started May 16 03:30:32 PM PDT 24
Finished May 16 03:31:01 PM PDT 24
Peak memory 218896 kb
Host smart-b03f7a41-2362-4090-852c-766cd8c0171a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042931569 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3042931569
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.593748476
Short name T681
Test name
Test status
Simulation time 373976272 ps
CPU time 1.96 seconds
Started May 16 03:30:32 PM PDT 24
Finished May 16 03:30:43 PM PDT 24
Peak memory 209400 kb
Host smart-b299cb41-d32c-4508-9a96-2d1104bf108e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593748476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.593748476
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.3664421116
Short name T173
Test name
Test status
Simulation time 2618075995 ps
CPU time 39.45 seconds
Started May 16 03:30:29 PM PDT 24
Finished May 16 03:31:19 PM PDT 24
Peak memory 218852 kb
Host smart-031f2100-d583-4a22-89f9-66fcd021dc7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664421116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.3664421116
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2401370000
Short name T337
Test name
Test status
Simulation time 529518562 ps
CPU time 13.6 seconds
Started May 16 03:30:36 PM PDT 24
Finished May 16 03:30:58 PM PDT 24
Peak memory 213712 kb
Host smart-e17f8d5b-6fdb-4c81-bc91-41ba66333fbb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401370000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2401370000
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3699254427
Short name T296
Test name
Test status
Simulation time 6647990412 ps
CPU time 68.3 seconds
Started May 16 03:30:32 PM PDT 24
Finished May 16 03:31:49 PM PDT 24
Peak memory 270748 kb
Host smart-de3ca11a-7f33-4646-a3d9-c7c9ac6b3c85
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699254427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3699254427
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1106718829
Short name T388
Test name
Test status
Simulation time 326493123 ps
CPU time 11.36 seconds
Started May 16 03:30:38 PM PDT 24
Finished May 16 03:30:57 PM PDT 24
Peak memory 222888 kb
Host smart-cb13c342-69c1-4ccd-be6a-79e37011859b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106718829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1106718829
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.819463428
Short name T814
Test name
Test status
Simulation time 316218503 ps
CPU time 4.79 seconds
Started May 16 03:30:31 PM PDT 24
Finished May 16 03:30:46 PM PDT 24
Peak memory 217896 kb
Host smart-b45dfc10-79a3-4415-b27b-548d5500b5bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819463428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.819463428
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.13220454
Short name T571
Test name
Test status
Simulation time 384897575 ps
CPU time 16.8 seconds
Started May 16 03:30:31 PM PDT 24
Finished May 16 03:30:57 PM PDT 24
Peak memory 218852 kb
Host smart-e1114e73-42a4-467c-a12b-7717a4665c58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13220454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.13220454
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.71302518
Short name T57
Test name
Test status
Simulation time 2955128225 ps
CPU time 11.46 seconds
Started May 16 03:30:33 PM PDT 24
Finished May 16 03:30:53 PM PDT 24
Peak memory 217984 kb
Host smart-fddde27c-bb23-4db1-9aaa-f3ba3ab982a8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71302518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_dig
est.71302518
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.2831878677
Short name T170
Test name
Test status
Simulation time 1691990294 ps
CPU time 11.09 seconds
Started May 16 03:30:29 PM PDT 24
Finished May 16 03:30:50 PM PDT 24
Peak memory 217864 kb
Host smart-29598f62-4278-4b1d-84ff-99bd10646986
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831878677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
2831878677
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.3764071574
Short name T513
Test name
Test status
Simulation time 935208136 ps
CPU time 6.11 seconds
Started May 16 03:30:36 PM PDT 24
Finished May 16 03:30:51 PM PDT 24
Peak memory 217848 kb
Host smart-748062f6-5d59-485d-be1e-26f672056af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764071574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.3764071574
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.3187970855
Short name T760
Test name
Test status
Simulation time 666312197 ps
CPU time 4.2 seconds
Started May 16 03:30:36 PM PDT 24
Finished May 16 03:30:49 PM PDT 24
Peak memory 217844 kb
Host smart-a57cc597-0c06-4e08-a15a-076ba0b3c2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187970855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.3187970855
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3193835673
Short name T400
Test name
Test status
Simulation time 361093563 ps
CPU time 18.01 seconds
Started May 16 03:30:30 PM PDT 24
Finished May 16 03:30:58 PM PDT 24
Peak memory 250760 kb
Host smart-203d9223-f6a0-4338-a327-345211fb93fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193835673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3193835673
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2712329512
Short name T726
Test name
Test status
Simulation time 42801921 ps
CPU time 2.52 seconds
Started May 16 03:30:30 PM PDT 24
Finished May 16 03:30:42 PM PDT 24
Peak memory 222128 kb
Host smart-3b030afd-787c-4f45-bb46-2bc435b4b403
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712329512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2712329512
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.1854740226
Short name T383
Test name
Test status
Simulation time 18028202287 ps
CPU time 19.35 seconds
Started May 16 03:30:31 PM PDT 24
Finished May 16 03:31:00 PM PDT 24
Peak memory 226044 kb
Host smart-9d1b433c-693c-454f-b8a6-137e0a9dc17b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854740226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.1854740226
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.357923588
Short name T821
Test name
Test status
Simulation time 18959385 ps
CPU time 1 seconds
Started May 16 03:30:32 PM PDT 24
Finished May 16 03:30:42 PM PDT 24
Peak memory 211520 kb
Host smart-66886b5f-7cbc-4a2c-bec9-8a4a984b79a2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357923588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ct
rl_volatile_unlock_smoke.357923588
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.391584089
Short name T256
Test name
Test status
Simulation time 100004386 ps
CPU time 0.99 seconds
Started May 16 03:30:41 PM PDT 24
Finished May 16 03:30:51 PM PDT 24
Peak memory 209428 kb
Host smart-9f839c9b-691d-433a-8c41-0c15deefd531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391584089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.391584089
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1950375753
Short name T257
Test name
Test status
Simulation time 458799667 ps
CPU time 8.17 seconds
Started May 16 03:30:32 PM PDT 24
Finished May 16 03:30:49 PM PDT 24
Peak memory 217776 kb
Host smart-b6206ba0-995b-4107-a923-fb4888727889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950375753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1950375753
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3566865986
Short name T773
Test name
Test status
Simulation time 530290901 ps
CPU time 14.09 seconds
Started May 16 03:30:29 PM PDT 24
Finished May 16 03:30:53 PM PDT 24
Peak memory 209376 kb
Host smart-80ea4e6c-69e7-4934-8ab9-7151ac959808
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566865986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3566865986
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2533357232
Short name T437
Test name
Test status
Simulation time 18580071222 ps
CPU time 66.72 seconds
Started May 16 03:30:29 PM PDT 24
Finished May 16 03:31:46 PM PDT 24
Peak memory 218792 kb
Host smart-09cb6692-8da4-4296-bb7e-abf3925ec431
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533357232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2533357232
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.205179349
Short name T798
Test name
Test status
Simulation time 841729935 ps
CPU time 11.4 seconds
Started May 16 03:30:29 PM PDT 24
Finished May 16 03:30:50 PM PDT 24
Peak memory 217820 kb
Host smart-1a97f2be-c6f4-44dc-8c09-4217463e2ecf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205179349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.205179349
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1278686432
Short name T717
Test name
Test status
Simulation time 1043356955 ps
CPU time 8.23 seconds
Started May 16 03:30:29 PM PDT 24
Finished May 16 03:30:47 PM PDT 24
Peak memory 213708 kb
Host smart-8116ddf9-ab8f-4cbe-8180-eb301dbb39cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278686432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1278686432
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1745774546
Short name T235
Test name
Test status
Simulation time 1162830042 ps
CPU time 39.15 seconds
Started May 16 03:30:36 PM PDT 24
Finished May 16 03:31:24 PM PDT 24
Peak memory 250864 kb
Host smart-721029fb-16b9-4047-9e99-a3561d87ccda
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745774546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1745774546
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.4138422649
Short name T445
Test name
Test status
Simulation time 657291382 ps
CPU time 13.6 seconds
Started May 16 03:30:38 PM PDT 24
Finished May 16 03:30:59 PM PDT 24
Peak memory 246108 kb
Host smart-69f40063-04ec-48ce-8568-29fcf69a57bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138422649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.4138422649
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1707410225
Short name T573
Test name
Test status
Simulation time 80103970 ps
CPU time 2.25 seconds
Started May 16 03:30:30 PM PDT 24
Finished May 16 03:30:42 PM PDT 24
Peak memory 217876 kb
Host smart-0f6aba5a-c191-42d6-ba15-09bbf50e542d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707410225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1707410225
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.983536076
Short name T546
Test name
Test status
Simulation time 876161581 ps
CPU time 9.34 seconds
Started May 16 03:30:29 PM PDT 24
Finished May 16 03:30:48 PM PDT 24
Peak memory 225860 kb
Host smart-4101fd96-77f8-484b-9f72-64949f82a4fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983536076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.983536076
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1890955151
Short name T502
Test name
Test status
Simulation time 1063591261 ps
CPU time 11.41 seconds
Started May 16 03:30:39 PM PDT 24
Finished May 16 03:30:59 PM PDT 24
Peak memory 225856 kb
Host smart-59cd86e5-bf53-431f-856a-c7a3e4cfca1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890955151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1890955151
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.449458295
Short name T613
Test name
Test status
Simulation time 334677865 ps
CPU time 8.66 seconds
Started May 16 03:30:29 PM PDT 24
Finished May 16 03:30:48 PM PDT 24
Peak memory 217844 kb
Host smart-8a459bb6-56c2-4952-924b-406ded618e5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449458295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.449458295
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3102188398
Short name T768
Test name
Test status
Simulation time 5220934005 ps
CPU time 8.88 seconds
Started May 16 03:30:29 PM PDT 24
Finished May 16 03:30:48 PM PDT 24
Peak memory 218076 kb
Host smart-8531d0bd-fb28-445f-9644-664518a98693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102188398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3102188398
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.634773145
Short name T448
Test name
Test status
Simulation time 14702284 ps
CPU time 1.43 seconds
Started May 16 03:30:33 PM PDT 24
Finished May 16 03:30:44 PM PDT 24
Peak memory 213124 kb
Host smart-5d3abfb8-85d7-4a90-847a-1e5e1e4717e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634773145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.634773145
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3738008081
Short name T648
Test name
Test status
Simulation time 344180742 ps
CPU time 36.09 seconds
Started May 16 03:30:33 PM PDT 24
Finished May 16 03:31:19 PM PDT 24
Peak memory 250848 kb
Host smart-1b817a68-d603-49e2-9244-fed522f171bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738008081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3738008081
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2701346455
Short name T286
Test name
Test status
Simulation time 91762273 ps
CPU time 10.02 seconds
Started May 16 03:30:28 PM PDT 24
Finished May 16 03:30:48 PM PDT 24
Peak memory 250828 kb
Host smart-e00cd307-c012-442a-99b0-1872d944c0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701346455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2701346455
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1323052261
Short name T461
Test name
Test status
Simulation time 12051729 ps
CPU time 0.87 seconds
Started May 16 03:30:30 PM PDT 24
Finished May 16 03:30:41 PM PDT 24
Peak memory 211396 kb
Host smart-1ed22cfa-8147-4e44-88c5-f985fe3cd2f7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323052261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.1323052261
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.4229020779
Short name T616
Test name
Test status
Simulation time 40118340 ps
CPU time 0.98 seconds
Started May 16 03:29:32 PM PDT 24
Finished May 16 03:29:41 PM PDT 24
Peak memory 209508 kb
Host smart-6e683fd9-3dda-463b-8c68-47e03d98dd6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229020779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.4229020779
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3130368559
Short name T835
Test name
Test status
Simulation time 2450140586 ps
CPU time 15.52 seconds
Started May 16 03:29:31 PM PDT 24
Finished May 16 03:29:55 PM PDT 24
Peak memory 217976 kb
Host smart-52d52484-24aa-4b55-9c20-ecdcadd0049b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130368559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3130368559
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.3137623414
Short name T7
Test name
Test status
Simulation time 31945141 ps
CPU time 1.52 seconds
Started May 16 03:29:33 PM PDT 24
Finished May 16 03:29:42 PM PDT 24
Peak memory 209280 kb
Host smart-f0a8a17b-a542-47ca-82ce-22f0562eea96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137623414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.3137623414
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.3616687500
Short name T603
Test name
Test status
Simulation time 15569678771 ps
CPU time 106.82 seconds
Started May 16 03:29:29 PM PDT 24
Finished May 16 03:31:24 PM PDT 24
Peak memory 219592 kb
Host smart-1d50fc76-c562-4c4e-8504-5f38de56937a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616687500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.3616687500
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.565571371
Short name T373
Test name
Test status
Simulation time 885189053 ps
CPU time 7.84 seconds
Started May 16 03:29:31 PM PDT 24
Finished May 16 03:29:46 PM PDT 24
Peak memory 216868 kb
Host smart-668e6719-613e-483a-8192-605a94882090
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565571371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.565571371
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3730639833
Short name T686
Test name
Test status
Simulation time 937194817 ps
CPU time 7.07 seconds
Started May 16 03:29:35 PM PDT 24
Finished May 16 03:29:48 PM PDT 24
Peak memory 217884 kb
Host smart-773d2e13-32a3-4a04-979c-c71e5f1a2d63
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730639833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3730639833
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1421010879
Short name T655
Test name
Test status
Simulation time 6149851547 ps
CPU time 24.19 seconds
Started May 16 03:29:31 PM PDT 24
Finished May 16 03:30:03 PM PDT 24
Peak memory 213868 kb
Host smart-88fb0982-afae-4780-a567-defece6a117c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421010879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1421010879
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3685351122
Short name T80
Test name
Test status
Simulation time 410379126 ps
CPU time 2.33 seconds
Started May 16 03:29:30 PM PDT 24
Finished May 16 03:29:41 PM PDT 24
Peak memory 212944 kb
Host smart-e44c8ead-662b-47ba-bf2a-41072248b0b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685351122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3685351122
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.275198323
Short name T28
Test name
Test status
Simulation time 3230694484 ps
CPU time 67.22 seconds
Started May 16 03:29:37 PM PDT 24
Finished May 16 03:30:50 PM PDT 24
Peak memory 267412 kb
Host smart-b5e4dc32-ea0e-4b57-a676-d09835a06fc6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275198323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.275198323
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1584792019
Short name T590
Test name
Test status
Simulation time 315927584 ps
CPU time 9.95 seconds
Started May 16 03:29:30 PM PDT 24
Finished May 16 03:29:48 PM PDT 24
Peak memory 221696 kb
Host smart-c33adf7d-c17c-4bb1-a5a4-5ddfe98c3713
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584792019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1584792019
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3081652158
Short name T466
Test name
Test status
Simulation time 143387694 ps
CPU time 2.9 seconds
Started May 16 03:29:30 PM PDT 24
Finished May 16 03:29:41 PM PDT 24
Peak memory 217864 kb
Host smart-9cba726c-d686-4aba-8dd6-8e541db8eca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081652158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3081652158
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1651803834
Short name T488
Test name
Test status
Simulation time 348966695 ps
CPU time 23.2 seconds
Started May 16 03:29:31 PM PDT 24
Finished May 16 03:30:02 PM PDT 24
Peak memory 217644 kb
Host smart-ada833ce-83cd-400c-9bde-4cfb75cda385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651803834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1651803834
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2360551580
Short name T863
Test name
Test status
Simulation time 324415634 ps
CPU time 15.84 seconds
Started May 16 03:29:30 PM PDT 24
Finished May 16 03:29:54 PM PDT 24
Peak memory 218780 kb
Host smart-632f27fe-b0fd-44e4-9eac-ad5f779a79ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360551580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2360551580
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.2211057564
Short name T637
Test name
Test status
Simulation time 393603609 ps
CPU time 10.5 seconds
Started May 16 03:29:31 PM PDT 24
Finished May 16 03:29:50 PM PDT 24
Peak memory 217860 kb
Host smart-6f1fc0af-d129-46d5-808f-20d41c32f715
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211057564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.2211057564
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3735273887
Short name T631
Test name
Test status
Simulation time 805850096 ps
CPU time 9.41 seconds
Started May 16 03:29:35 PM PDT 24
Finished May 16 03:29:51 PM PDT 24
Peak memory 217872 kb
Host smart-6e1fe246-b9d9-4945-887a-c6990d9d7cfb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735273887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
735273887
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2427559517
Short name T721
Test name
Test status
Simulation time 606197317 ps
CPU time 11.69 seconds
Started May 16 03:29:35 PM PDT 24
Finished May 16 03:29:53 PM PDT 24
Peak memory 217960 kb
Host smart-8a4d7b3e-db30-4e65-8d4e-de4c0be5e68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427559517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2427559517
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1433016745
Short name T385
Test name
Test status
Simulation time 21537936 ps
CPU time 1.29 seconds
Started May 16 03:29:26 PM PDT 24
Finished May 16 03:29:32 PM PDT 24
Peak memory 213264 kb
Host smart-7dfd837f-edff-4833-8623-aa13490d275d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433016745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1433016745
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.3134919516
Short name T369
Test name
Test status
Simulation time 157900025 ps
CPU time 15.54 seconds
Started May 16 03:29:22 PM PDT 24
Finished May 16 03:29:44 PM PDT 24
Peak memory 250580 kb
Host smart-012ea3c1-165d-4729-8825-ec4364ebdd64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134919516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.3134919516
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.530985352
Short name T850
Test name
Test status
Simulation time 865762993 ps
CPU time 7.2 seconds
Started May 16 03:29:31 PM PDT 24
Finished May 16 03:29:47 PM PDT 24
Peak memory 246684 kb
Host smart-79e5b641-08db-4569-a109-f2e14929860a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530985352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.530985352
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1890773603
Short name T659
Test name
Test status
Simulation time 92243516479 ps
CPU time 476.27 seconds
Started May 16 03:29:29 PM PDT 24
Finished May 16 03:37:33 PM PDT 24
Peak memory 513128 kb
Host smart-9f582f0f-1cd8-4142-9028-91c4983dbd64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890773603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1890773603
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3317457392
Short name T416
Test name
Test status
Simulation time 12600797 ps
CPU time 0.93 seconds
Started May 16 03:29:27 PM PDT 24
Finished May 16 03:29:35 PM PDT 24
Peak memory 211504 kb
Host smart-4ab71496-ce42-4ba4-b89a-d5a1dce16b3c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317457392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3317457392
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.272238890
Short name T260
Test name
Test status
Simulation time 22275417 ps
CPU time 0.87 seconds
Started May 16 03:30:41 PM PDT 24
Finished May 16 03:30:51 PM PDT 24
Peak memory 209360 kb
Host smart-87453690-9872-4ae9-9c27-f2ecaaa6c06e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272238890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.272238890
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.556334501
Short name T799
Test name
Test status
Simulation time 2059033355 ps
CPU time 10.32 seconds
Started May 16 03:30:37 PM PDT 24
Finished May 16 03:30:56 PM PDT 24
Peak memory 217804 kb
Host smart-f6ab116b-93c5-4191-9318-e46d088e4ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556334501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.556334501
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.1506506305
Short name T876
Test name
Test status
Simulation time 1670911366 ps
CPU time 10.81 seconds
Started May 16 03:30:43 PM PDT 24
Finished May 16 03:31:03 PM PDT 24
Peak memory 209452 kb
Host smart-54173765-f316-4bef-976d-fc4d8fc0fb68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506506305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1506506305
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1687600176
Short name T816
Test name
Test status
Simulation time 50124925 ps
CPU time 2.57 seconds
Started May 16 03:30:40 PM PDT 24
Finished May 16 03:30:51 PM PDT 24
Peak memory 217768 kb
Host smart-3aa692b0-aa9f-4cbe-bec4-5c6f8d69b671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687600176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1687600176
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.896817015
Short name T409
Test name
Test status
Simulation time 884986927 ps
CPU time 12.9 seconds
Started May 16 03:30:41 PM PDT 24
Finished May 16 03:31:03 PM PDT 24
Peak memory 226040 kb
Host smart-f3b2ce23-726d-474c-8e35-15bb0701a211
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896817015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.896817015
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.291221470
Short name T539
Test name
Test status
Simulation time 960117810 ps
CPU time 13.38 seconds
Started May 16 03:30:38 PM PDT 24
Finished May 16 03:31:00 PM PDT 24
Peak memory 217828 kb
Host smart-9d9dcc9d-fc14-4b48-a791-405d277b8adb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291221470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.291221470
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.4128061423
Short name T839
Test name
Test status
Simulation time 2120350033 ps
CPU time 10.69 seconds
Started May 16 03:30:39 PM PDT 24
Finished May 16 03:30:58 PM PDT 24
Peak memory 217908 kb
Host smart-1e547305-b688-4fee-adea-b6fe628939c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128061423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
4128061423
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3863990215
Short name T310
Test name
Test status
Simulation time 1811575070 ps
CPU time 14.44 seconds
Started May 16 03:30:40 PM PDT 24
Finished May 16 03:31:03 PM PDT 24
Peak memory 217916 kb
Host smart-2fe0bd0e-c937-47f5-b64c-61bed2d0925c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863990215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3863990215
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.927721893
Short name T746
Test name
Test status
Simulation time 252548608 ps
CPU time 3.45 seconds
Started May 16 03:30:39 PM PDT 24
Finished May 16 03:30:51 PM PDT 24
Peak memory 214256 kb
Host smart-8c616196-5a1c-45e1-b801-2f2470ac46e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927721893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.927721893
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.4118238680
Short name T548
Test name
Test status
Simulation time 389626418 ps
CPU time 33.5 seconds
Started May 16 03:30:39 PM PDT 24
Finished May 16 03:31:20 PM PDT 24
Peak memory 250844 kb
Host smart-2241df2b-5985-4f7c-8569-4831ade486c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118238680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.4118238680
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1414750129
Short name T869
Test name
Test status
Simulation time 106869412 ps
CPU time 4.02 seconds
Started May 16 03:30:44 PM PDT 24
Finished May 16 03:30:57 PM PDT 24
Peak memory 226256 kb
Host smart-5f1cffbc-98ba-4d0b-b7de-50c7cab9a8c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414750129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1414750129
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.19931079
Short name T777
Test name
Test status
Simulation time 23578868772 ps
CPU time 119.68 seconds
Started May 16 03:30:39 PM PDT 24
Finished May 16 03:32:47 PM PDT 24
Peak memory 250964 kb
Host smart-68563a9b-9c53-4e7a-97f4-7c0db249da0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19931079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2
0.lc_ctrl_stress_all.19931079
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.1758743730
Short name T751
Test name
Test status
Simulation time 167160287402 ps
CPU time 691.66 seconds
Started May 16 03:30:42 PM PDT 24
Finished May 16 03:42:23 PM PDT 24
Peak memory 343200 kb
Host smart-3cb819f3-0ff8-4805-a1f7-e79c3ba6cfc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1758743730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.1758743730
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2161837849
Short name T471
Test name
Test status
Simulation time 10701989 ps
CPU time 0.98 seconds
Started May 16 03:30:40 PM PDT 24
Finished May 16 03:30:50 PM PDT 24
Peak memory 211584 kb
Host smart-23875871-cce1-495c-b8f1-ea0b764284e5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161837849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2161837849
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.812059139
Short name T395
Test name
Test status
Simulation time 126948755 ps
CPU time 1.05 seconds
Started May 16 03:30:45 PM PDT 24
Finished May 16 03:30:55 PM PDT 24
Peak memory 209448 kb
Host smart-ec48811b-4fad-489f-8fe6-9ab8b61aef6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812059139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.812059139
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.568205091
Short name T479
Test name
Test status
Simulation time 194033645 ps
CPU time 10.06 seconds
Started May 16 03:30:38 PM PDT 24
Finished May 16 03:30:56 PM PDT 24
Peak memory 217912 kb
Host smart-48663c6e-5abe-4144-8185-3cc10f4b2720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568205091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.568205091
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.726431208
Short name T861
Test name
Test status
Simulation time 228474300 ps
CPU time 2.28 seconds
Started May 16 03:30:43 PM PDT 24
Finished May 16 03:30:54 PM PDT 24
Peak memory 216808 kb
Host smart-3d9fd62d-142e-49c7-b1f5-1a496b8b0c49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726431208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.726431208
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.1513706574
Short name T336
Test name
Test status
Simulation time 132153666 ps
CPU time 2.79 seconds
Started May 16 03:30:39 PM PDT 24
Finished May 16 03:30:50 PM PDT 24
Peak memory 217820 kb
Host smart-9fbc256c-1926-4c02-a522-b2e5f1bc2d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513706574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.1513706574
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.3182194477
Short name T624
Test name
Test status
Simulation time 586771463 ps
CPU time 25.35 seconds
Started May 16 03:30:39 PM PDT 24
Finished May 16 03:31:12 PM PDT 24
Peak memory 217812 kb
Host smart-26ef92c1-a1fd-42a9-8c1f-cfb47e954c74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182194477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.3182194477
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.2128175515
Short name T828
Test name
Test status
Simulation time 188870321 ps
CPU time 8.92 seconds
Started May 16 03:30:46 PM PDT 24
Finished May 16 03:31:04 PM PDT 24
Peak memory 217832 kb
Host smart-c388bfd7-0e77-4374-b283-edcf9b409f92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128175515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.2128175515
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3050705805
Short name T268
Test name
Test status
Simulation time 13855774668 ps
CPU time 15.79 seconds
Started May 16 03:30:47 PM PDT 24
Finished May 16 03:31:12 PM PDT 24
Peak memory 217984 kb
Host smart-3085e4ff-7c8b-4a77-a273-d1a8e161f764
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050705805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3050705805
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2885619275
Short name T499
Test name
Test status
Simulation time 1661958094 ps
CPU time 16 seconds
Started May 16 03:30:39 PM PDT 24
Finished May 16 03:31:03 PM PDT 24
Peak memory 225544 kb
Host smart-bfffca60-3893-4123-ba60-49dc96646a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885619275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2885619275
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.861317884
Short name T860
Test name
Test status
Simulation time 23250038 ps
CPU time 1.27 seconds
Started May 16 03:30:37 PM PDT 24
Finished May 16 03:30:47 PM PDT 24
Peak memory 213236 kb
Host smart-fbba769f-a556-4048-bb33-17193526fbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861317884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.861317884
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3146592278
Short name T332
Test name
Test status
Simulation time 177393460 ps
CPU time 23.97 seconds
Started May 16 03:30:39 PM PDT 24
Finished May 16 03:31:11 PM PDT 24
Peak memory 250840 kb
Host smart-baeddf57-c170-45aa-82d5-22a35a29e938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146592278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3146592278
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3208326346
Short name T473
Test name
Test status
Simulation time 430029034 ps
CPU time 3.33 seconds
Started May 16 03:30:42 PM PDT 24
Finished May 16 03:30:54 PM PDT 24
Peak memory 222236 kb
Host smart-a918b2d7-bcda-4b50-a613-83aef86ad785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208326346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3208326346
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.4128282319
Short name T82
Test name
Test status
Simulation time 16081461777 ps
CPU time 488.29 seconds
Started May 16 03:30:48 PM PDT 24
Finished May 16 03:39:06 PM PDT 24
Peak memory 480260 kb
Host smart-68a984ef-b0ee-4c8d-8fbb-87526f0f8fd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128282319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.4128282319
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.805060006
Short name T371
Test name
Test status
Simulation time 89843928 ps
CPU time 1.04 seconds
Started May 16 03:30:38 PM PDT 24
Finished May 16 03:30:48 PM PDT 24
Peak memory 211524 kb
Host smart-1db27fba-0174-46a2-8efe-886f6d56022a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805060006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.805060006
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.2306289121
Short name T587
Test name
Test status
Simulation time 44603614 ps
CPU time 1.22 seconds
Started May 16 03:30:47 PM PDT 24
Finished May 16 03:30:57 PM PDT 24
Peak memory 209436 kb
Host smart-59555eb7-0d97-4334-95b6-a175ef44da81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306289121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.2306289121
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3043979418
Short name T695
Test name
Test status
Simulation time 571287588 ps
CPU time 10.42 seconds
Started May 16 03:30:47 PM PDT 24
Finished May 16 03:31:07 PM PDT 24
Peak memory 217860 kb
Host smart-29dc96e9-88b6-4b27-a621-39bfbd05b66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043979418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3043979418
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.4056273793
Short name T462
Test name
Test status
Simulation time 184450772 ps
CPU time 5.71 seconds
Started May 16 03:30:46 PM PDT 24
Finished May 16 03:31:01 PM PDT 24
Peak memory 209464 kb
Host smart-e2495ddd-0d69-436c-8702-929f51a8a724
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056273793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.4056273793
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.31101986
Short name T277
Test name
Test status
Simulation time 60610543 ps
CPU time 2.4 seconds
Started May 16 03:30:45 PM PDT 24
Finished May 16 03:30:57 PM PDT 24
Peak memory 217844 kb
Host smart-ef90be46-fba7-4a90-8680-1132ae5fe56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31101986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.31101986
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.519120739
Short name T498
Test name
Test status
Simulation time 1281608941 ps
CPU time 13.87 seconds
Started May 16 03:30:45 PM PDT 24
Finished May 16 03:31:09 PM PDT 24
Peak memory 225956 kb
Host smart-d6520792-2340-49c3-a4a2-c6e937ca23ac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519120739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.519120739
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.2455963429
Short name T378
Test name
Test status
Simulation time 1110840095 ps
CPU time 23.08 seconds
Started May 16 03:30:46 PM PDT 24
Finished May 16 03:31:18 PM PDT 24
Peak memory 217824 kb
Host smart-1da8e9d0-b81b-4f70-a485-ff07477b8d9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455963429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.2455963429
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3014375426
Short name T745
Test name
Test status
Simulation time 1125837300 ps
CPU time 9.14 seconds
Started May 16 03:30:45 PM PDT 24
Finished May 16 03:31:04 PM PDT 24
Peak memory 217860 kb
Host smart-dfb09d55-79cf-475c-b201-f6500204ce94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014375426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3014375426
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.3882835178
Short name T748
Test name
Test status
Simulation time 49256996 ps
CPU time 3.65 seconds
Started May 16 03:30:46 PM PDT 24
Finished May 16 03:30:59 PM PDT 24
Peak memory 217616 kb
Host smart-632e3eff-3479-4382-9834-886b1a0d9e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882835178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.3882835178
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3353617092
Short name T191
Test name
Test status
Simulation time 535122881 ps
CPU time 20.89 seconds
Started May 16 03:30:46 PM PDT 24
Finished May 16 03:31:16 PM PDT 24
Peak memory 250876 kb
Host smart-6f665be9-c132-4406-9858-e1d7900a39b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353617092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3353617092
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1735886868
Short name T763
Test name
Test status
Simulation time 127169284 ps
CPU time 9.53 seconds
Started May 16 03:30:49 PM PDT 24
Finished May 16 03:31:07 PM PDT 24
Peak memory 250808 kb
Host smart-f4e85d7d-7863-4ea3-88e1-8e9424705fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735886868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1735886868
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1865569741
Short name T553
Test name
Test status
Simulation time 4596941925 ps
CPU time 117.99 seconds
Started May 16 03:30:48 PM PDT 24
Finished May 16 03:32:55 PM PDT 24
Peak memory 282684 kb
Host smart-69fecb1c-3301-42e7-a76b-d185e2b9767e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865569741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1865569741
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1502422767
Short name T742
Test name
Test status
Simulation time 43873006 ps
CPU time 0.84 seconds
Started May 16 03:30:47 PM PDT 24
Finished May 16 03:30:57 PM PDT 24
Peak memory 211480 kb
Host smart-6f9e3b87-d549-4fd6-bab8-ff08190c40a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502422767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.1502422767
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.3851896987
Short name T536
Test name
Test status
Simulation time 14753091 ps
CPU time 0.91 seconds
Started May 16 03:30:44 PM PDT 24
Finished May 16 03:30:54 PM PDT 24
Peak memory 209364 kb
Host smart-686d50d5-82da-4fb5-8783-717291488f40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851896987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.3851896987
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3919582143
Short name T724
Test name
Test status
Simulation time 387697170 ps
CPU time 15.44 seconds
Started May 16 03:30:48 PM PDT 24
Finished May 16 03:31:12 PM PDT 24
Peak memory 217836 kb
Host smart-f73efbe2-684f-447c-81fc-67bc6aa820d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919582143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3919582143
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2468394786
Short name T493
Test name
Test status
Simulation time 1998543903 ps
CPU time 6.35 seconds
Started May 16 03:30:44 PM PDT 24
Finished May 16 03:30:59 PM PDT 24
Peak memory 217028 kb
Host smart-065ca047-d1a3-49c4-a596-ccff55736cde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468394786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2468394786
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.4081355043
Short name T877
Test name
Test status
Simulation time 148334216 ps
CPU time 2.16 seconds
Started May 16 03:30:47 PM PDT 24
Finished May 16 03:30:58 PM PDT 24
Peak memory 217836 kb
Host smart-e883bac2-3659-44a3-ba75-65c020fb22d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081355043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.4081355043
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1496545378
Short name T592
Test name
Test status
Simulation time 362480100 ps
CPU time 13.15 seconds
Started May 16 03:30:46 PM PDT 24
Finished May 16 03:31:09 PM PDT 24
Peak memory 218056 kb
Host smart-6ef36dfb-540e-4d44-acd0-0468f4f02ac2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496545378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1496545378
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.1444537201
Short name T617
Test name
Test status
Simulation time 613285712 ps
CPU time 13.78 seconds
Started May 16 03:30:47 PM PDT 24
Finished May 16 03:31:10 PM PDT 24
Peak memory 217768 kb
Host smart-391ba98d-149e-43d8-925c-8da8ff38f6ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444537201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.1444537201
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2593968671
Short name T435
Test name
Test status
Simulation time 408033214 ps
CPU time 9.5 seconds
Started May 16 03:30:49 PM PDT 24
Finished May 16 03:31:07 PM PDT 24
Peak memory 217956 kb
Host smart-007161bc-5cd4-42f7-9ca2-cbb91d9c4ad6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593968671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2593968671
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.4269509493
Short name T774
Test name
Test status
Simulation time 1189278120 ps
CPU time 9.22 seconds
Started May 16 03:30:47 PM PDT 24
Finished May 16 03:31:05 PM PDT 24
Peak memory 217984 kb
Host smart-f10bf3ab-c7ee-4d0d-8d11-860ab3001990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269509493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.4269509493
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.3512654291
Short name T855
Test name
Test status
Simulation time 43501311 ps
CPU time 1.9 seconds
Started May 16 03:30:48 PM PDT 24
Finished May 16 03:30:59 PM PDT 24
Peak memory 213488 kb
Host smart-dc9cd94d-4aac-4a2e-9af3-00b32dbb2c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512654291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.3512654291
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3914632165
Short name T3
Test name
Test status
Simulation time 6377518777 ps
CPU time 32.22 seconds
Started May 16 03:30:47 PM PDT 24
Finished May 16 03:31:28 PM PDT 24
Peak memory 250964 kb
Host smart-67db7309-921b-4a33-ad5c-4cf60e205978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914632165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3914632165
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.113488889
Short name T708
Test name
Test status
Simulation time 117588586 ps
CPU time 7.75 seconds
Started May 16 03:30:46 PM PDT 24
Finished May 16 03:31:03 PM PDT 24
Peak memory 250792 kb
Host smart-8f06e3df-3123-47e9-9d07-9c16a62eb41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113488889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.113488889
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3100023199
Short name T465
Test name
Test status
Simulation time 11032878319 ps
CPU time 172.93 seconds
Started May 16 03:30:45 PM PDT 24
Finished May 16 03:33:48 PM PDT 24
Peak memory 267228 kb
Host smart-86bca1b1-4986-4a15-b6c2-ee3aff0f3f02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100023199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3100023199
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.731073771
Short name T853
Test name
Test status
Simulation time 44399986 ps
CPU time 0.96 seconds
Started May 16 03:30:49 PM PDT 24
Finished May 16 03:30:59 PM PDT 24
Peak memory 211404 kb
Host smart-ca0e97f5-c54d-44ba-94c0-9753d845b08d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731073771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ct
rl_volatile_unlock_smoke.731073771
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1472639182
Short name T425
Test name
Test status
Simulation time 166815464 ps
CPU time 1.06 seconds
Started May 16 03:30:57 PM PDT 24
Finished May 16 03:31:05 PM PDT 24
Peak memory 209416 kb
Host smart-ac13e741-00fd-421b-882f-1d77c421e280
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472639182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1472639182
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2897792104
Short name T247
Test name
Test status
Simulation time 826681308 ps
CPU time 15.81 seconds
Started May 16 03:30:48 PM PDT 24
Finished May 16 03:31:12 PM PDT 24
Peak memory 217768 kb
Host smart-1d766dc8-4776-43cc-93ef-d62bcf3068eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897792104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2897792104
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1803741594
Short name T878
Test name
Test status
Simulation time 878690182 ps
CPU time 3.2 seconds
Started May 16 03:30:48 PM PDT 24
Finished May 16 03:31:01 PM PDT 24
Peak memory 209528 kb
Host smart-e699b210-badc-42c5-b132-6dc3fdd6fb32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803741594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1803741594
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.2853003491
Short name T506
Test name
Test status
Simulation time 44541888 ps
CPU time 1.69 seconds
Started May 16 03:30:45 PM PDT 24
Finished May 16 03:30:56 PM PDT 24
Peak memory 217876 kb
Host smart-98820236-22ef-44cc-a8d6-8b3aa3d7cc23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853003491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2853003491
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.690676964
Short name T307
Test name
Test status
Simulation time 1670031819 ps
CPU time 13.31 seconds
Started May 16 03:30:47 PM PDT 24
Finished May 16 03:31:09 PM PDT 24
Peak memory 218788 kb
Host smart-7d0bf381-f14b-4167-b4bb-9ffcfe9c2ebd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690676964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.690676964
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2455324987
Short name T533
Test name
Test status
Simulation time 2139777671 ps
CPU time 19.49 seconds
Started May 16 03:30:50 PM PDT 24
Finished May 16 03:31:18 PM PDT 24
Peak memory 217884 kb
Host smart-38baab2e-75a2-4711-b6f2-43e7c07cdaf6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455324987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2455324987
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1772732404
Short name T242
Test name
Test status
Simulation time 1390647587 ps
CPU time 9.66 seconds
Started May 16 03:30:48 PM PDT 24
Finished May 16 03:31:07 PM PDT 24
Peak memory 217944 kb
Host smart-d1fa19af-43de-4218-ada1-d8dddb9f6433
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772732404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1772732404
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.351474800
Short name T349
Test name
Test status
Simulation time 470563020 ps
CPU time 8.66 seconds
Started May 16 03:30:48 PM PDT 24
Finished May 16 03:31:06 PM PDT 24
Peak memory 217948 kb
Host smart-73f7fe0a-3c86-45a0-b44c-7c27afce19b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351474800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.351474800
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2846716811
Short name T74
Test name
Test status
Simulation time 199577342 ps
CPU time 2.51 seconds
Started May 16 03:30:48 PM PDT 24
Finished May 16 03:31:00 PM PDT 24
Peak memory 213956 kb
Host smart-210e4fa2-feaf-4a57-86d4-348bea2dfa98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846716811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2846716811
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1005407576
Short name T700
Test name
Test status
Simulation time 697737637 ps
CPU time 29.27 seconds
Started May 16 03:30:46 PM PDT 24
Finished May 16 03:31:25 PM PDT 24
Peak memory 250832 kb
Host smart-7feb50b6-aa04-439c-8853-791a9712f2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005407576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1005407576
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.4112567670
Short name T744
Test name
Test status
Simulation time 95812932 ps
CPU time 6.22 seconds
Started May 16 03:30:46 PM PDT 24
Finished May 16 03:31:02 PM PDT 24
Peak memory 250268 kb
Host smart-2dce9d75-ee91-4050-8e36-ceb0a9686bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112567670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.4112567670
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.628678800
Short name T61
Test name
Test status
Simulation time 4129422456 ps
CPU time 179.98 seconds
Started May 16 03:30:56 PM PDT 24
Finished May 16 03:34:03 PM PDT 24
Peak memory 250960 kb
Host smart-605ef0f6-d3af-4352-8e9c-9bbaa753881c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628678800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.628678800
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.3602648718
Short name T109
Test name
Test status
Simulation time 207780459949 ps
CPU time 843.35 seconds
Started May 16 03:30:58 PM PDT 24
Finished May 16 03:45:08 PM PDT 24
Peak memory 316556 kb
Host smart-38bae77d-7a36-43d7-a78e-b724a617d38b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3602648718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.3602648718
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3123031408
Short name T284
Test name
Test status
Simulation time 18746743 ps
CPU time 0.89 seconds
Started May 16 03:30:49 PM PDT 24
Finished May 16 03:30:58 PM PDT 24
Peak memory 211444 kb
Host smart-79a09507-cf06-4be8-afbe-60bd535e7f0c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123031408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3123031408
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.580038001
Short name T36
Test name
Test status
Simulation time 16833702 ps
CPU time 1.13 seconds
Started May 16 03:30:59 PM PDT 24
Finished May 16 03:31:07 PM PDT 24
Peak memory 209184 kb
Host smart-cc41cd54-f5ac-4e11-a8ed-ac33e4c97428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580038001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.580038001
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.234633543
Short name T264
Test name
Test status
Simulation time 1265748352 ps
CPU time 13.81 seconds
Started May 16 03:30:56 PM PDT 24
Finished May 16 03:31:17 PM PDT 24
Peak memory 217844 kb
Host smart-77020105-7f3f-441f-a192-a06bc64e1fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234633543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.234633543
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.3977677000
Short name T673
Test name
Test status
Simulation time 1888024263 ps
CPU time 12.86 seconds
Started May 16 03:30:57 PM PDT 24
Finished May 16 03:31:17 PM PDT 24
Peak memory 209404 kb
Host smart-e6d6f1d7-1146-41a5-8bbb-405a528fae8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977677000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.3977677000
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.47163657
Short name T299
Test name
Test status
Simulation time 174854254 ps
CPU time 3.17 seconds
Started May 16 03:31:01 PM PDT 24
Finished May 16 03:31:10 PM PDT 24
Peak memory 217836 kb
Host smart-00e1467c-9ec7-4ac7-b975-a391033445d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47163657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.47163657
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.3553511845
Short name T25
Test name
Test status
Simulation time 407980785 ps
CPU time 13.37 seconds
Started May 16 03:30:55 PM PDT 24
Finished May 16 03:31:16 PM PDT 24
Peak memory 217936 kb
Host smart-8c776f37-84a5-4f7d-a96f-e5ae55775ae1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553511845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3553511845
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3890939238
Short name T198
Test name
Test status
Simulation time 379654287 ps
CPU time 14.78 seconds
Started May 16 03:30:57 PM PDT 24
Finished May 16 03:31:19 PM PDT 24
Peak memory 225968 kb
Host smart-ec10ee80-d453-4d2c-a8a8-68076fa071a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890939238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3890939238
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.801101127
Short name T285
Test name
Test status
Simulation time 452576685 ps
CPU time 16.1 seconds
Started May 16 03:30:55 PM PDT 24
Finished May 16 03:31:19 PM PDT 24
Peak memory 217840 kb
Host smart-76976f22-6605-4996-8b82-6c638d7e450a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801101127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.801101127
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2428812904
Short name T691
Test name
Test status
Simulation time 113614780 ps
CPU time 4.99 seconds
Started May 16 03:30:58 PM PDT 24
Finished May 16 03:31:10 PM PDT 24
Peak memory 217716 kb
Host smart-1e369965-bc68-4ebf-8a7d-b0496c0a55a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428812904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2428812904
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.516628674
Short name T288
Test name
Test status
Simulation time 228393606 ps
CPU time 28.88 seconds
Started May 16 03:30:56 PM PDT 24
Finished May 16 03:31:32 PM PDT 24
Peak memory 250852 kb
Host smart-504e4a8e-e4ab-4e5d-85cc-0dddc6c6d364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516628674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.516628674
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.2108073001
Short name T636
Test name
Test status
Simulation time 356895313 ps
CPU time 9 seconds
Started May 16 03:30:58 PM PDT 24
Finished May 16 03:31:14 PM PDT 24
Peak memory 250836 kb
Host smart-84837773-581d-4f6f-bef4-c0a4bc5efbf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108073001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2108073001
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.979311946
Short name T580
Test name
Test status
Simulation time 4466287367 ps
CPU time 109.36 seconds
Started May 16 03:30:57 PM PDT 24
Finished May 16 03:32:53 PM PDT 24
Peak memory 234824 kb
Host smart-06dc288a-ec8e-4b43-8f0b-19d3898720d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979311946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.979311946
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.249753704
Short name T92
Test name
Test status
Simulation time 18602894761 ps
CPU time 360.71 seconds
Started May 16 03:30:55 PM PDT 24
Finished May 16 03:37:04 PM PDT 24
Peak memory 295432 kb
Host smart-a8afacaf-f9bb-49f3-831b-bc31c5f5663d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=249753704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_stress_all_with_rand_reset.249753704
Directory /workspace/25.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2236320277
Short name T646
Test name
Test status
Simulation time 23147294 ps
CPU time 0.97 seconds
Started May 16 03:30:56 PM PDT 24
Finished May 16 03:31:05 PM PDT 24
Peak memory 211432 kb
Host smart-f37eb465-9ae6-48d2-bba6-d9cbc006385e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236320277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2236320277
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2447564539
Short name T243
Test name
Test status
Simulation time 76634327 ps
CPU time 1.13 seconds
Started May 16 03:30:58 PM PDT 24
Finished May 16 03:31:06 PM PDT 24
Peak memory 209408 kb
Host smart-4c2cc24a-3fa3-4139-87e2-07a54b8a550c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447564539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2447564539
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1344091715
Short name T463
Test name
Test status
Simulation time 2048595767 ps
CPU time 9.58 seconds
Started May 16 03:30:58 PM PDT 24
Finished May 16 03:31:14 PM PDT 24
Peak memory 209532 kb
Host smart-4d3450ca-9da6-4aa6-978e-0bff280e1519
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344091715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1344091715
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.424221342
Short name T556
Test name
Test status
Simulation time 77314901 ps
CPU time 2.81 seconds
Started May 16 03:30:56 PM PDT 24
Finished May 16 03:31:06 PM PDT 24
Peak memory 217896 kb
Host smart-cd87a17f-daa3-4ba8-abd6-fba64035274f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424221342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.424221342
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.792660012
Short name T641
Test name
Test status
Simulation time 436158694 ps
CPU time 13.06 seconds
Started May 16 03:30:56 PM PDT 24
Finished May 16 03:31:17 PM PDT 24
Peak memory 225980 kb
Host smart-10204288-f49e-43a0-8f50-905eaa8bf890
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792660012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.792660012
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.149468565
Short name T418
Test name
Test status
Simulation time 5631534920 ps
CPU time 13.86 seconds
Started May 16 03:30:56 PM PDT 24
Finished May 16 03:31:18 PM PDT 24
Peak memory 218108 kb
Host smart-e4053c44-b62f-4351-ad50-047fb6f526a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149468565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_di
gest.149468565
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3872337545
Short name T443
Test name
Test status
Simulation time 434124608 ps
CPU time 10.94 seconds
Started May 16 03:30:57 PM PDT 24
Finished May 16 03:31:16 PM PDT 24
Peak memory 217956 kb
Host smart-5cd1a853-c92d-4295-8652-7fad216ad00e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872337545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3872337545
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.579626146
Short name T807
Test name
Test status
Simulation time 1675499777 ps
CPU time 10.41 seconds
Started May 16 03:30:54 PM PDT 24
Finished May 16 03:31:13 PM PDT 24
Peak memory 217908 kb
Host smart-98f499a9-bdfb-43d4-9fd4-873ba99c2e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579626146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.579626146
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.748579307
Short name T820
Test name
Test status
Simulation time 144758852 ps
CPU time 2.79 seconds
Started May 16 03:30:58 PM PDT 24
Finished May 16 03:31:08 PM PDT 24
Peak memory 214076 kb
Host smart-b563f16e-4b7d-433b-8db0-5f204def9d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748579307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.748579307
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3025754484
Short name T302
Test name
Test status
Simulation time 677294526 ps
CPU time 35.7 seconds
Started May 16 03:30:59 PM PDT 24
Finished May 16 03:31:41 PM PDT 24
Peak memory 250580 kb
Host smart-c7d14c75-30f9-4590-b8f0-bec48fdd7cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025754484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3025754484
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.1209716844
Short name T315
Test name
Test status
Simulation time 306601431 ps
CPU time 7.76 seconds
Started May 16 03:30:58 PM PDT 24
Finished May 16 03:31:13 PM PDT 24
Peak memory 250832 kb
Host smart-af25ce32-87ba-4541-84b3-827bac2045ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209716844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.1209716844
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2060735352
Short name T740
Test name
Test status
Simulation time 14560571664 ps
CPU time 100.89 seconds
Started May 16 03:30:56 PM PDT 24
Finished May 16 03:32:44 PM PDT 24
Peak memory 267768 kb
Host smart-84c32b76-6456-454d-a142-43a7409f5dcd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060735352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2060735352
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.3131578530
Short name T623
Test name
Test status
Simulation time 11620952 ps
CPU time 1.03 seconds
Started May 16 03:30:57 PM PDT 24
Finished May 16 03:31:06 PM PDT 24
Peak memory 211444 kb
Host smart-71582829-209e-476c-9ecc-5c5b911b46d6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131578530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.3131578530
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3900865514
Short name T298
Test name
Test status
Simulation time 105169652 ps
CPU time 1 seconds
Started May 16 03:31:06 PM PDT 24
Finished May 16 03:31:13 PM PDT 24
Peak memory 209468 kb
Host smart-b0271f26-35ad-4fc6-b1b1-a06956fb8772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900865514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3900865514
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3485564675
Short name T419
Test name
Test status
Simulation time 1251079196 ps
CPU time 14.61 seconds
Started May 16 03:30:55 PM PDT 24
Finished May 16 03:31:17 PM PDT 24
Peak memory 217920 kb
Host smart-ec6e9ca5-4116-44cd-8582-83cfdb822094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485564675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3485564675
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.3193650774
Short name T8
Test name
Test status
Simulation time 525119043 ps
CPU time 3.44 seconds
Started May 16 03:30:58 PM PDT 24
Finished May 16 03:31:08 PM PDT 24
Peak memory 216816 kb
Host smart-18ec2910-bc63-4a73-8904-000767363235
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193650774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.3193650774
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.3666780537
Short name T528
Test name
Test status
Simulation time 228001725 ps
CPU time 3.22 seconds
Started May 16 03:30:57 PM PDT 24
Finished May 16 03:31:08 PM PDT 24
Peak memory 217880 kb
Host smart-dae82caa-5804-4038-ba0b-a956199dd02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666780537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.3666780537
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3629096043
Short name T705
Test name
Test status
Simulation time 1169096175 ps
CPU time 9.8 seconds
Started May 16 03:31:01 PM PDT 24
Finished May 16 03:31:17 PM PDT 24
Peak memory 225948 kb
Host smart-2beaf163-3c17-4ba4-bbd1-f8b779204ce9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629096043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3629096043
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2385720724
Short name T186
Test name
Test status
Simulation time 384401003 ps
CPU time 9.54 seconds
Started May 16 03:30:59 PM PDT 24
Finished May 16 03:31:15 PM PDT 24
Peak memory 217804 kb
Host smart-9e39b932-e7f8-4ab2-a50a-e164b6c6f7ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385720724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2385720724
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.3185518406
Short name T504
Test name
Test status
Simulation time 172485553 ps
CPU time 6.49 seconds
Started May 16 03:30:57 PM PDT 24
Finished May 16 03:31:11 PM PDT 24
Peak memory 217960 kb
Host smart-a984145a-768a-4a98-85e3-af3f9b7de261
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185518406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
3185518406
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3432116141
Short name T328
Test name
Test status
Simulation time 270906129 ps
CPU time 11.55 seconds
Started May 16 03:30:57 PM PDT 24
Finished May 16 03:31:16 PM PDT 24
Peak memory 218024 kb
Host smart-b9d71fd6-d266-4880-8f12-6ca08e1c2a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432116141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3432116141
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.354239345
Short name T271
Test name
Test status
Simulation time 38508587 ps
CPU time 2.58 seconds
Started May 16 03:30:57 PM PDT 24
Finished May 16 03:31:07 PM PDT 24
Peak memory 217680 kb
Host smart-9b4e372f-efbf-4d7e-ada9-303b0bd31bfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354239345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.354239345
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.7184964
Short name T422
Test name
Test status
Simulation time 862398395 ps
CPU time 29.63 seconds
Started May 16 03:30:57 PM PDT 24
Finished May 16 03:31:34 PM PDT 24
Peak memory 250864 kb
Host smart-b998bbca-05ad-4057-ba8e-bda7862fb5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7184964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.7184964
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3326867662
Short name T194
Test name
Test status
Simulation time 101350317 ps
CPU time 7.25 seconds
Started May 16 03:30:56 PM PDT 24
Finished May 16 03:31:11 PM PDT 24
Peak memory 250348 kb
Host smart-7cb23b5e-8ff8-4ba9-846c-f09e12797d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326867662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3326867662
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.4078754939
Short name T688
Test name
Test status
Simulation time 1668692674 ps
CPU time 75.38 seconds
Started May 16 03:31:01 PM PDT 24
Finished May 16 03:32:23 PM PDT 24
Peak memory 267292 kb
Host smart-19b34ed6-fbf3-4e4c-af4f-9498dce1a7d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078754939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.4078754939
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1022684068
Short name T244
Test name
Test status
Simulation time 39469565 ps
CPU time 0.85 seconds
Started May 16 03:30:55 PM PDT 24
Finished May 16 03:31:04 PM PDT 24
Peak memory 211480 kb
Host smart-ed372855-9ec3-43e4-bb5f-cebf6e1ea219
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022684068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.1022684068
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1075578316
Short name T370
Test name
Test status
Simulation time 59886477 ps
CPU time 0.87 seconds
Started May 16 03:31:08 PM PDT 24
Finished May 16 03:31:15 PM PDT 24
Peak memory 209376 kb
Host smart-fd669d55-0cbf-4041-a109-5c8dce8ce7fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075578316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1075578316
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2656949833
Short name T341
Test name
Test status
Simulation time 1867643944 ps
CPU time 17.32 seconds
Started May 16 03:31:09 PM PDT 24
Finished May 16 03:31:32 PM PDT 24
Peak memory 217936 kb
Host smart-52817c91-9948-4360-917c-8808fbd05b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656949833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2656949833
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1217189470
Short name T30
Test name
Test status
Simulation time 570832903 ps
CPU time 6.69 seconds
Started May 16 03:31:08 PM PDT 24
Finished May 16 03:31:21 PM PDT 24
Peak memory 209416 kb
Host smart-4e976f06-3dd7-47f7-9c07-27018e2bada3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217189470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1217189470
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.4250765169
Short name T376
Test name
Test status
Simulation time 349704476 ps
CPU time 3.52 seconds
Started May 16 03:31:05 PM PDT 24
Finished May 16 03:31:14 PM PDT 24
Peak memory 217872 kb
Host smart-1b97fe0b-a9d9-4ac3-83c6-266b212d7a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250765169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.4250765169
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3396351524
Short name T239
Test name
Test status
Simulation time 890403168 ps
CPU time 14.89 seconds
Started May 16 03:31:05 PM PDT 24
Finished May 16 03:31:26 PM PDT 24
Peak memory 218836 kb
Host smart-5ca0a0a4-75ec-46b7-91dc-4622224380f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396351524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3396351524
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.2085533568
Short name T715
Test name
Test status
Simulation time 3765759060 ps
CPU time 6.81 seconds
Started May 16 03:31:05 PM PDT 24
Finished May 16 03:31:18 PM PDT 24
Peak memory 226108 kb
Host smart-09dd8766-c0c9-45a3-8496-64a2fe93b9f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085533568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.2085533568
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3094006976
Short name T862
Test name
Test status
Simulation time 887867843 ps
CPU time 15.06 seconds
Started May 16 03:31:09 PM PDT 24
Finished May 16 03:31:30 PM PDT 24
Peak memory 217880 kb
Host smart-b722573e-d484-48ad-b437-7f0a36d64f6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094006976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3094006976
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.937768537
Short name T231
Test name
Test status
Simulation time 597662420 ps
CPU time 13.64 seconds
Started May 16 03:31:05 PM PDT 24
Finished May 16 03:31:24 PM PDT 24
Peak memory 224600 kb
Host smart-a2308cd6-5248-4763-b76d-97fd19329dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937768537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.937768537
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.394320123
Short name T707
Test name
Test status
Simulation time 198722367 ps
CPU time 3.24 seconds
Started May 16 03:31:07 PM PDT 24
Finished May 16 03:31:16 PM PDT 24
Peak memory 217780 kb
Host smart-99392890-e4a7-4790-ae5e-7f06efd0fb65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394320123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.394320123
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.732443628
Short name T396
Test name
Test status
Simulation time 430847745 ps
CPU time 16.68 seconds
Started May 16 03:31:04 PM PDT 24
Finished May 16 03:31:27 PM PDT 24
Peak memory 250812 kb
Host smart-f2ab5f70-e219-4630-9b84-454b2e53f3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732443628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.732443628
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2114786661
Short name T464
Test name
Test status
Simulation time 1328167289 ps
CPU time 4.38 seconds
Started May 16 03:31:08 PM PDT 24
Finished May 16 03:31:18 PM PDT 24
Peak memory 217792 kb
Host smart-10180637-9a24-4b00-8083-07066cbac305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114786661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2114786661
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1209509512
Short name T182
Test name
Test status
Simulation time 149187058729 ps
CPU time 1082.95 seconds
Started May 16 03:31:11 PM PDT 24
Finished May 16 03:49:21 PM PDT 24
Peak memory 299460 kb
Host smart-55e53951-ec0e-4e06-b7a7-bc74d952e706
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1209509512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.1209509512
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3958611679
Short name T510
Test name
Test status
Simulation time 48900095 ps
CPU time 0.85 seconds
Started May 16 03:31:09 PM PDT 24
Finished May 16 03:31:16 PM PDT 24
Peak memory 211420 kb
Host smart-04a926f2-f6dc-4c29-8336-87c98c55299b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958611679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3958611679
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.3309668149
Short name T851
Test name
Test status
Simulation time 43283445 ps
CPU time 0.96 seconds
Started May 16 03:31:09 PM PDT 24
Finished May 16 03:31:16 PM PDT 24
Peak memory 209428 kb
Host smart-fdc235e4-4282-409c-bade-625b62ebe4c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309668149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.3309668149
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.3393740478
Short name T844
Test name
Test status
Simulation time 368129760 ps
CPU time 15.18 seconds
Started May 16 03:31:08 PM PDT 24
Finished May 16 03:31:29 PM PDT 24
Peak memory 217804 kb
Host smart-937b5933-2329-4b25-adf5-8b9cf39412b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393740478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.3393740478
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.704209399
Short name T750
Test name
Test status
Simulation time 277553474 ps
CPU time 3.71 seconds
Started May 16 03:31:08 PM PDT 24
Finished May 16 03:31:18 PM PDT 24
Peak memory 209428 kb
Host smart-28eafafd-6328-4f39-9196-5f14110bdbc0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704209399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.704209399
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.4058113459
Short name T858
Test name
Test status
Simulation time 196503481 ps
CPU time 2.26 seconds
Started May 16 03:31:05 PM PDT 24
Finished May 16 03:31:13 PM PDT 24
Peak memory 217844 kb
Host smart-3e9ccf03-852d-4b99-98dc-b5ca944df13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058113459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.4058113459
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1897263354
Short name T368
Test name
Test status
Simulation time 254397624 ps
CPU time 11.23 seconds
Started May 16 03:31:05 PM PDT 24
Finished May 16 03:31:22 PM PDT 24
Peak memory 225960 kb
Host smart-31fcf92e-af35-4dad-a78c-f8fdc01477f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897263354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1897263354
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.400830191
Short name T487
Test name
Test status
Simulation time 1184226605 ps
CPU time 11.88 seconds
Started May 16 03:31:10 PM PDT 24
Finished May 16 03:31:28 PM PDT 24
Peak memory 225980 kb
Host smart-154c63d8-df73-4782-9d6d-ac8ae0f07fa5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400830191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_di
gest.400830191
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3438898176
Short name T323
Test name
Test status
Simulation time 697428823 ps
CPU time 7.7 seconds
Started May 16 03:31:06 PM PDT 24
Finished May 16 03:31:19 PM PDT 24
Peak memory 217936 kb
Host smart-b77788f3-38c4-4e57-8765-d7662ed7d443
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438898176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3438898176
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3536522189
Short name T372
Test name
Test status
Simulation time 451454046 ps
CPU time 10.57 seconds
Started May 16 03:31:10 PM PDT 24
Finished May 16 03:31:26 PM PDT 24
Peak memory 217944 kb
Host smart-5dedd8c4-f12d-489a-83a0-768765791f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536522189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3536522189
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.866695721
Short name T365
Test name
Test status
Simulation time 1705342365 ps
CPU time 6.46 seconds
Started May 16 03:31:05 PM PDT 24
Finished May 16 03:31:17 PM PDT 24
Peak memory 217688 kb
Host smart-ab6b13df-37e7-4cca-86e8-ec09e51c1434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866695721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.866695721
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1409020966
Short name T266
Test name
Test status
Simulation time 1064670558 ps
CPU time 23.2 seconds
Started May 16 03:31:13 PM PDT 24
Finished May 16 03:31:43 PM PDT 24
Peak memory 250400 kb
Host smart-d9719d28-bd88-4be4-9987-804d6173b667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409020966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1409020966
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2621204329
Short name T413
Test name
Test status
Simulation time 89824985 ps
CPU time 8.2 seconds
Started May 16 03:31:13 PM PDT 24
Finished May 16 03:31:28 PM PDT 24
Peak memory 250300 kb
Host smart-38520b3f-75df-4bd0-80ea-8ba83305ee43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621204329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2621204329
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.3308346414
Short name T811
Test name
Test status
Simulation time 281829118 ps
CPU time 23.58 seconds
Started May 16 03:31:07 PM PDT 24
Finished May 16 03:31:37 PM PDT 24
Peak memory 250872 kb
Host smart-6b84c8ad-b495-4d67-a352-52b8f92645db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308346414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.3308346414
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3142145949
Short name T505
Test name
Test status
Simulation time 22351260 ps
CPU time 1.09 seconds
Started May 16 03:31:04 PM PDT 24
Finished May 16 03:31:11 PM PDT 24
Peak memory 212584 kb
Host smart-74fc1c9b-21fd-4ba5-bfd4-ead685927518
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142145949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3142145949
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2077013504
Short name T879
Test name
Test status
Simulation time 24210870 ps
CPU time 1.08 seconds
Started May 16 03:29:30 PM PDT 24
Finished May 16 03:29:39 PM PDT 24
Peak memory 209492 kb
Host smart-63bcc492-0d7d-442d-83b6-0316174f4789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077013504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2077013504
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.509467956
Short name T610
Test name
Test status
Simulation time 15801194 ps
CPU time 0.92 seconds
Started May 16 03:29:32 PM PDT 24
Finished May 16 03:29:40 PM PDT 24
Peak memory 209408 kb
Host smart-d600a96e-54de-4c25-87dd-bd6e84e13016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509467956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.509467956
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.4152948982
Short name T609
Test name
Test status
Simulation time 173359856 ps
CPU time 9.48 seconds
Started May 16 03:29:31 PM PDT 24
Finished May 16 03:29:48 PM PDT 24
Peak memory 217852 kb
Host smart-57f4d674-6181-47fe-994d-f4b21cabd936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152948982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.4152948982
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1655639097
Short name T415
Test name
Test status
Simulation time 734656138 ps
CPU time 7.61 seconds
Started May 16 03:29:32 PM PDT 24
Finished May 16 03:29:47 PM PDT 24
Peak memory 216976 kb
Host smart-a0013b77-712a-4f33-94b9-ab3f27f0ebc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655639097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1655639097
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.2076964948
Short name T848
Test name
Test status
Simulation time 1416400132 ps
CPU time 24.78 seconds
Started May 16 03:29:33 PM PDT 24
Finished May 16 03:30:05 PM PDT 24
Peak memory 217648 kb
Host smart-4198369a-f7ee-40aa-8d52-dfdfe5f329e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076964948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.2076964948
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3345926907
Short name T780
Test name
Test status
Simulation time 552160744 ps
CPU time 4.26 seconds
Started May 16 03:29:37 PM PDT 24
Finished May 16 03:29:47 PM PDT 24
Peak memory 217264 kb
Host smart-09cf189b-5240-4bd4-a010-45b40560b148
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345926907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
345926907
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2733399119
Short name T797
Test name
Test status
Simulation time 1671622026 ps
CPU time 7.2 seconds
Started May 16 03:29:32 PM PDT 24
Finished May 16 03:29:47 PM PDT 24
Peak memory 217568 kb
Host smart-06b5f24b-2da0-4e9d-a663-52e423eb1c51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733399119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2733399119
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.933449529
Short name T723
Test name
Test status
Simulation time 1795012942 ps
CPU time 13.26 seconds
Started May 16 03:29:30 PM PDT 24
Finished May 16 03:29:52 PM PDT 24
Peak memory 212900 kb
Host smart-3dabb050-1809-4cfb-917a-2b2542304a9b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933449529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_regwen_during_op.933449529
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3196880130
Short name T21
Test name
Test status
Simulation time 1267793253 ps
CPU time 9.31 seconds
Started May 16 03:29:30 PM PDT 24
Finished May 16 03:29:48 PM PDT 24
Peak memory 213496 kb
Host smart-1d0e88e5-3ddc-406d-90ba-55ee1e411b67
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196880130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3196880130
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1462779086
Short name T572
Test name
Test status
Simulation time 1926477437 ps
CPU time 71.25 seconds
Started May 16 03:29:32 PM PDT 24
Finished May 16 03:30:51 PM PDT 24
Peak memory 267680 kb
Host smart-8847f789-06e6-4b96-8a97-736762d58dcd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462779086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1462779086
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.37821204
Short name T326
Test name
Test status
Simulation time 817890978 ps
CPU time 13.88 seconds
Started May 16 03:29:31 PM PDT 24
Finished May 16 03:29:53 PM PDT 24
Peak memory 250764 kb
Host smart-70aafe41-6fe9-445e-83a6-8a21ad60036d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37821204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jt
ag_state_post_trans.37821204
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3248037691
Short name T329
Test name
Test status
Simulation time 19903659 ps
CPU time 1.84 seconds
Started May 16 03:29:29 PM PDT 24
Finished May 16 03:29:38 PM PDT 24
Peak memory 217940 kb
Host smart-67a4b987-ecc7-4d7c-8ee8-5bff9f600bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248037691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3248037691
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1144774011
Short name T753
Test name
Test status
Simulation time 1982819813 ps
CPU time 13.77 seconds
Started May 16 03:29:32 PM PDT 24
Finished May 16 03:29:54 PM PDT 24
Peak memory 214160 kb
Host smart-322b5458-ce11-4649-939a-989378430c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144774011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1144774011
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3175617083
Short name T53
Test name
Test status
Simulation time 113775369 ps
CPU time 24.27 seconds
Started May 16 03:29:30 PM PDT 24
Finished May 16 03:30:03 PM PDT 24
Peak memory 281984 kb
Host smart-810bee7d-8ae6-4dbf-872c-bdfd41dbf9f2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175617083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3175617083
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.3186097259
Short name T789
Test name
Test status
Simulation time 311702032 ps
CPU time 14.09 seconds
Started May 16 03:29:31 PM PDT 24
Finished May 16 03:29:54 PM PDT 24
Peak memory 217876 kb
Host smart-0e9409df-d655-4c81-a0e2-be1cda1b0a3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186097259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.3186097259
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.536988488
Short name T269
Test name
Test status
Simulation time 1084597959 ps
CPU time 12.11 seconds
Started May 16 03:29:29 PM PDT 24
Finished May 16 03:29:48 PM PDT 24
Peak memory 217872 kb
Host smart-94fe5b22-a93d-4a74-8e87-7bd3efa9408d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536988488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_dig
est.536988488
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.543189752
Short name T849
Test name
Test status
Simulation time 567478328 ps
CPU time 11.87 seconds
Started May 16 03:29:35 PM PDT 24
Finished May 16 03:29:53 PM PDT 24
Peak memory 217804 kb
Host smart-4773cdc5-cf18-4f21-b2d6-ce5ba44f3dba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543189752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.543189752
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.4183995955
Short name T50
Test name
Test status
Simulation time 557186192 ps
CPU time 10.14 seconds
Started May 16 03:29:32 PM PDT 24
Finished May 16 03:29:50 PM PDT 24
Peak memory 217640 kb
Host smart-e89133aa-0044-48a6-92d8-2bb04114ab49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183995955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.4183995955
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.4180270515
Short name T86
Test name
Test status
Simulation time 240487341 ps
CPU time 3.62 seconds
Started May 16 03:29:31 PM PDT 24
Finished May 16 03:29:42 PM PDT 24
Peak memory 217640 kb
Host smart-02e77c0e-c7f7-46d0-90ac-c11db2d5f21f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180270515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.4180270515
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.760252166
Short name T819
Test name
Test status
Simulation time 207806375 ps
CPU time 19.91 seconds
Started May 16 03:29:31 PM PDT 24
Finished May 16 03:29:59 PM PDT 24
Peak memory 250836 kb
Host smart-5bc4090e-bfec-4a11-b0ee-74cd55f2fbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760252166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.760252166
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1614030975
Short name T710
Test name
Test status
Simulation time 257173177 ps
CPU time 8.19 seconds
Started May 16 03:29:31 PM PDT 24
Finished May 16 03:29:48 PM PDT 24
Peak memory 250820 kb
Host smart-968426f1-81ae-4b95-8f43-bb9d4f2babcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614030975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1614030975
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2210379868
Short name T484
Test name
Test status
Simulation time 17761729826 ps
CPU time 99.66 seconds
Started May 16 03:29:32 PM PDT 24
Finished May 16 03:31:19 PM PDT 24
Peak memory 276704 kb
Host smart-c28bf21d-b873-407a-b094-ead5f5880d36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210379868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2210379868
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.82371840
Short name T420
Test name
Test status
Simulation time 30655164 ps
CPU time 0.83 seconds
Started May 16 03:29:29 PM PDT 24
Finished May 16 03:29:37 PM PDT 24
Peak memory 211408 kb
Host smart-dc5165e4-7c3f-4ce7-9233-b83bbc4dab8b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82371840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_volatile_unlock_smoke.82371840
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.3373152543
Short name T864
Test name
Test status
Simulation time 83880291 ps
CPU time 0.99 seconds
Started May 16 03:31:08 PM PDT 24
Finished May 16 03:31:15 PM PDT 24
Peak memory 208924 kb
Host smart-9de9e5c7-83dd-47e9-b53e-c046be89c90a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373152543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.3373152543
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3951156454
Short name T517
Test name
Test status
Simulation time 576541435 ps
CPU time 12.24 seconds
Started May 16 03:31:08 PM PDT 24
Finished May 16 03:31:27 PM PDT 24
Peak memory 217808 kb
Host smart-ce423283-61d8-4ab3-b7ad-884feec8c97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951156454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3951156454
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.4036125130
Short name T532
Test name
Test status
Simulation time 824503498 ps
CPU time 7.44 seconds
Started May 16 03:31:07 PM PDT 24
Finished May 16 03:31:20 PM PDT 24
Peak memory 209448 kb
Host smart-99cd1e7c-f8ed-4275-81f6-3cfba7c1ae85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036125130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.4036125130
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.1046498502
Short name T633
Test name
Test status
Simulation time 49195147 ps
CPU time 2.76 seconds
Started May 16 03:31:06 PM PDT 24
Finished May 16 03:31:15 PM PDT 24
Peak memory 217860 kb
Host smart-a4a702af-ca9f-485d-8a30-3c0f3edf4cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046498502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.1046498502
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3609830738
Short name T875
Test name
Test status
Simulation time 580042972 ps
CPU time 24.32 seconds
Started May 16 03:31:08 PM PDT 24
Finished May 16 03:31:39 PM PDT 24
Peak memory 225296 kb
Host smart-c080090f-f8a6-4a2e-be41-e91c79114da0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609830738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3609830738
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1718269094
Short name T720
Test name
Test status
Simulation time 1799702685 ps
CPU time 12.81 seconds
Started May 16 03:31:06 PM PDT 24
Finished May 16 03:31:25 PM PDT 24
Peak memory 217840 kb
Host smart-5acd9868-f76e-40d1-801e-4b8b66b65e87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718269094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1718269094
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1240773685
Short name T823
Test name
Test status
Simulation time 238752748 ps
CPU time 7.01 seconds
Started May 16 03:31:07 PM PDT 24
Finished May 16 03:31:20 PM PDT 24
Peak memory 217776 kb
Host smart-0bb136ca-8a8c-4744-891c-375d1ea3c721
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240773685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1240773685
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.2953046078
Short name T54
Test name
Test status
Simulation time 2300749019 ps
CPU time 10.85 seconds
Started May 16 03:31:05 PM PDT 24
Finished May 16 03:31:21 PM PDT 24
Peak memory 218072 kb
Host smart-0332aed0-19a4-4828-8d6d-986a7669fec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953046078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2953046078
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1487749362
Short name T747
Test name
Test status
Simulation time 47957909 ps
CPU time 1.98 seconds
Started May 16 03:31:07 PM PDT 24
Finished May 16 03:31:15 PM PDT 24
Peak memory 217860 kb
Host smart-d3763ebd-9ffc-400d-8c0c-8b1f38bbe084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487749362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1487749362
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.2358275264
Short name T833
Test name
Test status
Simulation time 520809197 ps
CPU time 26.9 seconds
Started May 16 03:31:06 PM PDT 24
Finished May 16 03:31:39 PM PDT 24
Peak memory 250780 kb
Host smart-d6795f0b-460a-43ab-b0db-139b599d3f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358275264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.2358275264
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.754681510
Short name T402
Test name
Test status
Simulation time 123748560 ps
CPU time 7.88 seconds
Started May 16 03:31:05 PM PDT 24
Finished May 16 03:31:19 PM PDT 24
Peak memory 250816 kb
Host smart-aef1b68a-6986-41b1-9cce-ff394717d7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754681510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.754681510
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2087243242
Short name T305
Test name
Test status
Simulation time 9582801065 ps
CPU time 101.19 seconds
Started May 16 03:31:06 PM PDT 24
Finished May 16 03:32:54 PM PDT 24
Peak memory 276660 kb
Host smart-f7469ac7-a49a-4cf8-8070-f1200cde75ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087243242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2087243242
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1839783920
Short name T246
Test name
Test status
Simulation time 34473783 ps
CPU time 0.79 seconds
Started May 16 03:31:05 PM PDT 24
Finished May 16 03:31:12 PM PDT 24
Peak memory 211580 kb
Host smart-abd83871-6d01-4fd1-9957-ee98da5e4289
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839783920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1839783920
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2778390962
Short name T393
Test name
Test status
Simulation time 20315445 ps
CPU time 0.93 seconds
Started May 16 03:31:16 PM PDT 24
Finished May 16 03:31:26 PM PDT 24
Peak memory 209448 kb
Host smart-35c93050-52f3-4417-8b09-082abc3f6c38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778390962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2778390962
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.451806210
Short name T272
Test name
Test status
Simulation time 1117330736 ps
CPU time 11.61 seconds
Started May 16 03:31:08 PM PDT 24
Finished May 16 03:31:26 PM PDT 24
Peak memory 217828 kb
Host smart-40890054-7873-4042-91ee-a9431c6af232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451806210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.451806210
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.404649903
Short name T702
Test name
Test status
Simulation time 901843860 ps
CPU time 11.76 seconds
Started May 16 03:31:08 PM PDT 24
Finished May 16 03:31:26 PM PDT 24
Peak memory 209436 kb
Host smart-204f7b73-5343-4722-a69d-9ad49b3b1fd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404649903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.404649903
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.1019434137
Short name T353
Test name
Test status
Simulation time 70380696 ps
CPU time 1.91 seconds
Started May 16 03:31:06 PM PDT 24
Finished May 16 03:31:14 PM PDT 24
Peak memory 217848 kb
Host smart-5e6498cb-68b2-442c-b4f3-f49c5fbc858e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019434137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1019434137
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.3368794588
Short name T516
Test name
Test status
Simulation time 273840261 ps
CPU time 13.45 seconds
Started May 16 03:31:05 PM PDT 24
Finished May 16 03:31:24 PM PDT 24
Peak memory 225540 kb
Host smart-6326f001-c9ba-4471-a4d8-8d85ff1062f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368794588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.3368794588
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.2999447883
Short name T856
Test name
Test status
Simulation time 643988116 ps
CPU time 22.21 seconds
Started May 16 03:31:07 PM PDT 24
Finished May 16 03:31:35 PM PDT 24
Peak memory 225836 kb
Host smart-fc1219ac-b0b6-484f-9cfa-e8355a37336d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999447883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.2999447883
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.59119815
Short name T278
Test name
Test status
Simulation time 205813316 ps
CPU time 7.4 seconds
Started May 16 03:31:06 PM PDT 24
Finished May 16 03:31:19 PM PDT 24
Peak memory 217852 kb
Host smart-89f26932-ac39-4a2c-ad15-e339f17a298b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59119815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.59119815
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3472761279
Short name T433
Test name
Test status
Simulation time 1228479836 ps
CPU time 8.41 seconds
Started May 16 03:31:07 PM PDT 24
Finished May 16 03:31:21 PM PDT 24
Peak memory 217904 kb
Host smart-3183b25a-aafc-4111-b648-7fe9d2e85fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472761279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3472761279
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2916331421
Short name T75
Test name
Test status
Simulation time 355996183 ps
CPU time 2.98 seconds
Started May 16 03:31:08 PM PDT 24
Finished May 16 03:31:16 PM PDT 24
Peak memory 214300 kb
Host smart-72b96588-2ff0-43d5-8466-c71d862cf1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916331421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2916331421
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1806951619
Short name T262
Test name
Test status
Simulation time 230943796 ps
CPU time 21.21 seconds
Started May 16 03:31:07 PM PDT 24
Finished May 16 03:31:34 PM PDT 24
Peak memory 250804 kb
Host smart-40825209-6881-4f3f-8ea3-a8f803320e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806951619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1806951619
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1605144649
Short name T201
Test name
Test status
Simulation time 117562667 ps
CPU time 8.82 seconds
Started May 16 03:31:08 PM PDT 24
Finished May 16 03:31:22 PM PDT 24
Peak memory 250216 kb
Host smart-3e645d8e-5999-48c3-9b02-ff1e7cfd744d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605144649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1605144649
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2547480304
Short name T730
Test name
Test status
Simulation time 4269457512 ps
CPU time 81.33 seconds
Started May 16 03:31:11 PM PDT 24
Finished May 16 03:32:39 PM PDT 24
Peak memory 283736 kb
Host smart-1ec89214-5c85-49dd-9a4f-ea72115db3ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547480304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2547480304
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.2907234732
Short name T152
Test name
Test status
Simulation time 38992567256 ps
CPU time 1354.07 seconds
Started May 16 03:31:07 PM PDT 24
Finished May 16 03:53:47 PM PDT 24
Peak memory 496772 kb
Host smart-94e8551f-38ea-4a25-aa08-b4fc80b95787
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2907234732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.2907234732
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.515295108
Short name T511
Test name
Test status
Simulation time 14269192 ps
CPU time 1.07 seconds
Started May 16 03:31:08 PM PDT 24
Finished May 16 03:31:16 PM PDT 24
Peak memory 211488 kb
Host smart-af786647-a867-4621-8d71-6290b0ef66f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515295108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ct
rl_volatile_unlock_smoke.515295108
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3079003761
Short name T189
Test name
Test status
Simulation time 42869747 ps
CPU time 1.17 seconds
Started May 16 03:31:17 PM PDT 24
Finished May 16 03:31:28 PM PDT 24
Peak memory 209448 kb
Host smart-391c815a-d01f-4682-82c4-30932fc63e12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079003761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3079003761
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2426549391
Short name T755
Test name
Test status
Simulation time 420139924 ps
CPU time 17.56 seconds
Started May 16 03:31:13 PM PDT 24
Finished May 16 03:31:37 PM PDT 24
Peak memory 217856 kb
Host smart-2a1b169c-fe56-4753-b265-3cfb92950e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426549391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2426549391
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.791307201
Short name T661
Test name
Test status
Simulation time 776316101 ps
CPU time 8.32 seconds
Started May 16 03:31:17 PM PDT 24
Finished May 16 03:31:34 PM PDT 24
Peak memory 209428 kb
Host smart-ebd5856c-c30f-43c4-a126-7a09ad6d8884
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791307201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.791307201
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3422705333
Short name T733
Test name
Test status
Simulation time 108606974 ps
CPU time 3.1 seconds
Started May 16 03:31:14 PM PDT 24
Finished May 16 03:31:25 PM PDT 24
Peak memory 217852 kb
Host smart-4ca84d6e-4d86-4899-bfe7-2d7a24e5f6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422705333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3422705333
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.4216582311
Short name T392
Test name
Test status
Simulation time 227503050 ps
CPU time 9.5 seconds
Started May 16 03:31:16 PM PDT 24
Finished May 16 03:31:35 PM PDT 24
Peak memory 218080 kb
Host smart-2551aad3-f636-47a7-933a-275294d654bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216582311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.4216582311
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.838982805
Short name T200
Test name
Test status
Simulation time 1572770751 ps
CPU time 14.87 seconds
Started May 16 03:31:14 PM PDT 24
Finished May 16 03:31:36 PM PDT 24
Peak memory 217868 kb
Host smart-b0fd442d-c9dd-4f7c-bf4d-ac1802fbe1a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838982805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_di
gest.838982805
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.294695607
Short name T287
Test name
Test status
Simulation time 2997896295 ps
CPU time 9.31 seconds
Started May 16 03:31:17 PM PDT 24
Finished May 16 03:31:35 PM PDT 24
Peak memory 217996 kb
Host smart-15f5fd56-02e0-4ec0-aae6-eacfa1ebf6ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294695607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.294695607
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.4244826724
Short name T786
Test name
Test status
Simulation time 1037042523 ps
CPU time 12.12 seconds
Started May 16 03:31:22 PM PDT 24
Finished May 16 03:31:43 PM PDT 24
Peak memory 225796 kb
Host smart-b5362c04-05cf-4eab-94bf-c4c9d42f8919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244826724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.4244826724
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3771339946
Short name T810
Test name
Test status
Simulation time 89780847 ps
CPU time 1.12 seconds
Started May 16 03:31:13 PM PDT 24
Finished May 16 03:31:22 PM PDT 24
Peak memory 212668 kb
Host smart-80aa0285-7a94-484b-9de9-7495ac563d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771339946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3771339946
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.2046242502
Short name T574
Test name
Test status
Simulation time 2609430100 ps
CPU time 27.89 seconds
Started May 16 03:31:16 PM PDT 24
Finished May 16 03:31:52 PM PDT 24
Peak memory 250984 kb
Host smart-0294079a-cc87-4df8-af8c-442b29bde6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046242502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.2046242502
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1646014519
Short name T440
Test name
Test status
Simulation time 60855760 ps
CPU time 8.78 seconds
Started May 16 03:31:14 PM PDT 24
Finished May 16 03:31:31 PM PDT 24
Peak memory 250796 kb
Host smart-b2babe46-2e7a-4c98-af39-81bb534608ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646014519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1646014519
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3215119745
Short name T324
Test name
Test status
Simulation time 33380665308 ps
CPU time 291.78 seconds
Started May 16 03:31:22 PM PDT 24
Finished May 16 03:36:23 PM PDT 24
Peak memory 226020 kb
Host smart-050e47b2-c186-4736-a4b5-75447d73f7bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215119745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3215119745
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.1522190324
Short name T179
Test name
Test status
Simulation time 160590543897 ps
CPU time 861.02 seconds
Started May 16 03:31:15 PM PDT 24
Finished May 16 03:45:44 PM PDT 24
Peak memory 382140 kb
Host smart-23cbfb5b-ada6-424a-96f7-7cf88d599265
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1522190324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.1522190324
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1969958075
Short name T359
Test name
Test status
Simulation time 12155040 ps
CPU time 0.98 seconds
Started May 16 03:31:14 PM PDT 24
Finished May 16 03:31:22 PM PDT 24
Peak memory 211452 kb
Host smart-dc6cc397-d779-484b-b824-a96c392a4962
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969958075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1969958075
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.28880527
Short name T275
Test name
Test status
Simulation time 19414958 ps
CPU time 0.9 seconds
Started May 16 03:31:18 PM PDT 24
Finished May 16 03:31:28 PM PDT 24
Peak memory 209432 kb
Host smart-7271368f-c2a8-4a6e-b898-50e2efb1d6af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28880527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.28880527
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.1404768032
Short name T44
Test name
Test status
Simulation time 972313796 ps
CPU time 11.37 seconds
Started May 16 03:31:15 PM PDT 24
Finished May 16 03:31:35 PM PDT 24
Peak memory 217868 kb
Host smart-878cd9c0-e5b2-4ea3-af76-b87f3956ec99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404768032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.1404768032
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3614571515
Short name T33
Test name
Test status
Simulation time 678071336 ps
CPU time 2.8 seconds
Started May 16 03:31:18 PM PDT 24
Finished May 16 03:31:31 PM PDT 24
Peak memory 209440 kb
Host smart-fe98d6f7-200c-4a58-961d-33694a167c82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614571515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3614571515
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.1684818731
Short name T459
Test name
Test status
Simulation time 79763869 ps
CPU time 2.74 seconds
Started May 16 03:31:22 PM PDT 24
Finished May 16 03:31:34 PM PDT 24
Peak memory 217760 kb
Host smart-cc61c6e8-af3e-45ac-bb84-19ce0e5b6477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684818731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.1684818731
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2209178093
Short name T101
Test name
Test status
Simulation time 495248607 ps
CPU time 10.52 seconds
Started May 16 03:31:16 PM PDT 24
Finished May 16 03:31:35 PM PDT 24
Peak memory 225956 kb
Host smart-64e9b203-b1cb-43da-92b8-e58b0078fd37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209178093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2209178093
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2299550977
Short name T483
Test name
Test status
Simulation time 239219165 ps
CPU time 7 seconds
Started May 16 03:31:15 PM PDT 24
Finished May 16 03:31:31 PM PDT 24
Peak memory 217848 kb
Host smart-302611d6-6b47-42a7-88e5-d198ac28dcce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299550977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2299550977
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1200212962
Short name T836
Test name
Test status
Simulation time 6117497122 ps
CPU time 12.52 seconds
Started May 16 03:31:18 PM PDT 24
Finished May 16 03:31:40 PM PDT 24
Peak memory 218036 kb
Host smart-9f171f58-4823-4872-abe1-df407da6fcba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200212962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1200212962
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.600426110
Short name T60
Test name
Test status
Simulation time 799788002 ps
CPU time 3.43 seconds
Started May 16 03:31:18 PM PDT 24
Finished May 16 03:31:31 PM PDT 24
Peak memory 214700 kb
Host smart-327436e6-c8bf-4210-94cf-75120d3ef569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600426110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.600426110
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2712544106
Short name T519
Test name
Test status
Simulation time 697566075 ps
CPU time 24.05 seconds
Started May 16 03:31:15 PM PDT 24
Finished May 16 03:31:48 PM PDT 24
Peak memory 250856 kb
Host smart-a52d62d5-f9b9-4d82-8ea9-82815f7c7e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712544106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2712544106
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1707786994
Short name T478
Test name
Test status
Simulation time 427174945 ps
CPU time 8.26 seconds
Started May 16 03:31:18 PM PDT 24
Finished May 16 03:31:37 PM PDT 24
Peak memory 250740 kb
Host smart-a6f5f6e4-35a5-410d-ad35-3734b72dda3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707786994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1707786994
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1097088977
Short name T778
Test name
Test status
Simulation time 10784766985 ps
CPU time 181.75 seconds
Started May 16 03:31:16 PM PDT 24
Finished May 16 03:34:27 PM PDT 24
Peak memory 250652 kb
Host smart-458326e1-1e4b-48b6-916b-8d0d0280b8d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097088977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1097088977
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.931468893
Short name T187
Test name
Test status
Simulation time 26220833 ps
CPU time 0.87 seconds
Started May 16 03:31:16 PM PDT 24
Finished May 16 03:31:25 PM PDT 24
Peak memory 211456 kb
Host smart-ecfb4f24-bfc0-4d7c-9f6e-2f50b617621e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931468893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ct
rl_volatile_unlock_smoke.931468893
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1138186072
Short name T491
Test name
Test status
Simulation time 18817340 ps
CPU time 1.12 seconds
Started May 16 03:31:16 PM PDT 24
Finished May 16 03:31:27 PM PDT 24
Peak memory 209472 kb
Host smart-83ffe131-939e-4f84-9478-7d8dba844d9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138186072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1138186072
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.2683950159
Short name T99
Test name
Test status
Simulation time 424820574 ps
CPU time 17.88 seconds
Started May 16 03:31:19 PM PDT 24
Finished May 16 03:31:47 PM PDT 24
Peak memory 217856 kb
Host smart-7a53cf2d-1c60-41a7-a819-2616fa20fdc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683950159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.2683950159
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.4037095976
Short name T699
Test name
Test status
Simulation time 309189986 ps
CPU time 1.98 seconds
Started May 16 03:31:16 PM PDT 24
Finished May 16 03:31:27 PM PDT 24
Peak memory 209124 kb
Host smart-afd4fbcd-9847-4a5c-bcc4-2da42c857545
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037095976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.4037095976
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.4282473243
Short name T712
Test name
Test status
Simulation time 84425549 ps
CPU time 2.15 seconds
Started May 16 03:31:16 PM PDT 24
Finished May 16 03:31:27 PM PDT 24
Peak memory 217876 kb
Host smart-b6247a01-8f5b-42a7-80cc-36ce17bddbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282473243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.4282473243
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.721962831
Short name T523
Test name
Test status
Simulation time 276510053 ps
CPU time 10.15 seconds
Started May 16 03:31:15 PM PDT 24
Finished May 16 03:31:34 PM PDT 24
Peak memory 218008 kb
Host smart-abf78b5d-a20f-4df0-8c5d-d3dc3ef6a149
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721962831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.721962831
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.1704459418
Short name T675
Test name
Test status
Simulation time 1379520066 ps
CPU time 13.09 seconds
Started May 16 03:31:15 PM PDT 24
Finished May 16 03:31:37 PM PDT 24
Peak memory 217852 kb
Host smart-35099519-2c09-4061-a7e9-b19e93bd852a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704459418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.1704459418
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.645574225
Short name T534
Test name
Test status
Simulation time 409438275 ps
CPU time 9.91 seconds
Started May 16 03:31:17 PM PDT 24
Finished May 16 03:31:36 PM PDT 24
Peak memory 217852 kb
Host smart-960fb5af-ff14-4c4c-94a4-ef8f6fb23a9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645574225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.645574225
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1242151829
Short name T230
Test name
Test status
Simulation time 1743175768 ps
CPU time 15.02 seconds
Started May 16 03:31:17 PM PDT 24
Finished May 16 03:31:41 PM PDT 24
Peak memory 217968 kb
Host smart-49aedace-2cab-4933-be0f-c81cc9fbaeb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242151829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1242151829
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.3524727642
Short name T679
Test name
Test status
Simulation time 452405030 ps
CPU time 2.05 seconds
Started May 16 03:31:22 PM PDT 24
Finished May 16 03:31:33 PM PDT 24
Peak memory 218072 kb
Host smart-388fa841-05e2-44c6-a4d7-b1110e998ed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524727642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.3524727642
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.3494679237
Short name T434
Test name
Test status
Simulation time 184668687 ps
CPU time 26.32 seconds
Started May 16 03:31:13 PM PDT 24
Finished May 16 03:31:47 PM PDT 24
Peak memory 250700 kb
Host smart-96729ee1-1ea9-4cf2-b888-ea570b6f5f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494679237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3494679237
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.955823981
Short name T815
Test name
Test status
Simulation time 106544093 ps
CPU time 6.5 seconds
Started May 16 03:31:15 PM PDT 24
Finished May 16 03:31:29 PM PDT 24
Peak memory 246472 kb
Host smart-a26925f2-962f-49c2-9a65-be317f3601f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955823981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.955823981
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.4209088938
Short name T736
Test name
Test status
Simulation time 3291795772 ps
CPU time 44.42 seconds
Started May 16 03:31:19 PM PDT 24
Finished May 16 03:32:13 PM PDT 24
Peak memory 250956 kb
Host smart-239fb429-c052-439e-98d7-343f33d8dc48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209088938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.4209088938
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.3827690858
Short name T870
Test name
Test status
Simulation time 99179020207 ps
CPU time 489.44 seconds
Started May 16 03:31:15 PM PDT 24
Finished May 16 03:39:33 PM PDT 24
Peak memory 496760 kb
Host smart-ecb0c2a6-38f1-4bd7-b8fc-65fb642f3c7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3827690858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.3827690858
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.3955913512
Short name T577
Test name
Test status
Simulation time 91986003 ps
CPU time 0.81 seconds
Started May 16 03:31:17 PM PDT 24
Finished May 16 03:31:28 PM PDT 24
Peak memory 211584 kb
Host smart-24f537cf-9f5e-4335-8b36-240fb25a5a11
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955913512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.3955913512
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2416023386
Short name T570
Test name
Test status
Simulation time 17920128 ps
CPU time 0.86 seconds
Started May 16 03:31:22 PM PDT 24
Finished May 16 03:31:32 PM PDT 24
Peak memory 209316 kb
Host smart-f5d1c83c-e554-4ef1-b10f-1d0544b7b89e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416023386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2416023386
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.833289012
Short name T737
Test name
Test status
Simulation time 1021493370 ps
CPU time 10.5 seconds
Started May 16 03:31:17 PM PDT 24
Finished May 16 03:31:37 PM PDT 24
Peak memory 217824 kb
Host smart-9dd3ec0c-8cde-48d2-a1c8-a7da08d2b546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833289012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.833289012
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.186271828
Short name T512
Test name
Test status
Simulation time 1571389231 ps
CPU time 9.95 seconds
Started May 16 03:31:25 PM PDT 24
Finished May 16 03:31:43 PM PDT 24
Peak memory 209456 kb
Host smart-60accdf0-67eb-44dc-8af0-45a52c5468e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186271828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.186271828
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.1249985989
Short name T495
Test name
Test status
Simulation time 246853673 ps
CPU time 2.79 seconds
Started May 16 03:31:18 PM PDT 24
Finished May 16 03:31:30 PM PDT 24
Peak memory 217832 kb
Host smart-48dcc01c-0c3d-43cc-b0d5-af663cd331a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249985989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.1249985989
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1869278869
Short name T834
Test name
Test status
Simulation time 1895736380 ps
CPU time 14.81 seconds
Started May 16 03:31:24 PM PDT 24
Finished May 16 03:31:47 PM PDT 24
Peak memory 218820 kb
Host smart-5204199a-1783-4e3a-b2d1-e478bdb99d87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869278869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1869278869
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2037656213
Short name T581
Test name
Test status
Simulation time 232762612 ps
CPU time 9.97 seconds
Started May 16 03:31:25 PM PDT 24
Finished May 16 03:31:43 PM PDT 24
Peak memory 217780 kb
Host smart-ba9d8e2c-2f26-48ba-b7b2-1863bd7371f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037656213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2037656213
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.307308150
Short name T263
Test name
Test status
Simulation time 423478926 ps
CPU time 10.08 seconds
Started May 16 03:31:24 PM PDT 24
Finished May 16 03:31:43 PM PDT 24
Peak memory 217800 kb
Host smart-73e366b4-2030-4760-97bc-39c35867324d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307308150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.307308150
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1344995467
Short name T561
Test name
Test status
Simulation time 357878702 ps
CPU time 7.68 seconds
Started May 16 03:31:30 PM PDT 24
Finished May 16 03:31:44 PM PDT 24
Peak memory 217432 kb
Host smart-6e872967-2f49-467a-bec4-1e6b73581dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344995467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1344995467
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.580327554
Short name T687
Test name
Test status
Simulation time 121771875 ps
CPU time 1.95 seconds
Started May 16 03:31:22 PM PDT 24
Finished May 16 03:31:33 PM PDT 24
Peak memory 213664 kb
Host smart-e3553489-eac6-4cf9-96f2-95dd9f566d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580327554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.580327554
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.2498300197
Short name T847
Test name
Test status
Simulation time 185784477 ps
CPU time 2.97 seconds
Started May 16 03:31:15 PM PDT 24
Finished May 16 03:31:27 PM PDT 24
Peak memory 222096 kb
Host smart-3eaabff1-6446-43e3-bde3-0a06bf805d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498300197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2498300197
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2226013403
Short name T19
Test name
Test status
Simulation time 6814981976 ps
CPU time 203.08 seconds
Started May 16 03:31:26 PM PDT 24
Finished May 16 03:34:57 PM PDT 24
Peak memory 280484 kb
Host smart-9558f6f1-cce5-4017-bb7c-967c6f6d21e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226013403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2226013403
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.4114284028
Short name T161
Test name
Test status
Simulation time 4111003758 ps
CPU time 170.46 seconds
Started May 16 03:31:25 PM PDT 24
Finished May 16 03:34:24 PM PDT 24
Peak memory 283760 kb
Host smart-e7985044-2b6f-4d0a-bfc0-2c6610ca9081
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4114284028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.4114284028
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2942147826
Short name T94
Test name
Test status
Simulation time 17488960 ps
CPU time 1 seconds
Started May 16 03:31:16 PM PDT 24
Finished May 16 03:31:27 PM PDT 24
Peak memory 212752 kb
Host smart-7568c4a6-1a3d-42f6-84a6-ba4c7ba1b668
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942147826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2942147826
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3660770860
Short name T297
Test name
Test status
Simulation time 42079289 ps
CPU time 0.85 seconds
Started May 16 03:31:26 PM PDT 24
Finished May 16 03:31:35 PM PDT 24
Peak memory 209404 kb
Host smart-e65fbf54-3077-48a6-bfd8-154a29eb2e1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660770860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3660770860
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.928136758
Short name T41
Test name
Test status
Simulation time 3097944957 ps
CPU time 10.56 seconds
Started May 16 03:31:24 PM PDT 24
Finished May 16 03:31:43 PM PDT 24
Peak memory 218900 kb
Host smart-f8fdf676-6f49-4a0e-a62d-930ff2ce2f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928136758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.928136758
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.629186872
Short name T377
Test name
Test status
Simulation time 1943284748 ps
CPU time 22.55 seconds
Started May 16 03:31:24 PM PDT 24
Finished May 16 03:31:55 PM PDT 24
Peak memory 209448 kb
Host smart-454de2b5-8d28-44ff-b0c1-632c8118f72c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629186872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.629186872
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1205967461
Short name T159
Test name
Test status
Simulation time 188830449 ps
CPU time 2.04 seconds
Started May 16 03:31:25 PM PDT 24
Finished May 16 03:31:35 PM PDT 24
Peak memory 218008 kb
Host smart-ef62b364-f8fb-4442-83f3-4bc0aec5e1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205967461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1205967461
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.2950431675
Short name T384
Test name
Test status
Simulation time 1225642894 ps
CPU time 22.15 seconds
Started May 16 03:31:25 PM PDT 24
Finished May 16 03:31:55 PM PDT 24
Peak memory 218096 kb
Host smart-65a93d29-0cb3-4b58-9763-c15d15997998
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950431675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.2950431675
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.520918214
Short name T442
Test name
Test status
Simulation time 334151152 ps
CPU time 11.96 seconds
Started May 16 03:31:26 PM PDT 24
Finished May 16 03:31:46 PM PDT 24
Peak memory 225920 kb
Host smart-cf832a05-2b0d-433b-8cc1-fa2852a3f465
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520918214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.520918214
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.749694469
Short name T446
Test name
Test status
Simulation time 404623365 ps
CPU time 9.17 seconds
Started May 16 03:31:23 PM PDT 24
Finished May 16 03:31:41 PM PDT 24
Peak memory 217816 kb
Host smart-8666bb89-a3fd-4def-83cb-274fac7dac9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749694469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.749694469
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.2225357340
Short name T357
Test name
Test status
Simulation time 3027801728 ps
CPU time 10.11 seconds
Started May 16 03:31:25 PM PDT 24
Finished May 16 03:31:43 PM PDT 24
Peak memory 217960 kb
Host smart-343b5b47-e965-4e73-9836-6e2911d18d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225357340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2225357340
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1063316887
Short name T621
Test name
Test status
Simulation time 49892530 ps
CPU time 1.15 seconds
Started May 16 03:31:25 PM PDT 24
Finished May 16 03:31:34 PM PDT 24
Peak memory 217568 kb
Host smart-697e56c2-d41b-4a20-8a49-cf5613f9eaed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063316887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1063316887
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3139494923
Short name T656
Test name
Test status
Simulation time 309387654 ps
CPU time 35.29 seconds
Started May 16 03:31:23 PM PDT 24
Finished May 16 03:32:07 PM PDT 24
Peak memory 250848 kb
Host smart-4e738b4b-5aca-41fb-8f3c-158beb82bbce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139494923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3139494923
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.2723544740
Short name T525
Test name
Test status
Simulation time 270728686 ps
CPU time 3.95 seconds
Started May 16 03:31:26 PM PDT 24
Finished May 16 03:31:38 PM PDT 24
Peak memory 217836 kb
Host smart-247ad4fc-fe90-4b8b-a931-ec054abeeb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723544740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.2723544740
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2596313981
Short name T739
Test name
Test status
Simulation time 20349862002 ps
CPU time 98.13 seconds
Started May 16 03:31:26 PM PDT 24
Finished May 16 03:33:12 PM PDT 24
Peak memory 267356 kb
Host smart-d877cd45-96ce-4f65-95d6-a67bd48d8173
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596313981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2596313981
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.965296439
Short name T252
Test name
Test status
Simulation time 18323142 ps
CPU time 0.73 seconds
Started May 16 03:31:29 PM PDT 24
Finished May 16 03:31:37 PM PDT 24
Peak memory 207168 kb
Host smart-64525c72-2ff0-4519-952a-cde722787d44
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965296439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.965296439
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3916011044
Short name T674
Test name
Test status
Simulation time 61114694 ps
CPU time 0.97 seconds
Started May 16 03:31:28 PM PDT 24
Finished May 16 03:31:36 PM PDT 24
Peak memory 209408 kb
Host smart-db9659b1-52fc-4e1f-bb5f-486bb5e4ba3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916011044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3916011044
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3651352019
Short name T557
Test name
Test status
Simulation time 980561117 ps
CPU time 16.02 seconds
Started May 16 03:31:23 PM PDT 24
Finished May 16 03:31:48 PM PDT 24
Peak memory 217896 kb
Host smart-2a0cd8ba-9632-4aab-9254-2c3f7427fa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651352019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3651352019
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1106640998
Short name T32
Test name
Test status
Simulation time 2061777984 ps
CPU time 23.97 seconds
Started May 16 03:31:26 PM PDT 24
Finished May 16 03:31:58 PM PDT 24
Peak memory 217192 kb
Host smart-1287864d-54a9-4107-92c6-9f63fcbe43d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106640998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1106640998
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3884974123
Short name T618
Test name
Test status
Simulation time 105504399 ps
CPU time 2.9 seconds
Started May 16 03:31:22 PM PDT 24
Finished May 16 03:31:34 PM PDT 24
Peak memory 217944 kb
Host smart-25048527-3b1d-4851-939b-187aa17f80f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884974123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3884974123
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2073609362
Short name T729
Test name
Test status
Simulation time 280178721 ps
CPU time 13.6 seconds
Started May 16 03:31:27 PM PDT 24
Finished May 16 03:31:48 PM PDT 24
Peak memory 217884 kb
Host smart-7ee2a356-097a-45b3-b20d-d6fcca79e3d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073609362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2073609362
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2907900006
Short name T237
Test name
Test status
Simulation time 755140743 ps
CPU time 9.2 seconds
Started May 16 03:31:28 PM PDT 24
Finished May 16 03:31:44 PM PDT 24
Peak memory 225904 kb
Host smart-1492d266-7ce8-455c-ba91-148dae647718
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907900006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2907900006
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1436373974
Short name T390
Test name
Test status
Simulation time 1637125585 ps
CPU time 9.86 seconds
Started May 16 03:31:27 PM PDT 24
Finished May 16 03:31:44 PM PDT 24
Peak memory 217880 kb
Host smart-7f747f30-cca9-4aca-b1af-953a6f6833e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436373974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1436373974
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.588586447
Short name T682
Test name
Test status
Simulation time 1199797920 ps
CPU time 7.73 seconds
Started May 16 03:31:24 PM PDT 24
Finished May 16 03:31:40 PM PDT 24
Peak memory 217844 kb
Host smart-bb41935d-2c65-4c2f-b762-398c096e89ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588586447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.588586447
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2196788407
Short name T669
Test name
Test status
Simulation time 18986304 ps
CPU time 1.46 seconds
Started May 16 03:31:25 PM PDT 24
Finished May 16 03:31:35 PM PDT 24
Peak memory 213260 kb
Host smart-7842d34d-26cc-4b07-b0c9-ac1c6456b593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196788407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2196788407
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.424636539
Short name T14
Test name
Test status
Simulation time 931517637 ps
CPU time 33.51 seconds
Started May 16 03:31:23 PM PDT 24
Finished May 16 03:32:06 PM PDT 24
Peak memory 250840 kb
Host smart-9d8b8e98-5b53-4886-a74c-85705291da04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424636539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.424636539
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.574779899
Short name T515
Test name
Test status
Simulation time 161333807 ps
CPU time 6.3 seconds
Started May 16 03:31:26 PM PDT 24
Finished May 16 03:31:40 PM PDT 24
Peak memory 246820 kb
Host smart-b2588653-7739-477f-9ca2-59a14e351bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574779899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.574779899
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.2485614255
Short name T106
Test name
Test status
Simulation time 342999832150 ps
CPU time 585.81 seconds
Started May 16 03:31:27 PM PDT 24
Finished May 16 03:41:20 PM PDT 24
Peak memory 263136 kb
Host smart-cd93a568-fcbe-4759-853a-01684eec8cfb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485614255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.2485614255
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.1394967780
Short name T155
Test name
Test status
Simulation time 18326888716 ps
CPU time 472.49 seconds
Started May 16 03:31:24 PM PDT 24
Finished May 16 03:39:26 PM PDT 24
Peak memory 283776 kb
Host smart-5b860c47-f3c1-4d20-a619-1dba963293ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1394967780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.1394967780
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.330903125
Short name T447
Test name
Test status
Simulation time 11341078 ps
CPU time 0.77 seconds
Started May 16 03:31:30 PM PDT 24
Finished May 16 03:31:37 PM PDT 24
Peak memory 207320 kb
Host smart-0e51957d-4424-41c1-8695-d978e9c3f130
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330903125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.330903125
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.3836718288
Short name T594
Test name
Test status
Simulation time 27300681 ps
CPU time 1.15 seconds
Started May 16 03:31:40 PM PDT 24
Finished May 16 03:31:46 PM PDT 24
Peak memory 209504 kb
Host smart-70803f1e-6a4e-4beb-8d5f-6895a5eda76b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836718288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.3836718288
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1352062405
Short name T718
Test name
Test status
Simulation time 1756622772 ps
CPU time 19.45 seconds
Started May 16 03:31:36 PM PDT 24
Finished May 16 03:32:01 PM PDT 24
Peak memory 217788 kb
Host smart-4a9ed4fe-b4ff-4318-829f-003514b85ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352062405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1352062405
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.312814092
Short name T654
Test name
Test status
Simulation time 218468462 ps
CPU time 3.27 seconds
Started May 16 03:31:34 PM PDT 24
Finished May 16 03:31:43 PM PDT 24
Peak memory 216800 kb
Host smart-b0145735-0d9b-4c32-9739-a976028f3ba6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312814092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.312814092
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1217393440
Short name T317
Test name
Test status
Simulation time 1225804875 ps
CPU time 3.35 seconds
Started May 16 03:31:33 PM PDT 24
Finished May 16 03:31:43 PM PDT 24
Peak memory 217836 kb
Host smart-d93567f0-be10-4149-9d7b-426ac862d6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217393440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1217393440
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1751262312
Short name T500
Test name
Test status
Simulation time 1273653341 ps
CPU time 14.3 seconds
Started May 16 03:31:34 PM PDT 24
Finished May 16 03:31:55 PM PDT 24
Peak memory 218836 kb
Host smart-87f0c070-b7ab-40fd-ba4f-d672a1070b8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751262312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1751262312
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2132287461
Short name T790
Test name
Test status
Simulation time 253011666 ps
CPU time 7.02 seconds
Started May 16 03:31:32 PM PDT 24
Finished May 16 03:31:46 PM PDT 24
Peak memory 217860 kb
Host smart-bc010907-892e-4e76-bbd2-233a3fbef83a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132287461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2132287461
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.31929561
Short name T843
Test name
Test status
Simulation time 2420133976 ps
CPU time 15.26 seconds
Started May 16 03:31:35 PM PDT 24
Finished May 16 03:31:57 PM PDT 24
Peak memory 217992 kb
Host smart-befba3e9-7abe-4b19-818b-d00c85025048
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31929561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.31929561
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1586800106
Short name T438
Test name
Test status
Simulation time 624899663 ps
CPU time 6.12 seconds
Started May 16 03:31:33 PM PDT 24
Finished May 16 03:31:45 PM PDT 24
Peak memory 217916 kb
Host smart-07b42631-19ff-412d-b7ec-9297b030cf2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586800106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1586800106
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3563788051
Short name T522
Test name
Test status
Simulation time 68681462 ps
CPU time 2.78 seconds
Started May 16 03:31:27 PM PDT 24
Finished May 16 03:31:37 PM PDT 24
Peak memory 214076 kb
Host smart-8d76f546-6ada-408d-af61-a354d4c50930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563788051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3563788051
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.882131164
Short name T597
Test name
Test status
Simulation time 220420805 ps
CPU time 25.52 seconds
Started May 16 03:31:33 PM PDT 24
Finished May 16 03:32:05 PM PDT 24
Peak memory 250864 kb
Host smart-0b908b46-e34e-4c3b-8776-2e1b941cc151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882131164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.882131164
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.491131417
Short name T605
Test name
Test status
Simulation time 70934706 ps
CPU time 6.79 seconds
Started May 16 03:31:33 PM PDT 24
Finished May 16 03:31:46 PM PDT 24
Peak memory 246708 kb
Host smart-37178ddf-cb07-489d-9d2a-e649d96770aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491131417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.491131417
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.525241746
Short name T78
Test name
Test status
Simulation time 1881340804 ps
CPU time 58.12 seconds
Started May 16 03:31:36 PM PDT 24
Finished May 16 03:32:40 PM PDT 24
Peak memory 250848 kb
Host smart-bac4b0ba-8b5a-440e-ba04-436c6407f487
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525241746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.525241746
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2846102835
Short name T397
Test name
Test status
Simulation time 23118743 ps
CPU time 0.95 seconds
Started May 16 03:31:33 PM PDT 24
Finished May 16 03:31:41 PM PDT 24
Peak memory 211480 kb
Host smart-6bd7dc43-9809-45fb-abc1-7204ef031fbb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846102835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2846102835
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.1149070315
Short name T549
Test name
Test status
Simulation time 161378791 ps
CPU time 2.54 seconds
Started May 16 03:31:35 PM PDT 24
Finished May 16 03:31:44 PM PDT 24
Peak memory 216880 kb
Host smart-07ce4d60-e89b-41cb-ba58-187739f7a2e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149070315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.1149070315
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2576357891
Short name T291
Test name
Test status
Simulation time 263509299 ps
CPU time 2.66 seconds
Started May 16 03:31:34 PM PDT 24
Finished May 16 03:31:43 PM PDT 24
Peak memory 217892 kb
Host smart-c1e43fb9-78f7-44e6-8077-41e0e504660f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576357891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2576357891
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3230383969
Short name T599
Test name
Test status
Simulation time 1006425725 ps
CPU time 12.01 seconds
Started May 16 03:31:34 PM PDT 24
Finished May 16 03:31:52 PM PDT 24
Peak memory 217872 kb
Host smart-28783526-e8c0-4ba0-8cf4-047d8f4ffc82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230383969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3230383969
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3075590473
Short name T470
Test name
Test status
Simulation time 685204934 ps
CPU time 18.63 seconds
Started May 16 03:31:35 PM PDT 24
Finished May 16 03:32:00 PM PDT 24
Peak memory 217868 kb
Host smart-88e4c264-412b-4e96-8c24-6848abc081a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075590473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3075590473
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2623525175
Short name T842
Test name
Test status
Simulation time 7744793633 ps
CPU time 11.25 seconds
Started May 16 03:31:34 PM PDT 24
Finished May 16 03:31:52 PM PDT 24
Peak memory 217980 kb
Host smart-b785635c-865c-44f3-8630-a731ed1a24c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623525175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2623525175
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.480471251
Short name T76
Test name
Test status
Simulation time 118569126 ps
CPU time 1.73 seconds
Started May 16 03:31:34 PM PDT 24
Finished May 16 03:31:43 PM PDT 24
Peak memory 213344 kb
Host smart-2b4e0ff9-e0ad-4886-89bc-25ed9c65786d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480471251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.480471251
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.1274231693
Short name T490
Test name
Test status
Simulation time 989630593 ps
CPU time 29.23 seconds
Started May 16 03:31:35 PM PDT 24
Finished May 16 03:32:11 PM PDT 24
Peak memory 250780 kb
Host smart-df9136f7-52f7-4a0a-8950-d1ce0ea03434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274231693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.1274231693
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.4177309998
Short name T103
Test name
Test status
Simulation time 162795679 ps
CPU time 9.54 seconds
Started May 16 03:31:32 PM PDT 24
Finished May 16 03:31:48 PM PDT 24
Peak memory 250832 kb
Host smart-a3b58f13-69d6-4020-b7e7-e63a6bd4e246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177309998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.4177309998
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.3614922051
Short name T93
Test name
Test status
Simulation time 61573354089 ps
CPU time 115.93 seconds
Started May 16 03:31:34 PM PDT 24
Finished May 16 03:33:36 PM PDT 24
Peak memory 267324 kb
Host smart-a193bf93-819b-4610-8a5b-fdd02b713c60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614922051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.3614922051
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.188826847
Short name T346
Test name
Test status
Simulation time 63149709 ps
CPU time 0.93 seconds
Started May 16 03:31:33 PM PDT 24
Finished May 16 03:31:40 PM PDT 24
Peak memory 212444 kb
Host smart-4fe374f9-2260-4cf8-97a6-eb68a53e2b02
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188826847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct
rl_volatile_unlock_smoke.188826847
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3328265166
Short name T314
Test name
Test status
Simulation time 52911097 ps
CPU time 0.85 seconds
Started May 16 03:29:44 PM PDT 24
Finished May 16 03:29:51 PM PDT 24
Peak memory 209444 kb
Host smart-7d684e0a-5ac5-4fe3-b255-09b7810d0b59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328265166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3328265166
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.2853930247
Short name T403
Test name
Test status
Simulation time 47252756 ps
CPU time 1.61 seconds
Started May 16 03:29:45 PM PDT 24
Finished May 16 03:29:54 PM PDT 24
Peak memory 209336 kb
Host smart-fcccdcd9-c23f-4f29-8258-25d49ff80f12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853930247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.2853930247
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.4119632820
Short name T467
Test name
Test status
Simulation time 4767328256 ps
CPU time 39.92 seconds
Started May 16 03:29:41 PM PDT 24
Finished May 16 03:30:24 PM PDT 24
Peak memory 218392 kb
Host smart-6f612a3d-d865-4f08-a652-bea58e702a88
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119632820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.4119632820
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1452395962
Short name T375
Test name
Test status
Simulation time 771893129 ps
CPU time 18.29 seconds
Started May 16 03:29:41 PM PDT 24
Finished May 16 03:30:04 PM PDT 24
Peak memory 217236 kb
Host smart-ad489413-eeb0-4b4b-bf34-2970db4c8d46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452395962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
452395962
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.806814714
Short name T301
Test name
Test status
Simulation time 184659580 ps
CPU time 6.57 seconds
Started May 16 03:29:41 PM PDT 24
Finished May 16 03:29:51 PM PDT 24
Peak memory 217856 kb
Host smart-f36b9ffd-d109-4c65-a71e-d5eef91c2106
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806814714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.806814714
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2020768147
Short name T732
Test name
Test status
Simulation time 1799469244 ps
CPU time 12.66 seconds
Started May 16 03:29:40 PM PDT 24
Finished May 16 03:29:57 PM PDT 24
Peak memory 212960 kb
Host smart-499ea733-18ec-4a5b-aeb2-a9b23802be77
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020768147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2020768147
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2337704435
Short name T6
Test name
Test status
Simulation time 1837617770 ps
CPU time 4.85 seconds
Started May 16 03:29:42 PM PDT 24
Finished May 16 03:29:52 PM PDT 24
Peak memory 213460 kb
Host smart-ebe66f64-aa9c-4ae0-a676-c6d270821a0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337704435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2337704435
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2404211647
Short name T449
Test name
Test status
Simulation time 5567734500 ps
CPU time 38.92 seconds
Started May 16 03:29:43 PM PDT 24
Finished May 16 03:30:27 PM PDT 24
Peak memory 250944 kb
Host smart-4ecca542-a449-45d0-98a9-e8c947529c92
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404211647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2404211647
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.4259949757
Short name T348
Test name
Test status
Simulation time 1360025248 ps
CPU time 10.65 seconds
Started May 16 03:29:42 PM PDT 24
Finished May 16 03:29:58 PM PDT 24
Peak memory 245172 kb
Host smart-142a7fb0-f6da-4f49-abb1-8768fc90d7cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259949757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.4259949757
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3514119362
Short name T454
Test name
Test status
Simulation time 160210544 ps
CPU time 2.8 seconds
Started May 16 03:29:31 PM PDT 24
Finished May 16 03:29:42 PM PDT 24
Peak memory 217836 kb
Host smart-e1f94f3f-5953-468b-8c0d-498b3275cbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514119362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3514119362
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3580734346
Short name T79
Test name
Test status
Simulation time 1222825624 ps
CPU time 19.06 seconds
Started May 16 03:29:42 PM PDT 24
Finished May 16 03:30:06 PM PDT 24
Peak memory 214276 kb
Host smart-12e50ce7-b6ce-4d74-89fa-40237b2d5a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580734346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3580734346
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1757216436
Short name T52
Test name
Test status
Simulation time 1343181487 ps
CPU time 37.82 seconds
Started May 16 03:29:43 PM PDT 24
Finished May 16 03:30:27 PM PDT 24
Peak memory 281592 kb
Host smart-bbcd5f07-c6ea-43f4-a082-cd8366d37780
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757216436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1757216436
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.4190256058
Short name T104
Test name
Test status
Simulation time 659442518 ps
CPU time 18.3 seconds
Started May 16 03:29:42 PM PDT 24
Finished May 16 03:30:04 PM PDT 24
Peak memory 225416 kb
Host smart-9a89c5bd-f1a0-418d-babf-45b86a207b26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190256058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.4190256058
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2757773544
Short name T831
Test name
Test status
Simulation time 1254898021 ps
CPU time 9.11 seconds
Started May 16 03:29:42 PM PDT 24
Finished May 16 03:29:55 PM PDT 24
Peak memory 225928 kb
Host smart-5f75b8ef-f538-47e8-93eb-d8141b94f0fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757773544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2757773544
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.2752101436
Short name T251
Test name
Test status
Simulation time 1722925286 ps
CPU time 9.9 seconds
Started May 16 03:29:42 PM PDT 24
Finished May 16 03:29:56 PM PDT 24
Peak memory 217776 kb
Host smart-bb5a4388-3cae-4260-bc39-cd00bc341344
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752101436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.2
752101436
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2660143876
Short name T644
Test name
Test status
Simulation time 209215563 ps
CPU time 8.2 seconds
Started May 16 03:29:43 PM PDT 24
Finished May 16 03:29:57 PM PDT 24
Peak memory 217900 kb
Host smart-1b249981-a6a4-4710-94cb-624ed136a029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660143876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2660143876
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.1929675806
Short name T586
Test name
Test status
Simulation time 26108734 ps
CPU time 2 seconds
Started May 16 03:29:32 PM PDT 24
Finished May 16 03:29:42 PM PDT 24
Peak memory 213764 kb
Host smart-bcd7ed14-b4bd-4686-a762-7b270fc4eacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929675806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.1929675806
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3589437408
Short name T565
Test name
Test status
Simulation time 264855347 ps
CPU time 27.51 seconds
Started May 16 03:29:32 PM PDT 24
Finished May 16 03:30:07 PM PDT 24
Peak memory 250808 kb
Host smart-e1f84a1d-6037-4350-91c3-c0304f1a1104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589437408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3589437408
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1636680648
Short name T107
Test name
Test status
Simulation time 129206789 ps
CPU time 8.79 seconds
Started May 16 03:29:31 PM PDT 24
Finished May 16 03:29:48 PM PDT 24
Peak memory 250704 kb
Host smart-69349807-b339-42f7-b9a3-1c2cd6f58790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636680648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1636680648
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.4287357304
Short name T188
Test name
Test status
Simulation time 4136525780 ps
CPU time 202.27 seconds
Started May 16 03:29:40 PM PDT 24
Finished May 16 03:33:06 PM PDT 24
Peak memory 271360 kb
Host smart-7a1faf5d-b2b5-4e4c-a7d1-96e4a8367571
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287357304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.4287357304
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.943501599
Short name T105
Test name
Test status
Simulation time 52406997989 ps
CPU time 2093.46 seconds
Started May 16 03:29:42 PM PDT 24
Finished May 16 04:04:40 PM PDT 24
Peak memory 644248 kb
Host smart-b73f41c7-1ac4-42f2-8c5c-4d609f8f724b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=943501599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.943501599
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2779672195
Short name T23
Test name
Test status
Simulation time 15137368 ps
CPU time 0.92 seconds
Started May 16 03:29:29 PM PDT 24
Finished May 16 03:29:37 PM PDT 24
Peak memory 211460 kb
Host smart-4ea63ae2-b535-4b13-b41a-42c8e9328e3a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779672195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2779672195
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.170345914
Short name T485
Test name
Test status
Simulation time 187662495 ps
CPU time 1.03 seconds
Started May 16 03:31:35 PM PDT 24
Finished May 16 03:31:43 PM PDT 24
Peak memory 209420 kb
Host smart-9d966ac0-d75b-45c3-9d73-5c56a446cf41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170345914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.170345914
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.3064168008
Short name T240
Test name
Test status
Simulation time 329939792 ps
CPU time 9.86 seconds
Started May 16 03:31:31 PM PDT 24
Finished May 16 03:31:47 PM PDT 24
Peak memory 217944 kb
Host smart-e56cde3a-5852-454a-bf37-af29feaa5c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064168008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3064168008
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1087271565
Short name T701
Test name
Test status
Simulation time 427113133 ps
CPU time 7.71 seconds
Started May 16 03:31:40 PM PDT 24
Finished May 16 03:31:53 PM PDT 24
Peak memory 209440 kb
Host smart-3431a520-b963-42c8-b140-a173312dca1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087271565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1087271565
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.912455130
Short name T12
Test name
Test status
Simulation time 93906054 ps
CPU time 3.13 seconds
Started May 16 03:31:35 PM PDT 24
Finished May 16 03:31:45 PM PDT 24
Peak memory 217916 kb
Host smart-466fbfd3-8c5c-4a93-a295-821f73310a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912455130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.912455130
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1152015427
Short name T319
Test name
Test status
Simulation time 952090368 ps
CPU time 11.76 seconds
Started May 16 03:31:34 PM PDT 24
Finished May 16 03:31:52 PM PDT 24
Peak memory 217840 kb
Host smart-c42e50fb-597f-442d-8c91-973fe732701c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152015427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1152015427
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3661749824
Short name T521
Test name
Test status
Simulation time 628320086 ps
CPU time 8.84 seconds
Started May 16 03:31:35 PM PDT 24
Finished May 16 03:31:50 PM PDT 24
Peak memory 217824 kb
Host smart-4088485a-0044-4996-8123-4af25bc281f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661749824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3661749824
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.1294447850
Short name T650
Test name
Test status
Simulation time 1101369985 ps
CPU time 8.86 seconds
Started May 16 03:31:33 PM PDT 24
Finished May 16 03:31:48 PM PDT 24
Peak memory 217888 kb
Host smart-3d665238-16df-487f-8e2f-eb0117bb6cff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294447850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
1294447850
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3783200132
Short name T643
Test name
Test status
Simulation time 3542513000 ps
CPU time 6.91 seconds
Started May 16 03:31:38 PM PDT 24
Finished May 16 03:31:51 PM PDT 24
Peak memory 218132 kb
Host smart-e448dd61-062b-4f81-bf20-87c1c21b065e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783200132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3783200132
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1297819422
Short name T731
Test name
Test status
Simulation time 243618096 ps
CPU time 2.03 seconds
Started May 16 03:31:32 PM PDT 24
Finished May 16 03:31:40 PM PDT 24
Peak memory 213852 kb
Host smart-118f4520-fe7a-49ce-9178-fcc36928787c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297819422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1297819422
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.2764415616
Short name T255
Test name
Test status
Simulation time 251886040 ps
CPU time 28.68 seconds
Started May 16 03:31:33 PM PDT 24
Finished May 16 03:32:09 PM PDT 24
Peak memory 250872 kb
Host smart-c3655891-f24b-4775-ac02-174bd9d68202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764415616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.2764415616
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.644041181
Short name T579
Test name
Test status
Simulation time 67159242 ps
CPU time 7.88 seconds
Started May 16 03:31:33 PM PDT 24
Finished May 16 03:31:47 PM PDT 24
Peak memory 250780 kb
Host smart-271bd1d4-e3fc-4658-9751-ad1c361bec70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644041181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.644041181
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1333337990
Short name T38
Test name
Test status
Simulation time 43532789971 ps
CPU time 465.08 seconds
Started May 16 03:31:34 PM PDT 24
Finished May 16 03:39:26 PM PDT 24
Peak memory 267464 kb
Host smart-93e6dbe4-b30c-4b5e-b743-b993290bb5ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333337990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1333337990
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3773347971
Short name T452
Test name
Test status
Simulation time 21202836 ps
CPU time 0.95 seconds
Started May 16 03:31:38 PM PDT 24
Finished May 16 03:31:45 PM PDT 24
Peak memory 211508 kb
Host smart-f4592bde-d548-4fc3-83e2-a14648fcc731
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773347971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3773347971
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.769427219
Short name T477
Test name
Test status
Simulation time 26688829 ps
CPU time 0.87 seconds
Started May 16 03:31:44 PM PDT 24
Finished May 16 03:31:51 PM PDT 24
Peak memory 209352 kb
Host smart-3581cf21-49c8-488a-bbb1-981176ad34e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769427219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.769427219
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2658328739
Short name T647
Test name
Test status
Simulation time 831101014 ps
CPU time 11.68 seconds
Started May 16 03:31:37 PM PDT 24
Finished May 16 03:31:55 PM PDT 24
Peak memory 217748 kb
Host smart-ea5cf0df-0aea-420c-832b-f6a9ac46cd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658328739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2658328739
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2975453708
Short name T414
Test name
Test status
Simulation time 171777000 ps
CPU time 1.45 seconds
Started May 16 03:31:36 PM PDT 24
Finished May 16 03:31:44 PM PDT 24
Peak memory 216800 kb
Host smart-e0e7a1c3-987f-47c6-969c-103b90008f5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2975453708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2975453708
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.153214123
Short name T827
Test name
Test status
Simulation time 30467247 ps
CPU time 2.18 seconds
Started May 16 03:31:32 PM PDT 24
Finished May 16 03:31:41 PM PDT 24
Peak memory 217808 kb
Host smart-661c0c96-1fac-4d41-9237-d8e5f928c1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153214123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.153214123
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.849399657
Short name T608
Test name
Test status
Simulation time 1042517575 ps
CPU time 13.43 seconds
Started May 16 03:31:34 PM PDT 24
Finished May 16 03:31:54 PM PDT 24
Peak memory 225936 kb
Host smart-d489070b-e696-49c7-8ab0-77b9d5158adb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849399657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.849399657
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2122837994
Short name T270
Test name
Test status
Simulation time 455204475 ps
CPU time 12.66 seconds
Started May 16 03:31:36 PM PDT 24
Finished May 16 03:31:55 PM PDT 24
Peak memory 217860 kb
Host smart-95628dfe-fe85-4e43-8618-c42dabdd7393
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122837994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2122837994
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.2841377977
Short name T306
Test name
Test status
Simulation time 1512536271 ps
CPU time 8.54 seconds
Started May 16 03:31:35 PM PDT 24
Finished May 16 03:31:50 PM PDT 24
Peak memory 217904 kb
Host smart-68195f93-73b8-42ad-aa2e-d7ac424abe1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841377977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
2841377977
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.625891724
Short name T100
Test name
Test status
Simulation time 589179532 ps
CPU time 7.55 seconds
Started May 16 03:31:36 PM PDT 24
Finished May 16 03:31:50 PM PDT 24
Peak memory 217936 kb
Host smart-1f82e51e-c5d9-4041-bd94-a6df68755cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625891724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.625891724
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.3414707179
Short name T725
Test name
Test status
Simulation time 77441067 ps
CPU time 1.82 seconds
Started May 16 03:31:38 PM PDT 24
Finished May 16 03:31:46 PM PDT 24
Peak memory 217600 kb
Host smart-5f7cbcde-2db3-4677-ac4f-44ac7eff67fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414707179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.3414707179
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1429134327
Short name T56
Test name
Test status
Simulation time 204863616 ps
CPU time 21.96 seconds
Started May 16 03:31:33 PM PDT 24
Finished May 16 03:32:02 PM PDT 24
Peak memory 250792 kb
Host smart-835202c2-3125-45fc-86cd-2f3576c45da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429134327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1429134327
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.4174467377
Short name T481
Test name
Test status
Simulation time 221710421 ps
CPU time 7.79 seconds
Started May 16 03:31:40 PM PDT 24
Finished May 16 03:31:53 PM PDT 24
Peak memory 246912 kb
Host smart-117feddb-bf8b-40ba-a6da-0437c1e61cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174467377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.4174467377
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1436315269
Short name T456
Test name
Test status
Simulation time 3849917236 ps
CPU time 51.89 seconds
Started May 16 03:31:46 PM PDT 24
Finished May 16 03:32:44 PM PDT 24
Peak memory 226052 kb
Host smart-8b1bb406-a0d8-4f88-ac6c-9272a1c9b3fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436315269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1436315269
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1962087314
Short name T552
Test name
Test status
Simulation time 24271253 ps
CPU time 1.04 seconds
Started May 16 03:31:44 PM PDT 24
Finished May 16 03:31:50 PM PDT 24
Peak memory 209392 kb
Host smart-5aea95af-d4cf-4bf3-838d-516791e235be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962087314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1962087314
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2263424791
Short name T444
Test name
Test status
Simulation time 399240578 ps
CPU time 13.33 seconds
Started May 16 03:31:48 PM PDT 24
Finished May 16 03:32:08 PM PDT 24
Peak memory 217844 kb
Host smart-49626e39-8c81-4580-a967-23fb47436684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263424791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2263424791
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1497325494
Short name T35
Test name
Test status
Simulation time 1501120712 ps
CPU time 16.13 seconds
Started May 16 03:31:45 PM PDT 24
Finished May 16 03:32:08 PM PDT 24
Peak memory 209416 kb
Host smart-c11a6dcd-3b3a-430d-9eae-1e74f97f6471
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497325494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1497325494
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.384972819
Short name T614
Test name
Test status
Simulation time 195953222 ps
CPU time 2.37 seconds
Started May 16 03:31:49 PM PDT 24
Finished May 16 03:31:57 PM PDT 24
Peak memory 217868 kb
Host smart-32689c80-111a-4881-ad88-a68f40878b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384972819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.384972819
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2342368697
Short name T476
Test name
Test status
Simulation time 345740179 ps
CPU time 10.72 seconds
Started May 16 03:31:47 PM PDT 24
Finished May 16 03:32:04 PM PDT 24
Peak memory 225936 kb
Host smart-c22f5996-0cab-477c-a893-e9856398244d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342368697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2342368697
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3558374868
Short name T295
Test name
Test status
Simulation time 211534935 ps
CPU time 9.01 seconds
Started May 16 03:31:49 PM PDT 24
Finished May 16 03:32:04 PM PDT 24
Peak memory 217920 kb
Host smart-5d0eae8d-ad7f-4f31-8af6-69d1aa92359a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558374868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3558374868
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1246891104
Short name T451
Test name
Test status
Simulation time 654197739 ps
CPU time 10.02 seconds
Started May 16 03:31:46 PM PDT 24
Finished May 16 03:32:02 PM PDT 24
Peak memory 217916 kb
Host smart-4a1e76a9-cc79-4d98-912f-727885cb8a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246891104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1246891104
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2588550782
Short name T83
Test name
Test status
Simulation time 447786973 ps
CPU time 3.69 seconds
Started May 16 03:31:45 PM PDT 24
Finished May 16 03:31:55 PM PDT 24
Peak memory 217656 kb
Host smart-d22fc06b-8f0b-4b0b-8d25-d328e71dbb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588550782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2588550782
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.194156286
Short name T727
Test name
Test status
Simulation time 555699319 ps
CPU time 24.47 seconds
Started May 16 03:31:47 PM PDT 24
Finished May 16 03:32:18 PM PDT 24
Peak memory 250620 kb
Host smart-5542f875-67f9-4744-aba7-d6d6603ad7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194156286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.194156286
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.4204633300
Short name T361
Test name
Test status
Simulation time 99098954 ps
CPU time 6.88 seconds
Started May 16 03:31:46 PM PDT 24
Finished May 16 03:31:59 PM PDT 24
Peak memory 248404 kb
Host smart-5de85ea9-19f9-48b3-bb4a-40111d4f498d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204633300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.4204633300
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.478327764
Short name T619
Test name
Test status
Simulation time 33011361124 ps
CPU time 281.96 seconds
Started May 16 03:31:44 PM PDT 24
Finished May 16 03:36:31 PM PDT 24
Peak memory 315640 kb
Host smart-253a9d5c-fa06-44e5-b028-33972291b0f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478327764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.478327764
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.169575354
Short name T800
Test name
Test status
Simulation time 13393249 ps
CPU time 0.89 seconds
Started May 16 03:31:48 PM PDT 24
Finished May 16 03:31:55 PM PDT 24
Peak memory 211416 kb
Host smart-fb3517da-6eac-4bad-9ffc-4533ced0eb03
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169575354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ct
rl_volatile_unlock_smoke.169575354
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2146310209
Short name T363
Test name
Test status
Simulation time 24085096 ps
CPU time 0.99 seconds
Started May 16 03:31:43 PM PDT 24
Finished May 16 03:31:49 PM PDT 24
Peak memory 209432 kb
Host smart-4f385420-7003-458d-8e8b-bb382bba7185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146310209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2146310209
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.298807537
Short name T738
Test name
Test status
Simulation time 290167914 ps
CPU time 13.26 seconds
Started May 16 03:31:50 PM PDT 24
Finished May 16 03:32:10 PM PDT 24
Peak memory 217944 kb
Host smart-d951f996-7264-4dcf-bead-2db1dc7225cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298807537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.298807537
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.1311664068
Short name T801
Test name
Test status
Simulation time 2374578037 ps
CPU time 10.35 seconds
Started May 16 03:31:46 PM PDT 24
Finished May 16 03:32:03 PM PDT 24
Peak memory 209496 kb
Host smart-78e32563-be04-47f0-818b-c73292338913
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311664068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.1311664068
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1536058929
Short name T40
Test name
Test status
Simulation time 190767058 ps
CPU time 2.86 seconds
Started May 16 03:31:44 PM PDT 24
Finished May 16 03:31:53 PM PDT 24
Peak memory 217896 kb
Host smart-c6c13d9f-1222-4f53-89e4-1b0cfcddd9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536058929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1536058929
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.1673397998
Short name T772
Test name
Test status
Simulation time 1623046555 ps
CPU time 12.77 seconds
Started May 16 03:31:45 PM PDT 24
Finished May 16 03:32:04 PM PDT 24
Peak memory 225984 kb
Host smart-7ddc7fca-73cc-4f60-99fe-9415b32c1720
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673397998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1673397998
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.118350689
Short name T812
Test name
Test status
Simulation time 718366713 ps
CPU time 12.69 seconds
Started May 16 03:31:47 PM PDT 24
Finished May 16 03:32:07 PM PDT 24
Peak memory 225876 kb
Host smart-dc4ee819-e794-475f-a965-11be7885fea6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118350689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_di
gest.118350689
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.413244875
Short name T698
Test name
Test status
Simulation time 425696493 ps
CPU time 14.04 seconds
Started May 16 03:31:47 PM PDT 24
Finished May 16 03:32:08 PM PDT 24
Peak memory 217896 kb
Host smart-0dab1468-7c8d-411b-a908-0a3049643ab8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413244875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.413244875
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.617819482
Short name T677
Test name
Test status
Simulation time 547776191 ps
CPU time 7.37 seconds
Started May 16 03:31:46 PM PDT 24
Finished May 16 03:32:00 PM PDT 24
Peak memory 217996 kb
Host smart-83a4e81b-2903-4661-ba0c-f9cd5b1e8e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617819482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.617819482
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3245498196
Short name T195
Test name
Test status
Simulation time 60192310 ps
CPU time 2.6 seconds
Started May 16 03:31:44 PM PDT 24
Finished May 16 03:31:53 PM PDT 24
Peak memory 213928 kb
Host smart-bf1d49f2-baab-4a1e-ac6d-c68b3a68482f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245498196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3245498196
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.4137779264
Short name T845
Test name
Test status
Simulation time 458936379 ps
CPU time 27.17 seconds
Started May 16 03:31:45 PM PDT 24
Finished May 16 03:32:18 PM PDT 24
Peak memory 250796 kb
Host smart-987edb2b-8699-4db8-a609-66c8f4b51ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137779264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.4137779264
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.4230900537
Short name T177
Test name
Test status
Simulation time 75323945 ps
CPU time 3.41 seconds
Started May 16 03:31:52 PM PDT 24
Finished May 16 03:32:02 PM PDT 24
Peak memory 222092 kb
Host smart-85b2d125-5160-4841-ac7d-47a2769db888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230900537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.4230900537
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.647026013
Short name T482
Test name
Test status
Simulation time 20959446212 ps
CPU time 76.15 seconds
Started May 16 03:31:44 PM PDT 24
Finished May 16 03:33:06 PM PDT 24
Peak memory 242764 kb
Host smart-5f3d19e1-ea01-468d-950a-04baf539cfdd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647026013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.647026013
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.424355189
Short name T113
Test name
Test status
Simulation time 13873180869 ps
CPU time 302.1 seconds
Started May 16 03:31:47 PM PDT 24
Finished May 16 03:36:56 PM PDT 24
Peak memory 283792 kb
Host smart-8d06b4ad-3aa3-4a05-932c-4dc90c4cc60e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=424355189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.424355189
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3344284923
Short name T417
Test name
Test status
Simulation time 68508871 ps
CPU time 0.93 seconds
Started May 16 03:31:47 PM PDT 24
Finished May 16 03:31:54 PM PDT 24
Peak memory 212472 kb
Host smart-f7d09063-a33e-489c-99e2-fd8c7dd21eee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344284923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3344284923
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3434138244
Short name T665
Test name
Test status
Simulation time 22959562 ps
CPU time 1.28 seconds
Started May 16 03:31:47 PM PDT 24
Finished May 16 03:31:55 PM PDT 24
Peak memory 209492 kb
Host smart-116aed49-13ef-432a-b845-95b44fb50685
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434138244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3434138244
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2982547702
Short name T612
Test name
Test status
Simulation time 698244882 ps
CPU time 11.78 seconds
Started May 16 03:31:45 PM PDT 24
Finished May 16 03:32:03 PM PDT 24
Peak memory 217840 kb
Host smart-eef177c7-1dc3-4487-90c0-de08b9ee562d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982547702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2982547702
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2375974952
Short name T364
Test name
Test status
Simulation time 90077210 ps
CPU time 1.62 seconds
Started May 16 03:31:48 PM PDT 24
Finished May 16 03:31:56 PM PDT 24
Peak memory 209316 kb
Host smart-1be33c99-2227-4750-b6ce-5db08cd135c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375974952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2375974952
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.2983351246
Short name T830
Test name
Test status
Simulation time 75855428 ps
CPU time 2.34 seconds
Started May 16 03:31:45 PM PDT 24
Finished May 16 03:31:53 PM PDT 24
Peak memory 217892 kb
Host smart-b1a18ec0-e713-4426-a4cb-22146028bf39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983351246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.2983351246
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1707964758
Short name T762
Test name
Test status
Simulation time 2345955440 ps
CPU time 16.08 seconds
Started May 16 03:31:46 PM PDT 24
Finished May 16 03:32:08 PM PDT 24
Peak memory 218908 kb
Host smart-99cdc472-b3ab-43b0-b928-38a030987a0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707964758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1707964758
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.793707022
Short name T542
Test name
Test status
Simulation time 2156234027 ps
CPU time 11.49 seconds
Started May 16 03:31:49 PM PDT 24
Finished May 16 03:32:07 PM PDT 24
Peak memory 217900 kb
Host smart-17632467-5a9c-4adc-8b27-cef15f1349da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793707022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.793707022
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.498819919
Short name T520
Test name
Test status
Simulation time 175260906 ps
CPU time 7.74 seconds
Started May 16 03:31:47 PM PDT 24
Finished May 16 03:32:01 PM PDT 24
Peak memory 217884 kb
Host smart-ff6e5ed0-580e-4e41-987b-94af3f26d044
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498819919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.498819919
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.930599760
Short name T805
Test name
Test status
Simulation time 336491910 ps
CPU time 9.29 seconds
Started May 16 03:31:47 PM PDT 24
Finished May 16 03:32:03 PM PDT 24
Peak memory 217924 kb
Host smart-ddaa68ba-7cb2-478c-883f-78d3efdc318a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930599760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.930599760
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2063682192
Short name T575
Test name
Test status
Simulation time 22862212 ps
CPU time 1.64 seconds
Started May 16 03:31:47 PM PDT 24
Finished May 16 03:31:55 PM PDT 24
Peak memory 213408 kb
Host smart-d7489bf5-205c-4aef-9186-73d10ccaca91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063682192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2063682192
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.780116206
Short name T658
Test name
Test status
Simulation time 442374723 ps
CPU time 21.9 seconds
Started May 16 03:31:50 PM PDT 24
Finished May 16 03:32:18 PM PDT 24
Peak memory 250820 kb
Host smart-1fd0b8ae-401b-4ca5-9dff-b0fa0e7b3701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780116206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.780116206
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3248473214
Short name T308
Test name
Test status
Simulation time 275377305 ps
CPU time 8.21 seconds
Started May 16 03:31:46 PM PDT 24
Finished May 16 03:32:00 PM PDT 24
Peak memory 250388 kb
Host smart-6024c679-8a32-4f3c-bac2-b4624f3f2c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248473214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3248473214
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.3207012950
Short name T880
Test name
Test status
Simulation time 734065266040 ps
CPU time 667.79 seconds
Started May 16 03:31:47 PM PDT 24
Finished May 16 03:43:01 PM PDT 24
Peak memory 251016 kb
Host smart-80de1c5e-13dd-4d1c-8ff4-dd76e67a23c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207012950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.3207012950
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.2767844741
Short name T150
Test name
Test status
Simulation time 29717784666 ps
CPU time 223.78 seconds
Started May 16 03:31:48 PM PDT 24
Finished May 16 03:35:39 PM PDT 24
Peak memory 422016 kb
Host smart-4f3a36b6-fd0e-4319-a0d6-64c7516202b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2767844741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.2767844741
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1319520003
Short name T276
Test name
Test status
Simulation time 12742574 ps
CPU time 1.05 seconds
Started May 16 03:31:44 PM PDT 24
Finished May 16 03:31:50 PM PDT 24
Peak memory 211476 kb
Host smart-bbcfd3c4-febb-4f7a-b7f9-a5d8c7e7032d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319520003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.1319520003
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2361980490
Short name T526
Test name
Test status
Simulation time 24763323 ps
CPU time 0.88 seconds
Started May 16 03:31:54 PM PDT 24
Finished May 16 03:32:02 PM PDT 24
Peak memory 209308 kb
Host smart-8b48c8ff-6766-4646-a098-f30d8748ecc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361980490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2361980490
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.299275142
Short name T535
Test name
Test status
Simulation time 296470107 ps
CPU time 10.17 seconds
Started May 16 03:31:54 PM PDT 24
Finished May 16 03:32:11 PM PDT 24
Peak memory 217844 kb
Host smart-141093b5-0515-450b-8c60-ccfae293cc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299275142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.299275142
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1506902343
Short name T672
Test name
Test status
Simulation time 1284726001 ps
CPU time 8.85 seconds
Started May 16 03:31:58 PM PDT 24
Finished May 16 03:32:17 PM PDT 24
Peak memory 209396 kb
Host smart-2285b225-005c-4e90-b249-65a3dd2be9cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506902343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1506902343
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.411341286
Short name T865
Test name
Test status
Simulation time 54277714 ps
CPU time 2.59 seconds
Started May 16 03:31:44 PM PDT 24
Finished May 16 03:31:52 PM PDT 24
Peak memory 217864 kb
Host smart-b496ed2d-b219-41d5-acbd-2028b35d60fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411341286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.411341286
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2004445768
Short name T690
Test name
Test status
Simulation time 622336791 ps
CPU time 14.3 seconds
Started May 16 03:31:58 PM PDT 24
Finished May 16 03:32:22 PM PDT 24
Peak memory 225900 kb
Host smart-63dff459-1b56-44c8-a3f6-a12f83b83ee8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004445768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2004445768
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.4107281935
Short name T472
Test name
Test status
Simulation time 788070147 ps
CPU time 15.45 seconds
Started May 16 03:31:57 PM PDT 24
Finished May 16 03:32:22 PM PDT 24
Peak memory 225948 kb
Host smart-94608fad-4cac-4801-9d46-70016cc48c36
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107281935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.4107281935
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2939988925
Short name T475
Test name
Test status
Simulation time 323088271 ps
CPU time 8.75 seconds
Started May 16 03:31:56 PM PDT 24
Finished May 16 03:32:15 PM PDT 24
Peak memory 217932 kb
Host smart-c8bc2194-59e2-475a-a178-245d50a2556b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939988925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2939988925
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.2830600727
Short name T568
Test name
Test status
Simulation time 236474574 ps
CPU time 8.28 seconds
Started May 16 03:31:55 PM PDT 24
Finished May 16 03:32:13 PM PDT 24
Peak memory 217992 kb
Host smart-e93f6d39-e9c8-4fd8-bfc2-f2750890c3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830600727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.2830600727
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3451070284
Short name T770
Test name
Test status
Simulation time 39550145 ps
CPU time 2.18 seconds
Started May 16 03:31:48 PM PDT 24
Finished May 16 03:31:56 PM PDT 24
Peak memory 213804 kb
Host smart-a65b2552-5a35-4865-ab6f-4c3345a507ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451070284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3451070284
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.878507565
Short name T671
Test name
Test status
Simulation time 1042406393 ps
CPU time 25.91 seconds
Started May 16 03:31:43 PM PDT 24
Finished May 16 03:32:14 PM PDT 24
Peak memory 250824 kb
Host smart-88cff27a-968c-4715-bc46-5bf4d8774e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878507565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.878507565
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.770377440
Short name T697
Test name
Test status
Simulation time 152180259 ps
CPU time 3.17 seconds
Started May 16 03:31:49 PM PDT 24
Finished May 16 03:31:58 PM PDT 24
Peak memory 217760 kb
Host smart-b202e8dc-cebb-4a78-a9e5-56b382fa06c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770377440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.770377440
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1011579009
Short name T582
Test name
Test status
Simulation time 16329640698 ps
CPU time 62.72 seconds
Started May 16 03:31:57 PM PDT 24
Finished May 16 03:33:09 PM PDT 24
Peak memory 225920 kb
Host smart-deda6a7d-2601-4ece-8584-747a1e069810
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011579009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1011579009
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.4004885281
Short name T162
Test name
Test status
Simulation time 41823108264 ps
CPU time 847.5 seconds
Started May 16 03:31:56 PM PDT 24
Finished May 16 03:46:13 PM PDT 24
Peak memory 540432 kb
Host smart-a7f7026e-0063-46bc-b431-fa506bf2b1a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4004885281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.4004885281
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.384684282
Short name T824
Test name
Test status
Simulation time 14507035 ps
CPU time 0.86 seconds
Started May 16 03:31:45 PM PDT 24
Finished May 16 03:31:52 PM PDT 24
Peak memory 211392 kb
Host smart-dff25556-719d-4f87-a793-996e90735800
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384684282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.384684282
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3749647267
Short name T432
Test name
Test status
Simulation time 14370208 ps
CPU time 0.97 seconds
Started May 16 03:31:57 PM PDT 24
Finished May 16 03:32:07 PM PDT 24
Peak memory 209432 kb
Host smart-0c449d56-78a0-4af6-85d4-6b73742bca56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749647267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3749647267
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2452733287
Short name T620
Test name
Test status
Simulation time 424388669 ps
CPU time 16.35 seconds
Started May 16 03:31:58 PM PDT 24
Finished May 16 03:32:24 PM PDT 24
Peak memory 217816 kb
Host smart-f48e5cf4-64b8-4f75-ab8a-6ef2dc7ab1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452733287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2452733287
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1207048265
Short name T34
Test name
Test status
Simulation time 2482558066 ps
CPU time 17.78 seconds
Started May 16 03:31:56 PM PDT 24
Finished May 16 03:32:23 PM PDT 24
Peak memory 209564 kb
Host smart-b8c60d5b-cec5-426e-9fdb-8bc26276c068
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207048265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1207048265
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.1276481843
Short name T342
Test name
Test status
Simulation time 238169439 ps
CPU time 2.62 seconds
Started May 16 03:31:53 PM PDT 24
Finished May 16 03:32:03 PM PDT 24
Peak memory 217908 kb
Host smart-87e4986f-ac62-46b5-a938-0b38ebfc942b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276481843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.1276481843
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.781702498
Short name T96
Test name
Test status
Simulation time 623399344 ps
CPU time 12.46 seconds
Started May 16 03:31:57 PM PDT 24
Finished May 16 03:32:20 PM PDT 24
Peak memory 218784 kb
Host smart-c5f1d00c-bbb3-4b4c-9bf3-df69a5725947
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781702498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.781702498
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.388966323
Short name T273
Test name
Test status
Simulation time 727103488 ps
CPU time 8.48 seconds
Started May 16 03:31:53 PM PDT 24
Finished May 16 03:32:09 PM PDT 24
Peak memory 217876 kb
Host smart-d3fd8403-8b56-4077-a4c2-8bbaf255ef70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388966323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di
gest.388966323
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3795550232
Short name T304
Test name
Test status
Simulation time 1073955577 ps
CPU time 9.68 seconds
Started May 16 03:31:55 PM PDT 24
Finished May 16 03:32:14 PM PDT 24
Peak memory 217836 kb
Host smart-fad254d0-856d-480f-95ca-33482298897b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795550232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3795550232
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.626491541
Short name T497
Test name
Test status
Simulation time 595647185 ps
CPU time 8.42 seconds
Started May 16 03:31:55 PM PDT 24
Finished May 16 03:32:13 PM PDT 24
Peak memory 217920 kb
Host smart-d8a85166-8f80-4244-a412-6d39173f4716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626491541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.626491541
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1462820711
Short name T374
Test name
Test status
Simulation time 120556758 ps
CPU time 1.71 seconds
Started May 16 03:31:56 PM PDT 24
Finished May 16 03:32:07 PM PDT 24
Peak memory 217632 kb
Host smart-5653c431-107d-416e-80d7-d37dd94297c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462820711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1462820711
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2111834009
Short name T241
Test name
Test status
Simulation time 279999124 ps
CPU time 26.77 seconds
Started May 16 03:31:58 PM PDT 24
Finished May 16 03:32:35 PM PDT 24
Peak memory 250796 kb
Host smart-67330668-6923-41ae-b0c4-a6185daff6b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111834009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2111834009
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2228402080
Short name T480
Test name
Test status
Simulation time 80662973 ps
CPU time 3.4 seconds
Started May 16 03:31:56 PM PDT 24
Finished May 16 03:32:08 PM PDT 24
Peak memory 222544 kb
Host smart-38546a70-c454-428e-9639-51cd0be14938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228402080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2228402080
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.4239377873
Short name T874
Test name
Test status
Simulation time 2097705060 ps
CPU time 78.19 seconds
Started May 16 03:31:55 PM PDT 24
Finished May 16 03:33:23 PM PDT 24
Peak memory 267256 kb
Host smart-a6a27049-c277-4e36-b60e-73cbd32d01fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239377873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.4239377873
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.854858363
Short name T175
Test name
Test status
Simulation time 46657757 ps
CPU time 0.98 seconds
Started May 16 03:31:56 PM PDT 24
Finished May 16 03:32:06 PM PDT 24
Peak memory 211468 kb
Host smart-0f850874-05e1-4ead-a757-401b5e7aa4d4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854858363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ct
rl_volatile_unlock_smoke.854858363
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.45366125
Short name T808
Test name
Test status
Simulation time 87813921 ps
CPU time 1.06 seconds
Started May 16 03:31:57 PM PDT 24
Finished May 16 03:32:09 PM PDT 24
Peak memory 209336 kb
Host smart-ef0647fa-c9c0-429b-bb75-784523a92f80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45366125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.45366125
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2357600346
Short name T16
Test name
Test status
Simulation time 204936829 ps
CPU time 10.19 seconds
Started May 16 03:31:57 PM PDT 24
Finished May 16 03:32:18 PM PDT 24
Peak memory 217788 kb
Host smart-3761ad68-cb42-4564-a1c0-83dedcd493ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357600346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2357600346
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3345073028
Short name T460
Test name
Test status
Simulation time 262353471 ps
CPU time 3.19 seconds
Started May 16 03:31:54 PM PDT 24
Finished May 16 03:32:05 PM PDT 24
Peak memory 209524 kb
Host smart-faa4f95c-a04e-4034-94eb-abcc209a91ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345073028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3345073028
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1795056381
Short name T779
Test name
Test status
Simulation time 334620600 ps
CPU time 3.05 seconds
Started May 16 03:31:58 PM PDT 24
Finished May 16 03:32:11 PM PDT 24
Peak memory 217952 kb
Host smart-f478f7a5-be77-41fb-a509-2fc991e5e453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795056381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1795056381
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2571530983
Short name T657
Test name
Test status
Simulation time 1002541016 ps
CPU time 11.27 seconds
Started May 16 03:31:53 PM PDT 24
Finished May 16 03:32:12 PM PDT 24
Peak memory 225912 kb
Host smart-0599a0e2-38ec-4d29-89f8-c978c0b5f7e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571530983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2571530983
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2364586415
Short name T588
Test name
Test status
Simulation time 791600918 ps
CPU time 8.05 seconds
Started May 16 03:31:56 PM PDT 24
Finished May 16 03:32:14 PM PDT 24
Peak memory 217864 kb
Host smart-e1ae8e79-f4d0-4f95-af08-34df9aa6a14b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364586415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2364586415
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.3731689012
Short name T734
Test name
Test status
Simulation time 603720996 ps
CPU time 10.56 seconds
Started May 16 03:31:58 PM PDT 24
Finished May 16 03:32:19 PM PDT 24
Peak memory 217880 kb
Host smart-5a6b6288-0959-4b8b-9d71-60b3a4ba7fa5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731689012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
3731689012
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.305281865
Short name T344
Test name
Test status
Simulation time 863765235 ps
CPU time 10.76 seconds
Started May 16 03:31:55 PM PDT 24
Finished May 16 03:32:14 PM PDT 24
Peak memory 217960 kb
Host smart-1541fad7-2f90-49d8-954c-8c0058887632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305281865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.305281865
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.567876440
Short name T806
Test name
Test status
Simulation time 481769311 ps
CPU time 7.95 seconds
Started May 16 03:31:53 PM PDT 24
Finished May 16 03:32:08 PM PDT 24
Peak memory 217668 kb
Host smart-5c677c0e-3ba1-4ba0-a29a-259cbd5aa69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567876440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.567876440
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.22977903
Short name T318
Test name
Test status
Simulation time 404532947 ps
CPU time 25.31 seconds
Started May 16 03:31:57 PM PDT 24
Finished May 16 03:32:32 PM PDT 24
Peak memory 247440 kb
Host smart-666c5eea-2ba4-41e6-adff-3aabff501a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22977903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.22977903
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2850304164
Short name T172
Test name
Test status
Simulation time 194417963 ps
CPU time 3.19 seconds
Started May 16 03:31:54 PM PDT 24
Finished May 16 03:32:05 PM PDT 24
Peak memory 222348 kb
Host smart-5801c7ff-e309-4648-aee4-61ce8ebe61ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850304164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2850304164
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1231799572
Short name T406
Test name
Test status
Simulation time 17124039 ps
CPU time 0.97 seconds
Started May 16 03:31:54 PM PDT 24
Finished May 16 03:32:03 PM PDT 24
Peak memory 212496 kb
Host smart-cdae020c-4a7f-4a9b-948d-ea442f15a456
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231799572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1231799572
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3659745648
Short name T868
Test name
Test status
Simulation time 19054437 ps
CPU time 1.16 seconds
Started May 16 03:31:56 PM PDT 24
Finished May 16 03:32:06 PM PDT 24
Peak memory 209544 kb
Host smart-47eed2e5-798f-409d-8909-c606837a9b02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659745648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3659745648
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2949891257
Short name T303
Test name
Test status
Simulation time 475039959 ps
CPU time 16.17 seconds
Started May 16 03:31:58 PM PDT 24
Finished May 16 03:32:24 PM PDT 24
Peak memory 217788 kb
Host smart-7224e232-b37a-40e5-a004-a24039de1461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949891257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2949891257
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.759229468
Short name T9
Test name
Test status
Simulation time 119885539 ps
CPU time 3.75 seconds
Started May 16 03:31:56 PM PDT 24
Finished May 16 03:32:09 PM PDT 24
Peak memory 209464 kb
Host smart-1f0e6f88-77db-47c7-9fa2-b86421d5ef50
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759229468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.759229468
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.1158713739
Short name T660
Test name
Test status
Simulation time 74916769 ps
CPU time 2.97 seconds
Started May 16 03:31:52 PM PDT 24
Finished May 16 03:32:02 PM PDT 24
Peak memory 217840 kb
Host smart-03e6ac44-9f7c-436d-add4-18bc11649c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158713739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.1158713739
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1989378852
Short name T339
Test name
Test status
Simulation time 2127423208 ps
CPU time 15.5 seconds
Started May 16 03:31:57 PM PDT 24
Finished May 16 03:32:22 PM PDT 24
Peak memory 217964 kb
Host smart-a752da50-a18a-4656-ac79-a02a4db33d8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989378852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1989378852
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.258620406
Short name T866
Test name
Test status
Simulation time 271553123 ps
CPU time 8.47 seconds
Started May 16 03:31:59 PM PDT 24
Finished May 16 03:32:17 PM PDT 24
Peak memory 217800 kb
Host smart-fb91d54a-6dcb-4e01-84b8-9634f19a9eee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=258620406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.258620406
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.4059582263
Short name T24
Test name
Test status
Simulation time 7035395006 ps
CPU time 10.41 seconds
Started May 16 03:31:54 PM PDT 24
Finished May 16 03:32:12 PM PDT 24
Peak memory 217988 kb
Host smart-7c1790cd-fab9-483a-9ad7-fa34f3097fb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059582263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
4059582263
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2626672671
Short name T458
Test name
Test status
Simulation time 635260528 ps
CPU time 12.93 seconds
Started May 16 03:32:01 PM PDT 24
Finished May 16 03:32:25 PM PDT 24
Peak memory 217828 kb
Host smart-73637e37-9d47-4f59-8560-06f1090baf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626672671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2626672671
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2987260028
Short name T601
Test name
Test status
Simulation time 180874813 ps
CPU time 2.05 seconds
Started May 16 03:31:58 PM PDT 24
Finished May 16 03:32:10 PM PDT 24
Peak memory 213492 kb
Host smart-1f81bc93-fa7e-44cd-85cd-d4ac5005889c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987260028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2987260028
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2093402093
Short name T600
Test name
Test status
Simulation time 1566214511 ps
CPU time 26.73 seconds
Started May 16 03:31:57 PM PDT 24
Finished May 16 03:32:33 PM PDT 24
Peak memory 250644 kb
Host smart-638ead18-6173-444e-b067-189c52216876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093402093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2093402093
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3225793154
Short name T202
Test name
Test status
Simulation time 104611626 ps
CPU time 7.16 seconds
Started May 16 03:31:54 PM PDT 24
Finished May 16 03:32:09 PM PDT 24
Peak memory 250344 kb
Host smart-b558534c-73a3-4fa6-8f07-e5fe9d3e3c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225793154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3225793154
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3572345904
Short name T638
Test name
Test status
Simulation time 3223890752 ps
CPU time 30.35 seconds
Started May 16 03:31:57 PM PDT 24
Finished May 16 03:32:37 PM PDT 24
Peak memory 250912 kb
Host smart-b26690f9-05c2-4067-9260-b02301d5696f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572345904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3572345904
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.2927906416
Short name T193
Test name
Test status
Simulation time 38221535944 ps
CPU time 868.93 seconds
Started May 16 03:31:55 PM PDT 24
Finished May 16 03:46:32 PM PDT 24
Peak memory 444012 kb
Host smart-0d34f529-a2c5-4f71-aa51-1a689c77b85a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2927906416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.2927906416
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.2418457558
Short name T224
Test name
Test status
Simulation time 37495619 ps
CPU time 0.85 seconds
Started May 16 03:31:55 PM PDT 24
Finished May 16 03:32:05 PM PDT 24
Peak memory 211512 kb
Host smart-a80d7277-c010-4e30-b410-771b59c603a4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418457558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.2418457558
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2979300420
Short name T391
Test name
Test status
Simulation time 66504666 ps
CPU time 0.88 seconds
Started May 16 03:32:01 PM PDT 24
Finished May 16 03:32:12 PM PDT 24
Peak memory 209332 kb
Host smart-b8d21af9-3e14-4cdb-b608-eba6716dabb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979300420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2979300420
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.4117275492
Short name T704
Test name
Test status
Simulation time 4415597282 ps
CPU time 16.54 seconds
Started May 16 03:31:55 PM PDT 24
Finished May 16 03:32:21 PM PDT 24
Peak memory 218180 kb
Host smart-96b911bd-f5fa-4c38-9027-c08b01b55f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117275492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.4117275492
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.364253768
Short name T190
Test name
Test status
Simulation time 3583809838 ps
CPU time 10 seconds
Started May 16 03:31:55 PM PDT 24
Finished May 16 03:32:14 PM PDT 24
Peak memory 217808 kb
Host smart-1d41357a-21c3-4d16-a6c9-b345a8e7fbe6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364253768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.364253768
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.665813135
Short name T615
Test name
Test status
Simulation time 186515201 ps
CPU time 3.34 seconds
Started May 16 03:31:56 PM PDT 24
Finished May 16 03:32:09 PM PDT 24
Peak memory 217972 kb
Host smart-3c7483f7-f4eb-4de1-8cf5-044df34bb14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665813135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.665813135
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.2641549234
Short name T749
Test name
Test status
Simulation time 673315648 ps
CPU time 12.53 seconds
Started May 16 03:31:53 PM PDT 24
Finished May 16 03:32:13 PM PDT 24
Peak memory 226020 kb
Host smart-1d7b009b-c92f-46a7-aff0-cccd5baeb551
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641549234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.2641549234
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.3937538474
Short name T184
Test name
Test status
Simulation time 1235163979 ps
CPU time 7.83 seconds
Started May 16 03:31:57 PM PDT 24
Finished May 16 03:32:15 PM PDT 24
Peak memory 217860 kb
Host smart-e1913c36-d992-4092-9693-45540077f569
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937538474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.3937538474
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.3276403911
Short name T639
Test name
Test status
Simulation time 1267057265 ps
CPU time 8.23 seconds
Started May 16 03:31:57 PM PDT 24
Finished May 16 03:32:16 PM PDT 24
Peak memory 217788 kb
Host smart-83e5f3bb-6122-427b-8e55-0f1f8dd99563
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276403911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
3276403911
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.985041527
Short name T283
Test name
Test status
Simulation time 484677762 ps
CPU time 10.21 seconds
Started May 16 03:31:57 PM PDT 24
Finished May 16 03:32:17 PM PDT 24
Peak memory 217892 kb
Host smart-cce1eb88-c15e-469d-be7e-535aa49f7c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985041527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.985041527
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.4034207319
Short name T604
Test name
Test status
Simulation time 16782769 ps
CPU time 1.1 seconds
Started May 16 03:31:55 PM PDT 24
Finished May 16 03:32:05 PM PDT 24
Peak memory 211692 kb
Host smart-917c6032-5bc0-476e-83d7-95001a0b5c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034207319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.4034207319
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.149984101
Short name T859
Test name
Test status
Simulation time 835480732 ps
CPU time 28.19 seconds
Started May 16 03:31:57 PM PDT 24
Finished May 16 03:32:35 PM PDT 24
Peak memory 250892 kb
Host smart-45057cbd-ffe7-446b-9f6d-aa402239660c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149984101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.149984101
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1560192005
Short name T312
Test name
Test status
Simulation time 55044456 ps
CPU time 7.77 seconds
Started May 16 03:32:02 PM PDT 24
Finished May 16 03:32:20 PM PDT 24
Peak memory 250744 kb
Host smart-9eb03029-8fb0-4515-adfb-96535b838fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560192005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1560192005
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.3252459371
Short name T320
Test name
Test status
Simulation time 26125536748 ps
CPU time 155.69 seconds
Started May 16 03:32:01 PM PDT 24
Finished May 16 03:34:48 PM PDT 24
Peak memory 283620 kb
Host smart-338477e3-ea3e-49f8-a8f5-1042ea2069eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252459371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.3252459371
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3636553003
Short name T756
Test name
Test status
Simulation time 69544715 ps
CPU time 1.01 seconds
Started May 16 03:31:57 PM PDT 24
Finished May 16 03:32:07 PM PDT 24
Peak memory 212476 kb
Host smart-44217f7d-95b6-4501-945a-2f5c40bd752f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636553003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3636553003
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3577062439
Short name T178
Test name
Test status
Simulation time 17158859 ps
CPU time 1.1 seconds
Started May 16 03:29:42 PM PDT 24
Finished May 16 03:29:49 PM PDT 24
Peak memory 209372 kb
Host smart-ee196f77-f31e-4a3c-a984-d24648f46483
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577062439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3577062439
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.4288879305
Short name T43
Test name
Test status
Simulation time 389906536 ps
CPU time 13.94 seconds
Started May 16 03:29:43 PM PDT 24
Finished May 16 03:30:03 PM PDT 24
Peak memory 217776 kb
Host smart-5fa8b4d5-a86f-4b41-819b-a5c703dac20a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288879305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.4288879305
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2083448415
Short name T29
Test name
Test status
Simulation time 4882388482 ps
CPU time 6.23 seconds
Started May 16 03:29:42 PM PDT 24
Finished May 16 03:29:53 PM PDT 24
Peak memory 209648 kb
Host smart-a678b01e-9131-4999-83ad-2721248d3500
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083448415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2083448415
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1942643238
Short name T356
Test name
Test status
Simulation time 10119800658 ps
CPU time 40.38 seconds
Started May 16 03:29:46 PM PDT 24
Finished May 16 03:30:33 PM PDT 24
Peak memory 218408 kb
Host smart-1d925557-0fe0-464c-9ba1-76a62aac5125
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942643238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1942643238
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2470678330
Short name T728
Test name
Test status
Simulation time 1140197110 ps
CPU time 13.86 seconds
Started May 16 03:29:45 PM PDT 24
Finished May 16 03:30:06 PM PDT 24
Peak memory 217292 kb
Host smart-12916356-c49e-4c47-b083-fbd0e890ee40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470678330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
470678330
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1707129209
Short name T160
Test name
Test status
Simulation time 901657707 ps
CPU time 8.2 seconds
Started May 16 03:29:42 PM PDT 24
Finished May 16 03:29:55 PM PDT 24
Peak memory 217832 kb
Host smart-be9bb190-5265-422c-b576-97b3dfdee8bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707129209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1707129209
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2013636206
Short name T176
Test name
Test status
Simulation time 825629377 ps
CPU time 13.38 seconds
Started May 16 03:29:47 PM PDT 24
Finished May 16 03:30:08 PM PDT 24
Peak memory 212944 kb
Host smart-b440f309-754b-4e5d-be67-b983594f974a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013636206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2013636206
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.391062714
Short name T37
Test name
Test status
Simulation time 897907567 ps
CPU time 4.17 seconds
Started May 16 03:29:45 PM PDT 24
Finished May 16 03:29:57 PM PDT 24
Peak memory 213012 kb
Host smart-648431c2-a14f-4515-84b9-297acd7a1cf9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391062714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.391062714
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3841931179
Short name T531
Test name
Test status
Simulation time 5271226109 ps
CPU time 63.64 seconds
Started May 16 03:29:41 PM PDT 24
Finished May 16 03:30:48 PM PDT 24
Peak memory 275476 kb
Host smart-70472056-b97d-46dd-bc88-e629fbe4d184
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841931179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3841931179
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2240248154
Short name T795
Test name
Test status
Simulation time 477785967 ps
CPU time 14.02 seconds
Started May 16 03:29:46 PM PDT 24
Finished May 16 03:30:07 PM PDT 24
Peak memory 250756 kb
Host smart-5861181b-9e7b-4969-8bd4-94e75bac1f82
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240248154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2240248154
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1920496296
Short name T872
Test name
Test status
Simulation time 290461080 ps
CPU time 3.59 seconds
Started May 16 03:29:47 PM PDT 24
Finished May 16 03:29:58 PM PDT 24
Peak memory 217920 kb
Host smart-43d5a817-e727-4370-919b-aaabd0d61e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920496296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1920496296
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.315940007
Short name T765
Test name
Test status
Simulation time 238801332 ps
CPU time 8.59 seconds
Started May 16 03:29:45 PM PDT 24
Finished May 16 03:30:01 PM PDT 24
Peak memory 217628 kb
Host smart-3d402398-ea09-41d4-a2c6-6e8fa9726ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315940007 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.315940007
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.607665505
Short name T694
Test name
Test status
Simulation time 1215105859 ps
CPU time 14.55 seconds
Started May 16 03:29:43 PM PDT 24
Finished May 16 03:30:03 PM PDT 24
Peak memory 217844 kb
Host smart-c4913726-7c08-4b29-89cb-6711f2cc70da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607665505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.607665505
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.1225448618
Short name T854
Test name
Test status
Simulation time 385973575 ps
CPU time 7.5 seconds
Started May 16 03:29:46 PM PDT 24
Finished May 16 03:30:01 PM PDT 24
Peak memory 224924 kb
Host smart-d1203adc-44b5-4092-8d83-94392d322b91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225448618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.1225448618
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1770240779
Short name T809
Test name
Test status
Simulation time 1082882309 ps
CPU time 9.99 seconds
Started May 16 03:29:43 PM PDT 24
Finished May 16 03:29:58 PM PDT 24
Peak memory 217840 kb
Host smart-fd3fb467-2eed-4d40-a0de-98ae6d05a1a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770240779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
770240779
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1226715994
Short name T788
Test name
Test status
Simulation time 201017826 ps
CPU time 6.1 seconds
Started May 16 03:29:41 PM PDT 24
Finished May 16 03:29:52 PM PDT 24
Peak memory 217916 kb
Host smart-9eb6d262-fd80-4940-80ab-13ff659795d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226715994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1226715994
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2180751212
Short name T412
Test name
Test status
Simulation time 519098132 ps
CPU time 11.06 seconds
Started May 16 03:29:40 PM PDT 24
Finished May 16 03:29:55 PM PDT 24
Peak memory 217656 kb
Host smart-74eea874-6bbb-426c-b58c-a362cc685563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180751212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2180751212
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.2701056334
Short name T684
Test name
Test status
Simulation time 482836229 ps
CPU time 29.04 seconds
Started May 16 03:29:43 PM PDT 24
Finished May 16 03:30:19 PM PDT 24
Peak memory 246404 kb
Host smart-0cd34431-748c-4e54-889c-5a48a8d18299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701056334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2701056334
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2097142894
Short name T555
Test name
Test status
Simulation time 347689550 ps
CPU time 8.72 seconds
Started May 16 03:29:41 PM PDT 24
Finished May 16 03:29:54 PM PDT 24
Peak memory 250844 kb
Host smart-28bf2635-3441-4bd1-bb92-bb99ff6992e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097142894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2097142894
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1375091005
Short name T881
Test name
Test status
Simulation time 16093917024 ps
CPU time 381.33 seconds
Started May 16 03:29:46 PM PDT 24
Finished May 16 03:36:15 PM PDT 24
Peak memory 311308 kb
Host smart-e3de3b3c-50ec-4bd6-9a88-df5c55071d88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375091005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1375091005
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2059720697
Short name T234
Test name
Test status
Simulation time 49226180 ps
CPU time 0.76 seconds
Started May 16 03:29:44 PM PDT 24
Finished May 16 03:29:51 PM PDT 24
Peak memory 207816 kb
Host smart-58a47473-bdac-43d6-a672-251ed84acf02
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059720697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2059720697
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3798765282
Short name T518
Test name
Test status
Simulation time 36502262 ps
CPU time 1.17 seconds
Started May 16 03:29:49 PM PDT 24
Finished May 16 03:29:58 PM PDT 24
Peak memory 209348 kb
Host smart-c65d05c6-0b7e-4e45-98f5-7d937717b585
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798765282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3798765282
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.634655523
Short name T227
Test name
Test status
Simulation time 18509020 ps
CPU time 0.84 seconds
Started May 16 03:29:47 PM PDT 24
Finished May 16 03:29:56 PM PDT 24
Peak memory 209300 kb
Host smart-2dc8a827-5c1c-441d-bec9-71fb3bf63728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634655523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.634655523
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.618134220
Short name T714
Test name
Test status
Simulation time 4080394373 ps
CPU time 14.69 seconds
Started May 16 03:29:45 PM PDT 24
Finished May 16 03:30:07 PM PDT 24
Peak memory 218936 kb
Host smart-86301fff-c008-4d34-b926-b8f0e83c7f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618134220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.618134220
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1074057803
Short name T382
Test name
Test status
Simulation time 2496762916 ps
CPU time 6.25 seconds
Started May 16 03:29:45 PM PDT 24
Finished May 16 03:29:58 PM PDT 24
Peak memory 217324 kb
Host smart-a9c71a92-6aad-4613-b228-fe53413c5f0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074057803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1074057803
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.1304082760
Short name T410
Test name
Test status
Simulation time 18416758646 ps
CPU time 96.28 seconds
Started May 16 03:29:45 PM PDT 24
Finished May 16 03:31:29 PM PDT 24
Peak memory 218880 kb
Host smart-d953eda6-844f-4fa7-858c-3a0167cd5fbf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304082760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.1304082760
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2290982463
Short name T538
Test name
Test status
Simulation time 945285423 ps
CPU time 3.76 seconds
Started May 16 03:29:44 PM PDT 24
Finished May 16 03:29:55 PM PDT 24
Peak memory 216960 kb
Host smart-afd058a2-45d8-43ee-ac79-db6cb3f9bc2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290982463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.2
290982463
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2594735082
Short name T97
Test name
Test status
Simulation time 2380696248 ps
CPU time 9.38 seconds
Started May 16 03:29:40 PM PDT 24
Finished May 16 03:29:53 PM PDT 24
Peak memory 217836 kb
Host smart-05fffeb6-061b-4e73-9266-7297b482c98c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594735082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2594735082
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2598711809
Short name T782
Test name
Test status
Simulation time 1832368119 ps
CPU time 14.77 seconds
Started May 16 03:29:44 PM PDT 24
Finished May 16 03:30:06 PM PDT 24
Peak memory 213008 kb
Host smart-7881c3d5-4147-4088-8b7a-99e7cdaf840b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598711809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2598711809
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3462187037
Short name T289
Test name
Test status
Simulation time 742955886 ps
CPU time 7.45 seconds
Started May 16 03:29:46 PM PDT 24
Finished May 16 03:30:00 PM PDT 24
Peak memory 213644 kb
Host smart-48333b23-7735-4859-9409-8e6fe6eef656
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462187037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3462187037
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2638783268
Short name T380
Test name
Test status
Simulation time 19543845391 ps
CPU time 59.5 seconds
Started May 16 03:29:46 PM PDT 24
Finished May 16 03:30:52 PM PDT 24
Peak memory 251540 kb
Host smart-7c6e089a-7f96-4ca5-b8f1-fed60f2edcae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638783268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2638783268
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.699878093
Short name T867
Test name
Test status
Simulation time 2464562343 ps
CPU time 18.81 seconds
Started May 16 03:29:48 PM PDT 24
Finished May 16 03:30:14 PM PDT 24
Peak memory 245936 kb
Host smart-84586af4-fd3c-4a35-afeb-a2055533fb2e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699878093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.699878093
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3325517201
Short name T668
Test name
Test status
Simulation time 116028199 ps
CPU time 5.08 seconds
Started May 16 03:29:45 PM PDT 24
Finished May 16 03:29:57 PM PDT 24
Peak memory 217832 kb
Host smart-53387859-8009-42b4-8121-e4bbc5b82b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325517201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3325517201
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1195286282
Short name T627
Test name
Test status
Simulation time 278216992 ps
CPU time 9.52 seconds
Started May 16 03:29:48 PM PDT 24
Finished May 16 03:30:05 PM PDT 24
Peak memory 217632 kb
Host smart-ab09c7b3-94da-45f3-b35b-783910a14a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195286282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1195286282
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.2273314369
Short name T496
Test name
Test status
Simulation time 425253839 ps
CPU time 10.76 seconds
Started May 16 03:29:47 PM PDT 24
Finished May 16 03:30:06 PM PDT 24
Peak memory 225932 kb
Host smart-89ce956a-608f-422e-8e53-f1e9a3eb2949
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273314369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.2273314369
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3962396721
Short name T18
Test name
Test status
Simulation time 8029735059 ps
CPU time 24.63 seconds
Started May 16 03:29:54 PM PDT 24
Finished May 16 03:30:26 PM PDT 24
Peak memory 226076 kb
Host smart-61f8c2f5-15c7-4723-a3e6-de21c402e031
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962396721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3962396721
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.704900869
Short name T501
Test name
Test status
Simulation time 848936957 ps
CPU time 10.18 seconds
Started May 16 03:30:02 PM PDT 24
Finished May 16 03:30:22 PM PDT 24
Peak memory 217836 kb
Host smart-fc0f50fb-38ef-4dc6-a320-e35e28ede203
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704900869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.704900869
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.699157170
Short name T338
Test name
Test status
Simulation time 443182114 ps
CPU time 9.23 seconds
Started May 16 03:29:45 PM PDT 24
Finished May 16 03:30:02 PM PDT 24
Peak memory 224728 kb
Host smart-00c1cf49-d319-4201-a324-a9cd8b797dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699157170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.699157170
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.2378785933
Short name T550
Test name
Test status
Simulation time 33016237 ps
CPU time 1.49 seconds
Started May 16 03:29:46 PM PDT 24
Finished May 16 03:29:55 PM PDT 24
Peak memory 213316 kb
Host smart-8645db34-25aa-4681-9b60-a265e04448c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378785933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.2378785933
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1252363874
Short name T709
Test name
Test status
Simulation time 2720646619 ps
CPU time 31.3 seconds
Started May 16 03:29:46 PM PDT 24
Finished May 16 03:30:24 PM PDT 24
Peak memory 250992 kb
Host smart-565018de-084e-4da3-8b0a-36cef9575b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252363874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1252363874
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.561175894
Short name T259
Test name
Test status
Simulation time 247143156 ps
CPU time 6.83 seconds
Started May 16 03:29:45 PM PDT 24
Finished May 16 03:29:59 PM PDT 24
Peak memory 246508 kb
Host smart-5a50f26f-7b4d-40d6-94a4-ccd767aa59ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561175894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.561175894
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.562975272
Short name T67
Test name
Test status
Simulation time 99563634474 ps
CPU time 386.42 seconds
Started May 16 03:29:47 PM PDT 24
Finished May 16 03:36:21 PM PDT 24
Peak memory 283704 kb
Host smart-327492e5-63c5-40ba-8fd5-3df652ed81bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562975272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.562975272
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3705637134
Short name T530
Test name
Test status
Simulation time 17596667 ps
CPU time 0.94 seconds
Started May 16 03:29:44 PM PDT 24
Finished May 16 03:29:52 PM PDT 24
Peak memory 211524 kb
Host smart-53eb474e-ffa6-42d0-a1bf-a92f14c8aefb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705637134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3705637134
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3777105181
Short name T431
Test name
Test status
Simulation time 16607685 ps
CPU time 1.11 seconds
Started May 16 03:30:00 PM PDT 24
Finished May 16 03:30:11 PM PDT 24
Peak memory 209412 kb
Host smart-d2552aa4-ece0-4274-aa7a-8b73b7950cea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777105181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3777105181
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.2281803266
Short name T158
Test name
Test status
Simulation time 48721144 ps
CPU time 0.79 seconds
Started May 16 03:30:01 PM PDT 24
Finished May 16 03:30:11 PM PDT 24
Peak memory 209332 kb
Host smart-c8b41820-1e05-46b9-a74e-8b66500c089f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281803266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.2281803266
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2659631323
Short name T17
Test name
Test status
Simulation time 2116148694 ps
CPU time 12.84 seconds
Started May 16 03:29:48 PM PDT 24
Finished May 16 03:30:09 PM PDT 24
Peak memory 217860 kb
Host smart-f3aa080c-e3a7-4d9c-969b-598dc32e8752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659631323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2659631323
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.115829486
Short name T629
Test name
Test status
Simulation time 697325821 ps
CPU time 7.21 seconds
Started May 16 03:29:58 PM PDT 24
Finished May 16 03:30:13 PM PDT 24
Peak memory 216916 kb
Host smart-9e240e6a-7ecf-4221-a392-30b40810b0bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115829486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.115829486
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.824659746
Short name T775
Test name
Test status
Simulation time 5022781486 ps
CPU time 74.9 seconds
Started May 16 03:29:57 PM PDT 24
Finished May 16 03:31:20 PM PDT 24
Peak memory 219256 kb
Host smart-6f539c9e-6116-435b-932f-030a8bca778b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824659746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_err
ors.824659746
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2357531267
Short name T569
Test name
Test status
Simulation time 334676177 ps
CPU time 2.79 seconds
Started May 16 03:29:59 PM PDT 24
Finished May 16 03:30:10 PM PDT 24
Peak memory 217064 kb
Host smart-66a74b77-d37e-4362-9b95-63e2b3017123
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357531267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
357531267
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1438594855
Short name T611
Test name
Test status
Simulation time 459552709 ps
CPU time 5.6 seconds
Started May 16 03:29:51 PM PDT 24
Finished May 16 03:30:04 PM PDT 24
Peak memory 217848 kb
Host smart-fbe0ea0f-abb4-402f-9e6e-548f97476705
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438594855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1438594855
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1869846675
Short name T450
Test name
Test status
Simulation time 1103745503 ps
CPU time 28.46 seconds
Started May 16 03:29:53 PM PDT 24
Finished May 16 03:30:29 PM PDT 24
Peak memory 213104 kb
Host smart-d32dd5f3-ca90-4c1f-8f4a-402f6d937789
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869846675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1869846675
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3129033608
Short name T292
Test name
Test status
Simulation time 675348070 ps
CPU time 5.13 seconds
Started May 16 03:29:56 PM PDT 24
Finished May 16 03:30:09 PM PDT 24
Peak memory 213212 kb
Host smart-f516624d-2d14-49e6-ac41-03d2e0141aa0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129033608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3129033608
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.1966844827
Short name T743
Test name
Test status
Simulation time 2985086835 ps
CPU time 55.22 seconds
Started May 16 03:29:53 PM PDT 24
Finished May 16 03:30:56 PM PDT 24
Peak memory 267724 kb
Host smart-02efe934-f55c-41e9-b54f-14979bb12201
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966844827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.1966844827
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.868517667
Short name T761
Test name
Test status
Simulation time 776603499 ps
CPU time 12.95 seconds
Started May 16 03:29:56 PM PDT 24
Finished May 16 03:30:16 PM PDT 24
Peak memory 250800 kb
Host smart-3e1e376a-5cbc-4c86-97d9-be220705eec8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868517667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_state_post_trans.868517667
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.262656695
Short name T300
Test name
Test status
Simulation time 302253887 ps
CPU time 3.14 seconds
Started May 16 03:30:01 PM PDT 24
Finished May 16 03:30:14 PM PDT 24
Peak memory 217912 kb
Host smart-8321c0be-adc3-429b-827b-0cac370ad4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262656695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.262656695
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1445892673
Short name T362
Test name
Test status
Simulation time 1393263564 ps
CPU time 21.24 seconds
Started May 16 03:29:52 PM PDT 24
Finished May 16 03:30:20 PM PDT 24
Peak memory 214392 kb
Host smart-c7a9fedd-cfb5-4a83-a3d6-92eda2d0fb3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445892673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1445892673
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.3385401684
Short name T468
Test name
Test status
Simulation time 1381075892 ps
CPU time 13.74 seconds
Started May 16 03:29:56 PM PDT 24
Finished May 16 03:30:16 PM PDT 24
Peak memory 217872 kb
Host smart-0297f807-ce6a-4d8a-8167-140608e3753f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385401684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.3385401684
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.2892839106
Short name T333
Test name
Test status
Simulation time 196848292 ps
CPU time 9.21 seconds
Started May 16 03:29:59 PM PDT 24
Finished May 16 03:30:18 PM PDT 24
Peak memory 225940 kb
Host smart-637889c0-7096-43d2-bab9-53da6e437baa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892839106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.2892839106
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.2955055382
Short name T634
Test name
Test status
Simulation time 3723491329 ps
CPU time 23.23 seconds
Started May 16 03:29:47 PM PDT 24
Finished May 16 03:30:18 PM PDT 24
Peak memory 217984 kb
Host smart-94f5e2d0-05ad-4ffd-90ca-30bb4d8952e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955055382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.2
955055382
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.3017873531
Short name T427
Test name
Test status
Simulation time 679622764 ps
CPU time 13.57 seconds
Started May 16 03:29:50 PM PDT 24
Finished May 16 03:30:11 PM PDT 24
Peak memory 217944 kb
Host smart-1c84750e-a26e-4aa7-b291-9d28b9d1140f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017873531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.3017873531
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.4174995493
Short name T84
Test name
Test status
Simulation time 34642139 ps
CPU time 2.57 seconds
Started May 16 03:29:57 PM PDT 24
Finished May 16 03:30:07 PM PDT 24
Peak memory 214068 kb
Host smart-e5647daf-e778-4757-a5ab-12a899c81c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174995493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.4174995493
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3599543558
Short name T584
Test name
Test status
Simulation time 231944446 ps
CPU time 25.15 seconds
Started May 16 03:29:52 PM PDT 24
Finished May 16 03:30:24 PM PDT 24
Peak memory 250844 kb
Host smart-69e9a9c9-35ff-452d-b84d-cb198af9c975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3599543558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3599543558
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2707759079
Short name T829
Test name
Test status
Simulation time 95671220 ps
CPU time 10.06 seconds
Started May 16 03:29:47 PM PDT 24
Finished May 16 03:30:04 PM PDT 24
Peak memory 250840 kb
Host smart-e027c921-e2a5-40af-94af-4ac417a038ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707759079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2707759079
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2753625399
Short name T583
Test name
Test status
Simulation time 11198104162 ps
CPU time 73.82 seconds
Started May 16 03:29:52 PM PDT 24
Finished May 16 03:31:13 PM PDT 24
Peak memory 274420 kb
Host smart-74fcbcfc-7a07-4208-840f-d37108bc05d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753625399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2753625399
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1796146811
Short name T439
Test name
Test status
Simulation time 21383756 ps
CPU time 0.9 seconds
Started May 16 03:29:57 PM PDT 24
Finished May 16 03:30:05 PM PDT 24
Peak memory 211488 kb
Host smart-0a609812-4fbe-445f-aa0b-e9ed89a3a8a6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796146811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1796146811
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.4135356439
Short name T766
Test name
Test status
Simulation time 87840645 ps
CPU time 1.22 seconds
Started May 16 03:29:55 PM PDT 24
Finished May 16 03:30:03 PM PDT 24
Peak memory 209368 kb
Host smart-d143108f-69c3-448b-ad5a-254b8d1516e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135356439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.4135356439
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2712365323
Short name T171
Test name
Test status
Simulation time 30211443 ps
CPU time 0.92 seconds
Started May 16 03:29:51 PM PDT 24
Finished May 16 03:29:59 PM PDT 24
Peak memory 209448 kb
Host smart-cf66d09c-dfef-4f9f-ae62-db6c01e0f7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712365323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2712365323
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.4177475135
Short name T424
Test name
Test status
Simulation time 345664318 ps
CPU time 16.58 seconds
Started May 16 03:29:54 PM PDT 24
Finished May 16 03:30:18 PM PDT 24
Peak memory 217960 kb
Host smart-7b0f843b-4161-4460-b433-1628bdda4dc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177475135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.4177475135
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2705035088
Short name T804
Test name
Test status
Simulation time 906789789 ps
CPU time 12.86 seconds
Started May 16 03:30:00 PM PDT 24
Finished May 16 03:30:22 PM PDT 24
Peak memory 216936 kb
Host smart-02c35202-ece5-4ae2-ad75-b369685a1b17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705035088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2705035088
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2180275430
Short name T352
Test name
Test status
Simulation time 80371035989 ps
CPU time 112.99 seconds
Started May 16 03:29:58 PM PDT 24
Finished May 16 03:31:59 PM PDT 24
Peak memory 218476 kb
Host smart-958dd72f-1591-4800-95f5-f2d33dbf49ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180275430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2180275430
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2735725010
Short name T293
Test name
Test status
Simulation time 1776045645 ps
CPU time 5.15 seconds
Started May 16 03:29:59 PM PDT 24
Finished May 16 03:30:12 PM PDT 24
Peak memory 217580 kb
Host smart-a9835f53-f0ff-4e1a-a875-22d4841bb46d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735725010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
735725010
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.1410200228
Short name T837
Test name
Test status
Simulation time 1097882281 ps
CPU time 8.26 seconds
Started May 16 03:30:00 PM PDT 24
Finished May 16 03:30:17 PM PDT 24
Peak memory 217832 kb
Host smart-99e18587-3cb4-4960-b761-6d07a5bfd88a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410200228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.1410200228
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.351963890
Short name T792
Test name
Test status
Simulation time 2249945697 ps
CPU time 15.4 seconds
Started May 16 03:29:52 PM PDT 24
Finished May 16 03:30:14 PM PDT 24
Peak memory 213208 kb
Host smart-ab4e84d5-47a1-473b-9209-1309123b9100
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351963890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_regwen_during_op.351963890
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.2787356923
Short name T585
Test name
Test status
Simulation time 3106784766 ps
CPU time 94.51 seconds
Started May 16 03:30:01 PM PDT 24
Finished May 16 03:31:46 PM PDT 24
Peak memory 282604 kb
Host smart-86b0732b-f451-49dc-9c50-397af905dfab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787356923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.2787356923
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.902297625
Short name T238
Test name
Test status
Simulation time 7793510146 ps
CPU time 12.24 seconds
Started May 16 03:29:49 PM PDT 24
Finished May 16 03:30:09 PM PDT 24
Peak memory 250840 kb
Host smart-0dd4a1d3-62eb-4515-88b3-ecb0d601221b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902297625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.902297625
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2048231507
Short name T541
Test name
Test status
Simulation time 101926687 ps
CPU time 2.3 seconds
Started May 16 03:29:58 PM PDT 24
Finished May 16 03:30:08 PM PDT 24
Peak memory 217880 kb
Host smart-5b9c1032-ba30-4d37-8b70-7d8d5dd1c6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048231507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2048231507
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.720546321
Short name T787
Test name
Test status
Simulation time 460411184 ps
CPU time 15.96 seconds
Started May 16 03:29:49 PM PDT 24
Finished May 16 03:30:12 PM PDT 24
Peak memory 217640 kb
Host smart-433039db-4846-4a75-9d31-30ef24fce29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720546321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.720546321
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.2603254630
Short name T846
Test name
Test status
Simulation time 453679042 ps
CPU time 12.99 seconds
Started May 16 03:29:54 PM PDT 24
Finished May 16 03:30:14 PM PDT 24
Peak memory 218840 kb
Host smart-75624b2e-92d2-40ff-8d67-628d347faa41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603254630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.2603254630
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.777378399
Short name T401
Test name
Test status
Simulation time 1177252305 ps
CPU time 21.45 seconds
Started May 16 03:30:01 PM PDT 24
Finished May 16 03:30:33 PM PDT 24
Peak memory 225412 kb
Host smart-d1dc576a-040f-41d5-b324-c64a7e48feaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777378399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_dig
est.777378399
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.618346780
Short name T330
Test name
Test status
Simulation time 280517962 ps
CPU time 7.95 seconds
Started May 16 03:30:02 PM PDT 24
Finished May 16 03:30:20 PM PDT 24
Peak memory 217800 kb
Host smart-e6c6f51f-2988-46d0-8170-d23ab5849885
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618346780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.618346780
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1585990893
Short name T769
Test name
Test status
Simulation time 515116481 ps
CPU time 6.86 seconds
Started May 16 03:29:59 PM PDT 24
Finished May 16 03:30:14 PM PDT 24
Peak memory 217832 kb
Host smart-eb96e004-a87c-40d0-a2f1-2874a8e6a63d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585990893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1585990893
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2830102896
Short name T81
Test name
Test status
Simulation time 112239512 ps
CPU time 1.75 seconds
Started May 16 03:29:51 PM PDT 24
Finished May 16 03:30:00 PM PDT 24
Peak memory 213728 kb
Host smart-19ef9326-d6a9-43f9-8c16-e83bbe013599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830102896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2830102896
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3392135504
Short name T282
Test name
Test status
Simulation time 1034463764 ps
CPU time 24.49 seconds
Started May 16 03:29:51 PM PDT 24
Finished May 16 03:30:23 PM PDT 24
Peak memory 250872 kb
Host smart-3ad103bd-08ae-4be8-a110-21fa5c67901e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392135504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3392135504
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3716232564
Short name T345
Test name
Test status
Simulation time 48172355 ps
CPU time 2.67 seconds
Started May 16 03:29:52 PM PDT 24
Finished May 16 03:30:02 PM PDT 24
Peak memory 222100 kb
Host smart-e8d725a0-c03e-47c9-b8af-57d24b8727c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716232564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3716232564
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.2604976282
Short name T793
Test name
Test status
Simulation time 7712460937 ps
CPU time 127.23 seconds
Started May 16 03:29:53 PM PDT 24
Finished May 16 03:32:08 PM PDT 24
Peak memory 267512 kb
Host smart-a98eea04-5aac-48f0-8a39-0e976fef275b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604976282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.2604976282
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3168555852
Short name T663
Test name
Test status
Simulation time 141655665603 ps
CPU time 835.19 seconds
Started May 16 03:30:00 PM PDT 24
Finished May 16 03:44:04 PM PDT 24
Peak memory 356288 kb
Host smart-368f3279-43ef-4c69-a6e2-baca1b39587a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3168555852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3168555852
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.2440149596
Short name T666
Test name
Test status
Simulation time 45951411 ps
CPU time 0.85 seconds
Started May 16 03:29:52 PM PDT 24
Finished May 16 03:30:00 PM PDT 24
Peak memory 211408 kb
Host smart-c4b294ae-c3a1-4918-aa19-7514af7154f9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440149596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.2440149596
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3370501987
Short name T322
Test name
Test status
Simulation time 31979568 ps
CPU time 0.99 seconds
Started May 16 03:30:03 PM PDT 24
Finished May 16 03:30:15 PM PDT 24
Peak memory 209460 kb
Host smart-d51c62c9-ce4b-4e1f-8184-6339ef93521f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370501987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3370501987
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2727647580
Short name T225
Test name
Test status
Simulation time 30340341 ps
CPU time 0.89 seconds
Started May 16 03:29:55 PM PDT 24
Finished May 16 03:30:03 PM PDT 24
Peak memory 209356 kb
Host smart-02da472e-ddf5-40bd-a8cc-26fe1f70aea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727647580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2727647580
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1871089252
Short name T741
Test name
Test status
Simulation time 2479014957 ps
CPU time 14.77 seconds
Started May 16 03:29:47 PM PDT 24
Finished May 16 03:30:10 PM PDT 24
Peak memory 217936 kb
Host smart-3483dd01-2d32-4fec-97d4-072c3c7597cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871089252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1871089252
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3872301044
Short name T758
Test name
Test status
Simulation time 3738380855 ps
CPU time 7.49 seconds
Started May 16 03:30:04 PM PDT 24
Finished May 16 03:30:22 PM PDT 24
Peak memory 217628 kb
Host smart-bd2042f9-af6c-4087-80ea-e8f8f0f1e510
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872301044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3872301044
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3348030910
Short name T554
Test name
Test status
Simulation time 23767351791 ps
CPU time 43.04 seconds
Started May 16 03:30:02 PM PDT 24
Finished May 16 03:30:55 PM PDT 24
Peak memory 217944 kb
Host smart-ca9f0108-3f8a-426d-b9a1-a563202354ee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348030910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3348030910
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.785388701
Short name T796
Test name
Test status
Simulation time 4802450227 ps
CPU time 12.74 seconds
Started May 16 03:29:48 PM PDT 24
Finished May 16 03:30:08 PM PDT 24
Peak memory 217768 kb
Host smart-d4047279-8f55-4a70-904d-22bb437f90d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785388701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.785388701
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1101471515
Short name T335
Test name
Test status
Simulation time 692422350 ps
CPU time 9.57 seconds
Started May 16 03:30:02 PM PDT 24
Finished May 16 03:30:21 PM PDT 24
Peak memory 217804 kb
Host smart-fb463abb-fba7-4402-b26d-52359d5c6409
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101471515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1101471515
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.312656453
Short name T602
Test name
Test status
Simulation time 2718414495 ps
CPU time 10.77 seconds
Started May 16 03:29:55 PM PDT 24
Finished May 16 03:30:13 PM PDT 24
Peak memory 213132 kb
Host smart-a3daa3c4-5d0c-4176-8113-978d3f78de5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312656453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.312656453
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2159650854
Short name T196
Test name
Test status
Simulation time 1045555665 ps
CPU time 4.21 seconds
Started May 16 03:29:53 PM PDT 24
Finished May 16 03:30:04 PM PDT 24
Peak memory 213232 kb
Host smart-2dbfb0ad-3a03-4944-bf7f-b9e8be96ecdb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159650854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2159650854
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3283585008
Short name T664
Test name
Test status
Simulation time 7911366303 ps
CPU time 76.37 seconds
Started May 16 03:30:01 PM PDT 24
Finished May 16 03:31:27 PM PDT 24
Peak memory 276152 kb
Host smart-30c08d85-8f2f-41a0-a5f2-0f3e19a52a43
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283585008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3283585008
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2398935195
Short name T754
Test name
Test status
Simulation time 532128060 ps
CPU time 10.11 seconds
Started May 16 03:29:52 PM PDT 24
Finished May 16 03:30:10 PM PDT 24
Peak memory 221992 kb
Host smart-5960219e-8022-4326-8af6-2c49eae2d37f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398935195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2398935195
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.4088550554
Short name T649
Test name
Test status
Simulation time 52678543 ps
CPU time 3.02 seconds
Started May 16 03:29:51 PM PDT 24
Finished May 16 03:30:02 PM PDT 24
Peak memory 217836 kb
Host smart-030bdc73-4547-43e8-b369-1c1c79a7dc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088550554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.4088550554
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.664120542
Short name T65
Test name
Test status
Simulation time 679113555 ps
CPU time 15.79 seconds
Started May 16 03:30:05 PM PDT 24
Finished May 16 03:30:32 PM PDT 24
Peak memory 217656 kb
Host smart-e1b829f7-b91e-4536-a85c-4e76aa4c4068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664120542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.664120542
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.3753895650
Short name T696
Test name
Test status
Simulation time 257333805 ps
CPU time 11.41 seconds
Started May 16 03:30:05 PM PDT 24
Finished May 16 03:30:27 PM PDT 24
Peak memory 217776 kb
Host smart-c1f70249-f9dd-40f1-aca8-5a102ff670ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753895650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3753895650
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.113755405
Short name T316
Test name
Test status
Simulation time 230109685 ps
CPU time 7.99 seconds
Started May 16 03:30:00 PM PDT 24
Finished May 16 03:30:18 PM PDT 24
Peak memory 226068 kb
Host smart-2b9f9879-a75e-45a6-bcbf-c43993cb0f6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113755405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_dig
est.113755405
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2366492821
Short name T767
Test name
Test status
Simulation time 659328012 ps
CPU time 11.77 seconds
Started May 16 03:30:05 PM PDT 24
Finished May 16 03:30:28 PM PDT 24
Peak memory 217860 kb
Host smart-47236e6d-4106-4de0-929e-25759e031a32
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366492821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
366492821
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.4221052599
Short name T347
Test name
Test status
Simulation time 537054491 ps
CPU time 11.46 seconds
Started May 16 03:30:01 PM PDT 24
Finished May 16 03:30:22 PM PDT 24
Peak memory 217944 kb
Host smart-5cf24609-a7ae-4b34-ad82-5be57d0d021c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221052599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.4221052599
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.411244494
Short name T559
Test name
Test status
Simulation time 16093842 ps
CPU time 1.04 seconds
Started May 16 03:29:55 PM PDT 24
Finished May 16 03:30:03 PM PDT 24
Peak memory 212584 kb
Host smart-5c803c48-2483-4a05-826c-3e3f263eed0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411244494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.411244494
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.2896038590
Short name T566
Test name
Test status
Simulation time 321539863 ps
CPU time 27.03 seconds
Started May 16 03:29:49 PM PDT 24
Finished May 16 03:30:24 PM PDT 24
Peak memory 250628 kb
Host smart-d7e1951f-cabe-4f88-be37-f5b30361c1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896038590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.2896038590
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3441184515
Short name T245
Test name
Test status
Simulation time 1104870515 ps
CPU time 4.4 seconds
Started May 16 03:29:55 PM PDT 24
Finished May 16 03:30:06 PM PDT 24
Peak memory 226192 kb
Host smart-85704e3e-35f8-41d1-9c0e-429e11a80224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441184515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3441184515
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1738133358
Short name T693
Test name
Test status
Simulation time 22599134378 ps
CPU time 84.18 seconds
Started May 16 03:30:04 PM PDT 24
Finished May 16 03:31:39 PM PDT 24
Peak memory 277276 kb
Host smart-1fbedf96-f0de-451c-9a22-883742077606
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738133358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1738133358
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1578980939
Short name T156
Test name
Test status
Simulation time 17032194 ps
CPU time 0.97 seconds
Started May 16 03:30:00 PM PDT 24
Finished May 16 03:30:11 PM PDT 24
Peak memory 211572 kb
Host smart-3bb185ac-f787-4441-b7b6-cd3dd92a2715
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578980939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1578980939
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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