Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98177515

1

T1

5322

T2

33835

T3

5050

auto[1]

1355007

1

T1

693

T2

980

T3

198

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

98188252

1

T1

5223

T2

34031

T3

4951

auto[1]

1344270

1

T1

792

T2

784

T3

297

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7107899	1			T1	1438		T2	1722		T3	1272
auto[IdleSt]	21824888	1			T1	1275		T2	17976		T3	1258
auto[ClkMuxSt]	35495	1			T1	15		T2	18		T3	7
auto[CntIncrSt]	35148	1			T1	15		T2	18		T3	7
auto[CntProgSt]	1493141	1			T1	478		T2	357		T3	35
auto[TransCheckSt]	27155	1			T3	7		T10	10		T4	64
auto[TokenHashSt]	38136652	1			T3	241		T10	401		T4	562
auto[FlashRmaSt]	28846	1			T3	23		T10	32		T4	73
auto[TokenCheck0St]	12563	1			T3	7		T10	10		T4	20
auto[TokenCheck1St]	9394	1			T3	7		T10	10		T4	9
auto[TransProgSt]	398032	1			T3	29		T10	20		T4	15
auto[PostTransSt]	13114360	1			T1	833		T2	7827		T3	1131
auto[ScrapSt]	172648	1			T5	2204		T11	6062		T17	38
auto[EscalateSt]	6469633	1			T1	1961		T2	6897		T3	820
auto[InvalidSt]	10664837	1			T3	404		T10	214		T5	364467

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1831	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10664837	1			T3	404		T10	214		T5	364467
EscalateSt	6469633	1			T1	1961		T2	6897		T3	820
ScrapSt	172648	1			T5	2204		T11	6062		T17	38
PostTransSt	13114360	1			T1	833		T2	7827		T3	1131
TransProgSt	398032	1			T3	29		T10	20		T4	15
TokenCheck1St	9394	1			T3	7		T10	10		T4	9
TokenCheck0St	12563	1			T3	7		T10	10		T4	20
FlashRmaSt	28846	1			T3	23		T10	32		T4	73
TokenHashSt	38136652	1			T3	241		T10	401		T4	562
TransCheckSt	27155	1			T3	7		T10	10		T4	64
CntProgSt	1493141	1			T1	478		T2	357		T3	35
CntIncrSt	35148	1			T1	15		T2	18		T3	7
ClkMuxSt	35495	1			T1	15		T2	18		T3	7
IdleSt	21824888	1			T1	1275		T2	17976		T3	1258
ResetSt	7107899	1			T1	1438		T2	1722		T3	1272
arcs[ResetSt=>IdleSt]	52575	1			T1	16		T2	19		T3	13
arcs[IdleSt=>ScrapSt]	295	1			T5	10		T11	6		T17	1
arcs[IdleSt=>ClkMuxSt]	35216	1			T1	15		T2	18		T3	7
arcs[ClkMuxSt=>CntIncrSt]	35148	1			T1	15		T2	18		T3	7
arcs[CntIncrSt=>PostTransSt]	1777	1			T4	14		T5	79		T11	10
arcs[CntIncrSt=>CntProgSt]	33311	1			T1	15		T2	18		T3	7
arcs[CntProgSt=>PostTransSt]	4941	1			T1	15		T2	18		T4	14
arcs[CntProgSt=>TransCheckSt]	27155	1			T3	7		T10	10		T4	64
arcs[TransCheckSt=>PostTransSt]	3649	1			T4	12		T5	70		T11	11
arcs[TransCheckSt=>TokenHashSt]	23405	1			T3	7		T10	10		T4	52
arcs[TokenHashSt=>PostTransSt]	10080	1			T4	32		T5	254		T11	45
arcs[TokenHashSt=>FlashRmaSt]	12665	1			T3	7		T10	10		T4	20
arcs[FlashRmaSt=>TokenCheck0St]	12563	1			T3	7		T10	10		T4	20
arcs[TokenCheck0St=>PostTransSt]	3137	1			T4	11		T5	62		T11	7
arcs[TokenCheck0St=>TokenCheck1St]	9394	1			T3	7		T10	10		T4	9
arcs[TokenCheck1St=>PostTransSt]	674	1			T4	1		T5	9		T11	1
arcs[TransProgSt=>PostTransSt]	7800	1			T3	7		T10	10		T4	8
arcs[IdleSt=>EscalateSt]	160	1			T16	8		T43	7		T45	5
arcs[ClkMuxSt=>EscalateSt]	68	1			T42	4		T16	2		T43	2
arcs[CntIncrSt=>EscalateSt]	60	1			T42	2		T16	1		T43	2
arcs[CntProgSt=>EscalateSt]	1215	1			T42	41		T16	30		T44	5
arcs[TransCheckSt=>EscalateSt]	101	1			T42	3		T44	7		T49	3
arcs[TokenHashSt=>EscalateSt]	660	1			T15	3		T42	17		T16	17
arcs[FlashRmaSt=>EscalateSt]	102	1			T42	6		T16	2		T44	2
arcs[TokenCheck0St=>EscalateSt]	32	1			T42	1		T44	1		T48	2
arcs[TokenCheck1St=>EscalateSt]	149	1			T42	3		T16	5		T44	1
arcs[TransProgSt=>EscalateSt]	771	1			T42	14		T16	23		T44	11
arcs[PostTransSt=>EscalateSt]	5174	1			T1	15		T2	18		T4	15
arcs[InvalidSt=>EscalateSt]	12908	1			T3	5		T10	3		T5	428

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7107707	1			T1	1438		T2	1722		T3	1272
auto[0]	auto[IdleSt]	21824784	1			T1	1275		T2	17976		T3	1258
auto[0]	auto[ClkMuxSt]	35447	1			T1	15		T2	18		T3	7
auto[0]	auto[CntIncrSt]	35106	1			T1	15		T2	18		T3	7
auto[0]	auto[CntProgSt]	1492332	1			T1	478		T2	357		T3	35
auto[0]	auto[TransCheckSt]	27083	1			T3	7		T10	10		T4	64
auto[0]	auto[TokenHashSt]	38136205	1			T3	241		T10	401		T4	562
auto[0]	auto[FlashRmaSt]	28779	1			T3	23		T10	32		T4	73
auto[0]	auto[TokenCheck0St]	12545	1			T3	7		T10	10		T4	20
auto[0]	auto[TokenCheck1St]	9310	1			T3	7		T10	10		T4	9
auto[0]	auto[TransProgSt]	397507	1			T3	29		T10	20		T4	15
auto[0]	auto[PostTransSt]	13111781	1			T1	826		T2	7817		T3	1131
auto[0]	auto[ScrapSt]	172603	1			T5	2204		T11	6062		T17	38
auto[0]	auto[EscalateSt]	5126148	1			T1	1275		T2	5927		T3	624
auto[0]	auto[InvalidSt]	10658347	1			T3	402		T10	212		T5	364268
auto[1]	auto[ResetSt]	192	1			T42	5		T16	2		T44	9
auto[1]	auto[IdleSt]	104	1			T16	7		T43	5		T45	3
auto[1]	auto[ClkMuxSt]	48	1			T42	2		T16	2		T43	1
auto[1]	auto[CntIncrSt]	42	1			T42	2		T16	1		T43	1
auto[1]	auto[CntProgSt]	809	1			T42	29		T16	17		T44	4
auto[1]	auto[TransCheckSt]	72	1			T42	3		T44	6		T49	3
auto[1]	auto[TokenHashSt]	447	1			T15	3		T42	12		T16	14
auto[1]	auto[FlashRmaSt]	67	1			T42	5		T16	2		T44	1
auto[1]	auto[TokenCheck0St]	18	1			T44	1		T48	2		T179	1
auto[1]	auto[TokenCheck1St]	84	1			T42	2		T16	2		T44	1
auto[1]	auto[TransProgSt]	525	1			T42	11		T16	20		T44	6
auto[1]	auto[PostTransSt]	2579	1			T1	7		T2	10		T4	10
auto[1]	auto[ScrapSt]	45	1			T16	2		T45	2		T87	1
auto[1]	auto[EscalateSt]	1343485	1			T1	686		T2	970		T3	196
auto[1]	auto[InvalidSt]	6490	1			T3	2		T10	2		T5	199

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7107721	1			T1	1438		T2	1722		T3	1272
auto[0]	auto[IdleSt]	21824787	1			T1	1275		T2	17976		T3	1258
auto[0]	auto[ClkMuxSt]	35455	1			T1	15		T2	18		T3	7
auto[0]	auto[CntIncrSt]	35109	1			T1	15		T2	18		T3	7
auto[0]	auto[CntProgSt]	1492339	1			T1	478		T2	357		T3	35
auto[0]	auto[TransCheckSt]	27090	1			T3	7		T10	10		T4	64
auto[0]	auto[TokenHashSt]	38136218	1			T3	241		T10	401		T4	562
auto[0]	auto[FlashRmaSt]	28787	1			T3	23		T10	32		T4	73
auto[0]	auto[TokenCheck0St]	12537	1			T3	7		T10	10		T4	20
auto[0]	auto[TokenCheck1St]	9283	1			T3	7		T10	10		T4	9
auto[0]	auto[TransProgSt]	397537	1			T3	29		T10	20		T4	15
auto[0]	auto[PostTransSt]	13111692	1			T1	825		T2	7819		T3	1131
auto[0]	auto[ScrapSt]	172598	1			T5	2204		T11	6062		T17	38
auto[0]	auto[EscalateSt]	5136849	1			T1	1177		T2	6121		T3	526
auto[0]	auto[InvalidSt]	10658419	1			T3	401		T10	213		T5	364238
auto[1]	auto[ResetSt]	178	1			T42	6		T16	4		T44	6
auto[1]	auto[IdleSt]	101	1			T16	4		T43	6		T45	5
auto[1]	auto[ClkMuxSt]	40	1			T42	3		T16	1		T43	1
auto[1]	auto[CntIncrSt]	39	1			T16	1		T43	2		T87	2
auto[1]	auto[CntProgSt]	802	1			T42	26		T16	21		T44	3
auto[1]	auto[TransCheckSt]	65	1			T42	2		T44	4		T49	1
auto[1]	auto[TokenHashSt]	434	1			T42	9		T16	12		T44	17
auto[1]	auto[FlashRmaSt]	59	1			T42	1		T16	1		T44	1
auto[1]	auto[TokenCheck0St]	26	1			T42	1		T44	1		T48	2
auto[1]	auto[TokenCheck1St]	111	1			T42	2		T16	5		T44	1
auto[1]	auto[TransProgSt]	495	1			T42	8		T16	12		T44	8
auto[1]	auto[PostTransSt]	2668	1			T1	8		T2	8		T4	5
auto[1]	auto[ScrapSt]	50	1			T42	1		T16	1		T45	2
auto[1]	auto[EscalateSt]	1332784	1			T1	784		T2	776		T3	294
auto[1]	auto[InvalidSt]	6418	1			T3	3		T10	1		T5	229