Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.18 97.82 95.93 93.31 100.00 98.52 98.76 95.94


Total test records in report: 1000
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T811 /workspace/coverage/default/38.lc_ctrl_security_escalation.2177478580 May 19 01:46:00 PM PDT 24 May 19 01:46:09 PM PDT 24 654976144 ps
T812 /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3375726215 May 19 01:45:34 PM PDT 24 May 19 01:45:36 PM PDT 24 43748586 ps
T813 /workspace/coverage/default/16.lc_ctrl_sec_token_digest.89912562 May 19 01:45:08 PM PDT 24 May 19 01:45:23 PM PDT 24 777670716 ps
T814 /workspace/coverage/default/14.lc_ctrl_jtag_errors.374909362 May 19 01:44:51 PM PDT 24 May 19 01:45:14 PM PDT 24 2694980311 ps
T815 /workspace/coverage/default/35.lc_ctrl_state_failure.2818074807 May 19 01:45:50 PM PDT 24 May 19 01:46:24 PM PDT 24 950009789 ps
T816 /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3835869223 May 19 01:44:01 PM PDT 24 May 19 01:45:31 PM PDT 24 4611363390 ps
T817 /workspace/coverage/default/0.lc_ctrl_jtag_errors.2669808588 May 19 01:44:03 PM PDT 24 May 19 01:44:24 PM PDT 24 3845574649 ps
T818 /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2133160246 May 19 01:44:10 PM PDT 24 May 19 01:44:19 PM PDT 24 248879727 ps
T819 /workspace/coverage/default/12.lc_ctrl_stress_all.1370645877 May 19 01:44:51 PM PDT 24 May 19 01:46:46 PM PDT 24 2754942606 ps
T820 /workspace/coverage/default/22.lc_ctrl_errors.3168518955 May 19 01:45:24 PM PDT 24 May 19 01:45:43 PM PDT 24 5883056723 ps
T821 /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1429280795 May 19 01:45:23 PM PDT 24 May 19 01:45:25 PM PDT 24 89252699 ps
T822 /workspace/coverage/default/18.lc_ctrl_sec_mubi.1758968433 May 19 01:45:09 PM PDT 24 May 19 01:45:28 PM PDT 24 612349387 ps
T823 /workspace/coverage/default/18.lc_ctrl_security_escalation.984777002 May 19 01:45:02 PM PDT 24 May 19 01:45:08 PM PDT 24 831364002 ps
T824 /workspace/coverage/default/29.lc_ctrl_smoke.2873776826 May 19 01:45:33 PM PDT 24 May 19 01:45:36 PM PDT 24 77578406 ps
T825 /workspace/coverage/default/9.lc_ctrl_jtag_priority.3136109839 May 19 01:44:46 PM PDT 24 May 19 01:44:50 PM PDT 24 1428866407 ps
T826 /workspace/coverage/default/33.lc_ctrl_state_post_trans.3923786384 May 19 01:45:50 PM PDT 24 May 19 01:45:59 PM PDT 24 99489690 ps
T827 /workspace/coverage/default/35.lc_ctrl_stress_all.1400541494 May 19 01:45:50 PM PDT 24 May 19 01:47:16 PM PDT 24 4103318255 ps
T83 /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.3109888682 May 19 01:45:43 PM PDT 24 May 19 02:08:49 PM PDT 24 146911592535 ps
T828 /workspace/coverage/default/48.lc_ctrl_security_escalation.2021473371 May 19 01:46:27 PM PDT 24 May 19 01:46:34 PM PDT 24 729967069 ps
T829 /workspace/coverage/default/48.lc_ctrl_sec_token_digest.4227992013 May 19 01:46:25 PM PDT 24 May 19 01:46:39 PM PDT 24 6065498212 ps
T830 /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1892905742 May 19 01:44:55 PM PDT 24 May 19 01:45:55 PM PDT 24 15289607555 ps
T831 /workspace/coverage/default/15.lc_ctrl_alert_test.2491537472 May 19 01:44:55 PM PDT 24 May 19 01:44:57 PM PDT 24 82625891 ps
T75 /workspace/coverage/default/8.lc_ctrl_smoke.3630687224 May 19 01:44:26 PM PDT 24 May 19 01:44:29 PM PDT 24 31341495 ps
T832 /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3312042936 May 19 01:43:56 PM PDT 24 May 19 01:44:07 PM PDT 24 1182767609 ps
T833 /workspace/coverage/default/18.lc_ctrl_state_post_trans.2696856770 May 19 01:45:05 PM PDT 24 May 19 01:45:14 PM PDT 24 463980275 ps
T834 /workspace/coverage/default/32.lc_ctrl_state_failure.472465322 May 19 01:45:41 PM PDT 24 May 19 01:46:05 PM PDT 24 257120607 ps
T835 /workspace/coverage/default/30.lc_ctrl_stress_all.3619286538 May 19 01:45:39 PM PDT 24 May 19 01:52:20 PM PDT 24 28141481774 ps
T836 /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.188734080 May 19 01:44:00 PM PDT 24 May 19 02:11:51 PM PDT 24 165809838983 ps
T837 /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.822341828 May 19 01:43:57 PM PDT 24 May 19 01:44:31 PM PDT 24 4934620450 ps
T69 /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1648769329 May 19 01:44:38 PM PDT 24 May 19 01:44:42 PM PDT 24 25498091 ps
T838 /workspace/coverage/default/13.lc_ctrl_alert_test.3378890537 May 19 01:44:48 PM PDT 24 May 19 01:44:50 PM PDT 24 18931529 ps
T839 /workspace/coverage/default/21.lc_ctrl_alert_test.1850378067 May 19 01:45:22 PM PDT 24 May 19 01:45:24 PM PDT 24 247923162 ps
T840 /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.2724710532 May 19 01:45:09 PM PDT 24 May 19 01:45:18 PM PDT 24 438506929 ps
T841 /workspace/coverage/default/21.lc_ctrl_sec_mubi.2468765247 May 19 01:45:21 PM PDT 24 May 19 01:45:32 PM PDT 24 224070061 ps
T842 /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3554064952 May 19 01:46:00 PM PDT 24 May 19 01:46:01 PM PDT 24 13323866 ps
T843 /workspace/coverage/default/21.lc_ctrl_errors.3900055922 May 19 01:45:19 PM PDT 24 May 19 01:45:37 PM PDT 24 690166936 ps
T844 /workspace/coverage/default/30.lc_ctrl_state_post_trans.94625025 May 19 01:45:36 PM PDT 24 May 19 01:45:46 PM PDT 24 293594975 ps
T845 /workspace/coverage/default/7.lc_ctrl_jtag_priority.1730283896 May 19 01:44:25 PM PDT 24 May 19 01:44:29 PM PDT 24 76610231 ps
T846 /workspace/coverage/default/6.lc_ctrl_claim_transition_if.32438258 May 19 01:44:19 PM PDT 24 May 19 01:44:21 PM PDT 24 111681804 ps
T847 /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2729601216 May 19 01:46:06 PM PDT 24 May 19 01:46:10 PM PDT 24 27688972 ps
T848 /workspace/coverage/default/10.lc_ctrl_sec_token_mux.165717946 May 19 01:44:36 PM PDT 24 May 19 01:44:50 PM PDT 24 640136076 ps
T849 /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1636841954 May 19 01:44:22 PM PDT 24 May 19 01:44:35 PM PDT 24 3793484649 ps
T850 /workspace/coverage/default/11.lc_ctrl_stress_all.2964242665 May 19 01:44:44 PM PDT 24 May 19 01:46:11 PM PDT 24 2287395595 ps
T851 /workspace/coverage/default/34.lc_ctrl_stress_all.3723464218 May 19 01:45:46 PM PDT 24 May 19 01:47:40 PM PDT 24 9543429576 ps
T852 /workspace/coverage/default/39.lc_ctrl_smoke.1773256139 May 19 01:46:01 PM PDT 24 May 19 01:46:06 PM PDT 24 111978215 ps
T853 /workspace/coverage/default/12.lc_ctrl_state_post_trans.811418738 May 19 01:44:49 PM PDT 24 May 19 01:44:56 PM PDT 24 57056802 ps
T854 /workspace/coverage/default/44.lc_ctrl_prog_failure.3681488592 May 19 01:46:22 PM PDT 24 May 19 01:46:26 PM PDT 24 185970483 ps
T855 /workspace/coverage/default/36.lc_ctrl_sec_mubi.1295823257 May 19 01:45:54 PM PDT 24 May 19 01:46:07 PM PDT 24 360693526 ps
T856 /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1913669538 May 19 01:43:56 PM PDT 24 May 19 01:44:30 PM PDT 24 1102461306 ps
T857 /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3818982060 May 19 01:44:36 PM PDT 24 May 19 01:44:53 PM PDT 24 850885370 ps
T858 /workspace/coverage/default/18.lc_ctrl_smoke.1046368012 May 19 01:45:05 PM PDT 24 May 19 01:45:14 PM PDT 24 220833117 ps
T859 /workspace/coverage/default/10.lc_ctrl_sec_mubi.1212662221 May 19 01:44:37 PM PDT 24 May 19 01:44:52 PM PDT 24 2317176195 ps
T860 /workspace/coverage/default/21.lc_ctrl_state_post_trans.2667849648 May 19 01:45:22 PM PDT 24 May 19 01:45:29 PM PDT 24 303337429 ps
T861 /workspace/coverage/default/46.lc_ctrl_alert_test.284443479 May 19 01:46:17 PM PDT 24 May 19 01:46:20 PM PDT 24 43026134 ps
T862 /workspace/coverage/default/27.lc_ctrl_sec_token_mux.989540683 May 19 01:45:34 PM PDT 24 May 19 01:45:48 PM PDT 24 1666889518 ps
T863 /workspace/coverage/default/42.lc_ctrl_state_post_trans.2362155701 May 19 01:46:08 PM PDT 24 May 19 01:46:18 PM PDT 24 115782669 ps
T864 /workspace/coverage/default/45.lc_ctrl_stress_all.1074215566 May 19 01:46:22 PM PDT 24 May 19 01:46:43 PM PDT 24 3704324522 ps
T865 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.4117838784 May 19 01:46:11 PM PDT 24 May 19 01:46:13 PM PDT 24 12072243 ps
T866 /workspace/coverage/default/41.lc_ctrl_stress_all.2645010609 May 19 01:46:15 PM PDT 24 May 19 01:47:16 PM PDT 24 2286961292 ps
T867 /workspace/coverage/default/5.lc_ctrl_state_failure.2188886448 May 19 01:44:19 PM PDT 24 May 19 01:44:49 PM PDT 24 618680521 ps
T868 /workspace/coverage/default/42.lc_ctrl_alert_test.2115812558 May 19 01:46:09 PM PDT 24 May 19 01:46:11 PM PDT 24 65404559 ps
T869 /workspace/coverage/default/35.lc_ctrl_sec_mubi.334360887 May 19 01:45:51 PM PDT 24 May 19 01:46:08 PM PDT 24 3817038259 ps
T870 /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3785458048 May 19 01:44:38 PM PDT 24 May 19 01:44:55 PM PDT 24 5021920495 ps
T871 /workspace/coverage/default/22.lc_ctrl_sec_token_digest.4138429221 May 19 01:45:22 PM PDT 24 May 19 01:45:44 PM PDT 24 2838450812 ps
T872 /workspace/coverage/default/34.lc_ctrl_state_failure.4280774135 May 19 01:45:48 PM PDT 24 May 19 01:46:18 PM PDT 24 251221975 ps
T105 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3131187693 May 19 01:39:48 PM PDT 24 May 19 01:39:57 PM PDT 24 4615315901 ps
T95 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.567938286 May 19 01:38:59 PM PDT 24 May 19 01:39:01 PM PDT 24 483047771 ps
T96 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3771128411 May 19 01:39:55 PM PDT 24 May 19 01:39:57 PM PDT 24 83091717 ps
T100 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2202126153 May 19 01:39:27 PM PDT 24 May 19 01:39:29 PM PDT 24 69171835 ps
T92 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2447890875 May 19 01:40:12 PM PDT 24 May 19 01:40:15 PM PDT 24 23638182 ps
T125 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2580823060 May 19 01:38:59 PM PDT 24 May 19 01:39:01 PM PDT 24 54352046 ps
T93 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.192517005 May 19 01:40:18 PM PDT 24 May 19 01:40:20 PM PDT 24 61006003 ps
T123 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1866317027 May 19 01:39:20 PM PDT 24 May 19 01:39:25 PM PDT 24 747717003 ps
T114 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.384755460 May 19 01:39:45 PM PDT 24 May 19 01:39:48 PM PDT 24 730269464 ps
T124 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.310881652 May 19 01:39:29 PM PDT 24 May 19 01:39:30 PM PDT 24 248516014 ps
T873 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2356459172 May 19 01:39:51 PM PDT 24 May 19 01:40:08 PM PDT 24 2258459033 ps
T130 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1544816010 May 19 01:39:19 PM PDT 24 May 19 01:39:22 PM PDT 24 50508734 ps
T94 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2295610266 May 19 01:39:09 PM PDT 24 May 19 01:39:14 PM PDT 24 1162364909 ps
T98 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3733899428 May 19 01:40:02 PM PDT 24 May 19 01:40:04 PM PDT 24 61531719 ps
T99 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.202523914 May 19 01:39:53 PM PDT 24 May 19 01:39:58 PM PDT 24 110736386 ps
T874 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.866774172 May 19 01:40:13 PM PDT 24 May 19 01:40:15 PM PDT 24 42056888 ps
T153 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.463549813 May 19 01:39:08 PM PDT 24 May 19 01:39:09 PM PDT 24 32651442 ps
T109 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1503809059 May 19 01:39:54 PM PDT 24 May 19 01:39:56 PM PDT 24 565255974 ps
T166 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1687458785 May 19 01:39:57 PM PDT 24 May 19 01:39:59 PM PDT 24 25448043 ps
T875 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3251186725 May 19 01:39:32 PM PDT 24 May 19 01:39:51 PM PDT 24 6758065471 ps
T167 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.315822350 May 19 01:40:08 PM PDT 24 May 19 01:40:09 PM PDT 24 23964041 ps
T876 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3669127471 May 19 01:40:18 PM PDT 24 May 19 01:40:20 PM PDT 24 69638487 ps
T122 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1627152563 May 19 01:39:04 PM PDT 24 May 19 01:39:06 PM PDT 24 193793438 ps
T131 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4271181833 May 19 01:38:59 PM PDT 24 May 19 01:39:01 PM PDT 24 62127266 ps
T132 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1481961181 May 19 01:39:19 PM PDT 24 May 19 01:39:20 PM PDT 24 16369376 ps
T168 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1228120911 May 19 01:39:41 PM PDT 24 May 19 01:39:43 PM PDT 24 114462365 ps
T154 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2528502597 May 19 01:39:54 PM PDT 24 May 19 01:39:55 PM PDT 24 20443023 ps
T877 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2503887104 May 19 01:39:29 PM PDT 24 May 19 01:39:31 PM PDT 24 26549971 ps
T878 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.310625595 May 19 01:39:24 PM PDT 24 May 19 01:39:26 PM PDT 24 51959942 ps
T97 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3469424998 May 19 01:39:53 PM PDT 24 May 19 01:39:55 PM PDT 24 146361511 ps
T879 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2272898276 May 19 01:39:47 PM PDT 24 May 19 01:39:51 PM PDT 24 109995578 ps
T880 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.298643590 May 19 01:38:53 PM PDT 24 May 19 01:38:55 PM PDT 24 213971310 ps
T881 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2584483980 May 19 01:38:54 PM PDT 24 May 19 01:39:00 PM PDT 24 941933344 ps
T882 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1980562034 May 19 01:39:15 PM PDT 24 May 19 01:39:17 PM PDT 24 21224775 ps
T101 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3150257888 May 19 01:40:02 PM PDT 24 May 19 01:40:07 PM PDT 24 143346644 ps
T883 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.403084312 May 19 01:40:02 PM PDT 24 May 19 01:40:03 PM PDT 24 72483642 ps
T169 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3510453422 May 19 01:39:47 PM PDT 24 May 19 01:39:49 PM PDT 24 72791904 ps
T104 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3600746846 May 19 01:40:24 PM PDT 24 May 19 01:40:29 PM PDT 24 204367301 ps
T884 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3326969039 May 19 01:39:39 PM PDT 24 May 19 01:39:41 PM PDT 24 112387293 ps
T102 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.470621697 May 19 01:40:08 PM PDT 24 May 19 01:40:11 PM PDT 24 279046239 ps
T885 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1346322635 May 19 01:39:57 PM PDT 24 May 19 01:40:03 PM PDT 24 918411864 ps
T886 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2725872641 May 19 01:39:21 PM PDT 24 May 19 01:39:22 PM PDT 24 53030014 ps
T887 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.4014990766 May 19 01:39:34 PM PDT 24 May 19 01:39:37 PM PDT 24 369710170 ps
T888 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.973887979 May 19 01:39:57 PM PDT 24 May 19 01:39:59 PM PDT 24 209129757 ps
T889 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1521464391 May 19 01:39:02 PM PDT 24 May 19 01:39:04 PM PDT 24 40406889 ps
T890 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3676515626 May 19 01:39:43 PM PDT 24 May 19 01:39:44 PM PDT 24 39815833 ps
T891 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3196970078 May 19 01:39:28 PM PDT 24 May 19 01:39:30 PM PDT 24 71866213 ps
T892 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1332578328 May 19 01:40:01 PM PDT 24 May 19 01:40:03 PM PDT 24 27016882 ps
T893 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.998212049 May 19 01:39:53 PM PDT 24 May 19 01:40:01 PM PDT 24 1247480040 ps
T894 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2307478069 May 19 01:39:19 PM PDT 24 May 19 01:39:22 PM PDT 24 54617656 ps
T895 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3724734444 May 19 01:39:04 PM PDT 24 May 19 01:39:06 PM PDT 24 40849666 ps
T896 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1611512553 May 19 01:39:03 PM PDT 24 May 19 01:39:20 PM PDT 24 676146075 ps
T897 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2355801889 May 19 01:39:57 PM PDT 24 May 19 01:40:11 PM PDT 24 17592203537 ps
T898 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3703989227 May 19 01:40:20 PM PDT 24 May 19 01:40:21 PM PDT 24 16328609 ps
T170 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.230083747 May 19 01:39:45 PM PDT 24 May 19 01:39:46 PM PDT 24 18653724 ps
T899 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.551987818 May 19 01:38:53 PM PDT 24 May 19 01:38:55 PM PDT 24 304267516 ps
T155 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.228367820 May 19 01:39:19 PM PDT 24 May 19 01:39:21 PM PDT 24 69697935 ps
T900 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2602973624 May 19 01:39:02 PM PDT 24 May 19 01:39:05 PM PDT 24 42751621 ps
T901 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.63438361 May 19 01:40:03 PM PDT 24 May 19 01:40:04 PM PDT 24 88212732 ps
T171 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1688049431 May 19 01:39:43 PM PDT 24 May 19 01:39:46 PM PDT 24 85813593 ps
T902 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1621928904 May 19 01:39:36 PM PDT 24 May 19 01:39:44 PM PDT 24 3889200351 ps
T106 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.225109162 May 19 01:39:57 PM PDT 24 May 19 01:40:01 PM PDT 24 274749954 ps
T903 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3048315911 May 19 01:39:49 PM PDT 24 May 19 01:39:51 PM PDT 24 111186619 ps
T904 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2310073784 May 19 01:39:54 PM PDT 24 May 19 01:39:56 PM PDT 24 174338084 ps
T111 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1389093703 May 19 01:39:57 PM PDT 24 May 19 01:40:02 PM PDT 24 139007653 ps
T905 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.4023650394 May 19 01:40:08 PM PDT 24 May 19 01:40:14 PM PDT 24 239149899 ps
T906 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.911212682 May 19 01:39:57 PM PDT 24 May 19 01:39:59 PM PDT 24 23465514 ps
T907 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.794173731 May 19 01:39:28 PM PDT 24 May 19 01:39:30 PM PDT 24 26776910 ps
T156 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.4188303021 May 19 01:39:28 PM PDT 24 May 19 01:39:29 PM PDT 24 13208364 ps
T908 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2490396016 May 19 01:39:49 PM PDT 24 May 19 01:39:52 PM PDT 24 260504880 ps
T112 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2131841059 May 19 01:39:08 PM PDT 24 May 19 01:39:13 PM PDT 24 127755062 ps
T909 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4236448413 May 19 01:39:22 PM PDT 24 May 19 01:39:24 PM PDT 24 281085505 ps
T910 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3335801363 May 19 01:39:13 PM PDT 24 May 19 01:39:15 PM PDT 24 111397940 ps
T911 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3337932113 May 19 01:39:36 PM PDT 24 May 19 01:39:37 PM PDT 24 16139526 ps
T912 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2469133097 May 19 01:39:34 PM PDT 24 May 19 01:39:37 PM PDT 24 91147728 ps
T157 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2417729048 May 19 01:39:40 PM PDT 24 May 19 01:39:42 PM PDT 24 170497967 ps
T913 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1067098970 May 19 01:39:27 PM PDT 24 May 19 01:39:29 PM PDT 24 94370719 ps
T914 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3192730896 May 19 01:40:12 PM PDT 24 May 19 01:40:14 PM PDT 24 74729485 ps
T120 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.290606327 May 19 01:39:47 PM PDT 24 May 19 01:39:53 PM PDT 24 257754599 ps
T158 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2079919731 May 19 01:39:28 PM PDT 24 May 19 01:39:30 PM PDT 24 16703360 ps
T915 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2075627032 May 19 01:39:13 PM PDT 24 May 19 01:39:16 PM PDT 24 252922625 ps
T916 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2370076759 May 19 01:40:02 PM PDT 24 May 19 01:40:04 PM PDT 24 30548258 ps
T917 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2830370477 May 19 01:39:27 PM PDT 24 May 19 01:39:29 PM PDT 24 119929599 ps
T918 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1169182317 May 19 01:39:38 PM PDT 24 May 19 01:39:45 PM PDT 24 6360678042 ps
T919 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.753411553 May 19 01:39:42 PM PDT 24 May 19 01:39:46 PM PDT 24 1169854566 ps
T920 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1402699705 May 19 01:40:07 PM PDT 24 May 19 01:40:09 PM PDT 24 82753481 ps
T921 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.869873649 May 19 01:39:50 PM PDT 24 May 19 01:39:52 PM PDT 24 44712936 ps
T922 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3064284045 May 19 01:38:58 PM PDT 24 May 19 01:39:00 PM PDT 24 32893940 ps
T923 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2251223344 May 19 01:40:12 PM PDT 24 May 19 01:40:14 PM PDT 24 63557983 ps
T924 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2573670084 May 19 01:40:22 PM PDT 24 May 19 01:40:25 PM PDT 24 21248243 ps
T925 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.661226816 May 19 01:39:01 PM PDT 24 May 19 01:39:07 PM PDT 24 838425770 ps
T926 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2708428033 May 19 01:39:54 PM PDT 24 May 19 01:39:56 PM PDT 24 127540405 ps
T927 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3235622829 May 19 01:39:04 PM PDT 24 May 19 01:39:12 PM PDT 24 2089472593 ps
T928 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3748292849 May 19 01:39:14 PM PDT 24 May 19 01:39:16 PM PDT 24 47471735 ps
T929 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.684905336 May 19 01:40:02 PM PDT 24 May 19 01:40:04 PM PDT 24 19540805 ps
T930 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1188177073 May 19 01:39:20 PM PDT 24 May 19 01:39:23 PM PDT 24 434547503 ps
T110 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3128226149 May 19 01:39:53 PM PDT 24 May 19 01:39:57 PM PDT 24 471426378 ps
T931 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3794377681 May 19 01:39:55 PM PDT 24 May 19 01:39:59 PM PDT 24 398566659 ps
T159 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2854954963 May 19 01:39:48 PM PDT 24 May 19 01:39:49 PM PDT 24 11421674 ps
T932 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2502337716 May 19 01:39:03 PM PDT 24 May 19 01:39:05 PM PDT 24 45190483 ps
T160 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2289913504 May 19 01:39:29 PM PDT 24 May 19 01:39:31 PM PDT 24 38769867 ps
T933 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2645160673 May 19 01:40:22 PM PDT 24 May 19 01:40:25 PM PDT 24 70726696 ps
T934 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.301569591 May 19 01:39:15 PM PDT 24 May 19 01:39:17 PM PDT 24 64433815 ps
T935 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2985180008 May 19 01:39:59 PM PDT 24 May 19 01:40:01 PM PDT 24 51165205 ps
T936 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1118922298 May 19 01:39:46 PM PDT 24 May 19 01:39:48 PM PDT 24 55079199 ps
T937 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1599091918 May 19 01:39:20 PM PDT 24 May 19 01:39:22 PM PDT 24 114455296 ps
T161 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.710641194 May 19 01:40:10 PM PDT 24 May 19 01:40:11 PM PDT 24 20253527 ps
T938 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3443818921 May 19 01:39:35 PM PDT 24 May 19 01:39:37 PM PDT 24 79432294 ps
T939 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.406888724 May 19 01:39:50 PM PDT 24 May 19 01:39:52 PM PDT 24 58235155 ps
T115 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.495285576 May 19 01:40:22 PM PDT 24 May 19 01:40:25 PM PDT 24 77898414 ps
T940 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3807237614 May 19 01:39:09 PM PDT 24 May 19 01:39:12 PM PDT 24 793190484 ps
T941 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3745486771 May 19 01:39:02 PM PDT 24 May 19 01:39:04 PM PDT 24 42269793 ps
T942 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1912471524 May 19 01:39:38 PM PDT 24 May 19 01:39:40 PM PDT 24 138329726 ps
T943 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1668716345 May 19 01:39:57 PM PDT 24 May 19 01:40:00 PM PDT 24 100771832 ps
T944 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1183099085 May 19 01:39:52 PM PDT 24 May 19 01:39:54 PM PDT 24 20585477 ps
T945 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1667682361 May 19 01:40:11 PM PDT 24 May 19 01:40:14 PM PDT 24 51284543 ps
T118 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1122800339 May 19 01:39:35 PM PDT 24 May 19 01:39:38 PM PDT 24 177107145 ps
T946 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1232359229 May 19 01:39:09 PM PDT 24 May 19 01:39:12 PM PDT 24 99917514 ps
T947 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.782207519 May 19 01:39:37 PM PDT 24 May 19 01:39:38 PM PDT 24 50582028 ps
T178 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2388429674 May 19 01:39:41 PM PDT 24 May 19 01:39:43 PM PDT 24 93283407 ps
T948 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1067081730 May 19 01:40:17 PM PDT 24 May 19 01:40:19 PM PDT 24 101151684 ps
T949 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3855805926 May 19 01:39:35 PM PDT 24 May 19 01:39:39 PM PDT 24 326426146 ps
T116 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.41801433 May 19 01:40:08 PM PDT 24 May 19 01:40:12 PM PDT 24 95938962 ps
T950 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.17618759 May 19 01:39:33 PM PDT 24 May 19 01:39:35 PM PDT 24 199269561 ps
T951 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.845976736 May 19 01:39:08 PM PDT 24 May 19 01:39:10 PM PDT 24 35373259 ps
T952 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3565788087 May 19 01:40:22 PM PDT 24 May 19 01:40:24 PM PDT 24 31783675 ps
T107 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2290686903 May 19 01:40:18 PM PDT 24 May 19 01:40:21 PM PDT 24 47944520 ps
T953 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3084308443 May 19 01:40:13 PM PDT 24 May 19 01:40:14 PM PDT 24 15869640 ps
T162 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3837672212 May 19 01:40:18 PM PDT 24 May 19 01:40:20 PM PDT 24 12916387 ps
T954 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2816328797 May 19 01:39:41 PM PDT 24 May 19 01:39:45 PM PDT 24 321872279 ps
T955 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2559735457 May 19 01:39:02 PM PDT 24 May 19 01:39:04 PM PDT 24 42719683 ps
T108 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1923504813 May 19 01:40:01 PM PDT 24 May 19 01:40:05 PM PDT 24 1770442445 ps
T956 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1973904138 May 19 01:40:14 PM PDT 24 May 19 01:40:15 PM PDT 24 69183872 ps
T957 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3170348985 May 19 01:39:32 PM PDT 24 May 19 01:39:34 PM PDT 24 83449675 ps
T113 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4202641078 May 19 01:39:28 PM PDT 24 May 19 01:39:30 PM PDT 24 229783205 ps
T958 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2409904914 May 19 01:40:11 PM PDT 24 May 19 01:40:17 PM PDT 24 892907623 ps
T959 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1130936792 May 19 01:40:13 PM PDT 24 May 19 01:40:14 PM PDT 24 82864897 ps
T960 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1193593701 May 19 01:40:23 PM PDT 24 May 19 01:40:26 PM PDT 24 123404632 ps
T961 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3802169540 May 19 01:40:18 PM PDT 24 May 19 01:40:20 PM PDT 24 92536023 ps
T962 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1080478115 May 19 01:39:08 PM PDT 24 May 19 01:39:10 PM PDT 24 29171623 ps
T163 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1757466567 May 19 01:40:13 PM PDT 24 May 19 01:40:15 PM PDT 24 11521008 ps
T963 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1403802004 May 19 01:39:23 PM PDT 24 May 19 01:39:54 PM PDT 24 2944846317 ps
T964 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1976238870 May 19 01:40:08 PM PDT 24 May 19 01:40:11 PM PDT 24 96543075 ps
T965 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2554686327 May 19 01:39:55 PM PDT 24 May 19 01:39:56 PM PDT 24 23023314 ps
T966 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4158078580 May 19 01:39:53 PM PDT 24 May 19 01:39:55 PM PDT 24 14886716 ps
T967 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2641004886 May 19 01:40:07 PM PDT 24 May 19 01:40:10 PM PDT 24 26331780 ps
T968 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2156205495 May 19 01:39:34 PM PDT 24 May 19 01:39:37 PM PDT 24 160759143 ps
T969 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3795098414 May 19 01:40:02 PM PDT 24 May 19 01:40:04 PM PDT 24 28392565 ps
T164 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2410623297 May 19 01:39:31 PM PDT 24 May 19 01:39:33 PM PDT 24 35028946 ps
T970 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.223957982 May 19 01:39:18 PM PDT 24 May 19 01:39:20 PM PDT 24 81051179 ps
T103 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.365935616 May 19 01:40:09 PM PDT 24 May 19 01:40:12 PM PDT 24 104207485 ps
T971 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1431675544 May 19 01:39:14 PM PDT 24 May 19 01:39:19 PM PDT 24 1508753735 ps
T119 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1116445449 May 19 01:38:58 PM PDT 24 May 19 01:39:03 PM PDT 24 1219655184 ps
T972 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4195105225 May 19 01:39:18 PM PDT 24 May 19 01:39:20 PM PDT 24 283626610 ps
T165 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.820774894 May 19 01:39:13 PM PDT 24 May 19 01:39:14 PM PDT 24 47565739 ps
T121 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.772083951 May 19 01:40:12 PM PDT 24 May 19 01:40:15 PM PDT 24 367916012 ps
T973 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2894602500 May 19 01:40:07 PM PDT 24 May 19 01:40:09 PM PDT 24 45928614 ps
T974 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1268053127 May 19 01:39:43 PM PDT 24 May 19 01:40:07 PM PDT 24 1083201253 ps
T975 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1720088139 May 19 01:39:52 PM PDT 24 May 19 01:39:54 PM PDT 24 27854424 ps
T976 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1220151180 May 19 01:39:45 PM PDT 24 May 19 01:39:48 PM PDT 24 58485558 ps
T977 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.202299845 May 19 01:40:07 PM PDT 24 May 19 01:40:09 PM PDT 24 189401645 ps
T978 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.738935044 May 19 01:39:56 PM PDT 24 May 19 01:39:58 PM PDT 24 38838931 ps
T979 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2055211535 May 19 01:40:17 PM PDT 24 May 19 01:40:21 PM PDT 24 41668197 ps
T980 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4095678150 May 19 01:39:50 PM PDT 24 May 19 01:39:52 PM PDT 24 107280611 ps
T981 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4017594074 May 19 01:39:18 PM PDT 24 May 19 01:39:19 PM PDT 24 88822643 ps
T982 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4184375446 May 19 01:40:07 PM PDT 24 May 19 01:40:09 PM PDT 24 15848183 ps
T983 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.864366896 May 19 01:39:19 PM PDT 24 May 19 01:39:21 PM PDT 24 44922235 ps
T984 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.803881672 May 19 01:39:48 PM PDT 24 May 19 01:39:50 PM PDT 24 53646307 ps
T985 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.391331691 May 19 01:39:45 PM PDT 24 May 19 01:39:47 PM PDT 24 28347606 ps
T986 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2759030850 May 19 01:39:41 PM PDT 24 May 19 01:39:43 PM PDT 24 559306965 ps
T987 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.432296915 May 19 01:39:51 PM PDT 24 May 19 01:39:53 PM PDT 24 70387967 ps
T117 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1989853180 May 19 01:40:18 PM PDT 24 May 19 01:40:22 PM PDT 24 962543282 ps
T988 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3980019148 May 19 01:40:08 PM PDT 24 May 19 01:40:10 PM PDT 24 22823014 ps
T989 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1944233019 May 19 01:39:37 PM PDT 24 May 19 01:39:39 PM PDT 24 106747054 ps
T990 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2086770736 May 19 01:39:59 PM PDT 24 May 19 01:40:01 PM PDT 24 232935790 ps
T991 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2553971289 May 19 01:39:46 PM PDT 24 May 19 01:39:48 PM PDT 24 96726700 ps
T992 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1859085826 May 19 01:39:42 PM PDT 24 May 19 01:39:46 PM PDT 24 86632419 ps
T993 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1269374509 May 19 01:38:58 PM PDT 24 May 19 01:39:00 PM PDT 24 59643612 ps
T994 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3829543540 May 19 01:40:11 PM PDT 24 May 19 01:40:13 PM PDT 24 93779573 ps
T995 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1777866757 May 19 01:40:10 PM PDT 24 May 19 01:40:14 PM PDT 24 114073552 ps
T996 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.649877610 May 19 01:39:57 PM PDT 24 May 19 01:40:00 PM PDT 24 42317652 ps
T997 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2694938686 May 19 01:39:32 PM PDT 24 May 19 01:39:34 PM PDT 24 94321332 ps
T998 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1584836677 May 19 01:39:38 PM PDT 24 May 19 01:39:40 PM PDT 24 87637381 ps
T999 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1157781488 May 19 01:40:08 PM PDT 24 May 19 01:40:14 PM PDT 24 152174392 ps
T1000 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1507474588 May 19 01:39:28 PM PDT 24 May 19 01:39:36 PM PDT 24 719783497 ps

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.3125942473
Short name T5
Test name
Test status
Simulation time 168706030733 ps
CPU time 1472.09 seconds
Started May 19 01:44:39 PM PDT 24
Finished May 19 02:09:14 PM PDT 24
Peak memory 435096 kb
Host smart-4e3214e1-78a9-431a-b0b8-ac08b630acf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3125942473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.3125942473
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3539577443
Short name T42
Test name
Test status
Simulation time 511744358 ps
CPU time 9.59 seconds
Started May 19 01:45:09 PM PDT 24
Finished May 19 01:45:20 PM PDT 24
Peak memory 217900 kb
Host smart-2cc647bc-16e4-4d5e-b719-746e28a1ec35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539577443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3539577443
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3471189629
Short name T35
Test name
Test status
Simulation time 913806573 ps
CPU time 12.05 seconds
Started May 19 01:46:06 PM PDT 24
Finished May 19 01:46:20 PM PDT 24
Peak memory 225904 kb
Host smart-501e89ab-8a60-4a22-9ad8-2abc700c1609
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471189629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3471189629
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1576303957
Short name T13
Test name
Test status
Simulation time 302069323 ps
CPU time 8.16 seconds
Started May 19 01:46:04 PM PDT 24
Finished May 19 01:46:15 PM PDT 24
Peak memory 217800 kb
Host smart-8bd39422-90ba-47b0-aeb9-1ad38a8086a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576303957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1576303957
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.2123855247
Short name T46
Test name
Test status
Simulation time 211476713 ps
CPU time 38.61 seconds
Started May 19 01:44:21 PM PDT 24
Finished May 19 01:45:02 PM PDT 24
Peak memory 268996 kb
Host smart-3ea106ec-14e3-4bd3-8ad2-2292e7021dba
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123855247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.2123855247
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3210554925
Short name T51
Test name
Test status
Simulation time 384125112 ps
CPU time 8.34 seconds
Started May 19 01:46:07 PM PDT 24
Finished May 19 01:46:17 PM PDT 24
Peak memory 217844 kb
Host smart-c166630b-ce88-48ae-98f0-f5cc0b278449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210554925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3210554925
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.192517005
Short name T93
Test name
Test status
Simulation time 61006003 ps
CPU time 1.92 seconds
Started May 19 01:40:18 PM PDT 24
Finished May 19 01:40:20 PM PDT 24
Peak memory 221756 kb
Host smart-18e204d6-f88e-4d00-aba1-25dc73b5bca7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192517005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_
err.192517005
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.1123220201
Short name T15
Test name
Test status
Simulation time 61232684573 ps
CPU time 592.71 seconds
Started May 19 01:46:09 PM PDT 24
Finished May 19 01:56:03 PM PDT 24
Peak memory 289916 kb
Host smart-2e94028d-2db9-4d88-8d11-cfe96deaedfc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1123220201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.1123220201
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.384755460
Short name T114
Test name
Test status
Simulation time 730269464 ps
CPU time 2.68 seconds
Started May 19 01:39:45 PM PDT 24
Finished May 19 01:39:48 PM PDT 24
Peak memory 217648 kb
Host smart-9f3d3c7f-dc20-47bd-9d68-e4edb6e077e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384755
460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.384755460
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3943229505
Short name T134
Test name
Test status
Simulation time 303446302 ps
CPU time 9.28 seconds
Started May 19 01:46:27 PM PDT 24
Finished May 19 01:46:36 PM PDT 24
Peak memory 217912 kb
Host smart-0d6a178b-17c2-4c62-80e2-bf9910278590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943229505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3943229505
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.1904674612
Short name T8
Test name
Test status
Simulation time 307248835 ps
CPU time 6.81 seconds
Started May 19 01:46:17 PM PDT 24
Finished May 19 01:46:26 PM PDT 24
Peak memory 216912 kb
Host smart-e001f57c-f5d6-4e59-81fb-f16836e658b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904674612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.1904674612
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1684665067
Short name T29
Test name
Test status
Simulation time 144604740 ps
CPU time 0.97 seconds
Started May 19 01:46:28 PM PDT 24
Finished May 19 01:46:30 PM PDT 24
Peak memory 209272 kb
Host smart-03fbf7a4-0e87-426a-b984-f21beb430c7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684665067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1684665067
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.463549813
Short name T153
Test name
Test status
Simulation time 32651442 ps
CPU time 0.77 seconds
Started May 19 01:39:08 PM PDT 24
Finished May 19 01:39:09 PM PDT 24
Peak memory 209268 kb
Host smart-b4298000-3c36-429b-b925-191fadb5fd6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463549813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.463549813
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3600746846
Short name T104
Test name
Test status
Simulation time 204367301 ps
CPU time 4.65 seconds
Started May 19 01:40:24 PM PDT 24
Finished May 19 01:40:29 PM PDT 24
Peak memory 218976 kb
Host smart-df342e4a-c2de-48ed-9697-95b6e5626760
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600746846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3600746846
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.784322674
Short name T32
Test name
Test status
Simulation time 67842001 ps
CPU time 1.23 seconds
Started May 19 01:45:40 PM PDT 24
Finished May 19 01:45:42 PM PDT 24
Peak memory 213020 kb
Host smart-645ced20-1512-4ca6-b4d3-51e787c508a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784322674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.784322674
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.225109162
Short name T106
Test name
Test status
Simulation time 274749954 ps
CPU time 3.53 seconds
Started May 19 01:39:57 PM PDT 24
Finished May 19 01:40:01 PM PDT 24
Peak memory 217616 kb
Host smart-caa1a00e-9a35-4a26-b029-63c7d524fbbf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225109162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.225109162
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1923504813
Short name T108
Test name
Test status
Simulation time 1770442445 ps
CPU time 2.85 seconds
Started May 19 01:40:01 PM PDT 24
Finished May 19 01:40:05 PM PDT 24
Peak memory 217592 kb
Host smart-ecd41f32-e265-4a82-80b2-2bc8e8b32b76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923504813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1923504813
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.365935616
Short name T103
Test name
Test status
Simulation time 104207485 ps
CPU time 1.9 seconds
Started May 19 01:40:09 PM PDT 24
Finished May 19 01:40:12 PM PDT 24
Peak memory 222000 kb
Host smart-13e82a56-d6cb-4d0b-8aac-898fd1b71578
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365935616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg_
err.365935616
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4202641078
Short name T113
Test name
Test status
Simulation time 229783205 ps
CPU time 2.39 seconds
Started May 19 01:39:28 PM PDT 24
Finished May 19 01:39:30 PM PDT 24
Peak memory 217696 kb
Host smart-710a90df-b3e6-42e7-bb22-a918115d45b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202641078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.4202641078
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.290606327
Short name T120
Test name
Test status
Simulation time 257754599 ps
CPU time 4.5 seconds
Started May 19 01:39:47 PM PDT 24
Finished May 19 01:39:53 PM PDT 24
Peak memory 217600 kb
Host smart-dcb04a48-3b6f-4c47-b072-62ff0cfd9987
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290606327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.290606327
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.3040034023
Short name T50
Test name
Test status
Simulation time 189624675822 ps
CPU time 1285.35 seconds
Started May 19 01:45:11 PM PDT 24
Finished May 19 02:06:37 PM PDT 24
Peak memory 405548 kb
Host smart-1b34b426-d790-49b9-a763-9fe1427b0d29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3040034023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.3040034023
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.2283770837
Short name T30
Test name
Test status
Simulation time 1132310965 ps
CPU time 13.02 seconds
Started May 19 01:46:19 PM PDT 24
Finished May 19 01:46:33 PM PDT 24
Peak memory 224512 kb
Host smart-e80884e9-9af7-4f75-bff3-5184a952236a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283770837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.2283770837
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1989853180
Short name T117
Test name
Test status
Simulation time 962543282 ps
CPU time 3.31 seconds
Started May 19 01:40:18 PM PDT 24
Finished May 19 01:40:22 PM PDT 24
Peak memory 222524 kb
Host smart-ccc773b0-c366-4154-97a4-e27d41e2078b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989853180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.1989853180
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.1509484508
Short name T177
Test name
Test status
Simulation time 16696357 ps
CPU time 0.95 seconds
Started May 19 01:43:52 PM PDT 24
Finished May 19 01:43:57 PM PDT 24
Peak memory 212420 kb
Host smart-be4dcc7d-09d4-484a-a6d5-9579dee84c4a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509484508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.1509484508
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.4100008270
Short name T175
Test name
Test status
Simulation time 11076621 ps
CPU time 0.83 seconds
Started May 19 01:44:05 PM PDT 24
Finished May 19 01:44:09 PM PDT 24
Peak memory 209308 kb
Host smart-5d4dc592-1dee-4c80-a09a-2353fc9530ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100008270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.4100008270
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.728523647
Short name T174
Test name
Test status
Simulation time 12807814 ps
CPU time 0.85 seconds
Started May 19 01:44:21 PM PDT 24
Finished May 19 01:44:24 PM PDT 24
Peak memory 209308 kb
Host smart-6d13c467-de69-4c3d-81c3-d69a0c346ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728523647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.728523647
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2131841059
Short name T112
Test name
Test status
Simulation time 127755062 ps
CPU time 4.3 seconds
Started May 19 01:39:08 PM PDT 24
Finished May 19 01:39:13 PM PDT 24
Peak memory 217620 kb
Host smart-4bf34a7f-e3ae-4cf8-9806-d400dda1626a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131841059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2131841059
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.41801433
Short name T116
Test name
Test status
Simulation time 95938962 ps
CPU time 2.72 seconds
Started May 19 01:40:08 PM PDT 24
Finished May 19 01:40:12 PM PDT 24
Peak memory 222184 kb
Host smart-43dd8c5f-86c1-4681-82dd-1a20cd491892
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41801433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_e
rr.41801433
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2290686903
Short name T107
Test name
Test status
Simulation time 47944520 ps
CPU time 2.25 seconds
Started May 19 01:40:18 PM PDT 24
Finished May 19 01:40:21 PM PDT 24
Peak memory 217660 kb
Host smart-785a8783-8f3a-4d71-8cf4-5583ed827f37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290686903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2290686903
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.772083951
Short name T121
Test name
Test status
Simulation time 367916012 ps
CPU time 1.93 seconds
Started May 19 01:40:12 PM PDT 24
Finished May 19 01:40:15 PM PDT 24
Peak memory 221752 kb
Host smart-5b03e6b4-4eb3-48bc-b5f0-06b09220eea7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772083951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_
err.772083951
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1122800339
Short name T118
Test name
Test status
Simulation time 177107145 ps
CPU time 2.35 seconds
Started May 19 01:39:35 PM PDT 24
Finished May 19 01:39:38 PM PDT 24
Peak memory 217620 kb
Host smart-47a4ee0c-2990-4ca7-baae-d310197df4df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122800339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.1122800339
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3049061236
Short name T12
Test name
Test status
Simulation time 324472613 ps
CPU time 12.5 seconds
Started May 19 01:45:04 PM PDT 24
Finished May 19 01:45:18 PM PDT 24
Peak memory 225812 kb
Host smart-15713c6f-76cb-4104-b7fb-bb8b98f831fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049061236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3049061236
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.930090812
Short name T2
Test name
Test status
Simulation time 710532791 ps
CPU time 7.37 seconds
Started May 19 01:44:49 PM PDT 24
Finished May 19 01:44:57 PM PDT 24
Peak memory 217688 kb
Host smart-1ad298da-7870-4abc-899d-655fb1a9d6a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930090812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_prog_failure.930090812
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3745486771
Short name T941
Test name
Test status
Simulation time 42269793 ps
CPU time 1.36 seconds
Started May 19 01:39:02 PM PDT 24
Finished May 19 01:39:04 PM PDT 24
Peak memory 209408 kb
Host smart-064bf4d7-7762-4aa1-9a8e-c72f83a025b7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745486771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.3745486771
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2580823060
Short name T125
Test name
Test status
Simulation time 54352046 ps
CPU time 1.47 seconds
Started May 19 01:38:59 PM PDT 24
Finished May 19 01:39:01 PM PDT 24
Peak memory 209204 kb
Host smart-f5ee2f3f-d9dc-4a71-bad3-64c1f9d89653
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580823060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2580823060
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.4271181833
Short name T131
Test name
Test status
Simulation time 62127266 ps
CPU time 0.91 seconds
Started May 19 01:38:59 PM PDT 24
Finished May 19 01:39:01 PM PDT 24
Peak memory 209876 kb
Host smart-49c5d188-f0ab-42c1-9423-cbb82dda6479
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271181833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.4271181833
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3724734444
Short name T895
Test name
Test status
Simulation time 40849666 ps
CPU time 1.3 seconds
Started May 19 01:39:04 PM PDT 24
Finished May 19 01:39:06 PM PDT 24
Peak memory 217672 kb
Host smart-5d1e80c0-0c4f-4476-a44c-5161c38573ee
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724734444 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3724734444
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.1269374509
Short name T993
Test name
Test status
Simulation time 59643612 ps
CPU time 0.98 seconds
Started May 19 01:38:58 PM PDT 24
Finished May 19 01:39:00 PM PDT 24
Peak memory 209044 kb
Host smart-a7f08df4-4cfb-47b4-b7d2-a88c8ef476ef
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269374509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.1269374509
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2559735457
Short name T955
Test name
Test status
Simulation time 42719683 ps
CPU time 1.59 seconds
Started May 19 01:39:02 PM PDT 24
Finished May 19 01:39:04 PM PDT 24
Peak memory 209308 kb
Host smart-f96e319a-7fd8-420e-adc0-c8d01ea4c29e
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559735457 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2559735457
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.661226816
Short name T925
Test name
Test status
Simulation time 838425770 ps
CPU time 5.58 seconds
Started May 19 01:39:01 PM PDT 24
Finished May 19 01:39:07 PM PDT 24
Peak memory 209260 kb
Host smart-0d212805-16ba-4cc1-b1e2-0ef968f070fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661226816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.661226816
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2584483980
Short name T881
Test name
Test status
Simulation time 941933344 ps
CPU time 5.4 seconds
Started May 19 01:38:54 PM PDT 24
Finished May 19 01:39:00 PM PDT 24
Peak memory 209124 kb
Host smart-59816d8f-5fea-4d75-9858-a70c978e038c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584483980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2584483980
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.298643590
Short name T880
Test name
Test status
Simulation time 213971310 ps
CPU time 1.54 seconds
Started May 19 01:38:53 PM PDT 24
Finished May 19 01:38:55 PM PDT 24
Peak memory 210380 kb
Host smart-18ffb677-1a98-4748-9a86-4a03a07aea4b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298643590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.298643590
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.567938286
Short name T95
Test name
Test status
Simulation time 483047771 ps
CPU time 2.09 seconds
Started May 19 01:38:59 PM PDT 24
Finished May 19 01:39:01 PM PDT 24
Peak memory 218988 kb
Host smart-a4d06251-1ed7-4765-9234-201a20f231fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567938
286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.567938286
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.551987818
Short name T899
Test name
Test status
Simulation time 304267516 ps
CPU time 1.6 seconds
Started May 19 01:38:53 PM PDT 24
Finished May 19 01:38:55 PM PDT 24
Peak memory 209320 kb
Host smart-c672e8dc-f9dc-4f9f-ad49-0cf7803611ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551987818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.551987818
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3064284045
Short name T922
Test name
Test status
Simulation time 32893940 ps
CPU time 1.14 seconds
Started May 19 01:38:58 PM PDT 24
Finished May 19 01:39:00 PM PDT 24
Peak memory 209448 kb
Host smart-5e955f22-6ad3-43ba-8dc9-58634e33b431
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064284045 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3064284045
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2502337716
Short name T932
Test name
Test status
Simulation time 45190483 ps
CPU time 1.88 seconds
Started May 19 01:39:03 PM PDT 24
Finished May 19 01:39:05 PM PDT 24
Peak memory 211532 kb
Host smart-7458ab51-5440-4154-9f3e-10c4f6f9ea59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502337716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2502337716
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2602973624
Short name T900
Test name
Test status
Simulation time 42751621 ps
CPU time 3.06 seconds
Started May 19 01:39:02 PM PDT 24
Finished May 19 01:39:05 PM PDT 24
Peak memory 217912 kb
Host smart-beeee453-1b8b-40fa-b5a6-445d564c70d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602973624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2602973624
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1116445449
Short name T119
Test name
Test status
Simulation time 1219655184 ps
CPU time 3.92 seconds
Started May 19 01:38:58 PM PDT 24
Finished May 19 01:39:03 PM PDT 24
Peak memory 217612 kb
Host smart-af9f2d49-fe5b-40ca-826a-f280d67f0cb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116445449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1116445449
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.820774894
Short name T165
Test name
Test status
Simulation time 47565739 ps
CPU time 1.29 seconds
Started May 19 01:39:13 PM PDT 24
Finished May 19 01:39:14 PM PDT 24
Peak memory 209328 kb
Host smart-6b57c40f-0ab3-4b6f-91c5-711f2dffd8aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820774894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.820774894
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.301569591
Short name T934
Test name
Test status
Simulation time 64433815 ps
CPU time 1.69 seconds
Started May 19 01:39:15 PM PDT 24
Finished May 19 01:39:17 PM PDT 24
Peak memory 208552 kb
Host smart-a60d851a-2073-452b-9f9a-df2aa81a08e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301569591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bash
.301569591
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.845976736
Short name T951
Test name
Test status
Simulation time 35373259 ps
CPU time 1.2 seconds
Started May 19 01:39:08 PM PDT 24
Finished May 19 01:39:10 PM PDT 24
Peak memory 211704 kb
Host smart-e5523815-6161-4d11-9e53-193ff6db1855
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845976736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.845976736
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1980562034
Short name T882
Test name
Test status
Simulation time 21224775 ps
CPU time 1.46 seconds
Started May 19 01:39:15 PM PDT 24
Finished May 19 01:39:17 PM PDT 24
Peak memory 217664 kb
Host smart-d09c7e2d-53b7-4ae0-b45b-c1f4fb8e9e8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980562034 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1980562034
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3807237614
Short name T940
Test name
Test status
Simulation time 793190484 ps
CPU time 2.38 seconds
Started May 19 01:39:09 PM PDT 24
Finished May 19 01:39:12 PM PDT 24
Peak memory 209244 kb
Host smart-0a845a39-c030-4cfa-849a-2c6da57c8de2
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807237614 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.3807237614
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3235622829
Short name T927
Test name
Test status
Simulation time 2089472593 ps
CPU time 7.34 seconds
Started May 19 01:39:04 PM PDT 24
Finished May 19 01:39:12 PM PDT 24
Peak memory 209156 kb
Host smart-dcbac657-1b15-4a31-86cc-cd01e450e624
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235622829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3235622829
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1611512553
Short name T896
Test name
Test status
Simulation time 676146075 ps
CPU time 16.28 seconds
Started May 19 01:39:03 PM PDT 24
Finished May 19 01:39:20 PM PDT 24
Peak memory 209540 kb
Host smart-399bc906-cbb7-4641-b892-1406087a5f48
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611512553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1611512553
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1627152563
Short name T122
Test name
Test status
Simulation time 193793438 ps
CPU time 1.79 seconds
Started May 19 01:39:04 PM PDT 24
Finished May 19 01:39:06 PM PDT 24
Peak memory 210996 kb
Host smart-2291955b-1df9-4ffe-bb78-e04d3a8d8855
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627152563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1627152563
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1232359229
Short name T946
Test name
Test status
Simulation time 99917514 ps
CPU time 2.92 seconds
Started May 19 01:39:09 PM PDT 24
Finished May 19 01:39:12 PM PDT 24
Peak memory 218688 kb
Host smart-392e17ab-460e-4d0e-8032-fafde29a92d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123235
9229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1232359229
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1521464391
Short name T889
Test name
Test status
Simulation time 40406889 ps
CPU time 1.08 seconds
Started May 19 01:39:02 PM PDT 24
Finished May 19 01:39:04 PM PDT 24
Peak memory 209248 kb
Host smart-dcb8b231-2f96-4b4e-9924-84d22a6f4b3a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521464391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.1521464391
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1080478115
Short name T962
Test name
Test status
Simulation time 29171623 ps
CPU time 1.09 seconds
Started May 19 01:39:08 PM PDT 24
Finished May 19 01:39:10 PM PDT 24
Peak memory 209344 kb
Host smart-460b88cd-8c8a-4f01-9474-7c77634ca2de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080478115 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1080478115
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3335801363
Short name T910
Test name
Test status
Simulation time 111397940 ps
CPU time 1.34 seconds
Started May 19 01:39:13 PM PDT 24
Finished May 19 01:39:15 PM PDT 24
Peak memory 209620 kb
Host smart-a88d6a25-39b8-40c3-9681-7bb49e57add3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335801363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3335801363
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2295610266
Short name T94
Test name
Test status
Simulation time 1162364909 ps
CPU time 4.24 seconds
Started May 19 01:39:09 PM PDT 24
Finished May 19 01:39:14 PM PDT 24
Peak memory 217684 kb
Host smart-609ff992-0a4b-43d8-bd95-c63173e47ae6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295610266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2295610266
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1332578328
Short name T892
Test name
Test status
Simulation time 27016882 ps
CPU time 1.56 seconds
Started May 19 01:40:01 PM PDT 24
Finished May 19 01:40:03 PM PDT 24
Peak memory 217608 kb
Host smart-6fb98dff-1f16-4878-8ee0-d84470add623
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332578328 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.1332578328
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.315822350
Short name T167
Test name
Test status
Simulation time 23964041 ps
CPU time 0.9 seconds
Started May 19 01:40:08 PM PDT 24
Finished May 19 01:40:09 PM PDT 24
Peak memory 209412 kb
Host smart-ea1b2809-d01c-4010-a26f-a5d906932bab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315822350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.315822350
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.202299845
Short name T977
Test name
Test status
Simulation time 189401645 ps
CPU time 1.41 seconds
Started May 19 01:40:07 PM PDT 24
Finished May 19 01:40:09 PM PDT 24
Peak memory 211412 kb
Host smart-9f464723-71a9-415c-a69d-e396370bbd66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202299845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.202299845
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.4023650394
Short name T905
Test name
Test status
Simulation time 239149899 ps
CPU time 4.77 seconds
Started May 19 01:40:08 PM PDT 24
Finished May 19 01:40:14 PM PDT 24
Peak memory 217680 kb
Host smart-7ab1614b-9940-464a-b4bb-61d93644510c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023650394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.4023650394
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.63438361
Short name T901
Test name
Test status
Simulation time 88212732 ps
CPU time 1.22 seconds
Started May 19 01:40:03 PM PDT 24
Finished May 19 01:40:04 PM PDT 24
Peak memory 217732 kb
Host smart-6c808b8e-3ea8-4ba8-ae6b-e743d2f5487f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63438361 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.63438361
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3795098414
Short name T969
Test name
Test status
Simulation time 28392565 ps
CPU time 1.1 seconds
Started May 19 01:40:02 PM PDT 24
Finished May 19 01:40:04 PM PDT 24
Peak memory 209412 kb
Host smart-a40d2271-1b27-4915-bac6-8a600cf3a05e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795098414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3795098414
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.684905336
Short name T929
Test name
Test status
Simulation time 19540805 ps
CPU time 1.44 seconds
Started May 19 01:40:02 PM PDT 24
Finished May 19 01:40:04 PM PDT 24
Peak memory 209516 kb
Host smart-47caf5f9-f03f-4fa0-91e0-621feccfecd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684905336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.684905336
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1976238870
Short name T964
Test name
Test status
Simulation time 96543075 ps
CPU time 1.94 seconds
Started May 19 01:40:08 PM PDT 24
Finished May 19 01:40:11 PM PDT 24
Peak memory 217820 kb
Host smart-29b45525-847d-4d23-b96b-2712b2d02e2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976238870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1976238870
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.470621697
Short name T102
Test name
Test status
Simulation time 279046239 ps
CPU time 2.7 seconds
Started May 19 01:40:08 PM PDT 24
Finished May 19 01:40:11 PM PDT 24
Peak memory 217612 kb
Host smart-00ea9a60-50f3-41bd-81ea-2398fce23c55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470621697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.470621697
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.4184375446
Short name T982
Test name
Test status
Simulation time 15848183 ps
CPU time 1.27 seconds
Started May 19 01:40:07 PM PDT 24
Finished May 19 01:40:09 PM PDT 24
Peak memory 217716 kb
Host smart-7f8f955c-4687-4358-a2e9-d664e8ba70dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184375446 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.4184375446
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.403084312
Short name T883
Test name
Test status
Simulation time 72483642 ps
CPU time 1.02 seconds
Started May 19 01:40:02 PM PDT 24
Finished May 19 01:40:03 PM PDT 24
Peak memory 209484 kb
Host smart-c4f32972-52e8-49c2-90de-86bccee05aa1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403084312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.403084312
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2894602500
Short name T973
Test name
Test status
Simulation time 45928614 ps
CPU time 1.44 seconds
Started May 19 01:40:07 PM PDT 24
Finished May 19 01:40:09 PM PDT 24
Peak memory 211424 kb
Host smart-aa972a63-b755-4443-8f7a-feaa12ce0f4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894602500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.2894602500
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3150257888
Short name T101
Test name
Test status
Simulation time 143346644 ps
CPU time 4.12 seconds
Started May 19 01:40:02 PM PDT 24
Finished May 19 01:40:07 PM PDT 24
Peak memory 217884 kb
Host smart-2a396c17-4481-47e5-9b17-6d1736b3aec1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150257888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3150257888
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3733899428
Short name T98
Test name
Test status
Simulation time 61531719 ps
CPU time 1.95 seconds
Started May 19 01:40:02 PM PDT 24
Finished May 19 01:40:04 PM PDT 24
Peak memory 222164 kb
Host smart-377bb296-bf88-4393-84fa-725be53a00c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733899428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3733899428
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1402699705
Short name T920
Test name
Test status
Simulation time 82753481 ps
CPU time 1.37 seconds
Started May 19 01:40:07 PM PDT 24
Finished May 19 01:40:09 PM PDT 24
Peak memory 218804 kb
Host smart-1d3958a7-73fe-470a-b35a-32631bb20845
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402699705 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1402699705
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.710641194
Short name T161
Test name
Test status
Simulation time 20253527 ps
CPU time 0.97 seconds
Started May 19 01:40:10 PM PDT 24
Finished May 19 01:40:11 PM PDT 24
Peak memory 208864 kb
Host smart-0723e532-6508-4104-b556-59bc1314de0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710641194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.710641194
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2641004886
Short name T967
Test name
Test status
Simulation time 26331780 ps
CPU time 1.39 seconds
Started May 19 01:40:07 PM PDT 24
Finished May 19 01:40:10 PM PDT 24
Peak memory 208724 kb
Host smart-3363b7a4-3666-4caa-a69f-3729a9cbedf7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641004886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2641004886
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1157781488
Short name T999
Test name
Test status
Simulation time 152174392 ps
CPU time 5.49 seconds
Started May 19 01:40:08 PM PDT 24
Finished May 19 01:40:14 PM PDT 24
Peak memory 217632 kb
Host smart-2a8407d6-4a11-4836-851a-f68b3fb56563
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157781488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1157781488
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.1667682361
Short name T945
Test name
Test status
Simulation time 51284543 ps
CPU time 1.43 seconds
Started May 19 01:40:11 PM PDT 24
Finished May 19 01:40:14 PM PDT 24
Peak memory 218232 kb
Host smart-ecb033b3-53f1-433c-97db-07ea90513abe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667682361 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.1667682361
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3980019148
Short name T988
Test name
Test status
Simulation time 22823014 ps
CPU time 0.91 seconds
Started May 19 01:40:08 PM PDT 24
Finished May 19 01:40:10 PM PDT 24
Peak memory 209352 kb
Host smart-20f8ad83-e71f-47e7-9233-69786aeaeb48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980019148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3980019148
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.3829543540
Short name T994
Test name
Test status
Simulation time 93779573 ps
CPU time 1.05 seconds
Started May 19 01:40:11 PM PDT 24
Finished May 19 01:40:13 PM PDT 24
Peak memory 209352 kb
Host smart-eb660e94-3032-4a09-89fc-a33576cae68b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829543540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.3829543540
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1777866757
Short name T995
Test name
Test status
Simulation time 114073552 ps
CPU time 3.35 seconds
Started May 19 01:40:10 PM PDT 24
Finished May 19 01:40:14 PM PDT 24
Peak memory 217752 kb
Host smart-1a7fed1d-ab48-4f13-9085-a0dad101b9ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777866757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.1777866757
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2573670084
Short name T924
Test name
Test status
Simulation time 21248243 ps
CPU time 1.44 seconds
Started May 19 01:40:22 PM PDT 24
Finished May 19 01:40:25 PM PDT 24
Peak memory 217696 kb
Host smart-c59d226a-d4e9-4853-8361-742a2b3ea80a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573670084 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2573670084
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3565788087
Short name T952
Test name
Test status
Simulation time 31783675 ps
CPU time 0.86 seconds
Started May 19 01:40:22 PM PDT 24
Finished May 19 01:40:24 PM PDT 24
Peak memory 209436 kb
Host smart-3a481d0d-3ec5-4a5b-8135-a335012865ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565788087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3565788087
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.1973904138
Short name T956
Test name
Test status
Simulation time 69183872 ps
CPU time 0.96 seconds
Started May 19 01:40:14 PM PDT 24
Finished May 19 01:40:15 PM PDT 24
Peak memory 209380 kb
Host smart-6189281c-b99b-45cb-ba52-1fb3819678c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973904138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.1973904138
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2447890875
Short name T92
Test name
Test status
Simulation time 23638182 ps
CPU time 1.7 seconds
Started May 19 01:40:12 PM PDT 24
Finished May 19 01:40:15 PM PDT 24
Peak memory 218208 kb
Host smart-aed058eb-2459-40aa-9c2a-a0aeaea7e69b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447890875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.2447890875
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1130936792
Short name T959
Test name
Test status
Simulation time 82864897 ps
CPU time 1.32 seconds
Started May 19 01:40:13 PM PDT 24
Finished May 19 01:40:14 PM PDT 24
Peak memory 217856 kb
Host smart-a5f118a8-bf5b-4561-9056-129ca735ef51
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130936792 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1130936792
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.866774172
Short name T874
Test name
Test status
Simulation time 42056888 ps
CPU time 1 seconds
Started May 19 01:40:13 PM PDT 24
Finished May 19 01:40:15 PM PDT 24
Peak memory 209308 kb
Host smart-f8b040b1-4ed2-455d-929a-7a11381cbcbf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866774172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.866774172
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2645160673
Short name T933
Test name
Test status
Simulation time 70726696 ps
CPU time 1.31 seconds
Started May 19 01:40:22 PM PDT 24
Finished May 19 01:40:25 PM PDT 24
Peak memory 209436 kb
Host smart-5b1e37b2-66b2-46ed-be7c-445ab6ff4bb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645160673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2645160673
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2251223344
Short name T923
Test name
Test status
Simulation time 63557983 ps
CPU time 1.57 seconds
Started May 19 01:40:12 PM PDT 24
Finished May 19 01:40:14 PM PDT 24
Peak memory 217728 kb
Host smart-dd2fc2e2-cbda-451d-be40-f6d4702d30a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251223344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2251223344
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.495285576
Short name T115
Test name
Test status
Simulation time 77898414 ps
CPU time 2.07 seconds
Started May 19 01:40:22 PM PDT 24
Finished May 19 01:40:25 PM PDT 24
Peak memory 217636 kb
Host smart-e3b07cbf-6406-4645-9066-91958c39ed1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495285576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.495285576
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3084308443
Short name T953
Test name
Test status
Simulation time 15869640 ps
CPU time 1.08 seconds
Started May 19 01:40:13 PM PDT 24
Finished May 19 01:40:14 PM PDT 24
Peak memory 217768 kb
Host smart-1ecc2c44-4a36-40f1-8b81-2b3e3bf33d06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084308443 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3084308443
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.1757466567
Short name T163
Test name
Test status
Simulation time 11521008 ps
CPU time 0.82 seconds
Started May 19 01:40:13 PM PDT 24
Finished May 19 01:40:15 PM PDT 24
Peak memory 209228 kb
Host smart-4f5e5aa7-8d41-4e5b-8791-e4c428bfa0f5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757466567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.1757466567
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3192730896
Short name T914
Test name
Test status
Simulation time 74729485 ps
CPU time 1.34 seconds
Started May 19 01:40:12 PM PDT 24
Finished May 19 01:40:14 PM PDT 24
Peak memory 209428 kb
Host smart-fc8f4cd7-7a45-476b-9f40-3b8d2f3437de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192730896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.3192730896
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2409904914
Short name T958
Test name
Test status
Simulation time 892907623 ps
CPU time 5.12 seconds
Started May 19 01:40:11 PM PDT 24
Finished May 19 01:40:17 PM PDT 24
Peak memory 217652 kb
Host smart-f0c45a73-ac1c-4076-ace7-a8c9b96f1aee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409904914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2409904914
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1067081730
Short name T948
Test name
Test status
Simulation time 101151684 ps
CPU time 1.04 seconds
Started May 19 01:40:17 PM PDT 24
Finished May 19 01:40:19 PM PDT 24
Peak memory 218680 kb
Host smart-4de73cc8-8113-41f6-a14b-d9af2caaa52a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067081730 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1067081730
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3703989227
Short name T898
Test name
Test status
Simulation time 16328609 ps
CPU time 0.9 seconds
Started May 19 01:40:20 PM PDT 24
Finished May 19 01:40:21 PM PDT 24
Peak memory 208948 kb
Host smart-41fd9b1f-3d28-4912-9c1c-3d35692ba619
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703989227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3703989227
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1193593701
Short name T960
Test name
Test status
Simulation time 123404632 ps
CPU time 1.52 seconds
Started May 19 01:40:23 PM PDT 24
Finished May 19 01:40:26 PM PDT 24
Peak memory 209384 kb
Host smart-f09ef5bf-5e41-4c2b-8081-3fd8d141de37
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193593701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1193593701
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2055211535
Short name T979
Test name
Test status
Simulation time 41668197 ps
CPU time 2.85 seconds
Started May 19 01:40:17 PM PDT 24
Finished May 19 01:40:21 PM PDT 24
Peak memory 217740 kb
Host smart-fc1797af-9899-4bc1-8f49-d01c73e130b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055211535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2055211535
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3669127471
Short name T876
Test name
Test status
Simulation time 69638487 ps
CPU time 1.03 seconds
Started May 19 01:40:18 PM PDT 24
Finished May 19 01:40:20 PM PDT 24
Peak memory 218848 kb
Host smart-a45639ad-bfec-42c7-9e9c-441744d4668f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669127471 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3669127471
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3837672212
Short name T162
Test name
Test status
Simulation time 12916387 ps
CPU time 1.02 seconds
Started May 19 01:40:18 PM PDT 24
Finished May 19 01:40:20 PM PDT 24
Peak memory 209432 kb
Host smart-323dc3ac-dbe7-41ed-9a90-f821f5a09ec0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837672212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3837672212
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3802169540
Short name T961
Test name
Test status
Simulation time 92536023 ps
CPU time 1.05 seconds
Started May 19 01:40:18 PM PDT 24
Finished May 19 01:40:20 PM PDT 24
Peak memory 209412 kb
Host smart-1a0e8efb-865a-407c-a71e-578b74372f3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802169540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3802169540
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.228367820
Short name T155
Test name
Test status
Simulation time 69697935 ps
CPU time 1.12 seconds
Started May 19 01:39:19 PM PDT 24
Finished May 19 01:39:21 PM PDT 24
Peak memory 209396 kb
Host smart-8cf66ce6-2c21-4073-8d7f-8c8cb90a597d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228367820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.228367820
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.4017594074
Short name T981
Test name
Test status
Simulation time 88822643 ps
CPU time 1.37 seconds
Started May 19 01:39:18 PM PDT 24
Finished May 19 01:39:19 PM PDT 24
Peak memory 209424 kb
Host smart-846e6824-eedc-4f17-962a-bda3d1f77b11
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017594074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.4017594074
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1481961181
Short name T132
Test name
Test status
Simulation time 16369376 ps
CPU time 1.08 seconds
Started May 19 01:39:19 PM PDT 24
Finished May 19 01:39:20 PM PDT 24
Peak memory 209952 kb
Host smart-654df99f-f32a-468b-bd3d-98167c6f04fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481961181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1481961181
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.223957982
Short name T970
Test name
Test status
Simulation time 81051179 ps
CPU time 1.34 seconds
Started May 19 01:39:18 PM PDT 24
Finished May 19 01:39:20 PM PDT 24
Peak memory 217656 kb
Host smart-028a7c30-837f-4981-8db6-ae30860a62d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223957982 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.223957982
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.2725872641
Short name T886
Test name
Test status
Simulation time 53030014 ps
CPU time 0.92 seconds
Started May 19 01:39:21 PM PDT 24
Finished May 19 01:39:22 PM PDT 24
Peak memory 217612 kb
Host smart-9a6a42e7-ab77-4543-a4b5-1e7dbc398f95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725872641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.2725872641
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1599091918
Short name T937
Test name
Test status
Simulation time 114455296 ps
CPU time 1.35 seconds
Started May 19 01:39:20 PM PDT 24
Finished May 19 01:39:22 PM PDT 24
Peak memory 209292 kb
Host smart-14f4de2c-fc59-4e96-9bbb-672517ce59ae
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599091918 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1599091918
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1866317027
Short name T123
Test name
Test status
Simulation time 747717003 ps
CPU time 4.96 seconds
Started May 19 01:39:20 PM PDT 24
Finished May 19 01:39:25 PM PDT 24
Peak memory 209148 kb
Host smart-82284edf-2798-4e53-85aa-34a7e43df53c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866317027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1866317027
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.1431675544
Short name T971
Test name
Test status
Simulation time 1508753735 ps
CPU time 4.6 seconds
Started May 19 01:39:14 PM PDT 24
Finished May 19 01:39:19 PM PDT 24
Peak memory 209248 kb
Host smart-34c68c53-8b90-45b5-a174-db38b5be278a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431675544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.1431675544
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2075627032
Short name T915
Test name
Test status
Simulation time 252922625 ps
CPU time 2.21 seconds
Started May 19 01:39:13 PM PDT 24
Finished May 19 01:39:16 PM PDT 24
Peak memory 210804 kb
Host smart-7f2a94d7-7073-473d-a1b1-58d57c6a303d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075627032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2075627032
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4195105225
Short name T972
Test name
Test status
Simulation time 283626610 ps
CPU time 1.53 seconds
Started May 19 01:39:18 PM PDT 24
Finished May 19 01:39:20 PM PDT 24
Peak memory 218764 kb
Host smart-e113ead2-c337-4f64-95dd-7e35cb9fc66a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419510
5225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4195105225
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3748292849
Short name T928
Test name
Test status
Simulation time 47471735 ps
CPU time 1.82 seconds
Started May 19 01:39:14 PM PDT 24
Finished May 19 01:39:16 PM PDT 24
Peak memory 209272 kb
Host smart-dcde228d-4ed7-4af9-8617-4a3cd3f01b5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748292849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3748292849
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.864366896
Short name T983
Test name
Test status
Simulation time 44922235 ps
CPU time 1.43 seconds
Started May 19 01:39:19 PM PDT 24
Finished May 19 01:39:21 PM PDT 24
Peak memory 217584 kb
Host smart-0dba7dec-4e34-4ed9-be28-6a0e4d897303
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864366896 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.864366896
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1544816010
Short name T130
Test name
Test status
Simulation time 50508734 ps
CPU time 2.18 seconds
Started May 19 01:39:19 PM PDT 24
Finished May 19 01:39:22 PM PDT 24
Peak memory 211428 kb
Host smart-499ec53f-92f0-49ac-8c7f-5ec22069bfa7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544816010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1544816010
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.2307478069
Short name T894
Test name
Test status
Simulation time 54617656 ps
CPU time 2.54 seconds
Started May 19 01:39:19 PM PDT 24
Finished May 19 01:39:22 PM PDT 24
Peak memory 217708 kb
Host smart-8a98fff7-aa4d-4ef3-a447-bedb4aba0a02
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307478069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.2307478069
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1188177073
Short name T930
Test name
Test status
Simulation time 434547503 ps
CPU time 2.21 seconds
Started May 19 01:39:20 PM PDT 24
Finished May 19 01:39:23 PM PDT 24
Peak memory 217616 kb
Host smart-cb2e329d-7a4b-4f38-a92d-5cde6527a90b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188177073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.1188177073
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2079919731
Short name T158
Test name
Test status
Simulation time 16703360 ps
CPU time 1.02 seconds
Started May 19 01:39:28 PM PDT 24
Finished May 19 01:39:30 PM PDT 24
Peak memory 209492 kb
Host smart-cfa8fe2f-25a5-4ed8-aa15-8a540b3e3c8b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079919731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.2079919731
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2503887104
Short name T877
Test name
Test status
Simulation time 26549971 ps
CPU time 1.51 seconds
Started May 19 01:39:29 PM PDT 24
Finished May 19 01:39:31 PM PDT 24
Peak memory 209484 kb
Host smart-58e83178-f8e8-4f79-a48e-291ee47fe3e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503887104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.2503887104
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.4188303021
Short name T156
Test name
Test status
Simulation time 13208364 ps
CPU time 0.89 seconds
Started May 19 01:39:28 PM PDT 24
Finished May 19 01:39:29 PM PDT 24
Peak memory 209712 kb
Host smart-a2c4bf36-4050-4965-9ddb-7121b0606342
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188303021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.4188303021
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3196970078
Short name T891
Test name
Test status
Simulation time 71866213 ps
CPU time 1.44 seconds
Started May 19 01:39:28 PM PDT 24
Finished May 19 01:39:30 PM PDT 24
Peak memory 218988 kb
Host smart-409a1457-ef23-4b01-bdc4-f8c8eb103bc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196970078 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.3196970078
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2289913504
Short name T160
Test name
Test status
Simulation time 38769867 ps
CPU time 0.82 seconds
Started May 19 01:39:29 PM PDT 24
Finished May 19 01:39:31 PM PDT 24
Peak memory 209276 kb
Host smart-5b0709a9-53af-4e28-9ff6-32c1764ba476
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289913504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2289913504
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1067098970
Short name T913
Test name
Test status
Simulation time 94370719 ps
CPU time 1.79 seconds
Started May 19 01:39:27 PM PDT 24
Finished May 19 01:39:29 PM PDT 24
Peak memory 209208 kb
Host smart-c5a3960f-462b-4396-ac3e-2931ff7334ca
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067098970 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1067098970
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1507474588
Short name T1000
Test name
Test status
Simulation time 719783497 ps
CPU time 6.53 seconds
Started May 19 01:39:28 PM PDT 24
Finished May 19 01:39:36 PM PDT 24
Peak memory 208560 kb
Host smart-78c88f58-0e46-46f6-9a89-ae6c4bbafa66
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507474588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1507474588
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1403802004
Short name T963
Test name
Test status
Simulation time 2944846317 ps
CPU time 30.74 seconds
Started May 19 01:39:23 PM PDT 24
Finished May 19 01:39:54 PM PDT 24
Peak memory 209360 kb
Host smart-a14fbbb7-2d1b-41fd-89fb-fa91dfc5342c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403802004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.1403802004
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.310625595
Short name T878
Test name
Test status
Simulation time 51959942 ps
CPU time 1.21 seconds
Started May 19 01:39:24 PM PDT 24
Finished May 19 01:39:26 PM PDT 24
Peak memory 210488 kb
Host smart-cdd008fb-b972-4974-ade5-9b75e003336b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310625595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.310625595
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2830370477
Short name T917
Test name
Test status
Simulation time 119929599 ps
CPU time 1.4 seconds
Started May 19 01:39:27 PM PDT 24
Finished May 19 01:39:29 PM PDT 24
Peak memory 217840 kb
Host smart-1d3420ab-a7b6-49ec-a63d-4faa100b4c53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283037
0477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2830370477
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.4236448413
Short name T909
Test name
Test status
Simulation time 281085505 ps
CPU time 1.68 seconds
Started May 19 01:39:22 PM PDT 24
Finished May 19 01:39:24 PM PDT 24
Peak memory 208424 kb
Host smart-08ef55dd-932d-4ef5-bdad-3f119b4f7e64
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236448413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.4236448413
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2202126153
Short name T100
Test name
Test status
Simulation time 69171835 ps
CPU time 1.27 seconds
Started May 19 01:39:27 PM PDT 24
Finished May 19 01:39:29 PM PDT 24
Peak memory 211344 kb
Host smart-39aca234-7dae-4237-b8d4-f8598239161c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202126153 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2202126153
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.310881652
Short name T124
Test name
Test status
Simulation time 248516014 ps
CPU time 1.15 seconds
Started May 19 01:39:29 PM PDT 24
Finished May 19 01:39:30 PM PDT 24
Peak memory 209496 kb
Host smart-f4c47598-005e-49df-ad1c-7eb900a8da32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310881652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.310881652
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.794173731
Short name T907
Test name
Test status
Simulation time 26776910 ps
CPU time 1.59 seconds
Started May 19 01:39:28 PM PDT 24
Finished May 19 01:39:30 PM PDT 24
Peak memory 217772 kb
Host smart-50bf962c-ab33-4e14-b93c-71ab8c6fc160
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794173731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.794173731
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.782207519
Short name T947
Test name
Test status
Simulation time 50582028 ps
CPU time 1.03 seconds
Started May 19 01:39:37 PM PDT 24
Finished May 19 01:39:38 PM PDT 24
Peak memory 209456 kb
Host smart-002b868e-3058-41d3-b8ff-0961ff46ac6d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782207519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing
.782207519
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3326969039
Short name T884
Test name
Test status
Simulation time 112387293 ps
CPU time 1.88 seconds
Started May 19 01:39:39 PM PDT 24
Finished May 19 01:39:41 PM PDT 24
Peak memory 208604 kb
Host smart-fd946c1a-ca62-442a-9b0c-3db99cd8dfaf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326969039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3326969039
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2410623297
Short name T164
Test name
Test status
Simulation time 35028946 ps
CPU time 0.99 seconds
Started May 19 01:39:31 PM PDT 24
Finished May 19 01:39:33 PM PDT 24
Peak memory 209976 kb
Host smart-2967ddc6-4255-47a4-8f94-30c96acc0e97
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410623297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2410623297
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1584836677
Short name T998
Test name
Test status
Simulation time 87637381 ps
CPU time 1.31 seconds
Started May 19 01:39:38 PM PDT 24
Finished May 19 01:39:40 PM PDT 24
Peak memory 217688 kb
Host smart-cfda0471-8207-4886-96f8-fea3954e466b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1584836677 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1584836677
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3337932113
Short name T911
Test name
Test status
Simulation time 16139526 ps
CPU time 0.88 seconds
Started May 19 01:39:36 PM PDT 24
Finished May 19 01:39:37 PM PDT 24
Peak memory 209612 kb
Host smart-2b4dbe8b-531d-4fda-b041-67c9984898af
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337932113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.3337932113
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2694938686
Short name T997
Test name
Test status
Simulation time 94321332 ps
CPU time 1.82 seconds
Started May 19 01:39:32 PM PDT 24
Finished May 19 01:39:34 PM PDT 24
Peak memory 208008 kb
Host smart-418ebe7f-e1b3-4492-a4cd-6fc191333442
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694938686 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.2694938686
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3855805926
Short name T949
Test name
Test status
Simulation time 326426146 ps
CPU time 3.6 seconds
Started May 19 01:39:35 PM PDT 24
Finished May 19 01:39:39 PM PDT 24
Peak memory 209120 kb
Host smart-ffdfac8c-4b12-426d-8ac8-ba0aeeb21f6e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855805926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.3855805926
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3251186725
Short name T875
Test name
Test status
Simulation time 6758065471 ps
CPU time 18.45 seconds
Started May 19 01:39:32 PM PDT 24
Finished May 19 01:39:51 PM PDT 24
Peak memory 209324 kb
Host smart-e2ec3ea4-5a4f-41ec-8980-c9439281aaab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251186725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3251186725
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3170348985
Short name T957
Test name
Test status
Simulation time 83449675 ps
CPU time 1.48 seconds
Started May 19 01:39:32 PM PDT 24
Finished May 19 01:39:34 PM PDT 24
Peak memory 210700 kb
Host smart-70daf853-ded0-4317-8485-56c9426fa567
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3170348985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.3170348985
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.17618759
Short name T950
Test name
Test status
Simulation time 199269561 ps
CPU time 1.67 seconds
Started May 19 01:39:33 PM PDT 24
Finished May 19 01:39:35 PM PDT 24
Peak memory 217780 kb
Host smart-5d6b4cda-c3d8-4e21-ba11-743d67ae4564
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176187
59 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.17618759
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2469133097
Short name T912
Test name
Test status
Simulation time 91147728 ps
CPU time 1.61 seconds
Started May 19 01:39:34 PM PDT 24
Finished May 19 01:39:37 PM PDT 24
Peak memory 209304 kb
Host smart-c312270f-254e-4524-a84f-9adff5fb7cfb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469133097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2469133097
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2156205495
Short name T968
Test name
Test status
Simulation time 160759143 ps
CPU time 1.37 seconds
Started May 19 01:39:34 PM PDT 24
Finished May 19 01:39:37 PM PDT 24
Peak memory 209352 kb
Host smart-e4defff3-a756-4150-875e-cb81645b709b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156205495 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2156205495
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1912471524
Short name T942
Test name
Test status
Simulation time 138329726 ps
CPU time 1.31 seconds
Started May 19 01:39:38 PM PDT 24
Finished May 19 01:39:40 PM PDT 24
Peak memory 211508 kb
Host smart-3495383f-680b-4314-a593-ad2d350dfbcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912471524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1912471524
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.4014990766
Short name T887
Test name
Test status
Simulation time 369710170 ps
CPU time 2.65 seconds
Started May 19 01:39:34 PM PDT 24
Finished May 19 01:39:37 PM PDT 24
Peak memory 218696 kb
Host smart-b56ea8fd-6875-4199-b85e-931301c4d590
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014990766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.4014990766
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.391331691
Short name T985
Test name
Test status
Simulation time 28347606 ps
CPU time 1.21 seconds
Started May 19 01:39:45 PM PDT 24
Finished May 19 01:39:47 PM PDT 24
Peak memory 217612 kb
Host smart-a9e9d977-26ce-456f-9049-91a2b84dad9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391331691 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.391331691
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2417729048
Short name T157
Test name
Test status
Simulation time 170497967 ps
CPU time 0.99 seconds
Started May 19 01:39:40 PM PDT 24
Finished May 19 01:39:42 PM PDT 24
Peak memory 209396 kb
Host smart-dc9df871-67f6-4061-bf8a-33d37ff963f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417729048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2417729048
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3676515626
Short name T890
Test name
Test status
Simulation time 39815833 ps
CPU time 1.18 seconds
Started May 19 01:39:43 PM PDT 24
Finished May 19 01:39:44 PM PDT 24
Peak memory 208028 kb
Host smart-7bc6419f-b396-4d24-a41f-010a9054cdfd
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676515626 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3676515626
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1621928904
Short name T902
Test name
Test status
Simulation time 3889200351 ps
CPU time 7.05 seconds
Started May 19 01:39:36 PM PDT 24
Finished May 19 01:39:44 PM PDT 24
Peak memory 208572 kb
Host smart-309e0c1e-717a-466b-b951-8ce7c65a6395
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621928904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1621928904
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1169182317
Short name T918
Test name
Test status
Simulation time 6360678042 ps
CPU time 6.11 seconds
Started May 19 01:39:38 PM PDT 24
Finished May 19 01:39:45 PM PDT 24
Peak memory 209380 kb
Host smart-7fb85ac7-3094-44a8-8dd1-f9f8b7122f4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169182317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1169182317
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1944233019
Short name T989
Test name
Test status
Simulation time 106747054 ps
CPU time 1.56 seconds
Started May 19 01:39:37 PM PDT 24
Finished May 19 01:39:39 PM PDT 24
Peak memory 208732 kb
Host smart-3aa22305-7dfe-4e19-b401-f6af47d743de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944233019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1944233019
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1220151180
Short name T976
Test name
Test status
Simulation time 58485558 ps
CPU time 2.21 seconds
Started May 19 01:39:45 PM PDT 24
Finished May 19 01:39:48 PM PDT 24
Peak memory 217608 kb
Host smart-7b1393a8-80dd-47c2-9625-770b1ae3e55d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122015
1180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1220151180
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3443818921
Short name T938
Test name
Test status
Simulation time 79432294 ps
CPU time 1.57 seconds
Started May 19 01:39:35 PM PDT 24
Finished May 19 01:39:37 PM PDT 24
Peak memory 208568 kb
Host smart-0be0f8fb-3055-4672-8420-72c715b7f139
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443818921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.3443818921
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1228120911
Short name T168
Test name
Test status
Simulation time 114462365 ps
CPU time 1.09 seconds
Started May 19 01:39:41 PM PDT 24
Finished May 19 01:39:43 PM PDT 24
Peak memory 209156 kb
Host smart-826f4bef-8c5b-44c4-9683-c1f6bac70ea8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228120911 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1228120911
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1688049431
Short name T171
Test name
Test status
Simulation time 85813593 ps
CPU time 1.72 seconds
Started May 19 01:39:43 PM PDT 24
Finished May 19 01:39:46 PM PDT 24
Peak memory 209408 kb
Host smart-7b4850ef-026b-4df2-8f33-bf57babfd351
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688049431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1688049431
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1859085826
Short name T992
Test name
Test status
Simulation time 86632419 ps
CPU time 3.48 seconds
Started May 19 01:39:42 PM PDT 24
Finished May 19 01:39:46 PM PDT 24
Peak memory 218708 kb
Host smart-32f4b771-ce04-4362-beb0-1446d816e74c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859085826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1859085826
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2388429674
Short name T178
Test name
Test status
Simulation time 93283407 ps
CPU time 1.73 seconds
Started May 19 01:39:41 PM PDT 24
Finished May 19 01:39:43 PM PDT 24
Peak memory 221684 kb
Host smart-39422c04-bafe-407f-a9eb-42b257079717
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388429674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2388429674
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.2553971289
Short name T991
Test name
Test status
Simulation time 96726700 ps
CPU time 1.08 seconds
Started May 19 01:39:46 PM PDT 24
Finished May 19 01:39:48 PM PDT 24
Peak memory 217760 kb
Host smart-64df8045-0de9-42a5-878b-6bd04ae592cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553971289 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.2553971289
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2854954963
Short name T159
Test name
Test status
Simulation time 11421674 ps
CPU time 0.87 seconds
Started May 19 01:39:48 PM PDT 24
Finished May 19 01:39:49 PM PDT 24
Peak memory 208752 kb
Host smart-f7e06841-095d-497b-a6eb-b2e5f7b09589
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854954963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.2854954963
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1118922298
Short name T936
Test name
Test status
Simulation time 55079199 ps
CPU time 1.37 seconds
Started May 19 01:39:46 PM PDT 24
Finished May 19 01:39:48 PM PDT 24
Peak memory 209288 kb
Host smart-46655b97-140c-49e8-8029-32202790d898
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118922298 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1118922298
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.753411553
Short name T919
Test name
Test status
Simulation time 1169854566 ps
CPU time 3.33 seconds
Started May 19 01:39:42 PM PDT 24
Finished May 19 01:39:46 PM PDT 24
Peak memory 209180 kb
Host smart-2cf0fbbe-c2bd-403f-befb-ed4915054227
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753411553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.753411553
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1268053127
Short name T974
Test name
Test status
Simulation time 1083201253 ps
CPU time 23.95 seconds
Started May 19 01:39:43 PM PDT 24
Finished May 19 01:40:07 PM PDT 24
Peak memory 209164 kb
Host smart-a3a298be-107c-4515-a2a7-b1ace8f6cc68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268053127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1268053127
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2759030850
Short name T986
Test name
Test status
Simulation time 559306965 ps
CPU time 1.74 seconds
Started May 19 01:39:41 PM PDT 24
Finished May 19 01:39:43 PM PDT 24
Peak memory 210940 kb
Host smart-66c6f435-cf61-4d0f-81a8-ce94a4409330
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759030850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2759030850
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2816328797
Short name T954
Test name
Test status
Simulation time 321872279 ps
CPU time 2.6 seconds
Started May 19 01:39:41 PM PDT 24
Finished May 19 01:39:45 PM PDT 24
Peak memory 209292 kb
Host smart-c764c2a3-1aad-4dd8-9a64-ff07c8d4bb4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816328797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.2816328797
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.230083747
Short name T170
Test name
Test status
Simulation time 18653724 ps
CPU time 0.97 seconds
Started May 19 01:39:45 PM PDT 24
Finished May 19 01:39:46 PM PDT 24
Peak memory 209336 kb
Host smart-18f054a7-61da-4165-8726-3f535331ac98
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230083747 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.230083747
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3510453422
Short name T169
Test name
Test status
Simulation time 72791904 ps
CPU time 1.27 seconds
Started May 19 01:39:47 PM PDT 24
Finished May 19 01:39:49 PM PDT 24
Peak memory 209144 kb
Host smart-50eff7eb-3f8e-4420-bdd1-83cc6fa728e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510453422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3510453422
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.432296915
Short name T987
Test name
Test status
Simulation time 70387967 ps
CPU time 1.82 seconds
Started May 19 01:39:51 PM PDT 24
Finished May 19 01:39:53 PM PDT 24
Peak memory 217664 kb
Host smart-0e057bd4-d53b-4877-8b46-e5f6c3d3a52d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432296915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.432296915
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1720088139
Short name T975
Test name
Test status
Simulation time 27854424 ps
CPU time 1.25 seconds
Started May 19 01:39:52 PM PDT 24
Finished May 19 01:39:54 PM PDT 24
Peak memory 217728 kb
Host smart-f856b096-fb80-4a7f-ba09-db762ee0e301
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720088139 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1720088139
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.1183099085
Short name T944
Test name
Test status
Simulation time 20585477 ps
CPU time 1 seconds
Started May 19 01:39:52 PM PDT 24
Finished May 19 01:39:54 PM PDT 24
Peak memory 209592 kb
Host smart-f94f4178-15f8-4bd3-b725-e0827cab1bf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183099085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.1183099085
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.869873649
Short name T921
Test name
Test status
Simulation time 44712936 ps
CPU time 1.68 seconds
Started May 19 01:39:50 PM PDT 24
Finished May 19 01:39:52 PM PDT 24
Peak memory 209268 kb
Host smart-1dbefd0a-821e-4197-b7fb-f77b33174665
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869873649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.lc_ctrl_jtag_alert_test.869873649
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2490396016
Short name T908
Test name
Test status
Simulation time 260504880 ps
CPU time 2.7 seconds
Started May 19 01:39:49 PM PDT 24
Finished May 19 01:39:52 PM PDT 24
Peak memory 209172 kb
Host smart-8dd5f288-1cb4-48c8-ae2f-aeeabe182ea3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490396016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2490396016
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3131187693
Short name T105
Test name
Test status
Simulation time 4615315901 ps
CPU time 8.81 seconds
Started May 19 01:39:48 PM PDT 24
Finished May 19 01:39:57 PM PDT 24
Peak memory 209396 kb
Host smart-87ed01c5-d27b-4d51-b7e2-75d7b2228f6e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131187693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3131187693
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3048315911
Short name T903
Test name
Test status
Simulation time 111186619 ps
CPU time 1.72 seconds
Started May 19 01:39:49 PM PDT 24
Finished May 19 01:39:51 PM PDT 24
Peak memory 210652 kb
Host smart-584dc1f7-9367-47bb-a30f-00f4df9e1dd3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048315911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3048315911
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3771128411
Short name T96
Test name
Test status
Simulation time 83091717 ps
CPU time 1.64 seconds
Started May 19 01:39:55 PM PDT 24
Finished May 19 01:39:57 PM PDT 24
Peak memory 220816 kb
Host smart-114a4b5d-3528-4973-8ba3-ca856be73dd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377112
8411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3771128411
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2272898276
Short name T879
Test name
Test status
Simulation time 109995578 ps
CPU time 2.92 seconds
Started May 19 01:39:47 PM PDT 24
Finished May 19 01:39:51 PM PDT 24
Peak memory 209332 kb
Host smart-d0c0c027-21f2-4a76-bb38-3b36d1b8a0eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272898276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2272898276
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.803881672
Short name T984
Test name
Test status
Simulation time 53646307 ps
CPU time 1.43 seconds
Started May 19 01:39:48 PM PDT 24
Finished May 19 01:39:50 PM PDT 24
Peak memory 211544 kb
Host smart-c4033e8f-8108-4f2f-a9f8-1286f1f59fde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803881672 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.803881672
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.4158078580
Short name T966
Test name
Test status
Simulation time 14886716 ps
CPU time 0.98 seconds
Started May 19 01:39:53 PM PDT 24
Finished May 19 01:39:55 PM PDT 24
Peak memory 209376 kb
Host smart-47d34c89-b702-492e-852c-c48b38b0fd6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158078580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.4158078580
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.406888724
Short name T939
Test name
Test status
Simulation time 58235155 ps
CPU time 1.46 seconds
Started May 19 01:39:50 PM PDT 24
Finished May 19 01:39:52 PM PDT 24
Peak memory 218696 kb
Host smart-a60c0bc2-e33d-4bf8-8473-b650fe4735ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406888724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.406888724
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.202523914
Short name T99
Test name
Test status
Simulation time 110736386 ps
CPU time 4.12 seconds
Started May 19 01:39:53 PM PDT 24
Finished May 19 01:39:58 PM PDT 24
Peak memory 217560 kb
Host smart-15083506-8648-4882-ad17-af30eb2bc438
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202523914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.202523914
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2985180008
Short name T935
Test name
Test status
Simulation time 51165205 ps
CPU time 1.19 seconds
Started May 19 01:39:59 PM PDT 24
Finished May 19 01:40:01 PM PDT 24
Peak memory 217748 kb
Host smart-74104f8d-c4f0-4dea-85be-48889ff6d63d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985180008 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.2985180008
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2528502597
Short name T154
Test name
Test status
Simulation time 20443023 ps
CPU time 0.95 seconds
Started May 19 01:39:54 PM PDT 24
Finished May 19 01:39:55 PM PDT 24
Peak memory 209352 kb
Host smart-7b6b3888-d9f8-420a-96dd-9e9ef195c013
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528502597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2528502597
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2708428033
Short name T926
Test name
Test status
Simulation time 127540405 ps
CPU time 1.59 seconds
Started May 19 01:39:54 PM PDT 24
Finished May 19 01:39:56 PM PDT 24
Peak memory 209316 kb
Host smart-a63cd0f4-fdd2-427a-b73c-90cc72ecda4d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708428033 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2708428033
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.998212049
Short name T893
Test name
Test status
Simulation time 1247480040 ps
CPU time 7.83 seconds
Started May 19 01:39:53 PM PDT 24
Finished May 19 01:40:01 PM PDT 24
Peak memory 209184 kb
Host smart-69ecabc7-52fc-41d8-94b7-b7a8cf358a06
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998212049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.998212049
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2356459172
Short name T873
Test name
Test status
Simulation time 2258459033 ps
CPU time 16.82 seconds
Started May 19 01:39:51 PM PDT 24
Finished May 19 01:40:08 PM PDT 24
Peak memory 209184 kb
Host smart-6431c8cb-79d2-4c6b-92ff-eb81abe06d79
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356459172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2356459172
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2310073784
Short name T904
Test name
Test status
Simulation time 174338084 ps
CPU time 1.75 seconds
Started May 19 01:39:54 PM PDT 24
Finished May 19 01:39:56 PM PDT 24
Peak memory 211012 kb
Host smart-4a13cb86-0daf-4d33-90bb-6475f04f3f38
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310073784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2310073784
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1503809059
Short name T109
Test name
Test status
Simulation time 565255974 ps
CPU time 1.91 seconds
Started May 19 01:39:54 PM PDT 24
Finished May 19 01:39:56 PM PDT 24
Peak memory 218744 kb
Host smart-e6682f56-4d67-48ec-90f0-36a840dba20d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150380
9059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1503809059
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.738935044
Short name T978
Test name
Test status
Simulation time 38838931 ps
CPU time 1.55 seconds
Started May 19 01:39:56 PM PDT 24
Finished May 19 01:39:58 PM PDT 24
Peak memory 209364 kb
Host smart-ee3d44e7-c532-4461-935b-ae687595aaf0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738935044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.738935044
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.4095678150
Short name T980
Test name
Test status
Simulation time 107280611 ps
CPU time 1.26 seconds
Started May 19 01:39:50 PM PDT 24
Finished May 19 01:39:52 PM PDT 24
Peak memory 209396 kb
Host smart-83e0bddd-bfb8-424f-9eed-791e2c59d4ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095678150 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.4095678150
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1687458785
Short name T166
Test name
Test status
Simulation time 25448043 ps
CPU time 1.36 seconds
Started May 19 01:39:57 PM PDT 24
Finished May 19 01:39:59 PM PDT 24
Peak memory 209416 kb
Host smart-c9be9f20-9b2a-4624-b690-fbb47399d9eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687458785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1687458785
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3469424998
Short name T97
Test name
Test status
Simulation time 146361511 ps
CPU time 2.19 seconds
Started May 19 01:39:53 PM PDT 24
Finished May 19 01:39:55 PM PDT 24
Peak memory 217712 kb
Host smart-6a6f214d-3983-4050-af9c-1e5bf193ce8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469424998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3469424998
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3128226149
Short name T110
Test name
Test status
Simulation time 471426378 ps
CPU time 2.97 seconds
Started May 19 01:39:53 PM PDT 24
Finished May 19 01:39:57 PM PDT 24
Peak memory 222368 kb
Host smart-48e879db-0a35-4a3b-bb1f-011b9e718747
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128226149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3128226149
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2370076759
Short name T916
Test name
Test status
Simulation time 30548258 ps
CPU time 1.1 seconds
Started May 19 01:40:02 PM PDT 24
Finished May 19 01:40:04 PM PDT 24
Peak memory 219520 kb
Host smart-e744e24f-4ded-49f5-964f-de0e3c87017e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370076759 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2370076759
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.2554686327
Short name T965
Test name
Test status
Simulation time 23023314 ps
CPU time 0.81 seconds
Started May 19 01:39:55 PM PDT 24
Finished May 19 01:39:56 PM PDT 24
Peak memory 208748 kb
Host smart-38285872-ad10-46db-b0c7-5d9e5a61e3cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554686327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.2554686327
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.973887979
Short name T888
Test name
Test status
Simulation time 209129757 ps
CPU time 1.26 seconds
Started May 19 01:39:57 PM PDT 24
Finished May 19 01:39:59 PM PDT 24
Peak memory 209224 kb
Host smart-09d9a152-0c28-4293-bf4d-15823afca069
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973887979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.973887979
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1346322635
Short name T885
Test name
Test status
Simulation time 918411864 ps
CPU time 5.4 seconds
Started May 19 01:39:57 PM PDT 24
Finished May 19 01:40:03 PM PDT 24
Peak memory 209140 kb
Host smart-d96eb322-1f4c-49ba-8619-85a044b41a94
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346322635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1346322635
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2355801889
Short name T897
Test name
Test status
Simulation time 17592203537 ps
CPU time 14.37 seconds
Started May 19 01:39:57 PM PDT 24
Finished May 19 01:40:11 PM PDT 24
Peak memory 209596 kb
Host smart-d2c4a1db-432a-4e3a-a81d-bdd54e0beea8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355801889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2355801889
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2086770736
Short name T990
Test name
Test status
Simulation time 232935790 ps
CPU time 2.04 seconds
Started May 19 01:39:59 PM PDT 24
Finished May 19 01:40:01 PM PDT 24
Peak memory 211028 kb
Host smart-659c8307-98cc-4f85-af07-a8bc5f061b34
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086770736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2086770736
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3794377681
Short name T931
Test name
Test status
Simulation time 398566659 ps
CPU time 2.85 seconds
Started May 19 01:39:55 PM PDT 24
Finished May 19 01:39:59 PM PDT 24
Peak memory 219048 kb
Host smart-35fb7a23-d9a7-4a26-ac8b-c095f13fc526
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379437
7681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3794377681
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1668716345
Short name T943
Test name
Test status
Simulation time 100771832 ps
CPU time 1.64 seconds
Started May 19 01:39:57 PM PDT 24
Finished May 19 01:40:00 PM PDT 24
Peak memory 209300 kb
Host smart-3d027ef5-fe7b-4e27-92fc-8cd1d6b0c427
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668716345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1668716345
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.911212682
Short name T906
Test name
Test status
Simulation time 23465514 ps
CPU time 1.49 seconds
Started May 19 01:39:57 PM PDT 24
Finished May 19 01:39:59 PM PDT 24
Peak memory 209392 kb
Host smart-13ded419-9cdb-40ac-b077-2600d0b6df71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911212682 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.911212682
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.649877610
Short name T996
Test name
Test status
Simulation time 42317652 ps
CPU time 1.96 seconds
Started May 19 01:39:57 PM PDT 24
Finished May 19 01:40:00 PM PDT 24
Peak memory 211352 kb
Host smart-f257465e-7aa9-43cf-a39b-7fc0a8943e62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649877610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.649877610
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1389093703
Short name T111
Test name
Test status
Simulation time 139007653 ps
CPU time 3.64 seconds
Started May 19 01:39:57 PM PDT 24
Finished May 19 01:40:02 PM PDT 24
Peak memory 217668 kb
Host smart-7fc2abc1-d63b-4d64-8a24-5c1136ac0f78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389093703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1389093703
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.1507678071
Short name T792
Test name
Test status
Simulation time 29661515 ps
CPU time 1.08 seconds
Started May 19 01:43:58 PM PDT 24
Finished May 19 01:44:02 PM PDT 24
Peak memory 209368 kb
Host smart-5cab903f-9ab4-4f62-bdfc-d94d9aaaaab5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507678071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.1507678071
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.2592255708
Short name T546
Test name
Test status
Simulation time 50894138 ps
CPU time 0.84 seconds
Started May 19 01:43:56 PM PDT 24
Finished May 19 01:44:00 PM PDT 24
Peak memory 209312 kb
Host smart-357d4468-f7e5-4bac-bf3c-93faa55c75dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592255708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.2592255708
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3441879396
Short name T662
Test name
Test status
Simulation time 641729609 ps
CPU time 11.31 seconds
Started May 19 01:44:02 PM PDT 24
Finished May 19 01:44:16 PM PDT 24
Peak memory 217832 kb
Host smart-1eaf63a7-66fa-474b-ac8c-da1260100457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441879396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3441879396
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2636744546
Short name T275
Test name
Test status
Simulation time 320226575 ps
CPU time 2.79 seconds
Started May 19 01:43:57 PM PDT 24
Finished May 19 01:44:03 PM PDT 24
Peak memory 209328 kb
Host smart-b0970ba6-6b5a-4fc6-8e5d-66dba9d5bdd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636744546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2636744546
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2669808588
Short name T817
Test name
Test status
Simulation time 3845574649 ps
CPU time 18.03 seconds
Started May 19 01:44:03 PM PDT 24
Finished May 19 01:44:24 PM PDT 24
Peak memory 217812 kb
Host smart-b9afa7e6-b8df-4290-b0e2-bf66ef829c1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669808588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2669808588
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.1431747828
Short name T492
Test name
Test status
Simulation time 2687645317 ps
CPU time 7.17 seconds
Started May 19 01:43:55 PM PDT 24
Finished May 19 01:44:06 PM PDT 24
Peak memory 217316 kb
Host smart-6c490a2f-e6c9-464a-b8df-094109952a03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431747828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.1
431747828
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.68992749
Short name T729
Test name
Test status
Simulation time 417733151 ps
CPU time 2.99 seconds
Started May 19 01:43:59 PM PDT 24
Finished May 19 01:44:05 PM PDT 24
Peak memory 217720 kb
Host smart-dccf6c38-4af3-4127-8a4c-04b82c5d10cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68992749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_p
rog_failure.68992749
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1913669538
Short name T856
Test name
Test status
Simulation time 1102461306 ps
CPU time 31.14 seconds
Started May 19 01:43:56 PM PDT 24
Finished May 19 01:44:30 PM PDT 24
Peak memory 212964 kb
Host smart-570e011b-2c1e-4991-a745-a9d0f2ce55d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913669538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.1913669538
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1211638163
Short name T563
Test name
Test status
Simulation time 529431447 ps
CPU time 6.82 seconds
Started May 19 01:43:56 PM PDT 24
Finished May 19 01:44:06 PM PDT 24
Peak memory 213540 kb
Host smart-2c53ae50-c334-43ba-a802-bc3a7ef0bda2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211638163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1211638163
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1694038009
Short name T250
Test name
Test status
Simulation time 11212025788 ps
CPU time 45.36 seconds
Started May 19 01:43:56 PM PDT 24
Finished May 19 01:44:44 PM PDT 24
Peak memory 267204 kb
Host smart-91d47029-e214-4043-aa33-b142d88dd064
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694038009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1694038009
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.545204419
Short name T295
Test name
Test status
Simulation time 1065092194 ps
CPU time 22.08 seconds
Started May 19 01:43:56 PM PDT 24
Finished May 19 01:44:21 PM PDT 24
Peak memory 250716 kb
Host smart-cf3345f4-1f3b-433e-b6d3-8c131c4d59fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545204419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.545204419
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3947876204
Short name T472
Test name
Test status
Simulation time 80269013 ps
CPU time 2.28 seconds
Started May 19 01:43:57 PM PDT 24
Finished May 19 01:44:03 PM PDT 24
Peak memory 217788 kb
Host smart-63dc3ab2-216c-4c27-a628-3a0d201e2b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947876204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3947876204
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.4152591447
Short name T646
Test name
Test status
Simulation time 253479114 ps
CPU time 14.01 seconds
Started May 19 01:43:55 PM PDT 24
Finished May 19 01:44:12 PM PDT 24
Peak memory 217540 kb
Host smart-388f0d1a-db2e-48d6-b487-32f53d11ab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152591447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.4152591447
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.1967115819
Short name T64
Test name
Test status
Simulation time 116186514 ps
CPU time 22.63 seconds
Started May 19 01:44:03 PM PDT 24
Finished May 19 01:44:29 PM PDT 24
Peak memory 268580 kb
Host smart-977f4656-1185-4e00-98f6-a7fd4a7446c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967115819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.1967115819
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2633237242
Short name T457
Test name
Test status
Simulation time 1228926653 ps
CPU time 9.17 seconds
Started May 19 01:44:00 PM PDT 24
Finished May 19 01:44:13 PM PDT 24
Peak memory 225800 kb
Host smart-9c771045-a847-434b-9950-b3c1176c9a40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633237242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2633237242
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.4190363592
Short name T611
Test name
Test status
Simulation time 888473521 ps
CPU time 10.53 seconds
Started May 19 01:43:58 PM PDT 24
Finished May 19 01:44:11 PM PDT 24
Peak memory 217880 kb
Host smart-60d4c947-5d97-4ea9-877a-7f2c68c82df1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190363592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.4190363592
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2560814940
Short name T338
Test name
Test status
Simulation time 1042358417 ps
CPU time 8.36 seconds
Started May 19 01:43:59 PM PDT 24
Finished May 19 01:44:10 PM PDT 24
Peak memory 217784 kb
Host smart-2d808654-3b62-401c-ac22-9f141184fd78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560814940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
560814940
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.4235986200
Short name T661
Test name
Test status
Simulation time 1100734007 ps
CPU time 6.86 seconds
Started May 19 01:43:59 PM PDT 24
Finished May 19 01:44:09 PM PDT 24
Peak memory 217844 kb
Host smart-14fb77ae-6f91-429d-8fe4-54571f7c4e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4235986200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.4235986200
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2340546985
Short name T71
Test name
Test status
Simulation time 204192557 ps
CPU time 3.47 seconds
Started May 19 01:43:52 PM PDT 24
Finished May 19 01:44:00 PM PDT 24
Peak memory 214440 kb
Host smart-32427e75-be98-4699-a3b0-5ec0ed1148f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340546985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2340546985
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1949133325
Short name T194
Test name
Test status
Simulation time 1390431600 ps
CPU time 19.6 seconds
Started May 19 01:44:03 PM PDT 24
Finished May 19 01:44:26 PM PDT 24
Peak memory 250744 kb
Host smart-f35b5230-af21-46f0-b868-04f4c0dd7a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949133325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1949133325
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1446616312
Short name T810
Test name
Test status
Simulation time 54036363 ps
CPU time 3.6 seconds
Started May 19 01:43:57 PM PDT 24
Finished May 19 01:44:04 PM PDT 24
Peak memory 222424 kb
Host smart-5af5ff0e-17ae-4645-8f31-123a8d8d8383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446616312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1446616312
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2024991131
Short name T494
Test name
Test status
Simulation time 12739173497 ps
CPU time 75.74 seconds
Started May 19 01:43:59 PM PDT 24
Finished May 19 01:45:17 PM PDT 24
Peak memory 225984 kb
Host smart-dda3793a-b1c5-455a-a415-4b85b96292a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024991131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2024991131
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.188734080
Short name T836
Test name
Test status
Simulation time 165809838983 ps
CPU time 1667.16 seconds
Started May 19 01:44:00 PM PDT 24
Finished May 19 02:11:51 PM PDT 24
Peak memory 905592 kb
Host smart-78daa1ed-0cb7-4eca-961d-74063f5e9c26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=188734080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.188734080
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3464358115
Short name T28
Test name
Test status
Simulation time 37468741 ps
CPU time 0.84 seconds
Started May 19 01:44:01 PM PDT 24
Finished May 19 01:44:05 PM PDT 24
Peak memory 209220 kb
Host smart-a9d0ec2b-a4ae-4b3b-bdd6-a62597ebb725
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464358115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3464358115
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.2165014490
Short name T685
Test name
Test status
Simulation time 22388510 ps
CPU time 0.81 seconds
Started May 19 01:44:03 PM PDT 24
Finished May 19 01:44:07 PM PDT 24
Peak memory 209236 kb
Host smart-4ac05d5c-7a21-4906-9c09-184d079be940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165014490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.2165014490
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2745015528
Short name T529
Test name
Test status
Simulation time 319052343 ps
CPU time 10.54 seconds
Started May 19 01:44:03 PM PDT 24
Finished May 19 01:44:17 PM PDT 24
Peak memory 217684 kb
Host smart-4af88dad-d13f-4536-970c-abbbdf3e7b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745015528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2745015528
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2841255698
Short name T148
Test name
Test status
Simulation time 308824244 ps
CPU time 2.4 seconds
Started May 19 01:43:55 PM PDT 24
Finished May 19 01:44:01 PM PDT 24
Peak memory 209364 kb
Host smart-7f876c4e-0b8e-4cef-a723-8d1e1b4ec991
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841255698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2841255698
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.106261827
Short name T195
Test name
Test status
Simulation time 2284490624 ps
CPU time 68.87 seconds
Started May 19 01:43:58 PM PDT 24
Finished May 19 01:45:10 PM PDT 24
Peak memory 217784 kb
Host smart-35b77389-70ef-4d43-8221-c8ff4fa43191
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106261827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.106261827
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.1057222927
Short name T173
Test name
Test status
Simulation time 1774279062 ps
CPU time 3.93 seconds
Started May 19 01:44:01 PM PDT 24
Finished May 19 01:44:08 PM PDT 24
Peak memory 217184 kb
Host smart-031a1c6f-8746-4d68-9fca-db73143b7911
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057222927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.1
057222927
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.4205134562
Short name T682
Test name
Test status
Simulation time 1016370280 ps
CPU time 10.79 seconds
Started May 19 01:44:02 PM PDT 24
Finished May 19 01:44:16 PM PDT 24
Peak memory 217700 kb
Host smart-e80128e9-db05-4833-959f-cc23b593d957
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205134562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.4205134562
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.3511367454
Short name T534
Test name
Test status
Simulation time 1785586421 ps
CPU time 10.27 seconds
Started May 19 01:44:02 PM PDT 24
Finished May 19 01:44:16 PM PDT 24
Peak memory 212980 kb
Host smart-d1cb99b2-4559-4c11-ad35-f88b25a07da0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511367454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.3511367454
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.3312042936
Short name T832
Test name
Test status
Simulation time 1182767609 ps
CPU time 7.62 seconds
Started May 19 01:43:56 PM PDT 24
Finished May 19 01:44:07 PM PDT 24
Peak memory 213236 kb
Host smart-b3e20bc0-6aff-4a82-bae6-0c582ad4f39a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312042936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
3312042936
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.822341828
Short name T837
Test name
Test status
Simulation time 4934620450 ps
CPU time 30.17 seconds
Started May 19 01:43:57 PM PDT 24
Finished May 19 01:44:31 PM PDT 24
Peak memory 250804 kb
Host smart-b26e67aa-7bcb-4758-8ee1-fecb15d00bda
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822341828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_state_failure.822341828
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.405290056
Short name T504
Test name
Test status
Simulation time 1859938841 ps
CPU time 13.61 seconds
Started May 19 01:44:00 PM PDT 24
Finished May 19 01:44:17 PM PDT 24
Peak memory 250628 kb
Host smart-509d2a57-2fd9-4ec3-97b3-f2b488cc2201
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405290056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.405290056
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.3156065264
Short name T262
Test name
Test status
Simulation time 361060180 ps
CPU time 4.44 seconds
Started May 19 01:44:02 PM PDT 24
Finished May 19 01:44:10 PM PDT 24
Peak memory 217756 kb
Host smart-1182b738-3abf-4883-afbb-725a4041167d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156065264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3156065264
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.1863868188
Short name T442
Test name
Test status
Simulation time 1049868010 ps
CPU time 9.75 seconds
Started May 19 01:44:03 PM PDT 24
Finished May 19 01:44:16 PM PDT 24
Peak memory 213476 kb
Host smart-22b272c3-0da0-404e-a16d-5e58d1569864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863868188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1863868188
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.420873218
Short name T47
Test name
Test status
Simulation time 1137757144 ps
CPU time 34.88 seconds
Started May 19 01:44:01 PM PDT 24
Finished May 19 01:44:39 PM PDT 24
Peak memory 283524 kb
Host smart-f0017766-a863-45d2-b0f3-91875973d726
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420873218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.420873218
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1068624794
Short name T764
Test name
Test status
Simulation time 283368762 ps
CPU time 11.5 seconds
Started May 19 01:44:02 PM PDT 24
Finished May 19 01:44:17 PM PDT 24
Peak memory 225852 kb
Host smart-b9d71382-45a9-4b46-92a6-f369089dd87b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068624794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1068624794
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.678805324
Short name T588
Test name
Test status
Simulation time 1622435815 ps
CPU time 9.04 seconds
Started May 19 01:44:01 PM PDT 24
Finished May 19 01:44:14 PM PDT 24
Peak memory 217788 kb
Host smart-5f1c7b91-b70f-4bcd-850a-0bd3c93902e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678805324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.678805324
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3530698785
Short name T676
Test name
Test status
Simulation time 567059137 ps
CPU time 12.1 seconds
Started May 19 01:44:04 PM PDT 24
Finished May 19 01:44:19 PM PDT 24
Peak memory 217728 kb
Host smart-96c0088f-cf61-4dbf-9628-2dd5f654ff0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530698785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
530698785
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3710327669
Short name T401
Test name
Test status
Simulation time 1070666776 ps
CPU time 6.84 seconds
Started May 19 01:43:56 PM PDT 24
Finished May 19 01:44:06 PM PDT 24
Peak memory 217912 kb
Host smart-fa9ca0eb-4929-4378-b43b-2dcd1dbdbe22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710327669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3710327669
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.271543842
Short name T74
Test name
Test status
Simulation time 79244419 ps
CPU time 2.97 seconds
Started May 19 01:44:03 PM PDT 24
Finished May 19 01:44:09 PM PDT 24
Peak memory 214136 kb
Host smart-29230f08-28ab-494b-8f04-bbe9e862906c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271543842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.271543842
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1848257791
Short name T536
Test name
Test status
Simulation time 1018762536 ps
CPU time 20.75 seconds
Started May 19 01:44:03 PM PDT 24
Finished May 19 01:44:27 PM PDT 24
Peak memory 250672 kb
Host smart-c8af036a-d07d-4f9a-b533-a0ae76ae4e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848257791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1848257791
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2749237003
Short name T798
Test name
Test status
Simulation time 56087178 ps
CPU time 3.43 seconds
Started May 19 01:43:56 PM PDT 24
Finished May 19 01:44:03 PM PDT 24
Peak memory 222128 kb
Host smart-929c9297-4903-4014-8afe-b540be4a498c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749237003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2749237003
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.1172713890
Short name T541
Test name
Test status
Simulation time 17092036302 ps
CPU time 158.65 seconds
Started May 19 01:44:01 PM PDT 24
Finished May 19 01:46:43 PM PDT 24
Peak memory 271808 kb
Host smart-05aec2e8-1fcf-48e9-9efd-289d8311f13b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172713890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.1172713890
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1311143586
Short name T230
Test name
Test status
Simulation time 21503977 ps
CPU time 1.01 seconds
Started May 19 01:44:03 PM PDT 24
Finished May 19 01:44:07 PM PDT 24
Peak memory 211428 kb
Host smart-ae7d6002-7ef1-4a53-a328-b493d7c0bfbd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311143586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1311143586
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.712312301
Short name T524
Test name
Test status
Simulation time 77521104 ps
CPU time 0.89 seconds
Started May 19 01:44:34 PM PDT 24
Finished May 19 01:44:36 PM PDT 24
Peak memory 209196 kb
Host smart-f4606bf3-c118-4e1a-a9ca-f6891099701b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712312301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.712312301
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3778752395
Short name T189
Test name
Test status
Simulation time 983680866 ps
CPU time 10.02 seconds
Started May 19 01:44:35 PM PDT 24
Finished May 19 01:44:46 PM PDT 24
Peak memory 217772 kb
Host smart-4e5e284e-e73f-4c84-b792-fc83405b26be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778752395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3778752395
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1482235405
Short name T26
Test name
Test status
Simulation time 2833819255 ps
CPU time 13.74 seconds
Started May 19 01:44:38 PM PDT 24
Finished May 19 01:44:55 PM PDT 24
Peak memory 209448 kb
Host smart-9b28321f-2571-4d20-abdf-a4221530a469
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482235405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1482235405
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2525180237
Short name T728
Test name
Test status
Simulation time 7860105089 ps
CPU time 105.47 seconds
Started May 19 01:44:39 PM PDT 24
Finished May 19 01:46:28 PM PDT 24
Peak memory 219368 kb
Host smart-c5366a69-4673-414e-89bd-2981f34b45d4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525180237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2525180237
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.4014748159
Short name T469
Test name
Test status
Simulation time 3944779864 ps
CPU time 8.83 seconds
Started May 19 01:44:39 PM PDT 24
Finished May 19 01:44:51 PM PDT 24
Peak memory 217796 kb
Host smart-0d0cb76f-2042-41d9-a5c2-6e84d14049a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014748159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.4014748159
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2734502223
Short name T503
Test name
Test status
Simulation time 2305965920 ps
CPU time 8.22 seconds
Started May 19 01:44:37 PM PDT 24
Finished May 19 01:44:48 PM PDT 24
Peak memory 213808 kb
Host smart-c94e97fa-81ae-4121-9ba0-5f03c5b261d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734502223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2734502223
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3247388529
Short name T243
Test name
Test status
Simulation time 667098817 ps
CPU time 27.21 seconds
Started May 19 01:44:42 PM PDT 24
Finished May 19 01:45:12 PM PDT 24
Peak memory 250704 kb
Host smart-f0424aaa-ad99-4b38-a91d-d72df1be475f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247388529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3247388529
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3570457208
Short name T332
Test name
Test status
Simulation time 875090561 ps
CPU time 10.88 seconds
Started May 19 01:44:38 PM PDT 24
Finished May 19 01:44:51 PM PDT 24
Peak memory 250712 kb
Host smart-3627ef3b-64ad-4bb3-8a83-862b19daf107
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570457208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3570457208
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.3835553370
Short name T421
Test name
Test status
Simulation time 104908258 ps
CPU time 1.77 seconds
Started May 19 01:44:38 PM PDT 24
Finished May 19 01:44:44 PM PDT 24
Peak memory 217884 kb
Host smart-d77e32f1-246f-424f-8e31-cea04cd21414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835553370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3835553370
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1212662221
Short name T859
Test name
Test status
Simulation time 2317176195 ps
CPU time 13.14 seconds
Started May 19 01:44:37 PM PDT 24
Finished May 19 01:44:52 PM PDT 24
Peak memory 226140 kb
Host smart-8d1ae50d-c330-4df7-9c8f-2aad5726cec2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212662221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1212662221
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3998528090
Short name T359
Test name
Test status
Simulation time 388710507 ps
CPU time 13.33 seconds
Started May 19 01:44:39 PM PDT 24
Finished May 19 01:44:56 PM PDT 24
Peak memory 217720 kb
Host smart-8d3ae3b5-db02-48a0-b57f-7954955a276c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998528090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3998528090
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.165717946
Short name T848
Test name
Test status
Simulation time 640136076 ps
CPU time 11.99 seconds
Started May 19 01:44:36 PM PDT 24
Finished May 19 01:44:50 PM PDT 24
Peak memory 217884 kb
Host smart-6a58429a-fb70-4420-9dc5-346ec0a6fd7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165717946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.165717946
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3824677047
Short name T408
Test name
Test status
Simulation time 721217077 ps
CPU time 10.37 seconds
Started May 19 01:44:38 PM PDT 24
Finished May 19 01:44:51 PM PDT 24
Peak memory 217932 kb
Host smart-d7968727-86b7-4aaa-a6ac-f7c3a83b945b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824677047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3824677047
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.4003492083
Short name T809
Test name
Test status
Simulation time 131867007 ps
CPU time 4.14 seconds
Started May 19 01:44:38 PM PDT 24
Finished May 19 01:44:46 PM PDT 24
Peak memory 217576 kb
Host smart-4a394cbc-6435-4bbd-b585-d6ae2d7e1c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003492083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.4003492083
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.429081492
Short name T452
Test name
Test status
Simulation time 337402645 ps
CPU time 26.41 seconds
Started May 19 01:44:40 PM PDT 24
Finished May 19 01:45:10 PM PDT 24
Peak memory 250772 kb
Host smart-aa187878-e614-4f25-997a-49eee10f7bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429081492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.429081492
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1669786658
Short name T213
Test name
Test status
Simulation time 66443119 ps
CPU time 7.94 seconds
Started May 19 01:44:36 PM PDT 24
Finished May 19 01:44:46 PM PDT 24
Peak memory 250724 kb
Host smart-9623a9bd-5223-4d59-812e-a44ef9d13674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669786658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1669786658
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1082091987
Short name T136
Test name
Test status
Simulation time 33941517341 ps
CPU time 140.15 seconds
Started May 19 01:44:41 PM PDT 24
Finished May 19 01:47:04 PM PDT 24
Peak memory 225960 kb
Host smart-c4cdcfb8-5e25-4874-88b6-d7f5ea20fd5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082091987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1082091987
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.857976114
Short name T614
Test name
Test status
Simulation time 6924203665 ps
CPU time 178.12 seconds
Started May 19 01:44:40 PM PDT 24
Finished May 19 01:47:41 PM PDT 24
Peak memory 259120 kb
Host smart-392a5b7a-4660-419b-ba19-cdea7e41e66a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=857976114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.857976114
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3380817169
Short name T210
Test name
Test status
Simulation time 36251249 ps
CPU time 0.98 seconds
Started May 19 01:44:42 PM PDT 24
Finished May 19 01:44:46 PM PDT 24
Peak memory 211372 kb
Host smart-80a6961b-3664-45f0-a2dd-bd1845e4020d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380817169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3380817169
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3438818192
Short name T680
Test name
Test status
Simulation time 16689908 ps
CPU time 1.13 seconds
Started May 19 01:44:39 PM PDT 24
Finished May 19 01:44:44 PM PDT 24
Peak memory 209352 kb
Host smart-3fec40c0-db76-4727-a1ae-ba92142f3344
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438818192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3438818192
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2271842612
Short name T758
Test name
Test status
Simulation time 203991473 ps
CPU time 9.34 seconds
Started May 19 01:44:40 PM PDT 24
Finished May 19 01:44:53 PM PDT 24
Peak memory 217756 kb
Host smart-edc059c9-1007-4341-ae69-d0dcc13850ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271842612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2271842612
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1767978437
Short name T25
Test name
Test status
Simulation time 326816625 ps
CPU time 5.25 seconds
Started May 19 01:44:40 PM PDT 24
Finished May 19 01:44:49 PM PDT 24
Peak memory 209372 kb
Host smart-039971e2-018e-4fb1-a89a-54fe39371182
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767978437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1767978437
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.2364880000
Short name T204
Test name
Test status
Simulation time 31086736515 ps
CPU time 47.1 seconds
Started May 19 01:44:40 PM PDT 24
Finished May 19 01:45:30 PM PDT 24
Peak memory 218748 kb
Host smart-1f2078b4-8dfb-401c-a40d-4122742490f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364880000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.2364880000
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1811891488
Short name T677
Test name
Test status
Simulation time 1510344763 ps
CPU time 21.52 seconds
Started May 19 01:44:42 PM PDT 24
Finished May 19 01:45:06 PM PDT 24
Peak memory 217668 kb
Host smart-14a3cc9b-be96-4d53-9bc5-853bde18fe55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811891488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1811891488
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.4017369962
Short name T435
Test name
Test status
Simulation time 530540774 ps
CPU time 13.73 seconds
Started May 19 01:44:35 PM PDT 24
Finished May 19 01:44:50 PM PDT 24
Peak memory 213548 kb
Host smart-aa7b6448-4ee4-4cdf-88e2-6dc02c1267f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017369962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.4017369962
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.746415633
Short name T405
Test name
Test status
Simulation time 3164913261 ps
CPU time 37.84 seconds
Started May 19 01:44:38 PM PDT 24
Finished May 19 01:45:19 PM PDT 24
Peak memory 250832 kb
Host smart-d20ced4d-df4a-468f-8a71-4bf431e3643f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746415633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.746415633
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3818982060
Short name T857
Test name
Test status
Simulation time 850885370 ps
CPU time 14.6 seconds
Started May 19 01:44:36 PM PDT 24
Finished May 19 01:44:53 PM PDT 24
Peak memory 223832 kb
Host smart-08d3d071-97ad-41b0-97df-dd0ffaf52b68
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818982060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3818982060
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.2973630199
Short name T459
Test name
Test status
Simulation time 52240624 ps
CPU time 2.63 seconds
Started May 19 01:44:42 PM PDT 24
Finished May 19 01:44:47 PM PDT 24
Peak memory 217772 kb
Host smart-309be601-6121-48cd-b1c9-26194b4ad5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973630199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.2973630199
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.2581540987
Short name T365
Test name
Test status
Simulation time 3142289416 ps
CPU time 22.81 seconds
Started May 19 01:44:41 PM PDT 24
Finished May 19 01:45:07 PM PDT 24
Peak memory 219220 kb
Host smart-03365825-6e32-4755-9f30-55e395849742
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581540987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.2581540987
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.2433951684
Short name T237
Test name
Test status
Simulation time 717721361 ps
CPU time 12.24 seconds
Started May 19 01:44:43 PM PDT 24
Finished May 19 01:44:58 PM PDT 24
Peak memory 217784 kb
Host smart-ded8f112-b81c-4e80-9055-20c22b566be4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433951684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.2433951684
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.933154001
Short name T389
Test name
Test status
Simulation time 1808597144 ps
CPU time 15.55 seconds
Started May 19 01:44:48 PM PDT 24
Finished May 19 01:45:04 PM PDT 24
Peak memory 217764 kb
Host smart-9ae2a07d-9755-45a9-8b44-9b5edf942723
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933154001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.933154001
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.59291283
Short name T770
Test name
Test status
Simulation time 3332279383 ps
CPU time 14.6 seconds
Started May 19 01:44:40 PM PDT 24
Finished May 19 01:44:58 PM PDT 24
Peak memory 225984 kb
Host smart-5aea01e6-747a-4976-b48a-27c849212f1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59291283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.59291283
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3127543626
Short name T289
Test name
Test status
Simulation time 213583612 ps
CPU time 2.82 seconds
Started May 19 01:44:39 PM PDT 24
Finished May 19 01:44:45 PM PDT 24
Peak memory 217660 kb
Host smart-ade07672-09b0-4192-a5fe-87a19279c0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127543626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3127543626
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3987226230
Short name T182
Test name
Test status
Simulation time 4839187783 ps
CPU time 37.07 seconds
Started May 19 01:44:36 PM PDT 24
Finished May 19 01:45:15 PM PDT 24
Peak memory 250912 kb
Host smart-30370039-eb75-4e85-8b6f-b9d24156bdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987226230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3987226230
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1168310206
Short name T781
Test name
Test status
Simulation time 236943544 ps
CPU time 7.56 seconds
Started May 19 01:44:41 PM PDT 24
Finished May 19 01:44:51 PM PDT 24
Peak memory 250640 kb
Host smart-6636bb01-1ba7-4184-a7d1-ec5864094b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168310206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1168310206
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2964242665
Short name T850
Test name
Test status
Simulation time 2287395595 ps
CPU time 85.37 seconds
Started May 19 01:44:44 PM PDT 24
Finished May 19 01:46:11 PM PDT 24
Peak memory 254912 kb
Host smart-07d2a376-98f0-4c4a-9834-03510f5aa084
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964242665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2964242665
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.2944681902
Short name T700
Test name
Test status
Simulation time 22682090900 ps
CPU time 535.99 seconds
Started May 19 01:44:42 PM PDT 24
Finished May 19 01:53:41 PM PDT 24
Peak memory 438356 kb
Host smart-00b5da3e-f11d-41b7-a66f-2d1d8b4bf1bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2944681902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.2944681902
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.4274255657
Short name T674
Test name
Test status
Simulation time 39800479 ps
CPU time 0.86 seconds
Started May 19 01:44:36 PM PDT 24
Finished May 19 01:44:39 PM PDT 24
Peak memory 211680 kb
Host smart-02311dcd-6c53-4d6a-8533-0f6eef71fe8f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274255657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.4274255657
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1340190183
Short name T27
Test name
Test status
Simulation time 39561880 ps
CPU time 0.82 seconds
Started May 19 01:44:46 PM PDT 24
Finished May 19 01:44:48 PM PDT 24
Peak memory 209224 kb
Host smart-f9b092e5-51d4-43e6-81a7-13cd93daad7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340190183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1340190183
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.4207854020
Short name T257
Test name
Test status
Simulation time 1116321941 ps
CPU time 16.43 seconds
Started May 19 01:44:47 PM PDT 24
Finished May 19 01:45:04 PM PDT 24
Peak memory 217764 kb
Host smart-0e0be0f7-c096-4357-bdc7-07cd350f1545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207854020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.4207854020
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.431360709
Short name T415
Test name
Test status
Simulation time 1177961511 ps
CPU time 3.85 seconds
Started May 19 01:44:44 PM PDT 24
Finished May 19 01:44:50 PM PDT 24
Peak memory 216800 kb
Host smart-8c358bd3-e03b-4b6a-8803-8a1a1ef886c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431360709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.431360709
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1301369106
Short name T220
Test name
Test status
Simulation time 2106498810 ps
CPU time 35.56 seconds
Started May 19 01:44:48 PM PDT 24
Finished May 19 01:45:25 PM PDT 24
Peak memory 217672 kb
Host smart-32ebc688-2aab-40f2-a610-e76e5db073b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301369106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1301369106
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1806603988
Short name T580
Test name
Test status
Simulation time 199204654 ps
CPU time 7.22 seconds
Started May 19 01:44:48 PM PDT 24
Finished May 19 01:44:56 PM PDT 24
Peak memory 217680 kb
Host smart-e6acf24d-8498-4313-82ec-d26cbb70df78
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806603988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1806603988
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3198460721
Short name T235
Test name
Test status
Simulation time 4291305269 ps
CPU time 7.57 seconds
Started May 19 01:44:41 PM PDT 24
Finished May 19 01:44:52 PM PDT 24
Peak memory 213668 kb
Host smart-68a3ed84-c1d3-4c4e-99e1-8addb2ace37e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198460721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3198460721
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1537278312
Short name T188
Test name
Test status
Simulation time 10134761704 ps
CPU time 92.49 seconds
Started May 19 01:44:45 PM PDT 24
Finished May 19 01:46:19 PM PDT 24
Peak memory 274084 kb
Host smart-0788baef-2422-42e7-ac46-381863c16635
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537278312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1537278312
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.482523046
Short name T413
Test name
Test status
Simulation time 19057615371 ps
CPU time 26.89 seconds
Started May 19 01:44:43 PM PDT 24
Finished May 19 01:45:12 PM PDT 24
Peak memory 224632 kb
Host smart-bebcec29-682d-4dc1-97ce-0e45d523b6ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482523046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.482523046
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.2909215710
Short name T364
Test name
Test status
Simulation time 20586281 ps
CPU time 1.77 seconds
Started May 19 01:44:46 PM PDT 24
Finished May 19 01:44:49 PM PDT 24
Peak memory 217852 kb
Host smart-44a9df9e-c868-4bca-90a9-1fdcb8ac2f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909215710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.2909215710
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2350577403
Short name T422
Test name
Test status
Simulation time 1117540607 ps
CPU time 12.59 seconds
Started May 19 01:44:43 PM PDT 24
Finished May 19 01:44:58 PM PDT 24
Peak memory 225912 kb
Host smart-1f60407c-8160-4f17-876c-d267c9128b88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350577403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2350577403
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.837961899
Short name T307
Test name
Test status
Simulation time 2328629861 ps
CPU time 15.05 seconds
Started May 19 01:44:44 PM PDT 24
Finished May 19 01:45:01 PM PDT 24
Peak memory 217820 kb
Host smart-45a63fce-f127-42ab-8c50-4e1481a5f11a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837961899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.837961899
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.57382090
Short name T528
Test name
Test status
Simulation time 986148435 ps
CPU time 7.16 seconds
Started May 19 01:44:43 PM PDT 24
Finished May 19 01:44:52 PM PDT 24
Peak memory 217728 kb
Host smart-c2565710-55c5-4520-9618-36acbfd05792
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57382090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.57382090
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2318997313
Short name T357
Test name
Test status
Simulation time 1691535442 ps
CPU time 10.64 seconds
Started May 19 01:44:42 PM PDT 24
Finished May 19 01:44:55 PM PDT 24
Peak memory 217812 kb
Host smart-8762a417-8412-4367-93ec-1e89c3f7da00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318997313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2318997313
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2355329726
Short name T267
Test name
Test status
Simulation time 481478429 ps
CPU time 3.07 seconds
Started May 19 01:44:39 PM PDT 24
Finished May 19 01:44:45 PM PDT 24
Peak memory 217580 kb
Host smart-c274e61c-4d21-467c-9bfc-77b93aca62fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355329726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2355329726
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.789535374
Short name T461
Test name
Test status
Simulation time 497526063 ps
CPU time 30.25 seconds
Started May 19 01:44:46 PM PDT 24
Finished May 19 01:45:18 PM PDT 24
Peak memory 250776 kb
Host smart-6ebf6d94-ad4f-4d2d-b975-1d8a45d0b894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789535374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.789535374
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.811418738
Short name T853
Test name
Test status
Simulation time 57056802 ps
CPU time 6.55 seconds
Started May 19 01:44:49 PM PDT 24
Finished May 19 01:44:56 PM PDT 24
Peak memory 250188 kb
Host smart-39f4adb7-7876-449e-9c09-d1fb73fe033e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811418738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.811418738
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1370645877
Short name T819
Test name
Test status
Simulation time 2754942606 ps
CPU time 113.49 seconds
Started May 19 01:44:51 PM PDT 24
Finished May 19 01:46:46 PM PDT 24
Peak memory 283544 kb
Host smart-a79410b0-adc8-4c64-b418-12f174227bf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370645877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1370645877
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3829037822
Short name T406
Test name
Test status
Simulation time 46680703 ps
CPU time 0.97 seconds
Started May 19 01:44:40 PM PDT 24
Finished May 19 01:44:44 PM PDT 24
Peak memory 211412 kb
Host smart-6e447e6c-a251-42ef-8fb3-89faf3abd9e0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829037822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3829037822
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.3378890537
Short name T838
Test name
Test status
Simulation time 18931529 ps
CPU time 0.79 seconds
Started May 19 01:44:48 PM PDT 24
Finished May 19 01:44:50 PM PDT 24
Peak memory 209300 kb
Host smart-840d4d09-ce1e-4c2f-94b2-efcb5dc56e0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378890537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.3378890537
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3716737989
Short name T321
Test name
Test status
Simulation time 4035768742 ps
CPU time 13.45 seconds
Started May 19 01:44:49 PM PDT 24
Finished May 19 01:45:04 PM PDT 24
Peak memory 218272 kb
Host smart-a9e07c6b-71ce-4e1e-95df-41a3f1d858b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716737989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3716737989
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2071042820
Short name T59
Test name
Test status
Simulation time 526824810 ps
CPU time 4.14 seconds
Started May 19 01:44:47 PM PDT 24
Finished May 19 01:44:52 PM PDT 24
Peak memory 209368 kb
Host smart-dde7e725-667b-451e-8904-f561ccf9417d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071042820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2071042820
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3689309798
Short name T4
Test name
Test status
Simulation time 9061905704 ps
CPU time 117.59 seconds
Started May 19 01:44:43 PM PDT 24
Finished May 19 01:46:43 PM PDT 24
Peak memory 219648 kb
Host smart-ea07301f-49da-4ad1-8375-b4c2cfc32552
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689309798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3689309798
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3474138620
Short name T511
Test name
Test status
Simulation time 696063049 ps
CPU time 5.31 seconds
Started May 19 01:44:45 PM PDT 24
Finished May 19 01:44:51 PM PDT 24
Peak memory 213072 kb
Host smart-8484a50d-422a-4ada-8474-3dac6003796f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474138620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3474138620
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.727928164
Short name T532
Test name
Test status
Simulation time 1996057579 ps
CPU time 30.33 seconds
Started May 19 01:44:43 PM PDT 24
Finished May 19 01:45:16 PM PDT 24
Peak memory 250696 kb
Host smart-f9dadd75-3cc1-402f-833b-9238ce831024
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727928164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_state_failure.727928164
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.521503688
Short name T343
Test name
Test status
Simulation time 480010264 ps
CPU time 19.04 seconds
Started May 19 01:44:46 PM PDT 24
Finished May 19 01:45:06 PM PDT 24
Peak memory 249228 kb
Host smart-861f2a27-2e23-42e2-a49f-3150555e90d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521503688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.521503688
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.238363081
Short name T426
Test name
Test status
Simulation time 68313939 ps
CPU time 2.06 seconds
Started May 19 01:44:50 PM PDT 24
Finished May 19 01:44:53 PM PDT 24
Peak memory 217748 kb
Host smart-0f5b855d-c6a0-4b6e-9fab-81749eeba8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238363081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.238363081
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.2936563738
Short name T581
Test name
Test status
Simulation time 1119507067 ps
CPU time 13.66 seconds
Started May 19 01:44:44 PM PDT 24
Finished May 19 01:44:59 PM PDT 24
Peak memory 225920 kb
Host smart-eb9ed60a-8a1b-4816-9bda-0b1b139a50f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936563738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.2936563738
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2609218604
Short name T301
Test name
Test status
Simulation time 240516844 ps
CPU time 11.71 seconds
Started May 19 01:44:51 PM PDT 24
Finished May 19 01:45:04 PM PDT 24
Peak memory 225656 kb
Host smart-a721f11b-ca12-4e75-9f39-9203626da9c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609218604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2609218604
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1398075369
Short name T191
Test name
Test status
Simulation time 1434432559 ps
CPU time 8.24 seconds
Started May 19 01:44:49 PM PDT 24
Finished May 19 01:44:58 PM PDT 24
Peak memory 217760 kb
Host smart-72816091-2bdb-48a2-8a41-cb08d6c4417a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398075369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1398075369
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.2707238634
Short name T806
Test name
Test status
Simulation time 2338681781 ps
CPU time 15.19 seconds
Started May 19 01:44:51 PM PDT 24
Finished May 19 01:45:07 PM PDT 24
Peak memory 217988 kb
Host smart-8b658a0a-f5fb-4775-b46d-395ad54e5930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707238634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.2707238634
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1510231118
Short name T750
Test name
Test status
Simulation time 124014629 ps
CPU time 2.07 seconds
Started May 19 01:44:43 PM PDT 24
Finished May 19 01:44:47 PM PDT 24
Peak memory 217608 kb
Host smart-3f51c5e5-4fed-4b16-93b0-9f1d341a9469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510231118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1510231118
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.31752676
Short name T675
Test name
Test status
Simulation time 215727751 ps
CPU time 24.39 seconds
Started May 19 01:44:46 PM PDT 24
Finished May 19 01:45:11 PM PDT 24
Peak memory 250708 kb
Host smart-597f76c9-1261-4cab-b6e3-3e99dad0b38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31752676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.31752676
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.2469499046
Short name T545
Test name
Test status
Simulation time 141073118 ps
CPU time 3.21 seconds
Started May 19 01:44:47 PM PDT 24
Finished May 19 01:44:51 PM PDT 24
Peak memory 222096 kb
Host smart-0683d34a-40f8-4af9-8fdf-7d7e60acd202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469499046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.2469499046
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.4053774040
Short name T664
Test name
Test status
Simulation time 32301838140 ps
CPU time 193.08 seconds
Started May 19 01:44:48 PM PDT 24
Finished May 19 01:48:02 PM PDT 24
Peak memory 278404 kb
Host smart-bf93c58d-ed1c-4f6c-b810-bfa5683ae192
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053774040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.4053774040
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.478537081
Short name T625
Test name
Test status
Simulation time 34382602 ps
CPU time 0.83 seconds
Started May 19 01:44:43 PM PDT 24
Finished May 19 01:44:46 PM PDT 24
Peak memory 211376 kb
Host smart-c63adcea-590b-4282-8ca0-44e7ca7049a4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478537081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.478537081
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3839005448
Short name T591
Test name
Test status
Simulation time 16892359 ps
CPU time 0.88 seconds
Started May 19 01:44:51 PM PDT 24
Finished May 19 01:44:53 PM PDT 24
Peak memory 209352 kb
Host smart-a9bcae27-9566-4947-99c6-392818725d94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839005448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3839005448
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.288504599
Short name T443
Test name
Test status
Simulation time 667067769 ps
CPU time 9.51 seconds
Started May 19 01:44:53 PM PDT 24
Finished May 19 01:45:04 PM PDT 24
Peak memory 217788 kb
Host smart-fb5d9a76-ba20-440a-b466-8ea64f7536f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288504599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.288504599
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.4024012864
Short name T398
Test name
Test status
Simulation time 103806053 ps
CPU time 1.85 seconds
Started May 19 01:44:53 PM PDT 24
Finished May 19 01:44:56 PM PDT 24
Peak memory 216840 kb
Host smart-1bbd073a-a042-44ef-85fe-a22405980557
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024012864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.4024012864
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.374909362
Short name T814
Test name
Test status
Simulation time 2694980311 ps
CPU time 22.24 seconds
Started May 19 01:44:51 PM PDT 24
Finished May 19 01:45:14 PM PDT 24
Peak memory 217912 kb
Host smart-18635d4b-5425-4a0c-a992-87c78c53d6df
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374909362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.374909362
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.3713863564
Short name T294
Test name
Test status
Simulation time 75423571 ps
CPU time 2.12 seconds
Started May 19 01:44:51 PM PDT 24
Finished May 19 01:44:55 PM PDT 24
Peak memory 217760 kb
Host smart-d3556d4a-d0b9-4b1e-8704-c4637ee67c5d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713863564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.3713863564
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3242784833
Short name T533
Test name
Test status
Simulation time 2204069989 ps
CPU time 9.75 seconds
Started May 19 01:44:52 PM PDT 24
Finished May 19 01:45:02 PM PDT 24
Peak memory 213308 kb
Host smart-0049d3e0-1578-4f38-8fe2-1d8064cbf7af
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242784833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.3242784833
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1482626000
Short name T571
Test name
Test status
Simulation time 7673272029 ps
CPU time 44.84 seconds
Started May 19 01:44:48 PM PDT 24
Finished May 19 01:45:33 PM PDT 24
Peak memory 283588 kb
Host smart-05ee732e-38ef-459e-9a67-c67af7f300c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482626000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1482626000
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.2362842334
Short name T183
Test name
Test status
Simulation time 1220488206 ps
CPU time 18.78 seconds
Started May 19 01:44:50 PM PDT 24
Finished May 19 01:45:09 PM PDT 24
Peak memory 250620 kb
Host smart-741c7158-9666-4900-8576-c503dc55ebda
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362842334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.2362842334
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2956202659
Short name T304
Test name
Test status
Simulation time 138294011 ps
CPU time 1.97 seconds
Started May 19 01:44:51 PM PDT 24
Finished May 19 01:44:55 PM PDT 24
Peak memory 217760 kb
Host smart-52f43c58-c31a-4148-a737-a12d77ff2624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956202659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2956202659
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.782647129
Short name T668
Test name
Test status
Simulation time 250014698 ps
CPU time 8.77 seconds
Started May 19 01:44:50 PM PDT 24
Finished May 19 01:45:00 PM PDT 24
Peak memory 218000 kb
Host smart-3d5de7a1-02d0-434b-b26c-83f2ad35fe9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782647129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.782647129
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.2397990895
Short name T760
Test name
Test status
Simulation time 283099339 ps
CPU time 11.9 seconds
Started May 19 01:44:51 PM PDT 24
Finished May 19 01:45:04 PM PDT 24
Peak memory 217796 kb
Host smart-1190895b-b3ac-4551-a70c-56d01b64a5e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397990895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_d
igest.2397990895
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.4245676373
Short name T270
Test name
Test status
Simulation time 880134945 ps
CPU time 9.96 seconds
Started May 19 01:44:52 PM PDT 24
Finished May 19 01:45:03 PM PDT 24
Peak memory 217764 kb
Host smart-f27d5c81-9689-408f-871f-33fa335f1cec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245676373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
4245676373
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.565180459
Short name T43
Test name
Test status
Simulation time 1562059056 ps
CPU time 8.8 seconds
Started May 19 01:44:49 PM PDT 24
Finished May 19 01:44:59 PM PDT 24
Peak memory 217780 kb
Host smart-412177d1-abbf-437e-8870-f3ee2d8734c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565180459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.565180459
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.334294798
Short name T419
Test name
Test status
Simulation time 30598543 ps
CPU time 1.96 seconds
Started May 19 01:44:48 PM PDT 24
Finished May 19 01:44:51 PM PDT 24
Peak memory 217516 kb
Host smart-f9e0718a-bfc6-4854-aa2c-d8e52ca8e28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334294798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.334294798
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.1128146927
Short name T778
Test name
Test status
Simulation time 173429616 ps
CPU time 17.66 seconds
Started May 19 01:44:50 PM PDT 24
Finished May 19 01:45:08 PM PDT 24
Peak memory 250784 kb
Host smart-d895015b-2aca-4bdf-a624-2fc499e2104f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128146927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1128146927
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2159178447
Short name T427
Test name
Test status
Simulation time 97208754 ps
CPU time 8.91 seconds
Started May 19 01:44:51 PM PDT 24
Finished May 19 01:45:00 PM PDT 24
Peak memory 250760 kb
Host smart-1d806467-a3d9-4cd3-8f4e-daf18191d77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159178447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2159178447
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3520324143
Short name T432
Test name
Test status
Simulation time 2774509255 ps
CPU time 96.63 seconds
Started May 19 01:44:52 PM PDT 24
Finished May 19 01:46:30 PM PDT 24
Peak memory 267232 kb
Host smart-5927261f-71ef-497c-9a25-47722407cd2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520324143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3520324143
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.2615333514
Short name T138
Test name
Test status
Simulation time 17694288732 ps
CPU time 340.11 seconds
Started May 19 01:44:50 PM PDT 24
Finished May 19 01:50:31 PM PDT 24
Peak memory 265820 kb
Host smart-17616778-6415-452a-9d0c-8ff7d8bd16bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2615333514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.2615333514
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1775697674
Short name T645
Test name
Test status
Simulation time 13994512 ps
CPU time 0.92 seconds
Started May 19 01:44:51 PM PDT 24
Finished May 19 01:44:53 PM PDT 24
Peak memory 211356 kb
Host smart-f2ebbc59-af25-486d-b745-fded022e01cc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775697674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1775697674
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2491537472
Short name T831
Test name
Test status
Simulation time 82625891 ps
CPU time 1.16 seconds
Started May 19 01:44:55 PM PDT 24
Finished May 19 01:44:57 PM PDT 24
Peak memory 209340 kb
Host smart-ae5fd790-b3c3-4fcf-bc61-18c10930adc5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491537472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2491537472
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3814421408
Short name T236
Test name
Test status
Simulation time 1210122364 ps
CPU time 10.1 seconds
Started May 19 01:44:55 PM PDT 24
Finished May 19 01:45:06 PM PDT 24
Peak memory 217784 kb
Host smart-4efea1cd-009b-4d4c-9213-e36606c142f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814421408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3814421408
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.820600182
Short name T483
Test name
Test status
Simulation time 2354150984 ps
CPU time 6.74 seconds
Started May 19 01:44:53 PM PDT 24
Finished May 19 01:45:00 PM PDT 24
Peak memory 209480 kb
Host smart-25f545c9-1872-4ff3-b2b5-86858844ed80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820600182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.820600182
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.2122857989
Short name T284
Test name
Test status
Simulation time 3914227667 ps
CPU time 57.65 seconds
Started May 19 01:44:54 PM PDT 24
Finished May 19 01:45:52 PM PDT 24
Peak memory 218404 kb
Host smart-29823791-4ec7-442b-b34a-e3b333519d42
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122857989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.2122857989
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.467572601
Short name T777
Test name
Test status
Simulation time 635468855 ps
CPU time 9.65 seconds
Started May 19 01:44:56 PM PDT 24
Finished May 19 01:45:06 PM PDT 24
Peak memory 217700 kb
Host smart-8163cc2d-13ec-4f39-98e0-b8e2622ee94c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467572601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.467572601
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.2094308972
Short name T721
Test name
Test status
Simulation time 140504785 ps
CPU time 4.39 seconds
Started May 19 01:44:54 PM PDT 24
Finished May 19 01:44:59 PM PDT 24
Peak memory 212976 kb
Host smart-153322ce-b244-4b4b-85b0-164f6bffdda0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094308972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.2094308972
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1892905742
Short name T830
Test name
Test status
Simulation time 15289607555 ps
CPU time 59.54 seconds
Started May 19 01:44:55 PM PDT 24
Finished May 19 01:45:55 PM PDT 24
Peak memory 252120 kb
Host smart-b14e4657-4806-478f-94ca-7073e73b9315
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892905742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1892905742
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3527690438
Short name T648
Test name
Test status
Simulation time 2423809363 ps
CPU time 23.88 seconds
Started May 19 01:44:54 PM PDT 24
Finished May 19 01:45:19 PM PDT 24
Peak memory 250740 kb
Host smart-0082c87b-702c-4ba8-b990-d762665bef62
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527690438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.3527690438
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2165329228
Short name T184
Test name
Test status
Simulation time 66885270 ps
CPU time 1.95 seconds
Started May 19 01:44:54 PM PDT 24
Finished May 19 01:44:57 PM PDT 24
Peak memory 217756 kb
Host smart-a0a8d6ad-05fa-4c1d-8d6d-d4e01c2ba489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165329228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2165329228
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1039551036
Short name T385
Test name
Test status
Simulation time 666917437 ps
CPU time 14.39 seconds
Started May 19 01:44:53 PM PDT 24
Finished May 19 01:45:09 PM PDT 24
Peak memory 218892 kb
Host smart-0b3ee27c-466c-439d-8170-ee6cc54e3e3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039551036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1039551036
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.2514251533
Short name T598
Test name
Test status
Simulation time 354330407 ps
CPU time 10.27 seconds
Started May 19 01:44:57 PM PDT 24
Finished May 19 01:45:08 PM PDT 24
Peak memory 225872 kb
Host smart-8ae9ba89-a994-45d9-95b3-57c44b1f61d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514251533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.2514251533
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1997766980
Short name T561
Test name
Test status
Simulation time 775907957 ps
CPU time 13.53 seconds
Started May 19 01:44:53 PM PDT 24
Finished May 19 01:45:08 PM PDT 24
Peak memory 217824 kb
Host smart-188cfb68-a5a2-4546-b547-b6e9793a3d67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997766980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1997766980
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.4114777654
Short name T481
Test name
Test status
Simulation time 3844057413 ps
CPU time 8.22 seconds
Started May 19 01:44:55 PM PDT 24
Finished May 19 01:45:04 PM PDT 24
Peak memory 218020 kb
Host smart-cd7bece7-0e50-4286-aa54-dc3456502c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114777654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.4114777654
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1890041781
Short name T56
Test name
Test status
Simulation time 87605265 ps
CPU time 2.09 seconds
Started May 19 01:44:53 PM PDT 24
Finished May 19 01:44:56 PM PDT 24
Peak memory 217580 kb
Host smart-96139ab9-933d-460e-899e-ab0ee50cfcff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890041781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1890041781
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1145744095
Short name T344
Test name
Test status
Simulation time 372589194 ps
CPU time 17.35 seconds
Started May 19 01:44:57 PM PDT 24
Finished May 19 01:45:15 PM PDT 24
Peak memory 250784 kb
Host smart-17469082-ce0c-4fcb-aa9a-5b5b2360595e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145744095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1145744095
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1251683639
Short name T520
Test name
Test status
Simulation time 116688397 ps
CPU time 8.47 seconds
Started May 19 01:44:53 PM PDT 24
Finished May 19 01:45:02 PM PDT 24
Peak memory 250780 kb
Host smart-3cbaa47d-8475-4706-930d-e2f153784e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251683639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1251683639
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1547464492
Short name T225
Test name
Test status
Simulation time 36411015895 ps
CPU time 336.27 seconds
Started May 19 01:44:54 PM PDT 24
Finished May 19 01:50:32 PM PDT 24
Peak memory 496708 kb
Host smart-2b36f62b-d1da-4971-b930-cc050dd31b3e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547464492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1547464492
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.4155522799
Short name T550
Test name
Test status
Simulation time 12863375 ps
CPU time 0.85 seconds
Started May 19 01:44:53 PM PDT 24
Finished May 19 01:44:55 PM PDT 24
Peak memory 211664 kb
Host smart-4fbc8846-71f1-4101-8274-19c7c62e1436
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155522799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.4155522799
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2391211248
Short name T217
Test name
Test status
Simulation time 40910984 ps
CPU time 1.03 seconds
Started May 19 01:44:57 PM PDT 24
Finished May 19 01:44:58 PM PDT 24
Peak memory 209644 kb
Host smart-d3a040c3-16bb-44e3-8574-cd35a4d85c1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391211248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2391211248
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.284995097
Short name T186
Test name
Test status
Simulation time 629541068 ps
CPU time 12.11 seconds
Started May 19 01:44:59 PM PDT 24
Finished May 19 01:45:12 PM PDT 24
Peak memory 217768 kb
Host smart-9ef64e14-088f-4f04-a0a1-ca9fb86a206a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284995097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.284995097
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.524183288
Short name T651
Test name
Test status
Simulation time 5019753940 ps
CPU time 13.28 seconds
Started May 19 01:45:02 PM PDT 24
Finished May 19 01:45:15 PM PDT 24
Peak memory 209440 kb
Host smart-4fe5d49c-b383-49ec-ac3d-ae3444129712
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524183288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.524183288
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1372434658
Short name T523
Test name
Test status
Simulation time 47829168750 ps
CPU time 64.08 seconds
Started May 19 01:45:49 PM PDT 24
Finished May 19 01:46:55 PM PDT 24
Peak memory 219476 kb
Host smart-71cbe365-7692-4580-b63b-f067912ae718
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372434658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1372434658
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.2724710532
Short name T840
Test name
Test status
Simulation time 438506929 ps
CPU time 7.61 seconds
Started May 19 01:45:09 PM PDT 24
Finished May 19 01:45:18 PM PDT 24
Peak memory 217772 kb
Host smart-9dd5ba5d-b4f7-4f91-b515-f9bb3f6aa3e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724710532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.2724710532
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3473222329
Short name T667
Test name
Test status
Simulation time 191235107 ps
CPU time 3.84 seconds
Started May 19 01:45:01 PM PDT 24
Finished May 19 01:45:05 PM PDT 24
Peak memory 213196 kb
Host smart-d6db6c84-0ab5-464a-b1df-d853d79b666a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473222329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3473222329
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.928732038
Short name T316
Test name
Test status
Simulation time 5200087045 ps
CPU time 89.05 seconds
Started May 19 01:45:08 PM PDT 24
Finished May 19 01:46:38 PM PDT 24
Peak memory 277404 kb
Host smart-f6b7ea2c-4c5c-4556-9ccd-848e6fcf2ad2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928732038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_state_failure.928732038
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3304053038
Short name T266
Test name
Test status
Simulation time 2316941965 ps
CPU time 14.77 seconds
Started May 19 01:44:58 PM PDT 24
Finished May 19 01:45:14 PM PDT 24
Peak memory 250480 kb
Host smart-d101c8b8-ef46-431e-8767-3ddd9f504ef2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304053038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3304053038
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.206497218
Short name T233
Test name
Test status
Simulation time 246666425 ps
CPU time 1.98 seconds
Started May 19 01:44:55 PM PDT 24
Finished May 19 01:44:58 PM PDT 24
Peak memory 217716 kb
Host smart-d2ec4a3c-1c55-4479-a28f-2aadb4afe625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206497218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.206497218
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.90512985
Short name T752
Test name
Test status
Simulation time 849756960 ps
CPU time 13.7 seconds
Started May 19 01:44:59 PM PDT 24
Finished May 19 01:45:13 PM PDT 24
Peak memory 225880 kb
Host smart-314f9b88-acfe-4b51-8796-db9501527252
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90512985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.90512985
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.89912562
Short name T813
Test name
Test status
Simulation time 777670716 ps
CPU time 13.34 seconds
Started May 19 01:45:08 PM PDT 24
Finished May 19 01:45:23 PM PDT 24
Peak memory 217736 kb
Host smart-3408f964-d7a3-48f8-9e65-4540fbe09172
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89912562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_dig
est.89912562
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.2776899134
Short name T201
Test name
Test status
Simulation time 5081544584 ps
CPU time 12.95 seconds
Started May 19 01:45:09 PM PDT 24
Finished May 19 01:45:23 PM PDT 24
Peak memory 217912 kb
Host smart-2a011615-df57-457e-8787-7319d5a8b57a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776899134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
2776899134
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.4208775566
Short name T596
Test name
Test status
Simulation time 2663707837 ps
CPU time 13.38 seconds
Started May 19 01:45:00 PM PDT 24
Finished May 19 01:45:14 PM PDT 24
Peak memory 217948 kb
Host smart-999c4101-6f8e-4941-8dc8-1503d107eb6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208775566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.4208775566
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1642086151
Short name T570
Test name
Test status
Simulation time 56583895 ps
CPU time 1.88 seconds
Started May 19 01:44:54 PM PDT 24
Finished May 19 01:44:57 PM PDT 24
Peak memory 217576 kb
Host smart-a3e8f098-152f-49e9-a913-9d97db5ce36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642086151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1642086151
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2408792603
Short name T240
Test name
Test status
Simulation time 836489166 ps
CPU time 22 seconds
Started May 19 01:44:53 PM PDT 24
Finished May 19 01:45:16 PM PDT 24
Peak memory 250780 kb
Host smart-b8902f9d-bd98-4ae9-ab61-55388561f52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408792603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2408792603
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.1011803969
Short name T341
Test name
Test status
Simulation time 76008194 ps
CPU time 7.7 seconds
Started May 19 01:44:53 PM PDT 24
Finished May 19 01:45:01 PM PDT 24
Peak memory 250748 kb
Host smart-e1d69e5f-3c9d-4305-863f-aacf7e184c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011803969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.1011803969
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.618788379
Short name T774
Test name
Test status
Simulation time 9291470615 ps
CPU time 60.77 seconds
Started May 19 01:44:57 PM PDT 24
Finished May 19 01:45:59 PM PDT 24
Peak memory 228120 kb
Host smart-908fe623-e230-4b58-a873-96f6110d76dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618788379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.618788379
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.792319813
Short name T126
Test name
Test status
Simulation time 123355490054 ps
CPU time 1070.4 seconds
Started May 19 01:45:09 PM PDT 24
Finished May 19 02:03:01 PM PDT 24
Peak memory 371316 kb
Host smart-db5af963-bc47-4464-a30d-6973660875b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=792319813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.792319813
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1772138166
Short name T600
Test name
Test status
Simulation time 48986497 ps
CPU time 0.84 seconds
Started May 19 01:44:53 PM PDT 24
Finished May 19 01:44:55 PM PDT 24
Peak memory 207772 kb
Host smart-44c7347c-eafe-4193-a577-d4595ef49db4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772138166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1772138166
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.4074548736
Short name T424
Test name
Test status
Simulation time 19272216 ps
CPU time 1.15 seconds
Started May 19 01:45:05 PM PDT 24
Finished May 19 01:45:07 PM PDT 24
Peak memory 209336 kb
Host smart-d9cf7d87-e580-4c47-a089-d6ede4a81003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074548736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.4074548736
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.66339130
Short name T602
Test name
Test status
Simulation time 4283976179 ps
CPU time 12.67 seconds
Started May 19 01:44:58 PM PDT 24
Finished May 19 01:45:12 PM PDT 24
Peak memory 218852 kb
Host smart-471e038d-a1fa-409d-936b-ea340d1da351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66339130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.66339130
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3044764003
Short name T20
Test name
Test status
Simulation time 799900013 ps
CPU time 4.17 seconds
Started May 19 01:45:04 PM PDT 24
Finished May 19 01:45:09 PM PDT 24
Peak memory 209340 kb
Host smart-442ba23b-98f2-4095-9191-dc8f6b1a26ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044764003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3044764003
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3834783153
Short name T339
Test name
Test status
Simulation time 1904755814 ps
CPU time 33.66 seconds
Started May 19 01:45:05 PM PDT 24
Finished May 19 01:45:40 PM PDT 24
Peak memory 217772 kb
Host smart-463b7383-e02a-44be-86af-90abc1f22524
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834783153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3834783153
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3572079288
Short name T348
Test name
Test status
Simulation time 146452108 ps
CPU time 3.21 seconds
Started May 19 01:45:04 PM PDT 24
Finished May 19 01:45:08 PM PDT 24
Peak memory 217772 kb
Host smart-aaaccad2-f302-4f72-b7ec-a6ae907a452e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572079288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3572079288
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2756017182
Short name T309
Test name
Test status
Simulation time 186433682 ps
CPU time 2.31 seconds
Started May 19 01:45:08 PM PDT 24
Finished May 19 01:45:12 PM PDT 24
Peak memory 212640 kb
Host smart-8fb5edc4-8cdd-40f8-824d-03ba207f8dcc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756017182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.2756017182
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2623348118
Short name T144
Test name
Test status
Simulation time 5258432961 ps
CPU time 82.43 seconds
Started May 19 01:45:04 PM PDT 24
Finished May 19 01:46:28 PM PDT 24
Peak memory 276424 kb
Host smart-7db88691-cdd3-421f-bab1-572234953f9b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623348118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2623348118
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.466642894
Short name T88
Test name
Test status
Simulation time 6289686290 ps
CPU time 13.4 seconds
Started May 19 01:45:02 PM PDT 24
Finished May 19 01:45:16 PM PDT 24
Peak memory 250812 kb
Host smart-3cbc78cb-fdbe-411f-82c1-6d5c33ff4e93
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466642894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.466642894
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.4086320473
Short name T345
Test name
Test status
Simulation time 38524514 ps
CPU time 1.91 seconds
Started May 19 01:45:08 PM PDT 24
Finished May 19 01:45:11 PM PDT 24
Peak memory 217736 kb
Host smart-84cb62d1-296b-4da0-97de-a0baa570292f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086320473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.4086320473
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3488669889
Short name T733
Test name
Test status
Simulation time 230046931 ps
CPU time 12.41 seconds
Started May 19 01:45:05 PM PDT 24
Finished May 19 01:45:18 PM PDT 24
Peak memory 218020 kb
Host smart-7d45c729-66f7-40de-a6e4-ed377e1c8d61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488669889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3488669889
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.1509755887
Short name T356
Test name
Test status
Simulation time 504834816 ps
CPU time 10.84 seconds
Started May 19 01:45:04 PM PDT 24
Finished May 19 01:45:16 PM PDT 24
Peak memory 217800 kb
Host smart-61dc69a3-b8a8-46df-bbd8-42ef3810d8eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509755887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
1509755887
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.2943798052
Short name T620
Test name
Test status
Simulation time 232720218 ps
CPU time 3.9 seconds
Started May 19 01:45:08 PM PDT 24
Finished May 19 01:45:13 PM PDT 24
Peak memory 217840 kb
Host smart-f2e0d377-1ffd-4c6f-8537-23c10368c581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943798052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.2943798052
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2504757623
Short name T197
Test name
Test status
Simulation time 696183004 ps
CPU time 18.09 seconds
Started May 19 01:45:09 PM PDT 24
Finished May 19 01:45:29 PM PDT 24
Peak memory 250748 kb
Host smart-40aac0e2-860a-4ae0-8bf6-36f7134f3ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504757623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2504757623
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2193308847
Short name T538
Test name
Test status
Simulation time 164470528 ps
CPU time 8.04 seconds
Started May 19 01:44:59 PM PDT 24
Finished May 19 01:45:08 PM PDT 24
Peak memory 250344 kb
Host smart-2ac962ee-b37f-425e-8816-7ca5a6933375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193308847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2193308847
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.147775653
Short name T678
Test name
Test status
Simulation time 8590545890 ps
CPU time 256.91 seconds
Started May 19 01:45:05 PM PDT 24
Finished May 19 01:49:23 PM PDT 24
Peak memory 283620 kb
Host smart-f45aed35-f492-4ecc-8947-d2af1c2c2f30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147775653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.147775653
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.434756004
Short name T697
Test name
Test status
Simulation time 65736496 ps
CPU time 1 seconds
Started May 19 01:45:00 PM PDT 24
Finished May 19 01:45:02 PM PDT 24
Peak memory 212644 kb
Host smart-ba9ca610-a78a-432f-bba1-a20a26caea3f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434756004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.434756004
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2938979053
Short name T430
Test name
Test status
Simulation time 12409020 ps
CPU time 0.81 seconds
Started May 19 01:45:09 PM PDT 24
Finished May 19 01:45:12 PM PDT 24
Peak memory 209288 kb
Host smart-5b4b0089-e2af-465f-bfb9-09c51c175773
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938979053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2938979053
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.437717191
Short name T218
Test name
Test status
Simulation time 1611372084 ps
CPU time 9.75 seconds
Started May 19 01:45:04 PM PDT 24
Finished May 19 01:45:15 PM PDT 24
Peak memory 217792 kb
Host smart-e4d75f73-2326-4152-9e88-ae5a6388f571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437717191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.437717191
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3091642199
Short name T594
Test name
Test status
Simulation time 87515871 ps
CPU time 3.02 seconds
Started May 19 01:45:08 PM PDT 24
Finished May 19 01:45:13 PM PDT 24
Peak memory 209376 kb
Host smart-dc97b5e0-176f-40df-aaba-360678d6bd0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091642199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3091642199
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2384472558
Short name T228
Test name
Test status
Simulation time 5976161527 ps
CPU time 46.44 seconds
Started May 19 01:45:11 PM PDT 24
Finished May 19 01:45:58 PM PDT 24
Peak memory 218412 kb
Host smart-3f977e50-ae8b-4a15-a4cb-d6cd4a498543
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384472558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2384472558
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2719206759
Short name T203
Test name
Test status
Simulation time 2218067443 ps
CPU time 5.58 seconds
Started May 19 01:45:10 PM PDT 24
Finished May 19 01:45:17 PM PDT 24
Peak memory 218024 kb
Host smart-2b712f05-17c7-4cac-aa36-5f35658295d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719206759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2719206759
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3513854567
Short name T73
Test name
Test status
Simulation time 953683085 ps
CPU time 5.06 seconds
Started May 19 01:45:04 PM PDT 24
Finished May 19 01:45:11 PM PDT 24
Peak memory 213444 kb
Host smart-81afaad5-454f-4a9c-9af8-0763fb63787e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513854567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3513854567
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.1144493774
Short name T686
Test name
Test status
Simulation time 5576355921 ps
CPU time 32.02 seconds
Started May 19 01:45:04 PM PDT 24
Finished May 19 01:45:37 PM PDT 24
Peak memory 267188 kb
Host smart-4e076cdb-102d-448f-bfad-a6c74b1825c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144493774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.1144493774
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.1522812582
Short name T19
Test name
Test status
Simulation time 785320621 ps
CPU time 29.56 seconds
Started May 19 01:45:08 PM PDT 24
Finished May 19 01:45:38 PM PDT 24
Peak memory 250724 kb
Host smart-550fc561-faec-481a-8f53-c604f8b0fc76
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522812582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.1522812582
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.1412543630
Short name T414
Test name
Test status
Simulation time 384925638 ps
CPU time 2.81 seconds
Started May 19 01:45:03 PM PDT 24
Finished May 19 01:45:06 PM PDT 24
Peak memory 217852 kb
Host smart-3b396dd3-58d7-46f0-a43f-a1dc48d831b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412543630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1412543630
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1758968433
Short name T822
Test name
Test status
Simulation time 612349387 ps
CPU time 16.87 seconds
Started May 19 01:45:09 PM PDT 24
Finished May 19 01:45:28 PM PDT 24
Peak memory 225880 kb
Host smart-2ebc83f9-8430-49ff-b875-9b7766e5651d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758968433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1758968433
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3849049465
Short name T312
Test name
Test status
Simulation time 3593136484 ps
CPU time 10.84 seconds
Started May 19 01:45:10 PM PDT 24
Finished May 19 01:45:22 PM PDT 24
Peak memory 225964 kb
Host smart-eeea14ed-0cb6-46e3-971d-eb40f29db6c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849049465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3849049465
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1530090477
Short name T734
Test name
Test status
Simulation time 946996367 ps
CPU time 7.36 seconds
Started May 19 01:45:10 PM PDT 24
Finished May 19 01:45:18 PM PDT 24
Peak memory 217992 kb
Host smart-7d49076f-29a3-4a01-9a62-d3d283cf7265
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530090477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1530090477
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.984777002
Short name T823
Test name
Test status
Simulation time 831364002 ps
CPU time 5.6 seconds
Started May 19 01:45:02 PM PDT 24
Finished May 19 01:45:08 PM PDT 24
Peak memory 217860 kb
Host smart-c70e700d-319b-4e57-9820-ac169904fbe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984777002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.984777002
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1046368012
Short name T858
Test name
Test status
Simulation time 220833117 ps
CPU time 7.91 seconds
Started May 19 01:45:05 PM PDT 24
Finished May 19 01:45:14 PM PDT 24
Peak memory 217556 kb
Host smart-330912df-8542-4dae-9dfb-2e1203006aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046368012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1046368012
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.770296664
Short name T441
Test name
Test status
Simulation time 325769826 ps
CPU time 34.84 seconds
Started May 19 01:45:04 PM PDT 24
Finished May 19 01:45:40 PM PDT 24
Peak memory 250764 kb
Host smart-59b08c08-3f6e-49bd-8c9f-7e982f1bbf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770296664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.770296664
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.2696856770
Short name T833
Test name
Test status
Simulation time 463980275 ps
CPU time 8.14 seconds
Started May 19 01:45:05 PM PDT 24
Finished May 19 01:45:14 PM PDT 24
Peak memory 250696 kb
Host smart-562597af-8c72-4e35-b2f2-283423b8f1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696856770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.2696856770
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3637039083
Short name T509
Test name
Test status
Simulation time 45823352116 ps
CPU time 338.39 seconds
Started May 19 01:45:08 PM PDT 24
Finished May 19 01:50:48 PM PDT 24
Peak memory 283660 kb
Host smart-80651fa0-5d66-4af0-856e-bb1e33d8ce45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637039083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3637039083
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.4121237211
Short name T143
Test name
Test status
Simulation time 15256316 ps
CPU time 0.93 seconds
Started May 19 01:45:03 PM PDT 24
Finished May 19 01:45:04 PM PDT 24
Peak memory 211408 kb
Host smart-035c1a71-2de4-4d1c-873d-f9c73481e407
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121237211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.4121237211
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.2937141139
Short name T629
Test name
Test status
Simulation time 45023426 ps
CPU time 0.88 seconds
Started May 19 01:45:11 PM PDT 24
Finished May 19 01:45:13 PM PDT 24
Peak memory 209296 kb
Host smart-b2983bcd-728a-4d1e-89c7-f19b4d681b96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937141139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.2937141139
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.556091867
Short name T567
Test name
Test status
Simulation time 2266679955 ps
CPU time 12.58 seconds
Started May 19 01:45:10 PM PDT 24
Finished May 19 01:45:24 PM PDT 24
Peak memory 217828 kb
Host smart-e7f77cb9-8f02-4386-9063-b512c3a60429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556091867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.556091867
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3182260191
Short name T6
Test name
Test status
Simulation time 487505375 ps
CPU time 2.36 seconds
Started May 19 01:45:15 PM PDT 24
Finished May 19 01:45:18 PM PDT 24
Peak memory 216816 kb
Host smart-f63beb7f-c59b-473b-8ec5-15bf2972a220
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182260191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3182260191
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.387370944
Short name T634
Test name
Test status
Simulation time 9920844941 ps
CPU time 69.71 seconds
Started May 19 01:45:13 PM PDT 24
Finished May 19 01:46:23 PM PDT 24
Peak memory 218752 kb
Host smart-5ffaf496-a8a0-4e8f-81fb-ace4c23b97d7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387370944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.387370944
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1187940582
Short name T314
Test name
Test status
Simulation time 2251996942 ps
CPU time 16.66 seconds
Started May 19 01:45:12 PM PDT 24
Finished May 19 01:45:30 PM PDT 24
Peak memory 217828 kb
Host smart-def72065-a571-4489-8e1a-f559389c2ac7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187940582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1187940582
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.713707365
Short name T628
Test name
Test status
Simulation time 210559929 ps
CPU time 3.84 seconds
Started May 19 01:45:13 PM PDT 24
Finished May 19 01:45:18 PM PDT 24
Peak memory 213100 kb
Host smart-a977bfce-47ed-4f51-9885-b88993c73222
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713707365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke.
713707365
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1632468246
Short name T510
Test name
Test status
Simulation time 2888599600 ps
CPU time 49.02 seconds
Started May 19 01:45:13 PM PDT 24
Finished May 19 01:46:03 PM PDT 24
Peak memory 267232 kb
Host smart-ffbae34f-d9f4-4795-927f-b8c93cf856ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632468246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1632468246
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1336026662
Short name T466
Test name
Test status
Simulation time 465379295 ps
CPU time 9.13 seconds
Started May 19 01:45:15 PM PDT 24
Finished May 19 01:45:24 PM PDT 24
Peak memory 246244 kb
Host smart-a0f25df8-9379-410d-b880-378c4da677bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336026662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1336026662
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.2903656876
Short name T704
Test name
Test status
Simulation time 39329653 ps
CPU time 2.24 seconds
Started May 19 01:45:07 PM PDT 24
Finished May 19 01:45:09 PM PDT 24
Peak memory 217864 kb
Host smart-549844c8-b8cb-4a86-97e9-19abc2a80573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903656876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.2903656876
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.3106376603
Short name T249
Test name
Test status
Simulation time 650797919 ps
CPU time 18.67 seconds
Started May 19 01:45:13 PM PDT 24
Finished May 19 01:45:33 PM PDT 24
Peak memory 218720 kb
Host smart-d05c4914-d4e9-4095-8379-b528161a719a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106376603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.3106376603
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2294663487
Short name T393
Test name
Test status
Simulation time 780597753 ps
CPU time 12.87 seconds
Started May 19 01:45:13 PM PDT 24
Finished May 19 01:45:27 PM PDT 24
Peak memory 225840 kb
Host smart-871366e1-2534-4206-90a8-735b145f38af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294663487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2294663487
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.288354832
Short name T802
Test name
Test status
Simulation time 1005896979 ps
CPU time 12.9 seconds
Started May 19 01:45:14 PM PDT 24
Finished May 19 01:45:27 PM PDT 24
Peak memory 217768 kb
Host smart-0fc2a208-5ea2-4db5-ba4a-456d57c89dbb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288354832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.288354832
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.3833025399
Short name T525
Test name
Test status
Simulation time 516329591 ps
CPU time 9.99 seconds
Started May 19 01:45:15 PM PDT 24
Finished May 19 01:45:25 PM PDT 24
Peak memory 217844 kb
Host smart-a40c4caf-53a3-4713-88b2-13f9688b20ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833025399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.3833025399
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.1239436339
Short name T368
Test name
Test status
Simulation time 83058651 ps
CPU time 1.37 seconds
Started May 19 01:45:08 PM PDT 24
Finished May 19 01:45:10 PM PDT 24
Peak memory 213276 kb
Host smart-c26f7c14-bd51-427a-ae92-3053d0dadbaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239436339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.1239436339
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2622415390
Short name T282
Test name
Test status
Simulation time 1204879370 ps
CPU time 27.73 seconds
Started May 19 01:45:10 PM PDT 24
Finished May 19 01:45:39 PM PDT 24
Peak memory 250732 kb
Host smart-73f780fc-965a-46c3-bbf1-76820659d9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622415390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2622415390
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.4153680340
Short name T330
Test name
Test status
Simulation time 164732773 ps
CPU time 7.56 seconds
Started May 19 01:45:07 PM PDT 24
Finished May 19 01:45:15 PM PDT 24
Peak memory 250972 kb
Host smart-503611b5-52bd-403e-af8d-9c0169869240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153680340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.4153680340
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.2957215452
Short name T387
Test name
Test status
Simulation time 6396534211 ps
CPU time 250.38 seconds
Started May 19 01:45:15 PM PDT 24
Finished May 19 01:49:26 PM PDT 24
Peak memory 283408 kb
Host smart-c8d35a4f-2ef0-4b41-8d81-f308a06b5a1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957215452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.2957215452
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2424056669
Short name T718
Test name
Test status
Simulation time 30501054 ps
CPU time 0.71 seconds
Started May 19 01:45:08 PM PDT 24
Finished May 19 01:45:09 PM PDT 24
Peak memory 206704 kb
Host smart-dcf37a70-6bd7-490d-b8fa-b79bf8032397
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424056669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2424056669
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1359010514
Short name T470
Test name
Test status
Simulation time 26006586 ps
CPU time 0.99 seconds
Started May 19 01:44:06 PM PDT 24
Finished May 19 01:44:09 PM PDT 24
Peak memory 209280 kb
Host smart-6dd6809f-c325-46b8-b99f-174ad6d4820e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359010514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1359010514
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.517355911
Short name T566
Test name
Test status
Simulation time 670845089 ps
CPU time 13.36 seconds
Started May 19 01:44:06 PM PDT 24
Finished May 19 01:44:21 PM PDT 24
Peak memory 217792 kb
Host smart-ca5d0150-2088-401a-8f04-a4a0129d73b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517355911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.517355911
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.2742735021
Short name T800
Test name
Test status
Simulation time 160664239 ps
CPU time 4.5 seconds
Started May 19 01:44:07 PM PDT 24
Finished May 19 01:44:13 PM PDT 24
Peak memory 216740 kb
Host smart-92588585-ec8e-4bcd-a6a8-90c9f6931d7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742735021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.2742735021
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.3238479292
Short name T409
Test name
Test status
Simulation time 3274323755 ps
CPU time 25.32 seconds
Started May 19 01:44:01 PM PDT 24
Finished May 19 01:44:29 PM PDT 24
Peak memory 218756 kb
Host smart-1cc886af-3330-4db1-83af-a1a735ab05b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238479292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.3238479292
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1845914163
Short name T394
Test name
Test status
Simulation time 116438823 ps
CPU time 2.09 seconds
Started May 19 01:44:05 PM PDT 24
Finished May 19 01:44:10 PM PDT 24
Peak memory 216956 kb
Host smart-b32a4186-cd2d-49cd-b5f4-51030963e9c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845914163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
845914163
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1348538904
Short name T716
Test name
Test status
Simulation time 809377115 ps
CPU time 12.42 seconds
Started May 19 01:44:02 PM PDT 24
Finished May 19 01:44:17 PM PDT 24
Peak memory 217788 kb
Host smart-5db17d5b-a799-435d-8477-07bf502d8380
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348538904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.1348538904
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.331177173
Short name T72
Test name
Test status
Simulation time 9887925114 ps
CPU time 19.64 seconds
Started May 19 01:44:05 PM PDT 24
Finished May 19 01:44:28 PM PDT 24
Peak memory 213868 kb
Host smart-f497b7a1-600a-4fdd-8efb-4c2487f5336c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331177173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.331177173
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1869782199
Short name T579
Test name
Test status
Simulation time 140521480 ps
CPU time 2.19 seconds
Started May 19 01:44:01 PM PDT 24
Finished May 19 01:44:07 PM PDT 24
Peak memory 212700 kb
Host smart-9afcfa33-11c0-4315-a27b-4db93773e180
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869782199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1869782199
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.3835869223
Short name T816
Test name
Test status
Simulation time 4611363390 ps
CPU time 86.72 seconds
Started May 19 01:44:01 PM PDT 24
Finished May 19 01:45:31 PM PDT 24
Peak memory 277452 kb
Host smart-2e6c4691-fd1d-41ca-a828-58ac2951b8cf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835869223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.3835869223
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2159628682
Short name T269
Test name
Test status
Simulation time 14203161527 ps
CPU time 20.13 seconds
Started May 19 01:44:02 PM PDT 24
Finished May 19 01:44:25 PM PDT 24
Peak memory 250356 kb
Host smart-4e50a776-7c32-4357-af51-528b08563e31
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159628682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2159628682
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2215392196
Short name T636
Test name
Test status
Simulation time 65502827 ps
CPU time 1.54 seconds
Started May 19 01:44:05 PM PDT 24
Finished May 19 01:44:09 PM PDT 24
Peak memory 217876 kb
Host smart-95f13957-3b35-4a5b-a901-386ed1bda932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215392196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2215392196
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1343274702
Short name T652
Test name
Test status
Simulation time 213161758 ps
CPU time 12.35 seconds
Started May 19 01:44:02 PM PDT 24
Finished May 19 01:44:18 PM PDT 24
Peak memory 217620 kb
Host smart-508b5adf-4d39-4e22-8f5b-dd73df9c250a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343274702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1343274702
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1745103990
Short name T80
Test name
Test status
Simulation time 457803403 ps
CPU time 24.5 seconds
Started May 19 01:44:11 PM PDT 24
Finished May 19 01:44:36 PM PDT 24
Peak memory 269096 kb
Host smart-ddfd956b-45d9-46d8-a092-6c219e571bb3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745103990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1745103990
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.735998560
Short name T248
Test name
Test status
Simulation time 537153468 ps
CPU time 8.03 seconds
Started May 19 01:44:05 PM PDT 24
Finished May 19 01:44:16 PM PDT 24
Peak memory 217784 kb
Host smart-d05fc565-c633-4415-8d3d-e302444ce4a7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735998560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.735998560
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1449925933
Short name T265
Test name
Test status
Simulation time 4642176606 ps
CPU time 8.26 seconds
Started May 19 01:44:06 PM PDT 24
Finished May 19 01:44:16 PM PDT 24
Peak memory 217624 kb
Host smart-81b67985-fad9-49f5-9869-3ef36ca999c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449925933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1449925933
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3936989911
Short name T454
Test name
Test status
Simulation time 398758703 ps
CPU time 6.76 seconds
Started May 19 01:44:07 PM PDT 24
Finished May 19 01:44:15 PM PDT 24
Peak memory 217804 kb
Host smart-fd9cc240-dfa6-48fd-a762-bc67673c385f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936989911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
936989911
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.940983095
Short name T574
Test name
Test status
Simulation time 515202447 ps
CPU time 13 seconds
Started May 19 01:44:01 PM PDT 24
Finished May 19 01:44:18 PM PDT 24
Peak memory 217828 kb
Host smart-45c95631-478f-44ef-af1e-5111ca470932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940983095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.940983095
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.198905868
Short name T325
Test name
Test status
Simulation time 58798801 ps
CPU time 2.82 seconds
Started May 19 01:44:05 PM PDT 24
Finished May 19 01:44:11 PM PDT 24
Peak memory 213692 kb
Host smart-58c3f0b3-3ba8-47ac-be2d-a49451711b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198905868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.198905868
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.274423860
Short name T766
Test name
Test status
Simulation time 1224404217 ps
CPU time 26.69 seconds
Started May 19 01:44:05 PM PDT 24
Finished May 19 01:44:35 PM PDT 24
Peak memory 250716 kb
Host smart-ea903937-3378-4e5f-8e40-5b60b961b8ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274423860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.274423860
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.248321249
Short name T722
Test name
Test status
Simulation time 341294922 ps
CPU time 3.93 seconds
Started May 19 01:44:02 PM PDT 24
Finished May 19 01:44:10 PM PDT 24
Peak memory 222588 kb
Host smart-1acf6d6a-b457-4c62-98f7-bed17415f3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248321249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.248321249
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2890413381
Short name T231
Test name
Test status
Simulation time 5262142370 ps
CPU time 102.08 seconds
Started May 19 01:44:09 PM PDT 24
Finished May 19 01:45:52 PM PDT 24
Peak memory 275472 kb
Host smart-74ae2051-6fe8-4ae0-8987-8e822c226fde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890413381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2890413381
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1927712259
Short name T775
Test name
Test status
Simulation time 38373313 ps
CPU time 0.81 seconds
Started May 19 01:44:01 PM PDT 24
Finished May 19 01:44:05 PM PDT 24
Peak memory 211488 kb
Host smart-5a26a769-a0c9-4b53-8531-8d43d1ef9e36
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927712259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1927712259
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3366262216
Short name T794
Test name
Test status
Simulation time 25394517 ps
CPU time 1.03 seconds
Started May 19 01:45:20 PM PDT 24
Finished May 19 01:45:22 PM PDT 24
Peak memory 209292 kb
Host smart-f73da74a-7ea1-4334-9330-1baafeeaf1d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366262216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3366262216
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.2691806307
Short name T635
Test name
Test status
Simulation time 208363700 ps
CPU time 8.44 seconds
Started May 19 01:45:19 PM PDT 24
Finished May 19 01:45:28 PM PDT 24
Peak memory 217748 kb
Host smart-e42eef05-26f3-4a5f-8ce0-1c520c144dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691806307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.2691806307
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.4017095924
Short name T658
Test name
Test status
Simulation time 1683840236 ps
CPU time 11.31 seconds
Started May 19 01:45:21 PM PDT 24
Finished May 19 01:45:34 PM PDT 24
Peak memory 209300 kb
Host smart-4eddfa9c-7954-435a-8c01-d52bdc9f027d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017095924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.4017095924
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.3858335350
Short name T355
Test name
Test status
Simulation time 21161376 ps
CPU time 1.58 seconds
Started May 19 01:45:16 PM PDT 24
Finished May 19 01:45:18 PM PDT 24
Peak memory 217792 kb
Host smart-5abb1716-7eb8-42ee-957e-f2a8138f1a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858335350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3858335350
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.1282744098
Short name T420
Test name
Test status
Simulation time 959078707 ps
CPU time 17.55 seconds
Started May 19 01:45:21 PM PDT 24
Finished May 19 01:45:39 PM PDT 24
Peak memory 225680 kb
Host smart-6d6ea6d3-fee8-4ae6-9531-938d731d4dca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282744098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.1282744098
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.44929346
Short name T222
Test name
Test status
Simulation time 1565758984 ps
CPU time 15.96 seconds
Started May 19 01:45:20 PM PDT 24
Finished May 19 01:45:36 PM PDT 24
Peak memory 217764 kb
Host smart-ae9c9499-4aee-4698-b842-458c85b10509
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44929346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_dig
est.44929346
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.4033711708
Short name T85
Test name
Test status
Simulation time 550759958 ps
CPU time 9.63 seconds
Started May 19 01:45:17 PM PDT 24
Finished May 19 01:45:27 PM PDT 24
Peak memory 217884 kb
Host smart-a3754499-117a-4d07-9c25-220e361fcb7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033711708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
4033711708
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.2870350619
Short name T672
Test name
Test status
Simulation time 468773539 ps
CPU time 15.16 seconds
Started May 19 01:45:14 PM PDT 24
Finished May 19 01:45:30 PM PDT 24
Peak memory 217848 kb
Host smart-10a72240-f312-4e47-be20-523c8892a63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870350619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.2870350619
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3677817947
Short name T761
Test name
Test status
Simulation time 58019672 ps
CPU time 2.27 seconds
Started May 19 01:45:12 PM PDT 24
Finished May 19 01:45:14 PM PDT 24
Peak memory 213828 kb
Host smart-77620f62-8168-418d-9154-9a55e3a41f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677817947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3677817947
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3406752088
Short name T717
Test name
Test status
Simulation time 1262016484 ps
CPU time 20.75 seconds
Started May 19 01:45:17 PM PDT 24
Finished May 19 01:45:39 PM PDT 24
Peak memory 250824 kb
Host smart-5d415a8e-dda2-4b12-9a9b-5996a6415a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406752088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3406752088
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.1300465047
Short name T759
Test name
Test status
Simulation time 94302482 ps
CPU time 3.04 seconds
Started May 19 01:45:18 PM PDT 24
Finished May 19 01:45:21 PM PDT 24
Peak memory 222076 kb
Host smart-d3d91121-ccb1-46ea-9f07-2899cbcf41ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300465047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.1300465047
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2486138203
Short name T748
Test name
Test status
Simulation time 4039690893 ps
CPU time 86.25 seconds
Started May 19 01:45:18 PM PDT 24
Finished May 19 01:46:45 PM PDT 24
Peak memory 267256 kb
Host smart-ae64cbc5-35d2-4bb2-8a62-f9ecf655b737
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486138203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2486138203
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1408680076
Short name T665
Test name
Test status
Simulation time 13907693 ps
CPU time 0.95 seconds
Started May 19 01:45:20 PM PDT 24
Finished May 19 01:45:21 PM PDT 24
Peak memory 207816 kb
Host smart-a293c7fd-66db-4e24-90ce-ceae25bed066
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408680076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1408680076
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1850378067
Short name T839
Test name
Test status
Simulation time 247923162 ps
CPU time 1.04 seconds
Started May 19 01:45:22 PM PDT 24
Finished May 19 01:45:24 PM PDT 24
Peak memory 209372 kb
Host smart-ac317625-db65-438f-a957-4f888f218bfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850378067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1850378067
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3900055922
Short name T843
Test name
Test status
Simulation time 690166936 ps
CPU time 17.05 seconds
Started May 19 01:45:19 PM PDT 24
Finished May 19 01:45:37 PM PDT 24
Peak memory 217760 kb
Host smart-46b64573-8f9b-4adb-b114-b08c3a7a03fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900055922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3900055922
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1615486470
Short name T308
Test name
Test status
Simulation time 974687085 ps
CPU time 6.42 seconds
Started May 19 01:45:17 PM PDT 24
Finished May 19 01:45:24 PM PDT 24
Peak memory 209376 kb
Host smart-2aafd44a-29d0-4aa8-b3a0-4e81a4874702
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615486470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1615486470
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2270208065
Short name T1
Test name
Test status
Simulation time 63331853 ps
CPU time 2.68 seconds
Started May 19 01:45:17 PM PDT 24
Finished May 19 01:45:20 PM PDT 24
Peak memory 217804 kb
Host smart-fe418625-ada3-490c-aa61-97cb32ead282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270208065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2270208065
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2468765247
Short name T841
Test name
Test status
Simulation time 224070061 ps
CPU time 10 seconds
Started May 19 01:45:21 PM PDT 24
Finished May 19 01:45:32 PM PDT 24
Peak memory 225896 kb
Host smart-3b428edb-6fc4-47b4-b7d9-59e26fbe470e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468765247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2468765247
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.236536577
Short name T501
Test name
Test status
Simulation time 274458011 ps
CPU time 12.02 seconds
Started May 19 01:45:21 PM PDT 24
Finished May 19 01:45:34 PM PDT 24
Peak memory 217716 kb
Host smart-6c5ce29a-465d-4e47-8c4e-7f5367135f6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236536577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_di
gest.236536577
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3499146701
Short name T505
Test name
Test status
Simulation time 199791808 ps
CPU time 7.92 seconds
Started May 19 01:45:18 PM PDT 24
Finished May 19 01:45:26 PM PDT 24
Peak memory 217772 kb
Host smart-e1e07288-11b5-4e69-8c70-3b5ed9c68cf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499146701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3499146701
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.919478572
Short name T179
Test name
Test status
Simulation time 384329755 ps
CPU time 9.85 seconds
Started May 19 01:45:18 PM PDT 24
Finished May 19 01:45:29 PM PDT 24
Peak memory 217840 kb
Host smart-7d2f450d-9383-4953-a8ca-18b4b960c144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919478572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.919478572
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1351436783
Short name T76
Test name
Test status
Simulation time 20537217 ps
CPU time 1.39 seconds
Started May 19 01:45:20 PM PDT 24
Finished May 19 01:45:22 PM PDT 24
Peak memory 213172 kb
Host smart-031df5a7-1770-42ee-9d45-0a4389e2e991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351436783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1351436783
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2455986614
Short name T720
Test name
Test status
Simulation time 1289487882 ps
CPU time 26.71 seconds
Started May 19 01:45:21 PM PDT 24
Finished May 19 01:45:49 PM PDT 24
Peak memory 250720 kb
Host smart-a6e325ee-4442-45dc-90aa-6f132292bc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455986614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2455986614
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2667849648
Short name T860
Test name
Test status
Simulation time 303337429 ps
CPU time 6.79 seconds
Started May 19 01:45:22 PM PDT 24
Finished May 19 01:45:29 PM PDT 24
Peak memory 246600 kb
Host smart-5a2df79d-96f4-40a6-9e88-636b5e76cb4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667849648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2667849648
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3528999193
Short name T37
Test name
Test status
Simulation time 4547434804 ps
CPU time 147.94 seconds
Started May 19 01:45:21 PM PDT 24
Finished May 19 01:47:50 PM PDT 24
Peak memory 220940 kb
Host smart-12bbf661-296f-4b8c-a4f5-9151f072d9f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528999193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3528999193
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1689083196
Short name T436
Test name
Test status
Simulation time 48190482 ps
CPU time 0.92 seconds
Started May 19 01:45:19 PM PDT 24
Finished May 19 01:45:20 PM PDT 24
Peak memory 211388 kb
Host smart-52f27630-80d5-4ce0-8b5e-fe0489cfc339
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689083196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1689083196
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1305804080
Short name T65
Test name
Test status
Simulation time 39654251 ps
CPU time 0.95 seconds
Started May 19 01:45:24 PM PDT 24
Finished May 19 01:45:26 PM PDT 24
Peak memory 209360 kb
Host smart-2f92500b-d4fe-4dfd-b43e-2db54908cc30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305804080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1305804080
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3168518955
Short name T820
Test name
Test status
Simulation time 5883056723 ps
CPU time 17.14 seconds
Started May 19 01:45:24 PM PDT 24
Finished May 19 01:45:43 PM PDT 24
Peak memory 218296 kb
Host smart-ea535d31-1067-49b6-8875-e67c88faed72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168518955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3168518955
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3361413825
Short name T333
Test name
Test status
Simulation time 630015974 ps
CPU time 4.31 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:45:28 PM PDT 24
Peak memory 209360 kb
Host smart-aa0abde5-f7c6-43a0-88e2-9ad1bab338a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361413825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3361413825
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1136567245
Short name T268
Test name
Test status
Simulation time 50320993 ps
CPU time 2.32 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:45:27 PM PDT 24
Peak memory 217752 kb
Host smart-dee4952e-e15f-406f-a82b-37e21cb89e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136567245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1136567245
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.954145650
Short name T55
Test name
Test status
Simulation time 619226652 ps
CPU time 17.92 seconds
Started May 19 01:45:24 PM PDT 24
Finished May 19 01:45:44 PM PDT 24
Peak memory 225528 kb
Host smart-5f6d475f-e800-43c8-947b-6f63ee4e946b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954145650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.954145650
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.4138429221
Short name T871
Test name
Test status
Simulation time 2838450812 ps
CPU time 21.96 seconds
Started May 19 01:45:22 PM PDT 24
Finished May 19 01:45:44 PM PDT 24
Peak memory 217896 kb
Host smart-323e82e5-5523-43e0-a0aa-2fd5132b5f0a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138429221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.4138429221
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.7408892
Short name T663
Test name
Test status
Simulation time 534547299 ps
CPU time 7.85 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:45:32 PM PDT 24
Peak memory 217756 kb
Host smart-96fca120-94e6-43ed-a912-a7895332ec8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7408892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.7408892
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.4144746342
Short name T272
Test name
Test status
Simulation time 635064532 ps
CPU time 8.99 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:45:34 PM PDT 24
Peak memory 217828 kb
Host smart-0847aecc-1a94-4af6-b461-d9558af15bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144746342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.4144746342
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2881745766
Short name T273
Test name
Test status
Simulation time 150800096 ps
CPU time 2.66 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:45:27 PM PDT 24
Peak memory 214072 kb
Host smart-0cfbe54f-3078-46e1-a3b4-23928089eb9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881745766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2881745766
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3822574321
Short name T391
Test name
Test status
Simulation time 900077170 ps
CPU time 30.28 seconds
Started May 19 01:45:21 PM PDT 24
Finished May 19 01:45:52 PM PDT 24
Peak memory 250748 kb
Host smart-e53337f8-6ee4-42c9-b0e4-972ce048e233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822574321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3822574321
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3569306379
Short name T403
Test name
Test status
Simulation time 116091072 ps
CPU time 6.87 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:45:31 PM PDT 24
Peak memory 250344 kb
Host smart-b0559bfa-9288-4cdf-b160-3d00fd2f013e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569306379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3569306379
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3596157258
Short name T337
Test name
Test status
Simulation time 4933968222 ps
CPU time 56.24 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:46:21 PM PDT 24
Peak memory 265136 kb
Host smart-101940dd-d4b4-49fd-832a-7846e0179e58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596157258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3596157258
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1429280795
Short name T821
Test name
Test status
Simulation time 89252699 ps
CPU time 0.88 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:45:25 PM PDT 24
Peak memory 211452 kb
Host smart-8417d06f-4aa1-4889-85d9-06a88da371e1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429280795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.1429280795
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1179125379
Short name T773
Test name
Test status
Simulation time 25607662 ps
CPU time 0.84 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:45:25 PM PDT 24
Peak memory 209356 kb
Host smart-e410b3f4-8d17-410c-acd3-474b50b3bc72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179125379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1179125379
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3792610577
Short name T39
Test name
Test status
Simulation time 423761035 ps
CPU time 14.1 seconds
Started May 19 01:45:24 PM PDT 24
Finished May 19 01:45:40 PM PDT 24
Peak memory 217772 kb
Host smart-a3b72086-4bad-4b60-8b56-660f39118b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792610577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3792610577
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.124359637
Short name T542
Test name
Test status
Simulation time 29722434 ps
CPU time 1.48 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:45:26 PM PDT 24
Peak memory 209292 kb
Host smart-ff144598-c95a-41f4-844f-d4cc9e70ae9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124359637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.124359637
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3527341138
Short name T805
Test name
Test status
Simulation time 193226717 ps
CPU time 2.56 seconds
Started May 19 01:45:26 PM PDT 24
Finished May 19 01:45:29 PM PDT 24
Peak memory 217804 kb
Host smart-65f83b3e-6602-4821-a257-68fde13f5534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527341138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3527341138
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1146238541
Short name T36
Test name
Test status
Simulation time 311505856 ps
CPU time 13.71 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:45:38 PM PDT 24
Peak memory 225272 kb
Host smart-3ecb2ac8-f2b8-4982-a6cb-159edb77d039
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146238541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1146238541
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3289737355
Short name T555
Test name
Test status
Simulation time 695507618 ps
CPU time 12.54 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:45:38 PM PDT 24
Peak memory 217784 kb
Host smart-2324693d-27b1-4e26-8d2d-d2e9f3bf86bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289737355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3289737355
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.2548237620
Short name T238
Test name
Test status
Simulation time 4522652291 ps
CPU time 10.32 seconds
Started May 19 01:45:25 PM PDT 24
Finished May 19 01:45:36 PM PDT 24
Peak memory 217900 kb
Host smart-a1269e99-c3d4-4cb8-8067-b9e0cbd14ee7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548237620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
2548237620
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.3666747909
Short name T44
Test name
Test status
Simulation time 1242951316 ps
CPU time 8.46 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:45:32 PM PDT 24
Peak memory 217780 kb
Host smart-6f7194d2-e446-4580-b8c3-f41269ea343b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666747909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.3666747909
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1586444682
Short name T199
Test name
Test status
Simulation time 200866431 ps
CPU time 2.94 seconds
Started May 19 01:45:24 PM PDT 24
Finished May 19 01:45:28 PM PDT 24
Peak memory 214248 kb
Host smart-047e598f-6c90-4f1b-9083-d4df5d8eecf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586444682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1586444682
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.3277926371
Short name T793
Test name
Test status
Simulation time 251569510 ps
CPU time 28.7 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:45:54 PM PDT 24
Peak memory 250728 kb
Host smart-b8f542e9-107c-442e-b183-b43fc7aadf68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277926371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.3277926371
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.4115670215
Short name T732
Test name
Test status
Simulation time 229494735 ps
CPU time 8.88 seconds
Started May 19 01:45:21 PM PDT 24
Finished May 19 01:45:31 PM PDT 24
Peak memory 246476 kb
Host smart-b0a991de-041c-47a8-be0a-912b8a3174d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115670215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.4115670215
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.230631796
Short name T137
Test name
Test status
Simulation time 7890739085 ps
CPU time 245.31 seconds
Started May 19 01:45:25 PM PDT 24
Finished May 19 01:49:31 PM PDT 24
Peak memory 225972 kb
Host smart-a4214c63-31b8-4d7b-abb1-01ff7ceb120c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230631796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.230631796
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.3732991334
Short name T77
Test name
Test status
Simulation time 12100518782 ps
CPU time 231.53 seconds
Started May 19 01:45:24 PM PDT 24
Finished May 19 01:49:17 PM PDT 24
Peak memory 283704 kb
Host smart-b1a59787-aa2f-414f-a648-d0b0f74ce9fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3732991334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.3732991334
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1555139866
Short name T654
Test name
Test status
Simulation time 26831545 ps
CPU time 1.09 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:45:25 PM PDT 24
Peak memory 211524 kb
Host smart-052de2f2-11e1-414d-aab1-5c8b33d77862
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555139866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1555139866
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.336189139
Short name T767
Test name
Test status
Simulation time 14278844 ps
CPU time 0.84 seconds
Started May 19 01:45:27 PM PDT 24
Finished May 19 01:45:29 PM PDT 24
Peak memory 209308 kb
Host smart-7d53bce8-2432-4eac-bb16-667b7b4998f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336189139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.336189139
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1237280693
Short name T346
Test name
Test status
Simulation time 672934324 ps
CPU time 11.26 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:45:36 PM PDT 24
Peak memory 217772 kb
Host smart-8dd4c83f-06a2-4f0c-8a46-6fce883fdf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237280693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1237280693
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.247711195
Short name T521
Test name
Test status
Simulation time 336184905 ps
CPU time 8.91 seconds
Started May 19 01:45:28 PM PDT 24
Finished May 19 01:45:38 PM PDT 24
Peak memory 216900 kb
Host smart-8cec59f4-df58-42d7-92e7-771f8f0135b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247711195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.247711195
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3225405198
Short name T739
Test name
Test status
Simulation time 58656075 ps
CPU time 2.38 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:45:27 PM PDT 24
Peak memory 218060 kb
Host smart-e8805f04-bc79-4041-b399-b8495c75aa2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225405198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3225405198
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2229557027
Short name T455
Test name
Test status
Simulation time 8015628131 ps
CPU time 23.73 seconds
Started May 19 01:45:26 PM PDT 24
Finished May 19 01:45:50 PM PDT 24
Peak memory 225980 kb
Host smart-1b3c106b-7db7-4d68-85b5-5246c505b80e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229557027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2229557027
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.2684924834
Short name T259
Test name
Test status
Simulation time 226031468 ps
CPU time 10.04 seconds
Started May 19 01:45:27 PM PDT 24
Finished May 19 01:45:37 PM PDT 24
Peak memory 217764 kb
Host smart-7fc49941-88a7-46d0-8e14-6499fa2dbb0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684924834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.2684924834
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2034658147
Short name T502
Test name
Test status
Simulation time 1346166831 ps
CPU time 13.31 seconds
Started May 19 01:45:27 PM PDT 24
Finished May 19 01:45:41 PM PDT 24
Peak memory 217780 kb
Host smart-13022a2d-66d3-4e9c-9212-94c13cbd9de4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034658147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2034658147
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3228016824
Short name T553
Test name
Test status
Simulation time 2360325755 ps
CPU time 12.62 seconds
Started May 19 01:45:38 PM PDT 24
Finished May 19 01:45:52 PM PDT 24
Peak memory 217928 kb
Host smart-a9e68bad-bfe8-42fa-a254-e33d4f85d8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228016824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3228016824
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.2743586780
Short name T63
Test name
Test status
Simulation time 635195873 ps
CPU time 7 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:45:32 PM PDT 24
Peak memory 214644 kb
Host smart-63dc3530-991a-4b9c-9712-94dcf9f1eaa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743586780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.2743586780
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.3209943385
Short name T499
Test name
Test status
Simulation time 827459976 ps
CPU time 21.91 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:45:47 PM PDT 24
Peak memory 250832 kb
Host smart-43162040-5ab1-42c6-bdf6-ce109b2a9bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209943385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.3209943385
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3671575356
Short name T313
Test name
Test status
Simulation time 378686228 ps
CPU time 3.54 seconds
Started May 19 01:45:25 PM PDT 24
Finished May 19 01:45:29 PM PDT 24
Peak memory 226140 kb
Host smart-fd36394f-22e7-48a5-aefc-407bdeee36ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671575356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3671575356
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2598738037
Short name T632
Test name
Test status
Simulation time 55671656 ps
CPU time 0.87 seconds
Started May 19 01:45:23 PM PDT 24
Finished May 19 01:45:26 PM PDT 24
Peak memory 207752 kb
Host smart-34f5ff03-adf0-49b5-82aa-85dd4adfa3fb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598738037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2598738037
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.202063904
Short name T633
Test name
Test status
Simulation time 24011459 ps
CPU time 1.01 seconds
Started May 19 01:45:38 PM PDT 24
Finished May 19 01:45:40 PM PDT 24
Peak memory 209316 kb
Host smart-ba57785b-b450-478a-a7e2-5984acf623a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202063904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.202063904
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3310716955
Short name T746
Test name
Test status
Simulation time 1630369127 ps
CPU time 17.68 seconds
Started May 19 01:45:28 PM PDT 24
Finished May 19 01:45:47 PM PDT 24
Peak memory 217776 kb
Host smart-631880d8-e08e-4177-a8fb-c2a0442aa8b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310716955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3310716955
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2936494602
Short name T146
Test name
Test status
Simulation time 1110061224 ps
CPU time 9.87 seconds
Started May 19 01:45:29 PM PDT 24
Finished May 19 01:45:40 PM PDT 24
Peak memory 209356 kb
Host smart-45dc3e85-cc63-4aca-bf65-0b9a65e4ce4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936494602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2936494602
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1540937078
Short name T604
Test name
Test status
Simulation time 87919708 ps
CPU time 2.49 seconds
Started May 19 01:45:31 PM PDT 24
Finished May 19 01:45:34 PM PDT 24
Peak memory 217368 kb
Host smart-832ccbfa-a426-4a02-919c-1026e532d89d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540937078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1540937078
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2970309884
Short name T440
Test name
Test status
Simulation time 595197403 ps
CPU time 13.78 seconds
Started May 19 01:45:40 PM PDT 24
Finished May 19 01:45:55 PM PDT 24
Peak memory 225692 kb
Host smart-656429b9-1a54-4ac8-aa34-1d92efa7c594
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970309884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2970309884
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2423461610
Short name T577
Test name
Test status
Simulation time 595182347 ps
CPU time 12.95 seconds
Started May 19 01:45:40 PM PDT 24
Finished May 19 01:45:54 PM PDT 24
Peak memory 217584 kb
Host smart-23ed70c6-68da-4bfb-8afb-9294f6ceb3dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423461610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2423461610
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.794576106
Short name T84
Test name
Test status
Simulation time 1016268772 ps
CPU time 7 seconds
Started May 19 01:45:28 PM PDT 24
Finished May 19 01:45:36 PM PDT 24
Peak memory 217708 kb
Host smart-04864eb5-2816-48b3-80b7-a6de3a8471a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794576106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.794576106
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.198584889
Short name T311
Test name
Test status
Simulation time 1490989967 ps
CPU time 9.81 seconds
Started May 19 01:45:29 PM PDT 24
Finished May 19 01:45:40 PM PDT 24
Peak memory 217804 kb
Host smart-fc68e3f7-41ed-491f-bb8e-8ef61aa84312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198584889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.198584889
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.1298021669
Short name T288
Test name
Test status
Simulation time 380755190 ps
CPU time 25.27 seconds
Started May 19 01:45:27 PM PDT 24
Finished May 19 01:45:53 PM PDT 24
Peak memory 250656 kb
Host smart-5cb84ce6-8877-4d8b-83df-ba275f1f3cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298021669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.1298021669
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.2137899092
Short name T263
Test name
Test status
Simulation time 104418724 ps
CPU time 2.76 seconds
Started May 19 01:45:29 PM PDT 24
Finished May 19 01:45:33 PM PDT 24
Peak memory 221980 kb
Host smart-19408aca-9fcc-4c29-ac2d-abd048400af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137899092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2137899092
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.226351738
Short name T696
Test name
Test status
Simulation time 83461239358 ps
CPU time 657.1 seconds
Started May 19 01:45:30 PM PDT 24
Finished May 19 01:56:28 PM PDT 24
Peak memory 283480 kb
Host smart-7234944f-d858-431e-a9a5-10694375dfac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226351738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.226351738
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2732931566
Short name T448
Test name
Test status
Simulation time 29573452 ps
CPU time 0.84 seconds
Started May 19 01:45:28 PM PDT 24
Finished May 19 01:45:30 PM PDT 24
Peak memory 211460 kb
Host smart-b64dc6ad-41b8-4f3f-aeaf-13e5af972940
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732931566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2732931566
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2472894499
Short name T258
Test name
Test status
Simulation time 19764919 ps
CPU time 0.93 seconds
Started May 19 01:45:35 PM PDT 24
Finished May 19 01:45:37 PM PDT 24
Peak memory 209312 kb
Host smart-289a5496-d839-4ab9-a37f-f3383fb388bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472894499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2472894499
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.603815851
Short name T710
Test name
Test status
Simulation time 1255178747 ps
CPU time 15.4 seconds
Started May 19 01:45:28 PM PDT 24
Finished May 19 01:45:45 PM PDT 24
Peak memory 217756 kb
Host smart-cbcfb298-c9ef-4e45-ae39-6106623c3a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603815851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.603815851
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3180809439
Short name T753
Test name
Test status
Simulation time 1617768520 ps
CPU time 11.47 seconds
Started May 19 01:45:31 PM PDT 24
Finished May 19 01:45:43 PM PDT 24
Peak memory 209380 kb
Host smart-0d289c97-5645-4558-b42f-3c19903d2736
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180809439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3180809439
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3002261609
Short name T779
Test name
Test status
Simulation time 30948078 ps
CPU time 1.87 seconds
Started May 19 01:45:29 PM PDT 24
Finished May 19 01:45:32 PM PDT 24
Peak memory 217836 kb
Host smart-89afc4ee-412b-4fcc-bed1-2b99f1e5c26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002261609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3002261609
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.326767728
Short name T254
Test name
Test status
Simulation time 892663161 ps
CPU time 12.14 seconds
Started May 19 01:45:30 PM PDT 24
Finished May 19 01:45:43 PM PDT 24
Peak memory 218692 kb
Host smart-401c4e82-fed2-4b11-8581-7c7b87fac880
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326767728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.326767728
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.3079971349
Short name T711
Test name
Test status
Simulation time 270436587 ps
CPU time 7.75 seconds
Started May 19 01:45:30 PM PDT 24
Finished May 19 01:45:39 PM PDT 24
Peak memory 217744 kb
Host smart-6d20a4f8-c324-4bd2-a7e2-e7203449f37c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079971349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.3079971349
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3925826180
Short name T790
Test name
Test status
Simulation time 1057661993 ps
CPU time 10.09 seconds
Started May 19 01:45:27 PM PDT 24
Finished May 19 01:45:38 PM PDT 24
Peak memory 217800 kb
Host smart-a8f49a66-7ffc-4791-874c-d9939d7c4bbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925826180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3925826180
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1647361262
Short name T687
Test name
Test status
Simulation time 207421350 ps
CPU time 8.32 seconds
Started May 19 01:45:35 PM PDT 24
Finished May 19 01:45:45 PM PDT 24
Peak memory 224348 kb
Host smart-10681ba7-24ba-4c4d-b3a1-98e50a81e645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647361262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1647361262
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.650821188
Short name T655
Test name
Test status
Simulation time 168493542 ps
CPU time 2.75 seconds
Started May 19 01:45:28 PM PDT 24
Finished May 19 01:45:32 PM PDT 24
Peak memory 217552 kb
Host smart-10a349f1-b263-48cf-ac9c-cfaebaf3c2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650821188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.650821188
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2542083137
Short name T639
Test name
Test status
Simulation time 266677820 ps
CPU time 25.99 seconds
Started May 19 01:45:28 PM PDT 24
Finished May 19 01:45:55 PM PDT 24
Peak memory 250780 kb
Host smart-faef17ad-ef0c-4792-af8d-f06839f3b492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542083137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2542083137
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.982742690
Short name T517
Test name
Test status
Simulation time 139205929 ps
CPU time 6.88 seconds
Started May 19 01:45:26 PM PDT 24
Finished May 19 01:45:34 PM PDT 24
Peak memory 250312 kb
Host smart-3313373c-1bf0-484a-98cf-c14cad7a9609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982742690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.982742690
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.3530644562
Short name T592
Test name
Test status
Simulation time 39022386642 ps
CPU time 220.79 seconds
Started May 19 01:45:28 PM PDT 24
Finished May 19 01:49:10 PM PDT 24
Peak memory 250880 kb
Host smart-aac217a5-cf79-40c4-ad4e-2fa3b0f72d6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530644562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.3530644562
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.3277706939
Short name T593
Test name
Test status
Simulation time 36992731 ps
CPU time 1.01 seconds
Started May 19 01:45:30 PM PDT 24
Finished May 19 01:45:32 PM PDT 24
Peak memory 212588 kb
Host smart-a48f74d5-f8c0-428b-abc0-e78c06da749d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277706939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.3277706939
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.3852649583
Short name T68
Test name
Test status
Simulation time 81242867 ps
CPU time 0.91 seconds
Started May 19 01:45:34 PM PDT 24
Finished May 19 01:45:37 PM PDT 24
Peak memory 209276 kb
Host smart-70bf659a-5a8c-45dc-b398-cbf0ba62469f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852649583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.3852649583
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3893674166
Short name T638
Test name
Test status
Simulation time 948946188 ps
CPU time 7.7 seconds
Started May 19 01:45:34 PM PDT 24
Finished May 19 01:45:43 PM PDT 24
Peak memory 217816 kb
Host smart-f3c2ab0b-d325-45ce-a9e2-a54fe621c09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893674166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3893674166
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.433315202
Short name T358
Test name
Test status
Simulation time 1523838375 ps
CPU time 8.37 seconds
Started May 19 01:45:35 PM PDT 24
Finished May 19 01:45:45 PM PDT 24
Peak memory 209392 kb
Host smart-f04b3cf4-535a-4c2f-86bf-87c672c0587f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433315202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.433315202
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1162387813
Short name T223
Test name
Test status
Simulation time 242492894 ps
CPU time 2.85 seconds
Started May 19 01:45:31 PM PDT 24
Finished May 19 01:45:35 PM PDT 24
Peak memory 217776 kb
Host smart-bd28ede8-9462-4216-8429-e6328705448b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162387813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1162387813
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.753094070
Short name T90
Test name
Test status
Simulation time 6310214983 ps
CPU time 13.04 seconds
Started May 19 01:45:31 PM PDT 24
Finished May 19 01:45:44 PM PDT 24
Peak memory 225996 kb
Host smart-67b8d4c5-8c7d-4b5a-8410-40c27458f753
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753094070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.753094070
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.1336701713
Short name T255
Test name
Test status
Simulation time 311609612 ps
CPU time 12.88 seconds
Started May 19 01:45:34 PM PDT 24
Finished May 19 01:45:48 PM PDT 24
Peak memory 225852 kb
Host smart-2608f260-0efd-4ede-acf0-18832b7da13d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336701713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.1336701713
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.989540683
Short name T862
Test name
Test status
Simulation time 1666889518 ps
CPU time 12.84 seconds
Started May 19 01:45:34 PM PDT 24
Finished May 19 01:45:48 PM PDT 24
Peak memory 217768 kb
Host smart-caf89a66-19ed-4db8-9a02-1740cd4f6d79
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989540683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.989540683
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3093872795
Short name T475
Test name
Test status
Simulation time 203292675 ps
CPU time 8.89 seconds
Started May 19 01:45:32 PM PDT 24
Finished May 19 01:45:41 PM PDT 24
Peak memory 217768 kb
Host smart-acc77a65-8c8e-45b6-9e39-fdfffbd8c838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093872795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3093872795
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3201437650
Short name T324
Test name
Test status
Simulation time 219433944 ps
CPU time 3.22 seconds
Started May 19 01:45:34 PM PDT 24
Finished May 19 01:45:39 PM PDT 24
Peak memory 214252 kb
Host smart-c9e45a3a-92e7-4f87-9337-208869834c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201437650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3201437650
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2760126622
Short name T256
Test name
Test status
Simulation time 194768728 ps
CPU time 21.01 seconds
Started May 19 01:45:30 PM PDT 24
Finished May 19 01:45:51 PM PDT 24
Peak memory 251012 kb
Host smart-d84c6da0-fe74-413c-a704-f060737d9d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760126622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2760126622
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1808880435
Short name T34
Test name
Test status
Simulation time 45225302 ps
CPU time 6.19 seconds
Started May 19 01:45:39 PM PDT 24
Finished May 19 01:45:46 PM PDT 24
Peak memory 250344 kb
Host smart-99178eb2-f41e-4c41-b978-794b196882b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808880435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1808880435
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1575156047
Short name T302
Test name
Test status
Simulation time 5116046672 ps
CPU time 102.72 seconds
Started May 19 01:45:33 PM PDT 24
Finished May 19 01:47:16 PM PDT 24
Peak memory 269124 kb
Host smart-7946a02a-e909-43c9-94ce-c785e6540dd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575156047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1575156047
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all_with_rand_reset.2240923002
Short name T140
Test name
Test status
Simulation time 21694533966 ps
CPU time 364.5 seconds
Started May 19 01:45:32 PM PDT 24
Finished May 19 01:51:37 PM PDT 24
Peak memory 275716 kb
Host smart-7a04ac0f-86ac-48ae-9d49-339253751246
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2240923002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_stress_all_with_rand_reset.2240923002
Directory /workspace/27.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.828546576
Short name T578
Test name
Test status
Simulation time 25677223 ps
CPU time 0.9 seconds
Started May 19 01:45:35 PM PDT 24
Finished May 19 01:45:37 PM PDT 24
Peak memory 211436 kb
Host smart-ef7a7d3c-dcf5-49b3-acb1-7fb609a2c57a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828546576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ct
rl_volatile_unlock_smoke.828546576
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1425062468
Short name T81
Test name
Test status
Simulation time 49511331 ps
CPU time 1.33 seconds
Started May 19 01:45:36 PM PDT 24
Finished May 19 01:45:38 PM PDT 24
Peak memory 209292 kb
Host smart-df0e34ba-dcc4-4398-936a-26391e776885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425062468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1425062468
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.3018451880
Short name T216
Test name
Test status
Simulation time 272888563 ps
CPU time 11.61 seconds
Started May 19 01:45:35 PM PDT 24
Finished May 19 01:45:48 PM PDT 24
Peak memory 217796 kb
Host smart-9e0ebd6d-4bd7-4fd2-a516-1db9690e4e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018451880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.3018451880
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.696800414
Short name T22
Test name
Test status
Simulation time 1362823409 ps
CPU time 8.69 seconds
Started May 19 01:45:34 PM PDT 24
Finished May 19 01:45:44 PM PDT 24
Peak memory 216716 kb
Host smart-6d5db643-7b59-4854-b61d-aa2923ed6506
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696800414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.696800414
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2105737821
Short name T601
Test name
Test status
Simulation time 123795925 ps
CPU time 3.91 seconds
Started May 19 01:45:34 PM PDT 24
Finished May 19 01:45:39 PM PDT 24
Peak memory 217792 kb
Host smart-5d51c47a-93c8-4483-a33f-65f566dac227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105737821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2105737821
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.415603263
Short name T549
Test name
Test status
Simulation time 570155167 ps
CPU time 13.27 seconds
Started May 19 01:45:31 PM PDT 24
Finished May 19 01:45:45 PM PDT 24
Peak memory 217788 kb
Host smart-f5a8f4b5-28fa-4ecb-bf9d-ad0e176a49f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415603263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.415603263
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.43692551
Short name T446
Test name
Test status
Simulation time 3011854770 ps
CPU time 17.11 seconds
Started May 19 01:45:32 PM PDT 24
Finished May 19 01:45:50 PM PDT 24
Peak memory 226028 kb
Host smart-3f6ec5e0-2666-4d4a-800a-835ca9fb9ebb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43692551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_dig
est.43692551
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3669586080
Short name T530
Test name
Test status
Simulation time 413249798 ps
CPU time 6.81 seconds
Started May 19 01:45:31 PM PDT 24
Finished May 19 01:45:38 PM PDT 24
Peak memory 217984 kb
Host smart-ee51098c-987f-4505-9f7c-80eb9ed1c340
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669586080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3669586080
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3770181823
Short name T785
Test name
Test status
Simulation time 730635369 ps
CPU time 6.91 seconds
Started May 19 01:46:06 PM PDT 24
Finished May 19 01:46:15 PM PDT 24
Peak memory 217876 kb
Host smart-48f68469-8f71-49a3-b722-4b96420c0298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770181823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3770181823
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.72307741
Short name T615
Test name
Test status
Simulation time 44465760 ps
CPU time 1.69 seconds
Started May 19 01:45:34 PM PDT 24
Finished May 19 01:45:37 PM PDT 24
Peak memory 213364 kb
Host smart-e18d7670-08a6-450f-baf1-48ec966d03fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72307741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.72307741
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2247228418
Short name T519
Test name
Test status
Simulation time 992551079 ps
CPU time 30.35 seconds
Started May 19 01:45:34 PM PDT 24
Finished May 19 01:46:05 PM PDT 24
Peak memory 250748 kb
Host smart-ace5d890-1a9d-4edb-8e43-d3e6144704cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247228418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2247228418
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.4137771829
Short name T274
Test name
Test status
Simulation time 150183279 ps
CPU time 9.9 seconds
Started May 19 01:45:32 PM PDT 24
Finished May 19 01:45:42 PM PDT 24
Peak memory 250616 kb
Host smart-e64d219c-21f9-4c2c-8ecb-4883d200dbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137771829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.4137771829
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2203356790
Short name T17
Test name
Test status
Simulation time 5442961836 ps
CPU time 74.88 seconds
Started May 19 01:45:34 PM PDT 24
Finished May 19 01:46:50 PM PDT 24
Peak memory 254300 kb
Host smart-513ffcdc-a259-4977-9503-11fcb6cb5600
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203356790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2203356790
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3375726215
Short name T812
Test name
Test status
Simulation time 43748586 ps
CPU time 0.96 seconds
Started May 19 01:45:34 PM PDT 24
Finished May 19 01:45:36 PM PDT 24
Peak memory 211308 kb
Host smart-26bbf619-8e8d-4452-b6cd-0aefedd9dbc5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375726215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3375726215
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1217794592
Short name T320
Test name
Test status
Simulation time 21281565 ps
CPU time 0.94 seconds
Started May 19 01:45:36 PM PDT 24
Finished May 19 01:45:38 PM PDT 24
Peak memory 209348 kb
Host smart-614e5054-5ba4-4ba8-81e8-127a33870036
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217794592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1217794592
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.3730002179
Short name T21
Test name
Test status
Simulation time 324940796 ps
CPU time 3.54 seconds
Started May 19 01:45:36 PM PDT 24
Finished May 19 01:45:41 PM PDT 24
Peak memory 209636 kb
Host smart-1eca3f78-ea31-4f91-9760-de05f7b6a8d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730002179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.3730002179
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3356830919
Short name T450
Test name
Test status
Simulation time 118028585 ps
CPU time 5.03 seconds
Started May 19 01:45:49 PM PDT 24
Finished May 19 01:45:56 PM PDT 24
Peak memory 217552 kb
Host smart-d8e9edec-8631-444b-b4a3-691600e365a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356830919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3356830919
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.4106745228
Short name T251
Test name
Test status
Simulation time 1694857217 ps
CPU time 12.59 seconds
Started May 19 01:45:48 PM PDT 24
Finished May 19 01:46:03 PM PDT 24
Peak memory 218380 kb
Host smart-882bb43b-125e-46ff-babe-06a6856ceb2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106745228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.4106745228
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3123433633
Short name T786
Test name
Test status
Simulation time 900728998 ps
CPU time 10.07 seconds
Started May 19 01:45:41 PM PDT 24
Finished May 19 01:45:52 PM PDT 24
Peak memory 217716 kb
Host smart-3013fc37-0111-44b0-ad05-d9baab14f414
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123433633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3123433633
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.489871215
Short name T741
Test name
Test status
Simulation time 327075311 ps
CPU time 12.29 seconds
Started May 19 01:45:37 PM PDT 24
Finished May 19 01:45:50 PM PDT 24
Peak memory 217844 kb
Host smart-a9c037f7-929c-4060-8e90-37875ac08a8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489871215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.489871215
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2689801951
Short name T756
Test name
Test status
Simulation time 749201771 ps
CPU time 6.46 seconds
Started May 19 01:45:36 PM PDT 24
Finished May 19 01:45:44 PM PDT 24
Peak memory 218068 kb
Host smart-64c1a7ad-c317-4cf8-bf0a-1b27f16cdb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689801951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2689801951
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2873776826
Short name T824
Test name
Test status
Simulation time 77578406 ps
CPU time 2.57 seconds
Started May 19 01:45:33 PM PDT 24
Finished May 19 01:45:36 PM PDT 24
Peak memory 213668 kb
Host smart-14d436e9-0836-4fb8-aa19-63dd352027a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873776826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2873776826
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1095448190
Short name T456
Test name
Test status
Simulation time 230418296 ps
CPU time 23.41 seconds
Started May 19 01:45:34 PM PDT 24
Finished May 19 01:45:59 PM PDT 24
Peak memory 250752 kb
Host smart-15eb07d6-ea99-4f4a-8006-8b70fd9bbfc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095448190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1095448190
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.959632856
Short name T185
Test name
Test status
Simulation time 515861451 ps
CPU time 7.79 seconds
Started May 19 01:45:37 PM PDT 24
Finished May 19 01:45:47 PM PDT 24
Peak memory 250800 kb
Host smart-4bd44195-8926-4abc-8e9d-43f3a56385e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959632856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.959632856
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1857660019
Short name T418
Test name
Test status
Simulation time 15325387524 ps
CPU time 114.22 seconds
Started May 19 01:45:37 PM PDT 24
Finished May 19 01:47:32 PM PDT 24
Peak memory 224944 kb
Host smart-b11dab43-a1d0-4700-8540-0e23994279ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857660019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1857660019
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.70897299
Short name T518
Test name
Test status
Simulation time 46744244 ps
CPU time 0.95 seconds
Started May 19 01:45:34 PM PDT 24
Finished May 19 01:45:37 PM PDT 24
Peak memory 211428 kb
Host smart-34b6950c-72bc-4c09-aa02-5d889150d686
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70897299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctr
l_volatile_unlock_smoke.70897299
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2059629739
Short name T352
Test name
Test status
Simulation time 13220841 ps
CPU time 0.82 seconds
Started May 19 01:44:11 PM PDT 24
Finished May 19 01:44:12 PM PDT 24
Peak memory 209280 kb
Host smart-1fb9a2f2-0d59-4cad-9680-137ab197faf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059629739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2059629739
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.4137105978
Short name T192
Test name
Test status
Simulation time 37741899 ps
CPU time 0.92 seconds
Started May 19 01:44:11 PM PDT 24
Finished May 19 01:44:13 PM PDT 24
Peak memory 209380 kb
Host smart-6c901a3d-bce5-43f8-aa8b-5cdaa897619c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137105978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.4137105978
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1115097844
Short name T796
Test name
Test status
Simulation time 342157813 ps
CPU time 15.42 seconds
Started May 19 01:44:11 PM PDT 24
Finished May 19 01:44:27 PM PDT 24
Peak memory 217736 kb
Host smart-9e6597ed-69f7-4e10-9662-2c6e8f52362b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115097844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1115097844
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3982043962
Short name T23
Test name
Test status
Simulation time 469754561 ps
CPU time 2.48 seconds
Started May 19 01:44:06 PM PDT 24
Finished May 19 01:44:11 PM PDT 24
Peak memory 209368 kb
Host smart-a7bd3e2a-32df-4825-a203-317949433e82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982043962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3982043962
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1462582036
Short name T788
Test name
Test status
Simulation time 22327516746 ps
CPU time 86.63 seconds
Started May 19 01:44:05 PM PDT 24
Finished May 19 01:45:34 PM PDT 24
Peak memory 218524 kb
Host smart-2785030f-70fa-4788-bf80-a21cb3aafb6c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462582036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1462582036
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3380735599
Short name T317
Test name
Test status
Simulation time 3901047581 ps
CPU time 11.12 seconds
Started May 19 01:44:10 PM PDT 24
Finished May 19 01:44:22 PM PDT 24
Peak memory 217680 kb
Host smart-e02c22f9-1863-4b94-bc6a-d51de8ddab6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380735599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
380735599
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2969510957
Short name T689
Test name
Test status
Simulation time 1569345037 ps
CPU time 6.22 seconds
Started May 19 01:44:07 PM PDT 24
Finished May 19 01:44:15 PM PDT 24
Peak memory 217800 kb
Host smart-fbea793a-a4ee-4359-960f-87ca5add0aad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969510957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2969510957
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3093086073
Short name T725
Test name
Test status
Simulation time 1516918893 ps
CPU time 40.61 seconds
Started May 19 01:44:06 PM PDT 24
Finished May 19 01:44:49 PM PDT 24
Peak memory 212740 kb
Host smart-cf284940-45ca-4ae7-bed8-ab2572f08299
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093086073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3093086073
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3111136737
Short name T451
Test name
Test status
Simulation time 1815699498 ps
CPU time 5.84 seconds
Started May 19 01:44:06 PM PDT 24
Finished May 19 01:44:14 PM PDT 24
Peak memory 213720 kb
Host smart-482c688f-278b-4d0a-a251-d06ca00b7444
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111136737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3111136737
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.1335625855
Short name T190
Test name
Test status
Simulation time 5685428906 ps
CPU time 53.79 seconds
Started May 19 01:44:07 PM PDT 24
Finished May 19 01:45:02 PM PDT 24
Peak memory 267220 kb
Host smart-33466a9f-8b90-46b2-be54-20289f021d07
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335625855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.1335625855
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.298392678
Short name T366
Test name
Test status
Simulation time 290294282 ps
CPU time 15.26 seconds
Started May 19 01:44:10 PM PDT 24
Finished May 19 01:44:27 PM PDT 24
Peak memory 250660 kb
Host smart-fb894e52-80e7-4e1d-9031-6c885e74457a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298392678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.298392678
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3299293832
Short name T209
Test name
Test status
Simulation time 17506389 ps
CPU time 1.65 seconds
Started May 19 01:44:06 PM PDT 24
Finished May 19 01:44:10 PM PDT 24
Peak memory 217812 kb
Host smart-11e4f55b-719f-4de6-92a5-3bed41005f59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299293832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3299293832
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2672397437
Short name T226
Test name
Test status
Simulation time 801420984 ps
CPU time 10.96 seconds
Started May 19 01:44:08 PM PDT 24
Finished May 19 01:44:20 PM PDT 24
Peak memory 217576 kb
Host smart-4d538e2e-834d-4632-b31c-6f7b261e2dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672397437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2672397437
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.3479990068
Short name T31
Test name
Test status
Simulation time 302782350 ps
CPU time 20.3 seconds
Started May 19 01:44:09 PM PDT 24
Finished May 19 01:44:30 PM PDT 24
Peak memory 268684 kb
Host smart-ce676cd2-db33-4afe-b033-e8370d33a06d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479990068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.3479990068
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.3694820570
Short name T650
Test name
Test status
Simulation time 1362758482 ps
CPU time 11.11 seconds
Started May 19 01:44:07 PM PDT 24
Finished May 19 01:44:20 PM PDT 24
Peak memory 218740 kb
Host smart-bcd1cfb5-39c3-4148-942c-7493c2fc7dc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694820570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.3694820570
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2133160246
Short name T818
Test name
Test status
Simulation time 248879727 ps
CPU time 7.84 seconds
Started May 19 01:44:10 PM PDT 24
Finished May 19 01:44:19 PM PDT 24
Peak memory 217804 kb
Host smart-f9a72084-2f45-4b00-bc97-6d4b04b9a340
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133160246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2133160246
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.2843803098
Short name T787
Test name
Test status
Simulation time 348824138 ps
CPU time 8.77 seconds
Started May 19 01:44:12 PM PDT 24
Finished May 19 01:44:22 PM PDT 24
Peak memory 217800 kb
Host smart-c5217b07-4077-4b82-9677-3883f0047a93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843803098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.2
843803098
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.821161579
Short name T16
Test name
Test status
Simulation time 598911579 ps
CPU time 9.91 seconds
Started May 19 01:44:05 PM PDT 24
Finished May 19 01:44:18 PM PDT 24
Peak memory 217828 kb
Host smart-63371188-8dd7-42db-8061-6fec23fd842b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821161579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.821161579
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3082493948
Short name T372
Test name
Test status
Simulation time 16373451 ps
CPU time 1.46 seconds
Started May 19 01:44:10 PM PDT 24
Finished May 19 01:44:12 PM PDT 24
Peak memory 213296 kb
Host smart-28bf3989-41f5-4b1c-97a9-15e38949873e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082493948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3082493948
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3211925372
Short name T613
Test name
Test status
Simulation time 286655331 ps
CPU time 36.84 seconds
Started May 19 01:44:06 PM PDT 24
Finished May 19 01:44:45 PM PDT 24
Peak memory 250732 kb
Host smart-0a49be7d-3255-435c-9bdf-64f24087c38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211925372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3211925372
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1734222261
Short name T701
Test name
Test status
Simulation time 119680148 ps
CPU time 6.33 seconds
Started May 19 01:44:06 PM PDT 24
Finished May 19 01:44:14 PM PDT 24
Peak memory 250324 kb
Host smart-4939c150-4d75-4edf-93aa-d98bf80f4b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734222261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1734222261
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3980087010
Short name T397
Test name
Test status
Simulation time 5858792938 ps
CPU time 93.22 seconds
Started May 19 01:44:11 PM PDT 24
Finished May 19 01:45:45 PM PDT 24
Peak memory 267264 kb
Host smart-6f56d7b0-ef5b-4b5c-9419-8ec1deed269b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980087010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3980087010
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1049295219
Short name T807
Test name
Test status
Simulation time 32588271 ps
CPU time 0.93 seconds
Started May 19 01:44:10 PM PDT 24
Finished May 19 01:44:12 PM PDT 24
Peak memory 211512 kb
Host smart-f3b166d1-641f-4280-8366-d86d3966d101
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049295219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1049295219
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2519332812
Short name T395
Test name
Test status
Simulation time 58828872 ps
CPU time 1.06 seconds
Started May 19 01:45:37 PM PDT 24
Finished May 19 01:45:40 PM PDT 24
Peak memory 209356 kb
Host smart-88fe97e7-7be4-47e8-a861-debd4a594321
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519332812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2519332812
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1159839713
Short name T647
Test name
Test status
Simulation time 462387768 ps
CPU time 12.22 seconds
Started May 19 01:45:38 PM PDT 24
Finished May 19 01:45:52 PM PDT 24
Peak memory 217796 kb
Host smart-bb2fdf3b-f797-4a26-812e-37955f161ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159839713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1159839713
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.1543832815
Short name T751
Test name
Test status
Simulation time 514919881 ps
CPU time 6.28 seconds
Started May 19 01:45:41 PM PDT 24
Finished May 19 01:45:48 PM PDT 24
Peak memory 209304 kb
Host smart-b1f45de4-dfbe-4ce3-a5bd-1f55ce409dab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543832815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.1543832815
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.63938000
Short name T637
Test name
Test status
Simulation time 255300748 ps
CPU time 3.25 seconds
Started May 19 01:45:37 PM PDT 24
Finished May 19 01:45:41 PM PDT 24
Peak memory 217764 kb
Host smart-46f28240-4b7a-4cc2-9ad2-6f70999c3402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63938000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.63938000
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3901397731
Short name T744
Test name
Test status
Simulation time 332487901 ps
CPU time 12.39 seconds
Started May 19 01:45:37 PM PDT 24
Finished May 19 01:45:51 PM PDT 24
Peak memory 225884 kb
Host smart-cdcdc163-9788-41d2-874e-8288c9c5775f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901397731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3901397731
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.4136977788
Short name T755
Test name
Test status
Simulation time 231189851 ps
CPU time 8.29 seconds
Started May 19 01:45:48 PM PDT 24
Finished May 19 01:45:59 PM PDT 24
Peak memory 217724 kb
Host smart-673dc959-a2d0-4b50-a5a6-8b4280499319
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136977788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.4136977788
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.4013568405
Short name T200
Test name
Test status
Simulation time 284252206 ps
CPU time 8.62 seconds
Started May 19 01:45:38 PM PDT 24
Finished May 19 01:45:48 PM PDT 24
Peak memory 217748 kb
Host smart-c296f3bc-8dfb-465d-aad6-337dcf1cb930
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013568405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
4013568405
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.161797164
Short name T537
Test name
Test status
Simulation time 646307248 ps
CPU time 12.04 seconds
Started May 19 01:45:40 PM PDT 24
Finished May 19 01:45:53 PM PDT 24
Peak memory 217796 kb
Host smart-780c0a0c-ec12-4ec8-9094-f61feef3387e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161797164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.161797164
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.3277683138
Short name T489
Test name
Test status
Simulation time 17601659 ps
CPU time 0.97 seconds
Started May 19 01:45:36 PM PDT 24
Finished May 19 01:45:38 PM PDT 24
Peak memory 211572 kb
Host smart-c8a729ef-6472-4002-b884-157e44b43fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277683138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.3277683138
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.489168577
Short name T587
Test name
Test status
Simulation time 191853367 ps
CPU time 24.67 seconds
Started May 19 01:45:36 PM PDT 24
Finished May 19 01:46:02 PM PDT 24
Peak memory 250748 kb
Host smart-9a80c3dc-967d-479e-9e6a-719356e48db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489168577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.489168577
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.94625025
Short name T844
Test name
Test status
Simulation time 293594975 ps
CPU time 8.86 seconds
Started May 19 01:45:36 PM PDT 24
Finished May 19 01:45:46 PM PDT 24
Peak memory 250704 kb
Host smart-fa94e66c-a900-4367-937b-f487443638f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94625025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.94625025
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3619286538
Short name T835
Test name
Test status
Simulation time 28141481774 ps
CPU time 398.82 seconds
Started May 19 01:45:39 PM PDT 24
Finished May 19 01:52:20 PM PDT 24
Peak memory 250824 kb
Host smart-39b74b54-adf5-45b7-9d1d-30513e98f4c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619286538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3619286538
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.27651527
Short name T382
Test name
Test status
Simulation time 19945344 ps
CPU time 0.98 seconds
Started May 19 01:45:37 PM PDT 24
Finished May 19 01:45:40 PM PDT 24
Peak memory 211452 kb
Host smart-80854e06-22f8-4dbb-a6d1-b30ff2eed813
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27651527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctr
l_volatile_unlock_smoke.27651527
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.926483461
Short name T603
Test name
Test status
Simulation time 22265882 ps
CPU time 0.97 seconds
Started May 19 01:45:47 PM PDT 24
Finished May 19 01:45:50 PM PDT 24
Peak memory 209360 kb
Host smart-c3b7f0ec-3e72-4a50-a203-a1962a96b672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926483461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.926483461
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3904249428
Short name T181
Test name
Test status
Simulation time 214375254 ps
CPU time 10.04 seconds
Started May 19 01:45:42 PM PDT 24
Finished May 19 01:45:52 PM PDT 24
Peak memory 217808 kb
Host smart-bc092bb2-226d-4330-b53f-3f5491e5fdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904249428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3904249428
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1657695900
Short name T473
Test name
Test status
Simulation time 199169869 ps
CPU time 2.6 seconds
Started May 19 01:45:49 PM PDT 24
Finished May 19 01:45:53 PM PDT 24
Peak memory 209300 kb
Host smart-c97b5689-2b07-40b1-a49c-778a003a6be6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657695900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1657695900
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.1762237643
Short name T187
Test name
Test status
Simulation time 391404759 ps
CPU time 4.58 seconds
Started May 19 01:45:42 PM PDT 24
Finished May 19 01:45:48 PM PDT 24
Peak memory 217856 kb
Host smart-b8b28047-01bd-43d1-9869-10b8643c8956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762237643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.1762237643
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.3646500807
Short name T315
Test name
Test status
Simulation time 928949602 ps
CPU time 9.71 seconds
Started May 19 01:45:41 PM PDT 24
Finished May 19 01:45:52 PM PDT 24
Peak memory 225872 kb
Host smart-60c29b3b-6f3c-4680-89f7-e6fd2c177706
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646500807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.3646500807
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.757326705
Short name T568
Test name
Test status
Simulation time 304023947 ps
CPU time 8.85 seconds
Started May 19 01:45:42 PM PDT 24
Finished May 19 01:45:52 PM PDT 24
Peak memory 217788 kb
Host smart-c7992237-f587-4f54-91ce-dc8ff22d2a24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757326705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_di
gest.757326705
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.762980635
Short name T479
Test name
Test status
Simulation time 209974820 ps
CPU time 7.91 seconds
Started May 19 01:45:42 PM PDT 24
Finished May 19 01:45:51 PM PDT 24
Peak memory 217812 kb
Host smart-8bca9351-343b-4ff0-9c6e-4e82ecb37efb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762980635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.762980635
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2108087176
Short name T386
Test name
Test status
Simulation time 327313831 ps
CPU time 13.12 seconds
Started May 19 01:45:47 PM PDT 24
Finished May 19 01:46:03 PM PDT 24
Peak memory 217896 kb
Host smart-2d62448f-3f54-4a56-8b7c-6c6cdbb3e5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2108087176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2108087176
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.3406668510
Short name T404
Test name
Test status
Simulation time 53581071 ps
CPU time 2.8 seconds
Started May 19 01:45:38 PM PDT 24
Finished May 19 01:45:42 PM PDT 24
Peak memory 217712 kb
Host smart-d50868eb-6ebe-4330-ab1f-bfee21931002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406668510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.3406668510
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2235993001
Short name T491
Test name
Test status
Simulation time 1322843536 ps
CPU time 27.27 seconds
Started May 19 01:45:38 PM PDT 24
Finished May 19 01:46:07 PM PDT 24
Peak memory 250736 kb
Host smart-480e132a-89aa-4142-bd7b-b0e6d6065ec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235993001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2235993001
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.2872672712
Short name T380
Test name
Test status
Simulation time 208266448 ps
CPU time 10.02 seconds
Started May 19 01:45:38 PM PDT 24
Finished May 19 01:45:50 PM PDT 24
Peak memory 250724 kb
Host smart-6e4d5e60-8506-4998-a720-8bc396af683d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872672712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.2872672712
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2579802141
Short name T396
Test name
Test status
Simulation time 19581551095 ps
CPU time 137.5 seconds
Started May 19 01:45:43 PM PDT 24
Finished May 19 01:48:01 PM PDT 24
Peak memory 274764 kb
Host smart-538c9afc-9a79-4510-aac1-dc7c63e59be1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579802141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2579802141
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.3109888682
Short name T83
Test name
Test status
Simulation time 146911592535 ps
CPU time 1385.16 seconds
Started May 19 01:45:43 PM PDT 24
Finished May 19 02:08:49 PM PDT 24
Peak memory 372704 kb
Host smart-6989b210-826f-4082-aee6-f3e7030a3445
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3109888682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.3109888682
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3617819515
Short name T402
Test name
Test status
Simulation time 24643452 ps
CPU time 0.86 seconds
Started May 19 01:45:48 PM PDT 24
Finished May 19 01:45:51 PM PDT 24
Peak memory 211336 kb
Host smart-18c18cd5-3b43-409b-83dd-6b31fa0f34a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617819515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3617819515
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.3057012848
Short name T281
Test name
Test status
Simulation time 16285869 ps
CPU time 0.92 seconds
Started May 19 01:45:49 PM PDT 24
Finished May 19 01:45:51 PM PDT 24
Peak memory 209140 kb
Host smart-ff83fd90-54d6-4e06-9abe-ad22642d8057
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057012848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.3057012848
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2604749767
Short name T738
Test name
Test status
Simulation time 183967106 ps
CPU time 9.62 seconds
Started May 19 01:45:39 PM PDT 24
Finished May 19 01:45:50 PM PDT 24
Peak memory 217708 kb
Host smart-517ae78a-4fc5-49d8-b6b9-bdd133946fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604749767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2604749767
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2285499831
Short name T7
Test name
Test status
Simulation time 3936239957 ps
CPU time 22.46 seconds
Started May 19 01:45:47 PM PDT 24
Finished May 19 01:46:11 PM PDT 24
Peak memory 209496 kb
Host smart-ebc7af17-de8b-46ec-90b6-7ecd27b9ad6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285499831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2285499831
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1399402334
Short name T730
Test name
Test status
Simulation time 65908956 ps
CPU time 2.48 seconds
Started May 19 01:45:45 PM PDT 24
Finished May 19 01:45:50 PM PDT 24
Peak memory 217864 kb
Host smart-ba02e482-c2bf-4e2c-b98f-059b407976ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399402334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1399402334
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1840901622
Short name T737
Test name
Test status
Simulation time 1292036764 ps
CPU time 13.99 seconds
Started May 19 01:45:39 PM PDT 24
Finished May 19 01:45:54 PM PDT 24
Peak memory 225852 kb
Host smart-2d4986bd-89cb-44f4-97c3-e0d7670aca62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840901622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1840901622
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3514594868
Short name T515
Test name
Test status
Simulation time 2885666207 ps
CPU time 20.91 seconds
Started May 19 01:45:44 PM PDT 24
Finished May 19 01:46:06 PM PDT 24
Peak memory 226020 kb
Host smart-1947c6fd-c26f-465c-92d6-30a847ee4e7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514594868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3514594868
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.491943280
Short name T498
Test name
Test status
Simulation time 1018318995 ps
CPU time 6.56 seconds
Started May 19 01:45:47 PM PDT 24
Finished May 19 01:45:56 PM PDT 24
Peak memory 217836 kb
Host smart-e0dacb12-32c7-4ee7-91c4-93fc5bdb5a3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491943280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.491943280
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3173577458
Short name T522
Test name
Test status
Simulation time 253462303 ps
CPU time 8.71 seconds
Started May 19 01:45:40 PM PDT 24
Finished May 19 01:45:50 PM PDT 24
Peak memory 217916 kb
Host smart-e12373d7-81d9-40d6-ac4e-b297e408693b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173577458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3173577458
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2174544131
Short name T351
Test name
Test status
Simulation time 141880927 ps
CPU time 2.73 seconds
Started May 19 01:45:47 PM PDT 24
Finished May 19 01:45:52 PM PDT 24
Peak memory 213740 kb
Host smart-ff3161be-4bcc-44ec-b890-0037046a1ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174544131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2174544131
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.472465322
Short name T834
Test name
Test status
Simulation time 257120607 ps
CPU time 22.68 seconds
Started May 19 01:45:41 PM PDT 24
Finished May 19 01:46:05 PM PDT 24
Peak memory 250752 kb
Host smart-92019139-69c6-4730-b650-3bb2ba58fa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472465322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.472465322
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3587088001
Short name T271
Test name
Test status
Simulation time 497933677 ps
CPU time 6.94 seconds
Started May 19 01:45:40 PM PDT 24
Finished May 19 01:45:48 PM PDT 24
Peak memory 245412 kb
Host smart-9832aaf1-cd89-4b0c-8551-f9ad2b4c9694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587088001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3587088001
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1510288550
Short name T462
Test name
Test status
Simulation time 14051444568 ps
CPU time 67.9 seconds
Started May 19 01:45:45 PM PDT 24
Finished May 19 01:46:55 PM PDT 24
Peak memory 225976 kb
Host smart-8b08e4ec-ca7d-453a-b55d-1a43deb6a829
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510288550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1510288550
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2456646174
Short name T128
Test name
Test status
Simulation time 38525843893 ps
CPU time 394.8 seconds
Started May 19 01:45:47 PM PDT 24
Finished May 19 01:52:24 PM PDT 24
Peak memory 291972 kb
Host smart-858968fb-f3fe-489a-9435-7574a813fb41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2456646174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.2456646174
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1175197324
Short name T471
Test name
Test status
Simulation time 26979855 ps
CPU time 1.03 seconds
Started May 19 01:45:40 PM PDT 24
Finished May 19 01:45:42 PM PDT 24
Peak memory 211508 kb
Host smart-924af6b5-061c-4765-8673-6280a61274e3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175197324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1175197324
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.2884328777
Short name T640
Test name
Test status
Simulation time 41559394 ps
CPU time 0.8 seconds
Started May 19 01:45:46 PM PDT 24
Finished May 19 01:45:49 PM PDT 24
Peak memory 209236 kb
Host smart-a6fe9d36-3be2-4d17-8ae8-8e337f652f3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884328777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.2884328777
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.246769304
Short name T745
Test name
Test status
Simulation time 553099826 ps
CPU time 10.67 seconds
Started May 19 01:45:47 PM PDT 24
Finished May 19 01:46:00 PM PDT 24
Peak memory 217808 kb
Host smart-0fdcb14f-f13a-4661-926a-0fa701d6bd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246769304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.246769304
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3138734681
Short name T584
Test name
Test status
Simulation time 824477364 ps
CPU time 3.68 seconds
Started May 19 01:45:46 PM PDT 24
Finished May 19 01:45:52 PM PDT 24
Peak memory 209396 kb
Host smart-cebdb3b0-d807-425b-8fcc-378f742ff56c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138734681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3138734681
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.446019441
Short name T260
Test name
Test status
Simulation time 19024562 ps
CPU time 1.81 seconds
Started May 19 01:45:49 PM PDT 24
Finished May 19 01:45:52 PM PDT 24
Peak memory 217648 kb
Host smart-45879806-2e78-4ff7-b1e5-991838f88395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446019441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.446019441
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.2045655617
Short name T783
Test name
Test status
Simulation time 827296045 ps
CPU time 8.17 seconds
Started May 19 01:45:44 PM PDT 24
Finished May 19 01:45:53 PM PDT 24
Peak memory 218716 kb
Host smart-fd00d2fe-9b21-47db-9a6e-ff3b9f43d176
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045655617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.2045655617
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2816433793
Short name T246
Test name
Test status
Simulation time 1887045811 ps
CPU time 11.56 seconds
Started May 19 01:45:48 PM PDT 24
Finished May 19 01:46:02 PM PDT 24
Peak memory 217808 kb
Host smart-7b9fd589-1cd7-4aa7-844c-33bbe56d3802
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816433793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2816433793
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.2737319936
Short name T54
Test name
Test status
Simulation time 364986939 ps
CPU time 9.02 seconds
Started May 19 01:45:46 PM PDT 24
Finished May 19 01:45:57 PM PDT 24
Peak memory 217796 kb
Host smart-577bfbf2-bcb1-4e25-a0cf-ce92374b684e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737319936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
2737319936
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2835754822
Short name T384
Test name
Test status
Simulation time 1499266266 ps
CPU time 8.95 seconds
Started May 19 01:45:45 PM PDT 24
Finished May 19 01:45:54 PM PDT 24
Peak memory 217768 kb
Host smart-4b9182ff-bf2f-4eb1-8977-70b5cb961cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835754822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2835754822
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3284376339
Short name T754
Test name
Test status
Simulation time 148750595 ps
CPU time 8.6 seconds
Started May 19 01:45:44 PM PDT 24
Finished May 19 01:45:53 PM PDT 24
Peak memory 217576 kb
Host smart-11b1fa8b-4269-4bbb-bf0b-d4f38081d846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284376339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3284376339
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2164209889
Short name T400
Test name
Test status
Simulation time 822367085 ps
CPU time 25.61 seconds
Started May 19 01:45:48 PM PDT 24
Finished May 19 01:46:15 PM PDT 24
Peak memory 250748 kb
Host smart-5059289a-6061-4828-8518-0115321f2a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164209889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2164209889
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.3923786384
Short name T826
Test name
Test status
Simulation time 99489690 ps
CPU time 7.2 seconds
Started May 19 01:45:50 PM PDT 24
Finished May 19 01:45:59 PM PDT 24
Peak memory 250304 kb
Host smart-bddc591a-4b4f-4ff3-b153-9d08c39ea34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923786384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.3923786384
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1273661005
Short name T791
Test name
Test status
Simulation time 15749729932 ps
CPU time 537.7 seconds
Started May 19 01:45:45 PM PDT 24
Finished May 19 01:54:46 PM PDT 24
Peak memory 283596 kb
Host smart-91d996b8-21ac-4035-ae7c-4a98234221b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273661005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1273661005
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2553022947
Short name T310
Test name
Test status
Simulation time 33631122 ps
CPU time 0.93 seconds
Started May 19 01:45:45 PM PDT 24
Finished May 19 01:45:49 PM PDT 24
Peak memory 212436 kb
Host smart-579ac50c-d54f-4cdf-8436-1eb4f215d41c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553022947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2553022947
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.206660428
Short name T202
Test name
Test status
Simulation time 40106209 ps
CPU time 1.03 seconds
Started May 19 01:45:49 PM PDT 24
Finished May 19 01:45:52 PM PDT 24
Peak memory 209388 kb
Host smart-13033e15-7e85-4430-b0fc-8453fac10111
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206660428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.206660428
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.843232997
Short name T224
Test name
Test status
Simulation time 299459246 ps
CPU time 10.4 seconds
Started May 19 01:45:51 PM PDT 24
Finished May 19 01:46:04 PM PDT 24
Peak memory 217784 kb
Host smart-a7bbe9ae-cbc1-433f-8164-cc963f53c296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843232997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.843232997
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.4051130784
Short name T684
Test name
Test status
Simulation time 496448268 ps
CPU time 3.64 seconds
Started May 19 01:45:47 PM PDT 24
Finished May 19 01:45:53 PM PDT 24
Peak memory 209320 kb
Host smart-b703595e-2d34-43fd-bdd8-7c929cb1b00a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051130784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.4051130784
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1970145440
Short name T585
Test name
Test status
Simulation time 134942432 ps
CPU time 2.37 seconds
Started May 19 01:45:47 PM PDT 24
Finished May 19 01:45:52 PM PDT 24
Peak memory 217708 kb
Host smart-a06e9766-d159-4985-9ecb-750470ce725d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970145440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1970145440
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.2951651135
Short name T52
Test name
Test status
Simulation time 1533369286 ps
CPU time 14.41 seconds
Started May 19 01:45:51 PM PDT 24
Finished May 19 01:46:07 PM PDT 24
Peak memory 218740 kb
Host smart-36d9e191-2794-4535-a5e3-83b91565e0fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951651135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2951651135
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3955588015
Short name T298
Test name
Test status
Simulation time 322025882 ps
CPU time 8.51 seconds
Started May 19 01:45:46 PM PDT 24
Finished May 19 01:45:57 PM PDT 24
Peak memory 217776 kb
Host smart-98a362b0-c066-4250-a515-fd53851a4202
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955588015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3955588015
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.75597003
Short name T464
Test name
Test status
Simulation time 422681487 ps
CPU time 8.05 seconds
Started May 19 01:45:46 PM PDT 24
Finished May 19 01:45:57 PM PDT 24
Peak memory 217864 kb
Host smart-7cdd0827-2c97-40c3-a178-78d2de35af31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75597003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.75597003
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3323944264
Short name T480
Test name
Test status
Simulation time 429223008 ps
CPU time 9.53 seconds
Started May 19 01:45:50 PM PDT 24
Finished May 19 01:46:02 PM PDT 24
Peak memory 217868 kb
Host smart-9c1fd8f5-1836-4796-b884-4bd8a3c50638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323944264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3323944264
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.4294679225
Short name T57
Test name
Test status
Simulation time 158809812 ps
CPU time 1.96 seconds
Started May 19 01:45:47 PM PDT 24
Finished May 19 01:45:52 PM PDT 24
Peak memory 213644 kb
Host smart-8e3a53ec-5b83-49a3-8860-4be39a316717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294679225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.4294679225
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.4280774135
Short name T872
Test name
Test status
Simulation time 251221975 ps
CPU time 28.24 seconds
Started May 19 01:45:48 PM PDT 24
Finished May 19 01:46:18 PM PDT 24
Peak memory 250752 kb
Host smart-f459d158-acda-46a1-9d02-f19482b8efba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280774135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.4280774135
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.2765112913
Short name T569
Test name
Test status
Simulation time 52657752 ps
CPU time 3.45 seconds
Started May 19 01:45:45 PM PDT 24
Finished May 19 01:45:51 PM PDT 24
Peak memory 222456 kb
Host smart-e50dd4b3-244e-4176-bd22-09d3da546daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765112913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.2765112913
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3723464218
Short name T851
Test name
Test status
Simulation time 9543429576 ps
CPU time 112.59 seconds
Started May 19 01:45:46 PM PDT 24
Finished May 19 01:47:40 PM PDT 24
Peak memory 283364 kb
Host smart-41f80656-b496-4b0e-bdd6-207c55257f5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723464218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3723464218
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1787191233
Short name T622
Test name
Test status
Simulation time 12792362 ps
CPU time 0.88 seconds
Started May 19 01:45:49 PM PDT 24
Finished May 19 01:45:52 PM PDT 24
Peak memory 211496 kb
Host smart-8c08d663-3e58-45fc-807c-4007046950b7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787191233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1787191233
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.824714567
Short name T660
Test name
Test status
Simulation time 31578060 ps
CPU time 0.91 seconds
Started May 19 01:45:50 PM PDT 24
Finished May 19 01:45:54 PM PDT 24
Peak memory 209344 kb
Host smart-5d198eb3-97a9-44ab-aa24-519d6abb4518
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824714567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.824714567
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.1914933078
Short name T547
Test name
Test status
Simulation time 1316837773 ps
CPU time 14.85 seconds
Started May 19 01:45:55 PM PDT 24
Finished May 19 01:46:10 PM PDT 24
Peak memory 217780 kb
Host smart-9c1c9aba-e215-4c7c-bdb1-39085fe73480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914933078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.1914933078
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2546801337
Short name T9
Test name
Test status
Simulation time 336078356 ps
CPU time 3.26 seconds
Started May 19 01:45:52 PM PDT 24
Finished May 19 01:45:57 PM PDT 24
Peak memory 216936 kb
Host smart-aa6f5c3f-42fc-4214-bbf3-0a40d4a1128b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546801337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2546801337
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2472144668
Short name T552
Test name
Test status
Simulation time 233965689 ps
CPU time 3.42 seconds
Started May 19 01:45:51 PM PDT 24
Finished May 19 01:45:57 PM PDT 24
Peak memory 217860 kb
Host smart-d7fa89aa-3164-4c11-b751-15004e8c9c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472144668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2472144668
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.334360887
Short name T869
Test name
Test status
Simulation time 3817038259 ps
CPU time 14.25 seconds
Started May 19 01:45:51 PM PDT 24
Finished May 19 01:46:08 PM PDT 24
Peak memory 219124 kb
Host smart-252e3e95-1261-4b4f-9c73-d9c64dcd3cab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334360887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.334360887
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.4035163021
Short name T241
Test name
Test status
Simulation time 3709308103 ps
CPU time 10.8 seconds
Started May 19 01:45:52 PM PDT 24
Finished May 19 01:46:04 PM PDT 24
Peak memory 217884 kb
Host smart-adbcac15-7abc-46a5-8f5e-4677829a19c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035163021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.4035163021
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1308495906
Short name T506
Test name
Test status
Simulation time 1474535189 ps
CPU time 13.04 seconds
Started May 19 01:45:55 PM PDT 24
Finished May 19 01:46:09 PM PDT 24
Peak memory 217844 kb
Host smart-5cd4419b-df20-446d-be87-1a07d833049d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308495906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1308495906
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2605330527
Short name T513
Test name
Test status
Simulation time 608037581 ps
CPU time 10.09 seconds
Started May 19 01:45:52 PM PDT 24
Finished May 19 01:46:04 PM PDT 24
Peak memory 217908 kb
Host smart-60a20c3a-16da-4b3d-bff1-40064c8e946d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605330527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2605330527
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3044296204
Short name T540
Test name
Test status
Simulation time 297463716 ps
CPU time 4.35 seconds
Started May 19 01:45:47 PM PDT 24
Finished May 19 01:45:54 PM PDT 24
Peak memory 214984 kb
Host smart-52d181b9-6c8f-40a1-9cfd-b991bce25420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044296204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3044296204
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2818074807
Short name T815
Test name
Test status
Simulation time 950009789 ps
CPU time 31.04 seconds
Started May 19 01:45:50 PM PDT 24
Finished May 19 01:46:24 PM PDT 24
Peak memory 250612 kb
Host smart-36ee736c-ab8f-4eec-a9aa-139c94659160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818074807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2818074807
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.3617271051
Short name T3
Test name
Test status
Simulation time 54699579 ps
CPU time 6.21 seconds
Started May 19 01:45:54 PM PDT 24
Finished May 19 01:46:01 PM PDT 24
Peak memory 246456 kb
Host smart-9e1a71a8-8947-4827-8cce-9a555b319efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617271051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.3617271051
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.1400541494
Short name T827
Test name
Test status
Simulation time 4103318255 ps
CPU time 83.33 seconds
Started May 19 01:45:50 PM PDT 24
Finished May 19 01:47:16 PM PDT 24
Peak memory 267292 kb
Host smart-58471069-5a53-4aac-9b8e-64f7dc38344b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400541494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.1400541494
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.2032358523
Short name T11
Test name
Test status
Simulation time 42280771757 ps
CPU time 447.58 seconds
Started May 19 01:45:50 PM PDT 24
Finished May 19 01:53:20 PM PDT 24
Peak memory 277624 kb
Host smart-c405d5d7-1fd2-4684-843a-b67516e5db98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2032358523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.2032358523
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1695646121
Short name T643
Test name
Test status
Simulation time 75826107 ps
CPU time 0.95 seconds
Started May 19 01:45:55 PM PDT 24
Finished May 19 01:45:57 PM PDT 24
Peak memory 212680 kb
Host smart-285d06c6-1798-4869-97c9-1f9640740074
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695646121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1695646121
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.101600764
Short name T67
Test name
Test status
Simulation time 51824972 ps
CPU time 0.92 seconds
Started May 19 01:46:00 PM PDT 24
Finished May 19 01:46:01 PM PDT 24
Peak memory 209364 kb
Host smart-4a0fa69c-4f05-46be-91f3-0fb30954cd17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101600764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.101600764
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.151971487
Short name T407
Test name
Test status
Simulation time 241742445 ps
CPU time 11.95 seconds
Started May 19 01:45:54 PM PDT 24
Finished May 19 01:46:07 PM PDT 24
Peak memory 217776 kb
Host smart-60eef4df-4b15-443a-be7a-8e84b573d95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151971487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.151971487
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2361415587
Short name T507
Test name
Test status
Simulation time 480864809 ps
CPU time 3.75 seconds
Started May 19 01:45:50 PM PDT 24
Finished May 19 01:45:57 PM PDT 24
Peak memory 209368 kb
Host smart-440ba885-c551-41ca-9081-96a0610e8197
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361415587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2361415587
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3443209798
Short name T557
Test name
Test status
Simulation time 488691277 ps
CPU time 5.13 seconds
Started May 19 01:45:52 PM PDT 24
Finished May 19 01:45:59 PM PDT 24
Peak memory 217828 kb
Host smart-bdf2d87e-f75f-4238-8650-2c274cf9ec88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443209798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3443209798
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1295823257
Short name T855
Test name
Test status
Simulation time 360693526 ps
CPU time 11.86 seconds
Started May 19 01:45:54 PM PDT 24
Finished May 19 01:46:07 PM PDT 24
Peak memory 218660 kb
Host smart-143bfb21-d008-4905-8a56-d9e91fa57934
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295823257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1295823257
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3573421860
Short name T376
Test name
Test status
Simulation time 2083059756 ps
CPU time 12.37 seconds
Started May 19 01:45:54 PM PDT 24
Finished May 19 01:46:07 PM PDT 24
Peak memory 225884 kb
Host smart-f46340da-de17-4244-8790-6316d1207c22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573421860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3573421860
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3501968835
Short name T657
Test name
Test status
Simulation time 1369430085 ps
CPU time 11.17 seconds
Started May 19 01:45:52 PM PDT 24
Finished May 19 01:46:05 PM PDT 24
Peak memory 217716 kb
Host smart-77352dfc-fbc7-494e-b91c-3e09e672d4b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501968835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3501968835
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.450763111
Short name T45
Test name
Test status
Simulation time 612743203 ps
CPU time 7.38 seconds
Started May 19 01:45:54 PM PDT 24
Finished May 19 01:46:02 PM PDT 24
Peak memory 217932 kb
Host smart-52eadd44-79c3-436f-87b2-eca2f702032a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450763111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.450763111
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3309709784
Short name T727
Test name
Test status
Simulation time 80129874 ps
CPU time 1.58 seconds
Started May 19 01:45:50 PM PDT 24
Finished May 19 01:45:54 PM PDT 24
Peak memory 217496 kb
Host smart-2f12f066-5abf-4060-810d-8292d74bf0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309709784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3309709784
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2506377268
Short name T762
Test name
Test status
Simulation time 902707432 ps
CPU time 29.57 seconds
Started May 19 01:45:54 PM PDT 24
Finished May 19 01:46:25 PM PDT 24
Peak memory 246056 kb
Host smart-bed0f3e4-76e4-4601-a6f7-996c62371915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506377268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2506377268
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.1077989456
Short name T554
Test name
Test status
Simulation time 114532904 ps
CPU time 3.44 seconds
Started May 19 01:45:52 PM PDT 24
Finished May 19 01:45:57 PM PDT 24
Peak memory 217792 kb
Host smart-cbca8952-beec-4caf-956b-b80db5b5de4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077989456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.1077989456
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.336464030
Short name T149
Test name
Test status
Simulation time 3548856336 ps
CPU time 162.5 seconds
Started May 19 01:45:56 PM PDT 24
Finished May 19 01:48:40 PM PDT 24
Peak memory 267252 kb
Host smart-e8d57ce0-20ab-425b-9b45-ffcbe854782b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336464030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.336464030
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all_with_rand_reset.1505540223
Short name T127
Test name
Test status
Simulation time 29053969428 ps
CPU time 528.04 seconds
Started May 19 01:45:57 PM PDT 24
Finished May 19 01:54:46 PM PDT 24
Peak memory 300112 kb
Host smart-282cd1c1-f792-43f8-9d98-c5ffd56231d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1505540223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_stress_all_with_rand_reset.1505540223
Directory /workspace/36.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2614613634
Short name T176
Test name
Test status
Simulation time 191332732 ps
CPU time 0.96 seconds
Started May 19 01:45:53 PM PDT 24
Finished May 19 01:45:55 PM PDT 24
Peak memory 211364 kb
Host smart-671466bf-ce63-4f92-ab01-f1084940ad8f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614613634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2614613634
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1800757839
Short name T559
Test name
Test status
Simulation time 33060329 ps
CPU time 0.95 seconds
Started May 19 01:45:55 PM PDT 24
Finished May 19 01:45:57 PM PDT 24
Peak memory 209368 kb
Host smart-9496d922-d531-4cb0-9b22-bed9c00228aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800757839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1800757839
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.3448555986
Short name T514
Test name
Test status
Simulation time 1186925261 ps
CPU time 10.68 seconds
Started May 19 01:45:57 PM PDT 24
Finished May 19 01:46:09 PM PDT 24
Peak memory 217704 kb
Host smart-72a57436-356f-4d39-ad1c-a50b71ad46db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448555986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.3448555986
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1478675172
Short name T606
Test name
Test status
Simulation time 273067181 ps
CPU time 6.92 seconds
Started May 19 01:45:56 PM PDT 24
Finished May 19 01:46:04 PM PDT 24
Peak memory 216804 kb
Host smart-9a778371-f385-4bf1-84c8-10729b11d01d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478675172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1478675172
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.2836934363
Short name T425
Test name
Test status
Simulation time 190422099 ps
CPU time 1.73 seconds
Started May 19 01:45:56 PM PDT 24
Finished May 19 01:45:58 PM PDT 24
Peak memory 217836 kb
Host smart-1190f798-1b1e-4780-87a3-7aed14cd2496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836934363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.2836934363
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2581134508
Short name T731
Test name
Test status
Simulation time 1267332189 ps
CPU time 14.39 seconds
Started May 19 01:45:57 PM PDT 24
Finished May 19 01:46:12 PM PDT 24
Peak memory 225872 kb
Host smart-38f699b0-c145-4c12-9b2a-655f0ea7adde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581134508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2581134508
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.1095319809
Short name T377
Test name
Test status
Simulation time 3048587846 ps
CPU time 9.54 seconds
Started May 19 01:45:57 PM PDT 24
Finished May 19 01:46:07 PM PDT 24
Peak memory 217924 kb
Host smart-0441d86b-0089-4c45-9bf6-fb0b4f1ae964
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095319809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.1095319809
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1081321916
Short name T630
Test name
Test status
Simulation time 3577099506 ps
CPU time 8.74 seconds
Started May 19 01:45:59 PM PDT 24
Finished May 19 01:46:08 PM PDT 24
Peak memory 217940 kb
Host smart-c30dea1d-d048-4908-8e5e-33bc003168cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081321916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1081321916
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3880500806
Short name T576
Test name
Test status
Simulation time 456654478 ps
CPU time 10.04 seconds
Started May 19 01:45:57 PM PDT 24
Finished May 19 01:46:08 PM PDT 24
Peak memory 217772 kb
Host smart-d945ec86-3a2f-4939-a4c5-7d78de081a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880500806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3880500806
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.3907948715
Short name T607
Test name
Test status
Simulation time 172196720 ps
CPU time 2.15 seconds
Started May 19 01:45:55 PM PDT 24
Finished May 19 01:45:58 PM PDT 24
Peak memory 213480 kb
Host smart-0ddfdc70-d119-4ca8-8b55-02a9b04ac4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907948715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3907948715
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.461068256
Short name T350
Test name
Test status
Simulation time 205506996 ps
CPU time 19.98 seconds
Started May 19 01:45:56 PM PDT 24
Finished May 19 01:46:18 PM PDT 24
Peak memory 250696 kb
Host smart-f019518e-89ff-403a-96b4-bceee5720118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461068256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.461068256
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2674696024
Short name T623
Test name
Test status
Simulation time 116613159 ps
CPU time 8.27 seconds
Started May 19 01:45:56 PM PDT 24
Finished May 19 01:46:05 PM PDT 24
Peak memory 250808 kb
Host smart-75f692bb-9f04-498b-adc0-b8a6616f3b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674696024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2674696024
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.4169193381
Short name T763
Test name
Test status
Simulation time 10262763628 ps
CPU time 79.99 seconds
Started May 19 01:45:56 PM PDT 24
Finished May 19 01:47:17 PM PDT 24
Peak memory 249480 kb
Host smart-d9bd49e9-821a-40b3-9659-9f73867bc43c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169193381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.4169193381
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.3554064952
Short name T842
Test name
Test status
Simulation time 13323866 ps
CPU time 0.94 seconds
Started May 19 01:46:00 PM PDT 24
Finished May 19 01:46:01 PM PDT 24
Peak memory 211392 kb
Host smart-d05ef819-8403-4212-9c19-e9c737244f77
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554064952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.3554064952
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.782912622
Short name T468
Test name
Test status
Simulation time 18014067 ps
CPU time 1.13 seconds
Started May 19 01:46:01 PM PDT 24
Finished May 19 01:46:03 PM PDT 24
Peak memory 209328 kb
Host smart-03321103-f0df-4087-936b-50c5910a58b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782912622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.782912622
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1224321009
Short name T715
Test name
Test status
Simulation time 2613267950 ps
CPU time 13.64 seconds
Started May 19 01:46:01 PM PDT 24
Finished May 19 01:46:15 PM PDT 24
Peak memory 218060 kb
Host smart-d8b47103-8e00-4e6d-bdee-e8a3ccd86b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224321009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1224321009
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.2228086635
Short name T463
Test name
Test status
Simulation time 1862066536 ps
CPU time 12.86 seconds
Started May 19 01:45:56 PM PDT 24
Finished May 19 01:46:10 PM PDT 24
Peak memory 209300 kb
Host smart-c3062aad-ff5d-4ca2-b53c-2d22e493efc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228086635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2228086635
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.3774673950
Short name T599
Test name
Test status
Simulation time 157818515 ps
CPU time 2.5 seconds
Started May 19 01:46:01 PM PDT 24
Finished May 19 01:46:04 PM PDT 24
Peak memory 217792 kb
Host smart-46531e15-fa13-4031-966d-cd293b66cdc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774673950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.3774673950
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1861962598
Short name T707
Test name
Test status
Simulation time 293015744 ps
CPU time 14.51 seconds
Started May 19 01:46:04 PM PDT 24
Finished May 19 01:46:20 PM PDT 24
Peak memory 225940 kb
Host smart-cc3d874e-8cfa-42c4-adab-6e908c66e66f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861962598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1861962598
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.817881894
Short name T297
Test name
Test status
Simulation time 1218611114 ps
CPU time 16.66 seconds
Started May 19 01:46:04 PM PDT 24
Finished May 19 01:46:23 PM PDT 24
Peak memory 217788 kb
Host smart-b19e7cde-c756-4543-ae41-0304d4d57e52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817881894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_di
gest.817881894
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.1587935351
Short name T196
Test name
Test status
Simulation time 398366122 ps
CPU time 10.45 seconds
Started May 19 01:45:59 PM PDT 24
Finished May 19 01:46:10 PM PDT 24
Peak memory 217756 kb
Host smart-f434cc8d-ab44-4ce7-8389-bcacf58be20a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587935351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
1587935351
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2177478580
Short name T811
Test name
Test status
Simulation time 654976144 ps
CPU time 8.76 seconds
Started May 19 01:46:00 PM PDT 24
Finished May 19 01:46:09 PM PDT 24
Peak memory 217876 kb
Host smart-ddd3795d-660c-477e-a884-460c0254b011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177478580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2177478580
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2558029886
Short name T198
Test name
Test status
Simulation time 46572957 ps
CPU time 2.05 seconds
Started May 19 01:46:01 PM PDT 24
Finished May 19 01:46:04 PM PDT 24
Peak memory 214088 kb
Host smart-ce196249-5549-4455-98d2-2273b15779a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558029886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2558029886
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.3909053308
Short name T412
Test name
Test status
Simulation time 447952080 ps
CPU time 21.13 seconds
Started May 19 01:46:00 PM PDT 24
Finished May 19 01:46:22 PM PDT 24
Peak memory 250752 kb
Host smart-1c27f44c-dbe8-4a03-8dcb-560abd0f7298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909053308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.3909053308
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.4167363414
Short name T33
Test name
Test status
Simulation time 686741909 ps
CPU time 10.84 seconds
Started May 19 01:46:00 PM PDT 24
Finished May 19 01:46:12 PM PDT 24
Peak memory 250740 kb
Host smart-bda17214-8e08-4e2c-84f7-6f8042ddc581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167363414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.4167363414
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.5043909
Short name T558
Test name
Test status
Simulation time 3472244953 ps
CPU time 111.9 seconds
Started May 19 01:46:01 PM PDT 24
Finished May 19 01:47:54 PM PDT 24
Peak memory 283320 kb
Host smart-75d6ecaa-704c-438a-919e-fcd3984d3428
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5043909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TE
ST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.lc_ctrl_stress_all.5043909
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.442797726
Short name T139
Test name
Test status
Simulation time 84454716657 ps
CPU time 405.59 seconds
Started May 19 01:46:03 PM PDT 24
Finished May 19 01:52:51 PM PDT 24
Peak memory 287736 kb
Host smart-7bcf7b58-d842-467a-b776-354902814e7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=442797726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.442797726
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1076008656
Short name T495
Test name
Test status
Simulation time 11961569 ps
CPU time 0.86 seconds
Started May 19 01:45:59 PM PDT 24
Finished May 19 01:46:01 PM PDT 24
Peak memory 211396 kb
Host smart-39da34ca-a53a-4603-b379-c98dc4fc3a20
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076008656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1076008656
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.1188702722
Short name T207
Test name
Test status
Simulation time 96356097 ps
CPU time 1 seconds
Started May 19 01:46:04 PM PDT 24
Finished May 19 01:46:08 PM PDT 24
Peak memory 209324 kb
Host smart-92946769-7611-4360-898f-7c8fd164a432
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188702722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.1188702722
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.208415289
Short name T429
Test name
Test status
Simulation time 630678451 ps
CPU time 16.19 seconds
Started May 19 01:46:04 PM PDT 24
Finished May 19 01:46:22 PM PDT 24
Peak memory 217848 kb
Host smart-ad27d5ed-9c21-47c3-a2da-ce98b69b5aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208415289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.208415289
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2637718798
Short name T742
Test name
Test status
Simulation time 267544288 ps
CPU time 3.62 seconds
Started May 19 01:46:00 PM PDT 24
Finished May 19 01:46:04 PM PDT 24
Peak memory 216816 kb
Host smart-32a84053-8678-4493-aa1c-c38f9876fbcc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637718798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2637718798
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1250124387
Short name T417
Test name
Test status
Simulation time 628081878 ps
CPU time 4.53 seconds
Started May 19 01:46:04 PM PDT 24
Finished May 19 01:46:10 PM PDT 24
Peak memory 217788 kb
Host smart-36cd8b44-55f9-42f7-ad3a-4f9c3865812e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250124387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1250124387
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.3614935641
Short name T219
Test name
Test status
Simulation time 2236031958 ps
CPU time 13.87 seconds
Started May 19 01:46:06 PM PDT 24
Finished May 19 01:46:22 PM PDT 24
Peak memory 218052 kb
Host smart-464353a8-2605-42ef-abda-6191330c1a8c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614935641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.3614935641
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3864724524
Short name T48
Test name
Test status
Simulation time 356315368 ps
CPU time 10.59 seconds
Started May 19 01:46:01 PM PDT 24
Finished May 19 01:46:12 PM PDT 24
Peak memory 217860 kb
Host smart-f162ecd8-de3d-4824-9367-d195c2450a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864724524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3864724524
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1773256139
Short name T852
Test name
Test status
Simulation time 111978215 ps
CPU time 4.05 seconds
Started May 19 01:46:01 PM PDT 24
Finished May 19 01:46:06 PM PDT 24
Peak memory 217948 kb
Host smart-c9a73387-2236-42ee-a71a-9ce8c554e0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773256139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1773256139
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3133408
Short name T434
Test name
Test status
Simulation time 1113942141 ps
CPU time 30.34 seconds
Started May 19 01:46:02 PM PDT 24
Finished May 19 01:46:33 PM PDT 24
Peak memory 250740 kb
Host smart-20568418-4a44-4e60-8def-69335ffbd535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3133408
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.4248466843
Short name T644
Test name
Test status
Simulation time 70963302 ps
CPU time 2.8 seconds
Started May 19 01:46:03 PM PDT 24
Finished May 19 01:46:08 PM PDT 24
Peak memory 222012 kb
Host smart-375f6e82-569a-4b1d-962d-91af1449f160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248466843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.4248466843
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1998611543
Short name T496
Test name
Test status
Simulation time 41545380344 ps
CPU time 291.9 seconds
Started May 19 01:46:07 PM PDT 24
Finished May 19 01:51:01 PM PDT 24
Peak memory 275716 kb
Host smart-cf78cb0f-5851-4886-8a85-99706bf7dd65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998611543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1998611543
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all_with_rand_reset.359191626
Short name T82
Test name
Test status
Simulation time 7196683446 ps
CPU time 152.24 seconds
Started May 19 01:46:05 PM PDT 24
Finished May 19 01:48:40 PM PDT 24
Peak memory 332720 kb
Host smart-07253512-7ac1-44d4-8065-4af79272eb88
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=359191626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_stress_all_with_rand_reset.359191626
Directory /workspace/39.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.3307178009
Short name T353
Test name
Test status
Simulation time 14187723 ps
CPU time 1.08 seconds
Started May 19 01:46:01 PM PDT 24
Finished May 19 01:46:03 PM PDT 24
Peak memory 211312 kb
Host smart-b5559e8f-e0c7-420f-8f80-5846bef14b75
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307178009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.3307178009
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3718415560
Short name T306
Test name
Test status
Simulation time 22963436 ps
CPU time 1.23 seconds
Started May 19 01:44:15 PM PDT 24
Finished May 19 01:44:17 PM PDT 24
Peak memory 209288 kb
Host smart-9cd3a53e-433e-4649-81f3-f5802b9f1965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718415560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3718415560
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1597305211
Short name T287
Test name
Test status
Simulation time 1262336324 ps
CPU time 13.16 seconds
Started May 19 01:44:09 PM PDT 24
Finished May 19 01:44:23 PM PDT 24
Peak memory 218048 kb
Host smart-7760c18d-8ad1-4a7f-b6e9-06164eb6087d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597305211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1597305211
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3973365473
Short name T656
Test name
Test status
Simulation time 1445752350 ps
CPU time 33.86 seconds
Started May 19 01:44:15 PM PDT 24
Finished May 19 01:44:50 PM PDT 24
Peak memory 217012 kb
Host smart-63ad350f-6637-4f35-9a8c-8c554bdc0b72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973365473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3973365473
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3079240029
Short name T205
Test name
Test status
Simulation time 3725232582 ps
CPU time 56.2 seconds
Started May 19 01:44:15 PM PDT 24
Finished May 19 01:45:12 PM PDT 24
Peak memory 217840 kb
Host smart-5c98319b-1c58-44da-a5cb-d03d19ea8fcc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079240029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3079240029
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3962095029
Short name T735
Test name
Test status
Simulation time 835820141 ps
CPU time 3.91 seconds
Started May 19 01:44:16 PM PDT 24
Finished May 19 01:44:21 PM PDT 24
Peak memory 217052 kb
Host smart-1c2af7aa-8390-4844-9153-4b2edafa1e07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962095029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.3
962095029
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.982064228
Short name T467
Test name
Test status
Simulation time 431676713 ps
CPU time 2.57 seconds
Started May 19 01:44:13 PM PDT 24
Finished May 19 01:44:16 PM PDT 24
Peak memory 217716 kb
Host smart-95b94086-0917-4196-8c06-941d433a7b70
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982064228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_
prog_failure.982064228
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1587264211
Short name T58
Test name
Test status
Simulation time 3062109259 ps
CPU time 20.72 seconds
Started May 19 01:44:13 PM PDT 24
Finished May 19 01:44:34 PM PDT 24
Peak memory 213356 kb
Host smart-42be2550-4e7c-4962-bddb-67a6376bc323
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587264211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.1587264211
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.1685747701
Short name T208
Test name
Test status
Simulation time 486192778 ps
CPU time 1.99 seconds
Started May 19 01:44:16 PM PDT 24
Finished May 19 01:44:18 PM PDT 24
Peak memory 212628 kb
Host smart-8cfd1bc2-f0a3-48a2-9f44-23f412dd6418
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685747701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
1685747701
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1652689825
Short name T399
Test name
Test status
Simulation time 1639104965 ps
CPU time 26.29 seconds
Started May 19 01:44:14 PM PDT 24
Finished May 19 01:44:41 PM PDT 24
Peak memory 250684 kb
Host smart-e7386562-7f2f-4345-a2a5-a9971fbdb63a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652689825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1652689825
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.2588669078
Short name T212
Test name
Test status
Simulation time 593633466 ps
CPU time 9.82 seconds
Started May 19 01:44:16 PM PDT 24
Finished May 19 01:44:26 PM PDT 24
Peak memory 250548 kb
Host smart-5969b9c1-cbb5-4fb4-81c0-bba47db6932b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2588669078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.2588669078
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3674204722
Short name T551
Test name
Test status
Simulation time 72000958 ps
CPU time 3.28 seconds
Started May 19 01:44:13 PM PDT 24
Finished May 19 01:44:16 PM PDT 24
Peak memory 217692 kb
Host smart-65fae85b-b3ca-426f-82ed-82dc0fba0c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674204722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3674204722
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2567594775
Short name T362
Test name
Test status
Simulation time 689395852 ps
CPU time 5.06 seconds
Started May 19 01:44:10 PM PDT 24
Finished May 19 01:44:15 PM PDT 24
Peak memory 213948 kb
Host smart-6079f03b-a0a5-47fc-b7e2-071146fdf2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567594775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2567594775
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.3252640440
Short name T641
Test name
Test status
Simulation time 1769323764 ps
CPU time 14.35 seconds
Started May 19 01:44:20 PM PDT 24
Finished May 19 01:44:35 PM PDT 24
Peak memory 225656 kb
Host smart-6d11356a-23b5-417f-a173-59bf4421b497
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252640440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.3252640440
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1523595463
Short name T714
Test name
Test status
Simulation time 3643489338 ps
CPU time 23.29 seconds
Started May 19 01:44:20 PM PDT 24
Finished May 19 01:44:44 PM PDT 24
Peak memory 218268 kb
Host smart-89857d2c-0815-4f6a-ac94-6a7577d3de56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523595463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1523595463
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1394571290
Short name T703
Test name
Test status
Simulation time 533229586 ps
CPU time 7.49 seconds
Started May 19 01:44:14 PM PDT 24
Finished May 19 01:44:22 PM PDT 24
Peak memory 217772 kb
Host smart-e8ce6c88-5a4d-4c03-9449-af6784a5638f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394571290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
394571290
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1093780607
Short name T390
Test name
Test status
Simulation time 449058540 ps
CPU time 16.45 seconds
Started May 19 01:44:14 PM PDT 24
Finished May 19 01:44:31 PM PDT 24
Peak memory 217844 kb
Host smart-2088fd46-3156-415c-841a-3460f3e1c2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093780607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1093780607
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3714046799
Short name T354
Test name
Test status
Simulation time 1810992612 ps
CPU time 8.1 seconds
Started May 19 01:44:10 PM PDT 24
Finished May 19 01:44:19 PM PDT 24
Peak memory 217984 kb
Host smart-bd5d31e0-4a61-423f-9d76-eab1fa15e8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714046799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3714046799
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3423304508
Short name T293
Test name
Test status
Simulation time 926519271 ps
CPU time 30.65 seconds
Started May 19 01:44:13 PM PDT 24
Finished May 19 01:44:45 PM PDT 24
Peak memory 250636 kb
Host smart-81c76d33-4ec4-451c-9213-1beb541d62bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423304508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3423304508
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.179898496
Short name T261
Test name
Test status
Simulation time 446904463 ps
CPU time 8.72 seconds
Started May 19 01:44:11 PM PDT 24
Finished May 19 01:44:21 PM PDT 24
Peak memory 246224 kb
Host smart-171122e7-b8f3-400f-8d58-a67569dcd9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179898496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.179898496
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.1062364055
Short name T300
Test name
Test status
Simulation time 1537204601 ps
CPU time 60.41 seconds
Started May 19 01:44:20 PM PDT 24
Finished May 19 01:45:21 PM PDT 24
Peak memory 250732 kb
Host smart-a4284ede-3151-4fd4-9550-6144f1bf7229
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062364055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.1062364055
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.530377747
Short name T129
Test name
Test status
Simulation time 21229111938 ps
CPU time 234.03 seconds
Started May 19 01:44:15 PM PDT 24
Finished May 19 01:48:10 PM PDT 24
Peak memory 274100 kb
Host smart-bb43b3fa-6984-415b-b573-6f594873bd39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=530377747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.530377747
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2346996479
Short name T765
Test name
Test status
Simulation time 12675376 ps
CPU time 0.9 seconds
Started May 19 01:44:10 PM PDT 24
Finished May 19 01:44:12 PM PDT 24
Peak memory 211404 kb
Host smart-5b7c14b1-baf7-429d-9dd9-d6048874a44e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346996479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.2346996479
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1396945230
Short name T526
Test name
Test status
Simulation time 37841942 ps
CPU time 1.19 seconds
Started May 19 01:46:04 PM PDT 24
Finished May 19 01:46:07 PM PDT 24
Peak memory 209332 kb
Host smart-8110c03a-2be5-4fe6-b7f6-0808715069e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396945230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1396945230
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2737914335
Short name T670
Test name
Test status
Simulation time 194409841 ps
CPU time 10.98 seconds
Started May 19 01:46:05 PM PDT 24
Finished May 19 01:46:19 PM PDT 24
Peak memory 217872 kb
Host smart-4546359f-781f-44ae-a4bb-69c6f6c74236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737914335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2737914335
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.1967028998
Short name T318
Test name
Test status
Simulation time 175194242 ps
CPU time 1.53 seconds
Started May 19 01:46:07 PM PDT 24
Finished May 19 01:46:10 PM PDT 24
Peak memory 209568 kb
Host smart-eb7da8b1-a9e6-47ab-959b-358781b144fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967028998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.1967028998
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2093959350
Short name T706
Test name
Test status
Simulation time 285529209 ps
CPU time 2.25 seconds
Started May 19 01:46:15 PM PDT 24
Finished May 19 01:46:18 PM PDT 24
Peak memory 217772 kb
Host smart-f560613c-4494-45e3-8a6a-7e51a074a377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093959350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2093959350
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.3537987709
Short name T428
Test name
Test status
Simulation time 1583085712 ps
CPU time 17.05 seconds
Started May 19 01:46:04 PM PDT 24
Finished May 19 01:46:23 PM PDT 24
Peak memory 218724 kb
Host smart-cec8168f-2f8c-4e07-b805-1991dc051389
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537987709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.3537987709
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3437713914
Short name T586
Test name
Test status
Simulation time 430106999 ps
CPU time 10.88 seconds
Started May 19 01:46:07 PM PDT 24
Finished May 19 01:46:19 PM PDT 24
Peak memory 217784 kb
Host smart-8a835677-81d6-4fad-a69e-918219116fe2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437713914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3437713914
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.825434263
Short name T247
Test name
Test status
Simulation time 440254325 ps
CPU time 10.03 seconds
Started May 19 01:46:04 PM PDT 24
Finished May 19 01:46:16 PM PDT 24
Peak memory 217796 kb
Host smart-67f72a00-32b6-4517-a98d-d430541e7c8e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825434263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.825434263
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.4103793854
Short name T757
Test name
Test status
Simulation time 300523145 ps
CPU time 2.98 seconds
Started May 19 01:46:03 PM PDT 24
Finished May 19 01:46:08 PM PDT 24
Peak memory 214440 kb
Host smart-d2924323-6dd0-424a-a43b-af268ce3d428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103793854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.4103793854
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1242372027
Short name T253
Test name
Test status
Simulation time 207502536 ps
CPU time 27.93 seconds
Started May 19 01:46:05 PM PDT 24
Finished May 19 01:46:35 PM PDT 24
Peak memory 250768 kb
Host smart-41559612-975d-4b1a-b507-be54291f0aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242372027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1242372027
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.3000448098
Short name T291
Test name
Test status
Simulation time 46341474 ps
CPU time 3.37 seconds
Started May 19 01:46:06 PM PDT 24
Finished May 19 01:46:11 PM PDT 24
Peak memory 222112 kb
Host smart-a7bd00a9-cae9-4d42-abe5-61426eda5ace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000448098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.3000448098
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3825360906
Short name T543
Test name
Test status
Simulation time 8617495163 ps
CPU time 151.75 seconds
Started May 19 01:46:04 PM PDT 24
Finished May 19 01:48:38 PM PDT 24
Peak memory 316428 kb
Host smart-451369c2-4d11-42f9-83ef-655eb6f2b809
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825360906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3825360906
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.3139799071
Short name T133
Test name
Test status
Simulation time 8515659930 ps
CPU time 275.29 seconds
Started May 19 01:46:04 PM PDT 24
Finished May 19 01:50:41 PM PDT 24
Peak memory 267352 kb
Host smart-c65dd668-2c33-4f06-9e3f-6ab04b8bebc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3139799071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.3139799071
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.3151008641
Short name T431
Test name
Test status
Simulation time 13229772 ps
CPU time 0.88 seconds
Started May 19 01:46:05 PM PDT 24
Finished May 19 01:46:08 PM PDT 24
Peak memory 211428 kb
Host smart-ab5dcfc9-519e-42b7-95eb-8cc08f82acdf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151008641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.3151008641
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.642651607
Short name T375
Test name
Test status
Simulation time 19628164 ps
CPU time 0.91 seconds
Started May 19 01:46:09 PM PDT 24
Finished May 19 01:46:11 PM PDT 24
Peak memory 209336 kb
Host smart-bbef123e-77fb-472f-90c7-dad2eee4bee9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642651607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.642651607
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.571587728
Short name T135
Test name
Test status
Simulation time 522386491 ps
CPU time 13.61 seconds
Started May 19 01:46:05 PM PDT 24
Finished May 19 01:46:21 PM PDT 24
Peak memory 217732 kb
Host smart-b7e141d5-d2f0-463a-a5e9-e9638953ec9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571587728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.571587728
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2602610067
Short name T147
Test name
Test status
Simulation time 88197086 ps
CPU time 2.07 seconds
Started May 19 01:46:12 PM PDT 24
Finished May 19 01:46:14 PM PDT 24
Peak memory 209360 kb
Host smart-25c10002-04c2-41ff-8d88-a51c51d6915c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602610067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2602610067
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.1397911713
Short name T347
Test name
Test status
Simulation time 382900819 ps
CPU time 3.15 seconds
Started May 19 01:46:05 PM PDT 24
Finished May 19 01:46:11 PM PDT 24
Peak memory 217776 kb
Host smart-f06c89e8-7393-48c6-98eb-61dc79ac9216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397911713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.1397911713
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1529781867
Short name T323
Test name
Test status
Simulation time 230739952 ps
CPU time 8.16 seconds
Started May 19 01:46:07 PM PDT 24
Finished May 19 01:46:17 PM PDT 24
Peak memory 225296 kb
Host smart-539c1537-ba93-4d99-a77f-11111f5eb25f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529781867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1529781867
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3685545313
Short name T808
Test name
Test status
Simulation time 7831438088 ps
CPU time 9.12 seconds
Started May 19 01:46:12 PM PDT 24
Finished May 19 01:46:21 PM PDT 24
Peak memory 217900 kb
Host smart-425da665-f292-47bb-99da-07cdec433119
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685545313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.3685545313
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.4094699102
Short name T460
Test name
Test status
Simulation time 717815243 ps
CPU time 18.06 seconds
Started May 19 01:46:11 PM PDT 24
Finished May 19 01:46:30 PM PDT 24
Peak memory 217784 kb
Host smart-b86dba92-d89b-4d5c-b0c7-821d48a475bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094699102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
4094699102
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.598845020
Short name T299
Test name
Test status
Simulation time 1094938870 ps
CPU time 9.06 seconds
Started May 19 01:46:04 PM PDT 24
Finished May 19 01:46:15 PM PDT 24
Peak memory 217908 kb
Host smart-a3952a8e-b884-4d67-9ccb-39559e07d053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598845020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.598845020
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1605065767
Short name T799
Test name
Test status
Simulation time 98194765 ps
CPU time 1.69 seconds
Started May 19 01:46:15 PM PDT 24
Finished May 19 01:46:18 PM PDT 24
Peak memory 213424 kb
Host smart-267187aa-eb24-4c03-adf4-ec9eefa8cb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605065767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1605065767
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.1430087335
Short name T78
Test name
Test status
Simulation time 865121221 ps
CPU time 25.05 seconds
Started May 19 01:46:03 PM PDT 24
Finished May 19 01:46:29 PM PDT 24
Peak memory 250744 kb
Host smart-b32a1462-56d5-4362-9c4d-dbe7dbaea0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430087335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.1430087335
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.1655279317
Short name T789
Test name
Test status
Simulation time 51656040 ps
CPU time 8.86 seconds
Started May 19 01:46:03 PM PDT 24
Finished May 19 01:46:14 PM PDT 24
Peak memory 250776 kb
Host smart-fd04c332-3540-4551-aebe-22499441aa8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655279317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.1655279317
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.2645010609
Short name T866
Test name
Test status
Simulation time 2286961292 ps
CPU time 58.62 seconds
Started May 19 01:46:15 PM PDT 24
Finished May 19 01:47:16 PM PDT 24
Peak memory 267184 kb
Host smart-e2e4346c-00ac-4776-8ca1-3854e7ab447b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645010609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.2645010609
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2729601216
Short name T847
Test name
Test status
Simulation time 27688972 ps
CPU time 1.06 seconds
Started May 19 01:46:06 PM PDT 24
Finished May 19 01:46:10 PM PDT 24
Peak memory 212692 kb
Host smart-28cad1ff-ec69-4818-a5cc-9975d8dd7c2f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729601216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2729601216
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2115812558
Short name T868
Test name
Test status
Simulation time 65404559 ps
CPU time 1.05 seconds
Started May 19 01:46:09 PM PDT 24
Finished May 19 01:46:11 PM PDT 24
Peak memory 209324 kb
Host smart-2299f07b-7500-4e99-a9ea-7b6f2fdcd887
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115812558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2115812558
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3249873319
Short name T388
Test name
Test status
Simulation time 225450141 ps
CPU time 9.41 seconds
Started May 19 01:46:10 PM PDT 24
Finished May 19 01:46:20 PM PDT 24
Peak memory 217776 kb
Host smart-d1c7ca32-aaa2-4e9f-bc57-58a16fefc36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249873319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3249873319
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.87248492
Short name T726
Test name
Test status
Simulation time 2185853958 ps
CPU time 13.64 seconds
Started May 19 01:46:10 PM PDT 24
Finished May 19 01:46:24 PM PDT 24
Peak memory 209400 kb
Host smart-9658af51-6e3f-452c-881c-9e623659a4c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87248492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.87248492
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2590271213
Short name T371
Test name
Test status
Simulation time 342125918 ps
CPU time 3.42 seconds
Started May 19 01:46:16 PM PDT 24
Finished May 19 01:46:21 PM PDT 24
Peak memory 216952 kb
Host smart-240f3d3a-2c29-4d7f-9331-c12fb9c83b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590271213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2590271213
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.2604944876
Short name T724
Test name
Test status
Simulation time 1288931172 ps
CPU time 15.75 seconds
Started May 19 01:46:09 PM PDT 24
Finished May 19 01:46:26 PM PDT 24
Peak memory 218668 kb
Host smart-19267dae-bb8d-4d91-a4aa-6566ad304bc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604944876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2604944876
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1232151555
Short name T245
Test name
Test status
Simulation time 365939815 ps
CPU time 12.05 seconds
Started May 19 01:46:16 PM PDT 24
Finished May 19 01:46:30 PM PDT 24
Peak memory 216972 kb
Host smart-00d79a61-12a0-4c00-8993-0797ae324636
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232151555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1232151555
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.3523144331
Short name T669
Test name
Test status
Simulation time 318539477 ps
CPU time 9.11 seconds
Started May 19 01:46:08 PM PDT 24
Finished May 19 01:46:18 PM PDT 24
Peak memory 217776 kb
Host smart-b8407f97-f62c-40a8-88fc-cbf2eacb0ced
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523144331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
3523144331
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.4192201276
Short name T539
Test name
Test status
Simulation time 187996232 ps
CPU time 6.36 seconds
Started May 19 01:46:11 PM PDT 24
Finished May 19 01:46:18 PM PDT 24
Peak memory 217868 kb
Host smart-aeb9327c-ec96-4b01-a3a9-5a4f8d5297d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192201276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.4192201276
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1152135557
Short name T597
Test name
Test status
Simulation time 473113325 ps
CPU time 2.94 seconds
Started May 19 01:46:08 PM PDT 24
Finished May 19 01:46:12 PM PDT 24
Peak memory 214060 kb
Host smart-1ea82994-3332-419c-843d-e222a863c4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152135557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1152135557
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.2114519559
Short name T801
Test name
Test status
Simulation time 1149698836 ps
CPU time 36.24 seconds
Started May 19 01:46:16 PM PDT 24
Finished May 19 01:46:55 PM PDT 24
Peak memory 250792 kb
Host smart-439c0cd9-0a4f-4c0f-b365-038f43c380c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114519559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.2114519559
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2362155701
Short name T863
Test name
Test status
Simulation time 115782669 ps
CPU time 8.58 seconds
Started May 19 01:46:08 PM PDT 24
Finished May 19 01:46:18 PM PDT 24
Peak memory 250732 kb
Host smart-790d27e6-d2de-4ea4-b615-be934eb704ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362155701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2362155701
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.768936843
Short name T329
Test name
Test status
Simulation time 1291173805 ps
CPU time 50.32 seconds
Started May 19 01:46:08 PM PDT 24
Finished May 19 01:47:00 PM PDT 24
Peak memory 250728 kb
Host smart-8dfeceb1-83ac-4485-9452-e0de4e6f6a14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768936843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.768936843
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1816208823
Short name T283
Test name
Test status
Simulation time 15049936 ps
CPU time 0.94 seconds
Started May 19 01:46:09 PM PDT 24
Finished May 19 01:46:11 PM PDT 24
Peak memory 211456 kb
Host smart-8a200638-8e1d-473c-b4ee-5cb574ad5fe4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816208823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1816208823
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2144260705
Short name T379
Test name
Test status
Simulation time 67930750 ps
CPU time 1.03 seconds
Started May 19 01:46:15 PM PDT 24
Finished May 19 01:46:18 PM PDT 24
Peak memory 209356 kb
Host smart-f11a4ede-8825-49e1-9203-c3508d58f319
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144260705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2144260705
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2107292711
Short name T41
Test name
Test status
Simulation time 280979685 ps
CPU time 10.21 seconds
Started May 19 01:46:14 PM PDT 24
Finished May 19 01:46:25 PM PDT 24
Peak memory 217788 kb
Host smart-4d358272-54bc-4ed9-b490-59047a393dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107292711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2107292711
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.515659798
Short name T490
Test name
Test status
Simulation time 125421872 ps
CPU time 3.82 seconds
Started May 19 01:46:15 PM PDT 24
Finished May 19 01:46:20 PM PDT 24
Peak memory 209348 kb
Host smart-ecaab6fa-db97-454c-aacc-59481feb458d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515659798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.515659798
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.2268423485
Short name T698
Test name
Test status
Simulation time 397238022 ps
CPU time 4.3 seconds
Started May 19 01:46:16 PM PDT 24
Finished May 19 01:46:23 PM PDT 24
Peak memory 217756 kb
Host smart-99f30f3c-af91-4429-91a7-4063e3010983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268423485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.2268423485
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.1618046035
Short name T242
Test name
Test status
Simulation time 234053748 ps
CPU time 9.72 seconds
Started May 19 01:46:16 PM PDT 24
Finished May 19 01:46:27 PM PDT 24
Peak memory 225836 kb
Host smart-6a369b3a-926d-4c31-8152-fcddbf09992c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618046035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.1618046035
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.3725622902
Short name T679
Test name
Test status
Simulation time 1167204682 ps
CPU time 7.57 seconds
Started May 19 01:46:14 PM PDT 24
Finished May 19 01:46:22 PM PDT 24
Peak memory 217820 kb
Host smart-4ae02426-5d24-4922-a1d8-120e9c6b11cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725622902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
3725622902
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.549129557
Short name T335
Test name
Test status
Simulation time 802319789 ps
CPU time 6.08 seconds
Started May 19 01:46:13 PM PDT 24
Finished May 19 01:46:20 PM PDT 24
Peak memory 217780 kb
Host smart-1a00e8a7-ac46-4750-bc3d-f5770d781d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549129557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.549129557
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.2030520729
Short name T252
Test name
Test status
Simulation time 32966464 ps
CPU time 1.55 seconds
Started May 19 01:46:08 PM PDT 24
Finished May 19 01:46:11 PM PDT 24
Peak memory 213436 kb
Host smart-5409169c-e5e7-47e1-98ad-8821468dc75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030520729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.2030520729
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3891902627
Short name T89
Test name
Test status
Simulation time 193816046 ps
CPU time 20.82 seconds
Started May 19 01:46:11 PM PDT 24
Finished May 19 01:46:32 PM PDT 24
Peak memory 250756 kb
Host smart-112536f3-5cff-495c-a92f-367dd7691c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891902627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3891902627
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3407313567
Short name T627
Test name
Test status
Simulation time 97508113 ps
CPU time 6.61 seconds
Started May 19 01:46:09 PM PDT 24
Finished May 19 01:46:16 PM PDT 24
Peak memory 250344 kb
Host smart-6451ba30-07df-4720-acd8-2f752130b23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407313567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3407313567
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.18627044
Short name T723
Test name
Test status
Simulation time 31971854851 ps
CPU time 219.34 seconds
Started May 19 01:46:16 PM PDT 24
Finished May 19 01:49:58 PM PDT 24
Peak memory 250736 kb
Host smart-b8c31df4-e97c-471c-b3dd-6ebdf9989aa0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18627044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
3.lc_ctrl_stress_all.18627044
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.4117838784
Short name T865
Test name
Test status
Simulation time 12072243 ps
CPU time 0.95 seconds
Started May 19 01:46:11 PM PDT 24
Finished May 19 01:46:13 PM PDT 24
Peak memory 211448 kb
Host smart-4e9aa840-a5a4-45c2-a24f-89c627179c4a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117838784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.4117838784
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.34442811
Short name T370
Test name
Test status
Simulation time 32680975 ps
CPU time 1.06 seconds
Started May 19 01:46:15 PM PDT 24
Finished May 19 01:46:18 PM PDT 24
Peak memory 209340 kb
Host smart-12ec8df7-3120-4079-973c-79b1acdefec0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34442811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.34442811
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.3889565888
Short name T91
Test name
Test status
Simulation time 989539219 ps
CPU time 8.01 seconds
Started May 19 01:46:13 PM PDT 24
Finished May 19 01:46:22 PM PDT 24
Peak memory 217804 kb
Host smart-61b467c3-2768-48d0-ad0b-f952dc53c8d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889565888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3889565888
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.2639019675
Short name T564
Test name
Test status
Simulation time 1171382183 ps
CPU time 14.39 seconds
Started May 19 01:46:13 PM PDT 24
Finished May 19 01:46:28 PM PDT 24
Peak memory 209372 kb
Host smart-33d20650-6d5b-4810-8e39-a0ed37241dbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639019675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.2639019675
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3681488592
Short name T854
Test name
Test status
Simulation time 185970483 ps
CPU time 2.66 seconds
Started May 19 01:46:22 PM PDT 24
Finished May 19 01:46:26 PM PDT 24
Peak memory 217876 kb
Host smart-a63df92a-492d-4b4c-952f-75c9b9f6da1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681488592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3681488592
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.3757859451
Short name T768
Test name
Test status
Simulation time 272319735 ps
CPU time 14.01 seconds
Started May 19 01:46:14 PM PDT 24
Finished May 19 01:46:29 PM PDT 24
Peak memory 225820 kb
Host smart-20a7dc88-68d1-48ac-a6bb-560fa55b80d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757859451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.3757859451
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.2110305868
Short name T296
Test name
Test status
Simulation time 811013297 ps
CPU time 18.15 seconds
Started May 19 01:46:16 PM PDT 24
Finished May 19 01:46:36 PM PDT 24
Peak memory 217768 kb
Host smart-47723f89-a0dd-4dd3-979b-d7d6efcfe3a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110305868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.2110305868
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1730098191
Short name T688
Test name
Test status
Simulation time 1459919541 ps
CPU time 8.48 seconds
Started May 19 01:46:14 PM PDT 24
Finished May 19 01:46:23 PM PDT 24
Peak memory 217732 kb
Host smart-afc39dc9-ade9-4ffa-9e5b-fd54758c9c7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730098191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1730098191
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.850765945
Short name T780
Test name
Test status
Simulation time 540882310 ps
CPU time 8.69 seconds
Started May 19 01:46:15 PM PDT 24
Finished May 19 01:46:26 PM PDT 24
Peak memory 217848 kb
Host smart-2eb80689-6e18-433e-8ab7-263fdc690b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850765945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.850765945
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2688281670
Short name T782
Test name
Test status
Simulation time 47962145 ps
CPU time 2.2 seconds
Started May 19 01:46:16 PM PDT 24
Finished May 19 01:46:20 PM PDT 24
Peak memory 213896 kb
Host smart-a8820fe2-ca44-43fd-8528-b02e216bf687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688281670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2688281670
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1472218100
Short name T493
Test name
Test status
Simulation time 1216791834 ps
CPU time 23.81 seconds
Started May 19 01:46:12 PM PDT 24
Finished May 19 01:46:36 PM PDT 24
Peak memory 250712 kb
Host smart-d6f58c44-10a8-430e-8c92-9597302ca3e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472218100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1472218100
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3098293454
Short name T10
Test name
Test status
Simulation time 115898780 ps
CPU time 3.58 seconds
Started May 19 01:46:16 PM PDT 24
Finished May 19 01:46:22 PM PDT 24
Peak memory 222668 kb
Host smart-38eda229-9295-4d08-8a91-dbd9859e1afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098293454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3098293454
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2605929595
Short name T575
Test name
Test status
Simulation time 16587303095 ps
CPU time 248.55 seconds
Started May 19 01:46:12 PM PDT 24
Finished May 19 01:50:21 PM PDT 24
Peak memory 275448 kb
Host smart-f1fc66fb-2b9b-4da1-a271-de6d1b2d3594
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605929595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2605929595
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.3043884699
Short name T331
Test name
Test status
Simulation time 41275705 ps
CPU time 0.86 seconds
Started May 19 01:46:12 PM PDT 24
Finished May 19 01:46:13 PM PDT 24
Peak memory 211392 kb
Host smart-0a2c69ec-5222-41c2-b7b5-54d65780626c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043884699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.3043884699
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.812860038
Short name T784
Test name
Test status
Simulation time 26528384 ps
CPU time 0.84 seconds
Started May 19 01:46:17 PM PDT 24
Finished May 19 01:46:20 PM PDT 24
Peak memory 209268 kb
Host smart-6fde7a4f-33ca-4877-ae72-d9f6dcbdd106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812860038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.812860038
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.2445678662
Short name T445
Test name
Test status
Simulation time 299786790 ps
CPU time 14.88 seconds
Started May 19 01:46:15 PM PDT 24
Finished May 19 01:46:32 PM PDT 24
Peak memory 217920 kb
Host smart-a4bda820-791d-4257-ba13-4770e5a13c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445678662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.2445678662
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1758930239
Short name T740
Test name
Test status
Simulation time 512987686 ps
CPU time 6.78 seconds
Started May 19 01:46:12 PM PDT 24
Finished May 19 01:46:20 PM PDT 24
Peak memory 216812 kb
Host smart-44bd62f6-da8d-4597-a5dc-d09a766d0b6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758930239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1758930239
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2522635613
Short name T18
Test name
Test status
Simulation time 315943206 ps
CPU time 2.99 seconds
Started May 19 01:46:13 PM PDT 24
Finished May 19 01:46:16 PM PDT 24
Peak memory 217772 kb
Host smart-a1863b45-6e20-47d2-95b0-95431ac737b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522635613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2522635613
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2082254104
Short name T292
Test name
Test status
Simulation time 748641944 ps
CPU time 13.28 seconds
Started May 19 01:46:19 PM PDT 24
Finished May 19 01:46:33 PM PDT 24
Peak memory 225536 kb
Host smart-e045080a-66ed-4e22-ae09-679f0848e140
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082254104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2082254104
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.497954062
Short name T486
Test name
Test status
Simulation time 1597381079 ps
CPU time 14.47 seconds
Started May 19 01:46:18 PM PDT 24
Finished May 19 01:46:34 PM PDT 24
Peak memory 217776 kb
Host smart-644a0a2d-a4cc-45a9-937b-4b439525fb69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497954062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.497954062
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2537538375
Short name T53
Test name
Test status
Simulation time 384961950 ps
CPU time 8.96 seconds
Started May 19 01:46:24 PM PDT 24
Finished May 19 01:46:34 PM PDT 24
Peak memory 217824 kb
Host smart-7c8699b0-b65f-43f6-ae3e-5c4eb0753884
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537538375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2537538375
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3675764517
Short name T582
Test name
Test status
Simulation time 1116246111 ps
CPU time 8.69 seconds
Started May 19 01:46:15 PM PDT 24
Finished May 19 01:46:26 PM PDT 24
Peak memory 217804 kb
Host smart-658c17aa-e570-49a6-b50f-4c4dc9aa33ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675764517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3675764517
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.459365487
Short name T305
Test name
Test status
Simulation time 53211162 ps
CPU time 1.61 seconds
Started May 19 01:46:13 PM PDT 24
Finished May 19 01:46:15 PM PDT 24
Peak memory 213552 kb
Host smart-8306983c-c79c-4e20-bcc7-dc26a8d40652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459365487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.459365487
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.1497980257
Short name T484
Test name
Test status
Simulation time 136940495 ps
CPU time 19.58 seconds
Started May 19 01:46:22 PM PDT 24
Finished May 19 01:46:43 PM PDT 24
Peak memory 250756 kb
Host smart-fa470d17-c930-41a1-9be0-39ffe6749361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497980257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.1497980257
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.778696032
Short name T776
Test name
Test status
Simulation time 544300977 ps
CPU time 2.93 seconds
Started May 19 01:46:22 PM PDT 24
Finished May 19 01:46:26 PM PDT 24
Peak memory 222308 kb
Host smart-7e9c3570-522e-4a76-993a-5882f5509825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778696032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.778696032
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1074215566
Short name T864
Test name
Test status
Simulation time 3704324522 ps
CPU time 20.02 seconds
Started May 19 01:46:22 PM PDT 24
Finished May 19 01:46:43 PM PDT 24
Peak memory 225976 kb
Host smart-660f7339-c112-4193-b8b7-6c303031f313
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074215566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1074215566
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all_with_rand_reset.393027775
Short name T649
Test name
Test status
Simulation time 77118897217 ps
CPU time 1070.46 seconds
Started May 19 01:46:24 PM PDT 24
Finished May 19 02:04:16 PM PDT 24
Peak memory 513044 kb
Host smart-8ff0fba7-1a84-4332-a290-64f177d34d1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=393027775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_stress_all_with_rand_reset.393027775
Directory /workspace/45.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.4124242060
Short name T278
Test name
Test status
Simulation time 14701802 ps
CPU time 0.91 seconds
Started May 19 01:46:14 PM PDT 24
Finished May 19 01:46:15 PM PDT 24
Peak memory 211332 kb
Host smart-9ad8810c-21bf-4dd0-959d-f9148b1bf167
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124242060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.4124242060
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.284443479
Short name T861
Test name
Test status
Simulation time 43026134 ps
CPU time 1.15 seconds
Started May 19 01:46:17 PM PDT 24
Finished May 19 01:46:20 PM PDT 24
Peak memory 209284 kb
Host smart-6f7398d8-ffd0-4eab-b851-f7f01b8aff2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284443479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.284443479
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3355233542
Short name T535
Test name
Test status
Simulation time 561999674 ps
CPU time 15.42 seconds
Started May 19 01:46:17 PM PDT 24
Finished May 19 01:46:34 PM PDT 24
Peak memory 218116 kb
Host smart-6e9fcde5-ad19-43e6-b2ea-74ada71c2e72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355233542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3355233542
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3938326189
Short name T360
Test name
Test status
Simulation time 389471651 ps
CPU time 3.89 seconds
Started May 19 01:46:18 PM PDT 24
Finished May 19 01:46:23 PM PDT 24
Peak memory 217692 kb
Host smart-67be71b5-3431-4887-bc1f-213822727971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938326189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3938326189
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.390780160
Short name T319
Test name
Test status
Simulation time 405538846 ps
CPU time 10.48 seconds
Started May 19 01:46:24 PM PDT 24
Finished May 19 01:46:36 PM PDT 24
Peak memory 217836 kb
Host smart-fde9131c-3908-4423-8b4d-a1f6dab5ea96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390780160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.390780160
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.185586688
Short name T433
Test name
Test status
Simulation time 969644164 ps
CPU time 8.41 seconds
Started May 19 01:46:18 PM PDT 24
Finished May 19 01:46:28 PM PDT 24
Peak memory 225856 kb
Host smart-58b2661a-bca1-4e78-8d42-8950dea5844b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185586688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di
gest.185586688
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3891948454
Short name T609
Test name
Test status
Simulation time 1967360742 ps
CPU time 16.24 seconds
Started May 19 01:46:25 PM PDT 24
Finished May 19 01:46:42 PM PDT 24
Peak memory 217764 kb
Host smart-598b7b56-f849-4bfb-8463-479398f86c4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891948454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3891948454
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1537045563
Short name T369
Test name
Test status
Simulation time 342337133 ps
CPU time 9.3 seconds
Started May 19 01:46:17 PM PDT 24
Finished May 19 01:46:29 PM PDT 24
Peak memory 217916 kb
Host smart-7ea161e1-f14f-4427-a149-8027c6f5e25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537045563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1537045563
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1064515450
Short name T438
Test name
Test status
Simulation time 30483262 ps
CPU time 2.22 seconds
Started May 19 01:46:19 PM PDT 24
Finished May 19 01:46:22 PM PDT 24
Peak memory 213780 kb
Host smart-7788bc26-5a2b-46f9-bf4d-d9dad86ab24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064515450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1064515450
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1968186473
Short name T303
Test name
Test status
Simulation time 1439818360 ps
CPU time 33 seconds
Started May 19 01:46:18 PM PDT 24
Finished May 19 01:46:53 PM PDT 24
Peak memory 250720 kb
Host smart-35b23ce1-a0b9-4d99-8072-9e5595b864ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968186473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1968186473
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2109323074
Short name T142
Test name
Test status
Simulation time 400844019 ps
CPU time 7.68 seconds
Started May 19 01:46:17 PM PDT 24
Finished May 19 01:46:27 PM PDT 24
Peak memory 248344 kb
Host smart-4b161fd1-757a-4cab-af92-169a86fab7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109323074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2109323074
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1065912527
Short name T244
Test name
Test status
Simulation time 19685684095 ps
CPU time 133.88 seconds
Started May 19 01:46:22 PM PDT 24
Finished May 19 01:48:37 PM PDT 24
Peak memory 282876 kb
Host smart-f46bcf46-659d-483d-8d10-9ac84c239071
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065912527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1065912527
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.4107586213
Short name T590
Test name
Test status
Simulation time 25468588 ps
CPU time 0.89 seconds
Started May 19 01:46:25 PM PDT 24
Finished May 19 01:46:27 PM PDT 24
Peak memory 211468 kb
Host smart-5e7096d1-404a-4816-9149-b4682090ca31
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107586213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.4107586213
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.402315513
Short name T497
Test name
Test status
Simulation time 62811557 ps
CPU time 0.88 seconds
Started May 19 01:46:28 PM PDT 24
Finished May 19 01:46:30 PM PDT 24
Peak memory 209316 kb
Host smart-99a7d88d-bbdf-4f5a-9b07-c1bca77a90ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402315513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.402315513
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.3854617847
Short name T14
Test name
Test status
Simulation time 248409062 ps
CPU time 11.96 seconds
Started May 19 01:46:23 PM PDT 24
Finished May 19 01:46:36 PM PDT 24
Peak memory 217832 kb
Host smart-c046d291-461c-407c-992f-0a4a64f8e595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854617847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.3854617847
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.3781004974
Short name T458
Test name
Test status
Simulation time 1264363420 ps
CPU time 4.57 seconds
Started May 19 01:46:25 PM PDT 24
Finished May 19 01:46:30 PM PDT 24
Peak memory 209452 kb
Host smart-5ef20fe8-1e78-4c99-8ccf-7d797ef09ffb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781004974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.3781004974
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.502973276
Short name T290
Test name
Test status
Simulation time 51407376 ps
CPU time 3 seconds
Started May 19 01:46:26 PM PDT 24
Finished May 19 01:46:30 PM PDT 24
Peak memory 217752 kb
Host smart-b476407e-7c3e-483b-ade2-d598c650da34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502973276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.502973276
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.2958916592
Short name T512
Test name
Test status
Simulation time 1261368896 ps
CPU time 12 seconds
Started May 19 01:46:22 PM PDT 24
Finished May 19 01:46:35 PM PDT 24
Peak memory 218720 kb
Host smart-9bab0215-a36f-4f52-ad3d-e92a4fc8f747
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958916592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.2958916592
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.2078361088
Short name T449
Test name
Test status
Simulation time 390786354 ps
CPU time 14.8 seconds
Started May 19 01:46:29 PM PDT 24
Finished May 19 01:46:45 PM PDT 24
Peak memory 217780 kb
Host smart-ccbe1696-503d-472a-8e6e-4b36abb8498c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078361088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.2078361088
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1409189673
Short name T234
Test name
Test status
Simulation time 1673083734 ps
CPU time 9.99 seconds
Started May 19 01:46:24 PM PDT 24
Finished May 19 01:46:34 PM PDT 24
Peak memory 217824 kb
Host smart-c68e564a-b15a-47a6-957d-f67903ab999a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409189673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1409189673
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3225225916
Short name T349
Test name
Test status
Simulation time 1586599789 ps
CPU time 7.92 seconds
Started May 19 01:46:24 PM PDT 24
Finished May 19 01:46:33 PM PDT 24
Peak memory 217944 kb
Host smart-e82e7e08-beac-42ca-a287-8f3e2ca84269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225225916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3225225916
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1176940722
Short name T367
Test name
Test status
Simulation time 188020869 ps
CPU time 3.01 seconds
Started May 19 01:46:22 PM PDT 24
Finished May 19 01:46:26 PM PDT 24
Peak memory 214020 kb
Host smart-8c0a8363-1498-49ff-beb6-3d5eb27f6e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176940722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1176940722
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1106022437
Short name T215
Test name
Test status
Simulation time 1106236502 ps
CPU time 32.2 seconds
Started May 19 01:46:25 PM PDT 24
Finished May 19 01:46:58 PM PDT 24
Peak memory 250804 kb
Host smart-0e5fa51b-f0ef-4ad2-a8db-f7e7e03d7ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106022437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1106022437
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.1951750055
Short name T378
Test name
Test status
Simulation time 494335056 ps
CPU time 7.42 seconds
Started May 19 01:46:30 PM PDT 24
Finished May 19 01:46:39 PM PDT 24
Peak memory 250756 kb
Host smart-6d20de0d-255f-449c-94c0-e7d8e65a49b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951750055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.1951750055
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2586860027
Short name T619
Test name
Test status
Simulation time 31939352275 ps
CPU time 125.81 seconds
Started May 19 01:46:23 PM PDT 24
Finished May 19 01:48:30 PM PDT 24
Peak memory 259060 kb
Host smart-96e6c84e-d822-4b68-a15d-232d04eb303d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586860027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2586860027
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1833208379
Short name T86
Test name
Test status
Simulation time 36680419 ps
CPU time 0.94 seconds
Started May 19 01:46:24 PM PDT 24
Finished May 19 01:46:26 PM PDT 24
Peak memory 211444 kb
Host smart-acf98b2f-c6a8-4593-a5b5-51e75d55f581
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833208379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1833208379
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.2154921980
Short name T653
Test name
Test status
Simulation time 1432623766 ps
CPU time 11.67 seconds
Started May 19 01:46:23 PM PDT 24
Finished May 19 01:46:35 PM PDT 24
Peak memory 218000 kb
Host smart-13dbc477-476b-47e7-a5ea-f3194b0b4c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154921980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.2154921980
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.1117274180
Short name T439
Test name
Test status
Simulation time 442128825 ps
CPU time 11.64 seconds
Started May 19 01:46:25 PM PDT 24
Finished May 19 01:46:38 PM PDT 24
Peak memory 209380 kb
Host smart-70a9e706-e57b-4285-8bde-ffb2a6871e76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117274180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.1117274180
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2851837568
Short name T565
Test name
Test status
Simulation time 74692293 ps
CPU time 3.96 seconds
Started May 19 01:46:23 PM PDT 24
Finished May 19 01:46:28 PM PDT 24
Peak memory 217720 kb
Host smart-2c31cea8-7983-4277-ae65-e87e4ddb5a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851837568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2851837568
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.2838622983
Short name T699
Test name
Test status
Simulation time 1579801443 ps
CPU time 12.08 seconds
Started May 19 01:46:23 PM PDT 24
Finished May 19 01:46:36 PM PDT 24
Peak memory 225860 kb
Host smart-a043c1cc-468d-47c1-b173-996d51338ebf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838622983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.2838622983
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.4227992013
Short name T829
Test name
Test status
Simulation time 6065498212 ps
CPU time 13.64 seconds
Started May 19 01:46:25 PM PDT 24
Finished May 19 01:46:39 PM PDT 24
Peak memory 217900 kb
Host smart-1db66166-7a42-4703-9ccf-b4a7bc1daa2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227992013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.4227992013
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.132825564
Short name T694
Test name
Test status
Simulation time 521233446 ps
CPU time 10.19 seconds
Started May 19 01:46:22 PM PDT 24
Finished May 19 01:46:33 PM PDT 24
Peak memory 217816 kb
Host smart-07af1a7b-3f2b-4c65-96d5-ef22535ff29e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132825564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.132825564
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2021473371
Short name T828
Test name
Test status
Simulation time 729967069 ps
CPU time 6.6 seconds
Started May 19 01:46:27 PM PDT 24
Finished May 19 01:46:34 PM PDT 24
Peak memory 217856 kb
Host smart-9cd35545-c304-4e17-9e6c-5fb0303ea4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021473371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2021473371
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3411483154
Short name T612
Test name
Test status
Simulation time 1086128100 ps
CPU time 5.57 seconds
Started May 19 01:46:30 PM PDT 24
Finished May 19 01:46:37 PM PDT 24
Peak memory 217552 kb
Host smart-f16cb8cc-e95d-4b0d-93d3-c76b7d8d9125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411483154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3411483154
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1072421543
Short name T361
Test name
Test status
Simulation time 943215905 ps
CPU time 27.67 seconds
Started May 19 01:46:25 PM PDT 24
Finished May 19 01:46:54 PM PDT 24
Peak memory 250764 kb
Host smart-3dc64763-e616-4251-9abc-1984fbc1db64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072421543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1072421543
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3776628808
Short name T610
Test name
Test status
Simulation time 132221675 ps
CPU time 8.59 seconds
Started May 19 01:46:23 PM PDT 24
Finished May 19 01:46:33 PM PDT 24
Peak memory 250744 kb
Host smart-c06cc429-73a1-489f-aefb-50e8cbf9f5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776628808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3776628808
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.1412707314
Short name T673
Test name
Test status
Simulation time 44944034645 ps
CPU time 186.94 seconds
Started May 19 01:46:29 PM PDT 24
Finished May 19 01:49:38 PM PDT 24
Peak memory 258920 kb
Host smart-9e874ff0-65f9-4159-a47f-eb384c400622
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412707314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.1412707314
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.2062514185
Short name T795
Test name
Test status
Simulation time 7859882673 ps
CPU time 161.9 seconds
Started May 19 01:46:27 PM PDT 24
Finished May 19 01:49:10 PM PDT 24
Peak memory 268904 kb
Host smart-7a47cc44-b90a-436a-988b-e51f5f059767
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2062514185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.2062514185
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.4214411461
Short name T280
Test name
Test status
Simulation time 40632892 ps
CPU time 0.93 seconds
Started May 19 01:46:22 PM PDT 24
Finished May 19 01:46:24 PM PDT 24
Peak memory 211504 kb
Host smart-ff50b07f-8586-4b65-a456-e819e4321ae1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214411461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.4214411461
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.2225447881
Short name T327
Test name
Test status
Simulation time 33039924 ps
CPU time 1.15 seconds
Started May 19 01:46:31 PM PDT 24
Finished May 19 01:46:33 PM PDT 24
Peak memory 209364 kb
Host smart-33f83f0c-6316-413f-9e47-da7f6df8ebd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225447881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.2225447881
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.3335855742
Short name T771
Test name
Test status
Simulation time 501805269 ps
CPU time 10.86 seconds
Started May 19 01:46:27 PM PDT 24
Finished May 19 01:46:39 PM PDT 24
Peak memory 217828 kb
Host smart-0c56859b-db1e-4fa5-a81a-0609645c1c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335855742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.3335855742
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.2521827355
Short name T150
Test name
Test status
Simulation time 669245383 ps
CPU time 15.52 seconds
Started May 19 01:46:28 PM PDT 24
Finished May 19 01:46:44 PM PDT 24
Peak memory 209356 kb
Host smart-331038e6-0a9f-4a1d-9ccf-46b3c8460461
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521827355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.2521827355
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2476357144
Short name T527
Test name
Test status
Simulation time 505655481 ps
CPU time 5.5 seconds
Started May 19 01:46:29 PM PDT 24
Finished May 19 01:46:36 PM PDT 24
Peak memory 217756 kb
Host smart-4c9378bf-a48e-486f-9369-fd6decf2dd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476357144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2476357144
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.17408578
Short name T712
Test name
Test status
Simulation time 353851697 ps
CPU time 12.37 seconds
Started May 19 01:46:26 PM PDT 24
Finished May 19 01:46:39 PM PDT 24
Peak memory 225912 kb
Host smart-176ecc01-3a48-4f01-88be-dc36f48b526d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17408578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.17408578
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1246840961
Short name T488
Test name
Test status
Simulation time 6493722148 ps
CPU time 19 seconds
Started May 19 01:46:30 PM PDT 24
Finished May 19 01:46:51 PM PDT 24
Peak memory 217900 kb
Host smart-dbad1cde-4a98-46e6-bce9-0ba504b851cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246840961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1246840961
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.3512457908
Short name T626
Test name
Test status
Simulation time 189811963 ps
CPU time 8.71 seconds
Started May 19 01:46:28 PM PDT 24
Finished May 19 01:46:38 PM PDT 24
Peak memory 217788 kb
Host smart-41130874-b0ee-456a-8665-1302f420f3b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512457908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
3512457908
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1237236308
Short name T70
Test name
Test status
Simulation time 515275082 ps
CPU time 2.8 seconds
Started May 19 01:46:27 PM PDT 24
Finished May 19 01:46:30 PM PDT 24
Peak memory 217580 kb
Host smart-5f12543a-d0a1-462e-ba3b-b692c34130d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237236308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1237236308
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.798257564
Short name T286
Test name
Test status
Simulation time 279447568 ps
CPU time 22.43 seconds
Started May 19 01:46:27 PM PDT 24
Finished May 19 01:46:51 PM PDT 24
Peak memory 250744 kb
Host smart-3b9cdb59-bd72-486c-8f3a-bef7010e9b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798257564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.798257564
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.2799397165
Short name T465
Test name
Test status
Simulation time 90383250 ps
CPU time 7.18 seconds
Started May 19 01:46:27 PM PDT 24
Finished May 19 01:46:35 PM PDT 24
Peak memory 250240 kb
Host smart-4b7a75e6-c674-4744-9ee5-0b582c46b205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799397165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2799397165
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.453817461
Short name T642
Test name
Test status
Simulation time 8408447627 ps
CPU time 71.34 seconds
Started May 19 01:46:29 PM PDT 24
Finished May 19 01:47:42 PM PDT 24
Peak memory 250804 kb
Host smart-f4ebc055-e8ac-4ed5-a078-d2df0b8b1210
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453817461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.453817461
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.845364867
Short name T40
Test name
Test status
Simulation time 31176619018 ps
CPU time 612.31 seconds
Started May 19 01:46:29 PM PDT 24
Finished May 19 01:56:43 PM PDT 24
Peak memory 282604 kb
Host smart-d5bfc9d7-0905-4ba8-9629-c573a092b39f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=845364867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.845364867
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3995928118
Short name T437
Test name
Test status
Simulation time 66442350 ps
CPU time 1.14 seconds
Started May 19 01:46:29 PM PDT 24
Finished May 19 01:46:31 PM PDT 24
Peak memory 212872 kb
Host smart-aed31c64-cb21-4146-acd4-9224af1a9147
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995928118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3995928118
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1421304069
Short name T772
Test name
Test status
Simulation time 31069024 ps
CPU time 1.1 seconds
Started May 19 01:44:20 PM PDT 24
Finished May 19 01:44:23 PM PDT 24
Peak memory 209352 kb
Host smart-df1e5932-7535-4a74-9109-1f4da9879432
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421304069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1421304069
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2255973706
Short name T322
Test name
Test status
Simulation time 11036777 ps
CPU time 0.98 seconds
Started May 19 01:44:20 PM PDT 24
Finished May 19 01:44:22 PM PDT 24
Peak memory 209368 kb
Host smart-53123287-0273-4ac7-98ae-699ffe3a0e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255973706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2255973706
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.3402184996
Short name T193
Test name
Test status
Simulation time 287006900 ps
CPU time 10.64 seconds
Started May 19 01:44:22 PM PDT 24
Finished May 19 01:44:35 PM PDT 24
Peak memory 217852 kb
Host smart-af6e3153-5fd4-478d-a942-2e1079143851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402184996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3402184996
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2863811977
Short name T702
Test name
Test status
Simulation time 71538288 ps
CPU time 1.51 seconds
Started May 19 01:44:19 PM PDT 24
Finished May 19 01:44:21 PM PDT 24
Peak memory 209336 kb
Host smart-4a521087-e2c3-4d75-91b2-3babed762f3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863811977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2863811977
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.267315101
Short name T326
Test name
Test status
Simulation time 4985013651 ps
CPU time 20.77 seconds
Started May 19 01:44:22 PM PDT 24
Finished May 19 01:44:45 PM PDT 24
Peak memory 217896 kb
Host smart-8a08b4ad-e35d-445b-86e4-ed39591c848c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267315101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.267315101
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2963294350
Short name T60
Test name
Test status
Simulation time 190011425 ps
CPU time 2.94 seconds
Started May 19 01:44:23 PM PDT 24
Finished May 19 01:44:27 PM PDT 24
Peak memory 217004 kb
Host smart-502285f3-580a-49f0-9df6-5f2021f2a48f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963294350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
963294350
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.155683431
Short name T595
Test name
Test status
Simulation time 956913848 ps
CPU time 5.09 seconds
Started May 19 01:44:20 PM PDT 24
Finished May 19 01:44:26 PM PDT 24
Peak memory 217708 kb
Host smart-423d1f02-2dcc-4633-8423-ba50cc7134ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155683431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
prog_failure.155683431
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1794743447
Short name T617
Test name
Test status
Simulation time 4175359550 ps
CPU time 30.56 seconds
Started May 19 01:44:21 PM PDT 24
Finished May 19 01:44:53 PM PDT 24
Peak memory 213964 kb
Host smart-55e4bbe4-d963-4304-8a1e-5a0cb8fc1d38
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794743447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1794743447
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1297888237
Short name T61
Test name
Test status
Simulation time 642039923 ps
CPU time 2.56 seconds
Started May 19 01:44:22 PM PDT 24
Finished May 19 01:44:27 PM PDT 24
Peak memory 212644 kb
Host smart-7bfbb9a6-687c-40cf-a02a-3b26ac5783e3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297888237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1297888237
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3508823107
Short name T227
Test name
Test status
Simulation time 4901530141 ps
CPU time 84.13 seconds
Started May 19 01:44:22 PM PDT 24
Finished May 19 01:45:48 PM PDT 24
Peak memory 275388 kb
Host smart-6eda9f5c-4e75-4f42-8289-4084eb135ac1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508823107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3508823107
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.3938833075
Short name T214
Test name
Test status
Simulation time 428272754 ps
CPU time 11.98 seconds
Started May 19 01:44:21 PM PDT 24
Finished May 19 01:44:35 PM PDT 24
Peak memory 245604 kb
Host smart-1775c773-0019-4393-b481-b8f336c82242
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938833075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.3938833075
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3836183983
Short name T631
Test name
Test status
Simulation time 68500917 ps
CPU time 2.65 seconds
Started May 19 01:44:21 PM PDT 24
Finished May 19 01:44:25 PM PDT 24
Peak memory 217940 kb
Host smart-4b6ed0d5-5646-4c1f-9de3-9f2ef376efd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836183983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3836183983
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1636841954
Short name T849
Test name
Test status
Simulation time 3793484649 ps
CPU time 11.35 seconds
Started May 19 01:44:22 PM PDT 24
Finished May 19 01:44:35 PM PDT 24
Peak memory 217684 kb
Host smart-3d7e796d-db4e-4413-97c3-76c5eba80b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636841954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1636841954
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.4072039341
Short name T659
Test name
Test status
Simulation time 1208009329 ps
CPU time 16.35 seconds
Started May 19 01:44:19 PM PDT 24
Finished May 19 01:44:37 PM PDT 24
Peak memory 218816 kb
Host smart-1577bf39-d221-46a0-8c40-451871617a3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072039341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.4072039341
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3440791079
Short name T340
Test name
Test status
Simulation time 1821425589 ps
CPU time 10.26 seconds
Started May 19 01:44:22 PM PDT 24
Finished May 19 01:44:34 PM PDT 24
Peak memory 217776 kb
Host smart-e5c0834e-e0f0-49c5-9852-afed19dcc273
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440791079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3440791079
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1167848715
Short name T572
Test name
Test status
Simulation time 181301574 ps
CPU time 7.24 seconds
Started May 19 01:44:22 PM PDT 24
Finished May 19 01:44:31 PM PDT 24
Peak memory 217844 kb
Host smart-e8c0b366-0bcd-45e9-8685-cf17280f5144
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167848715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
167848715
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.2807065730
Short name T381
Test name
Test status
Simulation time 472416136 ps
CPU time 12.25 seconds
Started May 19 01:44:20 PM PDT 24
Finished May 19 01:44:34 PM PDT 24
Peak memory 217860 kb
Host smart-5dbc3319-341a-4613-80c7-616489157f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807065730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.2807065730
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2295761875
Short name T749
Test name
Test status
Simulation time 27846879 ps
CPU time 2.29 seconds
Started May 19 01:44:21 PM PDT 24
Finished May 19 01:44:24 PM PDT 24
Peak memory 213984 kb
Host smart-09a29fb2-fabf-4357-b1e2-d3754323dc81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295761875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2295761875
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.2188886448
Short name T867
Test name
Test status
Simulation time 618680521 ps
CPU time 29.11 seconds
Started May 19 01:44:19 PM PDT 24
Finished May 19 01:44:49 PM PDT 24
Peak memory 250744 kb
Host smart-1078201a-7f2a-490a-b422-e023c74be4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188886448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2188886448
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1340153501
Short name T392
Test name
Test status
Simulation time 106465512 ps
CPU time 6.63 seconds
Started May 19 01:44:21 PM PDT 24
Finished May 19 01:44:30 PM PDT 24
Peak memory 248236 kb
Host smart-d99a0068-c59d-46b7-9eb8-f7381a382be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340153501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1340153501
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.950819537
Short name T411
Test name
Test status
Simulation time 21543570383 ps
CPU time 212.27 seconds
Started May 19 01:44:22 PM PDT 24
Finished May 19 01:47:56 PM PDT 24
Peak memory 276236 kb
Host smart-6e3a7ad5-bb70-4adf-986a-a2b5ef0df4c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950819537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.950819537
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.661587426
Short name T583
Test name
Test status
Simulation time 43410210 ps
CPU time 1.02 seconds
Started May 19 01:44:21 PM PDT 24
Finished May 19 01:44:24 PM PDT 24
Peak memory 211448 kb
Host smart-93d6983d-661d-4f74-9d5e-4e56173ef8e4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661587426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctr
l_volatile_unlock_smoke.661587426
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1060729330
Short name T769
Test name
Test status
Simulation time 26988800 ps
CPU time 0.91 seconds
Started May 19 01:44:37 PM PDT 24
Finished May 19 01:44:40 PM PDT 24
Peak memory 209324 kb
Host smart-4b19193c-c26a-4040-a7d1-de8dbd9f9fd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060729330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1060729330
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.32438258
Short name T846
Test name
Test status
Simulation time 111681804 ps
CPU time 0.9 seconds
Started May 19 01:44:19 PM PDT 24
Finished May 19 01:44:21 PM PDT 24
Peak memory 209364 kb
Host smart-d4b881c1-87a0-4925-b41e-85c527c25244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32438258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.32438258
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.214540159
Short name T416
Test name
Test status
Simulation time 2763164434 ps
CPU time 11.32 seconds
Started May 19 01:44:24 PM PDT 24
Finished May 19 01:44:36 PM PDT 24
Peak memory 217916 kb
Host smart-c9a53191-250d-4805-9075-a1fe58f9ff3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214540159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.214540159
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2365503092
Short name T151
Test name
Test status
Simulation time 811811415 ps
CPU time 19.57 seconds
Started May 19 01:44:35 PM PDT 24
Finished May 19 01:44:56 PM PDT 24
Peak memory 217040 kb
Host smart-a50112ad-f473-443b-929c-7291685ea583
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365503092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2365503092
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2453237682
Short name T508
Test name
Test status
Simulation time 6986422253 ps
CPU time 92.71 seconds
Started May 19 01:44:21 PM PDT 24
Finished May 19 01:45:55 PM PDT 24
Peak memory 219572 kb
Host smart-7c196447-66fc-43fe-b456-c6ec712e45bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453237682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2453237682
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.4246677183
Short name T709
Test name
Test status
Simulation time 588251162 ps
CPU time 4.67 seconds
Started May 19 01:44:36 PM PDT 24
Finished May 19 01:44:43 PM PDT 24
Peak memory 217576 kb
Host smart-0e80d826-c086-4d5f-af8b-2ac3c4bbac3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246677183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.4
246677183
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2531052132
Short name T690
Test name
Test status
Simulation time 217886533 ps
CPU time 5.38 seconds
Started May 19 01:44:22 PM PDT 24
Finished May 19 01:44:30 PM PDT 24
Peak memory 217640 kb
Host smart-99712009-9f31-4ffb-a21c-4f4b83c3f56e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531052132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2531052132
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.2789894231
Short name T562
Test name
Test status
Simulation time 1369404219 ps
CPU time 14.05 seconds
Started May 19 01:44:34 PM PDT 24
Finished May 19 01:44:48 PM PDT 24
Peak memory 212928 kb
Host smart-5aa15e8a-079e-4bc5-8f0c-de35d8c066b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789894231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.2789894231
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3844595615
Short name T62
Test name
Test status
Simulation time 1157725603 ps
CPU time 4.55 seconds
Started May 19 01:44:20 PM PDT 24
Finished May 19 01:44:25 PM PDT 24
Peak memory 213072 kb
Host smart-fe9c885a-e4ad-46e2-9364-3c464c77c542
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844595615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3844595615
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2074039709
Short name T285
Test name
Test status
Simulation time 11342529371 ps
CPU time 46.57 seconds
Started May 19 01:44:22 PM PDT 24
Finished May 19 01:45:10 PM PDT 24
Peak memory 251044 kb
Host smart-a05390f1-bfd9-4ba2-9459-39aecadfb484
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074039709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2074039709
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2011167898
Short name T747
Test name
Test status
Simulation time 745689550 ps
CPU time 15.69 seconds
Started May 19 01:44:23 PM PDT 24
Finished May 19 01:44:40 PM PDT 24
Peak memory 247184 kb
Host smart-fc9bd974-eb3c-4b05-9c4d-21326b4772e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011167898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2011167898
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.2561436187
Short name T232
Test name
Test status
Simulation time 45379115 ps
CPU time 2.73 seconds
Started May 19 01:44:20 PM PDT 24
Finished May 19 01:44:23 PM PDT 24
Peak memory 217732 kb
Host smart-a55927f0-8fc9-40e5-8b35-bbffdda90119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561436187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.2561436187
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3847591276
Short name T172
Test name
Test status
Simulation time 360001719 ps
CPU time 13.23 seconds
Started May 19 01:44:23 PM PDT 24
Finished May 19 01:44:38 PM PDT 24
Peak memory 217728 kb
Host smart-60ff3b7b-e4ed-4632-893b-a3f6a27b4b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847591276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3847591276
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.4178161361
Short name T276
Test name
Test status
Simulation time 686934122 ps
CPU time 14.39 seconds
Started May 19 01:44:35 PM PDT 24
Finished May 19 01:44:52 PM PDT 24
Peak memory 218744 kb
Host smart-69c2382a-c40c-4950-8340-16efc0648f11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178161361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.4178161361
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.839964572
Short name T803
Test name
Test status
Simulation time 708505285 ps
CPU time 7.14 seconds
Started May 19 01:44:35 PM PDT 24
Finished May 19 01:44:44 PM PDT 24
Peak memory 217740 kb
Host smart-3ea84744-a1f0-4f31-b949-e23187a68f7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839964572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dig
est.839964572
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1387058551
Short name T373
Test name
Test status
Simulation time 390419343 ps
CPU time 11.09 seconds
Started May 19 01:44:34 PM PDT 24
Finished May 19 01:44:46 PM PDT 24
Peak memory 217804 kb
Host smart-4ae8a786-9b6f-45ef-aaf1-d19836686d83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387058551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
387058551
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.1854894019
Short name T49
Test name
Test status
Simulation time 376250131 ps
CPU time 8.39 seconds
Started May 19 01:44:20 PM PDT 24
Finished May 19 01:44:30 PM PDT 24
Peak memory 218116 kb
Host smart-b50251fd-fcae-4fe3-8709-43d5289ec687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854894019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.1854894019
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1570829216
Short name T334
Test name
Test status
Simulation time 271359466 ps
CPU time 3.05 seconds
Started May 19 01:44:20 PM PDT 24
Finished May 19 01:44:23 PM PDT 24
Peak memory 214620 kb
Host smart-81567aef-918f-4c25-861a-ff00d1c79b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570829216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1570829216
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3049434954
Short name T683
Test name
Test status
Simulation time 287638734 ps
CPU time 29.27 seconds
Started May 19 01:44:25 PM PDT 24
Finished May 19 01:44:56 PM PDT 24
Peak memory 250704 kb
Host smart-4647f870-93c6-4c41-827a-b5da174bae64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049434954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3049434954
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.4230876244
Short name T621
Test name
Test status
Simulation time 50142787 ps
CPU time 7.58 seconds
Started May 19 01:44:22 PM PDT 24
Finished May 19 01:44:31 PM PDT 24
Peak memory 250740 kb
Host smart-3bd5b851-7242-4b5b-81cb-874376e37206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230876244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.4230876244
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1498487685
Short name T797
Test name
Test status
Simulation time 8139945328 ps
CPU time 71.23 seconds
Started May 19 01:44:24 PM PDT 24
Finished May 19 01:45:37 PM PDT 24
Peak memory 225924 kb
Host smart-76bdc9b6-e646-4732-afe7-93efb9faf930
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498487685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1498487685
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.694956037
Short name T671
Test name
Test status
Simulation time 46467154 ps
CPU time 0.87 seconds
Started May 19 01:44:23 PM PDT 24
Finished May 19 01:44:25 PM PDT 24
Peak memory 212616 kb
Host smart-b4806c4b-0596-491b-b37a-86d7a4c92d71
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694956037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctr
l_volatile_unlock_smoke.694956037
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2682221900
Short name T447
Test name
Test status
Simulation time 103015106 ps
CPU time 0.9 seconds
Started May 19 01:44:37 PM PDT 24
Finished May 19 01:44:41 PM PDT 24
Peak memory 209336 kb
Host smart-0f7ac05d-ff9f-47b0-9c5e-d4cd9ec7251e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682221900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2682221900
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.821515274
Short name T328
Test name
Test status
Simulation time 16825897 ps
CPU time 0.9 seconds
Started May 19 01:44:26 PM PDT 24
Finished May 19 01:44:29 PM PDT 24
Peak memory 209224 kb
Host smart-a96e8744-15fc-4854-8f31-f2404514ce03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821515274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.821515274
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.2864072629
Short name T693
Test name
Test status
Simulation time 268652573 ps
CPU time 12.68 seconds
Started May 19 01:44:26 PM PDT 24
Finished May 19 01:44:40 PM PDT 24
Peak memory 217824 kb
Host smart-1047fec8-f509-4fc4-8435-ed958d25b367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864072629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.2864072629
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3241578132
Short name T24
Test name
Test status
Simulation time 2142823265 ps
CPU time 9.52 seconds
Started May 19 01:44:37 PM PDT 24
Finished May 19 01:44:49 PM PDT 24
Peak memory 209348 kb
Host smart-49de3719-a785-42a6-8e6c-3ebdbfc0a29c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241578132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3241578132
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.4062907630
Short name T180
Test name
Test status
Simulation time 18436477691 ps
CPU time 53 seconds
Started May 19 01:44:38 PM PDT 24
Finished May 19 01:45:34 PM PDT 24
Peak memory 218388 kb
Host smart-6a99dd4c-5a01-429a-95e2-c0a7fc16dccf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062907630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.4062907630
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1730283896
Short name T845
Test name
Test status
Simulation time 76610231 ps
CPU time 2.75 seconds
Started May 19 01:44:25 PM PDT 24
Finished May 19 01:44:29 PM PDT 24
Peak memory 216876 kb
Host smart-d06d0b08-b331-4f7f-bcee-fc14376c900a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730283896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
730283896
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.3680747517
Short name T476
Test name
Test status
Simulation time 2874545315 ps
CPU time 6.56 seconds
Started May 19 01:44:37 PM PDT 24
Finished May 19 01:44:46 PM PDT 24
Peak memory 217812 kb
Host smart-51621d88-39d2-49b5-8667-2783e6519463
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680747517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.3680747517
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2932247887
Short name T66
Test name
Test status
Simulation time 3713279946 ps
CPU time 28.05 seconds
Started May 19 01:44:39 PM PDT 24
Finished May 19 01:45:10 PM PDT 24
Peak memory 213768 kb
Host smart-3c3880d9-94df-49f5-baa5-5908159533fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932247887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2932247887
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2392136165
Short name T692
Test name
Test status
Simulation time 647264610 ps
CPU time 12.1 seconds
Started May 19 01:44:36 PM PDT 24
Finished May 19 01:44:50 PM PDT 24
Peak memory 213376 kb
Host smart-69de9197-e6ab-49fa-aa41-de9e52cce300
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392136165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2392136165
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.3776412307
Short name T705
Test name
Test status
Simulation time 2242895875 ps
CPU time 27.76 seconds
Started May 19 01:44:25 PM PDT 24
Finished May 19 01:44:54 PM PDT 24
Peak memory 250724 kb
Host smart-5e74bc7c-083d-42d0-a0f7-94495c548c66
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776412307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.3776412307
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2451605752
Short name T423
Test name
Test status
Simulation time 2769733552 ps
CPU time 20.93 seconds
Started May 19 01:44:26 PM PDT 24
Finished May 19 01:44:49 PM PDT 24
Peak memory 223196 kb
Host smart-ba82d4c6-2e51-40fb-80d1-3593c174accd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451605752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2451605752
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.745256760
Short name T453
Test name
Test status
Simulation time 155635118 ps
CPU time 2.51 seconds
Started May 19 01:44:38 PM PDT 24
Finished May 19 01:44:44 PM PDT 24
Peak memory 217836 kb
Host smart-a2b6d49e-f1b0-4668-8913-8af0e66b5747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745256760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.745256760
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3962799008
Short name T616
Test name
Test status
Simulation time 392290408 ps
CPU time 21.59 seconds
Started May 19 01:44:38 PM PDT 24
Finished May 19 01:45:03 PM PDT 24
Peak memory 214328 kb
Host smart-d32c59ae-a0c4-456f-8729-dab262c28c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962799008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3962799008
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.724137369
Short name T374
Test name
Test status
Simulation time 295259333 ps
CPU time 8.82 seconds
Started May 19 01:44:36 PM PDT 24
Finished May 19 01:44:48 PM PDT 24
Peak memory 225912 kb
Host smart-9b17171e-1505-4bda-9513-a5fb3b8d6da6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724137369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.724137369
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.485085868
Short name T531
Test name
Test status
Simulation time 348861434 ps
CPU time 11.47 seconds
Started May 19 01:44:26 PM PDT 24
Finished May 19 01:44:39 PM PDT 24
Peak memory 217708 kb
Host smart-757ec846-0551-45d6-b142-5cca07daa32d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485085868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_dig
est.485085868
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1312190239
Short name T500
Test name
Test status
Simulation time 2504473923 ps
CPU time 11.39 seconds
Started May 19 01:44:26 PM PDT 24
Finished May 19 01:44:39 PM PDT 24
Peak memory 217852 kb
Host smart-7b148091-5d7b-4ee7-9dbd-34100e65aa06
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312190239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
312190239
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.1704582149
Short name T713
Test name
Test status
Simulation time 2319905832 ps
CPU time 9.87 seconds
Started May 19 01:44:35 PM PDT 24
Finished May 19 01:44:47 PM PDT 24
Peak memory 217904 kb
Host smart-49616deb-0e99-4647-b458-649b4018332a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704582149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.1704582149
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.4015553783
Short name T589
Test name
Test status
Simulation time 157236697 ps
CPU time 2.75 seconds
Started May 19 01:44:27 PM PDT 24
Finished May 19 01:44:31 PM PDT 24
Peak memory 214376 kb
Host smart-5b9c582e-13ad-4bbe-9537-582f9dc0f1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015553783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.4015553783
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.1481520942
Short name T695
Test name
Test status
Simulation time 312399079 ps
CPU time 36.75 seconds
Started May 19 01:44:23 PM PDT 24
Finished May 19 01:45:01 PM PDT 24
Peak memory 250792 kb
Host smart-7b5f8520-02c3-478c-bfb1-3f2436d9b704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481520942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.1481520942
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.4178906549
Short name T719
Test name
Test status
Simulation time 82667630 ps
CPU time 6.79 seconds
Started May 19 01:44:35 PM PDT 24
Finished May 19 01:44:44 PM PDT 24
Peak memory 250296 kb
Host smart-c09812fb-0acf-4bb8-8df2-a93c712a4603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178906549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.4178906549
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.337995263
Short name T605
Test name
Test status
Simulation time 3553907416 ps
CPU time 32 seconds
Started May 19 01:44:36 PM PDT 24
Finished May 19 01:45:10 PM PDT 24
Peak memory 250896 kb
Host smart-e70abcdd-1bdf-4ec0-b18b-cba0bded465f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337995263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.337995263
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1686668161
Short name T264
Test name
Test status
Simulation time 15287221 ps
CPU time 0.95 seconds
Started May 19 01:44:26 PM PDT 24
Finished May 19 01:44:28 PM PDT 24
Peak memory 211496 kb
Host smart-1ee8f93d-dcbc-43d5-921b-9b483b983f4d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686668161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1686668161
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2141792432
Short name T478
Test name
Test status
Simulation time 15790375 ps
CPU time 1.07 seconds
Started May 19 01:44:39 PM PDT 24
Finished May 19 01:44:43 PM PDT 24
Peak memory 209368 kb
Host smart-2dda0c23-6a57-414c-8d74-0e284c987526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141792432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2141792432
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1648769329
Short name T69
Test name
Test status
Simulation time 25498091 ps
CPU time 0.9 seconds
Started May 19 01:44:38 PM PDT 24
Finished May 19 01:44:42 PM PDT 24
Peak memory 209324 kb
Host smart-9290411a-b9e0-4fff-8523-197e23ed2ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648769329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1648769329
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.3886707388
Short name T211
Test name
Test status
Simulation time 683765066 ps
CPU time 12.55 seconds
Started May 19 01:44:39 PM PDT 24
Finished May 19 01:44:55 PM PDT 24
Peak memory 217752 kb
Host smart-11f306f0-55c6-4f4d-8c3c-7ffe0731d569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886707388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.3886707388
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3954640895
Short name T145
Test name
Test status
Simulation time 379873729 ps
CPU time 3 seconds
Started May 19 01:44:39 PM PDT 24
Finished May 19 01:44:45 PM PDT 24
Peak memory 209320 kb
Host smart-c3c08224-a706-47d1-a122-f73bca6ad50c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954640895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3954640895
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1455141732
Short name T474
Test name
Test status
Simulation time 1305597737 ps
CPU time 38.46 seconds
Started May 19 01:44:39 PM PDT 24
Finished May 19 01:45:21 PM PDT 24
Peak memory 217628 kb
Host smart-654825de-fb44-4f92-b12a-7bdf6de56869
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455141732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1455141732
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.1395181206
Short name T708
Test name
Test status
Simulation time 679313984 ps
CPU time 4.81 seconds
Started May 19 01:44:39 PM PDT 24
Finished May 19 01:44:48 PM PDT 24
Peak memory 217104 kb
Host smart-c6206d11-fa6d-48b5-9064-81ec158769d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395181206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.1
395181206
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.455119736
Short name T544
Test name
Test status
Simulation time 7558982185 ps
CPU time 15.7 seconds
Started May 19 01:44:40 PM PDT 24
Finished May 19 01:44:59 PM PDT 24
Peak memory 217884 kb
Host smart-28ddc8a6-e0ae-4218-bad3-98e1fe80d102
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455119736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.455119736
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3717094672
Short name T624
Test name
Test status
Simulation time 962878867 ps
CPU time 26.76 seconds
Started May 19 01:44:37 PM PDT 24
Finished May 19 01:45:07 PM PDT 24
Peak memory 213116 kb
Host smart-0e311a73-060f-46e3-a081-32e09708b6ed
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717094672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3717094672
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2127051081
Short name T487
Test name
Test status
Simulation time 2563150361 ps
CPU time 15.67 seconds
Started May 19 01:44:37 PM PDT 24
Finished May 19 01:44:55 PM PDT 24
Peak memory 213956 kb
Host smart-1c23e58c-075f-4c9e-b4c0-27eb03c1e3fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127051081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2127051081
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.4007620284
Short name T410
Test name
Test status
Simulation time 1633085637 ps
CPU time 31.95 seconds
Started May 19 01:44:38 PM PDT 24
Finished May 19 01:45:13 PM PDT 24
Peak memory 250704 kb
Host smart-49684cc3-b30d-430e-b13f-983f065ceda1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007620284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.4007620284
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.1189272540
Short name T221
Test name
Test status
Simulation time 1742750372 ps
CPU time 11.06 seconds
Started May 19 01:44:38 PM PDT 24
Finished May 19 01:44:52 PM PDT 24
Peak memory 249828 kb
Host smart-59284226-c3ae-49bf-ad5e-db7228dd18b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189272540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.1189272540
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1588185418
Short name T206
Test name
Test status
Simulation time 69484812 ps
CPU time 3.26 seconds
Started May 19 01:44:40 PM PDT 24
Finished May 19 01:44:46 PM PDT 24
Peak memory 217780 kb
Host smart-db1e6fd3-77f2-40f8-a96d-975001005d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588185418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1588185418
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2671415248
Short name T277
Test name
Test status
Simulation time 219243794 ps
CPU time 5.28 seconds
Started May 19 01:44:28 PM PDT 24
Finished May 19 01:44:34 PM PDT 24
Peak memory 213384 kb
Host smart-77d7e4c3-3dd1-4431-9848-16375168bc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671415248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2671415248
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.1197810867
Short name T556
Test name
Test status
Simulation time 1962963688 ps
CPU time 10.12 seconds
Started May 19 01:44:40 PM PDT 24
Finished May 19 01:44:54 PM PDT 24
Peak memory 225860 kb
Host smart-3e720f73-b857-46a8-a628-133130b6fc20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197810867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.1197810867
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2484348839
Short name T485
Test name
Test status
Simulation time 922908813 ps
CPU time 9.64 seconds
Started May 19 01:44:39 PM PDT 24
Finished May 19 01:44:52 PM PDT 24
Peak memory 217756 kb
Host smart-c89e119e-6b7a-4dc1-bdc2-0bc2065b50b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484348839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2484348839
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.198290787
Short name T681
Test name
Test status
Simulation time 2320594394 ps
CPU time 6.54 seconds
Started May 19 01:44:36 PM PDT 24
Finished May 19 01:44:45 PM PDT 24
Peak memory 217860 kb
Host smart-47b880ef-1d16-41aa-b656-022e308dcb63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198290787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.198290787
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.3992408432
Short name T482
Test name
Test status
Simulation time 982141652 ps
CPU time 7.83 seconds
Started May 19 01:44:39 PM PDT 24
Finished May 19 01:44:50 PM PDT 24
Peak memory 217748 kb
Host smart-fcd95ae1-b73d-4531-90d9-ec894c571d38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992408432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.3992408432
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3630687224
Short name T75
Test name
Test status
Simulation time 31341495 ps
CPU time 1.05 seconds
Started May 19 01:44:26 PM PDT 24
Finished May 19 01:44:29 PM PDT 24
Peak memory 211772 kb
Host smart-2f400e13-cdf0-4177-91c7-c0f43fadec1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630687224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3630687224
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3643542271
Short name T560
Test name
Test status
Simulation time 595338141 ps
CPU time 26.98 seconds
Started May 19 01:44:39 PM PDT 24
Finished May 19 01:45:09 PM PDT 24
Peak memory 250656 kb
Host smart-831c8ffa-7fe0-4b22-b9ca-45c00f9f4140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643542271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3643542271
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.632837536
Short name T141
Test name
Test status
Simulation time 87321579 ps
CPU time 6.99 seconds
Started May 19 01:44:26 PM PDT 24
Finished May 19 01:44:35 PM PDT 24
Peak memory 249888 kb
Host smart-6e008bc8-4164-4f9f-b5fb-31f088f02232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632837536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.632837536
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3338952228
Short name T477
Test name
Test status
Simulation time 3490213572 ps
CPU time 75.35 seconds
Started May 19 01:44:37 PM PDT 24
Finished May 19 01:45:54 PM PDT 24
Peak memory 248960 kb
Host smart-7400cc97-85c5-44b7-99f1-c07ce5544f22
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338952228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3338952228
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3081204100
Short name T804
Test name
Test status
Simulation time 37371685752 ps
CPU time 1529.94 seconds
Started May 19 01:44:30 PM PDT 24
Finished May 19 02:10:01 PM PDT 24
Peak memory 333096 kb
Host smart-65a41927-022d-4b93-96cd-925342d8b7d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3081204100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3081204100
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.292810038
Short name T342
Test name
Test status
Simulation time 56030211 ps
CPU time 1.03 seconds
Started May 19 01:44:24 PM PDT 24
Finished May 19 01:44:27 PM PDT 24
Peak memory 212464 kb
Host smart-5010026c-915f-4535-9054-0e62f326b9b5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292810038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctr
l_volatile_unlock_smoke.292810038
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.4288350606
Short name T279
Test name
Test status
Simulation time 90468073 ps
CPU time 0.92 seconds
Started May 19 01:44:37 PM PDT 24
Finished May 19 01:44:40 PM PDT 24
Peak memory 209352 kb
Host smart-54a38784-7dbb-45e3-be7a-ee4912bc76d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288350606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.4288350606
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.1543601778
Short name T573
Test name
Test status
Simulation time 13348728 ps
CPU time 0.99 seconds
Started May 19 01:44:36 PM PDT 24
Finished May 19 01:44:39 PM PDT 24
Peak memory 209576 kb
Host smart-4829a1d5-6db5-404a-9dc4-70ba846d3835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543601778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.1543601778
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.2890543723
Short name T38
Test name
Test status
Simulation time 2667288665 ps
CPU time 12.56 seconds
Started May 19 01:44:39 PM PDT 24
Finished May 19 01:44:55 PM PDT 24
Peak memory 218012 kb
Host smart-83d5b85b-6d2f-45aa-82a4-54713d897e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890543723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2890543723
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.3135219578
Short name T383
Test name
Test status
Simulation time 1449563653 ps
CPU time 8.77 seconds
Started May 19 01:44:37 PM PDT 24
Finished May 19 01:44:48 PM PDT 24
Peak memory 216984 kb
Host smart-994add47-e93b-493b-8a31-f6b36a4f59a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135219578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.3135219578
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3909800560
Short name T516
Test name
Test status
Simulation time 1824385883 ps
CPU time 29.95 seconds
Started May 19 01:44:37 PM PDT 24
Finished May 19 01:45:09 PM PDT 24
Peak memory 217640 kb
Host smart-fadf4fa7-d87b-49a9-9634-bdb5bc43ea9f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909800560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3909800560
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.3136109839
Short name T825
Test name
Test status
Simulation time 1428866407 ps
CPU time 2.3 seconds
Started May 19 01:44:46 PM PDT 24
Finished May 19 01:44:50 PM PDT 24
Peak memory 216884 kb
Host smart-30c6784c-deb4-48d3-be57-331ea3325a6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136109839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.3
136109839
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.4185539697
Short name T336
Test name
Test status
Simulation time 703008116 ps
CPU time 2.62 seconds
Started May 19 01:44:41 PM PDT 24
Finished May 19 01:44:47 PM PDT 24
Peak memory 217692 kb
Host smart-6fbb0858-0519-4f24-93e9-a0b302ae743b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185539697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.4185539697
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3785458048
Short name T870
Test name
Test status
Simulation time 5021920495 ps
CPU time 12.8 seconds
Started May 19 01:44:38 PM PDT 24
Finished May 19 01:44:55 PM PDT 24
Peak memory 213556 kb
Host smart-955283e9-b400-4668-86e8-e0de44a5c0ba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785458048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3785458048
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1402771752
Short name T608
Test name
Test status
Simulation time 163632662 ps
CPU time 4.58 seconds
Started May 19 01:44:39 PM PDT 24
Finished May 19 01:44:47 PM PDT 24
Peak memory 212764 kb
Host smart-9a8bccd0-943e-4292-82eb-6c046508c5ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402771752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1402771752
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.339982325
Short name T618
Test name
Test status
Simulation time 20051455761 ps
CPU time 65.84 seconds
Started May 19 01:44:46 PM PDT 24
Finished May 19 01:45:53 PM PDT 24
Peak memory 283572 kb
Host smart-9fdd0950-e764-40ac-a8f6-947f32b8975b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339982325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_state_failure.339982325
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.3743007427
Short name T743
Test name
Test status
Simulation time 447857369 ps
CPU time 13.58 seconds
Started May 19 01:44:30 PM PDT 24
Finished May 19 01:44:44 PM PDT 24
Peak memory 250568 kb
Host smart-12aa6053-959f-4551-a14f-7c9ed6aaf942
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743007427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.3743007427
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.4051417291
Short name T444
Test name
Test status
Simulation time 20699220 ps
CPU time 1.54 seconds
Started May 19 01:44:43 PM PDT 24
Finished May 19 01:44:47 PM PDT 24
Peak memory 217784 kb
Host smart-00282c36-61e3-4b28-806f-8ed73919d8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051417291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.4051417291
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.3795065909
Short name T152
Test name
Test status
Simulation time 238474515 ps
CPU time 8.87 seconds
Started May 19 01:44:36 PM PDT 24
Finished May 19 01:44:47 PM PDT 24
Peak memory 213528 kb
Host smart-632fef99-fc12-49ff-b833-a02fddbc5734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795065909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.3795065909
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.1569863313
Short name T239
Test name
Test status
Simulation time 350089529 ps
CPU time 15.32 seconds
Started May 19 01:44:41 PM PDT 24
Finished May 19 01:44:59 PM PDT 24
Peak memory 225864 kb
Host smart-31da1f50-1a68-432e-9600-774f0a027858
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569863313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.1569863313
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3973314780
Short name T548
Test name
Test status
Simulation time 294176730 ps
CPU time 12.41 seconds
Started May 19 01:44:38 PM PDT 24
Finished May 19 01:44:53 PM PDT 24
Peak memory 217800 kb
Host smart-bc3c1933-9884-401d-8f9b-eef9ae74bee8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973314780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3973314780
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.770508110
Short name T363
Test name
Test status
Simulation time 228649543 ps
CPU time 7.54 seconds
Started May 19 01:44:41 PM PDT 24
Finished May 19 01:44:52 PM PDT 24
Peak memory 217764 kb
Host smart-bf8a6d6b-3790-4854-a493-4dfa7c980efb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770508110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.770508110
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2494811333
Short name T87
Test name
Test status
Simulation time 1382623156 ps
CPU time 7.58 seconds
Started May 19 01:44:42 PM PDT 24
Finished May 19 01:44:52 PM PDT 24
Peak memory 217820 kb
Host smart-de196bba-a176-4a18-9eb8-be5347a0b5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494811333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2494811333
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.294227776
Short name T691
Test name
Test status
Simulation time 174948951 ps
CPU time 2.38 seconds
Started May 19 01:44:38 PM PDT 24
Finished May 19 01:44:44 PM PDT 24
Peak memory 214020 kb
Host smart-cc0ef401-9e82-4883-81c6-dc86f90e5b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294227776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.294227776
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3180019295
Short name T79
Test name
Test status
Simulation time 272358989 ps
CPU time 17.73 seconds
Started May 19 01:44:36 PM PDT 24
Finished May 19 01:44:55 PM PDT 24
Peak memory 250732 kb
Host smart-9b9041e1-910b-4405-9745-d6fdedd9d76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180019295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3180019295
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.2629799362
Short name T736
Test name
Test status
Simulation time 167626728 ps
CPU time 8.24 seconds
Started May 19 01:44:39 PM PDT 24
Finished May 19 01:44:50 PM PDT 24
Peak memory 247448 kb
Host smart-b901e9df-c94c-4074-98d2-ec55ce8e9e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629799362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.2629799362
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.4081322427
Short name T229
Test name
Test status
Simulation time 1219488149 ps
CPU time 11.08 seconds
Started May 19 01:44:47 PM PDT 24
Finished May 19 01:44:59 PM PDT 24
Peak memory 243244 kb
Host smart-a16463b1-68b0-4548-8ee7-55372d92b523
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081322427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.4081322427
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3178860566
Short name T666
Test name
Test status
Simulation time 20506733 ps
CPU time 0.93 seconds
Started May 19 01:44:41 PM PDT 24
Finished May 19 01:44:45 PM PDT 24
Peak memory 211364 kb
Host smart-ce97cba8-d4c5-4193-938e-9e4c3c97fa9d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178860566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3178860566
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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