Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55799 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[1] |
2001 |
1 |
|
|
T14 |
11 |
|
T5 |
14 |
|
T6 |
7 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57059 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[1] |
741 |
1 |
|
|
T56 |
11 |
|
T57 |
9 |
|
T58 |
12 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55710 |
1 |
|
|
T1 |
68 |
|
T2 |
20 |
|
T3 |
49 |
auto[1] |
2090 |
1 |
|
|
T1 |
10 |
|
T3 |
5 |
|
T5 |
59 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55695 |
1 |
|
|
T1 |
71 |
|
T2 |
20 |
|
T3 |
51 |
auto[1] |
2105 |
1 |
|
|
T1 |
7 |
|
T3 |
3 |
|
T5 |
50 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55655 |
1 |
|
|
T1 |
68 |
|
T2 |
20 |
|
T3 |
49 |
auto[1] |
2145 |
1 |
|
|
T1 |
10 |
|
T3 |
5 |
|
T5 |
42 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
52480 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
no_err_inj |
5320 |
1 |
|
|
T10 |
9 |
|
T5 |
58 |
|
T35 |
14 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55763 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[1] |
2037 |
1 |
|
|
T14 |
4 |
|
T5 |
5 |
|
T6 |
14 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57068 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[1] |
732 |
1 |
|
|
T56 |
10 |
|
T57 |
16 |
|
T58 |
9 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
40030 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[1] |
17770 |
1 |
|
|
T5 |
222 |
|
T6 |
70 |
|
T22 |
8 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55727 |
1 |
|
|
T1 |
71 |
|
T2 |
20 |
|
T3 |
47 |
auto[1] |
2073 |
1 |
|
|
T1 |
7 |
|
T3 |
7 |
|
T5 |
52 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55672 |
1 |
|
|
T1 |
67 |
|
T2 |
20 |
|
T3 |
48 |
auto[1] |
2128 |
1 |
|
|
T1 |
11 |
|
T3 |
6 |
|
T5 |
59 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55650 |
1 |
|
|
T1 |
71 |
|
T2 |
20 |
|
T3 |
48 |
auto[1] |
2150 |
1 |
|
|
T1 |
7 |
|
T3 |
6 |
|
T5 |
49 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55782 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[1] |
2018 |
1 |
|
|
T14 |
7 |
|
T5 |
6 |
|
T6 |
10 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55361 |
1 |
|
|
T1 |
78 |
|
T3 |
54 |
|
T10 |
9 |
auto[1] |
2439 |
1 |
|
|
T2 |
20 |
|
T11 |
5 |
|
T13 |
2 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57079 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[1] |
721 |
1 |
|
|
T56 |
12 |
|
T57 |
18 |
|
T58 |
9 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57064 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[1] |
736 |
1 |
|
|
T56 |
19 |
|
T57 |
13 |
|
T58 |
6 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57073 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[1] |
727 |
1 |
|
|
T56 |
11 |
|
T57 |
20 |
|
T58 |
14 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54856 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[1] |
2944 |
1 |
|
|
T5 |
10 |
|
T20 |
45 |
|
T69 |
15 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53959 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[1] |
3841 |
1 |
|
|
T47 |
50 |
|
T21 |
69 |
|
T45 |
78 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55670 |
1 |
|
|
T1 |
73 |
|
T2 |
20 |
|
T3 |
49 |
auto[1] |
2130 |
1 |
|
|
T1 |
5 |
|
T3 |
5 |
|
T5 |
48 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55628 |
1 |
|
|
T1 |
65 |
|
T2 |
20 |
|
T3 |
46 |
auto[1] |
2172 |
1 |
|
|
T1 |
13 |
|
T3 |
8 |
|
T5 |
42 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55687 |
1 |
|
|
T1 |
70 |
|
T2 |
20 |
|
T3 |
45 |
auto[1] |
2113 |
1 |
|
|
T1 |
8 |
|
T3 |
9 |
|
T5 |
43 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55816 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[1] |
1984 |
1 |
|
|
T14 |
9 |
|
T5 |
11 |
|
T6 |
8 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52162 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[1] |
5638 |
1 |
|
|
T14 |
13 |
|
T5 |
8 |
|
T17 |
96 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53915 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[1] |
3885 |
1 |
|
|
T19 |
95 |
|
T54 |
79 |
|
T55 |
77 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
57800 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55768 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[1] |
2032 |
1 |
|
|
T14 |
8 |
|
T5 |
8 |
|
T6 |
7 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55916 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[1] |
1884 |
1 |
|
|
T14 |
4 |
|
T5 |
15 |
|
T6 |
6 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55842 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[1] |
1958 |
1 |
|
|
T14 |
7 |
|
T5 |
10 |
|
T6 |
10 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
50998 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[0] |
no_err_inj |
3858 |
1 |
|
|
T10 |
9 |
|
T5 |
50 |
|
T35 |
14 |
auto[1] |
err_inj |
1482 |
1 |
|
|
T5 |
2 |
|
T20 |
23 |
|
T69 |
7 |
auto[1] |
no_err_inj |
1462 |
1 |
|
|
T5 |
8 |
|
T20 |
22 |
|
T69 |
8 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52846 |
1 |
|
|
T1 |
65 |
|
T2 |
20 |
|
T3 |
46 |
auto[0] |
auto[1] |
2010 |
1 |
|
|
T1 |
13 |
|
T3 |
8 |
|
T5 |
42 |
auto[1] |
auto[0] |
2782 |
1 |
|
|
T5 |
10 |
|
T20 |
42 |
|
T69 |
15 |
auto[1] |
auto[1] |
162 |
1 |
|
|
T20 |
3 |
|
T185 |
1 |
|
T186 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52876 |
1 |
|
|
T1 |
67 |
|
T2 |
20 |
|
T3 |
48 |
auto[0] |
auto[1] |
1980 |
1 |
|
|
T1 |
11 |
|
T3 |
6 |
|
T5 |
59 |
auto[1] |
auto[0] |
2796 |
1 |
|
|
T5 |
10 |
|
T20 |
44 |
|
T69 |
15 |
auto[1] |
auto[1] |
148 |
1 |
|
|
T20 |
1 |
|
T38 |
1 |
|
T185 |
3 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52919 |
1 |
|
|
T1 |
70 |
|
T2 |
20 |
|
T3 |
45 |
auto[0] |
auto[1] |
1937 |
1 |
|
|
T1 |
8 |
|
T3 |
9 |
|
T5 |
42 |
auto[1] |
auto[0] |
2768 |
1 |
|
|
T5 |
9 |
|
T20 |
44 |
|
T69 |
12 |
auto[1] |
auto[1] |
176 |
1 |
|
|
T5 |
1 |
|
T20 |
1 |
|
T69 |
3 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52910 |
1 |
|
|
T1 |
71 |
|
T2 |
20 |
|
T3 |
51 |
auto[0] |
auto[1] |
1946 |
1 |
|
|
T1 |
7 |
|
T3 |
3 |
|
T5 |
50 |
auto[1] |
auto[0] |
2785 |
1 |
|
|
T5 |
10 |
|
T20 |
42 |
|
T69 |
15 |
auto[1] |
auto[1] |
159 |
1 |
|
|
T20 |
3 |
|
T81 |
2 |
|
T185 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52877 |
1 |
|
|
T1 |
68 |
|
T2 |
20 |
|
T3 |
49 |
auto[0] |
auto[1] |
1979 |
1 |
|
|
T1 |
10 |
|
T3 |
5 |
|
T5 |
41 |
auto[1] |
auto[0] |
2778 |
1 |
|
|
T5 |
9 |
|
T20 |
42 |
|
T69 |
15 |
auto[1] |
auto[1] |
166 |
1 |
|
|
T5 |
1 |
|
T20 |
3 |
|
T38 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52933 |
1 |
|
|
T1 |
68 |
|
T2 |
20 |
|
T3 |
49 |
auto[0] |
auto[1] |
1923 |
1 |
|
|
T1 |
10 |
|
T3 |
5 |
|
T5 |
59 |
auto[1] |
auto[0] |
2777 |
1 |
|
|
T5 |
10 |
|
T20 |
43 |
|
T69 |
13 |
auto[1] |
auto[1] |
167 |
1 |
|
|
T20 |
2 |
|
T69 |
2 |
|
T185 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38807 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[0] |
auto[1] |
1223 |
1 |
|
|
T14 |
11 |
|
T20 |
22 |
|
T38 |
26 |
auto[1] |
auto[0] |
16992 |
1 |
|
|
T5 |
208 |
|
T6 |
63 |
|
T22 |
8 |
auto[1] |
auto[1] |
778 |
1 |
|
|
T5 |
14 |
|
T6 |
7 |
|
T20 |
18 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38776 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[0] |
auto[1] |
1254 |
1 |
|
|
T14 |
4 |
|
T20 |
15 |
|
T38 |
22 |
auto[1] |
auto[0] |
16987 |
1 |
|
|
T5 |
217 |
|
T6 |
56 |
|
T22 |
8 |
auto[1] |
auto[1] |
783 |
1 |
|
|
T5 |
5 |
|
T6 |
14 |
|
T20 |
19 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38820 |
1 |
|
|
T1 |
78 |
|
T3 |
54 |
|
T10 |
9 |
auto[0] |
auto[1] |
1210 |
1 |
|
|
T2 |
20 |
|
T11 |
5 |
|
T13 |
2 |
auto[1] |
auto[0] |
16541 |
1 |
|
|
T5 |
222 |
|
T6 |
70 |
|
T20 |
363 |
auto[1] |
auto[1] |
1229 |
1 |
|
|
T22 |
8 |
|
T20 |
76 |
|
T149 |
4 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38770 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[0] |
auto[1] |
1260 |
1 |
|
|
T14 |
7 |
|
T20 |
19 |
|
T38 |
22 |
auto[1] |
auto[0] |
17012 |
1 |
|
|
T5 |
216 |
|
T6 |
60 |
|
T22 |
8 |
auto[1] |
auto[1] |
758 |
1 |
|
|
T5 |
6 |
|
T6 |
10 |
|
T20 |
23 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35189 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[0] |
auto[1] |
4841 |
1 |
|
|
T14 |
13 |
|
T17 |
96 |
|
T20 |
12 |
auto[1] |
auto[0] |
16973 |
1 |
|
|
T5 |
214 |
|
T6 |
62 |
|
T22 |
8 |
auto[1] |
auto[1] |
797 |
1 |
|
|
T5 |
8 |
|
T6 |
8 |
|
T20 |
14 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38764 |
1 |
|
|
T1 |
65 |
|
T2 |
20 |
|
T3 |
46 |
auto[0] |
auto[1] |
1266 |
1 |
|
|
T1 |
13 |
|
T3 |
8 |
|
T5 |
28 |
auto[1] |
auto[0] |
16864 |
1 |
|
|
T5 |
208 |
|
T6 |
70 |
|
T22 |
8 |
auto[1] |
auto[1] |
906 |
1 |
|
|
T5 |
14 |
|
T20 |
19 |
|
T38 |
8 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38814 |
1 |
|
|
T1 |
73 |
|
T2 |
20 |
|
T3 |
49 |
auto[0] |
auto[1] |
1216 |
1 |
|
|
T1 |
5 |
|
T3 |
5 |
|
T5 |
38 |
auto[1] |
auto[0] |
16856 |
1 |
|
|
T5 |
212 |
|
T6 |
70 |
|
T22 |
8 |
auto[1] |
auto[1] |
914 |
1 |
|
|
T5 |
10 |
|
T20 |
11 |
|
T38 |
6 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38774 |
1 |
|
|
T1 |
67 |
|
T2 |
20 |
|
T3 |
48 |
auto[0] |
auto[1] |
1256 |
1 |
|
|
T1 |
11 |
|
T3 |
6 |
|
T5 |
43 |
auto[1] |
auto[0] |
16898 |
1 |
|
|
T5 |
206 |
|
T6 |
70 |
|
T22 |
8 |
auto[1] |
auto[1] |
872 |
1 |
|
|
T5 |
16 |
|
T20 |
16 |
|
T38 |
5 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38808 |
1 |
|
|
T1 |
71 |
|
T2 |
20 |
|
T3 |
47 |
auto[0] |
auto[1] |
1222 |
1 |
|
|
T1 |
7 |
|
T3 |
7 |
|
T5 |
41 |
auto[1] |
auto[0] |
16919 |
1 |
|
|
T5 |
211 |
|
T6 |
70 |
|
T22 |
8 |
auto[1] |
auto[1] |
851 |
1 |
|
|
T5 |
11 |
|
T20 |
15 |
|
T38 |
6 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38789 |
1 |
|
|
T1 |
71 |
|
T2 |
20 |
|
T3 |
51 |
auto[0] |
auto[1] |
1241 |
1 |
|
|
T1 |
7 |
|
T3 |
3 |
|
T5 |
35 |
auto[1] |
auto[0] |
16906 |
1 |
|
|
T5 |
207 |
|
T6 |
70 |
|
T22 |
8 |
auto[1] |
auto[1] |
864 |
1 |
|
|
T5 |
15 |
|
T20 |
27 |
|
T38 |
10 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38796 |
1 |
|
|
T1 |
68 |
|
T2 |
20 |
|
T3 |
49 |
auto[0] |
auto[1] |
1234 |
1 |
|
|
T1 |
10 |
|
T3 |
5 |
|
T5 |
46 |
auto[1] |
auto[0] |
16914 |
1 |
|
|
T5 |
209 |
|
T6 |
70 |
|
T22 |
8 |
auto[1] |
auto[1] |
856 |
1 |
|
|
T5 |
13 |
|
T20 |
15 |
|
T38 |
3 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38844 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[0] |
auto[1] |
1186 |
1 |
|
|
T14 |
7 |
|
T20 |
23 |
|
T38 |
26 |
auto[1] |
auto[0] |
16998 |
1 |
|
|
T5 |
212 |
|
T6 |
60 |
|
T22 |
8 |
auto[1] |
auto[1] |
772 |
1 |
|
|
T5 |
10 |
|
T6 |
10 |
|
T20 |
12 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38917 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[0] |
auto[1] |
1113 |
1 |
|
|
T14 |
4 |
|
T20 |
19 |
|
T38 |
20 |
auto[1] |
auto[0] |
16999 |
1 |
|
|
T5 |
207 |
|
T6 |
64 |
|
T22 |
8 |
auto[1] |
auto[1] |
771 |
1 |
|
|
T5 |
15 |
|
T6 |
6 |
|
T20 |
20 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
38209 |
1 |
|
|
T1 |
78 |
|
T2 |
20 |
|
T3 |
54 |
auto[0] |
auto[1] |
1821 |
1 |
|
|
T20 |
25 |
|
T69 |
15 |
|
T81 |
14 |
auto[1] |
auto[0] |
16647 |
1 |
|
|
T5 |
212 |
|
T6 |
70 |
|
T22 |
8 |
auto[1] |
auto[1] |
1123 |
1 |
|
|
T5 |
10 |
|
T20 |
20 |
|
T186 |
10 |