Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113397244

1

T1

24867

T2

5823

T3

17192

auto[1]

1506095

1

T1

3366

T2

1188

T3

1980

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

113397152

1

T1

25362

T2

6219

T3

17291

auto[1]

1506187

1

T1

2871

T2

792

T3

1881

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8197320	1			T1	8129		T2	1788		T3	5576
auto[IdleSt]	23739705	1			T1	1178		T2	1477		T3	1067
auto[ClkMuxSt]	37547	1			T2	20		T10	9		T11	5
auto[CntIncrSt]	37263	1			T2	20		T10	9		T11	5
auto[CntProgSt]	1402348	1			T2	40		T10	434		T11	63
auto[TransCheckSt]	29057	1			T10	9		T14	48		T5	105
auto[TokenHashSt]	44706169	1			T10	31499		T14	866		T5	334632
auto[FlashRmaSt]	30220	1			T10	14		T14	11		T5	154
auto[TokenCheck0St]	13560	1			T10	9		T14	11		T5	67
auto[TokenCheck1St]	10053	1			T10	9		T14	8		T5	62
auto[TransProgSt]	348092	1			T10	563		T14	71		T5	123
auto[PostTransSt]	13960751	1			T2	1257		T10	651		T11	287
auto[ScrapSt]	218426	1			T5	1350		T35	31		T20	6466
auto[EscalateSt]	7791325	1			T1	8742		T2	2409		T3	5615
auto[InvalidSt]	14379301	1			T1	10173		T3	6908		T5	290430

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2202	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	14379301	1			T1	10173		T3	6908		T5	290430
EscalateSt	7791325	1			T1	8742		T2	2409		T3	5615
ScrapSt	218426	1			T5	1350		T35	31		T20	6466
PostTransSt	13960751	1			T2	1257		T10	651		T11	287
TransProgSt	348092	1			T10	563		T14	71		T5	123
TokenCheck1St	10053	1			T10	9		T14	8		T5	62
TokenCheck0St	13560	1			T10	9		T14	11		T5	67
FlashRmaSt	30220	1			T10	14		T14	11		T5	154
TokenHashSt	44706169	1			T10	31499		T14	866		T5	334632
TransCheckSt	29057	1			T10	9		T14	48		T5	105
CntProgSt	1402348	1			T2	40		T10	434		T11	63
CntIncrSt	37263	1			T2	20		T10	9		T11	5
ClkMuxSt	37547	1			T2	20		T10	9		T11	5
IdleSt	23739705	1			T1	1178		T2	1477		T3	1067
ResetSt	8197320	1			T1	8129		T2	1788		T3	5576
arcs[ResetSt=>IdleSt]	57863	1			T1	72		T2	21		T3	49
arcs[IdleSt=>ScrapSt]	316	1			T5	3		T35	1		T20	4
arcs[IdleSt=>ClkMuxSt]	37321	1			T2	20		T10	9		T11	5
arcs[ClkMuxSt=>CntIncrSt]	37263	1			T2	20		T10	9		T11	5
arcs[CntIncrSt=>PostTransSt]	1886	1			T14	4		T5	15		T6	6
arcs[CntIncrSt=>CntProgSt]	35330	1			T2	20		T10	9		T11	5
arcs[CntProgSt=>PostTransSt]	5148	1			T2	20		T11	5		T13	2
arcs[CntProgSt=>TransCheckSt]	29057	1			T10	9		T14	48		T5	105
arcs[TransCheckSt=>PostTransSt]	3860	1			T14	7		T5	10		T19	43
arcs[TransCheckSt=>TokenHashSt]	25071	1			T10	9		T14	41		T5	95
arcs[TokenHashSt=>PostTransSt]	10710	1			T14	30		T5	27		T18	1
arcs[TokenHashSt=>FlashRmaSt]	13654	1			T10	9		T14	11		T5	67
arcs[FlashRmaSt=>TokenCheck0St]	13560	1			T10	9		T14	11		T5	67
arcs[TokenCheck0St=>PostTransSt]	3489	1			T14	3		T5	5		T19	18
arcs[TokenCheck0St=>TokenCheck1St]	10053	1			T10	9		T14	8		T5	62
arcs[TokenCheck1St=>PostTransSt]	693	1			T14	1		T19	20		T20	2
arcs[TransProgSt=>PostTransSt]	8433	1			T10	9		T14	7		T5	62
arcs[IdleSt=>EscalateSt]	215	1			T47	5		T21	5		T45	5
arcs[ClkMuxSt=>EscalateSt]	58	1			T21	1		T45	3		T46	2
arcs[CntIncrSt=>EscalateSt]	47	1			T47	2		T21	1		T48	4
arcs[CntProgSt=>EscalateSt]	1125	1			T47	16		T21	19		T45	28
arcs[TransCheckSt=>EscalateSt]	126	1			T21	4		T46	3		T48	2
arcs[TokenHashSt=>EscalateSt]	707	1			T5	1		T47	5		T21	14
arcs[FlashRmaSt=>EscalateSt]	94	1			T47	1		T21	2		T45	2
arcs[TokenCheck0St=>EscalateSt]	18	1			T21	1		T45	1		T15	1
arcs[TokenCheck1St=>EscalateSt]	151	1			T47	2		T21	5		T45	2
arcs[TransProgSt=>EscalateSt]	776	1			T47	12		T21	13		T45	21
arcs[PostTransSt=>EscalateSt]	5381	1			T2	20		T11	5		T13	2
arcs[InvalidSt=>EscalateSt]	15597	1			T1	63		T3	39		T5	353

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8197153	1			T1	8129		T2	1788		T3	5576
auto[0]	auto[IdleSt]	23739563	1			T1	1178		T2	1477		T3	1067
auto[0]	auto[ClkMuxSt]	37514	1			T2	20		T10	9		T11	5
auto[0]	auto[CntIncrSt]	37233	1			T2	20		T10	9		T11	5
auto[0]	auto[CntProgSt]	1401585	1			T2	40		T10	434		T11	63
auto[0]	auto[TransCheckSt]	28969	1			T10	9		T14	48		T5	105
auto[0]	auto[TokenHashSt]	44705711	1			T10	31499		T14	866		T5	334632
auto[0]	auto[FlashRmaSt]	30154	1			T10	14		T14	11		T5	154
auto[0]	auto[TokenCheck0St]	13550	1			T10	9		T14	11		T5	67
auto[0]	auto[TokenCheck1St]	9955	1			T10	9		T14	8		T5	62
auto[0]	auto[TransProgSt]	347577	1			T10	563		T14	71		T5	123
auto[0]	auto[PostTransSt]	13958023	1			T2	1245		T10	651		T11	286
auto[0]	auto[ScrapSt]	218389	1			T5	1350		T35	31		T20	6466
auto[0]	auto[EscalateSt]	6298176	1			T1	5410		T2	1233		T3	3655
auto[0]	auto[InvalidSt]	14371490	1			T1	10139		T3	6888		T5	290254
auto[1]	auto[ResetSt]	167	1			T47	4		T45	2		T46	4
auto[1]	auto[IdleSt]	142	1			T47	3		T21	3		T45	4
auto[1]	auto[ClkMuxSt]	33	1			T21	1		T45	3		T48	1
auto[1]	auto[CntIncrSt]	30	1			T47	2		T48	3		T182	1
auto[1]	auto[CntProgSt]	763	1			T47	8		T21	13		T45	16
auto[1]	auto[TransCheckSt]	88	1			T21	2		T46	3		T80	7
auto[1]	auto[TokenHashSt]	458	1			T47	2		T21	8		T45	4
auto[1]	auto[FlashRmaSt]	66	1			T21	2		T45	2		T46	4
auto[1]	auto[TokenCheck0St]	10	1			T21	1		T15	1		T183	1
auto[1]	auto[TokenCheck1St]	98	1			T47	2		T21	3		T45	2
auto[1]	auto[TransProgSt]	515	1			T47	7		T21	9		T45	14
auto[1]	auto[PostTransSt]	2728	1			T2	12		T11	1		T14	6
auto[1]	auto[ScrapSt]	37	1			T45	4		T15	1		T183	1
auto[1]	auto[EscalateSt]	1493149	1			T1	3332		T2	1176		T3	1960
auto[1]	auto[InvalidSt]	7811	1			T1	34		T3	20		T5	176

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8197132	1			T1	8129		T2	1788		T3	5576
auto[0]	auto[IdleSt]	23739570	1			T1	1178		T2	1477		T3	1067
auto[0]	auto[ClkMuxSt]	37504	1			T2	20		T10	9		T11	5
auto[0]	auto[CntIncrSt]	37235	1			T2	20		T10	9		T11	5
auto[0]	auto[CntProgSt]	1401603	1			T2	40		T10	434		T11	63
auto[0]	auto[TransCheckSt]	28976	1			T10	9		T14	48		T5	105
auto[0]	auto[TokenHashSt]	44705689	1			T10	31499		T14	866		T5	334631
auto[0]	auto[FlashRmaSt]	30163	1			T10	14		T14	11		T5	154
auto[0]	auto[TokenCheck0St]	13548	1			T10	9		T14	11		T5	67
auto[0]	auto[TokenCheck1St]	9949	1			T10	9		T14	8		T5	62
auto[0]	auto[TransProgSt]	347580	1			T10	563		T14	71		T5	123
auto[0]	auto[PostTransSt]	13958025	1			T2	1249		T10	651		T11	283
auto[0]	auto[ScrapSt]	218388	1			T5	1350		T35	31		T20	6466
auto[0]	auto[EscalateSt]	6298073	1			T1	5900		T2	1625		T3	3753
auto[0]	auto[InvalidSt]	14371515	1			T1	10144		T3	6889		T5	290253
auto[1]	auto[ResetSt]	188	1			T47	4		T21	1		T45	3
auto[1]	auto[IdleSt]	135	1			T47	4		T21	3		T45	3
auto[1]	auto[ClkMuxSt]	43	1			T21	1		T45	3		T46	2
auto[1]	auto[CntIncrSt]	28	1			T47	1		T21	1		T48	2
auto[1]	auto[CntProgSt]	745	1			T47	12		T21	13		T45	20
auto[1]	auto[TransCheckSt]	81	1			T21	3		T46	1		T48	2
auto[1]	auto[TokenHashSt]	480	1			T5	1		T47	4		T21	11
auto[1]	auto[FlashRmaSt]	57	1			T47	1		T45	2		T46	1
auto[1]	auto[TokenCheck0St]	12	1			T45	1		T15	1		T184	1
auto[1]	auto[TokenCheck1St]	104	1			T47	2		T21	2		T45	1
auto[1]	auto[TransProgSt]	512	1			T47	6		T21	8		T45	12
auto[1]	auto[PostTransSt]	2726	1			T2	8		T11	4		T13	2
auto[1]	auto[ScrapSt]	38	1			T47	1		T45	5		T48	1
auto[1]	auto[EscalateSt]	1493252	1			T1	2842		T2	784		T3	1862
auto[1]	auto[InvalidSt]	7786	1			T1	29		T3	19		T5	177