Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.17 97.82 95.66 93.31 100.00 98.52 98.76 96.11


Total test records in report: 1004
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T804 /workspace/coverage/default/48.lc_ctrl_smoke.3243997166 May 23 01:41:44 PM PDT 24 May 23 01:41:50 PM PDT 24 106866828 ps
T805 /workspace/coverage/default/46.lc_ctrl_stress_all.701884562 May 23 01:41:49 PM PDT 24 May 23 01:42:26 PM PDT 24 3171970353 ps
T806 /workspace/coverage/default/37.lc_ctrl_state_post_trans.4023308305 May 23 01:41:22 PM PDT 24 May 23 01:41:32 PM PDT 24 49561889 ps
T807 /workspace/coverage/default/23.lc_ctrl_sec_token_mux.4000401364 May 23 01:40:43 PM PDT 24 May 23 01:40:56 PM PDT 24 3395791448 ps
T808 /workspace/coverage/default/37.lc_ctrl_alert_test.115587885 May 23 01:41:19 PM PDT 24 May 23 01:41:22 PM PDT 24 37288132 ps
T809 /workspace/coverage/default/6.lc_ctrl_state_failure.1253649665 May 23 01:39:42 PM PDT 24 May 23 01:40:10 PM PDT 24 245819252 ps
T810 /workspace/coverage/default/3.lc_ctrl_stress_all.1638028279 May 23 01:39:29 PM PDT 24 May 23 01:42:35 PM PDT 24 12950155532 ps
T811 /workspace/coverage/default/11.lc_ctrl_stress_all.3149353182 May 23 01:39:59 PM PDT 24 May 23 01:41:26 PM PDT 24 13478668061 ps
T812 /workspace/coverage/default/6.lc_ctrl_sec_token_digest.499262704 May 23 01:39:46 PM PDT 24 May 23 01:40:01 PM PDT 24 1131506240 ps
T813 /workspace/coverage/default/16.lc_ctrl_alert_test.1391556649 May 23 01:40:23 PM PDT 24 May 23 01:40:25 PM PDT 24 13931396 ps
T814 /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3431853519 May 23 01:40:11 PM PDT 24 May 23 01:40:14 PM PDT 24 69287950 ps
T815 /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.1781135737 May 23 01:40:00 PM PDT 24 May 23 01:40:04 PM PDT 24 14907356 ps
T816 /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.632108669 May 23 01:39:54 PM PDT 24 May 23 01:41:16 PM PDT 24 14308986010 ps
T817 /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3297152462 May 23 01:41:09 PM PDT 24 May 23 01:41:22 PM PDT 24 362720434 ps
T818 /workspace/coverage/default/28.lc_ctrl_security_escalation.18681056 May 23 01:40:55 PM PDT 24 May 23 01:41:06 PM PDT 24 206588281 ps
T819 /workspace/coverage/default/33.lc_ctrl_security_escalation.685092019 May 23 01:41:15 PM PDT 24 May 23 01:41:24 PM PDT 24 285401155 ps
T820 /workspace/coverage/default/0.lc_ctrl_sec_token_mux.399221164 May 23 01:39:20 PM PDT 24 May 23 01:39:31 PM PDT 24 620327978 ps
T821 /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.4185774522 May 23 01:39:20 PM PDT 24 May 23 01:39:23 PM PDT 24 17737659 ps
T822 /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3244854897 May 23 01:39:39 PM PDT 24 May 23 01:39:56 PM PDT 24 1739815524 ps
T823 /workspace/coverage/default/2.lc_ctrl_smoke.2578915131 May 23 01:39:18 PM PDT 24 May 23 01:39:22 PM PDT 24 91639656 ps
T824 /workspace/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.2805764756 May 23 01:40:53 PM PDT 24 May 23 01:44:25 PM PDT 24 10724410916 ps
T825 /workspace/coverage/default/22.lc_ctrl_alert_test.2336210716 May 23 01:40:40 PM PDT 24 May 23 01:40:43 PM PDT 24 13475388 ps
T826 /workspace/coverage/default/21.lc_ctrl_alert_test.1321625933 May 23 01:40:43 PM PDT 24 May 23 01:40:46 PM PDT 24 40621242 ps
T827 /workspace/coverage/default/6.lc_ctrl_jtag_access.35855041 May 23 01:39:37 PM PDT 24 May 23 01:39:54 PM PDT 24 2045692394 ps
T828 /workspace/coverage/default/39.lc_ctrl_alert_test.296353295 May 23 01:41:19 PM PDT 24 May 23 01:41:22 PM PDT 24 28629756 ps
T829 /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3858954617 May 23 01:39:28 PM PDT 24 May 23 01:39:41 PM PDT 24 471858432 ps
T830 /workspace/coverage/default/6.lc_ctrl_jtag_priority.2979528667 May 23 01:39:37 PM PDT 24 May 23 01:39:48 PM PDT 24 186309960 ps
T831 /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.1890904078 May 23 01:40:57 PM PDT 24 May 23 01:48:48 PM PDT 24 38803980493 ps
T96 /workspace/coverage/default/1.lc_ctrl_sec_cm.3244686376 May 23 01:39:23 PM PDT 24 May 23 01:40:07 PM PDT 24 1077214312 ps
T144 /workspace/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.1842629301 May 23 01:39:47 PM PDT 24 May 23 01:47:18 PM PDT 24 42082038719 ps
T832 /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3122972446 May 23 01:39:43 PM PDT 24 May 23 01:40:07 PM PDT 24 361235037 ps
T833 /workspace/coverage/default/38.lc_ctrl_state_failure.2972340292 May 23 01:41:19 PM PDT 24 May 23 01:41:51 PM PDT 24 1163316020 ps
T834 /workspace/coverage/default/0.lc_ctrl_alert_test.1563029093 May 23 01:39:18 PM PDT 24 May 23 01:39:20 PM PDT 24 56275660 ps
T835 /workspace/coverage/default/16.lc_ctrl_sec_token_digest.3436392730 May 23 01:40:22 PM PDT 24 May 23 01:40:32 PM PDT 24 1361048527 ps
T836 /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3041290577 May 23 01:41:33 PM PDT 24 May 23 01:41:43 PM PDT 24 324247100 ps
T837 /workspace/coverage/default/27.lc_ctrl_state_failure.2666188120 May 23 01:40:57 PM PDT 24 May 23 01:41:26 PM PDT 24 710256905 ps
T838 /workspace/coverage/default/34.lc_ctrl_jtag_access.1254601943 May 23 01:41:14 PM PDT 24 May 23 01:41:26 PM PDT 24 1199304981 ps
T839 /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2347153514 May 23 01:40:24 PM PDT 24 May 23 01:40:36 PM PDT 24 1009273873 ps
T840 /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3933839535 May 23 01:39:20 PM PDT 24 May 23 01:39:30 PM PDT 24 5995036333 ps
T841 /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.155815104 May 23 01:41:36 PM PDT 24 May 23 01:41:39 PM PDT 24 49542709 ps
T842 /workspace/coverage/default/22.lc_ctrl_sec_token_mux.15133165 May 23 01:40:42 PM PDT 24 May 23 01:40:57 PM PDT 24 1520509990 ps
T843 /workspace/coverage/default/33.lc_ctrl_state_failure.621265513 May 23 01:41:09 PM PDT 24 May 23 01:41:37 PM PDT 24 999233518 ps
T844 /workspace/coverage/default/38.lc_ctrl_security_escalation.3096921739 May 23 01:41:30 PM PDT 24 May 23 01:41:45 PM PDT 24 359503212 ps
T845 /workspace/coverage/default/46.lc_ctrl_state_post_trans.3544930517 May 23 01:41:45 PM PDT 24 May 23 01:41:56 PM PDT 24 62274519 ps
T846 /workspace/coverage/default/13.lc_ctrl_state_failure.4183829779 May 23 01:40:00 PM PDT 24 May 23 01:40:27 PM PDT 24 193078135 ps
T847 /workspace/coverage/default/41.lc_ctrl_stress_all.913457519 May 23 01:41:30 PM PDT 24 May 23 01:43:24 PM PDT 24 4663096150 ps
T848 /workspace/coverage/default/40.lc_ctrl_stress_all.664219883 May 23 01:41:20 PM PDT 24 May 23 01:43:51 PM PDT 24 27913567104 ps
T849 /workspace/coverage/default/38.lc_ctrl_stress_all.2396761461 May 23 01:41:19 PM PDT 24 May 23 01:43:24 PM PDT 24 29030812747 ps
T850 /workspace/coverage/default/3.lc_ctrl_alert_test.1992598531 May 23 01:39:32 PM PDT 24 May 23 01:39:37 PM PDT 24 14650596 ps
T851 /workspace/coverage/default/2.lc_ctrl_jtag_errors.236359862 May 23 01:39:20 PM PDT 24 May 23 01:39:53 PM PDT 24 3403974954 ps
T852 /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3424158392 May 23 01:39:18 PM PDT 24 May 23 01:39:25 PM PDT 24 328007406 ps
T853 /workspace/coverage/default/18.lc_ctrl_prog_failure.2404061193 May 23 01:40:22 PM PDT 24 May 23 01:40:27 PM PDT 24 58719356 ps
T854 /workspace/coverage/default/27.lc_ctrl_prog_failure.1265217587 May 23 01:40:59 PM PDT 24 May 23 01:41:03 PM PDT 24 284767927 ps
T855 /workspace/coverage/default/35.lc_ctrl_security_escalation.3179296769 May 23 01:41:18 PM PDT 24 May 23 01:41:31 PM PDT 24 601486222 ps
T856 /workspace/coverage/default/5.lc_ctrl_regwen_during_op.3656610504 May 23 01:39:32 PM PDT 24 May 23 01:39:47 PM PDT 24 343764834 ps
T857 /workspace/coverage/default/18.lc_ctrl_state_post_trans.3731794570 May 23 01:40:22 PM PDT 24 May 23 01:40:30 PM PDT 24 71624113 ps
T858 /workspace/coverage/default/41.lc_ctrl_state_failure.770412704 May 23 01:41:30 PM PDT 24 May 23 01:41:57 PM PDT 24 453750127 ps
T859 /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2545511648 May 23 01:40:26 PM PDT 24 May 23 01:41:43 PM PDT 24 12753482955 ps
T860 /workspace/coverage/default/4.lc_ctrl_jtag_access.239692800 May 23 01:39:33 PM PDT 24 May 23 01:39:44 PM PDT 24 1647138878 ps
T861 /workspace/coverage/default/26.lc_ctrl_alert_test.3960292050 May 23 01:41:00 PM PDT 24 May 23 01:41:02 PM PDT 24 64522032 ps
T862 /workspace/coverage/default/16.lc_ctrl_sec_mubi.3050785532 May 23 01:40:21 PM PDT 24 May 23 01:40:34 PM PDT 24 613748609 ps
T863 /workspace/coverage/default/27.lc_ctrl_jtag_access.637227557 May 23 01:40:54 PM PDT 24 May 23 01:41:08 PM PDT 24 1028097873 ps
T864 /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3044287401 May 23 01:41:12 PM PDT 24 May 23 01:41:22 PM PDT 24 231184579 ps
T865 /workspace/coverage/default/37.lc_ctrl_state_failure.294042089 May 23 01:41:22 PM PDT 24 May 23 01:41:52 PM PDT 24 494249038 ps
T866 /workspace/coverage/default/48.lc_ctrl_sec_token_digest.2049064851 May 23 01:41:48 PM PDT 24 May 23 01:42:06 PM PDT 24 1311576831 ps
T867 /workspace/coverage/default/19.lc_ctrl_security_escalation.2879709516 May 23 01:40:25 PM PDT 24 May 23 01:40:43 PM PDT 24 707423559 ps
T868 /workspace/coverage/default/34.lc_ctrl_stress_all.4018988168 May 23 01:41:15 PM PDT 24 May 23 01:42:12 PM PDT 24 3339852882 ps
T869 /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1691316330 May 23 01:41:15 PM PDT 24 May 23 01:41:36 PM PDT 24 3598518287 ps
T870 /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1335043840 May 23 01:41:18 PM PDT 24 May 23 01:41:21 PM PDT 24 11627836 ps
T118 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1676711486 May 23 01:27:11 PM PDT 24 May 23 01:27:15 PM PDT 24 471160909 ps
T106 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2332734142 May 23 01:27:14 PM PDT 24 May 23 01:27:19 PM PDT 24 255719390 ps
T107 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2766254380 May 23 01:27:15 PM PDT 24 May 23 01:27:21 PM PDT 24 97980123 ps
T134 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1039029438 May 23 01:26:46 PM PDT 24 May 23 01:26:49 PM PDT 24 31309184 ps
T112 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3301782635 May 23 01:27:01 PM PDT 24 May 23 01:27:19 PM PDT 24 577330096 ps
T108 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1921982600 May 23 01:26:51 PM PDT 24 May 23 01:26:56 PM PDT 24 64154404 ps
T113 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1011009719 May 23 01:27:02 PM PDT 24 May 23 01:27:15 PM PDT 24 1634123964 ps
T173 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1766784505 May 23 01:27:02 PM PDT 24 May 23 01:27:20 PM PDT 24 2626789327 ps
T133 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1546384196 May 23 01:27:16 PM PDT 24 May 23 01:27:21 PM PDT 24 39315836 ps
T109 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1311156381 May 23 01:27:13 PM PDT 24 May 23 01:27:17 PM PDT 24 260267495 ps
T111 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.1143141813 May 23 01:27:14 PM PDT 24 May 23 01:27:19 PM PDT 24 114820935 ps
T140 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3842249778 May 23 01:27:17 PM PDT 24 May 23 01:27:21 PM PDT 24 29226561 ps
T114 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1431251485 May 23 01:27:14 PM PDT 24 May 23 01:27:18 PM PDT 24 336492909 ps
T871 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1889229007 May 23 01:26:53 PM PDT 24 May 23 01:27:00 PM PDT 24 1012241889 ps
T164 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2101572670 May 23 01:27:22 PM PDT 24 May 23 01:27:25 PM PDT 24 40254414 ps
T872 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3908331944 May 23 01:27:00 PM PDT 24 May 23 01:27:29 PM PDT 24 9243558303 ps
T117 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.197729929 May 23 01:27:01 PM PDT 24 May 23 01:27:07 PM PDT 24 99614885 ps
T141 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2056445716 May 23 01:26:59 PM PDT 24 May 23 01:27:03 PM PDT 24 23213417 ps
T873 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3657843573 May 23 01:26:58 PM PDT 24 May 23 01:27:12 PM PDT 24 1168260420 ps
T874 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2691763450 May 23 01:27:13 PM PDT 24 May 23 01:27:26 PM PDT 24 1635766298 ps
T875 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.4061496907 May 23 01:26:59 PM PDT 24 May 23 01:27:04 PM PDT 24 29622429 ps
T876 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.3772605642 May 23 01:26:52 PM PDT 24 May 23 01:26:56 PM PDT 24 48378833 ps
T146 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.2694594451 May 23 01:27:15 PM PDT 24 May 23 01:27:19 PM PDT 24 24120599 ps
T877 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1605595279 May 23 01:27:10 PM PDT 24 May 23 01:27:13 PM PDT 24 115309625 ps
T110 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2269979328 May 23 01:27:15 PM PDT 24 May 23 01:27:21 PM PDT 24 224128175 ps
T123 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1297638994 May 23 01:27:13 PM PDT 24 May 23 01:27:18 PM PDT 24 122780494 ps
T115 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3184778650 May 23 01:27:02 PM PDT 24 May 23 01:27:09 PM PDT 24 574129060 ps
T878 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4268220688 May 23 01:27:13 PM PDT 24 May 23 01:27:15 PM PDT 24 335585997 ps
T165 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.594889121 May 23 01:26:56 PM PDT 24 May 23 01:26:58 PM PDT 24 88866108 ps
T166 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2168515586 May 23 01:27:13 PM PDT 24 May 23 01:27:16 PM PDT 24 192519001 ps
T180 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2788488381 May 23 01:27:16 PM PDT 24 May 23 01:27:21 PM PDT 24 337526417 ps
T167 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3730760975 May 23 01:27:01 PM PDT 24 May 23 01:27:06 PM PDT 24 27210210 ps
T168 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1143519943 May 23 01:26:59 PM PDT 24 May 23 01:27:03 PM PDT 24 13307131 ps
T879 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.717315860 May 23 01:27:15 PM PDT 24 May 23 01:27:19 PM PDT 24 34794518 ps
T880 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3134187598 May 23 01:27:01 PM PDT 24 May 23 01:27:15 PM PDT 24 407188816 ps
T881 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.632647932 May 23 01:27:11 PM PDT 24 May 23 01:27:13 PM PDT 24 23936025 ps
T156 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.1433040775 May 23 01:27:02 PM PDT 24 May 23 01:27:07 PM PDT 24 22312680 ps
T169 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.465169032 May 23 01:27:15 PM PDT 24 May 23 01:27:18 PM PDT 24 37309217 ps
T882 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.3364841841 May 23 01:27:13 PM PDT 24 May 23 01:27:15 PM PDT 24 33517875 ps
T883 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.286701477 May 23 01:27:12 PM PDT 24 May 23 01:27:14 PM PDT 24 123013700 ps
T170 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2043627703 May 23 01:27:17 PM PDT 24 May 23 01:27:21 PM PDT 24 87716493 ps
T171 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2722679925 May 23 01:27:01 PM PDT 24 May 23 01:27:06 PM PDT 24 16612503 ps
T884 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3112427997 May 23 01:27:02 PM PDT 24 May 23 01:27:09 PM PDT 24 814871650 ps
T885 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.330523671 May 23 01:27:12 PM PDT 24 May 23 01:27:14 PM PDT 24 62211684 ps
T886 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3273066111 May 23 01:27:02 PM PDT 24 May 23 01:27:07 PM PDT 24 33458126 ps
T887 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3127993760 May 23 01:27:00 PM PDT 24 May 23 01:27:09 PM PDT 24 852541671 ps
T181 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3996699293 May 23 01:27:04 PM PDT 24 May 23 01:27:09 PM PDT 24 45186413 ps
T888 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.656402366 May 23 01:27:01 PM PDT 24 May 23 01:27:06 PM PDT 24 81552547 ps
T889 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3163215773 May 23 01:27:13 PM PDT 24 May 23 01:27:17 PM PDT 24 79965429 ps
T890 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3540908940 May 23 01:26:58 PM PDT 24 May 23 01:27:02 PM PDT 24 266146137 ps
T121 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3196119564 May 23 01:27:00 PM PDT 24 May 23 01:27:06 PM PDT 24 118709630 ps
T891 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3739187965 May 23 01:27:04 PM PDT 24 May 23 01:27:08 PM PDT 24 59069782 ps
T892 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1134493672 May 23 01:26:57 PM PDT 24 May 23 01:27:00 PM PDT 24 57255075 ps
T119 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1672998010 May 23 01:27:23 PM PDT 24 May 23 01:27:29 PM PDT 24 435106826 ps
T893 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.614809174 May 23 01:27:01 PM PDT 24 May 23 01:27:07 PM PDT 24 63238420 ps
T894 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1111617240 May 23 01:26:53 PM PDT 24 May 23 01:26:57 PM PDT 24 478138108 ps
T895 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4172194175 May 23 01:27:04 PM PDT 24 May 23 01:27:08 PM PDT 24 23783046 ps
T896 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.5195283 May 23 01:26:59 PM PDT 24 May 23 01:27:03 PM PDT 24 57451667 ps
T897 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2832702138 May 23 01:27:14 PM PDT 24 May 23 01:27:18 PM PDT 24 133203004 ps
T898 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1456812426 May 23 01:27:13 PM PDT 24 May 23 01:27:15 PM PDT 24 19244183 ps
T899 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.4149827261 May 23 01:27:13 PM PDT 24 May 23 01:27:17 PM PDT 24 227696198 ps
T900 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1243923398 May 23 01:26:59 PM PDT 24 May 23 01:27:03 PM PDT 24 44408865 ps
T901 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1477859654 May 23 01:26:50 PM PDT 24 May 23 01:26:58 PM PDT 24 1419794706 ps
T902 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1205671440 May 23 01:27:01 PM PDT 24 May 23 01:27:07 PM PDT 24 437007981 ps
T116 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1652141064 May 23 01:27:00 PM PDT 24 May 23 01:27:05 PM PDT 24 59166150 ps
T903 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4096368512 May 23 01:27:17 PM PDT 24 May 23 01:27:21 PM PDT 24 34496348 ps
T157 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2414266315 May 23 01:27:11 PM PDT 24 May 23 01:27:13 PM PDT 24 22188263 ps
T904 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3871732740 May 23 01:27:22 PM PDT 24 May 23 01:27:25 PM PDT 24 15925234 ps
T120 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.108429901 May 23 01:27:17 PM PDT 24 May 23 01:27:24 PM PDT 24 107561590 ps
T905 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2724697237 May 23 01:26:50 PM PDT 24 May 23 01:26:52 PM PDT 24 55918880 ps
T906 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3258331769 May 23 01:26:49 PM PDT 24 May 23 01:26:53 PM PDT 24 41058373 ps
T907 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.72139243 May 23 01:26:59 PM PDT 24 May 23 01:27:06 PM PDT 24 1383292699 ps
T908 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1473613611 May 23 01:27:04 PM PDT 24 May 23 01:27:08 PM PDT 24 815171935 ps
T909 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1855994509 May 23 01:27:16 PM PDT 24 May 23 01:27:23 PM PDT 24 483445952 ps
T910 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.981383720 May 23 01:27:01 PM PDT 24 May 23 01:27:21 PM PDT 24 6161518066 ps
T911 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.3003094343 May 23 01:27:17 PM PDT 24 May 23 01:27:21 PM PDT 24 131063830 ps
T912 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.668973300 May 23 01:27:01 PM PDT 24 May 23 01:27:05 PM PDT 24 226677180 ps
T913 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.973851471 May 23 01:27:15 PM PDT 24 May 23 01:27:19 PM PDT 24 29455169 ps
T914 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.599349829 May 23 01:26:54 PM PDT 24 May 23 01:26:58 PM PDT 24 43610508 ps
T915 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2654106868 May 23 01:26:54 PM PDT 24 May 23 01:26:57 PM PDT 24 57473557 ps
T916 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3514378121 May 23 01:26:58 PM PDT 24 May 23 01:27:01 PM PDT 24 13995521 ps
T917 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1700161826 May 23 01:27:02 PM PDT 24 May 23 01:27:09 PM PDT 24 215759899 ps
T918 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.678099793 May 23 01:27:16 PM PDT 24 May 23 01:27:20 PM PDT 24 69425797 ps
T919 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2574491919 May 23 01:27:13 PM PDT 24 May 23 01:27:16 PM PDT 24 280538517 ps
T920 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3872359822 May 23 01:26:46 PM PDT 24 May 23 01:26:53 PM PDT 24 2239215220 ps
T921 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3124813878 May 23 01:26:58 PM PDT 24 May 23 01:27:11 PM PDT 24 936420087 ps
T922 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3864987867 May 23 01:27:00 PM PDT 24 May 23 01:27:05 PM PDT 24 20936004 ps
T923 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3132878427 May 23 01:26:50 PM PDT 24 May 23 01:26:53 PM PDT 24 128709253 ps
T924 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2365816997 May 23 01:27:14 PM PDT 24 May 23 01:27:18 PM PDT 24 55926348 ps
T925 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3810646773 May 23 01:27:03 PM PDT 24 May 23 01:27:08 PM PDT 24 65925614 ps
T158 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1879749167 May 23 01:27:15 PM PDT 24 May 23 01:27:18 PM PDT 24 43257327 ps
T926 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.2532223042 May 23 01:27:12 PM PDT 24 May 23 01:27:15 PM PDT 24 153646986 ps
T927 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.737075926 May 23 01:27:14 PM PDT 24 May 23 01:27:19 PM PDT 24 161908103 ps
T928 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.3393157047 May 23 01:26:57 PM PDT 24 May 23 01:27:01 PM PDT 24 219700020 ps
T128 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2540579593 May 23 01:27:16 PM PDT 24 May 23 01:27:22 PM PDT 24 337570796 ps
T929 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.546012037 May 23 01:27:04 PM PDT 24 May 23 01:27:08 PM PDT 24 51423208 ps
T930 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.843835788 May 23 01:26:59 PM PDT 24 May 23 01:27:03 PM PDT 24 22057013 ps
T931 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2620109606 May 23 01:26:59 PM PDT 24 May 23 01:27:04 PM PDT 24 353231067 ps
T932 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.3755022630 May 23 01:27:14 PM PDT 24 May 23 01:27:17 PM PDT 24 66028014 ps
T933 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.2213971557 May 23 01:27:02 PM PDT 24 May 23 01:27:07 PM PDT 24 89000487 ps
T934 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2177651939 May 23 01:27:03 PM PDT 24 May 23 01:27:08 PM PDT 24 56422679 ps
T131 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1011720462 May 23 01:26:57 PM PDT 24 May 23 01:27:00 PM PDT 24 245154560 ps
T935 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.36816341 May 23 01:27:02 PM PDT 24 May 23 01:27:08 PM PDT 24 229486717 ps
T936 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3174323155 May 23 01:27:00 PM PDT 24 May 23 01:27:05 PM PDT 24 63059465 ps
T937 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2264605543 May 23 01:27:13 PM PDT 24 May 23 01:27:16 PM PDT 24 100522673 ps
T938 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1373414077 May 23 01:27:00 PM PDT 24 May 23 01:27:05 PM PDT 24 47582488 ps
T939 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.317196584 May 23 01:27:14 PM PDT 24 May 23 01:27:17 PM PDT 24 29471590 ps
T940 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.27513295 May 23 01:26:59 PM PDT 24 May 23 01:27:03 PM PDT 24 55221769 ps
T941 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1333313032 May 23 01:27:01 PM PDT 24 May 23 01:27:06 PM PDT 24 124613461 ps
T942 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1205266706 May 23 01:27:11 PM PDT 24 May 23 01:27:13 PM PDT 24 80120911 ps
T127 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2524849217 May 23 01:27:13 PM PDT 24 May 23 01:27:18 PM PDT 24 993811535 ps
T943 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1322205885 May 23 01:26:59 PM PDT 24 May 23 01:27:04 PM PDT 24 358578964 ps
T159 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4026203662 May 23 01:27:15 PM PDT 24 May 23 01:27:18 PM PDT 24 22213133 ps
T944 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.129991925 May 23 01:27:00 PM PDT 24 May 23 01:27:04 PM PDT 24 58937538 ps
T945 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.1913358850 May 23 01:26:47 PM PDT 24 May 23 01:26:50 PM PDT 24 50193436 ps
T946 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2519620050 May 23 01:27:14 PM PDT 24 May 23 01:27:17 PM PDT 24 87599698 ps
T947 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1705118727 May 23 01:27:02 PM PDT 24 May 23 01:27:07 PM PDT 24 35196409 ps
T948 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3263147953 May 23 01:26:57 PM PDT 24 May 23 01:26:59 PM PDT 24 72305560 ps
T125 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1045039451 May 23 01:27:03 PM PDT 24 May 23 01:27:09 PM PDT 24 69934369 ps
T949 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.545282683 May 23 01:27:00 PM PDT 24 May 23 01:27:06 PM PDT 24 319671426 ps
T950 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.4205174508 May 23 01:27:18 PM PDT 24 May 23 01:27:21 PM PDT 24 42174050 ps
T951 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1770046278 May 23 01:27:02 PM PDT 24 May 23 01:27:08 PM PDT 24 641982504 ps
T160 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2174075305 May 23 01:27:15 PM PDT 24 May 23 01:27:18 PM PDT 24 21640022 ps
T952 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2847587355 May 23 01:27:10 PM PDT 24 May 23 01:27:12 PM PDT 24 19774345 ps
T953 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3466448216 May 23 01:27:13 PM PDT 24 May 23 01:27:16 PM PDT 24 124569111 ps
T954 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1330251290 May 23 01:27:00 PM PDT 24 May 23 01:27:08 PM PDT 24 113026535 ps
T955 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1729946169 May 23 01:26:57 PM PDT 24 May 23 01:26:59 PM PDT 24 44687416 ps
T956 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2573875905 May 23 01:27:18 PM PDT 24 May 23 01:27:21 PM PDT 24 19877246 ps
T957 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3339882440 May 23 01:26:52 PM PDT 24 May 23 01:26:56 PM PDT 24 54688518 ps
T958 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2415674491 May 23 01:26:58 PM PDT 24 May 23 01:27:02 PM PDT 24 64543606 ps
T959 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2218953560 May 23 01:27:03 PM PDT 24 May 23 01:27:10 PM PDT 24 52309097 ps
T960 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.4165306828 May 23 01:27:04 PM PDT 24 May 23 01:27:17 PM PDT 24 952932644 ps
T961 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1921516931 May 23 01:27:14 PM PDT 24 May 23 01:27:17 PM PDT 24 18691898 ps
T962 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2031715243 May 23 01:26:55 PM PDT 24 May 23 01:27:03 PM PDT 24 1005675586 ps
T963 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2916052505 May 23 01:27:13 PM PDT 24 May 23 01:27:16 PM PDT 24 152323408 ps
T964 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.933642380 May 23 01:27:01 PM PDT 24 May 23 01:27:06 PM PDT 24 69558506 ps
T965 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1640968364 May 23 01:26:58 PM PDT 24 May 23 01:27:03 PM PDT 24 81176385 ps
T966 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.2589412965 May 23 01:27:01 PM PDT 24 May 23 01:27:06 PM PDT 24 55031917 ps
T967 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2911777524 May 23 01:26:52 PM PDT 24 May 23 01:26:55 PM PDT 24 533452549 ps
T968 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2158970482 May 23 01:27:03 PM PDT 24 May 23 01:27:08 PM PDT 24 122126835 ps
T122 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.4155006579 May 23 01:27:16 PM PDT 24 May 23 01:27:22 PM PDT 24 62322229 ps
T969 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1388729883 May 23 01:26:56 PM PDT 24 May 23 01:27:05 PM PDT 24 812260719 ps
T970 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.4170345033 May 23 01:26:54 PM PDT 24 May 23 01:26:57 PM PDT 24 35773364 ps
T971 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.1183307860 May 23 01:27:11 PM PDT 24 May 23 01:27:14 PM PDT 24 328729427 ps
T132 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2367627027 May 23 01:27:22 PM PDT 24 May 23 01:27:25 PM PDT 24 43344321 ps
T972 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1563454586 May 23 01:26:46 PM PDT 24 May 23 01:26:49 PM PDT 24 28380803 ps
T973 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4239647788 May 23 01:26:59 PM PDT 24 May 23 01:27:06 PM PDT 24 703184556 ps
T129 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3310024435 May 23 01:27:01 PM PDT 24 May 23 01:27:08 PM PDT 24 226881458 ps
T974 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.671177821 May 23 01:27:14 PM PDT 24 May 23 01:27:18 PM PDT 24 90219752 ps
T975 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2541184916 May 23 01:26:58 PM PDT 24 May 23 01:27:01 PM PDT 24 26869307 ps
T976 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2700275106 May 23 01:26:48 PM PDT 24 May 23 01:26:52 PM PDT 24 214993971 ps
T977 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2830175066 May 23 01:27:02 PM PDT 24 May 23 01:27:09 PM PDT 24 276951786 ps
T126 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1070353747 May 23 01:27:17 PM PDT 24 May 23 01:27:23 PM PDT 24 185966907 ps
T978 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3522488377 May 23 01:27:16 PM PDT 24 May 23 01:27:20 PM PDT 24 59452382 ps
T979 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.3983502328 May 23 01:27:18 PM PDT 24 May 23 01:27:23 PM PDT 24 49086876 ps
T980 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2463324090 May 23 01:27:02 PM PDT 24 May 23 01:27:08 PM PDT 24 290008087 ps
T981 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1991588286 May 23 01:26:59 PM PDT 24 May 23 01:27:03 PM PDT 24 78602289 ps
T982 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.317644141 May 23 01:27:01 PM PDT 24 May 23 01:27:07 PM PDT 24 55675702 ps
T983 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3569061681 May 23 01:27:15 PM PDT 24 May 23 01:27:19 PM PDT 24 36161348 ps
T984 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1217388466 May 23 01:27:13 PM PDT 24 May 23 01:27:18 PM PDT 24 131165594 ps
T985 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.269662296 May 23 01:27:01 PM PDT 24 May 23 01:27:09 PM PDT 24 144473069 ps
T986 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1749784187 May 23 01:27:04 PM PDT 24 May 23 01:27:08 PM PDT 24 16352622 ps
T161 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.347717134 May 23 01:27:14 PM PDT 24 May 23 01:27:17 PM PDT 24 72827009 ps
T162 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3833454776 May 23 01:26:46 PM PDT 24 May 23 01:26:49 PM PDT 24 232934962 ps
T987 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.636539893 May 23 01:27:00 PM PDT 24 May 23 01:27:08 PM PDT 24 148228476 ps
T988 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.1200371837 May 23 01:27:18 PM PDT 24 May 23 01:27:22 PM PDT 24 80754111 ps
T989 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.554800007 May 23 01:27:01 PM PDT 24 May 23 01:27:06 PM PDT 24 21900819 ps
T990 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3651185831 May 23 01:26:58 PM PDT 24 May 23 01:27:01 PM PDT 24 20762251 ps
T991 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1216667704 May 23 01:27:15 PM PDT 24 May 23 01:27:19 PM PDT 24 28615067 ps
T992 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.399765090 May 23 01:26:59 PM PDT 24 May 23 01:27:02 PM PDT 24 31571849 ps
T993 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1588490452 May 23 01:27:00 PM PDT 24 May 23 01:27:05 PM PDT 24 205157353 ps
T163 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3704895510 May 23 01:26:58 PM PDT 24 May 23 01:27:01 PM PDT 24 40648602 ps
T994 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.263715292 May 23 01:26:59 PM PDT 24 May 23 01:27:03 PM PDT 24 114271346 ps
T124 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1681705677 May 23 01:27:13 PM PDT 24 May 23 01:27:18 PM PDT 24 1461020354 ps
T995 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3903002345 May 23 01:26:50 PM PDT 24 May 23 01:27:01 PM PDT 24 751609192 ps
T996 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.4002446167 May 23 01:27:02 PM PDT 24 May 23 01:27:08 PM PDT 24 188260685 ps
T997 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.314779904 May 23 01:26:59 PM PDT 24 May 23 01:27:04 PM PDT 24 317861744 ps
T130 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1472789595 May 23 01:26:52 PM PDT 24 May 23 01:26:55 PM PDT 24 125187665 ps
T998 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1119177759 May 23 01:26:46 PM PDT 24 May 23 01:26:52 PM PDT 24 643961886 ps
T999 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3024732550 May 23 01:27:01 PM PDT 24 May 23 01:27:07 PM PDT 24 347788572 ps
T1000 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.3474422125 May 23 01:26:59 PM PDT 24 May 23 01:27:03 PM PDT 24 29960550 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%