Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94156951

1

T1

24099

T2

7112

T3

9385

auto[1]

1360262

1

T2

891

T3

297

T4

1083

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

94163160

1

T1

24099

T2

7310

T3

9385

auto[1]

1354053

1

T2

693

T3

297

T4

889

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7280374	1			T1	8058		T2	1493		T3	1116
auto[IdleSt]	20536336	1			T1	2193		T2	2783		T3	1760
auto[ClkMuxSt]	34433	1			T1	74		T2	16		T3	6
auto[CntIncrSt]	34231	1			T1	74		T2	16		T3	6
auto[CntProgSt]	1157468	1			T1	148		T2	32		T3	12
auto[TransCheckSt]	26778	1			T1	74		T3	6		T4	30
auto[TokenHashSt]	35871376	1			T1	1807		T3	2195		T4	188529
auto[FlashRmaSt]	27434	1			T1	49		T3	6		T4	95
auto[TokenCheck0St]	12129	1			T1	33		T3	6		T4	30
auto[TokenCheck1St]	8975	1			T1	8		T3	6		T4	30
auto[TransProgSt]	283103	1			T3	12		T4	60		T10	16
auto[PostTransSt]	12071916	1			T1	11581		T2	1305		T3	1732
auto[ScrapSt]	264168	1			T5	587		T6	259		T14	2245
auto[EscalateSt]	6576183	1			T2	2358		T3	1611		T4	6888
auto[InvalidSt]	11330439	1			T3	1208		T4	1604		T10	804

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1870	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11330439	1			T3	1208		T4	1604		T10	804
EscalateSt	6576183	1			T2	2358		T3	1611		T4	6888
ScrapSt	264168	1			T5	587		T6	259		T14	2245
PostTransSt	12071916	1			T1	11581		T2	1305		T3	1732
TransProgSt	283103	1			T3	12		T4	60		T10	16
TokenCheck1St	8975	1			T1	8		T3	6		T4	30
TokenCheck0St	12129	1			T1	33		T3	6		T4	30
FlashRmaSt	27434	1			T1	49		T3	6		T4	95
TokenHashSt	35871376	1			T1	1807		T3	2195		T4	188529
TransCheckSt	26778	1			T1	74		T3	6		T4	30
CntProgSt	1157468	1			T1	148		T2	32		T3	12
CntIncrSt	34231	1			T1	74		T2	16		T3	6
ClkMuxSt	34433	1			T1	74		T2	16		T3	6
IdleSt	20536336	1			T1	2193		T2	2783		T3	1760
ResetSt	7280374	1			T1	8058		T2	1493		T3	1116
arcs[ResetSt=>IdleSt]	52191	1			T1	75		T2	17		T3	13
arcs[IdleSt=>ScrapSt]	272	1			T5	1		T6	1		T14	1
arcs[IdleSt=>ClkMuxSt]	34292	1			T1	74		T2	16		T3	6
arcs[ClkMuxSt=>CntIncrSt]	34231	1			T1	74		T2	16		T3	6
arcs[CntIncrSt=>PostTransSt]	1710	1			T6	21		T14	58		T15	5
arcs[CntIncrSt=>CntProgSt]	32467	1			T1	74		T2	16		T3	6
arcs[CntProgSt=>PostTransSt]	4695	1			T2	16		T4	8		T5	19
arcs[CntProgSt=>TransCheckSt]	26778	1			T1	74		T3	6		T4	30
arcs[TransCheckSt=>PostTransSt]	3593	1			T1	39		T6	17		T14	54
arcs[TransCheckSt=>TokenHashSt]	23021	1			T1	35		T3	6		T4	30
arcs[TokenHashSt=>PostTransSt]	10082	1			T1	2		T6	63		T12	7
arcs[TokenHashSt=>FlashRmaSt]	12215	1			T1	33		T3	6		T4	30
arcs[FlashRmaSt=>TokenCheck0St]	12129	1			T1	33		T3	6		T4	30
arcs[TokenCheck0St=>PostTransSt]	3116	1			T1	25		T6	14		T12	10
arcs[TokenCheck0St=>TokenCheck1St]	8975	1			T1	8		T3	6		T4	30
arcs[TokenCheck1St=>PostTransSt]	665	1			T1	8		T6	1		T14	7
arcs[TransProgSt=>PostTransSt]	7404	1			T3	6		T4	30		T10	8
arcs[IdleSt=>EscalateSt]	193	1			T46	5		T44	10		T45	1
arcs[ClkMuxSt=>EscalateSt]	61	1			T43	1		T44	2		T45	1
arcs[CntIncrSt=>EscalateSt]	54	1			T43	1		T46	1		T44	1
arcs[CntProgSt=>EscalateSt]	994	1			T43	27		T46	9		T44	32
arcs[TransCheckSt=>EscalateSt]	164	1			T43	2		T46	5		T45	4
arcs[TokenHashSt=>EscalateSt]	724	1			T43	3		T46	15		T44	13
arcs[FlashRmaSt=>EscalateSt]	86	1			T43	3		T46	2		T44	1
arcs[TokenCheck0St=>EscalateSt]	38	1			T46	1		T47	1		T51	1
arcs[TokenCheck1St=>EscalateSt]	166	1			T43	1		T46	4		T44	3
arcs[TransProgSt=>EscalateSt]	740	1			T43	15		T46	5		T44	28
arcs[PostTransSt=>EscalateSt]	4958	1			T2	16		T4	8		T5	19
arcs[InvalidSt=>EscalateSt]	13417	1			T3	6		T4	12		T10	5

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7280196	1			T1	8058		T2	1493		T3	1116
auto[0]	auto[IdleSt]	20536210	1			T1	2193		T2	2783		T3	1760
auto[0]	auto[ClkMuxSt]	34390	1			T1	74		T2	16		T3	6
auto[0]	auto[CntIncrSt]	34190	1			T1	74		T2	16		T3	6
auto[0]	auto[CntProgSt]	1156821	1			T1	148		T2	32		T3	12
auto[0]	auto[TransCheckSt]	26674	1			T1	74		T3	6		T4	30
auto[0]	auto[TokenHashSt]	35870891	1			T1	1807		T3	2195		T4	188529
auto[0]	auto[FlashRmaSt]	27377	1			T1	49		T3	6		T4	95
auto[0]	auto[TokenCheck0St]	12108	1			T1	33		T3	6		T4	30
auto[0]	auto[TokenCheck1St]	8859	1			T1	8		T3	6		T4	30
auto[0]	auto[TransProgSt]	282615	1			T3	12		T4	60		T10	16
auto[0]	auto[PostTransSt]	12069391	1			T1	11581		T2	1296		T3	1732
auto[0]	auto[ScrapSt]	264129	1			T5	587		T6	259		T14	2245
auto[0]	auto[EscalateSt]	5227521	1			T2	1476		T3	1317		T4	5816
auto[0]	auto[InvalidSt]	11323709	1			T3	1205		T4	1599		T10	802
auto[1]	auto[ResetSt]	178	1			T43	2		T46	2		T44	6
auto[1]	auto[IdleSt]	126	1			T46	4		T44	7		T47	8
auto[1]	auto[ClkMuxSt]	43	1			T44	2		T45	1		T51	1
auto[1]	auto[CntIncrSt]	41	1			T43	1		T46	1		T44	1
auto[1]	auto[CntProgSt]	647	1			T43	15		T46	5		T44	22
auto[1]	auto[TransCheckSt]	104	1			T46	3		T45	2		T215	3
auto[1]	auto[TokenHashSt]	485	1			T43	2		T46	9		T44	10
auto[1]	auto[FlashRmaSt]	57	1			T43	2		T46	1		T44	1
auto[1]	auto[TokenCheck0St]	21	1			T171	1		T216	3		T217	1
auto[1]	auto[TokenCheck1St]	116	1			T43	1		T46	4		T44	2
auto[1]	auto[TransProgSt]	488	1			T43	13		T46	3		T44	20
auto[1]	auto[PostTransSt]	2525	1			T2	9		T4	6		T5	9
auto[1]	auto[ScrapSt]	39	1			T43	3		T46	1		T47	1
auto[1]	auto[EscalateSt]	1348662	1			T2	882		T3	294		T4	1072
auto[1]	auto[InvalidSt]	6730	1			T3	3		T4	5		T10	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7280217	1			T1	8058		T2	1493		T3	1116
auto[0]	auto[IdleSt]	20536202	1			T1	2193		T2	2783		T3	1760
auto[0]	auto[ClkMuxSt]	34393	1			T1	74		T2	16		T3	6
auto[0]	auto[CntIncrSt]	34195	1			T1	74		T2	16		T3	6
auto[0]	auto[CntProgSt]	1156792	1			T1	148		T2	32		T3	12
auto[0]	auto[TransCheckSt]	26663	1			T1	74		T3	6		T4	30
auto[0]	auto[TokenHashSt]	35870895	1			T1	1807		T3	2195		T4	188529
auto[0]	auto[FlashRmaSt]	27379	1			T1	49		T3	6		T4	95
auto[0]	auto[TokenCheck0St]	12105	1			T1	33		T3	6		T4	30
auto[0]	auto[TokenCheck1St]	8873	1			T1	8		T3	6		T4	30
auto[0]	auto[TransProgSt]	282611	1			T3	12		T4	60		T10	16
auto[0]	auto[PostTransSt]	12069408	1			T1	11581		T2	1298		T3	1732
auto[0]	auto[ScrapSt]	264128	1			T5	587		T6	259		T14	2245
auto[0]	auto[EscalateSt]	5233677	1			T2	1672		T3	1317		T4	6008
auto[0]	auto[InvalidSt]	11323752	1			T3	1205		T4	1597		T10	801
auto[1]	auto[ResetSt]	157	1			T43	2		T46	3		T44	4
auto[1]	auto[IdleSt]	134	1			T46	4		T44	8		T45	1
auto[1]	auto[ClkMuxSt]	40	1			T43	1		T44	2		T45	1
auto[1]	auto[CntIncrSt]	36	1			T43	1		T46	1		T44	1
auto[1]	auto[CntProgSt]	676	1			T43	19		T46	8		T44	25
auto[1]	auto[TransCheckSt]	115	1			T43	2		T46	3		T45	2
auto[1]	auto[TokenHashSt]	481	1			T43	2		T46	8		T44	9
auto[1]	auto[FlashRmaSt]	55	1			T43	3		T46	1		T45	2
auto[1]	auto[TokenCheck0St]	24	1			T46	1		T47	1		T51	1
auto[1]	auto[TokenCheck1St]	102	1			T43	1		T46	1		T44	1
auto[1]	auto[TransProgSt]	492	1			T43	9		T46	5		T44	20
auto[1]	auto[PostTransSt]	2508	1			T2	7		T4	2		T5	10
auto[1]	auto[ScrapSt]	40	1			T46	1		T47	2		T51	2
auto[1]	auto[EscalateSt]	1342506	1			T2	686		T3	294		T4	880
auto[1]	auto[InvalidSt]	6687	1			T3	3		T4	7		T10	3