Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49547 |
1 |
|
|
T1 |
13 |
|
T2 |
201 |
|
T3 |
85 |
auto[1] |
1739 |
1 |
|
|
T2 |
8 |
|
T15 |
7 |
|
T16 |
5 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50552 |
1 |
|
|
T1 |
13 |
|
T2 |
209 |
|
T3 |
72 |
auto[1] |
734 |
1 |
|
|
T3 |
13 |
|
T37 |
16 |
|
T62 |
16 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49558 |
1 |
|
|
T1 |
13 |
|
T2 |
200 |
|
T3 |
85 |
auto[1] |
1728 |
1 |
|
|
T2 |
9 |
|
T4 |
1 |
|
T14 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49578 |
1 |
|
|
T1 |
10 |
|
T2 |
200 |
|
T3 |
85 |
auto[1] |
1708 |
1 |
|
|
T1 |
3 |
|
T2 |
9 |
|
T4 |
1 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49648 |
1 |
|
|
T1 |
13 |
|
T2 |
199 |
|
T3 |
85 |
auto[1] |
1638 |
1 |
|
|
T2 |
10 |
|
T14 |
2 |
|
T48 |
7 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
46761 |
1 |
|
|
T1 |
7 |
|
T2 |
162 |
|
T3 |
85 |
no_err_inj |
4525 |
1 |
|
|
T1 |
6 |
|
T2 |
47 |
|
T4 |
6 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49565 |
1 |
|
|
T1 |
13 |
|
T2 |
198 |
|
T3 |
85 |
auto[1] |
1721 |
1 |
|
|
T2 |
11 |
|
T15 |
12 |
|
T16 |
17 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50539 |
1 |
|
|
T1 |
13 |
|
T2 |
209 |
|
T3 |
67 |
auto[1] |
747 |
1 |
|
|
T3 |
18 |
|
T37 |
13 |
|
T62 |
12 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
37051 |
1 |
|
|
T1 |
13 |
|
T2 |
103 |
|
T3 |
85 |
auto[1] |
14235 |
1 |
|
|
T2 |
106 |
|
T4 |
10 |
|
T5 |
7 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49607 |
1 |
|
|
T1 |
12 |
|
T2 |
203 |
|
T3 |
85 |
auto[1] |
1679 |
1 |
|
|
T1 |
1 |
|
T2 |
6 |
|
T48 |
3 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49582 |
1 |
|
|
T1 |
13 |
|
T2 |
204 |
|
T3 |
85 |
auto[1] |
1704 |
1 |
|
|
T2 |
5 |
|
T48 |
4 |
|
T27 |
4 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49615 |
1 |
|
|
T1 |
12 |
|
T2 |
201 |
|
T3 |
85 |
auto[1] |
1671 |
1 |
|
|
T1 |
1 |
|
T2 |
8 |
|
T40 |
1 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49457 |
1 |
|
|
T1 |
13 |
|
T2 |
198 |
|
T3 |
85 |
auto[1] |
1829 |
1 |
|
|
T2 |
11 |
|
T15 |
9 |
|
T16 |
14 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49417 |
1 |
|
|
T1 |
13 |
|
T2 |
194 |
|
T3 |
85 |
auto[1] |
1869 |
1 |
|
|
T2 |
15 |
|
T26 |
19 |
|
T61 |
3 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50552 |
1 |
|
|
T1 |
13 |
|
T2 |
209 |
|
T3 |
71 |
auto[1] |
734 |
1 |
|
|
T3 |
14 |
|
T37 |
13 |
|
T62 |
16 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50513 |
1 |
|
|
T1 |
13 |
|
T2 |
209 |
|
T3 |
64 |
auto[1] |
773 |
1 |
|
|
T3 |
21 |
|
T37 |
22 |
|
T62 |
23 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50533 |
1 |
|
|
T1 |
13 |
|
T2 |
209 |
|
T3 |
66 |
auto[1] |
753 |
1 |
|
|
T3 |
19 |
|
T37 |
11 |
|
T62 |
13 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48829 |
1 |
|
|
T2 |
199 |
|
T3 |
85 |
|
T5 |
7 |
auto[1] |
2457 |
1 |
|
|
T1 |
13 |
|
T2 |
10 |
|
T4 |
10 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47532 |
1 |
|
|
T1 |
13 |
|
T2 |
209 |
|
T3 |
85 |
auto[1] |
3754 |
1 |
|
|
T22 |
97 |
|
T38 |
62 |
|
T50 |
89 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49470 |
1 |
|
|
T1 |
13 |
|
T2 |
201 |
|
T3 |
85 |
auto[1] |
1816 |
1 |
|
|
T2 |
8 |
|
T14 |
2 |
|
T48 |
5 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49607 |
1 |
|
|
T1 |
12 |
|
T2 |
202 |
|
T3 |
85 |
auto[1] |
1679 |
1 |
|
|
T1 |
1 |
|
T2 |
7 |
|
T4 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49557 |
1 |
|
|
T1 |
12 |
|
T2 |
202 |
|
T3 |
85 |
auto[1] |
1729 |
1 |
|
|
T1 |
1 |
|
T2 |
7 |
|
T4 |
1 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49453 |
1 |
|
|
T1 |
13 |
|
T2 |
205 |
|
T3 |
85 |
auto[1] |
1833 |
1 |
|
|
T2 |
4 |
|
T15 |
8 |
|
T16 |
7 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
45657 |
1 |
|
|
T1 |
13 |
|
T2 |
197 |
|
T3 |
85 |
auto[1] |
5629 |
1 |
|
|
T2 |
12 |
|
T15 |
5 |
|
T24 |
75 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47433 |
1 |
|
|
T1 |
13 |
|
T2 |
209 |
|
T3 |
85 |
auto[1] |
3853 |
1 |
|
|
T20 |
64 |
|
T23 |
94 |
|
T17 |
91 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51286 |
1 |
|
|
T1 |
13 |
|
T2 |
209 |
|
T3 |
85 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49502 |
1 |
|
|
T1 |
13 |
|
T2 |
190 |
|
T3 |
85 |
auto[1] |
1784 |
1 |
|
|
T2 |
19 |
|
T15 |
9 |
|
T16 |
8 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49507 |
1 |
|
|
T1 |
13 |
|
T2 |
202 |
|
T3 |
85 |
auto[1] |
1779 |
1 |
|
|
T2 |
7 |
|
T15 |
14 |
|
T16 |
9 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49408 |
1 |
|
|
T1 |
13 |
|
T2 |
203 |
|
T3 |
85 |
auto[1] |
1878 |
1 |
|
|
T2 |
6 |
|
T15 |
14 |
|
T16 |
15 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
45551 |
1 |
|
|
T2 |
159 |
|
T3 |
85 |
|
T20 |
64 |
auto[0] |
no_err_inj |
3278 |
1 |
|
|
T2 |
40 |
|
T5 |
7 |
|
T11 |
1 |
auto[1] |
err_inj |
1210 |
1 |
|
|
T1 |
7 |
|
T2 |
3 |
|
T4 |
4 |
auto[1] |
no_err_inj |
1247 |
1 |
|
|
T1 |
6 |
|
T2 |
7 |
|
T4 |
6 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47278 |
1 |
|
|
T2 |
192 |
|
T3 |
85 |
|
T5 |
7 |
auto[0] |
auto[1] |
1551 |
1 |
|
|
T2 |
7 |
|
T48 |
11 |
|
T27 |
7 |
auto[1] |
auto[0] |
2329 |
1 |
|
|
T1 |
12 |
|
T2 |
10 |
|
T4 |
9 |
auto[1] |
auto[1] |
128 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T14 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47248 |
1 |
|
|
T2 |
195 |
|
T3 |
85 |
|
T5 |
7 |
auto[0] |
auto[1] |
1581 |
1 |
|
|
T2 |
4 |
|
T48 |
4 |
|
T27 |
4 |
auto[1] |
auto[0] |
2334 |
1 |
|
|
T1 |
13 |
|
T2 |
9 |
|
T4 |
10 |
auto[1] |
auto[1] |
123 |
1 |
|
|
T2 |
1 |
|
T44 |
3 |
|
T45 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47245 |
1 |
|
|
T2 |
192 |
|
T3 |
85 |
|
T5 |
7 |
auto[0] |
auto[1] |
1584 |
1 |
|
|
T2 |
7 |
|
T48 |
13 |
|
T27 |
8 |
auto[1] |
auto[0] |
2312 |
1 |
|
|
T1 |
12 |
|
T2 |
10 |
|
T4 |
9 |
auto[1] |
auto[1] |
145 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T14 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47264 |
1 |
|
|
T2 |
191 |
|
T3 |
85 |
|
T5 |
7 |
auto[0] |
auto[1] |
1565 |
1 |
|
|
T2 |
8 |
|
T48 |
5 |
|
T27 |
5 |
auto[1] |
auto[0] |
2314 |
1 |
|
|
T1 |
10 |
|
T2 |
9 |
|
T4 |
9 |
auto[1] |
auto[1] |
143 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47317 |
1 |
|
|
T2 |
189 |
|
T3 |
85 |
|
T5 |
7 |
auto[0] |
auto[1] |
1512 |
1 |
|
|
T2 |
10 |
|
T48 |
7 |
|
T27 |
9 |
auto[1] |
auto[0] |
2331 |
1 |
|
|
T1 |
13 |
|
T2 |
10 |
|
T4 |
10 |
auto[1] |
auto[1] |
126 |
1 |
|
|
T14 |
2 |
|
T86 |
1 |
|
T19 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
47227 |
1 |
|
|
T2 |
190 |
|
T3 |
85 |
|
T5 |
7 |
auto[0] |
auto[1] |
1602 |
1 |
|
|
T2 |
9 |
|
T48 |
9 |
|
T27 |
9 |
auto[1] |
auto[0] |
2331 |
1 |
|
|
T1 |
13 |
|
T2 |
10 |
|
T4 |
9 |
auto[1] |
auto[1] |
126 |
1 |
|
|
T4 |
1 |
|
T14 |
1 |
|
T40 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35984 |
1 |
|
|
T1 |
13 |
|
T2 |
103 |
|
T3 |
85 |
auto[0] |
auto[1] |
1067 |
1 |
|
|
T15 |
7 |
|
T19 |
7 |
|
T44 |
21 |
auto[1] |
auto[0] |
13563 |
1 |
|
|
T2 |
98 |
|
T4 |
10 |
|
T5 |
7 |
auto[1] |
auto[1] |
672 |
1 |
|
|
T2 |
8 |
|
T16 |
5 |
|
T44 |
10 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36030 |
1 |
|
|
T1 |
13 |
|
T2 |
103 |
|
T3 |
85 |
auto[0] |
auto[1] |
1021 |
1 |
|
|
T15 |
12 |
|
T19 |
5 |
|
T44 |
13 |
auto[1] |
auto[0] |
13535 |
1 |
|
|
T2 |
95 |
|
T4 |
10 |
|
T5 |
7 |
auto[1] |
auto[1] |
700 |
1 |
|
|
T2 |
11 |
|
T16 |
17 |
|
T44 |
12 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35910 |
1 |
|
|
T1 |
13 |
|
T2 |
91 |
|
T3 |
85 |
auto[0] |
auto[1] |
1141 |
1 |
|
|
T2 |
12 |
|
T26 |
19 |
|
T61 |
3 |
auto[1] |
auto[0] |
13507 |
1 |
|
|
T2 |
103 |
|
T4 |
10 |
|
T5 |
7 |
auto[1] |
auto[1] |
728 |
1 |
|
|
T2 |
3 |
|
T28 |
10 |
|
T220 |
20 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35931 |
1 |
|
|
T1 |
13 |
|
T2 |
103 |
|
T3 |
85 |
auto[0] |
auto[1] |
1120 |
1 |
|
|
T15 |
9 |
|
T19 |
14 |
|
T44 |
21 |
auto[1] |
auto[0] |
13526 |
1 |
|
|
T2 |
95 |
|
T4 |
10 |
|
T5 |
7 |
auto[1] |
auto[1] |
709 |
1 |
|
|
T2 |
11 |
|
T16 |
14 |
|
T44 |
18 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32143 |
1 |
|
|
T1 |
13 |
|
T2 |
103 |
|
T3 |
85 |
auto[0] |
auto[1] |
4908 |
1 |
|
|
T15 |
5 |
|
T24 |
75 |
|
T18 |
93 |
auto[1] |
auto[0] |
13514 |
1 |
|
|
T2 |
94 |
|
T4 |
10 |
|
T5 |
7 |
auto[1] |
auto[1] |
721 |
1 |
|
|
T2 |
12 |
|
T16 |
6 |
|
T44 |
11 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36000 |
1 |
|
|
T1 |
12 |
|
T2 |
96 |
|
T3 |
85 |
auto[0] |
auto[1] |
1051 |
1 |
|
|
T1 |
1 |
|
T2 |
7 |
|
T14 |
1 |
auto[1] |
auto[0] |
13607 |
1 |
|
|
T2 |
106 |
|
T4 |
9 |
|
T5 |
7 |
auto[1] |
auto[1] |
628 |
1 |
|
|
T4 |
1 |
|
T27 |
7 |
|
T44 |
3 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35909 |
1 |
|
|
T1 |
13 |
|
T2 |
95 |
|
T3 |
85 |
auto[0] |
auto[1] |
1142 |
1 |
|
|
T2 |
8 |
|
T14 |
2 |
|
T48 |
5 |
auto[1] |
auto[0] |
13561 |
1 |
|
|
T2 |
106 |
|
T4 |
10 |
|
T5 |
7 |
auto[1] |
auto[1] |
674 |
1 |
|
|
T27 |
11 |
|
T44 |
7 |
|
T45 |
2 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35991 |
1 |
|
|
T1 |
13 |
|
T2 |
98 |
|
T3 |
85 |
auto[0] |
auto[1] |
1060 |
1 |
|
|
T2 |
5 |
|
T48 |
4 |
|
T19 |
12 |
auto[1] |
auto[0] |
13591 |
1 |
|
|
T2 |
106 |
|
T4 |
10 |
|
T5 |
7 |
auto[1] |
auto[1] |
644 |
1 |
|
|
T27 |
4 |
|
T44 |
5 |
|
T45 |
2 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
36072 |
1 |
|
|
T1 |
12 |
|
T2 |
97 |
|
T3 |
85 |
auto[0] |
auto[1] |
979 |
1 |
|
|
T1 |
1 |
|
T2 |
6 |
|
T48 |
3 |
auto[1] |
auto[0] |
13535 |
1 |
|
|
T2 |
106 |
|
T4 |
10 |
|
T5 |
7 |
auto[1] |
auto[1] |
700 |
1 |
|
|
T27 |
6 |
|
T44 |
8 |
|
T148 |
9 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35977 |
1 |
|
|
T1 |
10 |
|
T2 |
94 |
|
T3 |
85 |
auto[0] |
auto[1] |
1074 |
1 |
|
|
T1 |
3 |
|
T2 |
9 |
|
T40 |
1 |
auto[1] |
auto[0] |
13601 |
1 |
|
|
T2 |
106 |
|
T4 |
9 |
|
T5 |
7 |
auto[1] |
auto[1] |
634 |
1 |
|
|
T4 |
1 |
|
T27 |
5 |
|
T44 |
3 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35950 |
1 |
|
|
T1 |
13 |
|
T2 |
94 |
|
T3 |
85 |
auto[0] |
auto[1] |
1101 |
1 |
|
|
T2 |
9 |
|
T14 |
1 |
|
T40 |
1 |
auto[1] |
auto[0] |
13608 |
1 |
|
|
T2 |
106 |
|
T4 |
9 |
|
T5 |
7 |
auto[1] |
auto[1] |
627 |
1 |
|
|
T4 |
1 |
|
T27 |
9 |
|
T44 |
6 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35926 |
1 |
|
|
T1 |
13 |
|
T2 |
103 |
|
T3 |
85 |
auto[0] |
auto[1] |
1125 |
1 |
|
|
T15 |
14 |
|
T19 |
12 |
|
T44 |
14 |
auto[1] |
auto[0] |
13482 |
1 |
|
|
T2 |
100 |
|
T4 |
10 |
|
T5 |
7 |
auto[1] |
auto[1] |
753 |
1 |
|
|
T2 |
6 |
|
T16 |
15 |
|
T44 |
16 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35973 |
1 |
|
|
T1 |
13 |
|
T2 |
103 |
|
T3 |
85 |
auto[0] |
auto[1] |
1078 |
1 |
|
|
T15 |
14 |
|
T19 |
9 |
|
T44 |
8 |
auto[1] |
auto[0] |
13534 |
1 |
|
|
T2 |
99 |
|
T4 |
10 |
|
T5 |
7 |
auto[1] |
auto[1] |
701 |
1 |
|
|
T2 |
7 |
|
T16 |
9 |
|
T44 |
10 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35634 |
1 |
|
|
T2 |
93 |
|
T3 |
85 |
|
T11 |
1 |
auto[0] |
auto[1] |
1417 |
1 |
|
|
T1 |
13 |
|
T2 |
10 |
|
T14 |
12 |
auto[1] |
auto[0] |
13195 |
1 |
|
|
T2 |
106 |
|
T5 |
7 |
|
T21 |
2 |
auto[1] |
auto[1] |
1040 |
1 |
|
|
T4 |
10 |
|
T45 |
15 |
|
T93 |
11 |