Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93924502

1

T1

10007

T2

637223

T3

74884

auto[1]

1302729

1

T1

198

T2

3860

T3

1584

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

93931625

1

T1

9908

T2

637323

T3

74686

auto[1]

1295606

1

T1

297

T2

3760

T3

1782

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6837751	1			T1	1189		T2	19915		T3	9079
auto[IdleSt]	20088367	1			T1	1064		T2	110710		T3	2114
auto[ClkMuxSt]	34758	1			T1	6		T2	142		T3	64
auto[CntIncrSt]	34545	1			T1	6		T2	138		T3	64
auto[CntProgSt]	1560529	1			T1	96		T2	254		T3	2137
auto[TransCheckSt]	27232	1			T1	6		T2	108		T3	51
auto[TokenHashSt]	38543541	1			T1	5440		T2	418134		T3	47542
auto[FlashRmaSt]	27951	1			T1	26		T2	78		T3	73
auto[TokenCheck0St]	12288	1			T1	6		T2	51		T3	41
auto[TokenCheck1St]	9103	1			T1	6		T2	41		T3	24
auto[TransProgSt]	344735	1			T1	51		T2	80		T3	968
auto[PostTransSt]	12306197	1			T1	1010		T2	74351		T3	8413
auto[ScrapSt]	133302	1			T2	293		T22	3		T39	191
auto[EscalateSt]	5880518	1			T1	861		T2	12748		T3	4354
auto[InvalidSt]	9384640	1			T1	438		T2	4035		T3	1544

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1774	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	9384640	1			T1	438		T2	4035		T3	1544
EscalateSt	5880518	1			T1	861		T2	12748		T3	4354
ScrapSt	133302	1			T2	293		T22	3		T39	191
PostTransSt	12306197	1			T1	1010		T2	74351		T3	8413
TransProgSt	344735	1			T1	51		T2	80		T3	968
TokenCheck1St	9103	1			T1	6		T2	41		T3	24
TokenCheck0St	12288	1			T1	6		T2	51		T3	41
FlashRmaSt	27951	1			T1	26		T2	78		T3	73
TokenHashSt	38543541	1			T1	5440		T2	418134		T3	47542
TransCheckSt	27232	1			T1	6		T2	108		T3	51
CntProgSt	1560529	1			T1	96		T2	254		T3	2137
CntIncrSt	34545	1			T1	6		T2	138		T3	64
ClkMuxSt	34758	1			T1	6		T2	142		T3	64
IdleSt	20088367	1			T1	1064		T2	110710		T3	2114
ResetSt	6837751	1			T1	1189		T2	19915		T3	9079
arcs[ResetSt=>IdleSt]	51665	1			T1	13		T2	207		T3	86
arcs[IdleSt=>ScrapSt]	291	1			T2	2		T22	1		T39	1
arcs[IdleSt=>ClkMuxSt]	34595	1			T1	6		T2	138		T3	64
arcs[ClkMuxSt=>CntIncrSt]	34545	1			T1	6		T2	138		T3	64
arcs[CntIncrSt=>PostTransSt]	1781	1			T2	7		T15	14		T16	9
arcs[CntIncrSt=>CntProgSt]	32709	1			T1	6		T2	131		T3	64
arcs[CntProgSt=>PostTransSt]	4317	1			T2	23		T3	13		T26	19
arcs[CntProgSt=>TransCheckSt]	27232	1			T1	6		T2	108		T3	51
arcs[TransCheckSt=>PostTransSt]	3770	1			T2	6		T20	42		T23	50
arcs[TransCheckSt=>TokenHashSt]	23344	1			T1	6		T2	102		T3	51
arcs[TokenHashSt=>PostTransSt]	10308	1			T2	51		T3	10		T20	2
arcs[TokenHashSt=>FlashRmaSt]	12388	1			T1	6		T2	51		T3	41
arcs[FlashRmaSt=>TokenCheck0St]	12288	1			T1	6		T2	51		T3	41
arcs[TokenCheck0St=>PostTransSt]	3170	1			T2	10		T3	17		T20	12
arcs[TokenCheck0St=>TokenCheck1St]	9103	1			T1	6		T2	41		T3	24
arcs[TokenCheck1St=>PostTransSt]	684	1			T2	1		T20	8		T23	12
arcs[TransProgSt=>PostTransSt]	7499	1			T1	6		T2	40		T3	24
arcs[IdleSt=>EscalateSt]	177	1			T22	6		T51	12		T52	6
arcs[ClkMuxSt=>EscalateSt]	50	1			T22	1		T38	4		T50	2
arcs[CntIncrSt=>EscalateSt]	55	1			T22	4		T38	2		T50	1
arcs[CntProgSt=>EscalateSt]	1160	1			T22	41		T38	25		T50	9
arcs[TransCheckSt=>EscalateSt]	118	1			T38	1		T50	11		T56	10
arcs[TokenHashSt=>EscalateSt]	648	1			T22	11		T38	4		T50	27
arcs[FlashRmaSt=>EscalateSt]	100	1			T22	3		T38	2		T50	4
arcs[TokenCheck0St=>EscalateSt]	15	1			T38	1		T50	1		T55	1
arcs[TokenCheck1St=>EscalateSt]	163	1			T22	7		T38	5		T50	2
arcs[TransProgSt=>EscalateSt]	757	1			T22	16		T38	9		T50	11
arcs[PostTransSt=>EscalateSt]	4542	1			T2	23		T3	13		T26	19
arcs[InvalidSt=>EscalateSt]	12735	1			T1	5		T2	54		T3	21

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6837594	1			T1	1189		T2	19915		T3	9079
auto[0]	auto[IdleSt]	20088256	1			T1	1064		T2	110710		T3	2114
auto[0]	auto[ClkMuxSt]	34721	1			T1	6		T2	142		T3	64
auto[0]	auto[CntIncrSt]	34508	1			T1	6		T2	138		T3	64
auto[0]	auto[CntProgSt]	1559756	1			T1	96		T2	254		T3	2137
auto[0]	auto[TransCheckSt]	27162	1			T1	6		T2	108		T3	51
auto[0]	auto[TokenHashSt]	38543099	1			T1	5440		T2	418134		T3	47542
auto[0]	auto[FlashRmaSt]	27890	1			T1	26		T2	78		T3	73
auto[0]	auto[TokenCheck0St]	12283	1			T1	6		T2	51		T3	41
auto[0]	auto[TokenCheck1St]	8997	1			T1	6		T2	41		T3	24
auto[0]	auto[TransProgSt]	344234	1			T1	51		T2	80		T3	968
auto[0]	auto[PostTransSt]	12303936	1			T1	1010		T2	74337		T3	8409
auto[0]	auto[ScrapSt]	133251	1			T2	293		T22	2		T39	191
auto[0]	auto[EscalateSt]	4588848	1			T1	665		T2	8927		T3	2786
auto[0]	auto[InvalidSt]	9378193	1			T1	436		T2	4010		T3	1532
auto[1]	auto[ResetSt]	157	1			T22	3		T38	4		T50	3
auto[1]	auto[IdleSt]	111	1			T22	4		T51	7		T52	1
auto[1]	auto[ClkMuxSt]	37	1			T38	4		T50	1		T52	2
auto[1]	auto[CntIncrSt]	37	1			T22	3		T38	2		T50	1
auto[1]	auto[CntProgSt]	773	1			T22	30		T38	19		T50	6
auto[1]	auto[TransCheckSt]	70	1			T50	5		T56	6		T216	6
auto[1]	auto[TokenHashSt]	442	1			T22	8		T38	3		T50	20
auto[1]	auto[FlashRmaSt]	61	1			T22	2		T38	2		T50	2
auto[1]	auto[TokenCheck0St]	5	1			T217	1		T218	1		T219	1
auto[1]	auto[TokenCheck1St]	106	1			T22	4		T38	3		T50	1
auto[1]	auto[TransProgSt]	501	1			T22	12		T38	5		T50	7
auto[1]	auto[PostTransSt]	2261	1			T2	14		T3	4		T26	9
auto[1]	auto[ScrapSt]	51	1			T22	1		T50	2		T53	2
auto[1]	auto[EscalateSt]	1291670	1			T1	196		T2	3821		T3	1568
auto[1]	auto[InvalidSt]	6447	1			T1	2		T2	25		T3	12

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6837584	1			T1	1189		T2	19915		T3	9079
auto[0]	auto[IdleSt]	20088246	1			T1	1064		T2	110710		T3	2114
auto[0]	auto[ClkMuxSt]	34723	1			T1	6		T2	142		T3	64
auto[0]	auto[CntIncrSt]	34506	1			T1	6		T2	138		T3	64
auto[0]	auto[CntProgSt]	1559778	1			T1	96		T2	254		T3	2137
auto[0]	auto[TransCheckSt]	27153	1			T1	6		T2	108		T3	51
auto[0]	auto[TokenHashSt]	38543108	1			T1	5440		T2	418134		T3	47542
auto[0]	auto[FlashRmaSt]	27881	1			T1	26		T2	78		T3	73
auto[0]	auto[TokenCheck0St]	12276	1			T1	6		T2	51		T3	41
auto[0]	auto[TokenCheck1St]	8997	1			T1	6		T2	41		T3	24
auto[0]	auto[TransProgSt]	344242	1			T1	51		T2	80		T3	968
auto[0]	auto[PostTransSt]	12303854	1			T1	1010		T2	74342		T3	8404
auto[0]	auto[ScrapSt]	133263	1			T2	293		T22	3		T39	191
auto[0]	auto[EscalateSt]	4595888	1			T1	567		T2	9026		T3	2590
auto[0]	auto[InvalidSt]	9378352	1			T1	435		T2	4006		T3	1535
auto[1]	auto[ResetSt]	167	1			T22	4		T38	6		T50	3
auto[1]	auto[IdleSt]	121	1			T22	3		T51	9		T52	5
auto[1]	auto[ClkMuxSt]	35	1			T22	1		T38	3		T50	1
auto[1]	auto[CntIncrSt]	39	1			T22	2		T38	1		T50	1
auto[1]	auto[CntProgSt]	751	1			T22	19		T38	14		T50	5
auto[1]	auto[TransCheckSt]	79	1			T38	1		T50	9		T56	6
auto[1]	auto[TokenHashSt]	433	1			T22	7		T38	3		T50	19
auto[1]	auto[FlashRmaSt]	70	1			T22	3		T38	1		T50	4
auto[1]	auto[TokenCheck0St]	12	1			T38	1		T50	1		T55	1
auto[1]	auto[TokenCheck1St]	106	1			T22	4		T38	4		T50	1
auto[1]	auto[TransProgSt]	493	1			T22	10		T38	6		T50	7
auto[1]	auto[PostTransSt]	2343	1			T2	9		T3	9		T26	10
auto[1]	auto[ScrapSt]	39	1			T53	1		T52	1		T216	3
auto[1]	auto[EscalateSt]	1284630	1			T1	294		T2	3722		T3	1764
auto[1]	auto[InvalidSt]	6288	1			T1	3		T2	29		T3	9