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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.17 97.82 95.93 93.31 100.00 98.52 98.51 96.11


Total test records in report: 998
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T819 /workspace/coverage/default/6.lc_ctrl_jtag_access.915926190 May 28 02:46:57 PM PDT 24 May 28 02:47:22 PM PDT 24 5092584943 ps
T820 /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3611482872 May 28 02:47:04 PM PDT 24 May 28 02:47:27 PM PDT 24 244594770 ps
T821 /workspace/coverage/default/9.lc_ctrl_sec_mubi.2513998476 May 28 02:47:09 PM PDT 24 May 28 02:47:29 PM PDT 24 405572824 ps
T822 /workspace/coverage/default/12.lc_ctrl_errors.1117667698 May 28 02:47:15 PM PDT 24 May 28 02:47:37 PM PDT 24 303130696 ps
T823 /workspace/coverage/default/5.lc_ctrl_prog_failure.3906570991 May 28 02:46:59 PM PDT 24 May 28 02:47:13 PM PDT 24 65572054 ps
T149 /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.861811075 May 28 02:47:42 PM PDT 24 May 28 02:54:24 PM PDT 24 438582730549 ps
T824 /workspace/coverage/default/25.lc_ctrl_state_post_trans.159841121 May 28 02:47:59 PM PDT 24 May 28 02:48:08 PM PDT 24 62511589 ps
T825 /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3848068267 May 28 02:46:56 PM PDT 24 May 28 02:47:24 PM PDT 24 643552514 ps
T826 /workspace/coverage/default/38.lc_ctrl_prog_failure.425448834 May 28 02:48:26 PM PDT 24 May 28 02:48:32 PM PDT 24 17145129 ps
T105 /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.892967609 May 28 02:47:57 PM PDT 24 May 28 02:50:32 PM PDT 24 6784523534 ps
T827 /workspace/coverage/default/44.lc_ctrl_prog_failure.627263367 May 28 02:48:49 PM PDT 24 May 28 02:48:58 PM PDT 24 322554031 ps
T828 /workspace/coverage/default/26.lc_ctrl_stress_all.3675828175 May 28 02:48:08 PM PDT 24 May 28 02:51:31 PM PDT 24 52661297861 ps
T829 /workspace/coverage/default/12.lc_ctrl_alert_test.4006656854 May 28 02:47:14 PM PDT 24 May 28 02:47:26 PM PDT 24 202553541 ps
T830 /workspace/coverage/default/1.lc_ctrl_state_post_trans.2311898104 May 28 02:46:29 PM PDT 24 May 28 02:46:48 PM PDT 24 163718185 ps
T831 /workspace/coverage/default/37.lc_ctrl_security_escalation.930725670 May 28 02:48:46 PM PDT 24 May 28 02:49:00 PM PDT 24 2030693770 ps
T832 /workspace/coverage/default/31.lc_ctrl_state_failure.2275811908 May 28 02:48:14 PM PDT 24 May 28 02:48:45 PM PDT 24 1022482362 ps
T833 /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2573821940 May 28 02:46:41 PM PDT 24 May 28 02:46:58 PM PDT 24 61280207 ps
T834 /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2968813762 May 28 02:47:17 PM PDT 24 May 28 02:48:13 PM PDT 24 5911423326 ps
T835 /workspace/coverage/default/35.lc_ctrl_prog_failure.3785043144 May 28 02:48:19 PM PDT 24 May 28 02:48:29 PM PDT 24 323972136 ps
T836 /workspace/coverage/default/16.lc_ctrl_state_post_trans.3054007036 May 28 02:47:43 PM PDT 24 May 28 02:47:56 PM PDT 24 441013923 ps
T837 /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3013391553 May 28 02:48:23 PM PDT 24 May 28 02:48:40 PM PDT 24 273766449 ps
T165 /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.426240414 May 28 02:47:51 PM PDT 24 May 28 02:54:47 PM PDT 24 156220142881 ps
T838 /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2953583358 May 28 02:48:57 PM PDT 24 May 28 02:49:17 PM PDT 24 341427299 ps
T839 /workspace/coverage/default/32.lc_ctrl_smoke.3702062714 May 28 02:48:15 PM PDT 24 May 28 02:48:24 PM PDT 24 137811977 ps
T840 /workspace/coverage/default/44.lc_ctrl_state_failure.1911018495 May 28 02:48:40 PM PDT 24 May 28 02:49:15 PM PDT 24 1395631858 ps
T841 /workspace/coverage/default/5.lc_ctrl_state_failure.3333105076 May 28 02:46:57 PM PDT 24 May 28 02:47:42 PM PDT 24 293797986 ps
T842 /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1718067433 May 28 02:47:25 PM PDT 24 May 28 02:47:45 PM PDT 24 1815053914 ps
T843 /workspace/coverage/default/12.lc_ctrl_prog_failure.3734400866 May 28 02:47:14 PM PDT 24 May 28 02:47:28 PM PDT 24 54618878 ps
T75 /workspace/coverage/default/36.lc_ctrl_alert_test.3877451482 May 28 02:48:26 PM PDT 24 May 28 02:48:31 PM PDT 24 33546519 ps
T844 /workspace/coverage/default/11.lc_ctrl_smoke.3326686657 May 28 02:47:10 PM PDT 24 May 28 02:47:24 PM PDT 24 89180737 ps
T845 /workspace/coverage/default/42.lc_ctrl_sec_mubi.757015883 May 28 02:48:33 PM PDT 24 May 28 02:48:57 PM PDT 24 452678251 ps
T846 /workspace/coverage/default/33.lc_ctrl_sec_token_digest.4222668090 May 28 02:48:20 PM PDT 24 May 28 02:48:37 PM PDT 24 236609260 ps
T847 /workspace/coverage/default/11.lc_ctrl_jtag_access.2466467574 May 28 02:47:15 PM PDT 24 May 28 02:47:38 PM PDT 24 386102491 ps
T848 /workspace/coverage/default/2.lc_ctrl_jtag_priority.457945504 May 28 02:46:43 PM PDT 24 May 28 02:47:07 PM PDT 24 15525895457 ps
T849 /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.2125155455 May 28 02:48:40 PM PDT 24 May 28 03:04:49 PM PDT 24 149795337628 ps
T850 /workspace/coverage/default/24.lc_ctrl_smoke.628120556 May 28 02:48:01 PM PDT 24 May 28 02:48:10 PM PDT 24 41694810 ps
T851 /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.353558748 May 28 02:47:09 PM PDT 24 May 28 02:48:15 PM PDT 24 5020596949 ps
T852 /workspace/coverage/default/30.lc_ctrl_stress_all.1030956689 May 28 02:48:15 PM PDT 24 May 28 02:53:23 PM PDT 24 57718954113 ps
T853 /workspace/coverage/default/24.lc_ctrl_security_escalation.2893268285 May 28 02:47:57 PM PDT 24 May 28 02:48:10 PM PDT 24 417139255 ps
T854 /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3897174610 May 28 02:47:41 PM PDT 24 May 28 02:47:58 PM PDT 24 6424105787 ps
T855 /workspace/coverage/default/16.lc_ctrl_sec_token_mux.134240223 May 28 02:47:44 PM PDT 24 May 28 02:48:01 PM PDT 24 348518099 ps
T856 /workspace/coverage/default/7.lc_ctrl_jtag_access.84987684 May 28 02:47:01 PM PDT 24 May 28 02:47:15 PM PDT 24 329284322 ps
T857 /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3190475379 May 28 02:46:55 PM PDT 24 May 28 02:47:08 PM PDT 24 13216929 ps
T858 /workspace/coverage/default/13.lc_ctrl_smoke.1255981566 May 28 02:47:14 PM PDT 24 May 28 02:47:27 PM PDT 24 82425797 ps
T859 /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1649236567 May 28 02:46:49 PM PDT 24 May 28 02:47:19 PM PDT 24 670259344 ps
T860 /workspace/coverage/default/28.lc_ctrl_sec_mubi.3382244901 May 28 02:48:02 PM PDT 24 May 28 02:48:22 PM PDT 24 1621976802 ps
T861 /workspace/coverage/default/11.lc_ctrl_state_failure.3574186169 May 28 02:47:16 PM PDT 24 May 28 02:47:58 PM PDT 24 353138001 ps
T862 /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2239777642 May 28 02:46:42 PM PDT 24 May 28 02:47:30 PM PDT 24 1433296061 ps
T863 /workspace/coverage/default/49.lc_ctrl_state_post_trans.3937162743 May 28 02:48:54 PM PDT 24 May 28 02:49:09 PM PDT 24 93121487 ps
T864 /workspace/coverage/default/30.lc_ctrl_sec_mubi.2542816365 May 28 02:48:15 PM PDT 24 May 28 02:48:38 PM PDT 24 898143459 ps
T865 /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3408506138 May 28 02:46:53 PM PDT 24 May 28 02:47:12 PM PDT 24 241449636 ps
T866 /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1670121592 May 28 02:47:58 PM PDT 24 May 28 02:48:10 PM PDT 24 598741873 ps
T867 /workspace/coverage/default/42.lc_ctrl_stress_all.3262096742 May 28 02:48:35 PM PDT 24 May 28 02:51:56 PM PDT 24 3476406454 ps
T868 /workspace/coverage/default/31.lc_ctrl_security_escalation.3191239397 May 28 02:48:13 PM PDT 24 May 28 02:48:30 PM PDT 24 397559399 ps
T869 /workspace/coverage/default/25.lc_ctrl_security_escalation.3697126307 May 28 02:48:03 PM PDT 24 May 28 02:48:19 PM PDT 24 646396492 ps
T870 /workspace/coverage/default/10.lc_ctrl_jtag_errors.215224120 May 28 02:47:16 PM PDT 24 May 28 02:48:35 PM PDT 24 9743111677 ps
T871 /workspace/coverage/default/36.lc_ctrl_prog_failure.1641825807 May 28 02:48:30 PM PDT 24 May 28 02:48:35 PM PDT 24 124046075 ps
T872 /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1565004112 May 28 02:47:06 PM PDT 24 May 28 02:47:19 PM PDT 24 14218339 ps
T873 /workspace/coverage/default/49.lc_ctrl_sec_token_mux.817636054 May 28 02:48:52 PM PDT 24 May 28 02:49:06 PM PDT 24 267633963 ps
T874 /workspace/coverage/default/0.lc_ctrl_jtag_access.2053198858 May 28 02:46:30 PM PDT 24 May 28 02:46:49 PM PDT 24 264312979 ps
T875 /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3494249423 May 28 02:47:26 PM PDT 24 May 28 02:47:44 PM PDT 24 2244306118 ps
T876 /workspace/coverage/default/29.lc_ctrl_alert_test.228614190 May 28 02:48:04 PM PDT 24 May 28 02:48:11 PM PDT 24 16684981 ps
T877 /workspace/coverage/default/8.lc_ctrl_errors.689454396 May 28 02:46:57 PM PDT 24 May 28 02:47:25 PM PDT 24 607137707 ps
T103 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.675250983 May 28 01:41:14 PM PDT 24 May 28 01:41:18 PM PDT 24 45725224 ps
T116 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1661638600 May 28 01:40:35 PM PDT 24 May 28 01:40:47 PM PDT 24 4015569809 ps
T111 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2456646111 May 28 01:40:53 PM PDT 24 May 28 01:40:59 PM PDT 24 22089840 ps
T112 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1878698501 May 28 01:41:01 PM PDT 24 May 28 01:41:08 PM PDT 24 47953612 ps
T104 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2332180976 May 28 01:41:05 PM PDT 24 May 28 01:41:11 PM PDT 24 238508049 ps
T139 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1059755147 May 28 01:40:39 PM PDT 24 May 28 01:40:44 PM PDT 24 70198232 ps
T107 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3594390336 May 28 01:40:50 PM PDT 24 May 28 01:40:54 PM PDT 24 18155292 ps
T106 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.928925524 May 28 01:41:28 PM PDT 24 May 28 01:41:33 PM PDT 24 636398360 ps
T113 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1515305009 May 28 01:42:02 PM PDT 24 May 28 01:42:06 PM PDT 24 14422138 ps
T138 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2398639971 May 28 01:41:02 PM PDT 24 May 28 01:41:08 PM PDT 24 27358725 ps
T137 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1696138807 May 28 01:41:15 PM PDT 24 May 28 01:41:20 PM PDT 24 2055888135 ps
T878 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.228303320 May 28 01:41:01 PM PDT 24 May 28 01:41:07 PM PDT 24 23319119 ps
T201 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.334868009 May 28 01:40:41 PM PDT 24 May 28 01:40:45 PM PDT 24 65422708 ps
T135 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1543992005 May 28 01:41:26 PM PDT 24 May 28 01:41:28 PM PDT 24 451770360 ps
T202 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2431737810 May 28 01:40:35 PM PDT 24 May 28 01:40:37 PM PDT 24 126122245 ps
T879 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.4029093472 May 28 01:40:52 PM PDT 24 May 28 01:40:58 PM PDT 24 123342456 ps
T880 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3851600629 May 28 01:40:49 PM PDT 24 May 28 01:40:53 PM PDT 24 54828695 ps
T881 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2427216639 May 28 01:41:14 PM PDT 24 May 28 01:41:17 PM PDT 24 112628374 ps
T882 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.4034819106 May 28 01:40:37 PM PDT 24 May 28 01:40:42 PM PDT 24 94422419 ps
T115 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.4238286625 May 28 01:40:48 PM PDT 24 May 28 01:40:52 PM PDT 24 102724418 ps
T108 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1588276591 May 28 01:40:40 PM PDT 24 May 28 01:40:45 PM PDT 24 234338898 ps
T203 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2819303500 May 28 01:41:44 PM PDT 24 May 28 01:41:47 PM PDT 24 61613554 ps
T109 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2314652161 May 28 01:40:54 PM PDT 24 May 28 01:41:01 PM PDT 24 398941486 ps
T166 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.322642806 May 28 01:41:43 PM PDT 24 May 28 01:41:47 PM PDT 24 24907837 ps
T174 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2416663176 May 28 01:40:54 PM PDT 24 May 28 01:41:01 PM PDT 24 109035836 ps
T124 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1466864986 May 28 01:41:43 PM PDT 24 May 28 01:41:47 PM PDT 24 45640144 ps
T883 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.28332462 May 28 01:40:54 PM PDT 24 May 28 01:41:09 PM PDT 24 1493536371 ps
T204 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3676720931 May 28 01:41:44 PM PDT 24 May 28 01:41:47 PM PDT 24 44479362 ps
T205 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2800139865 May 28 01:41:12 PM PDT 24 May 28 01:41:15 PM PDT 24 42095891 ps
T110 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.325653194 May 28 01:41:40 PM PDT 24 May 28 01:41:43 PM PDT 24 47685056 ps
T206 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2746981919 May 28 01:41:42 PM PDT 24 May 28 01:41:46 PM PDT 24 58507369 ps
T121 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.404563816 May 28 01:41:00 PM PDT 24 May 28 01:41:08 PM PDT 24 159509731 ps
T150 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3266178184 May 28 01:41:44 PM PDT 24 May 28 01:41:49 PM PDT 24 149330245 ps
T884 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1047249715 May 28 01:41:11 PM PDT 24 May 28 01:41:14 PM PDT 24 125575614 ps
T151 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3120829311 May 28 01:40:51 PM PDT 24 May 28 01:40:57 PM PDT 24 46530645 ps
T207 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2313929908 May 28 01:41:01 PM PDT 24 May 28 01:41:07 PM PDT 24 76550949 ps
T885 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.663463241 May 28 01:41:17 PM PDT 24 May 28 01:41:19 PM PDT 24 143636099 ps
T208 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2288496245 May 28 01:41:10 PM PDT 24 May 28 01:41:13 PM PDT 24 26236447 ps
T886 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.44528826 May 28 01:41:00 PM PDT 24 May 28 01:41:07 PM PDT 24 155497099 ps
T887 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4147561871 May 28 01:40:49 PM PDT 24 May 28 01:41:10 PM PDT 24 35305137877 ps
T888 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1185493671 May 28 01:41:18 PM PDT 24 May 28 01:41:20 PM PDT 24 20172027 ps
T889 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.4152144129 May 28 01:40:53 PM PDT 24 May 28 01:40:58 PM PDT 24 33441172 ps
T890 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.238981768 May 28 01:41:12 PM PDT 24 May 28 01:41:14 PM PDT 24 19687187 ps
T891 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.913393831 May 28 01:42:04 PM PDT 24 May 28 01:42:13 PM PDT 24 36587668 ps
T152 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2348923254 May 28 01:41:43 PM PDT 24 May 28 01:41:46 PM PDT 24 56357596 ps
T209 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3521821635 May 28 01:41:44 PM PDT 24 May 28 01:41:47 PM PDT 24 190532902 ps
T136 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3363146764 May 28 01:40:35 PM PDT 24 May 28 01:40:43 PM PDT 24 185131068 ps
T892 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2832955226 May 28 01:40:57 PM PDT 24 May 28 01:41:07 PM PDT 24 501856718 ps
T153 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.159563499 May 28 01:41:00 PM PDT 24 May 28 01:41:07 PM PDT 24 188755689 ps
T188 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2531691618 May 28 01:40:51 PM PDT 24 May 28 01:40:56 PM PDT 24 68131537 ps
T123 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3278105745 May 28 01:41:57 PM PDT 24 May 28 01:42:04 PM PDT 24 488230384 ps
T893 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4175401462 May 28 01:40:51 PM PDT 24 May 28 01:40:57 PM PDT 24 153499247 ps
T132 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2789909534 May 28 01:41:14 PM PDT 24 May 28 01:41:19 PM PDT 24 615626569 ps
T196 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.328005032 May 28 01:40:54 PM PDT 24 May 28 01:40:59 PM PDT 24 197371813 ps
T130 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.4283799385 May 28 01:41:46 PM PDT 24 May 28 01:41:51 PM PDT 24 212357555 ps
T894 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.890384954 May 28 01:41:45 PM PDT 24 May 28 01:41:49 PM PDT 24 83315962 ps
T895 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.797229772 May 28 01:40:54 PM PDT 24 May 28 01:41:01 PM PDT 24 270373178 ps
T896 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1012763021 May 28 01:40:42 PM PDT 24 May 28 01:40:45 PM PDT 24 47319929 ps
T189 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.97061884 May 28 01:40:50 PM PDT 24 May 28 01:40:54 PM PDT 24 62545167 ps
T897 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2741915094 May 28 01:41:40 PM PDT 24 May 28 01:41:42 PM PDT 24 196952461 ps
T898 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3671570633 May 28 01:41:43 PM PDT 24 May 28 01:41:46 PM PDT 24 41842546 ps
T190 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2577382782 May 28 01:41:13 PM PDT 24 May 28 01:41:15 PM PDT 24 28231951 ps
T899 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1539524821 May 28 01:41:27 PM PDT 24 May 28 01:41:35 PM PDT 24 2753179932 ps
T900 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1401846747 May 28 01:41:01 PM PDT 24 May 28 01:41:07 PM PDT 24 194422644 ps
T191 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.4275263002 May 28 01:41:41 PM PDT 24 May 28 01:41:43 PM PDT 24 19937492 ps
T901 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2827432552 May 28 01:41:13 PM PDT 24 May 28 01:41:19 PM PDT 24 606763033 ps
T902 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.596264160 May 28 01:40:37 PM PDT 24 May 28 01:40:47 PM PDT 24 294724321 ps
T903 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.86546927 May 28 01:41:14 PM PDT 24 May 28 01:41:23 PM PDT 24 545696562 ps
T904 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3107455802 May 28 01:41:14 PM PDT 24 May 28 01:41:22 PM PDT 24 1945952681 ps
T905 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3233105623 May 28 01:40:52 PM PDT 24 May 28 01:40:58 PM PDT 24 404248516 ps
T119 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2729155040 May 28 01:41:41 PM PDT 24 May 28 01:41:45 PM PDT 24 281324077 ps
T131 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1813108676 May 28 01:41:01 PM PDT 24 May 28 01:41:09 PM PDT 24 339386612 ps
T906 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3918243065 May 28 01:41:00 PM PDT 24 May 28 01:41:07 PM PDT 24 305062901 ps
T127 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3537610314 May 28 01:40:48 PM PDT 24 May 28 01:40:53 PM PDT 24 48477504 ps
T117 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1552825709 May 28 01:41:01 PM PDT 24 May 28 01:41:09 PM PDT 24 123380428 ps
T134 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2539770397 May 28 01:41:42 PM PDT 24 May 28 01:41:46 PM PDT 24 264198337 ps
T907 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3706974036 May 28 01:41:20 PM PDT 24 May 28 01:41:22 PM PDT 24 20838174 ps
T908 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3685967144 May 28 01:40:54 PM PDT 24 May 28 01:41:00 PM PDT 24 16231284 ps
T909 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3667365764 May 28 01:41:40 PM PDT 24 May 28 01:41:43 PM PDT 24 49199812 ps
T910 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.311812423 May 28 01:40:40 PM PDT 24 May 28 01:40:44 PM PDT 24 47305937 ps
T911 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.336449882 May 28 01:41:41 PM PDT 24 May 28 01:41:44 PM PDT 24 52164722 ps
T912 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4049772367 May 28 01:40:57 PM PDT 24 May 28 01:41:03 PM PDT 24 87999789 ps
T913 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1319830967 May 28 01:42:01 PM PDT 24 May 28 01:42:05 PM PDT 24 87623999 ps
T118 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2021479887 May 28 01:41:17 PM PDT 24 May 28 01:41:22 PM PDT 24 107553209 ps
T914 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2310856107 May 28 01:40:49 PM PDT 24 May 28 01:40:53 PM PDT 24 44716796 ps
T915 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3304533962 May 28 01:41:42 PM PDT 24 May 28 01:41:50 PM PDT 24 159937100 ps
T916 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1003567408 May 28 01:41:02 PM PDT 24 May 28 01:41:08 PM PDT 24 119160888 ps
T917 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.595137381 May 28 01:41:00 PM PDT 24 May 28 01:41:07 PM PDT 24 25965007 ps
T133 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2165548268 May 28 01:42:01 PM PDT 24 May 28 01:42:06 PM PDT 24 144657267 ps
T918 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2958448911 May 28 01:41:19 PM PDT 24 May 28 01:41:23 PM PDT 24 333302326 ps
T919 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.137640875 May 28 01:41:46 PM PDT 24 May 28 01:41:50 PM PDT 24 74141300 ps
T920 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1899421276 May 28 01:40:53 PM PDT 24 May 28 01:41:03 PM PDT 24 265128909 ps
T192 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.9897532 May 28 01:41:00 PM PDT 24 May 28 01:41:06 PM PDT 24 22594672 ps
T193 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2447101414 May 28 01:40:40 PM PDT 24 May 28 01:40:44 PM PDT 24 16932766 ps
T921 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.110463399 May 28 01:40:57 PM PDT 24 May 28 01:41:06 PM PDT 24 657788907 ps
T922 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2635247175 May 28 01:42:02 PM PDT 24 May 28 01:42:11 PM PDT 24 370206587 ps
T923 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2325318787 May 28 01:41:57 PM PDT 24 May 28 01:42:01 PM PDT 24 1997509730 ps
T924 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3712250304 May 28 01:42:00 PM PDT 24 May 28 01:42:04 PM PDT 24 112852788 ps
T194 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1450610164 May 28 01:41:40 PM PDT 24 May 28 01:41:42 PM PDT 24 62759680 ps
T925 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3253422138 May 28 01:41:01 PM PDT 24 May 28 01:41:07 PM PDT 24 58765609 ps
T926 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3687280628 May 28 01:42:02 PM PDT 24 May 28 01:42:09 PM PDT 24 22335296 ps
T927 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1649649146 May 28 01:40:50 PM PDT 24 May 28 01:40:55 PM PDT 24 96088425 ps
T195 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3584489192 May 28 01:41:00 PM PDT 24 May 28 01:41:06 PM PDT 24 70763639 ps
T928 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1970972261 May 28 01:40:47 PM PDT 24 May 28 01:40:50 PM PDT 24 24473501 ps
T929 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3102869712 May 28 01:42:01 PM PDT 24 May 28 01:42:05 PM PDT 24 16622096 ps
T930 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3183779900 May 28 01:42:01 PM PDT 24 May 28 01:42:06 PM PDT 24 109022220 ps
T128 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.811651547 May 28 01:41:43 PM PDT 24 May 28 01:41:50 PM PDT 24 459412199 ps
T931 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2030645048 May 28 01:40:37 PM PDT 24 May 28 01:40:41 PM PDT 24 238167800 ps
T932 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2907550316 May 28 01:41:03 PM PDT 24 May 28 01:41:09 PM PDT 24 80794010 ps
T933 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1649161842 May 28 01:41:42 PM PDT 24 May 28 01:41:45 PM PDT 24 33803092 ps
T197 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.856481501 May 28 01:41:44 PM PDT 24 May 28 01:41:47 PM PDT 24 91686288 ps
T934 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1607808654 May 28 01:41:42 PM PDT 24 May 28 01:41:46 PM PDT 24 42502825 ps
T935 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2034345501 May 28 01:40:57 PM PDT 24 May 28 01:41:08 PM PDT 24 684002845 ps
T936 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2074686956 May 28 01:40:47 PM PDT 24 May 28 01:40:50 PM PDT 24 108307789 ps
T937 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3448555501 May 28 01:41:02 PM PDT 24 May 28 01:41:22 PM PDT 24 2629451005 ps
T938 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.749426522 May 28 01:40:50 PM PDT 24 May 28 01:40:55 PM PDT 24 39576679 ps
T939 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1025439216 May 28 01:40:41 PM PDT 24 May 28 01:40:45 PM PDT 24 248669866 ps
T940 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3794355169 May 28 01:40:50 PM PDT 24 May 28 01:40:55 PM PDT 24 118149757 ps
T941 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2002641797 May 28 01:41:01 PM PDT 24 May 28 01:41:09 PM PDT 24 997616298 ps
T942 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3504635044 May 28 01:41:45 PM PDT 24 May 28 01:41:47 PM PDT 24 19987509 ps
T943 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4175769262 May 28 01:40:49 PM PDT 24 May 28 01:41:20 PM PDT 24 1340088852 ps
T944 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2406322190 May 28 01:41:58 PM PDT 24 May 28 01:42:01 PM PDT 24 49495815 ps
T945 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.892277297 May 28 01:41:56 PM PDT 24 May 28 01:41:59 PM PDT 24 48911449 ps
T120 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1881497980 May 28 01:40:54 PM PDT 24 May 28 01:41:00 PM PDT 24 250300175 ps
T946 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3496094945 May 28 01:41:01 PM PDT 24 May 28 01:41:09 PM PDT 24 192792425 ps
T947 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2661767089 May 28 01:41:47 PM PDT 24 May 28 01:41:49 PM PDT 24 25973941 ps
T948 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.524798590 May 28 01:40:49 PM PDT 24 May 28 01:40:53 PM PDT 24 69475486 ps
T949 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3058991740 May 28 01:41:57 PM PDT 24 May 28 01:42:00 PM PDT 24 49095760 ps
T114 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4184595341 May 28 01:41:58 PM PDT 24 May 28 01:42:05 PM PDT 24 114995949 ps
T950 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1637973692 May 28 01:41:58 PM PDT 24 May 28 01:42:02 PM PDT 24 95611344 ps
T951 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2597638237 May 28 01:41:26 PM PDT 24 May 28 01:41:30 PM PDT 24 211381179 ps
T952 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3555976353 May 28 01:42:01 PM PDT 24 May 28 01:42:08 PM PDT 24 40464678 ps
T953 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3543529699 May 28 01:41:07 PM PDT 24 May 28 01:41:19 PM PDT 24 413090777 ps
T198 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2941797286 May 28 01:40:50 PM PDT 24 May 28 01:40:55 PM PDT 24 17326931 ps
T954 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2388471648 May 28 01:41:01 PM PDT 24 May 28 01:41:09 PM PDT 24 336067670 ps
T955 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1083964552 May 28 01:40:59 PM PDT 24 May 28 01:41:06 PM PDT 24 25495764 ps
T956 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1782643119 May 28 01:41:02 PM PDT 24 May 28 01:41:08 PM PDT 24 268414835 ps
T957 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.171379623 May 28 01:40:54 PM PDT 24 May 28 01:41:00 PM PDT 24 208737791 ps
T958 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1930734816 May 28 01:40:57 PM PDT 24 May 28 01:41:03 PM PDT 24 49259443 ps
T959 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1682301517 May 28 01:40:49 PM PDT 24 May 28 01:40:55 PM PDT 24 575198907 ps
T129 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3788136280 May 28 01:41:00 PM PDT 24 May 28 01:41:08 PM PDT 24 485109850 ps
T960 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2825354868 May 28 01:41:14 PM PDT 24 May 28 01:41:17 PM PDT 24 42561967 ps
T961 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2169027805 May 28 01:41:00 PM PDT 24 May 28 01:41:10 PM PDT 24 341751159 ps
T962 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1613946362 May 28 01:41:45 PM PDT 24 May 28 01:41:48 PM PDT 24 71650482 ps
T963 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.108536954 May 28 01:41:12 PM PDT 24 May 28 01:41:32 PM PDT 24 3296789032 ps
T964 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2546474981 May 28 01:40:48 PM PDT 24 May 28 01:40:56 PM PDT 24 204209184 ps
T965 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1275740164 May 28 01:40:55 PM PDT 24 May 28 01:41:05 PM PDT 24 1217192670 ps
T125 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3830616198 May 28 01:41:14 PM PDT 24 May 28 01:41:19 PM PDT 24 577451005 ps
T966 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2999362415 May 28 01:40:55 PM PDT 24 May 28 01:41:10 PM PDT 24 885018875 ps
T199 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2316224990 May 28 01:40:51 PM PDT 24 May 28 01:40:56 PM PDT 24 158416946 ps
T967 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3230930258 May 28 01:40:56 PM PDT 24 May 28 01:41:02 PM PDT 24 80096445 ps
T968 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1491706913 May 28 01:40:57 PM PDT 24 May 28 01:41:02 PM PDT 24 65867582 ps
T969 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2494887932 May 28 01:41:14 PM PDT 24 May 28 01:41:18 PM PDT 24 80481344 ps
T970 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2344285600 May 28 01:41:00 PM PDT 24 May 28 01:41:07 PM PDT 24 66977846 ps
T971 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2998948292 May 28 01:40:52 PM PDT 24 May 28 01:40:57 PM PDT 24 107814095 ps
T972 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4052051744 May 28 01:40:55 PM PDT 24 May 28 01:41:01 PM PDT 24 131427972 ps
T200 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2361416375 May 28 01:40:39 PM PDT 24 May 28 01:40:43 PM PDT 24 21347182 ps
T973 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2222521663 May 28 01:40:49 PM PDT 24 May 28 01:40:53 PM PDT 24 55623766 ps
T974 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1738273161 May 28 01:41:11 PM PDT 24 May 28 01:41:16 PM PDT 24 150851013 ps
T975 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3708939696 May 28 01:41:01 PM PDT 24 May 28 01:41:07 PM PDT 24 110564865 ps
T976 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2297418778 May 28 01:41:41 PM PDT 24 May 28 01:41:45 PM PDT 24 294591977 ps
T977 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.519813988 May 28 01:41:44 PM PDT 24 May 28 01:41:49 PM PDT 24 550230293 ps
T978 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1605870862 May 28 01:40:52 PM PDT 24 May 28 01:40:57 PM PDT 24 672766229 ps
T126 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1130749082 May 28 01:41:47 PM PDT 24 May 28 01:41:50 PM PDT 24 44977113 ps
T979 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3617730121 May 28 01:40:54 PM PDT 24 May 28 01:41:00 PM PDT 24 41585414 ps
T980 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1158284429 May 28 01:42:01 PM PDT 24 May 28 01:42:05 PM PDT 24 21336755 ps
T981 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2193053897 May 28 01:41:02 PM PDT 24 May 28 01:41:08 PM PDT 24 130202882 ps
T982 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.227369672 May 28 01:41:28 PM PDT 24 May 28 01:41:30 PM PDT 24 73233454 ps
T983 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2431766475 May 28 01:40:53 PM PDT 24 May 28 01:40:58 PM PDT 24 27042532 ps
T984 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.290093800 May 28 01:41:01 PM PDT 24 May 28 01:41:07 PM PDT 24 108768898 ps
T985 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3342427737 May 28 01:40:54 PM PDT 24 May 28 01:41:12 PM PDT 24 1208952129 ps
T986 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.242740850 May 28 01:40:53 PM PDT 24 May 28 01:40:59 PM PDT 24 31047011 ps
T987 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2007004112 May 28 01:40:47 PM PDT 24 May 28 01:40:50 PM PDT 24 51431587 ps
T988 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.172044267 May 28 01:40:40 PM PDT 24 May 28 01:40:45 PM PDT 24 25814237 ps
T989 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3082415737 May 28 01:41:01 PM PDT 24 May 28 01:41:07 PM PDT 24 247215426 ps
T990 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2349079005 May 28 01:41:02 PM PDT 24 May 28 01:41:25 PM PDT 24 3004751519 ps
T991 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.801420531 May 28 01:41:21 PM PDT 24 May 28 01:41:25 PM PDT 24 101340248 ps
T992 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.669679137 May 28 01:41:42 PM PDT 24 May 28 01:41:46 PM PDT 24 87753732 ps
T122 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1032736949 May 28 01:41:43 PM PDT 24 May 28 01:41:48 PM PDT 24 120184532 ps
T993 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2019375827 May 28 01:40:54 PM PDT 24 May 28 01:41:00 PM PDT 24 98563214 ps
T994 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3989565528 May 28 01:40:40 PM PDT 24 May 28 01:40:43 PM PDT 24 17960851 ps
T995 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2113450813 May 28 01:41:02 PM PDT 24 May 28 01:41:12 PM PDT 24 431331989 ps
T996 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.319222362 May 28 01:40:50 PM PDT 24 May 28 01:40:54 PM PDT 24 67381616 ps
T997 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.648233667 May 28 01:41:42 PM PDT 24 May 28 01:41:46 PM PDT 24 45794639 ps
T998 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2925742935 May 28 01:41:12 PM PDT 24 May 28 01:41:15 PM PDT 24 55878107 ps

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2479173300
Short name T2
Test name
Test status
Simulation time 10684970172 ps
CPU time 157.6 seconds
Started May 28 02:47:41 PM PDT 24
Finished May 28 02:50:22 PM PDT 24
Peak memory 250948 kb
Host smart-65e35d15-28cf-43e6-864e-3a9ad98723c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479173300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2479173300
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.907214389
Short name T50
Test name
Test status
Simulation time 290334893 ps
CPU time 9.09 seconds
Started May 28 02:48:14 PM PDT 24
Finished May 28 02:48:28 PM PDT 24
Peak memory 217976 kb
Host smart-ccf45e95-0cd1-43b7-873b-4657e1128811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907214389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.907214389
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2517851697
Short name T3
Test name
Test status
Simulation time 6372372982 ps
CPU time 21.69 seconds
Started May 28 02:46:57 PM PDT 24
Finished May 28 02:47:32 PM PDT 24
Peak memory 218968 kb
Host smart-ccd214b4-4b9b-4c00-9c5b-4fb8a0786763
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517851697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2517851697
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.46579343
Short name T42
Test name
Test status
Simulation time 121488071353 ps
CPU time 1056.01 seconds
Started May 28 02:48:12 PM PDT 24
Finished May 28 03:05:54 PM PDT 24
Peak memory 479388 kb
Host smart-8b85583c-3e53-434a-a7a7-369e59424582
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=46579343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.46579343
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.875000177
Short name T23
Test name
Test status
Simulation time 1275067731 ps
CPU time 21.85 seconds
Started May 28 02:46:44 PM PDT 24
Finished May 28 02:47:22 PM PDT 24
Peak memory 217876 kb
Host smart-f2d6cee1-f6f2-40fc-abe5-435efd3b8f5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875000177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.875000177
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2332180976
Short name T104
Test name
Test status
Simulation time 238508049 ps
CPU time 2.71 seconds
Started May 28 01:41:05 PM PDT 24
Finished May 28 01:41:11 PM PDT 24
Peak memory 217772 kb
Host smart-0f79f167-447c-4214-8cac-e97be0f42c3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332180976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.2332180976
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.3783044847
Short name T161
Test name
Test status
Simulation time 7035219370 ps
CPU time 10.14 seconds
Started May 28 02:47:12 PM PDT 24
Finished May 28 02:47:34 PM PDT 24
Peak memory 218044 kb
Host smart-1b51a4f5-982e-4add-97fc-413ac071bdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783044847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.3783044847
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.903181210
Short name T54
Test name
Test status
Simulation time 237659547 ps
CPU time 37.59 seconds
Started May 28 02:46:41 PM PDT 24
Finished May 28 02:47:34 PM PDT 24
Peak memory 284508 kb
Host smart-e584fc4f-da97-47fb-a1e4-08f697829fab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903181210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.903181210
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.2576506562
Short name T19
Test name
Test status
Simulation time 19785347881 ps
CPU time 323.37 seconds
Started May 28 02:48:26 PM PDT 24
Finished May 28 02:53:53 PM PDT 24
Peak memory 267324 kb
Host smart-59b5a424-5dfa-4a1f-904d-5d58e1e1de94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576506562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.2576506562
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1588276591
Short name T108
Test name
Test status
Simulation time 234338898 ps
CPU time 1.98 seconds
Started May 28 01:40:40 PM PDT 24
Finished May 28 01:40:45 PM PDT 24
Peak memory 217628 kb
Host smart-8653d7b6-13c8-4a94-b849-2881789c7056
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588276591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1588276591
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1578690601
Short name T10
Test name
Test status
Simulation time 124092220 ps
CPU time 1.08 seconds
Started May 28 02:48:11 PM PDT 24
Finished May 28 02:48:17 PM PDT 24
Peak memory 209416 kb
Host smart-8e04995b-cb82-40d9-b3d8-a7d75fcce6b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578690601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1578690601
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.4110035968
Short name T6
Test name
Test status
Simulation time 902292786 ps
CPU time 9.8 seconds
Started May 28 02:48:27 PM PDT 24
Finished May 28 02:48:41 PM PDT 24
Peak memory 217024 kb
Host smart-db367685-0d37-4beb-a115-5bf1cc7233cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110035968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.4110035968
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1878698501
Short name T112
Test name
Test status
Simulation time 47953612 ps
CPU time 1.22 seconds
Started May 28 01:41:01 PM PDT 24
Finished May 28 01:41:08 PM PDT 24
Peak memory 210732 kb
Host smart-889c7485-2c9b-4c60-a172-c6257a0ab075
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878698501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1878698501
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2447101414
Short name T193
Test name
Test status
Simulation time 16932766 ps
CPU time 1.41 seconds
Started May 28 01:40:40 PM PDT 24
Finished May 28 01:40:44 PM PDT 24
Peak memory 209420 kb
Host smart-22e2a3be-1d30-4eb5-b504-0f1612ed573b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447101414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2447101414
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.4184595341
Short name T114
Test name
Test status
Simulation time 114995949 ps
CPU time 4.35 seconds
Started May 28 01:41:58 PM PDT 24
Finished May 28 01:42:05 PM PDT 24
Peak memory 217636 kb
Host smart-78b96e05-ec5e-4199-a0e0-d1785939f2f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184595341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.4184595341
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.1895181544
Short name T44
Test name
Test status
Simulation time 35361503583 ps
CPU time 605.68 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:58:14 PM PDT 24
Peak memory 267472 kb
Host smart-b5d69148-7d33-4d68-baa4-ab8c5a2e8287
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1895181544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.1895181544
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.811651547
Short name T128
Test name
Test status
Simulation time 459412199 ps
CPU time 4.22 seconds
Started May 28 01:41:43 PM PDT 24
Finished May 28 01:41:50 PM PDT 24
Peak memory 217668 kb
Host smart-c25dad43-3f13-43ac-9fd0-51f2c08e9453
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811651547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.811651547
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1370210945
Short name T22
Test name
Test status
Simulation time 615132405 ps
CPU time 13.76 seconds
Started May 28 02:48:43 PM PDT 24
Finished May 28 02:49:03 PM PDT 24
Peak memory 217920 kb
Host smart-7c458853-9754-4bb3-8c02-cd129c11f47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370210945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1370210945
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2021479887
Short name T118
Test name
Test status
Simulation time 107553209 ps
CPU time 4.22 seconds
Started May 28 01:41:17 PM PDT 24
Finished May 28 01:41:22 PM PDT 24
Peak memory 217492 kb
Host smart-28a29e02-98af-40fe-9abf-01b6e9524dac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021479887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.2021479887
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.334868009
Short name T201
Test name
Test status
Simulation time 65422708 ps
CPU time 1.3 seconds
Started May 28 01:40:41 PM PDT 24
Finished May 28 01:40:45 PM PDT 24
Peak memory 209464 kb
Host smart-efe53f5e-59c2-487b-b3d4-8ad196d865f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334868009 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.334868009
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3070771059
Short name T36
Test name
Test status
Simulation time 19205098 ps
CPU time 0.84 seconds
Started May 28 02:46:53 PM PDT 24
Finished May 28 02:47:06 PM PDT 24
Peak memory 209348 kb
Host smart-87aaa587-daa4-4b49-8582-bdeae93f02ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070771059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3070771059
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.2729155040
Short name T119
Test name
Test status
Simulation time 281324077 ps
CPU time 2.6 seconds
Started May 28 01:41:41 PM PDT 24
Finished May 28 01:41:45 PM PDT 24
Peak memory 222152 kb
Host smart-38b0e1df-6705-4d62-aaab-1058a6b29b96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729155040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.2729155040
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1032736949
Short name T122
Test name
Test status
Simulation time 120184532 ps
CPU time 2.77 seconds
Started May 28 01:41:43 PM PDT 24
Finished May 28 01:41:48 PM PDT 24
Peak memory 217704 kb
Host smart-180e9321-0c29-4969-aacd-8306fc977734
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032736949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1032736949
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.4283799385
Short name T130
Test name
Test status
Simulation time 212357555 ps
CPU time 3.04 seconds
Started May 28 01:41:46 PM PDT 24
Finished May 28 01:41:51 PM PDT 24
Peak memory 217484 kb
Host smart-681221e3-6414-46b0-b6d9-27fd95e7c630
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283799385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.4283799385
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3278105745
Short name T123
Test name
Test status
Simulation time 488230384 ps
CPU time 4.89 seconds
Started May 28 01:41:57 PM PDT 24
Finished May 28 01:42:04 PM PDT 24
Peak memory 217656 kb
Host smart-f5e67eda-c690-47ef-a974-a785b447d2a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278105745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3278105745
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.2165548268
Short name T133
Test name
Test status
Simulation time 144657267 ps
CPU time 1.72 seconds
Started May 28 01:42:01 PM PDT 24
Finished May 28 01:42:06 PM PDT 24
Peak memory 221732 kb
Host smart-266e2843-6bd2-473c-b0b1-9bbb86d886c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165548268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.2165548268
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.3048785383
Short name T246
Test name
Test status
Simulation time 13886916 ps
CPU time 0.88 seconds
Started May 28 02:46:30 PM PDT 24
Finished May 28 02:46:49 PM PDT 24
Peak memory 211396 kb
Host smart-557f05eb-2ed9-4463-be61-1b2fed8d44e6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048785383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.3048785383
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.438428522
Short name T214
Test name
Test status
Simulation time 36245643 ps
CPU time 0.78 seconds
Started May 28 02:46:43 PM PDT 24
Finished May 28 02:46:59 PM PDT 24
Peak memory 209368 kb
Host smart-b26b60dd-322f-46e6-b695-2b9ce6565aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438428522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.438428522
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.2893268285
Short name T853
Test name
Test status
Simulation time 417139255 ps
CPU time 8.78 seconds
Started May 28 02:47:57 PM PDT 24
Finished May 28 02:48:10 PM PDT 24
Peak memory 217904 kb
Host smart-75f95f1e-43c6-4ac8-826a-f5f0f8d29c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893268285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.2893268285
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3624827722
Short name T210
Test name
Test status
Simulation time 10403398 ps
CPU time 1.01 seconds
Started May 28 02:47:02 PM PDT 24
Finished May 28 02:47:14 PM PDT 24
Peak memory 209200 kb
Host smart-71b0180b-e819-4306-a547-4b4d079d5911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624827722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3624827722
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3397424878
Short name T5
Test name
Test status
Simulation time 6454771245 ps
CPU time 28.83 seconds
Started May 28 02:46:44 PM PDT 24
Finished May 28 02:47:29 PM PDT 24
Peak memory 213788 kb
Host smart-9277b9da-a27e-4f12-8889-6311b9a25ad4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397424878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3397424878
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.3537610314
Short name T127
Test name
Test status
Simulation time 48477504 ps
CPU time 2.3 seconds
Started May 28 01:40:48 PM PDT 24
Finished May 28 01:40:53 PM PDT 24
Peak memory 222132 kb
Host smart-56c4ae14-42dc-484b-8e8c-d2e6f8fa0ad3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537610314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.3537610314
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3830616198
Short name T125
Test name
Test status
Simulation time 577451005 ps
CPU time 3.1 seconds
Started May 28 01:41:14 PM PDT 24
Finished May 28 01:41:19 PM PDT 24
Peak memory 217660 kb
Host smart-d9f6ad4a-5fba-406c-a4c1-1ae4525b30a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830616198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3830616198
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.1910650768
Short name T47
Test name
Test status
Simulation time 42304718210 ps
CPU time 1049.71 seconds
Started May 28 02:47:52 PM PDT 24
Finished May 28 03:05:25 PM PDT 24
Peak memory 382880 kb
Host smart-2fd696c8-5248-4e0f-9619-50e605a1d1f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1910650768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.1910650768
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.1618809649
Short name T12
Test name
Test status
Simulation time 103377303 ps
CPU time 1.88 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:48:10 PM PDT 24
Peak memory 213748 kb
Host smart-06842c79-d05f-4d4d-8e51-8a06b126fc89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618809649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.1618809649
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2578341540
Short name T38
Test name
Test status
Simulation time 451689756 ps
CPU time 6.86 seconds
Started May 28 02:47:52 PM PDT 24
Finished May 28 02:48:02 PM PDT 24
Peak memory 217924 kb
Host smart-194aa486-56fe-4805-87a0-aa1e8b1b74a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578341540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2578341540
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.1059755147
Short name T139
Test name
Test status
Simulation time 70198232 ps
CPU time 1.32 seconds
Started May 28 01:40:39 PM PDT 24
Finished May 28 01:40:44 PM PDT 24
Peak memory 209540 kb
Host smart-68439331-4990-4112-ace1-e13c84f8adbb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059755147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.1059755147
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2361416375
Short name T200
Test name
Test status
Simulation time 21347182 ps
CPU time 1.06 seconds
Started May 28 01:40:39 PM PDT 24
Finished May 28 01:40:43 PM PDT 24
Peak memory 211764 kb
Host smart-7a98d53f-ae0e-41e3-abbd-5d7eb2c82e80
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361416375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2361416375
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.172044267
Short name T988
Test name
Test status
Simulation time 25814237 ps
CPU time 1.48 seconds
Started May 28 01:40:40 PM PDT 24
Finished May 28 01:40:45 PM PDT 24
Peak memory 217732 kb
Host smart-1e4cc305-cb08-41eb-8f5f-8c427909fed4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172044267 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.172044267
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3989565528
Short name T994
Test name
Test status
Simulation time 17960851 ps
CPU time 0.89 seconds
Started May 28 01:40:40 PM PDT 24
Finished May 28 01:40:43 PM PDT 24
Peak memory 209220 kb
Host smart-c4eb1d0e-dcfb-455c-a591-533a56492b7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989565528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.3989565528
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1012763021
Short name T896
Test name
Test status
Simulation time 47319929 ps
CPU time 1.1 seconds
Started May 28 01:40:42 PM PDT 24
Finished May 28 01:40:45 PM PDT 24
Peak memory 209164 kb
Host smart-53c66f56-915f-4fc8-a285-a5594c6664b8
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012763021 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1012763021
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.3363146764
Short name T136
Test name
Test status
Simulation time 185131068 ps
CPU time 5.45 seconds
Started May 28 01:40:35 PM PDT 24
Finished May 28 01:40:43 PM PDT 24
Peak memory 208584 kb
Host smart-23b3f48f-9da9-4de2-86e8-8cd5fb95bbbd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363146764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.3363146764
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1661638600
Short name T116
Test name
Test status
Simulation time 4015569809 ps
CPU time 9.34 seconds
Started May 28 01:40:35 PM PDT 24
Finished May 28 01:40:47 PM PDT 24
Peak memory 209388 kb
Host smart-00466a73-81a7-4002-9ba9-d1e2cd6bbf15
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661638600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1661638600
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.4034819106
Short name T882
Test name
Test status
Simulation time 94422419 ps
CPU time 1.74 seconds
Started May 28 01:40:37 PM PDT 24
Finished May 28 01:40:42 PM PDT 24
Peak memory 210788 kb
Host smart-a99f777b-bd12-4fc3-aa84-f567587340b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034819106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.4034819106
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.596264160
Short name T902
Test name
Test status
Simulation time 294724321 ps
CPU time 7.03 seconds
Started May 28 01:40:37 PM PDT 24
Finished May 28 01:40:47 PM PDT 24
Peak memory 218588 kb
Host smart-2a50e292-d817-4459-b535-586938c90746
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596264
160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.596264160
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.2030645048
Short name T931
Test name
Test status
Simulation time 238167800 ps
CPU time 1.35 seconds
Started May 28 01:40:37 PM PDT 24
Finished May 28 01:40:41 PM PDT 24
Peak memory 209388 kb
Host smart-4a088bf2-36e4-4d58-b4ae-975147ea559d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030645048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.2030645048
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2431737810
Short name T202
Test name
Test status
Simulation time 126122245 ps
CPU time 1.01 seconds
Started May 28 01:40:35 PM PDT 24
Finished May 28 01:40:37 PM PDT 24
Peak memory 209500 kb
Host smart-70ad351e-32fd-4a6b-8295-53de8bdb68f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431737810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2431737810
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1025439216
Short name T939
Test name
Test status
Simulation time 248669866 ps
CPU time 1.66 seconds
Started May 28 01:40:41 PM PDT 24
Finished May 28 01:40:45 PM PDT 24
Peak memory 217872 kb
Host smart-71adb300-3dfd-4492-bcb9-2b1b7bad60dd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025439216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1025439216
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2531691618
Short name T188
Test name
Test status
Simulation time 68131537 ps
CPU time 1.38 seconds
Started May 28 01:40:51 PM PDT 24
Finished May 28 01:40:56 PM PDT 24
Peak memory 209532 kb
Host smart-75bad4af-a4a7-427d-a5a6-79607a83e339
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531691618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.2531691618
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3617730121
Short name T979
Test name
Test status
Simulation time 41585414 ps
CPU time 1.34 seconds
Started May 28 01:40:54 PM PDT 24
Finished May 28 01:41:00 PM PDT 24
Peak memory 208588 kb
Host smart-d3fa249f-6129-4bea-8da7-59689d81fd29
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617730121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3617730121
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.9897532
Short name T192
Test name
Test status
Simulation time 22594672 ps
CPU time 1.01 seconds
Started May 28 01:41:00 PM PDT 24
Finished May 28 01:41:06 PM PDT 24
Peak memory 210636 kb
Host smart-41a44a0b-351c-4af5-b1d2-fc72c2ed63a1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9897532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset.9897532
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3594390336
Short name T107
Test name
Test status
Simulation time 18155292 ps
CPU time 1.33 seconds
Started May 28 01:40:50 PM PDT 24
Finished May 28 01:40:54 PM PDT 24
Peak memory 219388 kb
Host smart-d44da3f1-c2cc-49de-b4ee-8a6d1a96d55d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594390336 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.3594390336
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2222521663
Short name T973
Test name
Test status
Simulation time 55623766 ps
CPU time 0.92 seconds
Started May 28 01:40:49 PM PDT 24
Finished May 28 01:40:53 PM PDT 24
Peak memory 209388 kb
Host smart-8efc51dc-793d-45c8-99e6-ab2f4757d3fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222521663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2222521663
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.4029093472
Short name T879
Test name
Test status
Simulation time 123342456 ps
CPU time 2.12 seconds
Started May 28 01:40:52 PM PDT 24
Finished May 28 01:40:58 PM PDT 24
Peak memory 209344 kb
Host smart-d4663a5b-e79c-4a3e-aff2-11160bcf3bb6
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029093472 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.4029093472
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3342427737
Short name T985
Test name
Test status
Simulation time 1208952129 ps
CPU time 14.28 seconds
Started May 28 01:40:54 PM PDT 24
Finished May 28 01:41:12 PM PDT 24
Peak memory 209220 kb
Host smart-148b6d18-57ad-43e1-8a0a-8e63c4b86911
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342427737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3342427737
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.4147561871
Short name T887
Test name
Test status
Simulation time 35305137877 ps
CPU time 17.99 seconds
Started May 28 01:40:49 PM PDT 24
Finished May 28 01:41:10 PM PDT 24
Peak memory 209232 kb
Host smart-bbbf4aee-aec0-4424-bd66-1e52ec52ff78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147561871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.4147561871
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.311812423
Short name T910
Test name
Test status
Simulation time 47305937 ps
CPU time 1.26 seconds
Started May 28 01:40:40 PM PDT 24
Finished May 28 01:40:44 PM PDT 24
Peak memory 210776 kb
Host smart-7a913cd2-0b2a-4101-be48-9949e1a46712
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311812423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.311812423
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1899421276
Short name T920
Test name
Test status
Simulation time 265128909 ps
CPU time 6.41 seconds
Started May 28 01:40:53 PM PDT 24
Finished May 28 01:41:03 PM PDT 24
Peak memory 217720 kb
Host smart-fe4ac778-fc58-44c5-9a07-d8b50abcd6f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189942
1276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1899421276
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2019375827
Short name T993
Test name
Test status
Simulation time 98563214 ps
CPU time 1.19 seconds
Started May 28 01:40:54 PM PDT 24
Finished May 28 01:41:00 PM PDT 24
Peak memory 209336 kb
Host smart-efc33109-7afd-4b21-a085-ebd737c0666f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019375827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2019375827
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.524798590
Short name T948
Test name
Test status
Simulation time 69475486 ps
CPU time 1.18 seconds
Started May 28 01:40:49 PM PDT 24
Finished May 28 01:40:53 PM PDT 24
Peak memory 209488 kb
Host smart-d2e38716-54d1-4e37-a12a-ff4fbfc0bc5f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524798590 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.524798590
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1970972261
Short name T928
Test name
Test status
Simulation time 24473501 ps
CPU time 1.4 seconds
Started May 28 01:40:47 PM PDT 24
Finished May 28 01:40:50 PM PDT 24
Peak memory 209464 kb
Host smart-a148ce8c-b6fa-450f-8138-873a0037ca3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970972261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.1970972261
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1682301517
Short name T959
Test name
Test status
Simulation time 575198907 ps
CPU time 2.1 seconds
Started May 28 01:40:49 PM PDT 24
Finished May 28 01:40:55 PM PDT 24
Peak memory 217724 kb
Host smart-a292bb86-1cc3-4aef-b769-f14415c35864
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682301517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1682301517
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2348923254
Short name T152
Test name
Test status
Simulation time 56357596 ps
CPU time 1.17 seconds
Started May 28 01:41:43 PM PDT 24
Finished May 28 01:41:46 PM PDT 24
Peak memory 217896 kb
Host smart-c7ed2b3b-937e-4a57-8efe-2e3c0d97c0de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348923254 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2348923254
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1450610164
Short name T194
Test name
Test status
Simulation time 62759680 ps
CPU time 1.08 seconds
Started May 28 01:41:40 PM PDT 24
Finished May 28 01:41:42 PM PDT 24
Peak memory 209644 kb
Host smart-3ebd42e9-003a-42f8-969c-fff2a4f975ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450610164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1450610164
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2661767089
Short name T947
Test name
Test status
Simulation time 25973941 ps
CPU time 1.52 seconds
Started May 28 01:41:47 PM PDT 24
Finished May 28 01:41:49 PM PDT 24
Peak memory 209464 kb
Host smart-2442de69-a9cc-4bde-bb1f-9554a233a022
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661767089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2661767089
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2741915094
Short name T897
Test name
Test status
Simulation time 196952461 ps
CPU time 1.47 seconds
Started May 28 01:41:40 PM PDT 24
Finished May 28 01:41:42 PM PDT 24
Peak memory 218004 kb
Host smart-5f995038-3d95-45a6-a230-196fc765b888
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741915094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2741915094
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.325653194
Short name T110
Test name
Test status
Simulation time 47685056 ps
CPU time 2.37 seconds
Started May 28 01:41:40 PM PDT 24
Finished May 28 01:41:43 PM PDT 24
Peak memory 222220 kb
Host smart-c3c1d20d-26d3-4eb4-b454-2b0b22dcc2f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325653194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.325653194
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.648233667
Short name T997
Test name
Test status
Simulation time 45794639 ps
CPU time 1.25 seconds
Started May 28 01:41:42 PM PDT 24
Finished May 28 01:41:46 PM PDT 24
Peak memory 221640 kb
Host smart-c8f3764c-8481-4bb7-aa16-30c6f4ec252a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648233667 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.648233667
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3671570633
Short name T898
Test name
Test status
Simulation time 41842546 ps
CPU time 0.87 seconds
Started May 28 01:41:43 PM PDT 24
Finished May 28 01:41:46 PM PDT 24
Peak memory 209316 kb
Host smart-15dabc0c-66e7-4ddb-9cdb-0256621ce439
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671570633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3671570633
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1607808654
Short name T934
Test name
Test status
Simulation time 42502825 ps
CPU time 1.05 seconds
Started May 28 01:41:42 PM PDT 24
Finished May 28 01:41:46 PM PDT 24
Peak memory 209316 kb
Host smart-d4c89257-2512-46af-babe-4e2738524fa3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607808654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1607808654
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2297418778
Short name T976
Test name
Test status
Simulation time 294591977 ps
CPU time 2.97 seconds
Started May 28 01:41:41 PM PDT 24
Finished May 28 01:41:45 PM PDT 24
Peak memory 217700 kb
Host smart-443cd26d-2e7a-40ec-b595-e07083eb49c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297418778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2297418778
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.322642806
Short name T166
Test name
Test status
Simulation time 24907837 ps
CPU time 1.49 seconds
Started May 28 01:41:43 PM PDT 24
Finished May 28 01:41:47 PM PDT 24
Peak memory 217760 kb
Host smart-6849afcb-e97c-4c00-a223-bc0961219c82
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322642806 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.322642806
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.4275263002
Short name T191
Test name
Test status
Simulation time 19937492 ps
CPU time 0.83 seconds
Started May 28 01:41:41 PM PDT 24
Finished May 28 01:41:43 PM PDT 24
Peak memory 209316 kb
Host smart-30e72b79-8145-416b-adb5-6a2e8f88c2c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275263002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.4275263002
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2746981919
Short name T206
Test name
Test status
Simulation time 58507369 ps
CPU time 0.99 seconds
Started May 28 01:41:42 PM PDT 24
Finished May 28 01:41:46 PM PDT 24
Peak memory 209464 kb
Host smart-eab56033-b739-43e0-8c15-ff6b5291129f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746981919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.2746981919
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3266178184
Short name T150
Test name
Test status
Simulation time 149330245 ps
CPU time 2.59 seconds
Started May 28 01:41:44 PM PDT 24
Finished May 28 01:41:49 PM PDT 24
Peak memory 217696 kb
Host smart-fb815211-9fbe-4681-88d0-dd50bead3e55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266178184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.3266178184
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2539770397
Short name T134
Test name
Test status
Simulation time 264198337 ps
CPU time 2.01 seconds
Started May 28 01:41:42 PM PDT 24
Finished May 28 01:41:46 PM PDT 24
Peak memory 221976 kb
Host smart-fa033c77-a1bd-4312-aeaa-ab7476ff9b41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539770397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.2539770397
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1466864986
Short name T124
Test name
Test status
Simulation time 45640144 ps
CPU time 1.95 seconds
Started May 28 01:41:43 PM PDT 24
Finished May 28 01:41:47 PM PDT 24
Peak memory 219892 kb
Host smart-23271476-95a4-4e37-bdfa-a73050f4ce5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466864986 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1466864986
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.856481501
Short name T197
Test name
Test status
Simulation time 91686288 ps
CPU time 0.83 seconds
Started May 28 01:41:44 PM PDT 24
Finished May 28 01:41:47 PM PDT 24
Peak memory 209216 kb
Host smart-8e31b0fa-7dc1-488b-bd2c-a4f4a6b9ead7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856481501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.856481501
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3676720931
Short name T204
Test name
Test status
Simulation time 44479362 ps
CPU time 1.04 seconds
Started May 28 01:41:44 PM PDT 24
Finished May 28 01:41:47 PM PDT 24
Peak memory 209444 kb
Host smart-58696efa-3ade-4c08-b92c-247361583ef0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676720931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3676720931
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.890384954
Short name T894
Test name
Test status
Simulation time 83315962 ps
CPU time 2.59 seconds
Started May 28 01:41:45 PM PDT 24
Finished May 28 01:41:49 PM PDT 24
Peak memory 217704 kb
Host smart-d7ed51d5-6d0e-477d-b03c-a9f9925abf42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890384954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.890384954
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.669679137
Short name T992
Test name
Test status
Simulation time 87753732 ps
CPU time 1.73 seconds
Started May 28 01:41:42 PM PDT 24
Finished May 28 01:41:46 PM PDT 24
Peak memory 223352 kb
Host smart-b1db8a63-f147-42bd-90a0-d3f4d9a2b841
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669679137 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.669679137
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1649161842
Short name T933
Test name
Test status
Simulation time 33803092 ps
CPU time 0.88 seconds
Started May 28 01:41:42 PM PDT 24
Finished May 28 01:41:45 PM PDT 24
Peak memory 209312 kb
Host smart-710ae187-4cfe-4cba-98b0-f9cf53aafc05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649161842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1649161842
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2819303500
Short name T203
Test name
Test status
Simulation time 61613554 ps
CPU time 1.19 seconds
Started May 28 01:41:44 PM PDT 24
Finished May 28 01:41:47 PM PDT 24
Peak memory 217644 kb
Host smart-44ff10fb-98b4-4428-85df-1aa8548a2cfd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819303500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2819303500
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.137640875
Short name T919
Test name
Test status
Simulation time 74141300 ps
CPU time 2.47 seconds
Started May 28 01:41:46 PM PDT 24
Finished May 28 01:41:50 PM PDT 24
Peak memory 217728 kb
Host smart-38db5533-1c23-4cc1-a94d-89816b34340e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137640875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.137640875
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.1613946362
Short name T962
Test name
Test status
Simulation time 71650482 ps
CPU time 1.39 seconds
Started May 28 01:41:45 PM PDT 24
Finished May 28 01:41:48 PM PDT 24
Peak memory 217784 kb
Host smart-50156371-2d66-4038-81bb-894019478757
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613946362 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.1613946362
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3504635044
Short name T942
Test name
Test status
Simulation time 19987509 ps
CPU time 0.84 seconds
Started May 28 01:41:45 PM PDT 24
Finished May 28 01:41:47 PM PDT 24
Peak memory 209216 kb
Host smart-8575234e-212c-40f9-bddc-1c72c75bbece
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504635044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3504635044
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.336449882
Short name T911
Test name
Test status
Simulation time 52164722 ps
CPU time 1.04 seconds
Started May 28 01:41:41 PM PDT 24
Finished May 28 01:41:44 PM PDT 24
Peak memory 209468 kb
Host smart-4886bf3d-df49-4ae8-81bf-6bf14a137388
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336449882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.336449882
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.519813988
Short name T977
Test name
Test status
Simulation time 550230293 ps
CPU time 2.47 seconds
Started May 28 01:41:44 PM PDT 24
Finished May 28 01:41:49 PM PDT 24
Peak memory 217724 kb
Host smart-d338d4b1-c4ef-458a-8195-f8099d4ba446
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519813988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.519813988
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1130749082
Short name T126
Test name
Test status
Simulation time 44977113 ps
CPU time 2.32 seconds
Started May 28 01:41:47 PM PDT 24
Finished May 28 01:41:50 PM PDT 24
Peak memory 221984 kb
Host smart-14618c5d-abcf-4a4f-89d4-c50850df2fb6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130749082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1130749082
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.3058991740
Short name T949
Test name
Test status
Simulation time 49095760 ps
CPU time 1.23 seconds
Started May 28 01:41:57 PM PDT 24
Finished May 28 01:42:00 PM PDT 24
Peak memory 218796 kb
Host smart-adc81489-b8d8-4982-854f-4fd68523a013
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058991740 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.3058991740
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.892277297
Short name T945
Test name
Test status
Simulation time 48911449 ps
CPU time 0.86 seconds
Started May 28 01:41:56 PM PDT 24
Finished May 28 01:41:59 PM PDT 24
Peak memory 209292 kb
Host smart-f8c2309f-907d-4744-9729-e4b0dc0b8dc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892277297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.892277297
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3687280628
Short name T926
Test name
Test status
Simulation time 22335296 ps
CPU time 1.5 seconds
Started May 28 01:42:02 PM PDT 24
Finished May 28 01:42:09 PM PDT 24
Peak memory 211364 kb
Host smart-f0158727-88f2-476c-b5dc-c2fd22285039
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687280628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3687280628
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3304533962
Short name T915
Test name
Test status
Simulation time 159937100 ps
CPU time 5.63 seconds
Started May 28 01:41:42 PM PDT 24
Finished May 28 01:41:50 PM PDT 24
Peak memory 217712 kb
Host smart-097a51b0-d0cb-4fb4-8227-2ea5d001b709
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304533962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3304533962
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.913393831
Short name T891
Test name
Test status
Simulation time 36587668 ps
CPU time 1.33 seconds
Started May 28 01:42:04 PM PDT 24
Finished May 28 01:42:13 PM PDT 24
Peak memory 219484 kb
Host smart-bc7a0d72-19d7-442d-8ce8-2e4f98e5b049
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913393831 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.913393831
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2406322190
Short name T944
Test name
Test status
Simulation time 49495815 ps
CPU time 1.09 seconds
Started May 28 01:41:58 PM PDT 24
Finished May 28 01:42:01 PM PDT 24
Peak memory 209412 kb
Host smart-ed169ed5-376b-4964-a0dd-a50f46f8ce3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406322190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2406322190
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1637973692
Short name T950
Test name
Test status
Simulation time 95611344 ps
CPU time 0.97 seconds
Started May 28 01:41:58 PM PDT 24
Finished May 28 01:42:02 PM PDT 24
Peak memory 209496 kb
Host smart-0fb16c3c-c2ec-444b-a664-f30d2ad42f2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637973692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.1637973692
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2325318787
Short name T923
Test name
Test status
Simulation time 1997509730 ps
CPU time 2.81 seconds
Started May 28 01:41:57 PM PDT 24
Finished May 28 01:42:01 PM PDT 24
Peak memory 217768 kb
Host smart-f49a291c-ed5b-4c56-b374-b460364fade4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325318787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2325318787
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1319830967
Short name T913
Test name
Test status
Simulation time 87623999 ps
CPU time 1.13 seconds
Started May 28 01:42:01 PM PDT 24
Finished May 28 01:42:05 PM PDT 24
Peak memory 219188 kb
Host smart-0d5fc28a-0ffa-4e00-9408-6b98c2406542
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319830967 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1319830967
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.1515305009
Short name T113
Test name
Test status
Simulation time 14422138 ps
CPU time 1.07 seconds
Started May 28 01:42:02 PM PDT 24
Finished May 28 01:42:06 PM PDT 24
Peak memory 209436 kb
Host smart-4080b1cb-3ffe-4ded-95fd-c1530c924fe0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515305009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.1515305009
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.1158284429
Short name T980
Test name
Test status
Simulation time 21336755 ps
CPU time 1.2 seconds
Started May 28 01:42:01 PM PDT 24
Finished May 28 01:42:05 PM PDT 24
Peak memory 217628 kb
Host smart-06c5b70f-22ae-4bbf-9143-b1813190e7d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158284429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.1158284429
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2635247175
Short name T922
Test name
Test status
Simulation time 370206587 ps
CPU time 4.72 seconds
Started May 28 01:42:02 PM PDT 24
Finished May 28 01:42:11 PM PDT 24
Peak memory 217728 kb
Host smart-f675806a-5854-494f-b581-fdb1791ba224
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635247175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.2635247175
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3183779900
Short name T930
Test name
Test status
Simulation time 109022220 ps
CPU time 1.15 seconds
Started May 28 01:42:01 PM PDT 24
Finished May 28 01:42:06 PM PDT 24
Peak memory 217904 kb
Host smart-849ed242-39c6-408c-a0a3-c18c6744b500
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183779900 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3183779900
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3102869712
Short name T929
Test name
Test status
Simulation time 16622096 ps
CPU time 1.13 seconds
Started May 28 01:42:01 PM PDT 24
Finished May 28 01:42:05 PM PDT 24
Peak memory 209468 kb
Host smart-f3ccfdf2-b2c4-4b62-b23a-33b241ba0b53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102869712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3102869712
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3712250304
Short name T924
Test name
Test status
Simulation time 112852788 ps
CPU time 1.39 seconds
Started May 28 01:42:00 PM PDT 24
Finished May 28 01:42:04 PM PDT 24
Peak memory 211480 kb
Host smart-c8968991-1c10-439f-8200-fdbcbc6d3f69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712250304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3712250304
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.3555976353
Short name T952
Test name
Test status
Simulation time 40464678 ps
CPU time 2.86 seconds
Started May 28 01:42:01 PM PDT 24
Finished May 28 01:42:08 PM PDT 24
Peak memory 217704 kb
Host smart-44985783-fb7d-4048-8bc0-26e4163a5755
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555976353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.3555976353
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.2316224990
Short name T199
Test name
Test status
Simulation time 158416946 ps
CPU time 1.13 seconds
Started May 28 01:40:51 PM PDT 24
Finished May 28 01:40:56 PM PDT 24
Peak memory 209456 kb
Host smart-7e0ddb25-3bd1-4a4c-be73-583f6fb2ec84
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316224990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.2316224990
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.2007004112
Short name T987
Test name
Test status
Simulation time 51431587 ps
CPU time 2.11 seconds
Started May 28 01:40:47 PM PDT 24
Finished May 28 01:40:50 PM PDT 24
Peak memory 209444 kb
Host smart-6e978fd4-9f00-407c-b641-a851ea699304
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007004112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas
h.2007004112
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2456646111
Short name T111
Test name
Test status
Simulation time 22089840 ps
CPU time 1.32 seconds
Started May 28 01:40:53 PM PDT 24
Finished May 28 01:40:59 PM PDT 24
Peak memory 218268 kb
Host smart-9eca8366-fbea-43c1-b7dc-b58040994522
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456646111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.2456646111
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2074686956
Short name T936
Test name
Test status
Simulation time 108307789 ps
CPU time 1.23 seconds
Started May 28 01:40:47 PM PDT 24
Finished May 28 01:40:50 PM PDT 24
Peak memory 217916 kb
Host smart-4042ee90-1836-4f77-b608-68af4f0089d8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074686956 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2074686956
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.4152144129
Short name T889
Test name
Test status
Simulation time 33441172 ps
CPU time 0.8 seconds
Started May 28 01:40:53 PM PDT 24
Finished May 28 01:40:58 PM PDT 24
Peak memory 209312 kb
Host smart-42cf2da3-cee2-419e-87f4-bfa811846445
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152144129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.4152144129
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3851600629
Short name T880
Test name
Test status
Simulation time 54828695 ps
CPU time 1.02 seconds
Started May 28 01:40:49 PM PDT 24
Finished May 28 01:40:53 PM PDT 24
Peak memory 207880 kb
Host smart-dcb3398f-0072-4662-b28e-47631d801aaf
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851600629 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.3851600629
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2034345501
Short name T935
Test name
Test status
Simulation time 684002845 ps
CPU time 5.98 seconds
Started May 28 01:40:57 PM PDT 24
Finished May 28 01:41:08 PM PDT 24
Peak memory 207692 kb
Host smart-93909065-0fe6-4341-bc30-9fb23adb2fe1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034345501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2034345501
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4175769262
Short name T943
Test name
Test status
Simulation time 1340088852 ps
CPU time 28.64 seconds
Started May 28 01:40:49 PM PDT 24
Finished May 28 01:41:20 PM PDT 24
Peak memory 209188 kb
Host smart-cfb63342-aaa6-41cf-acd6-dce3f186043e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175769262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.4175769262
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3794355169
Short name T940
Test name
Test status
Simulation time 118149757 ps
CPU time 2.05 seconds
Started May 28 01:40:50 PM PDT 24
Finished May 28 01:40:55 PM PDT 24
Peak memory 210952 kb
Host smart-c9b45457-eb43-4316-9b94-ee905014e4dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794355169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3794355169
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2546474981
Short name T964
Test name
Test status
Simulation time 204209184 ps
CPU time 5.74 seconds
Started May 28 01:40:48 PM PDT 24
Finished May 28 01:40:56 PM PDT 24
Peak memory 218700 kb
Host smart-1fa1eb18-e461-4ff6-b753-9fce255166a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254647
4981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2546474981
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.171379623
Short name T957
Test name
Test status
Simulation time 208737791 ps
CPU time 1.82 seconds
Started May 28 01:40:54 PM PDT 24
Finished May 28 01:41:00 PM PDT 24
Peak memory 209332 kb
Host smart-8dfec440-b2c4-45ce-b927-3e33a6901d5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171379623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.171379623
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4052051744
Short name T972
Test name
Test status
Simulation time 131427972 ps
CPU time 1.61 seconds
Started May 28 01:40:55 PM PDT 24
Finished May 28 01:41:01 PM PDT 24
Peak memory 209460 kb
Host smart-e58c28e6-7fc9-4ca2-b70a-64b674acb96a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052051744 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.4052051744
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2431766475
Short name T983
Test name
Test status
Simulation time 27042532 ps
CPU time 1.06 seconds
Started May 28 01:40:53 PM PDT 24
Finished May 28 01:40:58 PM PDT 24
Peak memory 209484 kb
Host smart-8916fe8e-e807-4046-8429-ad1491ea1e71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431766475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2431766475
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.4238286625
Short name T115
Test name
Test status
Simulation time 102724418 ps
CPU time 2.28 seconds
Started May 28 01:40:48 PM PDT 24
Finished May 28 01:40:52 PM PDT 24
Peak memory 218776 kb
Host smart-ab676b62-55e6-4093-a35e-1ad2f9a77f41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238286625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.4238286625
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2314652161
Short name T109
Test name
Test status
Simulation time 398941486 ps
CPU time 2.48 seconds
Started May 28 01:40:54 PM PDT 24
Finished May 28 01:41:01 PM PDT 24
Peak memory 217220 kb
Host smart-299d22c3-4f21-474f-a489-21cc12c784e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314652161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2314652161
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.319222362
Short name T996
Test name
Test status
Simulation time 67381616 ps
CPU time 1.12 seconds
Started May 28 01:40:50 PM PDT 24
Finished May 28 01:40:54 PM PDT 24
Peak memory 209524 kb
Host smart-f2fc2f69-fbf7-4a7f-89e2-63f1a5b43ca3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319222362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasing
.319222362
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.328005032
Short name T196
Test name
Test status
Simulation time 197371813 ps
CPU time 1.27 seconds
Started May 28 01:40:54 PM PDT 24
Finished May 28 01:40:59 PM PDT 24
Peak memory 209400 kb
Host smart-62e211ed-fd3c-4f0c-8195-efdc6bb9baf5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328005032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.328005032
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3685967144
Short name T908
Test name
Test status
Simulation time 16231284 ps
CPU time 1.08 seconds
Started May 28 01:40:54 PM PDT 24
Finished May 28 01:41:00 PM PDT 24
Peak memory 209440 kb
Host smart-c4632315-a6a7-4ed2-aee1-7bcc7b6f7392
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685967144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3685967144
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2416663176
Short name T174
Test name
Test status
Simulation time 109035836 ps
CPU time 2.3 seconds
Started May 28 01:40:54 PM PDT 24
Finished May 28 01:41:01 PM PDT 24
Peak memory 219784 kb
Host smart-108a9ddd-de4d-4993-9f52-30c4caaa387a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416663176 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2416663176
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1930734816
Short name T958
Test name
Test status
Simulation time 49259443 ps
CPU time 0.88 seconds
Started May 28 01:40:57 PM PDT 24
Finished May 28 01:41:03 PM PDT 24
Peak memory 209440 kb
Host smart-78e53189-c515-452c-841a-10d58e37be9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930734816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1930734816
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2310856107
Short name T914
Test name
Test status
Simulation time 44716796 ps
CPU time 0.96 seconds
Started May 28 01:40:49 PM PDT 24
Finished May 28 01:40:53 PM PDT 24
Peak memory 209288 kb
Host smart-7724534b-a394-4fed-a0aa-a19af1e0a358
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310856107 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2310856107
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1275740164
Short name T965
Test name
Test status
Simulation time 1217192670 ps
CPU time 5.15 seconds
Started May 28 01:40:55 PM PDT 24
Finished May 28 01:41:05 PM PDT 24
Peak memory 208568 kb
Host smart-21777cab-5f1e-4e34-8682-89cfa6c60b14
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275740164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1275740164
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.28332462
Short name T883
Test name
Test status
Simulation time 1493536371 ps
CPU time 9.45 seconds
Started May 28 01:40:54 PM PDT 24
Finished May 28 01:41:09 PM PDT 24
Peak memory 209196 kb
Host smart-d02a68bd-9cc8-49eb-a1a9-588abc50bb7d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28332462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.28332462
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.110463399
Short name T921
Test name
Test status
Simulation time 657788907 ps
CPU time 4.13 seconds
Started May 28 01:40:57 PM PDT 24
Finished May 28 01:41:06 PM PDT 24
Peak memory 211000 kb
Host smart-e541fcf5-8650-411e-95bb-8d9a19c4eb37
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110463399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.110463399
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.44528826
Short name T886
Test name
Test status
Simulation time 155497099 ps
CPU time 2.7 seconds
Started May 28 01:41:00 PM PDT 24
Finished May 28 01:41:07 PM PDT 24
Peak memory 218388 kb
Host smart-4504e637-9682-4800-b52e-0f2142823324
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445288
26 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.44528826
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.1491706913
Short name T968
Test name
Test status
Simulation time 65867582 ps
CPU time 1.3 seconds
Started May 28 01:40:57 PM PDT 24
Finished May 28 01:41:02 PM PDT 24
Peak memory 209344 kb
Host smart-0ad8c575-91bb-476e-a0f1-030de9703d6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491706913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.1491706913
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2998948292
Short name T971
Test name
Test status
Simulation time 107814095 ps
CPU time 1.46 seconds
Started May 28 01:40:52 PM PDT 24
Finished May 28 01:40:57 PM PDT 24
Peak memory 209432 kb
Host smart-233ff7a7-1b21-46b2-8c46-61019018928d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998948292 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2998948292
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.242740850
Short name T986
Test name
Test status
Simulation time 31047011 ps
CPU time 1.47 seconds
Started May 28 01:40:53 PM PDT 24
Finished May 28 01:40:59 PM PDT 24
Peak memory 209520 kb
Host smart-01ddbae7-f9b2-4597-b20f-80f6081cedff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242740850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
same_csr_outstanding.242740850
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1649649146
Short name T927
Test name
Test status
Simulation time 96088425 ps
CPU time 1.72 seconds
Started May 28 01:40:50 PM PDT 24
Finished May 28 01:40:55 PM PDT 24
Peak memory 218748 kb
Host smart-f3755c93-aa79-4909-b1ef-8d8d38499d83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649649146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1649649146
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1881497980
Short name T120
Test name
Test status
Simulation time 250300175 ps
CPU time 1.91 seconds
Started May 28 01:40:54 PM PDT 24
Finished May 28 01:41:00 PM PDT 24
Peak memory 222004 kb
Host smart-5cf4a478-860c-493f-adad-85ef38d97f99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881497980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1881497980
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2941797286
Short name T198
Test name
Test status
Simulation time 17326931 ps
CPU time 1.19 seconds
Started May 28 01:40:50 PM PDT 24
Finished May 28 01:40:55 PM PDT 24
Peak memory 209456 kb
Host smart-d4757c4d-8903-4957-81e0-5f55dc9e1631
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941797286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2941797286
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1605870862
Short name T978
Test name
Test status
Simulation time 672766229 ps
CPU time 1.98 seconds
Started May 28 01:40:52 PM PDT 24
Finished May 28 01:40:57 PM PDT 24
Peak memory 209528 kb
Host smart-7d9f69c1-0295-471c-9c6b-ec9ddcbda822
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605870862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1605870862
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3253422138
Short name T925
Test name
Test status
Simulation time 58765609 ps
CPU time 0.99 seconds
Started May 28 01:41:01 PM PDT 24
Finished May 28 01:41:07 PM PDT 24
Peak memory 209988 kb
Host smart-bde1705d-f25f-494b-ade3-eb829020de20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253422138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3253422138
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.749426522
Short name T938
Test name
Test status
Simulation time 39576679 ps
CPU time 1.37 seconds
Started May 28 01:40:50 PM PDT 24
Finished May 28 01:40:55 PM PDT 24
Peak memory 219160 kb
Host smart-c7299da5-3eee-456d-9372-0719d09023d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749426522 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.749426522
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.97061884
Short name T189
Test name
Test status
Simulation time 62545167 ps
CPU time 0.88 seconds
Started May 28 01:40:50 PM PDT 24
Finished May 28 01:40:54 PM PDT 24
Peak memory 209460 kb
Host smart-cb0cf705-d335-40c4-9d3f-515a9cf92a90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97061884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.97061884
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.228303320
Short name T878
Test name
Test status
Simulation time 23319119 ps
CPU time 0.96 seconds
Started May 28 01:41:01 PM PDT 24
Finished May 28 01:41:07 PM PDT 24
Peak memory 207948 kb
Host smart-b7c23bc8-f850-4999-8107-e554b3d93b63
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228303320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.228303320
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2832955226
Short name T892
Test name
Test status
Simulation time 501856718 ps
CPU time 5.95 seconds
Started May 28 01:40:57 PM PDT 24
Finished May 28 01:41:07 PM PDT 24
Peak memory 209148 kb
Host smart-385fe09c-4c0e-42e8-814b-cbee25c42052
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832955226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2832955226
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2999362415
Short name T966
Test name
Test status
Simulation time 885018875 ps
CPU time 10.75 seconds
Started May 28 01:40:55 PM PDT 24
Finished May 28 01:41:10 PM PDT 24
Peak memory 209168 kb
Host smart-9f0ec451-2e4e-42d5-9fff-6d7f833ed12f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999362415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2999362415
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.797229772
Short name T895
Test name
Test status
Simulation time 270373178 ps
CPU time 2.22 seconds
Started May 28 01:40:54 PM PDT 24
Finished May 28 01:41:01 PM PDT 24
Peak memory 210284 kb
Host smart-b350c101-ed38-4a1c-a8d3-d0eac55d2aca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797229772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.797229772
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4049772367
Short name T912
Test name
Test status
Simulation time 87999789 ps
CPU time 2.52 seconds
Started May 28 01:40:57 PM PDT 24
Finished May 28 01:41:03 PM PDT 24
Peak memory 218800 kb
Host smart-1724536d-f139-4c1f-8276-1723734bd13a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404977
2367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4049772367
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.3233105623
Short name T905
Test name
Test status
Simulation time 404248516 ps
CPU time 1.41 seconds
Started May 28 01:40:52 PM PDT 24
Finished May 28 01:40:58 PM PDT 24
Peak memory 209424 kb
Host smart-909957b5-fe7a-4a0d-ada8-b47cb7c1f9bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233105623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.3233105623
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.3230930258
Short name T967
Test name
Test status
Simulation time 80096445 ps
CPU time 1.06 seconds
Started May 28 01:40:56 PM PDT 24
Finished May 28 01:41:02 PM PDT 24
Peak memory 209424 kb
Host smart-f21fbb6f-32e4-4d9c-8bd5-e33d6fc78cdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230930258 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.3230930258
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3120829311
Short name T151
Test name
Test status
Simulation time 46530645 ps
CPU time 1.92 seconds
Started May 28 01:40:51 PM PDT 24
Finished May 28 01:40:57 PM PDT 24
Peak memory 209464 kb
Host smart-c3858aa2-538a-4864-9c57-6941847af06d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120829311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.3120829311
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.404563816
Short name T121
Test name
Test status
Simulation time 159509731 ps
CPU time 3.67 seconds
Started May 28 01:41:00 PM PDT 24
Finished May 28 01:41:08 PM PDT 24
Peak memory 217752 kb
Host smart-a08115cb-62d7-4563-a529-4106258623b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404563816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.404563816
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3788136280
Short name T129
Test name
Test status
Simulation time 485109850 ps
CPU time 2.79 seconds
Started May 28 01:41:00 PM PDT 24
Finished May 28 01:41:08 PM PDT 24
Peak memory 222508 kb
Host smart-df464fc9-72a9-42bc-926f-9c0e2138a278
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788136280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.3788136280
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3708939696
Short name T975
Test name
Test status
Simulation time 110564865 ps
CPU time 1.59 seconds
Started May 28 01:41:01 PM PDT 24
Finished May 28 01:41:07 PM PDT 24
Peak memory 218984 kb
Host smart-049b1754-e722-446f-aa6b-750b8021b34d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708939696 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3708939696
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2398639971
Short name T138
Test name
Test status
Simulation time 27358725 ps
CPU time 1.06 seconds
Started May 28 01:41:02 PM PDT 24
Finished May 28 01:41:08 PM PDT 24
Peak memory 209552 kb
Host smart-7aee3043-d52d-4842-9c55-09777070a6a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398639971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2398639971
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.290093800
Short name T984
Test name
Test status
Simulation time 108768898 ps
CPU time 1.79 seconds
Started May 28 01:41:01 PM PDT 24
Finished May 28 01:41:07 PM PDT 24
Peak memory 209292 kb
Host smart-b1b2c2a9-3cb1-4f6c-9e5b-3a4758ab5a6a
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290093800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.lc_ctrl_jtag_alert_test.290093800
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2349079005
Short name T990
Test name
Test status
Simulation time 3004751519 ps
CPU time 17.96 seconds
Started May 28 01:41:02 PM PDT 24
Finished May 28 01:41:25 PM PDT 24
Peak memory 208636 kb
Host smart-047e71b9-0cd1-4b08-bb12-d97e70c42603
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349079005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2349079005
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.3448555501
Short name T937
Test name
Test status
Simulation time 2629451005 ps
CPU time 15.32 seconds
Started May 28 01:41:02 PM PDT 24
Finished May 28 01:41:22 PM PDT 24
Peak memory 209452 kb
Host smart-b0560dbe-2637-4004-a89c-c79d736b6fc1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448555501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.3448555501
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.4175401462
Short name T893
Test name
Test status
Simulation time 153499247 ps
CPU time 2.5 seconds
Started May 28 01:40:51 PM PDT 24
Finished May 28 01:40:57 PM PDT 24
Peak memory 211052 kb
Host smart-3e929133-141c-4b78-b076-c257ece39848
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175401462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.4175401462
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3082415737
Short name T989
Test name
Test status
Simulation time 247215426 ps
CPU time 1.6 seconds
Started May 28 01:41:01 PM PDT 24
Finished May 28 01:41:07 PM PDT 24
Peak memory 218284 kb
Host smart-73f762f3-3562-4df5-9416-396c93969402
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308241
5737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3082415737
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1782643119
Short name T956
Test name
Test status
Simulation time 268414835 ps
CPU time 1.56 seconds
Started May 28 01:41:02 PM PDT 24
Finished May 28 01:41:08 PM PDT 24
Peak memory 209348 kb
Host smart-de6a64d3-37a3-4167-8c0b-107f16fd94c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782643119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1782643119
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.159563499
Short name T153
Test name
Test status
Simulation time 188755689 ps
CPU time 1.47 seconds
Started May 28 01:41:00 PM PDT 24
Finished May 28 01:41:07 PM PDT 24
Peak memory 211620 kb
Host smart-34f0c9b5-0c9a-4f53-8c19-a61ac4a966d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159563499 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.159563499
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1003567408
Short name T916
Test name
Test status
Simulation time 119160888 ps
CPU time 1.11 seconds
Started May 28 01:41:02 PM PDT 24
Finished May 28 01:41:08 PM PDT 24
Peak memory 209548 kb
Host smart-33678d1f-7092-4f18-9a1f-5c99a588fd5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003567408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1003567408
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.595137381
Short name T917
Test name
Test status
Simulation time 25965007 ps
CPU time 1.66 seconds
Started May 28 01:41:00 PM PDT 24
Finished May 28 01:41:07 PM PDT 24
Peak memory 218796 kb
Host smart-51693b88-4a02-4513-bfdc-ed84780f3798
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595137381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.595137381
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1552825709
Short name T117
Test name
Test status
Simulation time 123380428 ps
CPU time 3.51 seconds
Started May 28 01:41:01 PM PDT 24
Finished May 28 01:41:09 PM PDT 24
Peak memory 217644 kb
Host smart-a05be6fe-c420-4baa-aa10-dc38aa23cd23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552825709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1552825709
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1083964552
Short name T955
Test name
Test status
Simulation time 25495764 ps
CPU time 1.51 seconds
Started May 28 01:40:59 PM PDT 24
Finished May 28 01:41:06 PM PDT 24
Peak memory 217848 kb
Host smart-f93d73aa-b15d-4f8a-bd66-b0a4ed390cff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083964552 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1083964552
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3584489192
Short name T195
Test name
Test status
Simulation time 70763639 ps
CPU time 1.06 seconds
Started May 28 01:41:00 PM PDT 24
Finished May 28 01:41:06 PM PDT 24
Peak memory 209396 kb
Host smart-3a8a4562-e0c1-454a-9aa4-0ad299dd4650
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584489192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3584489192
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1401846747
Short name T900
Test name
Test status
Simulation time 194422644 ps
CPU time 1.07 seconds
Started May 28 01:41:01 PM PDT 24
Finished May 28 01:41:07 PM PDT 24
Peak memory 209232 kb
Host smart-cddd81d2-cbd8-4ee4-85c5-134479b97f7f
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401846747 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1401846747
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2113450813
Short name T995
Test name
Test status
Simulation time 431331989 ps
CPU time 5.08 seconds
Started May 28 01:41:02 PM PDT 24
Finished May 28 01:41:12 PM PDT 24
Peak memory 209172 kb
Host smart-de649088-63f1-4b2d-91a4-01ad40049647
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113450813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2113450813
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.3543529699
Short name T953
Test name
Test status
Simulation time 413090777 ps
CPU time 10.05 seconds
Started May 28 01:41:07 PM PDT 24
Finished May 28 01:41:19 PM PDT 24
Peak memory 209360 kb
Host smart-68e2c2c0-f975-494d-98bb-14e9017af90b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543529699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.3543529699
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3496094945
Short name T946
Test name
Test status
Simulation time 192792425 ps
CPU time 2.78 seconds
Started May 28 01:41:01 PM PDT 24
Finished May 28 01:41:09 PM PDT 24
Peak memory 221332 kb
Host smart-b4d1bb83-36b6-46a3-8671-927b7012762e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349609
4945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3496094945
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.2193053897
Short name T981
Test name
Test status
Simulation time 130202882 ps
CPU time 1.21 seconds
Started May 28 01:41:02 PM PDT 24
Finished May 28 01:41:08 PM PDT 24
Peak memory 209328 kb
Host smart-f3b6cd67-0616-4b98-859e-394291d982c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193053897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.2193053897
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.2907550316
Short name T932
Test name
Test status
Simulation time 80794010 ps
CPU time 1 seconds
Started May 28 01:41:03 PM PDT 24
Finished May 28 01:41:09 PM PDT 24
Peak memory 209300 kb
Host smart-f044a969-a235-4e76-b1c3-3af0d43350d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907550316 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.2907550316
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.2313929908
Short name T207
Test name
Test status
Simulation time 76550949 ps
CPU time 1.2 seconds
Started May 28 01:41:01 PM PDT 24
Finished May 28 01:41:07 PM PDT 24
Peak memory 211512 kb
Host smart-9c66d444-b4cb-457f-9fe5-fcea2e834d3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313929908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.2313929908
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.1813108676
Short name T131
Test name
Test status
Simulation time 339386612 ps
CPU time 2.51 seconds
Started May 28 01:41:01 PM PDT 24
Finished May 28 01:41:09 PM PDT 24
Peak memory 217640 kb
Host smart-86839782-80df-42e6-bb8e-976a47d0438f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813108676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.1813108676
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2925742935
Short name T998
Test name
Test status
Simulation time 55878107 ps
CPU time 1.4 seconds
Started May 28 01:41:12 PM PDT 24
Finished May 28 01:41:15 PM PDT 24
Peak memory 218792 kb
Host smart-78291ed7-0c1d-4954-a1ca-fa0399f91f7d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925742935 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2925742935
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.238981768
Short name T890
Test name
Test status
Simulation time 19687187 ps
CPU time 0.96 seconds
Started May 28 01:41:12 PM PDT 24
Finished May 28 01:41:14 PM PDT 24
Peak memory 209460 kb
Host smart-9a02ac08-d5c8-4bf2-b690-ee8892d655fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238981768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.238981768
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2494887932
Short name T969
Test name
Test status
Simulation time 80481344 ps
CPU time 2.04 seconds
Started May 28 01:41:14 PM PDT 24
Finished May 28 01:41:18 PM PDT 24
Peak memory 209324 kb
Host smart-cfccb083-a6ba-4dfc-9da7-5258d52d3973
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494887932 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.2494887932
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2002641797
Short name T941
Test name
Test status
Simulation time 997616298 ps
CPU time 3.06 seconds
Started May 28 01:41:01 PM PDT 24
Finished May 28 01:41:09 PM PDT 24
Peak memory 209220 kb
Host smart-8b88d1f5-9f3c-45ce-ae85-dab189d52c44
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002641797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2002641797
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2169027805
Short name T961
Test name
Test status
Simulation time 341751159 ps
CPU time 4.49 seconds
Started May 28 01:41:00 PM PDT 24
Finished May 28 01:41:10 PM PDT 24
Peak memory 209164 kb
Host smart-f515ec51-ca64-472c-8d3b-b9d6b869df59
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169027805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2169027805
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2344285600
Short name T970
Test name
Test status
Simulation time 66977846 ps
CPU time 1.45 seconds
Started May 28 01:41:00 PM PDT 24
Finished May 28 01:41:07 PM PDT 24
Peak memory 210772 kb
Host smart-0ee94401-7617-4af1-8bcf-90b4ba347e98
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344285600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2344285600
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.801420531
Short name T991
Test name
Test status
Simulation time 101340248 ps
CPU time 3.36 seconds
Started May 28 01:41:21 PM PDT 24
Finished May 28 01:41:25 PM PDT 24
Peak memory 219296 kb
Host smart-77ec2803-f782-4318-801b-d4cc91236b6b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801420
531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.801420531
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2388471648
Short name T954
Test name
Test status
Simulation time 336067670 ps
CPU time 2.2 seconds
Started May 28 01:41:01 PM PDT 24
Finished May 28 01:41:09 PM PDT 24
Peak memory 209376 kb
Host smart-4b945ba2-60f8-4672-b285-a4afbff2e3fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388471648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2388471648
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3918243065
Short name T906
Test name
Test status
Simulation time 305062901 ps
CPU time 1.32 seconds
Started May 28 01:41:00 PM PDT 24
Finished May 28 01:41:07 PM PDT 24
Peak memory 209376 kb
Host smart-ec9c94ea-c55a-43c3-b434-5b22c5eb66f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918243065 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.3918243065
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.2288496245
Short name T208
Test name
Test status
Simulation time 26236447 ps
CPU time 1.07 seconds
Started May 28 01:41:10 PM PDT 24
Finished May 28 01:41:13 PM PDT 24
Peak memory 209468 kb
Host smart-475dfac3-a114-4df6-baf6-528b34cb18ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288496245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.2288496245
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.928925524
Short name T106
Test name
Test status
Simulation time 636398360 ps
CPU time 3.69 seconds
Started May 28 01:41:28 PM PDT 24
Finished May 28 01:41:33 PM PDT 24
Peak memory 217676 kb
Host smart-fecb16e3-0ad0-4920-95dd-b625e0638e75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928925524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.928925524
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2789909534
Short name T132
Test name
Test status
Simulation time 615626569 ps
CPU time 4.05 seconds
Started May 28 01:41:14 PM PDT 24
Finished May 28 01:41:19 PM PDT 24
Peak memory 217664 kb
Host smart-c9a02f2d-359c-42de-aa35-fc72028e0b25
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789909534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2789909534
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.1185493671
Short name T888
Test name
Test status
Simulation time 20172027 ps
CPU time 1.34 seconds
Started May 28 01:41:18 PM PDT 24
Finished May 28 01:41:20 PM PDT 24
Peak memory 219220 kb
Host smart-2f604124-de3a-4ef8-a6b7-672a77ee750c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185493671 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.1185493671
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2577382782
Short name T190
Test name
Test status
Simulation time 28231951 ps
CPU time 0.93 seconds
Started May 28 01:41:13 PM PDT 24
Finished May 28 01:41:15 PM PDT 24
Peak memory 209460 kb
Host smart-5c9b2690-5239-43b6-90b7-15301c29db70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577382782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2577382782
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.663463241
Short name T885
Test name
Test status
Simulation time 143636099 ps
CPU time 1.08 seconds
Started May 28 01:41:17 PM PDT 24
Finished May 28 01:41:19 PM PDT 24
Peak memory 209220 kb
Host smart-ec243658-8134-4c1c-9058-b3ae983ed309
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663463241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.663463241
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3107455802
Short name T904
Test name
Test status
Simulation time 1945952681 ps
CPU time 6.51 seconds
Started May 28 01:41:14 PM PDT 24
Finished May 28 01:41:22 PM PDT 24
Peak memory 209144 kb
Host smart-e6134a4f-1d87-405c-9b19-40defb06a9d6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107455802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3107455802
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.108536954
Short name T963
Test name
Test status
Simulation time 3296789032 ps
CPU time 18.87 seconds
Started May 28 01:41:12 PM PDT 24
Finished May 28 01:41:32 PM PDT 24
Peak memory 208552 kb
Host smart-2bce3a2c-f3c7-43d5-909e-f9096763a2fc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108536954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.108536954
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1696138807
Short name T137
Test name
Test status
Simulation time 2055888135 ps
CPU time 3.76 seconds
Started May 28 01:41:15 PM PDT 24
Finished May 28 01:41:20 PM PDT 24
Peak memory 211096 kb
Host smart-ff2190b8-b86b-4b27-bf11-597e3e39f528
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696138807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1696138807
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2597638237
Short name T951
Test name
Test status
Simulation time 211381179 ps
CPU time 3.77 seconds
Started May 28 01:41:26 PM PDT 24
Finished May 28 01:41:30 PM PDT 24
Peak memory 218784 kb
Host smart-fb2b8cb3-5ee3-4d56-ad19-1d395e8a889c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259763
8237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2597638237
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.1047249715
Short name T884
Test name
Test status
Simulation time 125575614 ps
CPU time 1.42 seconds
Started May 28 01:41:11 PM PDT 24
Finished May 28 01:41:14 PM PDT 24
Peak memory 209392 kb
Host smart-bbe605d3-c03f-4363-a52e-f73f22133e78
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047249715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.1047249715
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.227369672
Short name T982
Test name
Test status
Simulation time 73233454 ps
CPU time 1.25 seconds
Started May 28 01:41:28 PM PDT 24
Finished May 28 01:41:30 PM PDT 24
Peak memory 209412 kb
Host smart-4587783c-b79b-44c3-8d22-533cfa655d31
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227369672 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.227369672
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2825354868
Short name T960
Test name
Test status
Simulation time 42561967 ps
CPU time 1.94 seconds
Started May 28 01:41:14 PM PDT 24
Finished May 28 01:41:17 PM PDT 24
Peak memory 211348 kb
Host smart-40dc4aed-f63d-4d36-bea3-86bfc0f8edd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825354868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2825354868
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.1738273161
Short name T974
Test name
Test status
Simulation time 150851013 ps
CPU time 3.11 seconds
Started May 28 01:41:11 PM PDT 24
Finished May 28 01:41:16 PM PDT 24
Peak memory 217748 kb
Host smart-cc9b22c1-032f-471c-a204-986994764ae5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738273161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.1738273161
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3667365764
Short name T909
Test name
Test status
Simulation time 49199812 ps
CPU time 0.97 seconds
Started May 28 01:41:40 PM PDT 24
Finished May 28 01:41:43 PM PDT 24
Peak memory 217692 kb
Host smart-d87e13bc-6e33-4f87-a9ee-93b64b0387a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667365764 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3667365764
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3706974036
Short name T907
Test name
Test status
Simulation time 20838174 ps
CPU time 0.94 seconds
Started May 28 01:41:20 PM PDT 24
Finished May 28 01:41:22 PM PDT 24
Peak memory 209460 kb
Host smart-50a367e7-5f5d-4b85-a38b-74355c1072e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706974036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3706974036
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2427216639
Short name T881
Test name
Test status
Simulation time 112628374 ps
CPU time 1.13 seconds
Started May 28 01:41:14 PM PDT 24
Finished May 28 01:41:17 PM PDT 24
Peak memory 208040 kb
Host smart-e784fa75-af1c-4883-8e0e-46dbe9b49981
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427216639 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2427216639
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1539524821
Short name T899
Test name
Test status
Simulation time 2753179932 ps
CPU time 7.93 seconds
Started May 28 01:41:27 PM PDT 24
Finished May 28 01:41:35 PM PDT 24
Peak memory 209424 kb
Host smart-8c45f383-5ff2-4a9b-8ffb-9916b1294bf8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539524821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1539524821
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.86546927
Short name T903
Test name
Test status
Simulation time 545696562 ps
CPU time 6.52 seconds
Started May 28 01:41:14 PM PDT 24
Finished May 28 01:41:23 PM PDT 24
Peak memory 209196 kb
Host smart-b8d9769d-091b-4fd3-9482-7147b40ab35a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86546927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.86546927
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.2958448911
Short name T918
Test name
Test status
Simulation time 333302326 ps
CPU time 2.32 seconds
Started May 28 01:41:19 PM PDT 24
Finished May 28 01:41:23 PM PDT 24
Peak memory 210984 kb
Host smart-6f8f0d87-17d5-4afe-b6ba-a42f1f6ea0d5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958448911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.2958448911
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2827432552
Short name T901
Test name
Test status
Simulation time 606763033 ps
CPU time 4.22 seconds
Started May 28 01:41:13 PM PDT 24
Finished May 28 01:41:19 PM PDT 24
Peak memory 217816 kb
Host smart-768828b1-73a9-4c3f-8fa0-198bf7500d35
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282743
2552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2827432552
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.1543992005
Short name T135
Test name
Test status
Simulation time 451770360 ps
CPU time 1.26 seconds
Started May 28 01:41:26 PM PDT 24
Finished May 28 01:41:28 PM PDT 24
Peak memory 209352 kb
Host smart-3f1d64cf-b326-422b-a5f6-a087dd2b0381
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543992005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.1543992005
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2800139865
Short name T205
Test name
Test status
Simulation time 42095891 ps
CPU time 0.95 seconds
Started May 28 01:41:12 PM PDT 24
Finished May 28 01:41:15 PM PDT 24
Peak memory 209484 kb
Host smart-ba45407a-c422-429c-b2e2-8b34828ffe75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800139865 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.2800139865
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3521821635
Short name T209
Test name
Test status
Simulation time 190532902 ps
CPU time 1.28 seconds
Started May 28 01:41:44 PM PDT 24
Finished May 28 01:41:47 PM PDT 24
Peak memory 209516 kb
Host smart-ed695ce3-39b6-4e40-9d09-40fbf8644e11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521821635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3521821635
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.675250983
Short name T103
Test name
Test status
Simulation time 45725224 ps
CPU time 2.22 seconds
Started May 28 01:41:14 PM PDT 24
Finished May 28 01:41:18 PM PDT 24
Peak memory 217724 kb
Host smart-55c96110-484a-41f5-b012-3dc74205b0ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675250983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.675250983
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3860664502
Short name T402
Test name
Test status
Simulation time 55341518 ps
CPU time 0.81 seconds
Started May 28 02:46:27 PM PDT 24
Finished May 28 02:46:44 PM PDT 24
Peak memory 209344 kb
Host smart-dd59ab96-7157-4da4-9c1f-4d5a98a02314
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860664502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3860664502
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1334959428
Short name T288
Test name
Test status
Simulation time 11631626 ps
CPU time 0.85 seconds
Started May 28 02:46:28 PM PDT 24
Finished May 28 02:46:44 PM PDT 24
Peak memory 209332 kb
Host smart-53190545-a91f-4534-8bcf-d1c22e145c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334959428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1334959428
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.809513876
Short name T762
Test name
Test status
Simulation time 500264360 ps
CPU time 15 seconds
Started May 28 02:46:34 PM PDT 24
Finished May 28 02:47:07 PM PDT 24
Peak memory 217856 kb
Host smart-dfdd4400-985d-467b-b446-a65e6fc963f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809513876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.809513876
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2053198858
Short name T874
Test name
Test status
Simulation time 264312979 ps
CPU time 3.01 seconds
Started May 28 02:46:30 PM PDT 24
Finished May 28 02:46:49 PM PDT 24
Peak memory 216740 kb
Host smart-75aba47a-579e-49df-838e-32bc55fa90d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053198858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2053198858
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3710031787
Short name T637
Test name
Test status
Simulation time 996790163 ps
CPU time 18.92 seconds
Started May 28 02:46:31 PM PDT 24
Finished May 28 02:47:07 PM PDT 24
Peak memory 217880 kb
Host smart-13c8770f-6cca-4ccc-abdf-2dc9926baf0e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710031787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3710031787
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.3480002797
Short name T501
Test name
Test status
Simulation time 2247901264 ps
CPU time 5 seconds
Started May 28 02:46:27 PM PDT 24
Finished May 28 02:46:48 PM PDT 24
Peak memory 217832 kb
Host smart-6c129361-2a0f-4aae-bd09-74d9403b197a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480002797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.3
480002797
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.13045320
Short name T28
Test name
Test status
Simulation time 523648118 ps
CPU time 8.47 seconds
Started May 28 02:46:31 PM PDT 24
Finished May 28 02:46:56 PM PDT 24
Peak memory 217748 kb
Host smart-ac66081d-6913-4cb2-b9a3-9e9be9746fe7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13045320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_p
rog_failure.13045320
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3256935870
Short name T683
Test name
Test status
Simulation time 3558818485 ps
CPU time 13.34 seconds
Started May 28 02:46:30 PM PDT 24
Finished May 28 02:47:01 PM PDT 24
Peak memory 213616 kb
Host smart-0cd1cabb-514b-4863-8c6e-860abaa8b0e4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256935870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3256935870
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1508565390
Short name T94
Test name
Test status
Simulation time 1659688704 ps
CPU time 4.37 seconds
Started May 28 02:46:30 PM PDT 24
Finished May 28 02:46:52 PM PDT 24
Peak memory 213060 kb
Host smart-35e18ef3-de28-42c4-b533-b37e6345ee89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508565390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1508565390
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1615493135
Short name T575
Test name
Test status
Simulation time 2093034473 ps
CPU time 90.09 seconds
Started May 28 02:46:30 PM PDT 24
Finished May 28 02:48:16 PM PDT 24
Peak memory 279640 kb
Host smart-4d6eea9e-122a-4570-b3d7-87127209e95f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615493135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1615493135
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.515343129
Short name T606
Test name
Test status
Simulation time 3728343790 ps
CPU time 6.85 seconds
Started May 28 02:46:29 PM PDT 24
Finished May 28 02:46:52 PM PDT 24
Peak memory 221536 kb
Host smart-f3d8c7ea-8b39-4a21-b218-554f91a8b9b3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515343129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.515343129
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.306702877
Short name T530
Test name
Test status
Simulation time 45362875 ps
CPU time 2.84 seconds
Started May 28 02:46:31 PM PDT 24
Finished May 28 02:46:50 PM PDT 24
Peak memory 217844 kb
Host smart-1c47a951-243c-41c7-bbb6-912a84de65ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306702877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.306702877
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.96112728
Short name T187
Test name
Test status
Simulation time 1319935819 ps
CPU time 7.21 seconds
Started May 28 02:46:31 PM PDT 24
Finished May 28 02:46:55 PM PDT 24
Peak memory 217820 kb
Host smart-fbce0323-c52e-4c78-8621-3ec286517081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=96112728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.96112728
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2074491852
Short name T87
Test name
Test status
Simulation time 223752752 ps
CPU time 25.61 seconds
Started May 28 02:46:31 PM PDT 24
Finished May 28 02:47:14 PM PDT 24
Peak memory 268432 kb
Host smart-b19b08b6-6a25-46fa-b703-0784fc2e5604
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074491852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2074491852
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.3365547335
Short name T623
Test name
Test status
Simulation time 1677449042 ps
CPU time 18.42 seconds
Started May 28 02:46:30 PM PDT 24
Finished May 28 02:47:05 PM PDT 24
Peak memory 225960 kb
Host smart-c56c73dd-6dda-415b-be5b-96beb9eadd83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365547335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.3365547335
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2252404081
Short name T539
Test name
Test status
Simulation time 677296832 ps
CPU time 11.67 seconds
Started May 28 02:46:32 PM PDT 24
Finished May 28 02:47:01 PM PDT 24
Peak memory 217840 kb
Host smart-9e5ce06a-12b0-4744-9b6f-92787e03b706
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252404081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2252404081
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3421943400
Short name T266
Test name
Test status
Simulation time 698730868 ps
CPU time 12.87 seconds
Started May 28 02:46:29 PM PDT 24
Finished May 28 02:46:58 PM PDT 24
Peak memory 217888 kb
Host smart-991a70e7-a0fa-4d00-b55c-cced73fe151d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421943400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
421943400
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2273886974
Short name T688
Test name
Test status
Simulation time 219399595 ps
CPU time 8.73 seconds
Started May 28 02:46:30 PM PDT 24
Finished May 28 02:46:55 PM PDT 24
Peak memory 217920 kb
Host smart-972cce32-34e2-41a0-94fd-b75a99bd3adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273886974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2273886974
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3012016104
Short name T768
Test name
Test status
Simulation time 107893624 ps
CPU time 3.02 seconds
Started May 28 02:46:31 PM PDT 24
Finished May 28 02:46:51 PM PDT 24
Peak memory 214140 kb
Host smart-28c2b5e9-c1db-4310-93f0-6852e82f33cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012016104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3012016104
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.614920688
Short name T789
Test name
Test status
Simulation time 259844516 ps
CPU time 24.5 seconds
Started May 28 02:46:29 PM PDT 24
Finished May 28 02:47:10 PM PDT 24
Peak memory 250848 kb
Host smart-053a5c2c-88fe-44df-8caa-8f8c62e63f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614920688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.614920688
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1671383929
Short name T807
Test name
Test status
Simulation time 176732366 ps
CPU time 5.22 seconds
Started May 28 02:46:29 PM PDT 24
Finished May 28 02:46:51 PM PDT 24
Peak memory 217848 kb
Host smart-145d7a6a-0469-42b7-8eab-c32c5ff2d155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671383929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1671383929
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.2945451201
Short name T793
Test name
Test status
Simulation time 26315539036 ps
CPU time 473.39 seconds
Started May 28 02:46:29 PM PDT 24
Finished May 28 02:54:39 PM PDT 24
Peak memory 267324 kb
Host smart-2ce60e58-6d15-406a-a9d5-0b7ec384b6d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945451201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.2945451201
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.423643414
Short name T738
Test name
Test status
Simulation time 36939854 ps
CPU time 0.8 seconds
Started May 28 02:46:29 PM PDT 24
Finished May 28 02:46:46 PM PDT 24
Peak memory 211468 kb
Host smart-63eee79f-85de-4067-94d7-be7a44718850
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423643414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.423643414
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.846617107
Short name T482
Test name
Test status
Simulation time 86897358 ps
CPU time 0.97 seconds
Started May 28 02:46:45 PM PDT 24
Finished May 28 02:47:02 PM PDT 24
Peak memory 209412 kb
Host smart-8a767ba4-b103-4bd3-a604-fbba26a884dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846617107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.846617107
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.599839790
Short name T444
Test name
Test status
Simulation time 27420341 ps
CPU time 0.85 seconds
Started May 28 02:46:29 PM PDT 24
Finished May 28 02:46:46 PM PDT 24
Peak memory 209324 kb
Host smart-1c021a4e-901d-407c-8998-e135d8779f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599839790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.599839790
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.2549248893
Short name T629
Test name
Test status
Simulation time 3986642764 ps
CPU time 18.75 seconds
Started May 28 02:46:34 PM PDT 24
Finished May 28 02:47:11 PM PDT 24
Peak memory 218924 kb
Host smart-d6c93b5c-6bed-4cb0-ad56-a22064983556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549248893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.2549248893
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2858370846
Short name T297
Test name
Test status
Simulation time 552916598 ps
CPU time 4.96 seconds
Started May 28 02:46:29 PM PDT 24
Finished May 28 02:46:49 PM PDT 24
Peak memory 209412 kb
Host smart-8cc23163-5205-4c72-9ef3-bdfa6b378300
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858370846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2858370846
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2765717867
Short name T548
Test name
Test status
Simulation time 4984758479 ps
CPU time 36.86 seconds
Started May 28 02:46:30 PM PDT 24
Finished May 28 02:47:23 PM PDT 24
Peak memory 217876 kb
Host smart-d376069d-c701-4d55-8d7d-3be488e74a43
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765717867 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2765717867
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3265375780
Short name T636
Test name
Test status
Simulation time 948901201 ps
CPU time 5.12 seconds
Started May 28 02:46:31 PM PDT 24
Finished May 28 02:46:53 PM PDT 24
Peak memory 217028 kb
Host smart-d98a767a-117d-4792-96f3-50c67283ed68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265375780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3
265375780
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.441950983
Short name T500
Test name
Test status
Simulation time 245839733 ps
CPU time 2.17 seconds
Started May 28 02:46:34 PM PDT 24
Finished May 28 02:46:54 PM PDT 24
Peak memory 217788 kb
Host smart-8d0654b9-ddcb-4a9b-8767-bf8a7dc8d8c4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441950983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.441950983
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.647610332
Short name T685
Test name
Test status
Simulation time 1417258747 ps
CPU time 15.58 seconds
Started May 28 02:46:31 PM PDT 24
Finished May 28 02:47:04 PM PDT 24
Peak memory 213020 kb
Host smart-c40ebbc5-2805-474c-888d-d2228772caac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647610332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_regwen_during_op.647610332
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.1369449976
Short name T504
Test name
Test status
Simulation time 7173507720 ps
CPU time 13.56 seconds
Started May 28 02:46:31 PM PDT 24
Finished May 28 02:47:01 PM PDT 24
Peak memory 214388 kb
Host smart-7ebe6748-6abd-49a5-8105-699c2c6a4fcf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369449976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
1369449976
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2167103286
Short name T148
Test name
Test status
Simulation time 2618362964 ps
CPU time 56.51 seconds
Started May 28 02:46:34 PM PDT 24
Finished May 28 02:47:48 PM PDT 24
Peak memory 275480 kb
Host smart-1e5891ee-452a-44f1-b29e-7c205730903f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167103286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2167103286
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3967138734
Short name T323
Test name
Test status
Simulation time 1027326922 ps
CPU time 8.9 seconds
Started May 28 02:46:29 PM PDT 24
Finished May 28 02:46:53 PM PDT 24
Peak memory 242572 kb
Host smart-88e3765c-e273-425b-a4d8-8aaf1c6d0488
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967138734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3967138734
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.3183945765
Short name T658
Test name
Test status
Simulation time 46481722 ps
CPU time 2.85 seconds
Started May 28 02:46:29 PM PDT 24
Finished May 28 02:46:48 PM PDT 24
Peak memory 217844 kb
Host smart-14e990e9-626d-4f78-84dd-6ad19d697e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183945765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.3183945765
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.422075882
Short name T179
Test name
Test status
Simulation time 370363006 ps
CPU time 8.25 seconds
Started May 28 02:46:30 PM PDT 24
Finished May 28 02:46:55 PM PDT 24
Peak memory 217864 kb
Host smart-2257999f-2469-44e7-a12b-ed6dba690f4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422075882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.422075882
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.889515983
Short name T89
Test name
Test status
Simulation time 819255824 ps
CPU time 23.66 seconds
Started May 28 02:46:42 PM PDT 24
Finished May 28 02:47:21 PM PDT 24
Peak memory 269444 kb
Host smart-3f8c0bad-8f03-4849-b417-86a42da92745
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889515983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.889515983
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.2749059717
Short name T396
Test name
Test status
Simulation time 771344140 ps
CPU time 13.6 seconds
Started May 28 02:46:29 PM PDT 24
Finished May 28 02:46:59 PM PDT 24
Peak memory 217988 kb
Host smart-ac0da78f-c375-4152-a50d-c72e33b99b76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749059717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.2749059717
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.4171529377
Short name T692
Test name
Test status
Simulation time 515618394 ps
CPU time 13.39 seconds
Started May 28 02:46:33 PM PDT 24
Finished May 28 02:47:04 PM PDT 24
Peak memory 225928 kb
Host smart-40e11599-1f26-4a6b-b3ae-004421ce4d26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171529377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.4171529377
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.3821485958
Short name T380
Test name
Test status
Simulation time 1148819478 ps
CPU time 6.26 seconds
Started May 28 02:46:29 PM PDT 24
Finished May 28 02:46:52 PM PDT 24
Peak memory 217896 kb
Host smart-2e8f300b-8c67-4559-9c70-1f58482478d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821485958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.3
821485958
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.2424142304
Short name T352
Test name
Test status
Simulation time 224079909 ps
CPU time 9.97 seconds
Started May 28 02:46:31 PM PDT 24
Finished May 28 02:46:58 PM PDT 24
Peak memory 218108 kb
Host smart-f0908428-4b2e-47eb-bac4-4420076b4837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424142304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.2424142304
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.3182183740
Short name T84
Test name
Test status
Simulation time 59780866 ps
CPU time 1.13 seconds
Started May 28 02:46:29 PM PDT 24
Finished May 28 02:46:47 PM PDT 24
Peak memory 213216 kb
Host smart-9f2fc427-1843-4f0d-a3e6-ee6620be75f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182183740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.3182183740
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3153685341
Short name T330
Test name
Test status
Simulation time 406158817 ps
CPU time 24.63 seconds
Started May 28 02:46:29 PM PDT 24
Finished May 28 02:47:10 PM PDT 24
Peak memory 246124 kb
Host smart-0c37d768-01fb-4e2f-be70-9fc112be7335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153685341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3153685341
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2311898104
Short name T830
Test name
Test status
Simulation time 163718185 ps
CPU time 2.59 seconds
Started May 28 02:46:29 PM PDT 24
Finished May 28 02:46:48 PM PDT 24
Peak memory 217848 kb
Host smart-cfbbd6f2-50cb-45d2-8c4a-1a8f0bce9edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311898104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2311898104
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2129349020
Short name T93
Test name
Test status
Simulation time 21434976292 ps
CPU time 97.99 seconds
Started May 28 02:46:30 PM PDT 24
Finished May 28 02:48:25 PM PDT 24
Peak memory 275540 kb
Host smart-4bcf44e9-d971-4ac4-ad4e-fdf62aaca422
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129349020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2129349020
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2604592814
Short name T140
Test name
Test status
Simulation time 35500258630 ps
CPU time 158.06 seconds
Started May 28 02:46:31 PM PDT 24
Finished May 28 02:49:26 PM PDT 24
Peak memory 405268 kb
Host smart-75479316-cef6-4523-aacd-9c4e3a1cf131
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2604592814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.2604592814
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2377843517
Short name T72
Test name
Test status
Simulation time 16409704 ps
CPU time 1.09 seconds
Started May 28 02:47:08 PM PDT 24
Finished May 28 02:47:21 PM PDT 24
Peak memory 209456 kb
Host smart-3fb37bd4-a324-44b0-8111-8267ea38b10f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377843517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2377843517
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.2885287582
Short name T641
Test name
Test status
Simulation time 727137888 ps
CPU time 16.02 seconds
Started May 28 02:47:02 PM PDT 24
Finished May 28 02:47:30 PM PDT 24
Peak memory 217788 kb
Host smart-e167f8ca-4b61-4bc0-a59d-e42a5a3ed4ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885287582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.2885287582
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3558677695
Short name T29
Test name
Test status
Simulation time 142695048 ps
CPU time 3.5 seconds
Started May 28 02:47:08 PM PDT 24
Finished May 28 02:47:23 PM PDT 24
Peak memory 216864 kb
Host smart-0dade7ae-d78b-475d-95af-bf3b451c94d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558677695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3558677695
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.215224120
Short name T870
Test name
Test status
Simulation time 9743111677 ps
CPU time 67.29 seconds
Started May 28 02:47:16 PM PDT 24
Finished May 28 02:48:35 PM PDT 24
Peak memory 218588 kb
Host smart-42022743-d653-4910-aaaa-deec49d94657
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215224120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_er
rors.215224120
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.4047701571
Short name T460
Test name
Test status
Simulation time 1897461855 ps
CPU time 12.57 seconds
Started May 28 02:47:09 PM PDT 24
Finished May 28 02:47:34 PM PDT 24
Peak memory 217788 kb
Host smart-2ac36af3-3c97-430e-a5d7-e89d4608349c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047701571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.4047701571
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.360987826
Short name T567
Test name
Test status
Simulation time 618060261 ps
CPU time 5.01 seconds
Started May 28 02:47:08 PM PDT 24
Finished May 28 02:47:25 PM PDT 24
Peak memory 213232 kb
Host smart-d3eec621-be7b-45b0-bf32-aba86488cc50
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360987826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke.
360987826
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.353558748
Short name T851
Test name
Test status
Simulation time 5020596949 ps
CPU time 54.41 seconds
Started May 28 02:47:09 PM PDT 24
Finished May 28 02:48:15 PM PDT 24
Peak memory 250932 kb
Host smart-5463253a-d69d-41fd-9172-18b64fe138bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353558748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_state_failure.353558748
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.440265599
Short name T740
Test name
Test status
Simulation time 569945535 ps
CPU time 16.33 seconds
Started May 28 02:47:12 PM PDT 24
Finished May 28 02:47:40 PM PDT 24
Peak memory 250332 kb
Host smart-42c81595-6729-447a-85cf-8ec60b2c6cd7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440265599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.440265599
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.3133030588
Short name T716
Test name
Test status
Simulation time 90311123 ps
CPU time 2.56 seconds
Started May 28 02:47:08 PM PDT 24
Finished May 28 02:47:23 PM PDT 24
Peak memory 217840 kb
Host smart-8b9795e2-4f26-417c-a436-b7da281ad966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3133030588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.3133030588
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1783956743
Short name T732
Test name
Test status
Simulation time 759407797 ps
CPU time 13.31 seconds
Started May 28 02:47:10 PM PDT 24
Finished May 28 02:47:35 PM PDT 24
Peak memory 226116 kb
Host smart-89766200-387f-46fd-be62-c962186d22c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783956743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1783956743
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1692651952
Short name T424
Test name
Test status
Simulation time 2142640650 ps
CPU time 15.85 seconds
Started May 28 02:47:16 PM PDT 24
Finished May 28 02:47:43 PM PDT 24
Peak memory 217784 kb
Host smart-de76af73-30e9-4eb9-ba31-a10b4c5db015
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692651952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1692651952
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.4041310785
Short name T680
Test name
Test status
Simulation time 1215548593 ps
CPU time 8.03 seconds
Started May 28 02:47:12 PM PDT 24
Finished May 28 02:47:32 PM PDT 24
Peak memory 217424 kb
Host smart-29ca95a8-fec1-437b-ad13-95fb1e105e9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041310785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
4041310785
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.2534686158
Short name T550
Test name
Test status
Simulation time 910931604 ps
CPU time 9.66 seconds
Started May 28 02:47:03 PM PDT 24
Finished May 28 02:47:24 PM PDT 24
Peak memory 217960 kb
Host smart-500c2dd2-7974-4b1b-87b3-f7ee1e00f8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534686158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.2534686158
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3259919960
Short name T764
Test name
Test status
Simulation time 37205634 ps
CPU time 2.39 seconds
Started May 28 02:47:03 PM PDT 24
Finished May 28 02:47:17 PM PDT 24
Peak memory 218120 kb
Host smart-ae2b23fc-546e-4876-ba91-ec766cb08a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259919960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3259919960
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.2070994717
Short name T725
Test name
Test status
Simulation time 159395514 ps
CPU time 18.1 seconds
Started May 28 02:47:07 PM PDT 24
Finished May 28 02:47:37 PM PDT 24
Peak memory 250772 kb
Host smart-693ef52f-ebaa-4889-8b5d-2c69349e4b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070994717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.2070994717
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2036651667
Short name T645
Test name
Test status
Simulation time 281880718 ps
CPU time 3.59 seconds
Started May 28 02:47:09 PM PDT 24
Finished May 28 02:47:25 PM PDT 24
Peak memory 226192 kb
Host smart-8f60631e-ae9f-44b4-9f71-fdb1c435704d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036651667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2036651667
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2194064956
Short name T163
Test name
Test status
Simulation time 33495773176 ps
CPU time 305.64 seconds
Started May 28 02:47:12 PM PDT 24
Finished May 28 02:52:29 PM PDT 24
Peak memory 283192 kb
Host smart-b8267b56-3ec4-4a87-908e-0458dff9ced8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194064956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2194064956
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3360309891
Short name T185
Test name
Test status
Simulation time 14315442 ps
CPU time 0.89 seconds
Started May 28 02:47:10 PM PDT 24
Finished May 28 02:47:23 PM PDT 24
Peak memory 211568 kb
Host smart-da5d05ec-ab02-4616-81ee-28f102e4fd6b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360309891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3360309891
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.3717315386
Short name T570
Test name
Test status
Simulation time 150101127 ps
CPU time 1.07 seconds
Started May 28 02:47:14 PM PDT 24
Finished May 28 02:47:26 PM PDT 24
Peak memory 209420 kb
Host smart-18d15da1-6d96-4959-9a75-03cdd7f822b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717315386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.3717315386
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.4173443571
Short name T461
Test name
Test status
Simulation time 1455462225 ps
CPU time 11.59 seconds
Started May 28 02:47:06 PM PDT 24
Finished May 28 02:47:29 PM PDT 24
Peak memory 217792 kb
Host smart-63b64bc2-d88d-45d0-be59-08bf72d6d16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173443571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.4173443571
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.2466467574
Short name T847
Test name
Test status
Simulation time 386102491 ps
CPU time 10.64 seconds
Started May 28 02:47:15 PM PDT 24
Finished May 28 02:47:38 PM PDT 24
Peak memory 209424 kb
Host smart-830549f4-4e69-487c-ac4b-6713adc1d753
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466467574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.2466467574
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.4123887813
Short name T615
Test name
Test status
Simulation time 2188062691 ps
CPU time 63.97 seconds
Started May 28 02:47:09 PM PDT 24
Finished May 28 02:48:25 PM PDT 24
Peak memory 217836 kb
Host smart-95fd373d-bbe0-4489-bed2-35a4b14b239c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123887813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.4123887813
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.1345346025
Short name T344
Test name
Test status
Simulation time 1921103553 ps
CPU time 5.96 seconds
Started May 28 02:47:16 PM PDT 24
Finished May 28 02:47:33 PM PDT 24
Peak memory 217840 kb
Host smart-c986abec-8086-4ac6-a728-c50a45ecdb3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345346025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.1345346025
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.4217991804
Short name T256
Test name
Test status
Simulation time 162408191 ps
CPU time 5.72 seconds
Started May 28 02:47:16 PM PDT 24
Finished May 28 02:47:33 PM PDT 24
Peak memory 213308 kb
Host smart-ab8bd5ca-f3ed-4fee-960f-b664b054843f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217991804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.4217991804
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2968813762
Short name T834
Test name
Test status
Simulation time 5911423326 ps
CPU time 44.75 seconds
Started May 28 02:47:17 PM PDT 24
Finished May 28 02:48:13 PM PDT 24
Peak memory 275460 kb
Host smart-2dd0407e-f140-4840-9da5-5bd0b3dbd71c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968813762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2968813762
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1277435136
Short name T477
Test name
Test status
Simulation time 1362466929 ps
CPU time 15.14 seconds
Started May 28 02:47:15 PM PDT 24
Finished May 28 02:47:42 PM PDT 24
Peak memory 250804 kb
Host smart-45bc413f-1b17-4cd6-ac13-7c7267526e80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277435136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1277435136
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1751743789
Short name T667
Test name
Test status
Simulation time 771178462 ps
CPU time 2.79 seconds
Started May 28 02:47:16 PM PDT 24
Finished May 28 02:47:30 PM PDT 24
Peak memory 217836 kb
Host smart-d1d93e9e-2e55-46e0-897b-97aac4395221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751743789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1751743789
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.761423738
Short name T473
Test name
Test status
Simulation time 331738417 ps
CPU time 14.51 seconds
Started May 28 02:47:08 PM PDT 24
Finished May 28 02:47:34 PM PDT 24
Peak memory 225800 kb
Host smart-efb81348-4ee4-488d-beba-6e4536cedb34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761423738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.761423738
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.4178836010
Short name T601
Test name
Test status
Simulation time 231170851 ps
CPU time 9.52 seconds
Started May 28 02:47:14 PM PDT 24
Finished May 28 02:47:35 PM PDT 24
Peak memory 217696 kb
Host smart-f479a150-2bfc-4267-a89b-2d722f41dbca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178836010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.4178836010
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.3361968593
Short name T183
Test name
Test status
Simulation time 1760311456 ps
CPU time 9.65 seconds
Started May 28 02:47:16 PM PDT 24
Finished May 28 02:47:37 PM PDT 24
Peak memory 217944 kb
Host smart-bb591551-ed91-4070-a2e8-0ff176f058f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361968593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
3361968593
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3326686657
Short name T844
Test name
Test status
Simulation time 89180737 ps
CPU time 1.87 seconds
Started May 28 02:47:10 PM PDT 24
Finished May 28 02:47:24 PM PDT 24
Peak memory 213680 kb
Host smart-e89a7309-7a56-479f-8812-af8d4d9a237c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326686657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3326686657
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3574186169
Short name T861
Test name
Test status
Simulation time 353138001 ps
CPU time 30.95 seconds
Started May 28 02:47:16 PM PDT 24
Finished May 28 02:47:58 PM PDT 24
Peak memory 250780 kb
Host smart-5ff0fd3d-e1c5-441e-8652-ca74d8813860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574186169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3574186169
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.3277443616
Short name T445
Test name
Test status
Simulation time 237258485 ps
CPU time 6.29 seconds
Started May 28 02:47:16 PM PDT 24
Finished May 28 02:47:33 PM PDT 24
Peak memory 247128 kb
Host smart-c24d5033-9167-4b85-b907-259a023953e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277443616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.3277443616
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.362484098
Short name T358
Test name
Test status
Simulation time 31284018840 ps
CPU time 90.62 seconds
Started May 28 02:47:16 PM PDT 24
Finished May 28 02:48:58 PM PDT 24
Peak memory 253564 kb
Host smart-a35e54ed-49d4-4590-b022-0685975d13eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362484098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.362484098
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3828433845
Short name T261
Test name
Test status
Simulation time 14134381 ps
CPU time 0.93 seconds
Started May 28 02:47:16 PM PDT 24
Finished May 28 02:47:28 PM PDT 24
Peak memory 207800 kb
Host smart-c3a83e3f-f67d-4f5c-bf2c-339d89472b56
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828433845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3828433845
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.4006656854
Short name T829
Test name
Test status
Simulation time 202553541 ps
CPU time 0.9 seconds
Started May 28 02:47:14 PM PDT 24
Finished May 28 02:47:26 PM PDT 24
Peak memory 209432 kb
Host smart-e3729230-992f-4bea-9ba5-51326b7296a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006656854 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.4006656854
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.1117667698
Short name T822
Test name
Test status
Simulation time 303130696 ps
CPU time 10.61 seconds
Started May 28 02:47:15 PM PDT 24
Finished May 28 02:47:37 PM PDT 24
Peak memory 217852 kb
Host smart-ca7c0a37-a37c-4ea0-86b4-4672fb39e497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117667698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.1117667698
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2566752929
Short name T556
Test name
Test status
Simulation time 1541679845 ps
CPU time 5.84 seconds
Started May 28 02:47:17 PM PDT 24
Finished May 28 02:47:34 PM PDT 24
Peak memory 216876 kb
Host smart-9621e96c-15ae-4596-8341-13a5de9b2981
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566752929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2566752929
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.2820486675
Short name T245
Test name
Test status
Simulation time 2308544617 ps
CPU time 34.12 seconds
Started May 28 02:47:14 PM PDT 24
Finished May 28 02:48:00 PM PDT 24
Peak memory 217872 kb
Host smart-4999c1cf-cba5-47e1-a819-5eab057f1114
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820486675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.2820486675
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.2101710500
Short name T447
Test name
Test status
Simulation time 810009061 ps
CPU time 20.43 seconds
Started May 28 02:47:21 PM PDT 24
Finished May 28 02:47:51 PM PDT 24
Peak memory 217792 kb
Host smart-da57cbc3-e734-427c-b458-39ddcce80eba
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101710500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.2101710500
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.1980222939
Short name T85
Test name
Test status
Simulation time 672157603 ps
CPU time 8.36 seconds
Started May 28 02:47:14 PM PDT 24
Finished May 28 02:47:34 PM PDT 24
Peak memory 213508 kb
Host smart-a1e25076-18d6-409c-bcfc-26f34844f4c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980222939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.1980222939
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2222662169
Short name T432
Test name
Test status
Simulation time 1338887363 ps
CPU time 53.7 seconds
Started May 28 02:47:17 PM PDT 24
Finished May 28 02:48:22 PM PDT 24
Peak memory 250772 kb
Host smart-7b5c1223-6d97-492f-b876-9ae8b07ae194
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222662169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2222662169
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.2495861790
Short name T399
Test name
Test status
Simulation time 1531075023 ps
CPU time 11.39 seconds
Started May 28 02:47:15 PM PDT 24
Finished May 28 02:47:38 PM PDT 24
Peak memory 250748 kb
Host smart-8fce8b62-a1ec-470f-ab4b-d9a7f1660ee8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495861790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.2495861790
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3734400866
Short name T843
Test name
Test status
Simulation time 54618878 ps
CPU time 2.21 seconds
Started May 28 02:47:14 PM PDT 24
Finished May 28 02:47:28 PM PDT 24
Peak memory 217828 kb
Host smart-53ce6107-6c7e-4401-9102-6654e6a1cbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734400866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3734400866
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2327203094
Short name T608
Test name
Test status
Simulation time 1036644899 ps
CPU time 8.89 seconds
Started May 28 02:47:14 PM PDT 24
Finished May 28 02:47:35 PM PDT 24
Peak memory 217812 kb
Host smart-e1215bb6-f15a-4493-97cd-889f789bf862
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327203094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2327203094
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1078555940
Short name T419
Test name
Test status
Simulation time 10408629507 ps
CPU time 26.63 seconds
Started May 28 02:47:13 PM PDT 24
Finished May 28 02:47:51 PM PDT 24
Peak memory 218052 kb
Host smart-78a94565-c144-4e6c-b99d-1b8a319b8cb7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078555940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1078555940
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2172057346
Short name T388
Test name
Test status
Simulation time 960217438 ps
CPU time 8.37 seconds
Started May 28 02:47:14 PM PDT 24
Finished May 28 02:47:34 PM PDT 24
Peak memory 217872 kb
Host smart-df6844ad-5b0f-4bb3-a0c2-67a920688e4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172057346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2172057346
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2556438489
Short name T557
Test name
Test status
Simulation time 285836374 ps
CPU time 9.63 seconds
Started May 28 02:47:21 PM PDT 24
Finished May 28 02:47:40 PM PDT 24
Peak memory 217920 kb
Host smart-0114cc54-405e-4e63-b6d0-839fbf7a2d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556438489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2556438489
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1319579780
Short name T412
Test name
Test status
Simulation time 123894666 ps
CPU time 2.77 seconds
Started May 28 02:47:15 PM PDT 24
Finished May 28 02:47:29 PM PDT 24
Peak memory 213884 kb
Host smart-49d865cf-ff03-4a74-9af0-b81297252052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319579780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1319579780
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.4288660530
Short name T803
Test name
Test status
Simulation time 1009967031 ps
CPU time 30.26 seconds
Started May 28 02:47:15 PM PDT 24
Finished May 28 02:47:57 PM PDT 24
Peak memory 250844 kb
Host smart-f0a77417-332a-451e-8fc6-64b5d68b9b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288660530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.4288660530
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2336652052
Short name T244
Test name
Test status
Simulation time 61729875 ps
CPU time 8.24 seconds
Started May 28 02:47:18 PM PDT 24
Finished May 28 02:47:37 PM PDT 24
Peak memory 250596 kb
Host smart-3169c726-c33a-4a90-a0af-ce45d1182f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336652052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2336652052
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1995270556
Short name T394
Test name
Test status
Simulation time 5710107105 ps
CPU time 142.54 seconds
Started May 28 02:47:18 PM PDT 24
Finished May 28 02:49:51 PM PDT 24
Peak memory 250924 kb
Host smart-4260c087-33ce-4d29-84a2-d50acdc1c389
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995270556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1995270556
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.3616643477
Short name T413
Test name
Test status
Simulation time 18409333 ps
CPU time 0.96 seconds
Started May 28 02:47:13 PM PDT 24
Finished May 28 02:47:26 PM PDT 24
Peak memory 211440 kb
Host smart-da4811fb-0073-4878-85bd-399b791ed74b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616643477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.3616643477
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.110183631
Short name T181
Test name
Test status
Simulation time 14057737 ps
CPU time 0.9 seconds
Started May 28 02:47:17 PM PDT 24
Finished May 28 02:47:29 PM PDT 24
Peak memory 209344 kb
Host smart-34b355e4-82f9-4eb6-b643-f77d99ff6c6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110183631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.110183631
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3201143114
Short name T691
Test name
Test status
Simulation time 1004077051 ps
CPU time 12.95 seconds
Started May 28 02:47:17 PM PDT 24
Finished May 28 02:47:41 PM PDT 24
Peak memory 217800 kb
Host smart-47c4402e-ee12-47b3-839f-acd36b8e4435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201143114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3201143114
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2823227556
Short name T49
Test name
Test status
Simulation time 57364903 ps
CPU time 2.28 seconds
Started May 28 02:47:21 PM PDT 24
Finished May 28 02:47:33 PM PDT 24
Peak memory 209448 kb
Host smart-189a347c-38ea-417e-80ac-bda0b567c99c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823227556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2823227556
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2920026137
Short name T168
Test name
Test status
Simulation time 6853999166 ps
CPU time 66.68 seconds
Started May 28 02:47:17 PM PDT 24
Finished May 28 02:48:34 PM PDT 24
Peak memory 219536 kb
Host smart-4ec435b0-2545-40dd-9ab2-cad6b3a1d0d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920026137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2920026137
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.1939207684
Short name T542
Test name
Test status
Simulation time 2047789051 ps
CPU time 4.2 seconds
Started May 28 02:47:15 PM PDT 24
Finished May 28 02:47:31 PM PDT 24
Peak memory 217852 kb
Host smart-3097bc2f-ffe4-4a60-8acf-9e718490337d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939207684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.1939207684
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.2536352240
Short name T66
Test name
Test status
Simulation time 688783126 ps
CPU time 3.71 seconds
Started May 28 02:47:17 PM PDT 24
Finished May 28 02:47:32 PM PDT 24
Peak memory 213296 kb
Host smart-c4bd1180-0fe7-4a35-b9f5-531fb9aaaf5b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536352240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.2536352240
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.1288164337
Short name T547
Test name
Test status
Simulation time 1572221969 ps
CPU time 48.22 seconds
Started May 28 02:47:17 PM PDT 24
Finished May 28 02:48:16 PM PDT 24
Peak memory 267156 kb
Host smart-cc209b61-8edd-47b7-a5ca-1387f4f9ed95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288164337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.1288164337
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3801464067
Short name T290
Test name
Test status
Simulation time 6501023470 ps
CPU time 35.46 seconds
Started May 28 02:47:15 PM PDT 24
Finished May 28 02:48:02 PM PDT 24
Peak memory 250804 kb
Host smart-2e106b5e-80a3-4500-b9e3-acc210d350a1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801464067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3801464067
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.371271544
Short name T536
Test name
Test status
Simulation time 121407659 ps
CPU time 4.39 seconds
Started May 28 02:47:22 PM PDT 24
Finished May 28 02:47:35 PM PDT 24
Peak memory 217928 kb
Host smart-06348f4f-89ed-494f-ba89-16b0834a16cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371271544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.371271544
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.603696167
Short name T782
Test name
Test status
Simulation time 1338053226 ps
CPU time 14.01 seconds
Started May 28 02:47:15 PM PDT 24
Finished May 28 02:47:40 PM PDT 24
Peak memory 218812 kb
Host smart-a628b5e5-27c1-43a5-9ded-7214ee37bfa3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603696167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.603696167
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2254917494
Short name T523
Test name
Test status
Simulation time 412152964 ps
CPU time 9.27 seconds
Started May 28 02:47:16 PM PDT 24
Finished May 28 02:47:37 PM PDT 24
Peak memory 225928 kb
Host smart-2653deea-8923-456f-8258-8aab3acd92cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254917494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2254917494
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.661695710
Short name T765
Test name
Test status
Simulation time 387233269 ps
CPU time 8.41 seconds
Started May 28 02:47:15 PM PDT 24
Finished May 28 02:47:35 PM PDT 24
Peak memory 217876 kb
Host smart-3e561145-2379-4eed-80c9-b1ad2cc3e40c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661695710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.661695710
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3114030253
Short name T674
Test name
Test status
Simulation time 448114579 ps
CPU time 7.15 seconds
Started May 28 02:47:21 PM PDT 24
Finished May 28 02:47:38 PM PDT 24
Peak memory 217988 kb
Host smart-8fe09cb8-68dc-46b7-90cf-7ed72ce951bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114030253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3114030253
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1255981566
Short name T858
Test name
Test status
Simulation time 82425797 ps
CPU time 1.74 seconds
Started May 28 02:47:14 PM PDT 24
Finished May 28 02:47:27 PM PDT 24
Peak memory 217656 kb
Host smart-c4ed2411-858d-42ca-b432-227d8b5d9eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255981566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1255981566
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.80786037
Short name T816
Test name
Test status
Simulation time 1116448200 ps
CPU time 27.56 seconds
Started May 28 02:47:21 PM PDT 24
Finished May 28 02:47:58 PM PDT 24
Peak memory 250852 kb
Host smart-c6bf3651-7446-4e64-ac05-593a16d6da05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80786037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.80786037
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.332964748
Short name T532
Test name
Test status
Simulation time 48837629 ps
CPU time 7.01 seconds
Started May 28 02:47:16 PM PDT 24
Finished May 28 02:47:35 PM PDT 24
Peak memory 250856 kb
Host smart-c5a8ba3f-0798-4859-8bb3-3ff9f10aa656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332964748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.332964748
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.2070856115
Short name T647
Test name
Test status
Simulation time 32913251070 ps
CPU time 268.6 seconds
Started May 28 02:47:12 PM PDT 24
Finished May 28 02:51:53 PM PDT 24
Peak memory 267292 kb
Host smart-a61dfffa-42f0-4c94-bf01-059ee8631eb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070856115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.2070856115
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.23618827
Short name T230
Test name
Test status
Simulation time 38202290 ps
CPU time 0.85 seconds
Started May 28 02:47:21 PM PDT 24
Finished May 28 02:47:31 PM PDT 24
Peak memory 211492 kb
Host smart-5deb6b88-ac1d-43ec-90f4-2a3a09ff799a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23618827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_volatile_unlock_smoke.23618827
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.487201333
Short name T13
Test name
Test status
Simulation time 20977064 ps
CPU time 1.25 seconds
Started May 28 02:47:27 PM PDT 24
Finished May 28 02:47:35 PM PDT 24
Peak memory 209436 kb
Host smart-2c5c2f38-0a2f-47f0-9c28-1b68d800df5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487201333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.487201333
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.4207020503
Short name T593
Test name
Test status
Simulation time 745484569 ps
CPU time 13.72 seconds
Started May 28 02:47:22 PM PDT 24
Finished May 28 02:47:44 PM PDT 24
Peak memory 217852 kb
Host smart-79649823-a191-4b52-a9bc-32ebd3b33ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207020503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.4207020503
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.2531196930
Short name T802
Test name
Test status
Simulation time 392794811 ps
CPU time 5.55 seconds
Started May 28 02:47:25 PM PDT 24
Finished May 28 02:47:38 PM PDT 24
Peak memory 216848 kb
Host smart-76c67d42-0af5-415a-aa44-eecfcb0c74a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531196930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.2531196930
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2802897834
Short name T693
Test name
Test status
Simulation time 2938261423 ps
CPU time 45.59 seconds
Started May 28 02:47:28 PM PDT 24
Finished May 28 02:48:19 PM PDT 24
Peak memory 218800 kb
Host smart-b1da81ff-6da3-4f23-b11e-20cfa48614e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802897834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2802897834
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.1718067433
Short name T842
Test name
Test status
Simulation time 1815053914 ps
CPU time 12.63 seconds
Started May 28 02:47:25 PM PDT 24
Finished May 28 02:47:45 PM PDT 24
Peak memory 217792 kb
Host smart-7a5b8b17-cc30-4875-ae3f-a189d31a797b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718067433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.1718067433
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.1911215676
Short name T431
Test name
Test status
Simulation time 1061785549 ps
CPU time 4.62 seconds
Started May 28 02:47:17 PM PDT 24
Finished May 28 02:47:33 PM PDT 24
Peak memory 213260 kb
Host smart-fed08306-5b66-47b8-82c1-150240c95e8d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911215676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.1911215676
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2411264129
Short name T487
Test name
Test status
Simulation time 2967163080 ps
CPU time 46.17 seconds
Started May 28 02:47:15 PM PDT 24
Finished May 28 02:48:13 PM PDT 24
Peak memory 275484 kb
Host smart-01a841f7-1c28-44b9-96e5-ed6d872b6565
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411264129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2411264129
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.662038292
Short name T281
Test name
Test status
Simulation time 2577751295 ps
CPU time 21.22 seconds
Started May 28 02:47:16 PM PDT 24
Finished May 28 02:47:49 PM PDT 24
Peak memory 250896 kb
Host smart-042dd9c1-6f0d-4068-8b4a-8c0e33ee5885
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662038292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_
jtag_state_post_trans.662038292
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2663988031
Short name T173
Test name
Test status
Simulation time 37730909 ps
CPU time 2.43 seconds
Started May 28 02:47:18 PM PDT 24
Finished May 28 02:47:31 PM PDT 24
Peak memory 217836 kb
Host smart-caef36ca-886d-4ff2-95ce-9f19f2e8c214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663988031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2663988031
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2919070066
Short name T813
Test name
Test status
Simulation time 449589816 ps
CPU time 20.32 seconds
Started May 28 02:47:26 PM PDT 24
Finished May 28 02:47:54 PM PDT 24
Peak memory 225944 kb
Host smart-fc54f6e4-8ac5-47b8-870f-4244c9fed304
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919070066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2919070066
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.711582473
Short name T695
Test name
Test status
Simulation time 775335181 ps
CPU time 10.27 seconds
Started May 28 02:47:25 PM PDT 24
Finished May 28 02:47:43 PM PDT 24
Peak memory 225304 kb
Host smart-a53eb50e-a31e-4559-981e-4c3f6a154af3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711582473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.711582473
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.765043571
Short name T273
Test name
Test status
Simulation time 6708066205 ps
CPU time 12.27 seconds
Started May 28 02:47:25 PM PDT 24
Finished May 28 02:47:45 PM PDT 24
Peak memory 217992 kb
Host smart-e9f27c1a-eb11-415e-8ba0-5b9be7538689
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765043571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.765043571
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2001091718
Short name T243
Test name
Test status
Simulation time 2794634361 ps
CPU time 7.78 seconds
Started May 28 02:47:15 PM PDT 24
Finished May 28 02:47:35 PM PDT 24
Peak memory 218040 kb
Host smart-1b881f53-8d0a-4ab6-a3ca-d9e5d3a5c088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001091718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2001091718
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2695068242
Short name T603
Test name
Test status
Simulation time 107772156 ps
CPU time 3.86 seconds
Started May 28 02:47:14 PM PDT 24
Finished May 28 02:47:30 PM PDT 24
Peak memory 217844 kb
Host smart-ee6e11f0-33a5-4073-9e5f-843a7c73dba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695068242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2695068242
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.3678818490
Short name T420
Test name
Test status
Simulation time 240475515 ps
CPU time 27 seconds
Started May 28 02:47:14 PM PDT 24
Finished May 28 02:47:52 PM PDT 24
Peak memory 250844 kb
Host smart-b82ec0bf-f789-40a0-8b36-e7a0950606c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678818490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.3678818490
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.631128801
Short name T632
Test name
Test status
Simulation time 73890655 ps
CPU time 6.95 seconds
Started May 28 02:47:21 PM PDT 24
Finished May 28 02:47:37 PM PDT 24
Peak memory 246916 kb
Host smart-f8d09e34-af0a-49d1-9d1c-7878a70e4855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631128801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.631128801
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1258858779
Short name T709
Test name
Test status
Simulation time 3209958731 ps
CPU time 72.61 seconds
Started May 28 02:47:26 PM PDT 24
Finished May 28 02:48:46 PM PDT 24
Peak memory 250900 kb
Host smart-769e15a7-4910-4efb-9e8d-bbd1e54b9728
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258858779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1258858779
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.3354150091
Short name T142
Test name
Test status
Simulation time 17521025906 ps
CPU time 232.46 seconds
Started May 28 02:47:26 PM PDT 24
Finished May 28 02:51:26 PM PDT 24
Peak memory 274444 kb
Host smart-ea8a100d-2122-415d-b8cb-7126180bdc3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3354150091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.3354150091
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2824274371
Short name T798
Test name
Test status
Simulation time 20837592 ps
CPU time 0.82 seconds
Started May 28 02:47:22 PM PDT 24
Finished May 28 02:47:32 PM PDT 24
Peak memory 211484 kb
Host smart-debad29a-274f-44fb-bd6a-5c394adef373
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824274371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2824274371
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.2593904035
Short name T673
Test name
Test status
Simulation time 210673774 ps
CPU time 1.13 seconds
Started May 28 02:47:26 PM PDT 24
Finished May 28 02:47:34 PM PDT 24
Peak memory 209400 kb
Host smart-f746704c-7b19-4820-971f-e5292d7384ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593904035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.2593904035
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.3096495315
Short name T354
Test name
Test status
Simulation time 2991182773 ps
CPU time 16.64 seconds
Started May 28 02:47:28 PM PDT 24
Finished May 28 02:47:50 PM PDT 24
Peak memory 219032 kb
Host smart-74d30020-e908-46d8-be93-270b755589b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096495315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.3096495315
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.3798241019
Short name T169
Test name
Test status
Simulation time 1824111613 ps
CPU time 6.03 seconds
Started May 28 02:47:26 PM PDT 24
Finished May 28 02:47:39 PM PDT 24
Peak memory 217052 kb
Host smart-51e70cb5-da41-4da0-b7a5-58ac471b3f9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798241019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.3798241019
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.211920049
Short name T513
Test name
Test status
Simulation time 32363820424 ps
CPU time 53.73 seconds
Started May 28 02:47:25 PM PDT 24
Finished May 28 02:48:26 PM PDT 24
Peak memory 218244 kb
Host smart-ded6dd0d-71d1-4fa3-9085-7d526c53fab3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211920049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er
rors.211920049
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.1490214076
Short name T751
Test name
Test status
Simulation time 455002673 ps
CPU time 5.72 seconds
Started May 28 02:47:27 PM PDT 24
Finished May 28 02:47:39 PM PDT 24
Peak memory 217788 kb
Host smart-e0e0ad4d-73b7-4e78-b3b3-50695989bb5b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490214076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.1490214076
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3494249423
Short name T875
Test name
Test status
Simulation time 2244306118 ps
CPU time 11.24 seconds
Started May 28 02:47:26 PM PDT 24
Finished May 28 02:47:44 PM PDT 24
Peak memory 213836 kb
Host smart-6e66aa05-82dd-497d-83de-7b01e15df4a2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494249423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3494249423
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.478692421
Short name T27
Test name
Test status
Simulation time 938464601 ps
CPU time 48.54 seconds
Started May 28 02:47:25 PM PDT 24
Finished May 28 02:48:21 PM PDT 24
Peak memory 250772 kb
Host smart-8e1be5d8-e598-4298-91bf-11f1f9c9980e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478692421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.478692421
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.2907740079
Short name T578
Test name
Test status
Simulation time 904745719 ps
CPU time 10.39 seconds
Started May 28 02:47:24 PM PDT 24
Finished May 28 02:47:42 PM PDT 24
Peak memory 222792 kb
Host smart-169e0512-7454-4069-9e51-8a073f77d9be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907740079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.2907740079
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1424839422
Short name T471
Test name
Test status
Simulation time 36119156 ps
CPU time 2.48 seconds
Started May 28 02:47:25 PM PDT 24
Finished May 28 02:47:35 PM PDT 24
Peak memory 217840 kb
Host smart-73db31c3-28ca-4d1d-9abc-8c0739d54e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424839422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1424839422
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1327002096
Short name T516
Test name
Test status
Simulation time 195990722 ps
CPU time 10.72 seconds
Started May 28 02:47:28 PM PDT 24
Finished May 28 02:47:44 PM PDT 24
Peak memory 225912 kb
Host smart-2d73a9d9-e292-4257-a931-e6d98bceaad3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327002096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1327002096
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.256115747
Short name T507
Test name
Test status
Simulation time 394669449 ps
CPU time 11.24 seconds
Started May 28 02:47:26 PM PDT 24
Finished May 28 02:47:44 PM PDT 24
Peak memory 217804 kb
Host smart-efa783e4-6ac7-4bfe-9d4e-437af83dfdae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256115747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.256115747
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1599478119
Short name T409
Test name
Test status
Simulation time 1174489113 ps
CPU time 7.43 seconds
Started May 28 02:47:27 PM PDT 24
Finished May 28 02:47:41 PM PDT 24
Peak memory 217816 kb
Host smart-70a433c7-68bb-40c4-a7bd-62e02474c92d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599478119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1599478119
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.700248315
Short name T599
Test name
Test status
Simulation time 1566996043 ps
CPU time 15.06 seconds
Started May 28 02:47:26 PM PDT 24
Finished May 28 02:47:48 PM PDT 24
Peak memory 217892 kb
Host smart-5359f2be-4cc1-40b4-9199-6d4985823af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700248315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.700248315
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1645159588
Short name T481
Test name
Test status
Simulation time 49533039 ps
CPU time 1.78 seconds
Started May 28 02:47:25 PM PDT 24
Finished May 28 02:47:34 PM PDT 24
Peak memory 213596 kb
Host smart-58e37810-258a-4c30-ba36-89c202f5e57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645159588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1645159588
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.2473616785
Short name T287
Test name
Test status
Simulation time 493673827 ps
CPU time 22.7 seconds
Started May 28 02:47:23 PM PDT 24
Finished May 28 02:47:54 PM PDT 24
Peak memory 250820 kb
Host smart-d7ca7076-6bf5-4b01-bcaf-abba1dd31033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473616785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.2473616785
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.3705878616
Short name T228
Test name
Test status
Simulation time 78196767 ps
CPU time 7.4 seconds
Started May 28 02:47:27 PM PDT 24
Finished May 28 02:47:41 PM PDT 24
Peak memory 247316 kb
Host smart-104cf929-b0b6-470e-9317-9e99bc2b1251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705878616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.3705878616
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.1669752002
Short name T182
Test name
Test status
Simulation time 6371797854 ps
CPU time 97.47 seconds
Started May 28 02:47:27 PM PDT 24
Finished May 28 02:49:11 PM PDT 24
Peak memory 226004 kb
Host smart-cc887127-bd02-41b8-a758-e42f3ec318f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669752002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.1669752002
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.3300936538
Short name T545
Test name
Test status
Simulation time 50740356 ps
CPU time 0.92 seconds
Started May 28 02:47:29 PM PDT 24
Finished May 28 02:47:35 PM PDT 24
Peak memory 212900 kb
Host smart-ec0f6ff2-3721-42a8-947e-dff58ec5b19f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300936538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.3300936538
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.57821002
Short name T254
Test name
Test status
Simulation time 13935838 ps
CPU time 1.07 seconds
Started May 28 02:47:40 PM PDT 24
Finished May 28 02:47:42 PM PDT 24
Peak memory 209596 kb
Host smart-450dc997-dd31-4e04-a70a-146fa50cf779
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57821002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.57821002
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.484719474
Short name T422
Test name
Test status
Simulation time 848350966 ps
CPU time 14.92 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:48:02 PM PDT 24
Peak memory 217828 kb
Host smart-393e2757-8fe3-4c13-9fa4-54926f8ae5f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484719474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.484719474
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3565614698
Short name T573
Test name
Test status
Simulation time 313038150 ps
CPU time 4.78 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:47:52 PM PDT 24
Peak memory 209424 kb
Host smart-a3963f53-c334-4391-9e4e-74faa32ac3b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565614698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3565614698
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.664159724
Short name T429
Test name
Test status
Simulation time 19383846336 ps
CPU time 67.77 seconds
Started May 28 02:47:42 PM PDT 24
Finished May 28 02:48:53 PM PDT 24
Peak memory 218844 kb
Host smart-3d9bd355-d4b1-4632-93c3-84c6d8379c52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664159724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.664159724
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1192994900
Short name T625
Test name
Test status
Simulation time 96287985 ps
CPU time 3.67 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:47:51 PM PDT 24
Peak memory 217752 kb
Host smart-f16dbb37-ce76-4b94-b7f4-41686236eb6e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192994900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1192994900
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.1268265626
Short name T656
Test name
Test status
Simulation time 1123077738 ps
CPU time 9.7 seconds
Started May 28 02:47:44 PM PDT 24
Finished May 28 02:47:58 PM PDT 24
Peak memory 213512 kb
Host smart-473e5731-d301-4707-8877-e6a37a57c681
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268265626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.1268265626
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3505761963
Short name T356
Test name
Test status
Simulation time 4073136388 ps
CPU time 139.21 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:50:07 PM PDT 24
Peak memory 283680 kb
Host smart-1d2ebbae-8763-42cc-8fcb-5b99cf9b1589
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505761963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3505761963
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3642365755
Short name T546
Test name
Test status
Simulation time 1075383478 ps
CPU time 36.19 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:48:23 PM PDT 24
Peak memory 250772 kb
Host smart-7c08188b-b4c8-4f99-8aef-c8f99bba849d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642365755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3642365755
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.2567408833
Short name T285
Test name
Test status
Simulation time 49602073 ps
CPU time 2.21 seconds
Started May 28 02:47:42 PM PDT 24
Finished May 28 02:47:48 PM PDT 24
Peak memory 217920 kb
Host smart-2d189ed3-3d28-42c8-ae6e-8cf69e745ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567408833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.2567408833
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3414949286
Short name T746
Test name
Test status
Simulation time 1831269112 ps
CPU time 15.72 seconds
Started May 28 02:47:40 PM PDT 24
Finished May 28 02:47:58 PM PDT 24
Peak memory 225860 kb
Host smart-e434dfc4-943c-4468-9561-9e20a7509fc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414949286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3414949286
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2923983233
Short name T452
Test name
Test status
Simulation time 254368484 ps
CPU time 11.15 seconds
Started May 28 02:47:40 PM PDT 24
Finished May 28 02:47:52 PM PDT 24
Peak memory 225848 kb
Host smart-91855e47-73da-4cf3-8632-fc882bbfd0f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923983233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2923983233
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.134240223
Short name T855
Test name
Test status
Simulation time 348518099 ps
CPU time 13.19 seconds
Started May 28 02:47:44 PM PDT 24
Finished May 28 02:48:01 PM PDT 24
Peak memory 217916 kb
Host smart-6bda2193-4bcc-47eb-8460-44d77ddb69a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134240223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.134240223
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.656180274
Short name T491
Test name
Test status
Simulation time 1544865914 ps
CPU time 13.56 seconds
Started May 28 02:47:41 PM PDT 24
Finished May 28 02:47:58 PM PDT 24
Peak memory 217936 kb
Host smart-499bd6d1-a826-4540-8529-34afba2b6032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656180274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.656180274
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.752115727
Short name T64
Test name
Test status
Simulation time 905830767 ps
CPU time 4.21 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:47:52 PM PDT 24
Peak memory 214424 kb
Host smart-f2122b58-147d-431a-a39f-18ba8320bf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752115727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.752115727
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1832793188
Short name T677
Test name
Test status
Simulation time 666843255 ps
CPU time 28.19 seconds
Started May 28 02:47:42 PM PDT 24
Finished May 28 02:48:14 PM PDT 24
Peak memory 250836 kb
Host smart-27be7860-43ca-4c85-a6d9-bfc68d33e24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832793188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1832793188
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3054007036
Short name T836
Test name
Test status
Simulation time 441013923 ps
CPU time 8.86 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:47:56 PM PDT 24
Peak memory 250844 kb
Host smart-dc969004-cf84-4f84-b6aa-c509db95cb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054007036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3054007036
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.146610380
Short name T370
Test name
Test status
Simulation time 13497166 ps
CPU time 0.87 seconds
Started May 28 02:47:41 PM PDT 24
Finished May 28 02:47:45 PM PDT 24
Peak memory 211552 kb
Host smart-f9f489bd-b533-4b42-b46c-6155d0713c1a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146610380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.146610380
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.1088613006
Short name T144
Test name
Test status
Simulation time 29740599 ps
CPU time 1.43 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:47:49 PM PDT 24
Peak memory 209428 kb
Host smart-8f6ad1df-4860-4c62-8864-1c9fa1e8c204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088613006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.1088613006
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.2912709325
Short name T503
Test name
Test status
Simulation time 421202535 ps
CPU time 17.7 seconds
Started May 28 02:47:45 PM PDT 24
Finished May 28 02:48:06 PM PDT 24
Peak memory 217852 kb
Host smart-0399cc61-5893-4ea0-b64d-3bedc7dfcdeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912709325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.2912709325
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.2068536884
Short name T571
Test name
Test status
Simulation time 203108291 ps
CPU time 2.61 seconds
Started May 28 02:47:42 PM PDT 24
Finished May 28 02:47:49 PM PDT 24
Peak memory 216652 kb
Host smart-08096f9f-d626-46d2-98d8-2ca21723553a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068536884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.2068536884
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.4087988960
Short name T640
Test name
Test status
Simulation time 1552248427 ps
CPU time 19.38 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:48:06 PM PDT 24
Peak memory 217728 kb
Host smart-b8b9f5ab-4bed-499b-8f0a-ab59d88c39d2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087988960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.4087988960
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.2364827263
Short name T280
Test name
Test status
Simulation time 1373397494 ps
CPU time 10.27 seconds
Started May 28 02:47:41 PM PDT 24
Finished May 28 02:47:54 PM PDT 24
Peak memory 217860 kb
Host smart-7dd5d269-30f4-436d-a710-9b1491a581be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364827263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.2364827263
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.2318834025
Short name T488
Test name
Test status
Simulation time 816252217 ps
CPU time 10.82 seconds
Started May 28 02:47:40 PM PDT 24
Finished May 28 02:47:52 PM PDT 24
Peak memory 213400 kb
Host smart-eff18c25-0b24-414b-a7fd-0b30cafb682c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318834025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.2318834025
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2991219306
Short name T289
Test name
Test status
Simulation time 927352494 ps
CPU time 38.97 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:48:26 PM PDT 24
Peak memory 250744 kb
Host smart-e51db5b4-fa99-4377-949b-c724b6465907
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991219306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2991219306
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1090446810
Short name T566
Test name
Test status
Simulation time 1588081345 ps
CPU time 7.33 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:47:54 PM PDT 24
Peak memory 222704 kb
Host smart-e9130d90-58e3-46b0-a953-7db77c54dcca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090446810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1090446810
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.2605081001
Short name T773
Test name
Test status
Simulation time 65137435 ps
CPU time 2.61 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:47:50 PM PDT 24
Peak memory 217872 kb
Host smart-d8f79818-4c6c-42f8-a4a4-08327c8fdac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605081001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.2605081001
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.3292606201
Short name T392
Test name
Test status
Simulation time 505944732 ps
CPU time 12.23 seconds
Started May 28 02:47:40 PM PDT 24
Finished May 28 02:47:54 PM PDT 24
Peak memory 218804 kb
Host smart-fae6daf8-e1a5-494d-b591-ae49d811ff28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292606201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.3292606201
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3897174610
Short name T854
Test name
Test status
Simulation time 6424105787 ps
CPU time 12.62 seconds
Started May 28 02:47:41 PM PDT 24
Finished May 28 02:47:58 PM PDT 24
Peak memory 218072 kb
Host smart-c53b00b6-052d-461a-9d76-51ac5112218c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897174610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3897174610
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2810115488
Short name T57
Test name
Test status
Simulation time 645989484 ps
CPU time 9.67 seconds
Started May 28 02:47:42 PM PDT 24
Finished May 28 02:47:55 PM PDT 24
Peak memory 217932 kb
Host smart-5e138341-2f60-4d7b-8e92-9250334eda5a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810115488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2810115488
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.4113828644
Short name T614
Test name
Test status
Simulation time 781335266 ps
CPU time 6.59 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:47:54 PM PDT 24
Peak memory 217916 kb
Host smart-cc159151-3f38-4307-b842-b36cfa284f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113828644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.4113828644
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1622725356
Short name T549
Test name
Test status
Simulation time 89481609 ps
CPU time 1.78 seconds
Started May 28 02:47:42 PM PDT 24
Finished May 28 02:47:48 PM PDT 24
Peak memory 213528 kb
Host smart-a7ea7c31-3725-439c-904d-63c716b17d92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622725356 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1622725356
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.2929882734
Short name T251
Test name
Test status
Simulation time 704633721 ps
CPU time 29.64 seconds
Started May 28 02:47:42 PM PDT 24
Finished May 28 02:48:15 PM PDT 24
Peak memory 250872 kb
Host smart-627f16ec-36ec-4de1-9207-c4a5231758b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929882734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.2929882734
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.3823506237
Short name T391
Test name
Test status
Simulation time 213256239 ps
CPU time 6.27 seconds
Started May 28 02:47:41 PM PDT 24
Finished May 28 02:47:49 PM PDT 24
Peak memory 250308 kb
Host smart-8872ec9b-387a-484a-8390-f42de7aeb998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823506237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.3823506237
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.227911639
Short name T265
Test name
Test status
Simulation time 4273753763 ps
CPU time 98.21 seconds
Started May 28 02:47:44 PM PDT 24
Finished May 28 02:49:26 PM PDT 24
Peak memory 250936 kb
Host smart-71ded694-6787-4065-8cf8-43622243630f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227911639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.227911639
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.861811075
Short name T149
Test name
Test status
Simulation time 438582730549 ps
CPU time 398.11 seconds
Started May 28 02:47:42 PM PDT 24
Finished May 28 02:54:24 PM PDT 24
Peak memory 283876 kb
Host smart-4fe91405-00ab-4d0e-ab09-d7c76055570f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=861811075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.861811075
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.2798750232
Short name T450
Test name
Test status
Simulation time 12519996 ps
CPU time 0.89 seconds
Started May 28 02:47:42 PM PDT 24
Finished May 28 02:47:47 PM PDT 24
Peak memory 211468 kb
Host smart-b5714f60-a02d-484c-854a-1f5cff871778
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798750232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.2798750232
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1978263010
Short name T425
Test name
Test status
Simulation time 25605628 ps
CPU time 0.87 seconds
Started May 28 02:47:52 PM PDT 24
Finished May 28 02:47:56 PM PDT 24
Peak memory 209356 kb
Host smart-7e2868d0-0230-43d3-a978-3dc0e8819158
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978263010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1978263010
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2217869979
Short name T707
Test name
Test status
Simulation time 1274389051 ps
CPU time 12.43 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:47:59 PM PDT 24
Peak memory 217852 kb
Host smart-bbbe6942-4593-4360-be9f-f28dd7700026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217869979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2217869979
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.2076429025
Short name T359
Test name
Test status
Simulation time 660084557 ps
CPU time 17.1 seconds
Started May 28 02:47:44 PM PDT 24
Finished May 28 02:48:05 PM PDT 24
Peak memory 209404 kb
Host smart-4785d6fe-eae9-450f-923b-8044aeae4870
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076429025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.2076429025
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2533895183
Short name T375
Test name
Test status
Simulation time 1402813094 ps
CPU time 45.01 seconds
Started May 28 02:47:42 PM PDT 24
Finished May 28 02:48:32 PM PDT 24
Peak memory 217760 kb
Host smart-a24c929b-fbfd-4633-ba7a-4b3d38f47120
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533895183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2533895183
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2085835661
Short name T805
Test name
Test status
Simulation time 264392027 ps
CPU time 5.02 seconds
Started May 28 02:47:41 PM PDT 24
Finished May 28 02:47:48 PM PDT 24
Peak memory 217740 kb
Host smart-244cde7a-36b7-4c4f-8daa-a22e18953268
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085835661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2085835661
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.1817223523
Short name T493
Test name
Test status
Simulation time 89906549 ps
CPU time 2.03 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:47:49 PM PDT 24
Peak memory 212960 kb
Host smart-912e078a-a0e0-4973-aee9-ebd81256ccf7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817223523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.1817223523
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.4242097876
Short name T98
Test name
Test status
Simulation time 8919145045 ps
CPU time 43.49 seconds
Started May 28 02:47:42 PM PDT 24
Finished May 28 02:48:29 PM PDT 24
Peak memory 275488 kb
Host smart-475678da-3d71-4ce8-85d8-8aca6873293a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242097876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.4242097876
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2918746266
Short name T4
Test name
Test status
Simulation time 2800711484 ps
CPU time 14.62 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:48:01 PM PDT 24
Peak memory 250032 kb
Host smart-51682f1f-4f27-4fd3-b544-58231ac873bf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918746266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2918746266
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.2913466336
Short name T652
Test name
Test status
Simulation time 41063118 ps
CPU time 2.12 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:47:49 PM PDT 24
Peak memory 217856 kb
Host smart-42f5660a-5e3d-474a-a4a0-134b5b7687af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913466336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.2913466336
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.3680932686
Short name T426
Test name
Test status
Simulation time 567541816 ps
CPU time 13.87 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:48:01 PM PDT 24
Peak memory 218800 kb
Host smart-742c9e59-1649-47d7-86e4-99e45cb42303
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680932686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3680932686
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.3212628313
Short name T561
Test name
Test status
Simulation time 686574092 ps
CPU time 16.82 seconds
Started May 28 02:47:59 PM PDT 24
Finished May 28 02:48:20 PM PDT 24
Peak memory 217856 kb
Host smart-9a6a8dd8-dc34-4557-bbee-ad3186140f2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212628313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.3212628313
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3204827263
Short name T633
Test name
Test status
Simulation time 333173141 ps
CPU time 7.29 seconds
Started May 28 02:47:42 PM PDT 24
Finished May 28 02:47:53 PM PDT 24
Peak memory 217916 kb
Host smart-fed0f218-4ea0-441a-9a8f-d21342bf2aa6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204827263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3204827263
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.583231974
Short name T528
Test name
Test status
Simulation time 478435421 ps
CPU time 7.67 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:47:55 PM PDT 24
Peak memory 217924 kb
Host smart-bf97dcc1-72b7-4136-bece-1fc5e84701ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583231974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.583231974
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.2302664135
Short name T697
Test name
Test status
Simulation time 229700729 ps
CPU time 1.76 seconds
Started May 28 02:47:42 PM PDT 24
Finished May 28 02:47:48 PM PDT 24
Peak memory 213516 kb
Host smart-e42bd03f-2647-45fa-aa36-147bd532c501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302664135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.2302664135
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.2897706905
Short name T439
Test name
Test status
Simulation time 652041765 ps
CPU time 40.2 seconds
Started May 28 02:47:41 PM PDT 24
Finished May 28 02:48:25 PM PDT 24
Peak memory 250792 kb
Host smart-68c93776-9db5-4b61-ae2a-e7700ba87b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897706905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.2897706905
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.1112477634
Short name T341
Test name
Test status
Simulation time 79050830 ps
CPU time 6.32 seconds
Started May 28 02:47:43 PM PDT 24
Finished May 28 02:47:54 PM PDT 24
Peak memory 246992 kb
Host smart-ea1e221d-f1a7-4fbe-ad09-65026eff4795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112477634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.1112477634
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.631994576
Short name T267
Test name
Test status
Simulation time 4492224123 ps
CPU time 101.08 seconds
Started May 28 02:47:51 PM PDT 24
Finished May 28 02:49:35 PM PDT 24
Peak memory 250956 kb
Host smart-3efcd5ec-0a39-4b04-aac5-917688e10c6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631994576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.631994576
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all_with_rand_reset.426240414
Short name T165
Test name
Test status
Simulation time 156220142881 ps
CPU time 413.2 seconds
Started May 28 02:47:51 PM PDT 24
Finished May 28 02:54:47 PM PDT 24
Peak memory 295784 kb
Host smart-93df683c-c0b5-40b2-a2b8-c91d8cf5fb65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=426240414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_stress_all_with_rand_reset.426240414
Directory /workspace/18.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1035140110
Short name T624
Test name
Test status
Simulation time 93353474 ps
CPU time 0.87 seconds
Started May 28 02:47:42 PM PDT 24
Finished May 28 02:47:46 PM PDT 24
Peak memory 211496 kb
Host smart-794f66cc-b331-4b24-8870-e5165263ad3d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035140110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.1035140110
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1876633076
Short name T661
Test name
Test status
Simulation time 73597113 ps
CPU time 0.91 seconds
Started May 28 02:47:56 PM PDT 24
Finished May 28 02:48:00 PM PDT 24
Peak memory 209420 kb
Host smart-6b8b9d9e-24e8-42ce-820c-72af0619f913
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876633076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1876633076
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.3965676927
Short name T815
Test name
Test status
Simulation time 1945314103 ps
CPU time 8.54 seconds
Started May 28 02:47:54 PM PDT 24
Finished May 28 02:48:06 PM PDT 24
Peak memory 217852 kb
Host smart-eedf2075-f25c-49f1-864d-cdc1d1ffaf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965676927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.3965676927
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.2439005216
Short name T33
Test name
Test status
Simulation time 2063001242 ps
CPU time 5.54 seconds
Started May 28 02:47:56 PM PDT 24
Finished May 28 02:48:05 PM PDT 24
Peak memory 209144 kb
Host smart-0bf62f4b-850c-4331-a55d-98c2db5810a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439005216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.2439005216
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.1346945541
Short name T58
Test name
Test status
Simulation time 3502977814 ps
CPU time 20.53 seconds
Started May 28 02:47:56 PM PDT 24
Finished May 28 02:48:20 PM PDT 24
Peak memory 217716 kb
Host smart-16c157dd-65a1-4d9e-b810-84895f722404
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346945541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.1346945541
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.1249651090
Short name T684
Test name
Test status
Simulation time 968218384 ps
CPU time 13.65 seconds
Started May 28 02:47:55 PM PDT 24
Finished May 28 02:48:12 PM PDT 24
Peak memory 217844 kb
Host smart-02efa238-c8ca-42f2-ae87-e9d34d2bbc0f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249651090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.1249651090
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1417548768
Short name T257
Test name
Test status
Simulation time 371983770 ps
CPU time 3.32 seconds
Started May 28 02:47:54 PM PDT 24
Finished May 28 02:48:01 PM PDT 24
Peak memory 212836 kb
Host smart-fe3ab391-047c-4b43-846a-d8779a4f655c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417548768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1417548768
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.914760574
Short name T713
Test name
Test status
Simulation time 4258695356 ps
CPU time 39.6 seconds
Started May 28 02:47:55 PM PDT 24
Finished May 28 02:48:38 PM PDT 24
Peak memory 250892 kb
Host smart-37635638-dde9-4453-95dc-e906c50035dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914760574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_state_failure.914760574
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1176420235
Short name T757
Test name
Test status
Simulation time 699130710 ps
CPU time 15.45 seconds
Started May 28 02:47:53 PM PDT 24
Finished May 28 02:48:12 PM PDT 24
Peak memory 250792 kb
Host smart-7ca3d6d9-ec10-4f6d-ba7f-8489d32ff07f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176420235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1176420235
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.3175093585
Short name T790
Test name
Test status
Simulation time 209566152 ps
CPU time 2.07 seconds
Started May 28 02:47:52 PM PDT 24
Finished May 28 02:47:58 PM PDT 24
Peak memory 217820 kb
Host smart-0dea2fb0-55a3-4472-9c95-2a151fd30ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175093585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.3175093585
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.152966616
Short name T540
Test name
Test status
Simulation time 644784606 ps
CPU time 10.32 seconds
Started May 28 02:47:58 PM PDT 24
Finished May 28 02:48:12 PM PDT 24
Peak memory 218080 kb
Host smart-f16a6601-7b77-4cc9-8090-2a236fd63eb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152966616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.152966616
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.2816537326
Short name T24
Test name
Test status
Simulation time 724084709 ps
CPU time 11.96 seconds
Started May 28 02:47:54 PM PDT 24
Finished May 28 02:48:10 PM PDT 24
Peak memory 217860 kb
Host smart-2d55f072-c2e2-4d0c-a175-e145c27a7f5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816537326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.2816537326
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1344359693
Short name T235
Test name
Test status
Simulation time 533713021 ps
CPU time 10.04 seconds
Started May 28 02:47:58 PM PDT 24
Finished May 28 02:48:12 PM PDT 24
Peak memory 217664 kb
Host smart-8ab3d639-6411-4bb0-952b-fb51e753f6e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344359693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1344359693
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3851926516
Short name T389
Test name
Test status
Simulation time 95213791 ps
CPU time 1.65 seconds
Started May 28 02:47:50 PM PDT 24
Finished May 28 02:47:53 PM PDT 24
Peak memory 213576 kb
Host smart-4c629c06-4b05-4cde-8bde-ae2b78adf528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851926516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3851926516
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.2932501783
Short name T553
Test name
Test status
Simulation time 718916117 ps
CPU time 34.48 seconds
Started May 28 02:47:51 PM PDT 24
Finished May 28 02:48:28 PM PDT 24
Peak memory 250744 kb
Host smart-693e0e2f-1c2d-407c-a949-44400424c9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932501783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.2932501783
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.2667537547
Short name T315
Test name
Test status
Simulation time 93437244 ps
CPU time 7.93 seconds
Started May 28 02:47:51 PM PDT 24
Finished May 28 02:48:02 PM PDT 24
Peak memory 250812 kb
Host smart-c7f049ca-fc95-49e5-a144-a346ea556ae8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667537547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.2667537547
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.4097576941
Short name T590
Test name
Test status
Simulation time 8137663496 ps
CPU time 49.65 seconds
Started May 28 02:47:55 PM PDT 24
Finished May 28 02:48:48 PM PDT 24
Peak memory 271876 kb
Host smart-23cbb280-c87c-4430-bb2d-6a69cb87095a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097576941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.4097576941
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.58370075
Short name T478
Test name
Test status
Simulation time 65239811 ps
CPU time 0.97 seconds
Started May 28 02:47:57 PM PDT 24
Finished May 28 02:48:02 PM PDT 24
Peak memory 211564 kb
Host smart-763c22df-9f78-4497-be3e-4f3cc463cc6a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58370075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_volatile_unlock_smoke.58370075
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.2556369247
Short name T649
Test name
Test status
Simulation time 101048386 ps
CPU time 0.9 seconds
Started May 28 02:46:41 PM PDT 24
Finished May 28 02:46:58 PM PDT 24
Peak memory 209404 kb
Host smart-119476b4-9205-48ff-bbe1-46fb864fdb74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556369247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.2556369247
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.568073146
Short name T568
Test name
Test status
Simulation time 1078922922 ps
CPU time 10.18 seconds
Started May 28 02:46:42 PM PDT 24
Finished May 28 02:47:08 PM PDT 24
Peak memory 217924 kb
Host smart-bda18b70-8a58-4f9c-9eaf-9f21cbf5703a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568073146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.568073146
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.493004151
Short name T744
Test name
Test status
Simulation time 193561582 ps
CPU time 5.06 seconds
Started May 28 02:46:42 PM PDT 24
Finished May 28 02:47:02 PM PDT 24
Peak memory 209420 kb
Host smart-00166b07-749a-4d53-af74-45f26fca0f5b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493004151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.493004151
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1329470592
Short name T369
Test name
Test status
Simulation time 5201614991 ps
CPU time 31.3 seconds
Started May 28 02:46:41 PM PDT 24
Finished May 28 02:47:28 PM PDT 24
Peak memory 217884 kb
Host smart-e86373ab-1707-44e1-9f48-6c811abf7b4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329470592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1329470592
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.457945504
Short name T848
Test name
Test status
Simulation time 15525895457 ps
CPU time 8.74 seconds
Started May 28 02:46:43 PM PDT 24
Finished May 28 02:47:07 PM PDT 24
Peak memory 217820 kb
Host smart-f1cfb6b8-573b-40d4-8d57-77ce47a9caac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457945504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.457945504
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2787551905
Short name T770
Test name
Test status
Simulation time 522298403 ps
CPU time 8.4 seconds
Started May 28 02:46:51 PM PDT 24
Finished May 28 02:47:12 PM PDT 24
Peak memory 217872 kb
Host smart-7d4f6c98-1a9e-4249-a3ef-a4de8697f276
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787551905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2787551905
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.1305022714
Short name T353
Test name
Test status
Simulation time 2153062369 ps
CPU time 26.71 seconds
Started May 28 02:46:40 PM PDT 24
Finished May 28 02:47:22 PM PDT 24
Peak memory 213172 kb
Host smart-e07981dc-57ac-4b45-8ebe-da9b62fc711a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305022714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.1305022714
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.3400610848
Short name T97
Test name
Test status
Simulation time 360664230 ps
CPU time 8.1 seconds
Started May 28 02:46:43 PM PDT 24
Finished May 28 02:47:07 PM PDT 24
Peak memory 213736 kb
Host smart-635302eb-a71e-41bf-85cc-7f52a7c86987
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400610848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
3400610848
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2239777642
Short name T862
Test name
Test status
Simulation time 1433296061 ps
CPU time 32.04 seconds
Started May 28 02:46:42 PM PDT 24
Finished May 28 02:47:30 PM PDT 24
Peak memory 252328 kb
Host smart-01838ebc-7718-4634-9868-61af0e3469b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239777642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2239777642
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.2356411271
Short name T383
Test name
Test status
Simulation time 1410668055 ps
CPU time 23.07 seconds
Started May 28 02:46:47 PM PDT 24
Finished May 28 02:47:25 PM PDT 24
Peak memory 250468 kb
Host smart-d9d3f90c-0cdc-496b-8dfd-27314300eb5d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356411271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.2356411271
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.14604925
Short name T771
Test name
Test status
Simulation time 117241910 ps
CPU time 3.77 seconds
Started May 28 02:46:42 PM PDT 24
Finished May 28 02:47:02 PM PDT 24
Peak memory 217848 kb
Host smart-95adf5e6-4743-4b98-9f0a-85477a65159e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14604925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.14604925
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.752641132
Short name T73
Test name
Test status
Simulation time 1251564618 ps
CPU time 15.56 seconds
Started May 28 02:46:45 PM PDT 24
Finished May 28 02:47:17 PM PDT 24
Peak memory 214284 kb
Host smart-64def35c-fb3b-43d6-b4d1-dc08e323f432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752641132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.752641132
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2639912419
Short name T88
Test name
Test status
Simulation time 483891741 ps
CPU time 25.3 seconds
Started May 28 02:46:43 PM PDT 24
Finished May 28 02:47:25 PM PDT 24
Peak memory 281852 kb
Host smart-800b72ac-87cb-45e8-ab8a-ae94090eacd6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639912419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2639912419
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.690163887
Short name T497
Test name
Test status
Simulation time 1014531029 ps
CPU time 19.6 seconds
Started May 28 02:46:51 PM PDT 24
Finished May 28 02:47:24 PM PDT 24
Peak memory 218976 kb
Host smart-e6f33189-3216-4161-b72e-e9d053c79a1d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690163887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.690163887
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1266442221
Short name T634
Test name
Test status
Simulation time 592034085 ps
CPU time 13.01 seconds
Started May 28 02:46:44 PM PDT 24
Finished May 28 02:47:13 PM PDT 24
Peak memory 217856 kb
Host smart-7a2be531-2df9-4d72-9766-e7d8dc6fc1b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266442221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1266442221
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.716265858
Short name T456
Test name
Test status
Simulation time 3175684348 ps
CPU time 11.47 seconds
Started May 28 02:46:44 PM PDT 24
Finished May 28 02:47:12 PM PDT 24
Peak memory 217988 kb
Host smart-ef887daf-920a-469d-ae31-91169fb7267f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716265858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.716265858
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.2190537621
Short name T626
Test name
Test status
Simulation time 1483622643 ps
CPU time 13.39 seconds
Started May 28 02:46:41 PM PDT 24
Finished May 28 02:47:10 PM PDT 24
Peak memory 217920 kb
Host smart-b4f89806-ac0f-452a-bdc0-a8d55e709287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190537621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.2190537621
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.3942861893
Short name T776
Test name
Test status
Simulation time 45443677 ps
CPU time 2.94 seconds
Started May 28 02:46:41 PM PDT 24
Finished May 28 02:46:59 PM PDT 24
Peak memory 214060 kb
Host smart-4644acf1-7c3e-48ec-8abf-4c8c4bb6b057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942861893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.3942861893
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.4100094268
Short name T702
Test name
Test status
Simulation time 309666202 ps
CPU time 27.88 seconds
Started May 28 02:46:43 PM PDT 24
Finished May 28 02:47:27 PM PDT 24
Peak memory 250812 kb
Host smart-8afb4bd3-bca5-4810-bd1a-92b51eb77995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100094268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.4100094268
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.285047113
Short name T772
Test name
Test status
Simulation time 225123686 ps
CPU time 8.23 seconds
Started May 28 02:46:44 PM PDT 24
Finished May 28 02:47:08 PM PDT 24
Peak memory 250824 kb
Host smart-661809f6-c681-4bb4-b750-fbb2081cd0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285047113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.285047113
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2913336176
Short name T804
Test name
Test status
Simulation time 3438188149 ps
CPU time 89.52 seconds
Started May 28 02:46:42 PM PDT 24
Finished May 28 02:48:27 PM PDT 24
Peak memory 272472 kb
Host smart-41634c6c-3b9a-4d61-9be5-df13840897ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913336176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2913336176
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.4215642968
Short name T654
Test name
Test status
Simulation time 39623368 ps
CPU time 0.95 seconds
Started May 28 02:46:43 PM PDT 24
Finished May 28 02:47:00 PM PDT 24
Peak memory 212524 kb
Host smart-48980cb4-8747-42d6-bc55-1b464e6a45ed
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215642968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.4215642968
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.782324673
Short name T778
Test name
Test status
Simulation time 35690772 ps
CPU time 0.89 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:48:09 PM PDT 24
Peak memory 209432 kb
Host smart-e219c827-2abd-40da-a34f-a31280592eee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782324673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.782324673
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.959749239
Short name T767
Test name
Test status
Simulation time 3440295258 ps
CPU time 11.04 seconds
Started May 28 02:47:53 PM PDT 24
Finished May 28 02:48:07 PM PDT 24
Peak memory 217988 kb
Host smart-1f689b2d-7193-4925-ab09-925b43c132ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959749239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.959749239
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.1585077252
Short name T222
Test name
Test status
Simulation time 105635959 ps
CPU time 1.26 seconds
Started May 28 02:48:00 PM PDT 24
Finished May 28 02:48:07 PM PDT 24
Peak memory 209428 kb
Host smart-7547af2b-335c-4e4f-bdb9-4c271316d12a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585077252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.1585077252
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.853135890
Short name T278
Test name
Test status
Simulation time 65969801 ps
CPU time 2.86 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:48:10 PM PDT 24
Peak memory 217868 kb
Host smart-aa941ec6-561b-4b43-a57b-8225c81971e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853135890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.853135890
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2656045909
Short name T766
Test name
Test status
Simulation time 455945477 ps
CPU time 20.02 seconds
Started May 28 02:47:56 PM PDT 24
Finished May 28 02:48:19 PM PDT 24
Peak memory 225944 kb
Host smart-9589f181-1331-40ee-8681-f0a45c098b5f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656045909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2656045909
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.104990882
Short name T351
Test name
Test status
Simulation time 1898108100 ps
CPU time 17.7 seconds
Started May 28 02:48:00 PM PDT 24
Finished May 28 02:48:23 PM PDT 24
Peak memory 217844 kb
Host smart-4716713f-ae35-4a98-b422-b079d71b0ab8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104990882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.104990882
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.3967523324
Short name T510
Test name
Test status
Simulation time 664652261 ps
CPU time 19.18 seconds
Started May 28 02:47:57 PM PDT 24
Finished May 28 02:48:19 PM PDT 24
Peak memory 217872 kb
Host smart-ee9f361b-bcc6-452a-bf62-b8bb5e58bb14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967523324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
3967523324
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3341643380
Short name T52
Test name
Test status
Simulation time 1396401745 ps
CPU time 8.9 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:48:17 PM PDT 24
Peak memory 217900 kb
Host smart-1e833fbf-b134-49c9-977c-fe970f8d7af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341643380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3341643380
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2697976083
Short name T25
Test name
Test status
Simulation time 69605201 ps
CPU time 2.97 seconds
Started May 28 02:47:51 PM PDT 24
Finished May 28 02:47:57 PM PDT 24
Peak memory 214520 kb
Host smart-eae71171-9148-4d7d-87c3-4df8e031d0a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697976083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2697976083
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2539794305
Short name T408
Test name
Test status
Simulation time 5019460584 ps
CPU time 28.36 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:48:35 PM PDT 24
Peak memory 250880 kb
Host smart-4b3b0ffe-59b5-4f9e-8f57-870f1cc76cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539794305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2539794305
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2806835681
Short name T167
Test name
Test status
Simulation time 104090809 ps
CPU time 5.54 seconds
Started May 28 02:47:56 PM PDT 24
Finished May 28 02:48:05 PM PDT 24
Peak memory 245956 kb
Host smart-af76908f-d529-44c8-8ce3-19b8f465fd45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806835681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2806835681
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2408142411
Short name T336
Test name
Test status
Simulation time 58573604311 ps
CPU time 175.57 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:51:04 PM PDT 24
Peak memory 271116 kb
Host smart-ecc6990c-ce82-4439-881f-926bd7ded77c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408142411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2408142411
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.892967609
Short name T105
Test name
Test status
Simulation time 6784523534 ps
CPU time 150.46 seconds
Started May 28 02:47:57 PM PDT 24
Finished May 28 02:50:32 PM PDT 24
Peak memory 274660 kb
Host smart-46494e57-b560-43c4-9031-e2a022b40d82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=892967609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.892967609
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2232858712
Short name T610
Test name
Test status
Simulation time 29287010 ps
CPU time 0.93 seconds
Started May 28 02:47:57 PM PDT 24
Finished May 28 02:48:02 PM PDT 24
Peak memory 211560 kb
Host smart-425ab9ad-d128-40d3-8763-ef25d22dae10
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232858712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2232858712
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.4223979642
Short name T630
Test name
Test status
Simulation time 29638826 ps
CPU time 0.97 seconds
Started May 28 02:47:52 PM PDT 24
Finished May 28 02:47:55 PM PDT 24
Peak memory 209436 kb
Host smart-a849b088-0ab6-42f5-accd-32eac52d2422
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223979642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.4223979642
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.1434576594
Short name T43
Test name
Test status
Simulation time 4356143981 ps
CPU time 12.13 seconds
Started May 28 02:47:57 PM PDT 24
Finished May 28 02:48:13 PM PDT 24
Peak memory 218924 kb
Host smart-192ecb87-bf4f-4a09-9b31-45b9a6e8f902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434576594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.1434576594
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1190271602
Short name T635
Test name
Test status
Simulation time 148426153 ps
CPU time 4.45 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:48:11 PM PDT 24
Peak memory 216828 kb
Host smart-fe159be8-d509-4f8f-946a-eba54c6222d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190271602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1190271602
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2761181222
Short name T305
Test name
Test status
Simulation time 120370119 ps
CPU time 1.85 seconds
Started May 28 02:47:57 PM PDT 24
Finished May 28 02:48:02 PM PDT 24
Peak memory 217852 kb
Host smart-3e29d600-dc17-45b1-8a33-c3fd7afdee27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761181222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2761181222
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.1880749647
Short name T247
Test name
Test status
Simulation time 783642752 ps
CPU time 14.6 seconds
Started May 28 02:47:57 PM PDT 24
Finished May 28 02:48:15 PM PDT 24
Peak memory 218812 kb
Host smart-cc847215-c15e-4367-8e9c-37810410b4c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880749647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.1880749647
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1827744963
Short name T303
Test name
Test status
Simulation time 355221144 ps
CPU time 10.01 seconds
Started May 28 02:48:04 PM PDT 24
Finished May 28 02:48:20 PM PDT 24
Peak memory 217704 kb
Host smart-99327c48-e49e-4115-aa60-46ba76e7ca3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827744963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1827744963
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1288194972
Short name T302
Test name
Test status
Simulation time 167085357 ps
CPU time 6.94 seconds
Started May 28 02:47:59 PM PDT 24
Finished May 28 02:48:11 PM PDT 24
Peak memory 217876 kb
Host smart-ebb8e8a5-53ee-45b5-be10-5c39751ab345
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288194972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1288194972
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2632202206
Short name T393
Test name
Test status
Simulation time 183300954 ps
CPU time 6.36 seconds
Started May 28 02:47:57 PM PDT 24
Finished May 28 02:48:07 PM PDT 24
Peak memory 217916 kb
Host smart-c381ca2a-bc99-4a74-9bb0-119b39840e4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632202206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2632202206
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3143990934
Short name T180
Test name
Test status
Simulation time 115423400 ps
CPU time 1 seconds
Started May 28 02:47:57 PM PDT 24
Finished May 28 02:48:01 PM PDT 24
Peak memory 211912 kb
Host smart-c268a45c-e5d7-40c2-a8a5-e01d8f52716f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143990934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3143990934
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.152386935
Short name T609
Test name
Test status
Simulation time 329780831 ps
CPU time 18.4 seconds
Started May 28 02:47:55 PM PDT 24
Finished May 28 02:48:17 PM PDT 24
Peak memory 250848 kb
Host smart-c70d55cd-8be0-4b7f-805b-d102c7c80e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152386935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.152386935
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1606311076
Short name T572
Test name
Test status
Simulation time 717044513 ps
CPU time 8.95 seconds
Started May 28 02:47:58 PM PDT 24
Finished May 28 02:48:11 PM PDT 24
Peak memory 250840 kb
Host smart-5357782b-b2c9-4a08-b8e6-388a82a12f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606311076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1606311076
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.3986251037
Short name T453
Test name
Test status
Simulation time 21181746667 ps
CPU time 401.68 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:54:48 PM PDT 24
Peak memory 283656 kb
Host smart-de7bf5ac-cc16-488d-87bc-10c260f26085
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986251037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.3986251037
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.894226624
Short name T594
Test name
Test status
Simulation time 36696652 ps
CPU time 0.97 seconds
Started May 28 02:47:57 PM PDT 24
Finished May 28 02:48:01 PM PDT 24
Peak memory 211424 kb
Host smart-a0e402e6-ec9d-4efe-8b35-77078231b152
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894226624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.894226624
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.660216471
Short name T361
Test name
Test status
Simulation time 19726913 ps
CPU time 0.94 seconds
Started May 28 02:47:58 PM PDT 24
Finished May 28 02:48:02 PM PDT 24
Peak memory 209428 kb
Host smart-20ea8f95-e012-424e-b315-367fd2c8edd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660216471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.660216471
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2113349680
Short name T176
Test name
Test status
Simulation time 436721275 ps
CPU time 21.5 seconds
Started May 28 02:47:51 PM PDT 24
Finished May 28 02:48:15 PM PDT 24
Peak memory 217908 kb
Host smart-4653399c-6be5-4f9a-974c-71b9e99fc05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113349680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2113349680
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.2727096135
Short name T35
Test name
Test status
Simulation time 345354960 ps
CPU time 9.92 seconds
Started May 28 02:47:54 PM PDT 24
Finished May 28 02:48:08 PM PDT 24
Peak memory 209444 kb
Host smart-19e2cdd7-e6f4-48d3-bd89-72e710842e52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727096135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.2727096135
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2947830485
Short name T663
Test name
Test status
Simulation time 143086194 ps
CPU time 3.14 seconds
Started May 28 02:47:51 PM PDT 24
Finished May 28 02:47:56 PM PDT 24
Peak memory 217824 kb
Host smart-0345b7c4-fdf7-407e-9bf7-483bb543f69c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947830485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2947830485
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.3969189597
Short name T301
Test name
Test status
Simulation time 529085159 ps
CPU time 17.61 seconds
Started May 28 02:47:52 PM PDT 24
Finished May 28 02:48:12 PM PDT 24
Peak memory 225504 kb
Host smart-3f0931d1-c5d3-4d80-9bf4-ae71d97c97cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969189597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.3969189597
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3936618023
Short name T395
Test name
Test status
Simulation time 1160897731 ps
CPU time 11.27 seconds
Started May 28 02:47:54 PM PDT 24
Finished May 28 02:48:09 PM PDT 24
Peak memory 217816 kb
Host smart-e98e6694-70a4-4bda-8d32-0b4a0e33f9a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936618023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3936618023
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.865415513
Short name T368
Test name
Test status
Simulation time 351081826 ps
CPU time 7.42 seconds
Started May 28 02:47:53 PM PDT 24
Finished May 28 02:48:04 PM PDT 24
Peak memory 217904 kb
Host smart-a31ecb4f-1258-43f7-bd38-196b5df3cd63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865415513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.865415513
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3240947132
Short name T162
Test name
Test status
Simulation time 262455374 ps
CPU time 7.73 seconds
Started May 28 02:48:07 PM PDT 24
Finished May 28 02:48:20 PM PDT 24
Peak memory 217916 kb
Host smart-5a4f32a2-0804-4b26-b210-59cb09cdcdbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240947132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3240947132
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2847466410
Short name T11
Test name
Test status
Simulation time 76830445 ps
CPU time 1.35 seconds
Started May 28 02:47:51 PM PDT 24
Finished May 28 02:47:55 PM PDT 24
Peak memory 212800 kb
Host smart-df2dcf44-5dcd-4a82-8ae2-cff1a0d9795c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847466410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2847466410
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.2418088624
Short name T274
Test name
Test status
Simulation time 156469575 ps
CPU time 21.89 seconds
Started May 28 02:47:52 PM PDT 24
Finished May 28 02:48:17 PM PDT 24
Peak memory 250824 kb
Host smart-fa0d5037-2307-4756-83ad-42bc857e64fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418088624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2418088624
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2169373638
Short name T86
Test name
Test status
Simulation time 63372651 ps
CPU time 2.96 seconds
Started May 28 02:47:57 PM PDT 24
Finished May 28 02:48:04 PM PDT 24
Peak memory 226260 kb
Host smart-9e7239b1-b108-470e-98eb-4a8584edc574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169373638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2169373638
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3317590748
Short name T592
Test name
Test status
Simulation time 1380412088 ps
CPU time 34.35 seconds
Started May 28 02:47:57 PM PDT 24
Finished May 28 02:48:35 PM PDT 24
Peak memory 250824 kb
Host smart-5da1f826-d51d-4f02-8729-854c8ab60e0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317590748 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3317590748
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.3159889503
Short name T141
Test name
Test status
Simulation time 109764726273 ps
CPU time 1133.08 seconds
Started May 28 02:47:52 PM PDT 24
Finished May 28 03:06:48 PM PDT 24
Peak memory 496712 kb
Host smart-11d4a9ca-bc60-4f85-a5d1-bd4e9d7083f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3159889503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.3159889503
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.958831635
Short name T781
Test name
Test status
Simulation time 13969710 ps
CPU time 1.01 seconds
Started May 28 02:47:55 PM PDT 24
Finished May 28 02:48:00 PM PDT 24
Peak memory 211436 kb
Host smart-4c9d0358-2fae-4f44-baf3-58cf6825680b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958831635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.958831635
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1799673184
Short name T604
Test name
Test status
Simulation time 27562625 ps
CPU time 0.88 seconds
Started May 28 02:47:57 PM PDT 24
Finished May 28 02:48:01 PM PDT 24
Peak memory 209428 kb
Host smart-0f0169fd-c777-469f-b896-9dac291d4357
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799673184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1799673184
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3178576646
Short name T416
Test name
Test status
Simulation time 360891593 ps
CPU time 14.9 seconds
Started May 28 02:47:56 PM PDT 24
Finished May 28 02:48:14 PM PDT 24
Peak memory 217916 kb
Host smart-1b52c0e9-bb0d-41f3-b65a-ab69478edab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178576646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3178576646
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3576660831
Short name T806
Test name
Test status
Simulation time 1527163335 ps
CPU time 5.42 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:48:12 PM PDT 24
Peak memory 209464 kb
Host smart-07e34352-a9c6-4335-ac5e-4fa9015e9ea3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576660831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3576660831
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3721876956
Short name T678
Test name
Test status
Simulation time 44462884 ps
CPU time 1.83 seconds
Started May 28 02:47:56 PM PDT 24
Finished May 28 02:48:01 PM PDT 24
Peak memory 217824 kb
Host smart-a6191787-ada2-44bb-8250-ea0e3cfed46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721876956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3721876956
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.4252877923
Short name T475
Test name
Test status
Simulation time 6389736491 ps
CPU time 16.94 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:48:24 PM PDT 24
Peak memory 226068 kb
Host smart-2892dcea-668e-41b4-944b-528703edd6e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252877923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.4252877923
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.917463065
Short name T749
Test name
Test status
Simulation time 1276837861 ps
CPU time 12.91 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:48:19 PM PDT 24
Peak memory 217760 kb
Host smart-7d0a9f0e-cf7e-4b23-949b-e24b42f7c4b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917463065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.917463065
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.735901661
Short name T312
Test name
Test status
Simulation time 1102610943 ps
CPU time 8.6 seconds
Started May 28 02:47:54 PM PDT 24
Finished May 28 02:48:06 PM PDT 24
Peak memory 217856 kb
Host smart-8c2e0fe0-d7a8-4dd2-bfea-850e9c584d40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735901661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.735901661
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2939284932
Short name T331
Test name
Test status
Simulation time 392304416 ps
CPU time 7.93 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:48:15 PM PDT 24
Peak memory 217940 kb
Host smart-c0c454aa-6d1d-403d-a681-fbc815b286b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939284932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2939284932
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.2616019633
Short name T262
Test name
Test status
Simulation time 36306872 ps
CPU time 1.99 seconds
Started May 28 02:47:54 PM PDT 24
Finished May 28 02:47:59 PM PDT 24
Peak memory 213676 kb
Host smart-07e7da01-652d-4152-b64a-dbb256532287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2616019633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.2616019633
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.413761931
Short name T734
Test name
Test status
Simulation time 223975083 ps
CPU time 27.37 seconds
Started May 28 02:47:53 PM PDT 24
Finished May 28 02:48:24 PM PDT 24
Peak memory 250932 kb
Host smart-5e578599-1933-4ae3-996c-b297786c9100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413761931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.413761931
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3716148385
Short name T506
Test name
Test status
Simulation time 44651744 ps
CPU time 8.74 seconds
Started May 28 02:47:58 PM PDT 24
Finished May 28 02:48:11 PM PDT 24
Peak memory 250632 kb
Host smart-cbfc7c35-3976-4083-b69d-22fb5424ad2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716148385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3716148385
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.1995266271
Short name T466
Test name
Test status
Simulation time 1669360695 ps
CPU time 28.82 seconds
Started May 28 02:47:54 PM PDT 24
Finished May 28 02:48:26 PM PDT 24
Peak memory 250816 kb
Host smart-8ded7dd8-554b-44a3-8506-0dc0b4536ae5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995266271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.1995266271
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1936093306
Short name T527
Test name
Test status
Simulation time 13049629 ps
CPU time 0.78 seconds
Started May 28 02:47:56 PM PDT 24
Finished May 28 02:48:00 PM PDT 24
Peak memory 207708 kb
Host smart-14365fd4-c1a4-4a6e-a73f-4c3ac5ae1117
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936093306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1936093306
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.1930800200
Short name T722
Test name
Test status
Simulation time 24820788 ps
CPU time 1.26 seconds
Started May 28 02:48:04 PM PDT 24
Finished May 28 02:48:12 PM PDT 24
Peak memory 209296 kb
Host smart-55b9588a-7e1f-4af9-a352-6de571bbd993
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930800200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.1930800200
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2385409212
Short name T794
Test name
Test status
Simulation time 1972296191 ps
CPU time 8.91 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:48:17 PM PDT 24
Peak memory 217876 kb
Host smart-50ab0669-6d40-4e29-9636-442b2bf01386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385409212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2385409212
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.4239234377
Short name T696
Test name
Test status
Simulation time 370202338 ps
CPU time 1.83 seconds
Started May 28 02:47:58 PM PDT 24
Finished May 28 02:48:03 PM PDT 24
Peak memory 216704 kb
Host smart-d1c9634b-53bd-4262-9fa3-bf8ca6d0bc3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239234377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.4239234377
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.3496110956
Short name T154
Test name
Test status
Simulation time 154330061 ps
CPU time 2.6 seconds
Started May 28 02:47:51 PM PDT 24
Finished May 28 02:47:56 PM PDT 24
Peak memory 217832 kb
Host smart-5f8768b3-76d8-4525-b73d-36fa2944861d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496110956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.3496110956
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.744869140
Short name T470
Test name
Test status
Simulation time 525591562 ps
CPU time 10.91 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:48:19 PM PDT 24
Peak memory 217872 kb
Host smart-0c8804cf-b222-4e91-bea1-9f6962db4fb0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744869140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.744869140
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.4231594878
Short name T643
Test name
Test status
Simulation time 3360283019 ps
CPU time 16.61 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:48:24 PM PDT 24
Peak memory 226080 kb
Host smart-84422ee7-2992-476b-aafd-e8f31415d0dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231594878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.4231594878
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.1670121592
Short name T866
Test name
Test status
Simulation time 598741873 ps
CPU time 7.61 seconds
Started May 28 02:47:58 PM PDT 24
Finished May 28 02:48:10 PM PDT 24
Peak memory 217872 kb
Host smart-d5a173cc-0860-4443-9247-44adb4fa4b0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670121592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
1670121592
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.628120556
Short name T850
Test name
Test status
Simulation time 41694810 ps
CPU time 3.16 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:48:10 PM PDT 24
Peak memory 214332 kb
Host smart-f9f5f1cc-d995-4f3f-b98a-b88eeef6ab8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628120556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.628120556
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.135628139
Short name T360
Test name
Test status
Simulation time 219457951 ps
CPU time 16.61 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:48:25 PM PDT 24
Peak memory 250900 kb
Host smart-bb63f54a-a066-4ae3-9a7a-ab7f3eef07a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135628139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.135628139
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.2497337182
Short name T650
Test name
Test status
Simulation time 282891440 ps
CPU time 7.4 seconds
Started May 28 02:47:57 PM PDT 24
Finished May 28 02:48:09 PM PDT 24
Peak memory 250336 kb
Host smart-7976ffff-cda7-47a2-9fd6-cd0e2c572f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497337182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.2497337182
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.1635583417
Short name T787
Test name
Test status
Simulation time 4051463720 ps
CPU time 95.41 seconds
Started May 28 02:47:58 PM PDT 24
Finished May 28 02:49:37 PM PDT 24
Peak memory 226064 kb
Host smart-608d1c04-8747-4035-9f2b-467e605844e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635583417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.1635583417
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2557367014
Short name T638
Test name
Test status
Simulation time 18103368 ps
CPU time 0.91 seconds
Started May 28 02:47:57 PM PDT 24
Finished May 28 02:48:01 PM PDT 24
Peak memory 211544 kb
Host smart-d6dde34e-652c-4f4c-9ec8-e6e50d032978
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557367014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2557367014
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.4053960406
Short name T518
Test name
Test status
Simulation time 73856162 ps
CPU time 1.19 seconds
Started May 28 02:48:03 PM PDT 24
Finished May 28 02:48:10 PM PDT 24
Peak memory 209448 kb
Host smart-0c28fef8-7162-41ba-a95a-7aa0e7525ff4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053960406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.4053960406
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.333264912
Short name T241
Test name
Test status
Simulation time 809167985 ps
CPU time 8.25 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:48:15 PM PDT 24
Peak memory 217804 kb
Host smart-b5f987c3-9f2f-40be-8999-9a0fd736ee2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333264912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.333264912
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1437760954
Short name T300
Test name
Test status
Simulation time 298102275 ps
CPU time 8.23 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:48:15 PM PDT 24
Peak memory 217032 kb
Host smart-c75fb0ea-9849-4575-b8c6-8055072b095f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437760954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1437760954
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1286521897
Short name T371
Test name
Test status
Simulation time 174240997 ps
CPU time 2.64 seconds
Started May 28 02:48:05 PM PDT 24
Finished May 28 02:48:13 PM PDT 24
Peak memory 217916 kb
Host smart-212178f7-13e7-4fce-a34e-dfc4420c84ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286521897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1286521897
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.271090549
Short name T308
Test name
Test status
Simulation time 330795854 ps
CPU time 9.3 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:48:17 PM PDT 24
Peak memory 217920 kb
Host smart-a9274d59-e726-4454-aa3d-ddffd3e1be49
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271090549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.271090549
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.201927272
Short name T537
Test name
Test status
Simulation time 327655917 ps
CPU time 7.89 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:48:16 PM PDT 24
Peak memory 217856 kb
Host smart-b26756bc-4db8-4061-9705-7704c514e39f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201927272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_di
gest.201927272
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.2962917334
Short name T679
Test name
Test status
Simulation time 1742369899 ps
CPU time 7.38 seconds
Started May 28 02:48:08 PM PDT 24
Finished May 28 02:48:20 PM PDT 24
Peak memory 217836 kb
Host smart-84669174-a790-4073-811f-d5c9d70879c4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962917334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
2962917334
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.3697126307
Short name T869
Test name
Test status
Simulation time 646396492 ps
CPU time 9.64 seconds
Started May 28 02:48:03 PM PDT 24
Finished May 28 02:48:19 PM PDT 24
Peak memory 217920 kb
Host smart-252a6f8f-3eb1-4b20-8213-b52aaa0f5184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697126307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.3697126307
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1490868653
Short name T76
Test name
Test status
Simulation time 92464373 ps
CPU time 3.43 seconds
Started May 28 02:48:05 PM PDT 24
Finished May 28 02:48:14 PM PDT 24
Peak memory 214220 kb
Host smart-f5dcb7ff-8f9d-44d6-be8b-e20e2a4d569c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490868653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1490868653
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3036293811
Short name T48
Test name
Test status
Simulation time 1036056173 ps
CPU time 22.71 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:48:29 PM PDT 24
Peak memory 250840 kb
Host smart-18469bb3-0d50-4e3d-90c5-be8e94634996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036293811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3036293811
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.159841121
Short name T824
Test name
Test status
Simulation time 62511589 ps
CPU time 3.39 seconds
Started May 28 02:47:59 PM PDT 24
Finished May 28 02:48:08 PM PDT 24
Peak memory 217852 kb
Host smart-1a1f1926-bebc-4b4e-9c47-325b59b63e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159841121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.159841121
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.3078756571
Short name T91
Test name
Test status
Simulation time 6019539822 ps
CPU time 117.08 seconds
Started May 28 02:48:04 PM PDT 24
Finished May 28 02:50:07 PM PDT 24
Peak memory 283640 kb
Host smart-e680fcb6-e14d-46a1-80c8-35894be83426
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078756571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.3078756571
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2253396339
Short name T617
Test name
Test status
Simulation time 18729794 ps
CPU time 1.3 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:48:08 PM PDT 24
Peak memory 212808 kb
Host smart-914145d7-23d4-49ce-ab38-8c2cd0a39f04
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253396339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2253396339
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.3622624172
Short name T534
Test name
Test status
Simulation time 30748830 ps
CPU time 0.99 seconds
Started May 28 02:48:00 PM PDT 24
Finished May 28 02:48:07 PM PDT 24
Peak memory 209420 kb
Host smart-3a81acd5-fdd0-412d-b0ad-07c4196f160d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622624172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.3622624172
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.1439514188
Short name T730
Test name
Test status
Simulation time 229487424 ps
CPU time 9.42 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:48:17 PM PDT 24
Peak memory 217888 kb
Host smart-b683f459-cf22-4172-832a-be88eadaf482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439514188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.1439514188
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1055392061
Short name T34
Test name
Test status
Simulation time 4842305907 ps
CPU time 7.21 seconds
Started May 28 02:48:03 PM PDT 24
Finished May 28 02:48:16 PM PDT 24
Peak memory 217516 kb
Host smart-3c6cb9ad-861b-4efa-a30f-1dfe8710bc2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055392061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1055392061
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1887069773
Short name T293
Test name
Test status
Simulation time 355607786 ps
CPU time 3.27 seconds
Started May 28 02:48:04 PM PDT 24
Finished May 28 02:48:13 PM PDT 24
Peak memory 217904 kb
Host smart-b6c46cc2-dac4-453a-8f03-8c3abb23a52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887069773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1887069773
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.4227163991
Short name T146
Test name
Test status
Simulation time 4367914904 ps
CPU time 10.85 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:48:19 PM PDT 24
Peak memory 226092 kb
Host smart-7ceacc8c-c7e5-4d9e-9a2d-82205733ebcd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227163991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.4227163991
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.1592387270
Short name T284
Test name
Test status
Simulation time 12589934971 ps
CPU time 23.1 seconds
Started May 28 02:48:00 PM PDT 24
Finished May 28 02:48:29 PM PDT 24
Peak memory 226076 kb
Host smart-257dfd69-c22d-4397-a8c2-b690dc92871e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592387270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.1592387270
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1793400909
Short name T531
Test name
Test status
Simulation time 1544661156 ps
CPU time 14.22 seconds
Started May 28 02:48:03 PM PDT 24
Finished May 28 02:48:23 PM PDT 24
Peak memory 217876 kb
Host smart-24999274-6bfb-4c4c-bece-574f341b84aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793400909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1793400909
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1750438148
Short name T660
Test name
Test status
Simulation time 1140670918 ps
CPU time 7.68 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:48:16 PM PDT 24
Peak memory 217976 kb
Host smart-a4e85b41-4b20-4c8b-9678-c2d3fc691e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750438148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1750438148
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.2377403413
Short name T397
Test name
Test status
Simulation time 30971224 ps
CPU time 1.01 seconds
Started May 28 02:48:03 PM PDT 24
Finished May 28 02:48:10 PM PDT 24
Peak memory 211640 kb
Host smart-339c021f-014b-4002-9e29-f887ce63c6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377403413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.2377403413
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.4131426490
Short name T574
Test name
Test status
Simulation time 562308922 ps
CPU time 32.08 seconds
Started May 28 02:48:00 PM PDT 24
Finished May 28 02:48:37 PM PDT 24
Peak memory 250880 kb
Host smart-10f3640a-94d4-40d0-a5a4-e65b9d4dcf90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131426490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.4131426490
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.3132799506
Short name T763
Test name
Test status
Simulation time 173879032 ps
CPU time 6.69 seconds
Started May 28 02:48:17 PM PDT 24
Finished May 28 02:48:30 PM PDT 24
Peak memory 250316 kb
Host smart-bb1e64f4-d817-4978-8191-6ed7add0ef72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132799506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.3132799506
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.3675828175
Short name T828
Test name
Test status
Simulation time 52661297861 ps
CPU time 197.75 seconds
Started May 28 02:48:08 PM PDT 24
Finished May 28 02:51:31 PM PDT 24
Peak memory 283600 kb
Host smart-dbb48975-de8f-46e2-a2ef-141e87b51750
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675828175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.3675828175
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.131621056
Short name T669
Test name
Test status
Simulation time 53965981 ps
CPU time 0.97 seconds
Started May 28 02:48:04 PM PDT 24
Finished May 28 02:48:11 PM PDT 24
Peak memory 212568 kb
Host smart-dcae73bb-cb42-42da-848b-8b5f7c3d778f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131621056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.131621056
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2982129497
Short name T239
Test name
Test status
Simulation time 32003541 ps
CPU time 1.02 seconds
Started May 28 02:48:07 PM PDT 24
Finished May 28 02:48:14 PM PDT 24
Peak memory 209480 kb
Host smart-27070cfe-3260-4320-b3b4-ec7338aec990
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982129497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2982129497
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.275284088
Short name T708
Test name
Test status
Simulation time 350911923 ps
CPU time 14.64 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:48:23 PM PDT 24
Peak memory 217108 kb
Host smart-2c7fe148-d324-4750-ba14-b275dc8a3d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275284088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.275284088
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.372313552
Short name T492
Test name
Test status
Simulation time 6538075822 ps
CPU time 5.45 seconds
Started May 28 02:48:03 PM PDT 24
Finished May 28 02:48:14 PM PDT 24
Peak memory 209588 kb
Host smart-e2fcb206-7eca-4abb-a0e0-7b4eeffb0056
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372313552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.372313552
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1218548324
Short name T26
Test name
Test status
Simulation time 73372352 ps
CPU time 3.9 seconds
Started May 28 02:48:03 PM PDT 24
Finished May 28 02:48:13 PM PDT 24
Peak memory 217828 kb
Host smart-88c17a2a-61f8-495c-8623-e67dc44ba147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218548324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1218548324
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.2703679663
Short name T62
Test name
Test status
Simulation time 2131180642 ps
CPU time 14.01 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:48:22 PM PDT 24
Peak memory 218788 kb
Host smart-ac2cc695-eff9-4b81-854b-8695c6ff9ee2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703679663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.2703679663
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.748137050
Short name T446
Test name
Test status
Simulation time 468808496 ps
CPU time 12.14 seconds
Started May 28 02:48:03 PM PDT 24
Finished May 28 02:48:22 PM PDT 24
Peak memory 217836 kb
Host smart-84c1d33b-2bec-4a5b-af70-19ae8a52caf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748137050 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di
gest.748137050
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.116493177
Short name T252
Test name
Test status
Simulation time 899302747 ps
CPU time 7.22 seconds
Started May 28 02:48:07 PM PDT 24
Finished May 28 02:48:20 PM PDT 24
Peak memory 217912 kb
Host smart-810cf219-f992-4056-8a76-dbcf3bbbbf23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116493177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.116493177
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.3050291416
Short name T559
Test name
Test status
Simulation time 2184047352 ps
CPU time 12 seconds
Started May 28 02:47:59 PM PDT 24
Finished May 28 02:48:15 PM PDT 24
Peak memory 217984 kb
Host smart-866a222d-cff8-49ef-a5b2-e755f365c7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050291416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.3050291416
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1546508532
Short name T59
Test name
Test status
Simulation time 48842116 ps
CPU time 3.2 seconds
Started May 28 02:48:03 PM PDT 24
Finished May 28 02:48:12 PM PDT 24
Peak memory 214536 kb
Host smart-0194c9d9-d86d-4fb5-8944-df003549ad22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546508532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1546508532
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2875305473
Short name T710
Test name
Test status
Simulation time 466605561 ps
CPU time 34.97 seconds
Started May 28 02:48:06 PM PDT 24
Finished May 28 02:48:47 PM PDT 24
Peak memory 250788 kb
Host smart-de98ac24-9fe6-4f21-8de1-e99dc716746f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875305473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2875305473
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.1283807700
Short name T728
Test name
Test status
Simulation time 347516644 ps
CPU time 7.91 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:48:16 PM PDT 24
Peak memory 250804 kb
Host smart-33b7c911-a750-4f1b-9b3f-b20d70c2a250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283807700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.1283807700
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.477563672
Short name T71
Test name
Test status
Simulation time 1849299013 ps
CPU time 32.01 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:48:41 PM PDT 24
Peak memory 226132 kb
Host smart-e9cc773a-aa53-4d42-bad8-ce97f96dcb39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477563672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.477563672
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.4242005012
Short name T515
Test name
Test status
Simulation time 75717005 ps
CPU time 0.89 seconds
Started May 28 02:48:06 PM PDT 24
Finished May 28 02:48:13 PM PDT 24
Peak memory 211468 kb
Host smart-56a800b5-e142-49ef-90ba-e07df06c1c79
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242005012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.4242005012
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1456334204
Short name T720
Test name
Test status
Simulation time 63883394 ps
CPU time 0.9 seconds
Started May 28 02:48:03 PM PDT 24
Finished May 28 02:48:11 PM PDT 24
Peak memory 209404 kb
Host smart-91ad8faf-886b-4f71-9652-c16ef6137f96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456334204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1456334204
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.4173596093
Short name T350
Test name
Test status
Simulation time 1312975006 ps
CPU time 11.85 seconds
Started May 28 02:48:10 PM PDT 24
Finished May 28 02:48:26 PM PDT 24
Peak memory 217980 kb
Host smart-15cccc68-7102-4d64-bb0a-7103221a2775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173596093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.4173596093
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.1912162291
Short name T576
Test name
Test status
Simulation time 2386016559 ps
CPU time 21.4 seconds
Started May 28 02:48:04 PM PDT 24
Finished May 28 02:48:32 PM PDT 24
Peak memory 209624 kb
Host smart-3db4e6ef-ac48-45be-9a15-ff9e12a1702e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912162291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.1912162291
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.4000926341
Short name T646
Test name
Test status
Simulation time 54947843 ps
CPU time 1.63 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:48:10 PM PDT 24
Peak memory 217832 kb
Host smart-fe6cc658-1b29-44f3-8093-5ac8add2c523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000926341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.4000926341
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3382244901
Short name T860
Test name
Test status
Simulation time 1621976802 ps
CPU time 14.33 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:48:22 PM PDT 24
Peak memory 218792 kb
Host smart-01af9494-e634-4461-96ce-025bb9c91075
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382244901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3382244901
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3707710268
Short name T591
Test name
Test status
Simulation time 369764903 ps
CPU time 14.95 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:48:23 PM PDT 24
Peak memory 225956 kb
Host smart-767b687b-4364-4a41-960f-4cc00a1fc499
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707710268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3707710268
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1471017850
Short name T310
Test name
Test status
Simulation time 1679609548 ps
CPU time 9.63 seconds
Started May 28 02:48:09 PM PDT 24
Finished May 28 02:48:24 PM PDT 24
Peak memory 217912 kb
Host smart-0efe731e-0fa9-4ef4-9810-429d4e577e82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471017850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1471017850
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.3581778699
Short name T216
Test name
Test status
Simulation time 269604199 ps
CPU time 12.79 seconds
Started May 28 02:48:09 PM PDT 24
Finished May 28 02:48:27 PM PDT 24
Peak memory 225400 kb
Host smart-f5173aa0-ed56-43de-8d64-178a1b728797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581778699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.3581778699
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3332225509
Short name T795
Test name
Test status
Simulation time 137187312 ps
CPU time 2.13 seconds
Started May 28 02:48:01 PM PDT 24
Finished May 28 02:48:08 PM PDT 24
Peak memory 213676 kb
Host smart-713b0822-de6c-4af6-b8d8-17c93ebe1a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332225509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3332225509
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3632137018
Short name T783
Test name
Test status
Simulation time 249165492 ps
CPU time 32.85 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:48:41 PM PDT 24
Peak memory 250880 kb
Host smart-8d28d6a2-72cd-405c-98d7-38a2598fba1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632137018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3632137018
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3676228359
Short name T705
Test name
Test status
Simulation time 55137971 ps
CPU time 7.2 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:48:15 PM PDT 24
Peak memory 250840 kb
Host smart-b4c29f75-ff63-4cea-bf9b-b4ecd8ea9e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676228359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3676228359
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.1474828182
Short name T521
Test name
Test status
Simulation time 59601660531 ps
CPU time 159.93 seconds
Started May 28 02:48:08 PM PDT 24
Finished May 28 02:50:53 PM PDT 24
Peak memory 226056 kb
Host smart-b45b39ed-e946-41f2-8129-bff383d8157f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474828182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.1474828182
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.2031774937
Short name T100
Test name
Test status
Simulation time 40876129916 ps
CPU time 2018.75 seconds
Started May 28 02:48:09 PM PDT 24
Finished May 28 03:21:53 PM PDT 24
Peak memory 578684 kb
Host smart-6bb59e52-c69e-4d7c-9da3-c7e785d84ffc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2031774937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.2031774937
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.2465970421
Short name T676
Test name
Test status
Simulation time 26478808 ps
CPU time 0.92 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:48:09 PM PDT 24
Peak memory 211880 kb
Host smart-11f3f7e2-a6cf-490e-83c1-1a5c134d39d3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465970421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.2465970421
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.228614190
Short name T876
Test name
Test status
Simulation time 16684981 ps
CPU time 0.92 seconds
Started May 28 02:48:04 PM PDT 24
Finished May 28 02:48:11 PM PDT 24
Peak memory 209320 kb
Host smart-85c3992d-dbe6-41d6-8793-d6d207f956fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228614190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.228614190
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.1722788941
Short name T386
Test name
Test status
Simulation time 2352746420 ps
CPU time 13.38 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:48:21 PM PDT 24
Peak memory 218048 kb
Host smart-b5ff014e-06c7-4100-ba44-6db09f052f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722788941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.1722788941
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1617188224
Short name T348
Test name
Test status
Simulation time 190342460 ps
CPU time 1.8 seconds
Started May 28 02:48:06 PM PDT 24
Finished May 28 02:48:14 PM PDT 24
Peak memory 209608 kb
Host smart-74131809-aa08-409a-bce3-40727313c950
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617188224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1617188224
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.2353771200
Short name T512
Test name
Test status
Simulation time 107474182 ps
CPU time 2.8 seconds
Started May 28 02:48:05 PM PDT 24
Finished May 28 02:48:14 PM PDT 24
Peak memory 217836 kb
Host smart-40bb2357-9a91-4099-b169-de09d5a7fbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353771200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.2353771200
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2881883367
Short name T585
Test name
Test status
Simulation time 413671169 ps
CPU time 10.29 seconds
Started May 28 02:48:04 PM PDT 24
Finished May 28 02:48:20 PM PDT 24
Peak memory 225592 kb
Host smart-3c95dfc8-0497-424d-8556-75ae0eff736e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881883367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2881883367
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1791196159
Short name T160
Test name
Test status
Simulation time 499378510 ps
CPU time 10.25 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:48:18 PM PDT 24
Peak memory 217872 kb
Host smart-2ce021d1-2000-4d47-a05e-901f439cea9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791196159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1791196159
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3424827538
Short name T731
Test name
Test status
Simulation time 384000496 ps
CPU time 13.48 seconds
Started May 28 02:48:05 PM PDT 24
Finished May 28 02:48:24 PM PDT 24
Peak memory 217712 kb
Host smart-bd4d24a1-6008-40f2-9021-c78a8fbc00c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424827538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3424827538
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.4173705310
Short name T498
Test name
Test status
Simulation time 1859052499 ps
CPU time 10.65 seconds
Started May 28 02:48:05 PM PDT 24
Finished May 28 02:48:22 PM PDT 24
Peak memory 217988 kb
Host smart-0bd4461c-afa9-4bd0-a9a0-13c43eb31699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173705310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.4173705310
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2863238889
Short name T99
Test name
Test status
Simulation time 179310669 ps
CPU time 18.96 seconds
Started May 28 02:48:04 PM PDT 24
Finished May 28 02:48:29 PM PDT 24
Peak memory 250848 kb
Host smart-0a69ebc0-3724-463d-91db-5e8fdc81286f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863238889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2863238889
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.182165029
Short name T517
Test name
Test status
Simulation time 67109870 ps
CPU time 3.62 seconds
Started May 28 02:48:04 PM PDT 24
Finished May 28 02:48:14 PM PDT 24
Peak memory 217920 kb
Host smart-03a0a08e-46c4-4d89-aab4-ae4f632b8e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182165029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.182165029
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2435227141
Short name T664
Test name
Test status
Simulation time 38260063721 ps
CPU time 195.14 seconds
Started May 28 02:48:08 PM PDT 24
Finished May 28 02:51:28 PM PDT 24
Peak memory 254404 kb
Host smart-00312ee7-93b8-4340-9249-d30fd2c4894c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435227141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2435227141
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1638742030
Short name T737
Test name
Test status
Simulation time 32386146 ps
CPU time 0.98 seconds
Started May 28 02:48:02 PM PDT 24
Finished May 28 02:48:09 PM PDT 24
Peak memory 211500 kb
Host smart-74f71456-bdb1-4b0b-8b43-d01b39131f86
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638742030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1638742030
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.568329108
Short name T520
Test name
Test status
Simulation time 26585879 ps
CPU time 0.98 seconds
Started May 28 02:46:44 PM PDT 24
Finished May 28 02:47:01 PM PDT 24
Peak memory 209432 kb
Host smart-636da804-47e6-406a-be69-c8a8dbccba1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568329108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.568329108
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3255694242
Short name T213
Test name
Test status
Simulation time 12229532 ps
CPU time 0.92 seconds
Started May 28 02:46:44 PM PDT 24
Finished May 28 02:47:01 PM PDT 24
Peak memory 209440 kb
Host smart-23667b59-cf71-4b75-a3b2-77d499fa2e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255694242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3255694242
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.800519814
Short name T584
Test name
Test status
Simulation time 669732051 ps
CPU time 14.83 seconds
Started May 28 02:46:43 PM PDT 24
Finished May 28 02:47:13 PM PDT 24
Peak memory 217856 kb
Host smart-adfb838b-2213-4a64-ae17-ccb83ebf7066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800519814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.800519814
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3503552308
Short name T7
Test name
Test status
Simulation time 2620343581 ps
CPU time 7.67 seconds
Started May 28 02:46:49 PM PDT 24
Finished May 28 02:47:11 PM PDT 24
Peak memory 209536 kb
Host smart-292eadd7-a3e6-449b-a1ce-1b214c343f10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503552308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3503552308
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.3871308692
Short name T16
Test name
Test status
Simulation time 13440011135 ps
CPU time 52.29 seconds
Started May 28 02:46:44 PM PDT 24
Finished May 28 02:47:53 PM PDT 24
Peak memory 217896 kb
Host smart-402be24c-7b9c-4981-8807-d4ae914775de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871308692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.3871308692
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.713639410
Short name T362
Test name
Test status
Simulation time 129746694 ps
CPU time 1.71 seconds
Started May 28 02:46:43 PM PDT 24
Finished May 28 02:47:01 PM PDT 24
Peak memory 216964 kb
Host smart-70050049-8246-4a85-a3c6-4291d8ca466c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713639410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.713639410
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.4294146170
Short name T406
Test name
Test status
Simulation time 268616620 ps
CPU time 1.87 seconds
Started May 28 02:46:42 PM PDT 24
Finished May 28 02:46:59 PM PDT 24
Peak memory 217792 kb
Host smart-5ea59629-2826-4910-aa3d-c28e69b2e926
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294146170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.4294146170
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.2497920892
Short name T68
Test name
Test status
Simulation time 1094792430 ps
CPU time 8.51 seconds
Started May 28 02:46:43 PM PDT 24
Finished May 28 02:47:08 PM PDT 24
Peak memory 212824 kb
Host smart-fc96c288-3554-47cb-903c-780490c28518
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497920892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.2497920892
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1848701997
Short name T724
Test name
Test status
Simulation time 338976342 ps
CPU time 4.77 seconds
Started May 28 02:46:42 PM PDT 24
Finished May 28 02:47:02 PM PDT 24
Peak memory 213000 kb
Host smart-35de49e4-32b4-499b-ac3d-5cf203b84961
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848701997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1848701997
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.2792328170
Short name T717
Test name
Test status
Simulation time 5150188401 ps
CPU time 42.22 seconds
Started May 28 02:46:41 PM PDT 24
Finished May 28 02:47:39 PM PDT 24
Peak memory 275580 kb
Host smart-dbf696c3-28f3-407d-9a38-4c741a39bb5e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792328170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.2792328170
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1643577521
Short name T718
Test name
Test status
Simulation time 369454229 ps
CPU time 13.34 seconds
Started May 28 02:46:40 PM PDT 24
Finished May 28 02:47:09 PM PDT 24
Peak memory 250380 kb
Host smart-216b7ff1-4114-454d-bb10-b1a3636deea0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643577521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.1643577521
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.3595303614
Short name T345
Test name
Test status
Simulation time 63842413 ps
CPU time 3.41 seconds
Started May 28 02:46:43 PM PDT 24
Finished May 28 02:47:03 PM PDT 24
Peak memory 217824 kb
Host smart-a49e8939-e2eb-4e2e-918f-787dcd85dab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595303614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.3595303614
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.746823450
Short name T69
Test name
Test status
Simulation time 249178895 ps
CPU time 6.24 seconds
Started May 28 02:46:42 PM PDT 24
Finished May 28 02:47:04 PM PDT 24
Peak memory 214212 kb
Host smart-58dcaebb-4dd4-40d1-ab49-1b1feb6e0162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746823450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.746823450
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2886924803
Short name T37
Test name
Test status
Simulation time 2634187331 ps
CPU time 13.67 seconds
Started May 28 02:46:54 PM PDT 24
Finished May 28 02:47:19 PM PDT 24
Peak memory 226240 kb
Host smart-743c8b3c-0d5b-419d-b602-bd2c6c2b9cd1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886924803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2886924803
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2397151340
Short name T463
Test name
Test status
Simulation time 201107569 ps
CPU time 8.81 seconds
Started May 28 02:46:41 PM PDT 24
Finished May 28 02:47:05 PM PDT 24
Peak memory 225956 kb
Host smart-98fe5c95-c305-48ad-b614-7f5853367a16
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397151340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2397151340
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.265834160
Short name T382
Test name
Test status
Simulation time 1239589523 ps
CPU time 15.55 seconds
Started May 28 02:46:42 PM PDT 24
Finished May 28 02:47:14 PM PDT 24
Peak memory 217916 kb
Host smart-4bf4da94-8bee-424e-b113-d8c6582a9f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265834160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.265834160
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.1037656999
Short name T329
Test name
Test status
Simulation time 204467432 ps
CPU time 2.42 seconds
Started May 28 02:46:42 PM PDT 24
Finished May 28 02:46:59 PM PDT 24
Peak memory 214168 kb
Host smart-8728e72a-01fc-4a80-a280-adc3d34db07e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037656999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.1037656999
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.1194673909
Short name T596
Test name
Test status
Simulation time 267924211 ps
CPU time 31.97 seconds
Started May 28 02:46:43 PM PDT 24
Finished May 28 02:47:31 PM PDT 24
Peak memory 250592 kb
Host smart-a8c29169-9418-4e13-a39c-3248bfd3aa4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194673909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.1194673909
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2379500795
Short name T748
Test name
Test status
Simulation time 79722856 ps
CPU time 7.63 seconds
Started May 28 02:46:43 PM PDT 24
Finished May 28 02:47:06 PM PDT 24
Peak memory 250844 kb
Host smart-3efcfe97-85a9-452f-bd42-fbfb7032ada5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379500795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2379500795
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2658588155
Short name T372
Test name
Test status
Simulation time 5388856958 ps
CPU time 63.47 seconds
Started May 28 02:46:42 PM PDT 24
Finished May 28 02:48:01 PM PDT 24
Peak memory 273336 kb
Host smart-ef51d27f-0c6f-4bed-b1e5-84ae050e0aed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658588155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2658588155
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2573821940
Short name T833
Test name
Test status
Simulation time 61280207 ps
CPU time 0.91 seconds
Started May 28 02:46:41 PM PDT 24
Finished May 28 02:46:58 PM PDT 24
Peak memory 211500 kb
Host smart-b25f2017-f992-43e6-b63a-be152fb5e18e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573821940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2573821940
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1225934353
Short name T464
Test name
Test status
Simulation time 1270055432 ps
CPU time 12.89 seconds
Started May 28 02:48:12 PM PDT 24
Finished May 28 02:48:30 PM PDT 24
Peak memory 217924 kb
Host smart-093a88d4-33cd-4c1c-9c34-a428ee43a56c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225934353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1225934353
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2145501752
Short name T31
Test name
Test status
Simulation time 922595285 ps
CPU time 2.69 seconds
Started May 28 02:48:10 PM PDT 24
Finished May 28 02:48:18 PM PDT 24
Peak memory 209444 kb
Host smart-e4570208-f109-4288-bc7a-1836b4ab36bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145501752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2145501752
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.4232585700
Short name T170
Test name
Test status
Simulation time 289149155 ps
CPU time 2.91 seconds
Started May 28 02:48:12 PM PDT 24
Finished May 28 02:48:20 PM PDT 24
Peak memory 217868 kb
Host smart-b56038af-f04f-4555-99da-8a139aac94c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232585700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.4232585700
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.2542816365
Short name T864
Test name
Test status
Simulation time 898143459 ps
CPU time 16.49 seconds
Started May 28 02:48:15 PM PDT 24
Finished May 28 02:48:38 PM PDT 24
Peak memory 218792 kb
Host smart-c3f382e4-eab1-4e79-9800-d99b963649e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542816365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.2542816365
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2188350619
Short name T332
Test name
Test status
Simulation time 405320891 ps
CPU time 15.43 seconds
Started May 28 02:48:12 PM PDT 24
Finished May 28 02:48:33 PM PDT 24
Peak memory 217864 kb
Host smart-79e1e19d-d077-46ad-b6e7-cd26aeeb8a3a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188350619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2188350619
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2768632863
Short name T443
Test name
Test status
Simulation time 4098337460 ps
CPU time 20.69 seconds
Started May 28 02:48:49 PM PDT 24
Finished May 28 02:49:15 PM PDT 24
Peak memory 217988 kb
Host smart-27014253-045a-47be-8e1f-4658deaffc72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768632863 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2768632863
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.1045576255
Short name T311
Test name
Test status
Simulation time 1193640879 ps
CPU time 10.04 seconds
Started May 28 02:48:11 PM PDT 24
Finished May 28 02:48:26 PM PDT 24
Peak memory 217920 kb
Host smart-b1fa9166-74c6-434d-adf7-38ff069cdfb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045576255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.1045576255
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.169847509
Short name T295
Test name
Test status
Simulation time 264348637 ps
CPU time 2.75 seconds
Started May 28 02:48:15 PM PDT 24
Finished May 28 02:48:24 PM PDT 24
Peak memory 214380 kb
Host smart-fc80f3b6-f2d8-490f-9bcc-374325552913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169847509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.169847509
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.681556281
Short name T480
Test name
Test status
Simulation time 886207594 ps
CPU time 21.05 seconds
Started May 28 02:48:13 PM PDT 24
Finished May 28 02:48:40 PM PDT 24
Peak memory 250828 kb
Host smart-abcc6c16-4afc-4e0e-8949-61ca6c8dc464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681556281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.681556281
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2748046620
Short name T627
Test name
Test status
Simulation time 1569034153 ps
CPU time 7.09 seconds
Started May 28 02:48:10 PM PDT 24
Finished May 28 02:48:23 PM PDT 24
Peak memory 250348 kb
Host smart-21475286-726b-42be-b559-617cb3b4e1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748046620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2748046620
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1030956689
Short name T852
Test name
Test status
Simulation time 57718954113 ps
CPU time 301.24 seconds
Started May 28 02:48:15 PM PDT 24
Finished May 28 02:53:23 PM PDT 24
Peak memory 250936 kb
Host smart-3587dcd4-41ad-4457-912f-a2e43510bce0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030956689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1030956689
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.3838211006
Short name T164
Test name
Test status
Simulation time 12330150707 ps
CPU time 433.74 seconds
Started May 28 02:48:12 PM PDT 24
Finished May 28 02:55:31 PM PDT 24
Peak memory 283720 kb
Host smart-24316165-519c-4e6a-942c-005a0b0a6242
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3838211006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.3838211006
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1064123084
Short name T595
Test name
Test status
Simulation time 10841404 ps
CPU time 0.74 seconds
Started May 28 02:48:15 PM PDT 24
Finished May 28 02:48:22 PM PDT 24
Peak memory 207816 kb
Host smart-7a1a6a02-fc44-41dc-aba8-c9a87a652f79
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064123084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1064123084
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.871723856
Short name T586
Test name
Test status
Simulation time 164563291 ps
CPU time 0.89 seconds
Started May 28 02:48:13 PM PDT 24
Finished May 28 02:48:20 PM PDT 24
Peak memory 209452 kb
Host smart-3c389552-8f15-4cf0-9c1c-4926641b5790
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871723856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.871723856
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1774586540
Short name T430
Test name
Test status
Simulation time 555745046 ps
CPU time 14 seconds
Started May 28 02:48:47 PM PDT 24
Finished May 28 02:49:07 PM PDT 24
Peak memory 217848 kb
Host smart-1404b7e4-42e0-4482-8436-28a210912fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774586540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1774586540
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.3659045057
Short name T817
Test name
Test status
Simulation time 2131293563 ps
CPU time 7.53 seconds
Started May 28 02:48:12 PM PDT 24
Finished May 28 02:48:25 PM PDT 24
Peak memory 216964 kb
Host smart-520679d9-9a5f-4990-96f2-2afc23f0ecd5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659045057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.3659045057
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.226714857
Short name T662
Test name
Test status
Simulation time 97518892 ps
CPU time 3.33 seconds
Started May 28 02:48:12 PM PDT 24
Finished May 28 02:48:21 PM PDT 24
Peak memory 217856 kb
Host smart-2ca424ca-26a5-4439-985a-fd4c69961782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226714857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.226714857
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.2491625878
Short name T786
Test name
Test status
Simulation time 4621425909 ps
CPU time 12.37 seconds
Started May 28 02:48:16 PM PDT 24
Finished May 28 02:48:34 PM PDT 24
Peak memory 218500 kb
Host smart-04c16cb3-9413-495b-9bea-aeb6c18b7529
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491625878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.2491625878
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3559410112
Short name T307
Test name
Test status
Simulation time 839235905 ps
CPU time 7.89 seconds
Started May 28 02:48:11 PM PDT 24
Finished May 28 02:48:24 PM PDT 24
Peak memory 217876 kb
Host smart-ae93a24d-7222-4e40-a318-65d15379d835
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559410112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3559410112
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.2130375355
Short name T229
Test name
Test status
Simulation time 1377534157 ps
CPU time 10.24 seconds
Started May 28 02:48:13 PM PDT 24
Finished May 28 02:48:29 PM PDT 24
Peak memory 217872 kb
Host smart-65a48ef7-fe23-4b19-9ca3-7121cd919d21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130375355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
2130375355
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.3191239397
Short name T868
Test name
Test status
Simulation time 397559399 ps
CPU time 11.82 seconds
Started May 28 02:48:13 PM PDT 24
Finished May 28 02:48:30 PM PDT 24
Peak memory 217916 kb
Host smart-d3f647f9-c3f3-4a74-abf1-05b8492665d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191239397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.3191239397
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2680431404
Short name T337
Test name
Test status
Simulation time 19795574 ps
CPU time 1.56 seconds
Started May 28 02:48:12 PM PDT 24
Finished May 28 02:48:20 PM PDT 24
Peak memory 213396 kb
Host smart-175e0c3d-ce94-464e-acc4-697b0171f684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680431404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2680431404
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2275811908
Short name T832
Test name
Test status
Simulation time 1022482362 ps
CPU time 26.07 seconds
Started May 28 02:48:14 PM PDT 24
Finished May 28 02:48:45 PM PDT 24
Peak memory 244824 kb
Host smart-3670aff2-699f-4075-b447-047dbad89363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275811908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2275811908
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3735339088
Short name T40
Test name
Test status
Simulation time 891658874 ps
CPU time 6.56 seconds
Started May 28 02:48:11 PM PDT 24
Finished May 28 02:48:23 PM PDT 24
Peak memory 248488 kb
Host smart-51b2309e-b0d1-4690-aac8-4296cb9896f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735339088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3735339088
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2639822742
Short name T333
Test name
Test status
Simulation time 10392973585 ps
CPU time 119.62 seconds
Started May 28 02:48:11 PM PDT 24
Finished May 28 02:50:16 PM PDT 24
Peak memory 278224 kb
Host smart-82fe87eb-a13e-4c40-bce4-7b1250f48720
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639822742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2639822742
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3469020554
Short name T675
Test name
Test status
Simulation time 23494145 ps
CPU time 1.06 seconds
Started May 28 02:48:14 PM PDT 24
Finished May 28 02:48:22 PM PDT 24
Peak memory 211444 kb
Host smart-14f86f97-d8a4-417e-a650-033a54502135
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469020554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3469020554
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1026605112
Short name T95
Test name
Test status
Simulation time 28380667 ps
CPU time 1 seconds
Started May 28 02:48:14 PM PDT 24
Finished May 28 02:48:21 PM PDT 24
Peak memory 209416 kb
Host smart-58c48433-cd4c-4f2e-9c4d-0b6e3fd3150a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026605112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1026605112
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.494313687
Short name T227
Test name
Test status
Simulation time 2120941871 ps
CPU time 20.96 seconds
Started May 28 02:48:16 PM PDT 24
Finished May 28 02:48:43 PM PDT 24
Peak memory 217960 kb
Host smart-3a3f925d-4429-418c-ba37-9162ed9ef7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494313687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.494313687
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.1264399322
Short name T32
Test name
Test status
Simulation time 94550746 ps
CPU time 1.88 seconds
Started May 28 02:48:12 PM PDT 24
Finished May 28 02:48:19 PM PDT 24
Peak memory 209444 kb
Host smart-b9f50142-972d-412c-883e-9bfc3afc1a75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264399322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.1264399322
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1992769003
Short name T427
Test name
Test status
Simulation time 221163448 ps
CPU time 2.44 seconds
Started May 28 02:48:15 PM PDT 24
Finished May 28 02:48:24 PM PDT 24
Peak memory 217920 kb
Host smart-5d655ddd-2b0b-4eeb-9963-a3ea83de64bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992769003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1992769003
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3480789734
Short name T374
Test name
Test status
Simulation time 352718041 ps
CPU time 14.2 seconds
Started May 28 02:48:16 PM PDT 24
Finished May 28 02:48:36 PM PDT 24
Peak memory 218064 kb
Host smart-dccaf5a7-ccc8-43b1-a007-468b8fcdda4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480789734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3480789734
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3804787759
Short name T440
Test name
Test status
Simulation time 1129515190 ps
CPU time 12.95 seconds
Started May 28 02:48:13 PM PDT 24
Finished May 28 02:48:32 PM PDT 24
Peak memory 217800 kb
Host smart-a1c9880d-38ae-4417-9b3b-39cea7ef76f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804787759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3804787759
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1206266857
Short name T792
Test name
Test status
Simulation time 997106111 ps
CPU time 8.33 seconds
Started May 28 02:48:14 PM PDT 24
Finished May 28 02:48:28 PM PDT 24
Peak memory 217876 kb
Host smart-ee39a932-a170-44dc-8360-90bbd1c82b91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206266857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1206266857
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3702062714
Short name T839
Test name
Test status
Simulation time 137811977 ps
CPU time 2.37 seconds
Started May 28 02:48:15 PM PDT 24
Finished May 28 02:48:24 PM PDT 24
Peak memory 213732 kb
Host smart-5e39817c-3c48-4c25-9810-895db6a88dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702062714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3702062714
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.1532113343
Short name T543
Test name
Test status
Simulation time 859458815 ps
CPU time 23.79 seconds
Started May 28 02:48:11 PM PDT 24
Finished May 28 02:48:40 PM PDT 24
Peak memory 250808 kb
Host smart-394ebfc3-1ea4-41b6-a8ef-997db3c17302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532113343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.1532113343
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.3654368563
Short name T469
Test name
Test status
Simulation time 405541073 ps
CPU time 2.84 seconds
Started May 28 02:48:13 PM PDT 24
Finished May 28 02:48:22 PM PDT 24
Peak memory 222264 kb
Host smart-4ba3c0e0-ed50-4222-8492-2bd9ce477659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654368563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.3654368563
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.4102586704
Short name T700
Test name
Test status
Simulation time 4683366731 ps
CPU time 109.28 seconds
Started May 28 02:48:17 PM PDT 24
Finished May 28 02:50:12 PM PDT 24
Peak memory 268580 kb
Host smart-6e6efc7c-efd4-4eeb-a04a-d2022ff81f4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102586704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.4102586704
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.2649025923
Short name T101
Test name
Test status
Simulation time 18456179952 ps
CPU time 572.49 seconds
Started May 28 02:48:17 PM PDT 24
Finished May 28 02:57:56 PM PDT 24
Peak memory 496656 kb
Host smart-30ed8832-a1b9-4378-bdcd-1818646a2633
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2649025923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.2649025923
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.1758180775
Short name T494
Test name
Test status
Simulation time 20474279 ps
CPU time 0.97 seconds
Started May 28 02:48:14 PM PDT 24
Finished May 28 02:48:20 PM PDT 24
Peak memory 211484 kb
Host smart-f1d97325-e177-47bf-9253-eafdc64aa0c5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758180775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.1758180775
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1318845200
Short name T721
Test name
Test status
Simulation time 26891046 ps
CPU time 0.99 seconds
Started May 28 02:48:12 PM PDT 24
Finished May 28 02:48:18 PM PDT 24
Peak memory 209424 kb
Host smart-138ab8bf-787e-4d14-9c09-bd528b571307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318845200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1318845200
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.4231598764
Short name T253
Test name
Test status
Simulation time 683245130 ps
CPU time 9.94 seconds
Started May 28 02:48:18 PM PDT 24
Finished May 28 02:48:35 PM PDT 24
Peak memory 217848 kb
Host smart-f6c47317-a8b9-4017-a1fc-1608bfbcfe93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231598764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.4231598764
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1846968237
Short name T448
Test name
Test status
Simulation time 1198361580 ps
CPU time 3.78 seconds
Started May 28 02:48:18 PM PDT 24
Finished May 28 02:48:29 PM PDT 24
Peak memory 209436 kb
Host smart-c454068e-9485-4c4e-89ee-27e746afdfc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846968237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1846968237
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2894507063
Short name T378
Test name
Test status
Simulation time 346935167 ps
CPU time 3.21 seconds
Started May 28 02:48:13 PM PDT 24
Finished May 28 02:48:22 PM PDT 24
Peak memory 217800 kb
Host smart-a13da6b5-0b2f-4479-b124-5fb55d4d7e1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894507063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2894507063
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.3269396944
Short name T373
Test name
Test status
Simulation time 617056507 ps
CPU time 11.22 seconds
Started May 28 02:48:18 PM PDT 24
Finished May 28 02:48:36 PM PDT 24
Peak memory 225940 kb
Host smart-75dcc748-4cf8-47e5-82f6-860d3dda018f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269396944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.3269396944
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.4222668090
Short name T846
Test name
Test status
Simulation time 236609260 ps
CPU time 10.85 seconds
Started May 28 02:48:20 PM PDT 24
Finished May 28 02:48:37 PM PDT 24
Peak memory 225968 kb
Host smart-0d7db37b-2aa3-4fd2-bf91-c42db60d42e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222668090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.4222668090
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3700816917
Short name T495
Test name
Test status
Simulation time 259666765 ps
CPU time 10.26 seconds
Started May 28 02:48:18 PM PDT 24
Finished May 28 02:48:35 PM PDT 24
Peak memory 217872 kb
Host smart-7ebf7feb-84d6-43f0-9b8f-93ad1c143ccf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700816917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3700816917
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.364027593
Short name T454
Test name
Test status
Simulation time 255794614 ps
CPU time 12.02 seconds
Started May 28 02:48:18 PM PDT 24
Finished May 28 02:48:37 PM PDT 24
Peak memory 225940 kb
Host smart-f2f5137d-671b-4b10-8774-09cc9b90033c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364027593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.364027593
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.2876738499
Short name T294
Test name
Test status
Simulation time 64510445 ps
CPU time 3 seconds
Started May 28 02:48:14 PM PDT 24
Finished May 28 02:48:22 PM PDT 24
Peak memory 214104 kb
Host smart-d9382156-7659-4892-882c-c775e9091213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876738499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.2876738499
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3170576657
Short name T797
Test name
Test status
Simulation time 828796925 ps
CPU time 25.25 seconds
Started May 28 02:48:12 PM PDT 24
Finished May 28 02:48:43 PM PDT 24
Peak memory 246868 kb
Host smart-532e2e3e-b18d-449d-b076-3eae298713ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170576657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3170576657
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.2656549794
Short name T316
Test name
Test status
Simulation time 101286784 ps
CPU time 12.36 seconds
Started May 28 02:48:14 PM PDT 24
Finished May 28 02:48:32 PM PDT 24
Peak memory 250840 kb
Host smart-94a599be-d8e3-419a-b1c1-f58bae341ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656549794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.2656549794
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.4175578221
Short name T286
Test name
Test status
Simulation time 74261776008 ps
CPU time 617.37 seconds
Started May 28 02:48:16 PM PDT 24
Finished May 28 02:58:39 PM PDT 24
Peak memory 283672 kb
Host smart-4b5f9d61-bda1-4118-8fa0-4886c60c56c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175578221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.4175578221
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.3197239220
Short name T270
Test name
Test status
Simulation time 18346896 ps
CPU time 0.95 seconds
Started May 28 02:48:16 PM PDT 24
Finished May 28 02:48:23 PM PDT 24
Peak memory 211480 kb
Host smart-f5cb8fb1-7fc1-4cc6-8d15-1261e30fd931
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197239220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.3197239220
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.2619359102
Short name T282
Test name
Test status
Simulation time 15126474 ps
CPU time 1.04 seconds
Started May 28 02:48:20 PM PDT 24
Finished May 28 02:48:27 PM PDT 24
Peak memory 209512 kb
Host smart-1ead136b-c9d7-4083-8bfc-2cc03d383a87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619359102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.2619359102
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1242045450
Short name T15
Test name
Test status
Simulation time 1674335053 ps
CPU time 13.94 seconds
Started May 28 02:48:21 PM PDT 24
Finished May 28 02:48:41 PM PDT 24
Peak memory 217792 kb
Host smart-146c2855-763d-4514-b599-5a32fea89eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242045450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1242045450
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.3798494635
Short name T552
Test name
Test status
Simulation time 542843127 ps
CPU time 13.45 seconds
Started May 28 02:48:21 PM PDT 24
Finished May 28 02:48:41 PM PDT 24
Peak memory 209444 kb
Host smart-c08cd3d4-916a-4a93-8021-cb9e05c9d60d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798494635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.3798494635
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1981867436
Short name T462
Test name
Test status
Simulation time 354584291 ps
CPU time 6.22 seconds
Started May 28 02:48:16 PM PDT 24
Finished May 28 02:48:28 PM PDT 24
Peak memory 217812 kb
Host smart-c5f989cc-d47c-4665-a231-dc9d9fb9cd6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981867436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1981867436
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.4008664145
Short name T365
Test name
Test status
Simulation time 218645348 ps
CPU time 8.16 seconds
Started May 28 02:48:21 PM PDT 24
Finished May 28 02:48:35 PM PDT 24
Peak memory 225956 kb
Host smart-b22ff146-d49d-4f7c-a7e4-8fd9a5413068
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008664145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.4008664145
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2155662710
Short name T271
Test name
Test status
Simulation time 4233899774 ps
CPU time 9.17 seconds
Started May 28 02:48:21 PM PDT 24
Finished May 28 02:48:36 PM PDT 24
Peak memory 226024 kb
Host smart-ac4aba07-fb26-449c-9d5c-ae25a7b32504
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155662710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2155662710
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.4050308105
Short name T465
Test name
Test status
Simulation time 1126564363 ps
CPU time 10.75 seconds
Started May 28 02:48:21 PM PDT 24
Finished May 28 02:48:38 PM PDT 24
Peak memory 217876 kb
Host smart-7b2bf713-225a-4afd-8daf-cd0c8137e0cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050308105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
4050308105
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.3234086596
Short name T53
Test name
Test status
Simulation time 314001599 ps
CPU time 12.68 seconds
Started May 28 02:48:15 PM PDT 24
Finished May 28 02:48:34 PM PDT 24
Peak memory 217876 kb
Host smart-f40fd478-5d47-48cd-b8de-0aae1e2e4ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234086596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.3234086596
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1957387017
Short name T509
Test name
Test status
Simulation time 1106566097 ps
CPU time 8.57 seconds
Started May 28 02:48:18 PM PDT 24
Finished May 28 02:48:33 PM PDT 24
Peak memory 213856 kb
Host smart-fd47952e-8996-4dca-979f-6d0baa06116e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957387017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1957387017
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.3150178862
Short name T621
Test name
Test status
Simulation time 264580414 ps
CPU time 18.09 seconds
Started May 28 02:48:20 PM PDT 24
Finished May 28 02:48:44 PM PDT 24
Peak memory 250848 kb
Host smart-1881fa39-53ae-4f4f-96b8-7ee131a4cb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150178862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3150178862
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.1419775812
Short name T260
Test name
Test status
Simulation time 53815794 ps
CPU time 6.97 seconds
Started May 28 02:48:19 PM PDT 24
Finished May 28 02:48:33 PM PDT 24
Peak memory 246204 kb
Host smart-ee53ba7d-1fb7-4f0a-b419-f8f8b8ffcdce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419775812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.1419775812
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2606683079
Short name T814
Test name
Test status
Simulation time 4384723794 ps
CPU time 33.09 seconds
Started May 28 02:48:21 PM PDT 24
Finished May 28 02:49:00 PM PDT 24
Peak memory 250952 kb
Host smart-ab742ee3-3809-4943-850c-b974e22377a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606683079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2606683079
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1904058512
Short name T458
Test name
Test status
Simulation time 11133477 ps
CPU time 1.06 seconds
Started May 28 02:48:15 PM PDT 24
Finished May 28 02:48:22 PM PDT 24
Peak memory 211488 kb
Host smart-d428fe6a-904d-4adb-9c89-a6f34308f31a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904058512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.1904058512
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.4284493188
Short name T324
Test name
Test status
Simulation time 64948935 ps
CPU time 1.12 seconds
Started May 28 02:48:12 PM PDT 24
Finished May 28 02:48:19 PM PDT 24
Peak memory 209280 kb
Host smart-b3689082-8c5c-4484-bf40-165b31d894ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284493188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.4284493188
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.438109281
Short name T400
Test name
Test status
Simulation time 229849776 ps
CPU time 9.37 seconds
Started May 28 02:48:17 PM PDT 24
Finished May 28 02:48:32 PM PDT 24
Peak memory 217848 kb
Host smart-7e9c760f-494d-4aaa-94af-1032ca69e9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438109281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.438109281
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2152777573
Short name T560
Test name
Test status
Simulation time 4288017772 ps
CPU time 23.82 seconds
Started May 28 02:48:17 PM PDT 24
Finished May 28 02:48:47 PM PDT 24
Peak memory 217744 kb
Host smart-d285c891-1661-47ac-bdba-721553195921
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152777573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2152777573
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.3785043144
Short name T835
Test name
Test status
Simulation time 323972136 ps
CPU time 2.83 seconds
Started May 28 02:48:19 PM PDT 24
Finished May 28 02:48:29 PM PDT 24
Peak memory 217824 kb
Host smart-d510b5df-957f-40e1-8253-eea0cec986ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785043144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.3785043144
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1725146211
Short name T569
Test name
Test status
Simulation time 1237344194 ps
CPU time 17.65 seconds
Started May 28 02:48:18 PM PDT 24
Finished May 28 02:48:42 PM PDT 24
Peak memory 225940 kb
Host smart-67776be6-d3fc-47ea-9473-e5eae95ae209
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725146211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1725146211
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2087840320
Short name T800
Test name
Test status
Simulation time 1400282231 ps
CPU time 10.23 seconds
Started May 28 02:48:19 PM PDT 24
Finished May 28 02:48:36 PM PDT 24
Peak memory 224912 kb
Host smart-b46cee61-b67a-4200-b519-7d44279fdddb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087840320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2087840320
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.24275634
Short name T648
Test name
Test status
Simulation time 308112390 ps
CPU time 7.97 seconds
Started May 28 02:48:16 PM PDT 24
Finished May 28 02:48:30 PM PDT 24
Peak memory 217820 kb
Host smart-b10c0e22-5ce3-4b87-a0e6-baf6fda43d6d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24275634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.24275634
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3267752351
Short name T668
Test name
Test status
Simulation time 2418722518 ps
CPU time 6.25 seconds
Started May 28 02:48:17 PM PDT 24
Finished May 28 02:48:30 PM PDT 24
Peak memory 218032 kb
Host smart-874113d4-bf7a-4744-ba1f-259df006260d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267752351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3267752351
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3028509250
Short name T39
Test name
Test status
Simulation time 149764131 ps
CPU time 4.17 seconds
Started May 28 02:48:21 PM PDT 24
Finished May 28 02:48:31 PM PDT 24
Peak memory 223032 kb
Host smart-aed8c97c-f2e7-4fb6-89c3-0206e9627893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028509250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3028509250
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.4275359542
Short name T727
Test name
Test status
Simulation time 581303053 ps
CPU time 23.93 seconds
Started May 28 02:48:15 PM PDT 24
Finished May 28 02:48:45 PM PDT 24
Peak memory 250568 kb
Host smart-637ce038-0fd9-4faa-8167-2fdd9fd02130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275359542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.4275359542
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.1477046624
Short name T616
Test name
Test status
Simulation time 104898327 ps
CPU time 3.11 seconds
Started May 28 02:48:16 PM PDT 24
Finished May 28 02:48:25 PM PDT 24
Peak memory 217776 kb
Host smart-3bd4e29a-8eb8-4c3b-adf0-d6926732c9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477046624 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.1477046624
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2687039110
Short name T177
Test name
Test status
Simulation time 23726561859 ps
CPU time 208.55 seconds
Started May 28 02:48:15 PM PDT 24
Finished May 28 02:51:50 PM PDT 24
Peak memory 283656 kb
Host smart-f47d377b-1a4d-41d0-86ac-7239ee2caab1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687039110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2687039110
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.1875389572
Short name T483
Test name
Test status
Simulation time 19443280 ps
CPU time 0.83 seconds
Started May 28 02:48:18 PM PDT 24
Finished May 28 02:48:26 PM PDT 24
Peak memory 211452 kb
Host smart-34b050e7-1834-48b3-8aea-be67ab32a835
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875389572 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.1875389572
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3877451482
Short name T75
Test name
Test status
Simulation time 33546519 ps
CPU time 0.91 seconds
Started May 28 02:48:26 PM PDT 24
Finished May 28 02:48:31 PM PDT 24
Peak memory 209432 kb
Host smart-b7bdd524-c844-4375-88a8-7ce8660c9614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877451482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3877451482
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3833877548
Short name T642
Test name
Test status
Simulation time 407554728 ps
CPU time 13.05 seconds
Started May 28 02:48:22 PM PDT 24
Finished May 28 02:48:41 PM PDT 24
Peak memory 217856 kb
Host smart-546a4936-ffda-46ff-b38c-6f903c1bcd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833877548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3833877548
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2251262369
Short name T415
Test name
Test status
Simulation time 744371654 ps
CPU time 14.64 seconds
Started May 28 02:48:51 PM PDT 24
Finished May 28 02:49:12 PM PDT 24
Peak memory 216980 kb
Host smart-cc7c05f8-a018-48e9-8d92-7193204424d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251262369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2251262369
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.1641825807
Short name T871
Test name
Test status
Simulation time 124046075 ps
CPU time 1.92 seconds
Started May 28 02:48:30 PM PDT 24
Finished May 28 02:48:35 PM PDT 24
Peak memory 217688 kb
Host smart-442a59ba-64a6-4fa1-8d2d-ee2422704406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641825807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.1641825807
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.3490607459
Short name T535
Test name
Test status
Simulation time 238570696 ps
CPU time 8.29 seconds
Started May 28 02:48:30 PM PDT 24
Finished May 28 02:48:42 PM PDT 24
Peak memory 225688 kb
Host smart-fedca143-0f86-48bf-8710-090835050110
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490607459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3490607459
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.3013391553
Short name T837
Test name
Test status
Simulation time 273766449 ps
CPU time 11.9 seconds
Started May 28 02:48:23 PM PDT 24
Finished May 28 02:48:40 PM PDT 24
Peak memory 217860 kb
Host smart-5a5df4f5-dacd-4f13-b9c3-9ddbc7ef80ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013391553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.3013391553
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.4057961661
Short name T410
Test name
Test status
Simulation time 1248705808 ps
CPU time 9.65 seconds
Started May 28 02:48:38 PM PDT 24
Finished May 28 02:48:53 PM PDT 24
Peak memory 217852 kb
Host smart-adc85094-13a1-45c3-a024-b99fce21b922
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057961661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
4057961661
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.2046512142
Short name T451
Test name
Test status
Simulation time 265490412 ps
CPU time 8.05 seconds
Started May 28 02:48:51 PM PDT 24
Finished May 28 02:49:05 PM PDT 24
Peak memory 217508 kb
Host smart-91bf3a6d-ccba-4cab-a7dc-3d46560513d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046512142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2046512142
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.2603383901
Short name T81
Test name
Test status
Simulation time 249946063 ps
CPU time 3.5 seconds
Started May 28 02:48:21 PM PDT 24
Finished May 28 02:48:31 PM PDT 24
Peak memory 214432 kb
Host smart-93c95a49-76ce-40eb-8ddb-4be977090301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603383901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.2603383901
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2191764191
Short name T554
Test name
Test status
Simulation time 416462832 ps
CPU time 25.4 seconds
Started May 28 02:48:21 PM PDT 24
Finished May 28 02:48:53 PM PDT 24
Peak memory 250816 kb
Host smart-09ce7e3b-7377-49d7-906e-e087d81bda1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191764191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2191764191
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3405746777
Short name T317
Test name
Test status
Simulation time 207511088 ps
CPU time 7.25 seconds
Started May 28 02:48:36 PM PDT 24
Finished May 28 02:48:48 PM PDT 24
Peak memory 250816 kb
Host smart-0deafe35-c7fc-4b68-91b0-1902502f98b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405746777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3405746777
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1711115847
Short name T690
Test name
Test status
Simulation time 13885480 ps
CPU time 0.96 seconds
Started May 28 02:48:51 PM PDT 24
Finished May 28 02:48:58 PM PDT 24
Peak memory 211012 kb
Host smart-f1910c0c-3d58-4bc4-8d65-99a8468e2e74
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711115847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1711115847
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1045604457
Short name T612
Test name
Test status
Simulation time 43955551 ps
CPU time 1.1 seconds
Started May 28 02:48:27 PM PDT 24
Finished May 28 02:48:32 PM PDT 24
Peak memory 209400 kb
Host smart-a930a6f4-0b13-4c34-9ede-aa53027ed740
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045604457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1045604457
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2011121399
Short name T418
Test name
Test status
Simulation time 1234400397 ps
CPU time 10.56 seconds
Started May 28 02:48:30 PM PDT 24
Finished May 28 02:48:44 PM PDT 24
Peak memory 217832 kb
Host smart-b0c4c996-fb82-4c7a-9578-b32781c09e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011121399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2011121399
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1662603593
Short name T600
Test name
Test status
Simulation time 219946835 ps
CPU time 2.78 seconds
Started May 28 02:48:22 PM PDT 24
Finished May 28 02:48:30 PM PDT 24
Peak memory 209384 kb
Host smart-b62ce250-5572-461f-b9f8-9cc572b0c4e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662603593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1662603593
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.1410671825
Short name T686
Test name
Test status
Simulation time 78018402 ps
CPU time 2.38 seconds
Started May 28 02:48:30 PM PDT 24
Finished May 28 02:48:36 PM PDT 24
Peak memory 217824 kb
Host smart-1d3becae-dae8-42c4-bdfe-d53de5c12838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410671825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.1410671825
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.851580208
Short name T753
Test name
Test status
Simulation time 964909662 ps
CPU time 8.11 seconds
Started May 28 02:48:33 PM PDT 24
Finished May 28 02:48:46 PM PDT 24
Peak memory 225948 kb
Host smart-eb947170-3c85-4c61-9c0b-59ffbe53ee57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851580208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.851580208
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.469899701
Short name T236
Test name
Test status
Simulation time 3425563746 ps
CPU time 21.97 seconds
Started May 28 02:48:29 PM PDT 24
Finished May 28 02:48:55 PM PDT 24
Peak memory 217980 kb
Host smart-aaa7df26-0b4f-40ae-b9ec-dbc16542d398
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469899701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.469899701
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.934251745
Short name T659
Test name
Test status
Simulation time 1865613663 ps
CPU time 13.52 seconds
Started May 28 02:48:28 PM PDT 24
Finished May 28 02:48:45 PM PDT 24
Peak memory 217772 kb
Host smart-bec79b25-7ebe-4da9-ae80-30311ad75399
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934251745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.934251745
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.930725670
Short name T831
Test name
Test status
Simulation time 2030693770 ps
CPU time 8.15 seconds
Started May 28 02:48:46 PM PDT 24
Finished May 28 02:49:00 PM PDT 24
Peak memory 218088 kb
Host smart-e151125a-69e0-434f-8b11-f383cb249a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930725670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.930725670
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.2188246016
Short name T78
Test name
Test status
Simulation time 39400494 ps
CPU time 3.04 seconds
Started May 28 02:48:30 PM PDT 24
Finished May 28 02:48:37 PM PDT 24
Peak memory 214604 kb
Host smart-15f97298-b062-4534-9389-1fc5e7ef271b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188246016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.2188246016
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3763353442
Short name T715
Test name
Test status
Simulation time 645585950 ps
CPU time 23.67 seconds
Started May 28 02:48:30 PM PDT 24
Finished May 28 02:48:57 PM PDT 24
Peak memory 250824 kb
Host smart-c09c7b92-11cd-47f9-b913-09e8c726877a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763353442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3763353442
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.498753958
Short name T14
Test name
Test status
Simulation time 256247022 ps
CPU time 7.03 seconds
Started May 28 02:48:28 PM PDT 24
Finished May 28 02:48:39 PM PDT 24
Peak memory 250760 kb
Host smart-33d10046-bb7d-41f2-8ef8-b7363cc21e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498753958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.498753958
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.3361794539
Short name T580
Test name
Test status
Simulation time 9501756727 ps
CPU time 56.09 seconds
Started May 28 02:48:29 PM PDT 24
Finished May 28 02:49:29 PM PDT 24
Peak memory 270880 kb
Host smart-cb62cca3-3914-4ac5-8ba9-4bb97b1ba13b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361794539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.3361794539
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.284346979
Short name T143
Test name
Test status
Simulation time 137313865520 ps
CPU time 1067.67 seconds
Started May 28 02:48:40 PM PDT 24
Finished May 28 03:06:34 PM PDT 24
Peak memory 349444 kb
Host smart-3455b481-e822-46c2-9f09-89ca07e158db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=284346979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.284346979
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.81846241
Short name T622
Test name
Test status
Simulation time 31917696 ps
CPU time 0.91 seconds
Started May 28 02:48:23 PM PDT 24
Finished May 28 02:48:29 PM PDT 24
Peak memory 211424 kb
Host smart-c972660b-239c-41b7-a894-a4f3c645ca6f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81846241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctr
l_volatile_unlock_smoke.81846241
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.4072078897
Short name T499
Test name
Test status
Simulation time 66194266 ps
CPU time 1.01 seconds
Started May 28 02:48:21 PM PDT 24
Finished May 28 02:48:29 PM PDT 24
Peak memory 209448 kb
Host smart-af0e6d26-6155-48bf-b07e-9ac0ec70859b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072078897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.4072078897
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2938532228
Short name T756
Test name
Test status
Simulation time 2294672838 ps
CPU time 10.99 seconds
Started May 28 02:48:22 PM PDT 24
Finished May 28 02:48:39 PM PDT 24
Peak memory 217840 kb
Host smart-e2ec4aca-114b-4378-b399-40068e7fe0c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938532228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2938532228
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.425448834
Short name T826
Test name
Test status
Simulation time 17145129 ps
CPU time 1.5 seconds
Started May 28 02:48:26 PM PDT 24
Finished May 28 02:48:32 PM PDT 24
Peak memory 217836 kb
Host smart-020842f2-ceb3-416f-b72f-45d0ed21ab68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425448834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.425448834
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3913511332
Short name T414
Test name
Test status
Simulation time 403987907 ps
CPU time 9.94 seconds
Started May 28 02:48:49 PM PDT 24
Finished May 28 02:49:04 PM PDT 24
Peak memory 217868 kb
Host smart-c9794b48-efe3-488e-b728-757e8fbc3641
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913511332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3913511332
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1576131175
Short name T433
Test name
Test status
Simulation time 258832122 ps
CPU time 10.99 seconds
Started May 28 02:48:25 PM PDT 24
Finished May 28 02:48:40 PM PDT 24
Peak memory 217848 kb
Host smart-3517f786-2451-4418-b040-de8acdbf0603
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576131175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1576131175
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.4019392687
Short name T20
Test name
Test status
Simulation time 206342364 ps
CPU time 8.36 seconds
Started May 28 02:48:26 PM PDT 24
Finished May 28 02:48:38 PM PDT 24
Peak memory 217936 kb
Host smart-d087eafa-9a60-4b82-92e5-76eefe529024
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019392687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
4019392687
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1110807070
Short name T459
Test name
Test status
Simulation time 889709103 ps
CPU time 7.8 seconds
Started May 28 02:48:22 PM PDT 24
Finished May 28 02:48:35 PM PDT 24
Peak memory 217972 kb
Host smart-8365e47a-46d9-44c5-9458-9fbb656b5813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110807070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1110807070
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.4211012443
Short name T322
Test name
Test status
Simulation time 268509772 ps
CPU time 6.87 seconds
Started May 28 02:48:24 PM PDT 24
Finished May 28 02:48:35 PM PDT 24
Peak memory 214652 kb
Host smart-5cadab5d-e91f-4177-a523-d944b7a5c4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211012443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.4211012443
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2193049899
Short name T428
Test name
Test status
Simulation time 165736823 ps
CPU time 22.59 seconds
Started May 28 02:48:31 PM PDT 24
Finished May 28 02:48:58 PM PDT 24
Peak memory 250672 kb
Host smart-77302a95-04d6-4b2a-a673-8129268f3b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193049899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2193049899
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1713621523
Short name T665
Test name
Test status
Simulation time 73828015 ps
CPU time 6.63 seconds
Started May 28 02:48:35 PM PDT 24
Finished May 28 02:48:47 PM PDT 24
Peak memory 250440 kb
Host smart-9ab8aaad-7dc9-45df-a90f-a0909d442450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713621523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1713621523
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1168056764
Short name T761
Test name
Test status
Simulation time 68803550721 ps
CPU time 315.16 seconds
Started May 28 02:48:23 PM PDT 24
Finished May 28 02:53:44 PM PDT 24
Peak memory 282868 kb
Host smart-3cf2fd3d-73ef-41c8-a4d3-8f603f899358
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168056764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1168056764
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.824167940
Short name T238
Test name
Test status
Simulation time 13267698 ps
CPU time 1.03 seconds
Started May 28 02:48:54 PM PDT 24
Finished May 28 02:49:03 PM PDT 24
Peak memory 211512 kb
Host smart-991aac9a-f696-4aeb-b109-3ea1874602c9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824167940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ct
rl_volatile_unlock_smoke.824167940
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.2220329708
Short name T750
Test name
Test status
Simulation time 58158295 ps
CPU time 0.87 seconds
Started May 28 02:48:30 PM PDT 24
Finished May 28 02:48:35 PM PDT 24
Peak memory 209432 kb
Host smart-27b29457-adf7-4074-b2d2-468d79c9a68b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2220329708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2220329708
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.1406063697
Short name T809
Test name
Test status
Simulation time 753517824 ps
CPU time 12.77 seconds
Started May 28 02:48:38 PM PDT 24
Finished May 28 02:48:56 PM PDT 24
Peak memory 217768 kb
Host smart-ba911a00-116e-482f-b6cf-d89be754efd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406063697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.1406063697
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2840133242
Short name T349
Test name
Test status
Simulation time 691311713 ps
CPU time 4.06 seconds
Started May 28 02:48:23 PM PDT 24
Finished May 28 02:48:32 PM PDT 24
Peak memory 216800 kb
Host smart-2debe6d2-1db1-4af6-956a-cd596dd985a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840133242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2840133242
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.2326360928
Short name T468
Test name
Test status
Simulation time 85335568 ps
CPU time 2.8 seconds
Started May 28 02:48:22 PM PDT 24
Finished May 28 02:48:31 PM PDT 24
Peak memory 217856 kb
Host smart-d7d1f728-4d8b-4882-a166-54b57f5ce643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326360928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.2326360928
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3367449716
Short name T321
Test name
Test status
Simulation time 3050070805 ps
CPU time 11.92 seconds
Started May 28 02:48:25 PM PDT 24
Finished May 28 02:48:41 PM PDT 24
Peak memory 226136 kb
Host smart-6d1a6716-3e34-45f7-a355-0ad9d2a10a03
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367449716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3367449716
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.1094864990
Short name T735
Test name
Test status
Simulation time 2341410944 ps
CPU time 13.15 seconds
Started May 28 02:48:29 PM PDT 24
Finished May 28 02:48:46 PM PDT 24
Peak memory 217980 kb
Host smart-97380ff3-264d-4d14-9ad7-0d4b5c29dad7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094864990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.1094864990
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.1864282066
Short name T529
Test name
Test status
Simulation time 1121975703 ps
CPU time 11.66 seconds
Started May 28 02:48:25 PM PDT 24
Finished May 28 02:48:41 PM PDT 24
Peak memory 217860 kb
Host smart-cda3b075-f25b-4842-b858-9497ee691b09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864282066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
1864282066
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3644070977
Short name T597
Test name
Test status
Simulation time 434911669 ps
CPU time 8.7 seconds
Started May 28 02:48:28 PM PDT 24
Finished May 28 02:48:40 PM PDT 24
Peak memory 217840 kb
Host smart-e4a049af-07b6-4d03-b170-fbea833c67e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644070977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3644070977
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.3320401841
Short name T172
Test name
Test status
Simulation time 93906199 ps
CPU time 2.01 seconds
Started May 28 02:48:50 PM PDT 24
Finished May 28 02:48:58 PM PDT 24
Peak memory 222720 kb
Host smart-f893de47-690e-4228-bff4-302753fdd875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320401841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.3320401841
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.903351694
Short name T579
Test name
Test status
Simulation time 454417104 ps
CPU time 25.75 seconds
Started May 28 02:48:28 PM PDT 24
Finished May 28 02:48:58 PM PDT 24
Peak memory 250784 kb
Host smart-0362d09e-ee1f-4c5d-aeee-1081abad7a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903351694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.903351694
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3191318200
Short name T582
Test name
Test status
Simulation time 205383214 ps
CPU time 6.12 seconds
Started May 28 02:48:24 PM PDT 24
Finished May 28 02:48:35 PM PDT 24
Peak memory 246552 kb
Host smart-f16fc76c-b188-4085-9227-75d25c30197c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191318200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3191318200
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.2854977848
Short name T343
Test name
Test status
Simulation time 7549173622 ps
CPU time 61.26 seconds
Started May 28 02:48:31 PM PDT 24
Finished May 28 02:49:37 PM PDT 24
Peak memory 250776 kb
Host smart-6e0a36c1-322a-4b13-be15-7b04acd7446e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854977848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.2854977848
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1948679012
Short name T486
Test name
Test status
Simulation time 13104766 ps
CPU time 1.03 seconds
Started May 28 02:48:22 PM PDT 24
Finished May 28 02:48:29 PM PDT 24
Peak memory 211424 kb
Host smart-a7e0a038-3924-407c-af0d-5df0e0c40848
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948679012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1948679012
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2665345695
Short name T186
Test name
Test status
Simulation time 17246374 ps
CPU time 1.07 seconds
Started May 28 02:46:54 PM PDT 24
Finished May 28 02:47:07 PM PDT 24
Peak memory 209428 kb
Host smart-c71b62ad-6073-4868-a5f3-ad7265e05272
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665345695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2665345695
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1545942621
Short name T438
Test name
Test status
Simulation time 40358471 ps
CPU time 0.86 seconds
Started May 28 02:46:42 PM PDT 24
Finished May 28 02:46:59 PM PDT 24
Peak memory 209336 kb
Host smart-ee6e6270-1e84-4579-ac8e-7133c088dff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545942621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1545942621
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.270761238
Short name T485
Test name
Test status
Simulation time 251150625 ps
CPU time 10.5 seconds
Started May 28 02:46:44 PM PDT 24
Finished May 28 02:47:11 PM PDT 24
Peak memory 217792 kb
Host smart-03b813a6-25d3-40a7-b3ff-36eb8693026b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270761238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.270761238
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.4222472190
Short name T9
Test name
Test status
Simulation time 1398379337 ps
CPU time 7.51 seconds
Started May 28 02:46:46 PM PDT 24
Finished May 28 02:47:09 PM PDT 24
Peak memory 209468 kb
Host smart-e43806a5-092f-4ddc-aa17-57ae9d4801e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222472190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.4222472190
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.349483973
Short name T363
Test name
Test status
Simulation time 2678684487 ps
CPU time 21.2 seconds
Started May 28 02:46:43 PM PDT 24
Finished May 28 02:47:20 PM PDT 24
Peak memory 217972 kb
Host smart-893fef13-797e-4318-b57d-939786c02dfc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349483973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.349483973
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.696795776
Short name T8
Test name
Test status
Simulation time 7325970972 ps
CPU time 5.22 seconds
Started May 28 02:46:44 PM PDT 24
Finished May 28 02:47:06 PM PDT 24
Peak memory 217580 kb
Host smart-61ca4777-3982-4ff0-9c42-b19b5e59c414
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696795776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.696795776
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1411159823
Short name T760
Test name
Test status
Simulation time 246493633 ps
CPU time 4.9 seconds
Started May 28 02:46:41 PM PDT 24
Finished May 28 02:47:01 PM PDT 24
Peak memory 217796 kb
Host smart-5252ed9c-433c-46d5-a557-800d2dc5da5c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411159823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1411159823
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.2386609137
Short name T83
Test name
Test status
Simulation time 255803622 ps
CPU time 6.64 seconds
Started May 28 02:46:43 PM PDT 24
Finished May 28 02:47:05 PM PDT 24
Peak memory 213768 kb
Host smart-f4b183df-03da-4c37-8613-3870375eda67
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386609137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
2386609137
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.868713167
Short name T639
Test name
Test status
Simulation time 5135781155 ps
CPU time 30.62 seconds
Started May 28 02:46:42 PM PDT 24
Finished May 28 02:47:29 PM PDT 24
Peak memory 254140 kb
Host smart-7603996d-7f7e-4750-9b51-1afc5861be33
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868713167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_state_failure.868713167
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1649236567
Short name T859
Test name
Test status
Simulation time 670259344 ps
CPU time 15.96 seconds
Started May 28 02:46:49 PM PDT 24
Finished May 28 02:47:19 PM PDT 24
Peak memory 250708 kb
Host smart-26c2043e-f846-47f0-973e-dae570781f4f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649236567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1649236567
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.1968994227
Short name T607
Test name
Test status
Simulation time 231932518 ps
CPU time 3.38 seconds
Started May 28 02:46:51 PM PDT 24
Finished May 28 02:47:07 PM PDT 24
Peak memory 217740 kb
Host smart-797f0afc-3d21-4131-9cd0-392c42744705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968994227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.1968994227
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2354585741
Short name T70
Test name
Test status
Simulation time 479019807 ps
CPU time 9.44 seconds
Started May 28 02:46:42 PM PDT 24
Finished May 28 02:47:08 PM PDT 24
Peak memory 214196 kb
Host smart-43786fd9-19c2-496a-8725-8ec67f843535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354585741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2354585741
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.37156750
Short name T92
Test name
Test status
Simulation time 2433503932 ps
CPU time 41.33 seconds
Started May 28 02:46:53 PM PDT 24
Finished May 28 02:47:46 PM PDT 24
Peak memory 271204 kb
Host smart-40fe1a09-4a5e-4211-9617-e983300dc9d4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37156750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.37156750
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.3445988072
Short name T304
Test name
Test status
Simulation time 647863432 ps
CPU time 14.39 seconds
Started May 28 02:46:44 PM PDT 24
Finished May 28 02:47:15 PM PDT 24
Peak memory 225960 kb
Host smart-d11d231e-1e20-4acf-936a-3e4cb07182de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445988072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.3445988072
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.2145505243
Short name T799
Test name
Test status
Simulation time 591499390 ps
CPU time 9.98 seconds
Started May 28 02:46:44 PM PDT 24
Finished May 28 02:47:10 PM PDT 24
Peak memory 217836 kb
Host smart-5b4e53f8-c8f5-4db3-ab4b-d860531d51b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145505243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.2145505243
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.10688736
Short name T681
Test name
Test status
Simulation time 377886142 ps
CPU time 10.32 seconds
Started May 28 02:46:43 PM PDT 24
Finished May 28 02:47:10 PM PDT 24
Peak memory 217916 kb
Host smart-aa259806-6e06-40e9-99e6-898e513f9472
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10688736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.10688736
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.4078783795
Short name T411
Test name
Test status
Simulation time 4096857955 ps
CPU time 14.12 seconds
Started May 28 02:46:43 PM PDT 24
Finished May 28 02:47:14 PM PDT 24
Peak memory 226084 kb
Host smart-ca2262c7-51c5-4b35-bd07-08aa48bba1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078783795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.4078783795
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.4121285015
Short name T496
Test name
Test status
Simulation time 35371825 ps
CPU time 2.2 seconds
Started May 28 02:46:41 PM PDT 24
Finished May 28 02:46:59 PM PDT 24
Peak memory 213696 kb
Host smart-25792514-3fdf-47d6-8cd6-5a5a0a107689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121285015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.4121285015
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3844834679
Short name T755
Test name
Test status
Simulation time 652201701 ps
CPU time 24.13 seconds
Started May 28 02:46:47 PM PDT 24
Finished May 28 02:47:26 PM PDT 24
Peak memory 250728 kb
Host smart-43143e91-60a6-4d4a-bc94-cd078d677af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844834679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3844834679
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.3673563629
Short name T275
Test name
Test status
Simulation time 379569191 ps
CPU time 7.62 seconds
Started May 28 02:46:44 PM PDT 24
Finished May 28 02:47:08 PM PDT 24
Peak memory 250268 kb
Host smart-7bd711af-6e6b-4a71-b2de-f8a87e7b2526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673563629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.3673563629
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3456236966
Short name T437
Test name
Test status
Simulation time 10100731719 ps
CPU time 150.76 seconds
Started May 28 02:46:43 PM PDT 24
Finished May 28 02:49:31 PM PDT 24
Peak memory 250952 kb
Host smart-3e27a3a9-ea28-4915-b881-db70810c188a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456236966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3456236966
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.805942000
Short name T712
Test name
Test status
Simulation time 42446965 ps
CPU time 0.9 seconds
Started May 28 02:46:43 PM PDT 24
Finished May 28 02:47:01 PM PDT 24
Peak memory 211496 kb
Host smart-27ad3093-5d56-47db-b106-010b2d6dd847
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805942000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctr
l_volatile_unlock_smoke.805942000
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.4254681443
Short name T723
Test name
Test status
Simulation time 88457708 ps
CPU time 1.1 seconds
Started May 28 02:48:33 PM PDT 24
Finished May 28 02:48:39 PM PDT 24
Peak memory 209424 kb
Host smart-fadf071e-4492-4993-ba62-57a060a70962
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254681443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.4254681443
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.734810842
Short name T449
Test name
Test status
Simulation time 229921627 ps
CPU time 10.87 seconds
Started May 28 02:48:32 PM PDT 24
Finished May 28 02:48:47 PM PDT 24
Peak memory 217900 kb
Host smart-d5a68d51-e6a9-49b5-81a0-ce52bc3fdb23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734810842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.734810842
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.334306165
Short name T484
Test name
Test status
Simulation time 115428551 ps
CPU time 1.16 seconds
Started May 28 02:48:33 PM PDT 24
Finished May 28 02:48:38 PM PDT 24
Peak memory 216788 kb
Host smart-6524dce9-3f3e-4953-8fec-7c336aea033a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334306165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.334306165
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3079314082
Short name T231
Test name
Test status
Simulation time 343479637 ps
CPU time 3.92 seconds
Started May 28 02:48:31 PM PDT 24
Finished May 28 02:48:38 PM PDT 24
Peak memory 217936 kb
Host smart-fd55bc90-ac68-40e8-98dd-c384b6aa7eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079314082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3079314082
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2302327613
Short name T602
Test name
Test status
Simulation time 2980024903 ps
CPU time 22.28 seconds
Started May 28 02:48:37 PM PDT 24
Finished May 28 02:49:05 PM PDT 24
Peak memory 226084 kb
Host smart-583655b0-a186-4f00-9998-1b29242212b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302327613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2302327613
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1231148351
Short name T791
Test name
Test status
Simulation time 1123710331 ps
CPU time 7.65 seconds
Started May 28 02:48:33 PM PDT 24
Finished May 28 02:48:44 PM PDT 24
Peak memory 217868 kb
Host smart-90170460-dbb0-45f7-b828-4a69d907a849
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231148351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1231148351
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2506173746
Short name T398
Test name
Test status
Simulation time 440291099 ps
CPU time 16.4 seconds
Started May 28 02:48:31 PM PDT 24
Finished May 28 02:48:51 PM PDT 24
Peak memory 217936 kb
Host smart-e188fe9a-9134-4724-bba2-3d7b12807e0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506173746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
2506173746
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.4063660465
Short name T672
Test name
Test status
Simulation time 1436896296 ps
CPU time 9.1 seconds
Started May 28 02:48:32 PM PDT 24
Finished May 28 02:48:46 PM PDT 24
Peak memory 218012 kb
Host smart-0be41b64-0d7d-40ce-be3f-cb1cbf619e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063660465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.4063660465
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.3156012088
Short name T309
Test name
Test status
Simulation time 279771607 ps
CPU time 3.57 seconds
Started May 28 02:48:35 PM PDT 24
Finished May 28 02:48:43 PM PDT 24
Peak memory 217780 kb
Host smart-c1ea00a9-920e-4307-a37f-0a727a3e0d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156012088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.3156012088
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1485628543
Short name T508
Test name
Test status
Simulation time 462752985 ps
CPU time 25.51 seconds
Started May 28 02:48:30 PM PDT 24
Finished May 28 02:48:59 PM PDT 24
Peak memory 250728 kb
Host smart-f4addd8a-f80a-42af-aa8a-43aaf04db08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485628543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1485628543
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1045149290
Short name T1
Test name
Test status
Simulation time 408210690 ps
CPU time 3.94 seconds
Started May 28 02:48:38 PM PDT 24
Finished May 28 02:48:47 PM PDT 24
Peak memory 226180 kb
Host smart-d4c9c3c1-626c-4200-8e7e-23c817717585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045149290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1045149290
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1055042083
Short name T276
Test name
Test status
Simulation time 3515075132 ps
CPU time 129.35 seconds
Started May 28 02:48:36 PM PDT 24
Finished May 28 02:50:51 PM PDT 24
Peak memory 421884 kb
Host smart-806071c6-0550-4873-b4cf-2712c68a2a62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055042083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1055042083
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.2125155455
Short name T849
Test name
Test status
Simulation time 149795337628 ps
CPU time 963.63 seconds
Started May 28 02:48:40 PM PDT 24
Finished May 28 03:04:49 PM PDT 24
Peak memory 496852 kb
Host smart-673a2d57-4568-40f8-922a-bb0ebff09240
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2125155455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.2125155455
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.516893113
Short name T387
Test name
Test status
Simulation time 20779716 ps
CPU time 0.83 seconds
Started May 28 02:48:30 PM PDT 24
Finished May 28 02:48:34 PM PDT 24
Peak memory 211464 kb
Host smart-d014b076-785d-443c-a555-ed8c835eab63
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516893113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.516893113
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.714858327
Short name T733
Test name
Test status
Simulation time 24883695 ps
CPU time 1.28 seconds
Started May 28 02:48:37 PM PDT 24
Finished May 28 02:48:44 PM PDT 24
Peak memory 209416 kb
Host smart-b43e0bf7-6f96-4ec0-879b-ac7195926249
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714858327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.714858327
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.442200477
Short name T526
Test name
Test status
Simulation time 1314588602 ps
CPU time 14.14 seconds
Started May 28 02:48:37 PM PDT 24
Finished May 28 02:48:57 PM PDT 24
Peak memory 217856 kb
Host smart-7c0f4363-0d82-45f6-abe8-88c79f451834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442200477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.442200477
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.2300659585
Short name T347
Test name
Test status
Simulation time 170574938 ps
CPU time 5.04 seconds
Started May 28 02:48:34 PM PDT 24
Finished May 28 02:48:44 PM PDT 24
Peak memory 216800 kb
Host smart-8539acec-2297-4f60-80a3-0878290d3cf8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300659585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.2300659585
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.4199594739
Short name T184
Test name
Test status
Simulation time 40193067 ps
CPU time 2.28 seconds
Started May 28 02:48:32 PM PDT 24
Finished May 28 02:48:38 PM PDT 24
Peak memory 217860 kb
Host smart-e3e4975c-76d3-4433-a229-4a75e0e88bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199594739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.4199594739
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.2351572931
Short name T769
Test name
Test status
Simulation time 1985985540 ps
CPU time 12.44 seconds
Started May 28 02:48:39 PM PDT 24
Finished May 28 02:48:56 PM PDT 24
Peak memory 218776 kb
Host smart-859ceaa5-d1e0-460f-814a-866b7b4b9e67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351572931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.2351572931
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.3948765876
Short name T403
Test name
Test status
Simulation time 659523678 ps
CPU time 12.99 seconds
Started May 28 02:48:35 PM PDT 24
Finished May 28 02:48:53 PM PDT 24
Peak memory 225944 kb
Host smart-29348d95-35e8-4cfc-aafa-ad426eaeddb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948765876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.3948765876
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3175557884
Short name T524
Test name
Test status
Simulation time 1532589845 ps
CPU time 14.55 seconds
Started May 28 02:48:35 PM PDT 24
Finished May 28 02:48:54 PM PDT 24
Peak memory 217864 kb
Host smart-1ba1963e-bfc3-44c5-a140-7f7173e9408d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175557884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3175557884
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.3488289704
Short name T779
Test name
Test status
Simulation time 1338908280 ps
CPU time 10.41 seconds
Started May 28 02:48:32 PM PDT 24
Finished May 28 02:48:47 PM PDT 24
Peak memory 225264 kb
Host smart-51123a92-1a1c-4518-8e54-deb0a076a859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488289704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.3488289704
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2484008546
Short name T442
Test name
Test status
Simulation time 50324849 ps
CPU time 1.75 seconds
Started May 28 02:48:38 PM PDT 24
Finished May 28 02:48:45 PM PDT 24
Peak memory 213632 kb
Host smart-249d1360-1a2c-4ab3-945c-ef95e3d60804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484008546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2484008546
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.3463467282
Short name T698
Test name
Test status
Simulation time 1357120727 ps
CPU time 29.34 seconds
Started May 28 02:48:31 PM PDT 24
Finished May 28 02:49:05 PM PDT 24
Peak memory 250796 kb
Host smart-43e2522f-b754-455d-bde7-228295876e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463467282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3463467282
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2665942536
Short name T237
Test name
Test status
Simulation time 264691666 ps
CPU time 7.06 seconds
Started May 28 02:48:38 PM PDT 24
Finished May 28 02:48:50 PM PDT 24
Peak memory 250840 kb
Host smart-fd558fd9-494c-4f36-b4a8-a8a03ce155e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665942536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2665942536
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.713901915
Short name T598
Test name
Test status
Simulation time 3036670079 ps
CPU time 51.91 seconds
Started May 28 02:48:32 PM PDT 24
Finished May 28 02:49:29 PM PDT 24
Peak memory 226084 kb
Host smart-5f205533-8546-442d-9db8-4d17d11ac38d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713901915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.713901915
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.907518210
Short name T788
Test name
Test status
Simulation time 30456263139 ps
CPU time 648.38 seconds
Started May 28 02:48:32 PM PDT 24
Finished May 28 02:59:25 PM PDT 24
Peak memory 283804 kb
Host smart-ab9dcb80-8fdd-464d-8c14-3581ca4df2cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=907518210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.907518210
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1972659999
Short name T234
Test name
Test status
Simulation time 19232422 ps
CPU time 0.98 seconds
Started May 28 02:48:38 PM PDT 24
Finished May 28 02:48:45 PM PDT 24
Peak memory 211588 kb
Host smart-c1331e09-af31-4fe2-929d-8b649eafc663
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972659999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1972659999
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.546826148
Short name T90
Test name
Test status
Simulation time 23746490 ps
CPU time 1.24 seconds
Started May 28 02:48:34 PM PDT 24
Finished May 28 02:48:40 PM PDT 24
Peak memory 209408 kb
Host smart-80fb1ea3-7107-435e-bc09-fc4cf33616d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546826148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.546826148
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.4252041693
Short name T338
Test name
Test status
Simulation time 2041349046 ps
CPU time 14.25 seconds
Started May 28 02:48:38 PM PDT 24
Finished May 28 02:48:57 PM PDT 24
Peak memory 217676 kb
Host smart-0b9aa358-ef15-4ec3-a362-d7e87615cfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252041693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.4252041693
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1533639609
Short name T441
Test name
Test status
Simulation time 120816179 ps
CPU time 2.48 seconds
Started May 28 02:48:37 PM PDT 24
Finished May 28 02:48:45 PM PDT 24
Peak memory 209420 kb
Host smart-3713f6f8-77be-4418-a32c-aa9d6a2322f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533639609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1533639609
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.494900959
Short name T259
Test name
Test status
Simulation time 51504886 ps
CPU time 2.42 seconds
Started May 28 02:48:38 PM PDT 24
Finished May 28 02:48:46 PM PDT 24
Peak memory 217928 kb
Host smart-54a9e543-1cdb-49d9-86a6-5ab8693d6940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494900959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.494900959
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.757015883
Short name T845
Test name
Test status
Simulation time 452678251 ps
CPU time 18.96 seconds
Started May 28 02:48:33 PM PDT 24
Finished May 28 02:48:57 PM PDT 24
Peak memory 218808 kb
Host smart-500e26f8-9b08-440c-af1a-c14a066dcf29
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757015883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.757015883
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2201089587
Short name T334
Test name
Test status
Simulation time 609244561 ps
CPU time 12.3 seconds
Started May 28 02:48:41 PM PDT 24
Finished May 28 02:49:00 PM PDT 24
Peak memory 217868 kb
Host smart-20aa81c4-8688-45d6-9e37-317dea37f9b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201089587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2201089587
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.216900398
Short name T319
Test name
Test status
Simulation time 694923307 ps
CPU time 12.83 seconds
Started May 28 02:48:33 PM PDT 24
Finished May 28 02:48:50 PM PDT 24
Peak memory 217936 kb
Host smart-6f4b93dc-9a0e-44a7-a0f1-9ab212a193e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216900398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.216900398
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.2937799749
Short name T56
Test name
Test status
Simulation time 1833626121 ps
CPU time 9.27 seconds
Started May 28 02:48:43 PM PDT 24
Finished May 28 02:48:59 PM PDT 24
Peak memory 217916 kb
Host smart-6b2d7ffe-3eeb-4ad3-b544-267cfbc0f48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937799749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.2937799749
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.1248808633
Short name T421
Test name
Test status
Simulation time 75303028 ps
CPU time 1.24 seconds
Started May 28 02:48:31 PM PDT 24
Finished May 28 02:48:37 PM PDT 24
Peak memory 213352 kb
Host smart-3e471259-1966-434c-85c8-940f9214bea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248808633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.1248808633
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3127546718
Short name T272
Test name
Test status
Simulation time 248703737 ps
CPU time 31.23 seconds
Started May 28 02:48:34 PM PDT 24
Finished May 28 02:49:10 PM PDT 24
Peak memory 250836 kb
Host smart-aea3b2e9-670b-4702-9f5b-1198b915d383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127546718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3127546718
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3510423660
Short name T342
Test name
Test status
Simulation time 94434927 ps
CPU time 11.32 seconds
Started May 28 02:48:32 PM PDT 24
Finished May 28 02:48:48 PM PDT 24
Peak memory 250844 kb
Host smart-e9f4d8e0-1c35-4be0-94ef-c29db9a210b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510423660 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3510423660
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.3262096742
Short name T867
Test name
Test status
Simulation time 3476406454 ps
CPU time 195.57 seconds
Started May 28 02:48:35 PM PDT 24
Finished May 28 02:51:56 PM PDT 24
Peak memory 250976 kb
Host smart-c7c34438-5242-4730-b78b-2a039cbde413
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262096742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.3262096742
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3336915234
Short name T476
Test name
Test status
Simulation time 12480979 ps
CPU time 0.96 seconds
Started May 28 02:48:37 PM PDT 24
Finished May 28 02:48:44 PM PDT 24
Peak memory 211276 kb
Host smart-b675a8b8-e5f1-4d26-8211-20dc31010611
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336915234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.3336915234
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2022678714
Short name T785
Test name
Test status
Simulation time 42831852 ps
CPU time 1.09 seconds
Started May 28 02:48:51 PM PDT 24
Finished May 28 02:48:59 PM PDT 24
Peak memory 209352 kb
Host smart-d414edf5-fad7-4629-979a-def0835ba5c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022678714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2022678714
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2813384231
Short name T653
Test name
Test status
Simulation time 625593990 ps
CPU time 11.94 seconds
Started May 28 02:48:42 PM PDT 24
Finished May 28 02:49:01 PM PDT 24
Peak memory 217916 kb
Host smart-5849d34e-cfa9-459f-b8ec-a52e534e6525
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813384231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2813384231
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3685158703
Short name T525
Test name
Test status
Simulation time 2686520560 ps
CPU time 16.89 seconds
Started May 28 02:48:34 PM PDT 24
Finished May 28 02:48:55 PM PDT 24
Peak memory 209564 kb
Host smart-86394411-cddc-4c18-9053-910cfa8dd0dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685158703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3685158703
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.3402972571
Short name T61
Test name
Test status
Simulation time 133561369 ps
CPU time 1.96 seconds
Started May 28 02:48:37 PM PDT 24
Finished May 28 02:48:44 PM PDT 24
Peak memory 217892 kb
Host smart-6a3ed5d7-dfc2-433b-adfd-e38102645c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402972571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.3402972571
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2959910781
Short name T328
Test name
Test status
Simulation time 1536830326 ps
CPU time 10.97 seconds
Started May 28 02:48:32 PM PDT 24
Finished May 28 02:48:48 PM PDT 24
Peak memory 225960 kb
Host smart-cd9a7302-c2cc-4c42-a5fb-40d9c236ea6a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959910781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2959910781
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3396888404
Short name T613
Test name
Test status
Simulation time 1947756752 ps
CPU time 13.98 seconds
Started May 28 02:48:42 PM PDT 24
Finished May 28 02:49:03 PM PDT 24
Peak memory 217856 kb
Host smart-8b0c819e-c55b-4059-931e-5b9ea3106feb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396888404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3396888404
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.2604262216
Short name T155
Test name
Test status
Simulation time 3426629195 ps
CPU time 11.49 seconds
Started May 28 02:48:34 PM PDT 24
Finished May 28 02:48:50 PM PDT 24
Peak memory 218000 kb
Host smart-264eecf7-a693-4ac2-8121-e6223c818244
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604262216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
2604262216
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.200519155
Short name T60
Test name
Test status
Simulation time 113040957 ps
CPU time 2.55 seconds
Started May 28 02:48:40 PM PDT 24
Finished May 28 02:48:48 PM PDT 24
Peak memory 213760 kb
Host smart-3e061f9a-a813-4898-b304-bc0825169eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200519155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.200519155
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3117687436
Short name T801
Test name
Test status
Simulation time 390423263 ps
CPU time 23.33 seconds
Started May 28 02:48:43 PM PDT 24
Finished May 28 02:49:13 PM PDT 24
Peak memory 250844 kb
Host smart-05fc2bc9-3022-4eb4-b4c1-3ab37725ccdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117687436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3117687436
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2508584075
Short name T666
Test name
Test status
Simulation time 156850574 ps
CPU time 8.35 seconds
Started May 28 02:48:34 PM PDT 24
Finished May 28 02:48:46 PM PDT 24
Peak memory 246956 kb
Host smart-963d5ab5-9120-456f-9e88-479b634a607f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508584075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2508584075
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2226638401
Short name T299
Test name
Test status
Simulation time 4281091596 ps
CPU time 76.52 seconds
Started May 28 02:48:36 PM PDT 24
Finished May 28 02:49:58 PM PDT 24
Peak memory 279752 kb
Host smart-0281f328-f468-4faa-8d12-45caf2fdc600
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226638401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2226638401
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.2464321405
Short name T175
Test name
Test status
Simulation time 38832460414 ps
CPU time 672.82 seconds
Started May 28 02:48:43 PM PDT 24
Finished May 28 03:00:03 PM PDT 24
Peak memory 275612 kb
Host smart-8ef967cf-ddcf-4bfe-831b-3cd7e1939f27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2464321405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.2464321405
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2877248815
Short name T583
Test name
Test status
Simulation time 13427866 ps
CPU time 1.05 seconds
Started May 28 02:48:39 PM PDT 24
Finished May 28 02:48:46 PM PDT 24
Peak memory 211604 kb
Host smart-73d1e90f-8093-4dd8-aea6-7edc1489213f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877248815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2877248815
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.2934539904
Short name T522
Test name
Test status
Simulation time 74903751 ps
CPU time 0.95 seconds
Started May 28 02:48:41 PM PDT 24
Finished May 28 02:48:49 PM PDT 24
Peak memory 209424 kb
Host smart-0f0ae455-5dc0-4a81-b5a1-d12d1289b2d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934539904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.2934539904
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1339322631
Short name T255
Test name
Test status
Simulation time 1325907545 ps
CPU time 14.16 seconds
Started May 28 02:48:41 PM PDT 24
Finished May 28 02:49:02 PM PDT 24
Peak memory 217848 kb
Host smart-2dfa6b6a-7b02-4467-9c6c-25f3741a2685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339322631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1339322631
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1009392458
Short name T719
Test name
Test status
Simulation time 499185330 ps
CPU time 12 seconds
Started May 28 02:48:46 PM PDT 24
Finished May 28 02:49:04 PM PDT 24
Peak memory 209440 kb
Host smart-813f0bee-b86f-45f9-bc2a-0943e8d77235
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009392458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1009392458
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.627263367
Short name T827
Test name
Test status
Simulation time 322554031 ps
CPU time 3.92 seconds
Started May 28 02:48:49 PM PDT 24
Finished May 28 02:48:58 PM PDT 24
Peak memory 217920 kb
Host smart-70bead2a-d485-4460-adcb-bb29cf33877c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627263367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.627263367
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1559445335
Short name T502
Test name
Test status
Simulation time 809209683 ps
CPU time 11.93 seconds
Started May 28 02:48:51 PM PDT 24
Finished May 28 02:49:09 PM PDT 24
Peak memory 218732 kb
Host smart-9453e9ab-574a-4ab9-aec6-9f78939f6207
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559445335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1559445335
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.113509600
Short name T18
Test name
Test status
Simulation time 450082275 ps
CPU time 16.65 seconds
Started May 28 02:48:44 PM PDT 24
Finished May 28 02:49:07 PM PDT 24
Peak memory 225932 kb
Host smart-ea41aee5-7d3f-42c7-aa96-86bf3653cd08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113509600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.113509600
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2651804783
Short name T687
Test name
Test status
Simulation time 589427495 ps
CPU time 12.38 seconds
Started May 28 02:48:39 PM PDT 24
Finished May 28 02:48:58 PM PDT 24
Peak memory 217864 kb
Host smart-0a80be66-e3cf-46b9-a43c-f75e1bc1ae4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651804783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2651804783
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.1490692072
Short name T775
Test name
Test status
Simulation time 5418417134 ps
CPU time 9.72 seconds
Started May 28 02:48:46 PM PDT 24
Finished May 28 02:49:02 PM PDT 24
Peak memory 218048 kb
Host smart-a51f676f-9746-4e4a-8148-c282139351ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490692072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.1490692072
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.3363980597
Short name T67
Test name
Test status
Simulation time 750771606 ps
CPU time 3.45 seconds
Started May 28 02:48:41 PM PDT 24
Finished May 28 02:48:51 PM PDT 24
Peak memory 217632 kb
Host smart-716cc574-d9e7-4181-a249-89d410d66b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363980597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.3363980597
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1911018495
Short name T840
Test name
Test status
Simulation time 1395631858 ps
CPU time 28.11 seconds
Started May 28 02:48:40 PM PDT 24
Finished May 28 02:49:15 PM PDT 24
Peak memory 250816 kb
Host smart-92611590-e014-438f-88a7-c520d42ead46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911018495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1911018495
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1794478525
Short name T455
Test name
Test status
Simulation time 114847462 ps
CPU time 3.41 seconds
Started May 28 02:48:42 PM PDT 24
Finished May 28 02:48:53 PM PDT 24
Peak memory 217532 kb
Host smart-883653e1-46ea-4ec3-aac9-5a432acaae39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794478525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1794478525
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2052569520
Short name T45
Test name
Test status
Simulation time 9244496765 ps
CPU time 81.33 seconds
Started May 28 02:48:41 PM PDT 24
Finished May 28 02:50:09 PM PDT 24
Peak memory 252972 kb
Host smart-0a9de9ee-12ba-47d6-a9ea-0ef8fd3db6dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052569520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2052569520
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1052434746
Short name T774
Test name
Test status
Simulation time 31523621 ps
CPU time 0.92 seconds
Started May 28 02:48:42 PM PDT 24
Finished May 28 02:48:50 PM PDT 24
Peak memory 211444 kb
Host smart-50d30d8c-1512-40b1-aef8-241f8cf835f7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052434746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.1052434746
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.4136457261
Short name T355
Test name
Test status
Simulation time 18870735 ps
CPU time 0.96 seconds
Started May 28 02:48:51 PM PDT 24
Finished May 28 02:48:58 PM PDT 24
Peak memory 209364 kb
Host smart-fac133c0-be76-495c-85be-7168c50ac3bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136457261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.4136457261
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1071467406
Short name T777
Test name
Test status
Simulation time 1390475187 ps
CPU time 16.12 seconds
Started May 28 02:48:42 PM PDT 24
Finished May 28 02:49:05 PM PDT 24
Peak memory 217824 kb
Host smart-a23b04c6-a8d9-4c61-9546-7b1dc4cb711b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071467406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1071467406
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3999944720
Short name T620
Test name
Test status
Simulation time 4044376223 ps
CPU time 4.95 seconds
Started May 28 02:48:43 PM PDT 24
Finished May 28 02:48:55 PM PDT 24
Peak memory 209524 kb
Host smart-f1155de4-a7fe-46c3-a69d-ce57d9c626c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999944720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3999944720
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.3723994924
Short name T701
Test name
Test status
Simulation time 315237555 ps
CPU time 2.06 seconds
Started May 28 02:48:45 PM PDT 24
Finished May 28 02:48:53 PM PDT 24
Peak memory 217852 kb
Host smart-5c0fbaab-f3cf-49de-9241-92ecd63e05b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723994924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.3723994924
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.973848919
Short name T158
Test name
Test status
Simulation time 273239047 ps
CPU time 10.72 seconds
Started May 28 02:48:46 PM PDT 24
Finished May 28 02:49:03 PM PDT 24
Peak memory 225948 kb
Host smart-3f7a8e74-7889-4b31-bf4e-eb6fa7fcc7fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973848919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.973848919
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.658071724
Short name T326
Test name
Test status
Simulation time 3685015829 ps
CPU time 8.92 seconds
Started May 28 02:48:41 PM PDT 24
Finished May 28 02:48:56 PM PDT 24
Peak memory 217988 kb
Host smart-80ae1086-7f71-4c48-923e-6da5e52d3d55
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658071724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.658071724
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.552015096
Short name T17
Test name
Test status
Simulation time 2244916229 ps
CPU time 11.33 seconds
Started May 28 02:48:45 PM PDT 24
Finished May 28 02:49:02 PM PDT 24
Peak memory 217992 kb
Host smart-8359d5fc-eba6-47ab-8474-529982a0eae6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552015096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.552015096
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3841653364
Short name T218
Test name
Test status
Simulation time 413860890 ps
CPU time 9.67 seconds
Started May 28 02:48:41 PM PDT 24
Finished May 28 02:48:58 PM PDT 24
Peak memory 217920 kb
Host smart-eb259e02-16b7-4a97-95ce-e7b582b79ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841653364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3841653364
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.819891613
Short name T811
Test name
Test status
Simulation time 21981010 ps
CPU time 1.28 seconds
Started May 28 02:48:50 PM PDT 24
Finished May 28 02:48:58 PM PDT 24
Peak memory 217564 kb
Host smart-7bf1e6b2-e25a-43b1-8de0-df954d00a6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819891613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.819891613
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.4019159273
Short name T335
Test name
Test status
Simulation time 1097708736 ps
CPU time 30.31 seconds
Started May 28 02:48:51 PM PDT 24
Finished May 28 02:49:28 PM PDT 24
Peak memory 250868 kb
Host smart-70eda20e-ad1d-4a4a-8249-69d927942e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019159273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.4019159273
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2666278266
Short name T357
Test name
Test status
Simulation time 865949783 ps
CPU time 6.35 seconds
Started May 28 02:48:51 PM PDT 24
Finished May 28 02:49:03 PM PDT 24
Peak memory 245304 kb
Host smart-4e258980-c64f-4d5c-b537-50f98223241d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666278266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2666278266
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.2479459639
Short name T435
Test name
Test status
Simulation time 1861141413 ps
CPU time 46.7 seconds
Started May 28 02:48:43 PM PDT 24
Finished May 28 02:49:36 PM PDT 24
Peak memory 267452 kb
Host smart-45d2ab32-f5f5-4ca7-92fd-b74bd02d47bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479459639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.2479459639
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3599925498
Short name T225
Test name
Test status
Simulation time 82725920 ps
CPU time 1.01 seconds
Started May 28 02:48:47 PM PDT 24
Finished May 28 02:48:54 PM PDT 24
Peak memory 211488 kb
Host smart-8a8b8769-61b1-4b08-83b8-ad25ce74b331
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599925498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.3599925498
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1583574363
Short name T651
Test name
Test status
Simulation time 23650603 ps
CPU time 1.01 seconds
Started May 28 02:48:40 PM PDT 24
Finished May 28 02:48:47 PM PDT 24
Peak memory 209424 kb
Host smart-abfe15db-b757-46e2-bcd9-8464035fa03c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583574363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1583574363
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3632709614
Short name T306
Test name
Test status
Simulation time 1166412671 ps
CPU time 9.49 seconds
Started May 28 02:48:41 PM PDT 24
Finished May 28 02:48:56 PM PDT 24
Peak memory 217856 kb
Host smart-f38796f6-e0a8-4159-9f30-7dca0d1d52ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632709614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3632709614
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.2291396644
Short name T489
Test name
Test status
Simulation time 306052743 ps
CPU time 2.74 seconds
Started May 28 02:48:51 PM PDT 24
Finished May 28 02:49:00 PM PDT 24
Peak memory 216728 kb
Host smart-0f37dfc6-b079-4253-9b4e-882dcd5cb56c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291396644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2291396644
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3001934174
Short name T318
Test name
Test status
Simulation time 319542205 ps
CPU time 3.23 seconds
Started May 28 02:48:41 PM PDT 24
Finished May 28 02:48:51 PM PDT 24
Peak memory 217860 kb
Host smart-f7c3c58d-81e7-469c-8aa8-fca18a16475e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001934174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3001934174
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2793407723
Short name T628
Test name
Test status
Simulation time 496527387 ps
CPU time 10.85 seconds
Started May 28 02:48:47 PM PDT 24
Finished May 28 02:49:03 PM PDT 24
Peak memory 225896 kb
Host smart-6fc359f0-7ed1-42f2-a157-5b271c280fc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793407723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2793407723
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.408435082
Short name T810
Test name
Test status
Simulation time 840463682 ps
CPU time 9.99 seconds
Started May 28 02:48:40 PM PDT 24
Finished May 28 02:48:57 PM PDT 24
Peak memory 217852 kb
Host smart-3094c0f4-c84a-40a1-a941-f846ebce4465
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408435082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di
gest.408435082
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.2217469285
Short name T377
Test name
Test status
Simulation time 2902365042 ps
CPU time 7.93 seconds
Started May 28 02:48:51 PM PDT 24
Finished May 28 02:49:05 PM PDT 24
Peak memory 217924 kb
Host smart-d05b07b9-6086-4827-a4c1-244b8110274f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217469285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
2217469285
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.2816774996
Short name T291
Test name
Test status
Simulation time 1001028154 ps
CPU time 9.71 seconds
Started May 28 02:48:42 PM PDT 24
Finished May 28 02:48:58 PM PDT 24
Peak memory 217988 kb
Host smart-bf68cd59-4da6-4487-b082-40d5c1f0780f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816774996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.2816774996
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3584444426
Short name T541
Test name
Test status
Simulation time 25736549 ps
CPU time 1.44 seconds
Started May 28 02:48:46 PM PDT 24
Finished May 28 02:48:53 PM PDT 24
Peak memory 217768 kb
Host smart-7a2e81ea-54f6-4126-98f1-1076630a1764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584444426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3584444426
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.2922967793
Short name T618
Test name
Test status
Simulation time 1279597668 ps
CPU time 29.11 seconds
Started May 28 02:48:47 PM PDT 24
Finished May 28 02:49:22 PM PDT 24
Peak memory 250728 kb
Host smart-7e91bb5b-076f-4a04-8102-19a0282ca151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922967793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.2922967793
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.923092671
Short name T366
Test name
Test status
Simulation time 155862479 ps
CPU time 6.7 seconds
Started May 28 02:48:45 PM PDT 24
Finished May 28 02:48:58 PM PDT 24
Peak memory 242652 kb
Host smart-d88a1aa0-8238-416d-b67d-5f176f4cac49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923092671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.923092671
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.3752938351
Short name T587
Test name
Test status
Simulation time 902151456 ps
CPU time 26.2 seconds
Started May 28 02:48:41 PM PDT 24
Finished May 28 02:49:14 PM PDT 24
Peak memory 247216 kb
Host smart-af12d2d8-9064-465c-9725-82c77b60165c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752938351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.3752938351
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3889155380
Short name T215
Test name
Test status
Simulation time 35441958 ps
CPU time 0.83 seconds
Started May 28 02:48:42 PM PDT 24
Finished May 28 02:48:50 PM PDT 24
Peak memory 211468 kb
Host smart-b69801e3-d722-4efb-bb8b-ab6df7450a48
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889155380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3889155380
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2440441812
Short name T812
Test name
Test status
Simulation time 29016434 ps
CPU time 1.21 seconds
Started May 28 02:48:55 PM PDT 24
Finished May 28 02:49:04 PM PDT 24
Peak memory 209420 kb
Host smart-62064d1b-7080-4458-8a0d-ab791f187c26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440441812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2440441812
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2734564340
Short name T689
Test name
Test status
Simulation time 344553184 ps
CPU time 11.22 seconds
Started May 28 02:48:47 PM PDT 24
Finished May 28 02:49:04 PM PDT 24
Peak memory 217856 kb
Host smart-6aa6a24b-711c-4524-bb63-aed2f2782f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734564340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2734564340
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1785688956
Short name T758
Test name
Test status
Simulation time 203066598 ps
CPU time 4.71 seconds
Started May 28 02:48:42 PM PDT 24
Finished May 28 02:48:54 PM PDT 24
Peak memory 209192 kb
Host smart-899be217-280c-4fc4-bc7a-0b4f71a2a5fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785688956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.1785688956
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.670234201
Short name T404
Test name
Test status
Simulation time 190726184 ps
CPU time 2.4 seconds
Started May 28 02:48:45 PM PDT 24
Finished May 28 02:48:53 PM PDT 24
Peak memory 217888 kb
Host smart-6be5660b-f658-4e62-9c84-6377bfe03797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670234201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.670234201
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.899141888
Short name T277
Test name
Test status
Simulation time 612213828 ps
CPU time 13.5 seconds
Started May 28 02:48:45 PM PDT 24
Finished May 28 02:49:04 PM PDT 24
Peak memory 217836 kb
Host smart-7dcb7985-28de-4b1e-a1eb-7219c2f4167e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899141888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.899141888
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.660717769
Short name T268
Test name
Test status
Simulation time 741501796 ps
CPU time 8.41 seconds
Started May 28 02:48:40 PM PDT 24
Finished May 28 02:48:55 PM PDT 24
Peak memory 217860 kb
Host smart-b50c232a-c98d-4195-8fc8-767e90929bea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660717769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.660717769
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1484587659
Short name T320
Test name
Test status
Simulation time 380985193 ps
CPU time 13.09 seconds
Started May 28 02:48:44 PM PDT 24
Finished May 28 02:49:04 PM PDT 24
Peak memory 217920 kb
Host smart-512d6e95-d5ca-4f01-9ab3-c6b554659e4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484587659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1484587659
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.4167338074
Short name T384
Test name
Test status
Simulation time 1354412598 ps
CPU time 11.62 seconds
Started May 28 02:48:45 PM PDT 24
Finished May 28 02:49:03 PM PDT 24
Peak memory 217916 kb
Host smart-a1fa3663-315d-4347-b944-af76718b7480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167338074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.4167338074
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.2607429593
Short name T325
Test name
Test status
Simulation time 36472956 ps
CPU time 2.65 seconds
Started May 28 02:48:46 PM PDT 24
Finished May 28 02:48:55 PM PDT 24
Peak memory 213956 kb
Host smart-50ac0e70-3218-4ea9-9cca-9fdd0c17c0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607429593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.2607429593
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1509704709
Short name T581
Test name
Test status
Simulation time 218302882 ps
CPU time 25.75 seconds
Started May 28 02:48:44 PM PDT 24
Finished May 28 02:49:16 PM PDT 24
Peak memory 250828 kb
Host smart-a0d94a42-1740-4106-ac33-12523616081f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509704709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1509704709
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2673940232
Short name T736
Test name
Test status
Simulation time 1016999281 ps
CPU time 4.08 seconds
Started May 28 02:48:42 PM PDT 24
Finished May 28 02:48:54 PM PDT 24
Peak memory 226256 kb
Host smart-c5fb37c9-189a-42da-8b8d-4752caead01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673940232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2673940232
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.1263915706
Short name T367
Test name
Test status
Simulation time 30162541002 ps
CPU time 48.82 seconds
Started May 28 02:48:42 PM PDT 24
Finished May 28 02:49:38 PM PDT 24
Peak memory 276004 kb
Host smart-92bcd016-005a-44a9-9aa5-7cdd584753b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263915706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.1263915706
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2351698184
Short name T376
Test name
Test status
Simulation time 21969573 ps
CPU time 0.94 seconds
Started May 28 02:48:47 PM PDT 24
Finished May 28 02:48:54 PM PDT 24
Peak memory 211380 kb
Host smart-039256ab-bd9d-4e05-992a-864f99bfdbe1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351698184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2351698184
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.3220408736
Short name T279
Test name
Test status
Simulation time 30582195 ps
CPU time 0.99 seconds
Started May 28 02:48:56 PM PDT 24
Finished May 28 02:49:06 PM PDT 24
Peak memory 209432 kb
Host smart-36d2857f-4697-4516-9edb-9c75d9e5493f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220408736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.3220408736
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.160045253
Short name T96
Test name
Test status
Simulation time 196971897 ps
CPU time 8.63 seconds
Started May 28 02:48:53 PM PDT 24
Finished May 28 02:49:09 PM PDT 24
Peak memory 217928 kb
Host smart-c53af690-3b09-484d-b1ea-d2a0887a49e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160045253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.160045253
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.785864276
Short name T563
Test name
Test status
Simulation time 593634268 ps
CPU time 8.75 seconds
Started May 28 02:48:54 PM PDT 24
Finished May 28 02:49:11 PM PDT 24
Peak memory 216836 kb
Host smart-06887c24-c8f2-4cd3-ab1d-38e0cea17e39
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785864276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.785864276
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3755625094
Short name T611
Test name
Test status
Simulation time 48267702 ps
CPU time 2.45 seconds
Started May 28 02:48:56 PM PDT 24
Finished May 28 02:49:06 PM PDT 24
Peak memory 217852 kb
Host smart-eec11591-6461-4100-bb7f-19972ab78d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755625094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3755625094
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1763426313
Short name T232
Test name
Test status
Simulation time 1216329394 ps
CPU time 13 seconds
Started May 28 02:48:55 PM PDT 24
Finished May 28 02:49:17 PM PDT 24
Peak memory 225940 kb
Host smart-4eef46eb-3d3c-4687-a2a5-9c18781e38f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763426313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1763426313
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3564413329
Short name T808
Test name
Test status
Simulation time 273909899 ps
CPU time 13.3 seconds
Started May 28 02:48:54 PM PDT 24
Finished May 28 02:49:15 PM PDT 24
Peak memory 217860 kb
Host smart-b9eb9258-fd8e-4b77-b218-6542e38fe75b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564413329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3564413329
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3171066837
Short name T472
Test name
Test status
Simulation time 1496325999 ps
CPU time 8.93 seconds
Started May 28 02:48:56 PM PDT 24
Finished May 28 02:49:13 PM PDT 24
Peak memory 217852 kb
Host smart-89525c34-367b-42b8-b12f-13d891e72993
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171066837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3171066837
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3707079995
Short name T51
Test name
Test status
Simulation time 307497424 ps
CPU time 11.7 seconds
Started May 28 02:48:58 PM PDT 24
Finished May 28 02:49:18 PM PDT 24
Peak memory 217940 kb
Host smart-46c40c6a-9d8c-4008-bb5c-edd83e505d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707079995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3707079995
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.2873725002
Short name T381
Test name
Test status
Simulation time 54833268 ps
CPU time 2.88 seconds
Started May 28 02:48:54 PM PDT 24
Finished May 28 02:49:05 PM PDT 24
Peak memory 214256 kb
Host smart-29bbdf09-922f-4b11-9d67-906fcfb0e6b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873725002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.2873725002
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.3635536164
Short name T248
Test name
Test status
Simulation time 4122171788 ps
CPU time 22.78 seconds
Started May 28 02:48:54 PM PDT 24
Finished May 28 02:49:25 PM PDT 24
Peak memory 250832 kb
Host smart-99608e0d-e684-4a8b-89ac-9008246c6415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635536164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.3635536164
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1316357876
Short name T401
Test name
Test status
Simulation time 74627494 ps
CPU time 7.84 seconds
Started May 28 02:48:53 PM PDT 24
Finished May 28 02:49:09 PM PDT 24
Peak memory 250804 kb
Host smart-91d06ee9-7b3a-46c7-ad97-cb54f62692e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316357876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1316357876
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.2954479463
Short name T490
Test name
Test status
Simulation time 6344456290 ps
CPU time 85.21 seconds
Started May 28 02:48:54 PM PDT 24
Finished May 28 02:50:28 PM PDT 24
Peak memory 253148 kb
Host smart-7734dada-e4ea-4191-9942-97fea66bc86a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954479463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.2954479463
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3206048255
Short name T178
Test name
Test status
Simulation time 13731739 ps
CPU time 0.9 seconds
Started May 28 02:48:51 PM PDT 24
Finished May 28 02:48:58 PM PDT 24
Peak memory 211556 kb
Host smart-45dd4c88-4121-43ac-95ca-961547207275
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206048255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3206048255
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.97271308
Short name T564
Test name
Test status
Simulation time 22364309 ps
CPU time 1.12 seconds
Started May 28 02:48:54 PM PDT 24
Finished May 28 02:49:03 PM PDT 24
Peak memory 209396 kb
Host smart-63c0970c-8b2d-47e3-a065-c84360b8c761
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97271308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.97271308
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2284789141
Short name T249
Test name
Test status
Simulation time 364163570 ps
CPU time 10.22 seconds
Started May 28 02:48:55 PM PDT 24
Finished May 28 02:49:14 PM PDT 24
Peak memory 217824 kb
Host smart-c7ecb560-bca5-49a5-baa7-4fd57952fbf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284789141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2284789141
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.67418458
Short name T589
Test name
Test status
Simulation time 977762872 ps
CPU time 3.4 seconds
Started May 28 02:48:57 PM PDT 24
Finished May 28 02:49:09 PM PDT 24
Peak memory 209504 kb
Host smart-a6219782-5829-4b95-9da0-a347a875729f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67418458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.67418458
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1054809347
Short name T250
Test name
Test status
Simulation time 114720846 ps
CPU time 2.33 seconds
Started May 28 02:48:54 PM PDT 24
Finished May 28 02:49:05 PM PDT 24
Peak memory 217896 kb
Host smart-914a1fba-1bf9-404d-b170-3620863eb4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054809347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1054809347
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.1991122579
Short name T729
Test name
Test status
Simulation time 282601497 ps
CPU time 12.54 seconds
Started May 28 02:48:55 PM PDT 24
Finished May 28 02:49:15 PM PDT 24
Peak memory 225928 kb
Host smart-3931685f-05ae-4c33-9ebf-5ecbb7e4716c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991122579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1991122579
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.2953583358
Short name T838
Test name
Test status
Simulation time 341427299 ps
CPU time 12.31 seconds
Started May 28 02:48:57 PM PDT 24
Finished May 28 02:49:17 PM PDT 24
Peak memory 225840 kb
Host smart-4e1e06c4-806b-4fdb-a5ce-187ebf077870
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953583358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.2953583358
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.817636054
Short name T873
Test name
Test status
Simulation time 267633963 ps
CPU time 7.27 seconds
Started May 28 02:48:52 PM PDT 24
Finished May 28 02:49:06 PM PDT 24
Peak memory 217864 kb
Host smart-7590dba7-3c68-4fe2-b9b2-ae62c391b046
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817636054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.817636054
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3597019396
Short name T741
Test name
Test status
Simulation time 280592665 ps
CPU time 7.63 seconds
Started May 28 02:48:54 PM PDT 24
Finished May 28 02:49:09 PM PDT 24
Peak memory 217896 kb
Host smart-81c7357f-c05a-434e-a20f-60a56005131c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597019396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3597019396
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.723511563
Short name T699
Test name
Test status
Simulation time 269815459 ps
CPU time 3.41 seconds
Started May 28 02:49:05 PM PDT 24
Finished May 28 02:49:18 PM PDT 24
Peak memory 217936 kb
Host smart-549ddb25-757d-482c-b9ac-ce0ca8ca3e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723511563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.723511563
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3736233441
Short name T605
Test name
Test status
Simulation time 2491881733 ps
CPU time 28.36 seconds
Started May 28 02:48:55 PM PDT 24
Finished May 28 02:49:31 PM PDT 24
Peak memory 250968 kb
Host smart-7efa24c7-0761-478f-b7b9-a368b05de7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736233441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3736233441
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.3937162743
Short name T863
Test name
Test status
Simulation time 93121487 ps
CPU time 6.95 seconds
Started May 28 02:48:54 PM PDT 24
Finished May 28 02:49:09 PM PDT 24
Peak memory 248424 kb
Host smart-24d12ca7-8fa4-44d1-a7aa-fc167c194269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937162743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.3937162743
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2844637878
Short name T80
Test name
Test status
Simulation time 2149872642 ps
CPU time 54 seconds
Started May 28 02:48:53 PM PDT 24
Finished May 28 02:49:54 PM PDT 24
Peak memory 225992 kb
Host smart-67a57d32-b1cb-46f5-9cd4-fffcf081d54d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844637878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2844637878
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.1991650222
Short name T102
Test name
Test status
Simulation time 64683241495 ps
CPU time 1240.08 seconds
Started May 28 02:48:54 PM PDT 24
Finished May 28 03:09:42 PM PDT 24
Peak memory 280408 kb
Host smart-c7cd8a6e-0709-4f68-a863-c7ab304af10e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1991650222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.1991650222
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1273293015
Short name T147
Test name
Test status
Simulation time 31281394 ps
CPU time 0.93 seconds
Started May 28 02:48:52 PM PDT 24
Finished May 28 02:49:00 PM PDT 24
Peak memory 212676 kb
Host smart-f253de1b-f9c8-4624-950e-e3729ee75d4d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273293015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1273293015
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1670358459
Short name T233
Test name
Test status
Simulation time 26406499 ps
CPU time 1.35 seconds
Started May 28 02:46:59 PM PDT 24
Finished May 28 02:47:12 PM PDT 24
Peak memory 209396 kb
Host smart-af3ab206-3772-452b-b3ff-fb35f4f69fc2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670358459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1670358459
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2765806818
Short name T752
Test name
Test status
Simulation time 13349372 ps
CPU time 0.81 seconds
Started May 28 02:46:54 PM PDT 24
Finished May 28 02:47:08 PM PDT 24
Peak memory 209368 kb
Host smart-6af92265-35ad-4fda-949c-4c1b8ec996f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765806818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2765806818
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.3858432211
Short name T538
Test name
Test status
Simulation time 208112803 ps
CPU time 7.79 seconds
Started May 28 02:46:54 PM PDT 24
Finished May 28 02:47:14 PM PDT 24
Peak memory 217836 kb
Host smart-7a9eeb99-b911-4b9e-bacd-f882d7500875
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858432211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.3858432211
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2287061023
Short name T292
Test name
Test status
Simulation time 481737363 ps
CPU time 1.85 seconds
Started May 28 02:46:55 PM PDT 24
Finished May 28 02:47:09 PM PDT 24
Peak memory 209444 kb
Host smart-c7daea5b-7a59-417d-8903-c635e1415a3b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287061023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2287061023
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.115665949
Short name T784
Test name
Test status
Simulation time 1577299548 ps
CPU time 24.11 seconds
Started May 28 02:46:54 PM PDT 24
Finished May 28 02:47:30 PM PDT 24
Peak memory 217788 kb
Host smart-2d348bef-c0b0-45dd-a20d-46578399b940
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115665949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_err
ors.115665949
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.1452993191
Short name T346
Test name
Test status
Simulation time 276282247 ps
CPU time 7.33 seconds
Started May 28 02:46:55 PM PDT 24
Finished May 28 02:47:15 PM PDT 24
Peak memory 216976 kb
Host smart-b5dc64a7-1696-4a6f-ba05-d78db033cafe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452993191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.1
452993191
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.1986248223
Short name T551
Test name
Test status
Simulation time 96233678 ps
CPU time 2.35 seconds
Started May 28 02:46:55 PM PDT 24
Finished May 28 02:47:09 PM PDT 24
Peak memory 217840 kb
Host smart-aeb74bc0-a06e-4021-90f6-f6fd2b570f45
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986248223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.1986248223
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2169928046
Short name T743
Test name
Test status
Simulation time 1604732152 ps
CPU time 13.02 seconds
Started May 28 02:46:53 PM PDT 24
Finished May 28 02:47:18 PM PDT 24
Peak memory 212912 kb
Host smart-aebc518b-06ae-499f-903a-f8cdda20e77f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169928046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.2169928046
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3942832092
Short name T511
Test name
Test status
Simulation time 173889196 ps
CPU time 3.44 seconds
Started May 28 02:46:56 PM PDT 24
Finished May 28 02:47:12 PM PDT 24
Peak memory 213032 kb
Host smart-cf68e4d3-e4be-4715-bbd0-928ee64063cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942832092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3942832092
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.2787395384
Short name T714
Test name
Test status
Simulation time 7684519005 ps
CPU time 123.05 seconds
Started May 28 02:46:57 PM PDT 24
Finished May 28 02:49:13 PM PDT 24
Peak memory 283512 kb
Host smart-5adf512d-e98e-4688-82d3-b71db397a724
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787395384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.2787395384
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2093843069
Short name T156
Test name
Test status
Simulation time 1151437223 ps
CPU time 10.06 seconds
Started May 28 02:46:54 PM PDT 24
Finished May 28 02:47:16 PM PDT 24
Peak memory 249796 kb
Host smart-9023f6a7-0ef2-41ca-9dea-9ae52d1f4ec8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093843069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2093843069
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3906570991
Short name T823
Test name
Test status
Simulation time 65572054 ps
CPU time 1.54 seconds
Started May 28 02:46:59 PM PDT 24
Finished May 28 02:47:13 PM PDT 24
Peak memory 217920 kb
Host smart-7d9f57e7-c658-4db4-bdd7-e60c66cdc32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906570991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3906570991
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2958716075
Short name T77
Test name
Test status
Simulation time 362619724 ps
CPU time 24.93 seconds
Started May 28 02:46:57 PM PDT 24
Finished May 28 02:47:34 PM PDT 24
Peak memory 214480 kb
Host smart-06413024-d34b-481c-be20-827a72b50150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958716075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2958716075
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.4193988132
Short name T565
Test name
Test status
Simulation time 1257061978 ps
CPU time 9.77 seconds
Started May 28 02:46:56 PM PDT 24
Finished May 28 02:47:19 PM PDT 24
Peak memory 217856 kb
Host smart-2d9dcbab-06a7-480d-b2dc-c7799fadac2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193988132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.4193988132
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3408506138
Short name T865
Test name
Test status
Simulation time 241449636 ps
CPU time 7.39 seconds
Started May 28 02:46:53 PM PDT 24
Finished May 28 02:47:12 PM PDT 24
Peak memory 217840 kb
Host smart-c4acd472-4c8c-4343-b49e-615c3eb920bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408506138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
408506138
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.928329455
Short name T217
Test name
Test status
Simulation time 1779790655 ps
CPU time 12.82 seconds
Started May 28 02:46:54 PM PDT 24
Finished May 28 02:47:19 PM PDT 24
Peak memory 225324 kb
Host smart-9122cf85-9d7a-4956-a8f5-a0d08c670664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928329455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.928329455
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.3956698858
Short name T296
Test name
Test status
Simulation time 50853468 ps
CPU time 1.77 seconds
Started May 28 02:46:56 PM PDT 24
Finished May 28 02:47:11 PM PDT 24
Peak memory 217632 kb
Host smart-2dc49755-53a3-4188-b1b9-6b12ddeb099d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956698858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.3956698858
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3333105076
Short name T841
Test name
Test status
Simulation time 293797986 ps
CPU time 32.33 seconds
Started May 28 02:46:57 PM PDT 24
Finished May 28 02:47:42 PM PDT 24
Peak memory 250824 kb
Host smart-1d41f82a-2cb4-47c3-94a6-d27389716d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333105076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3333105076
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.1104247358
Short name T417
Test name
Test status
Simulation time 400573877 ps
CPU time 3.57 seconds
Started May 28 02:46:54 PM PDT 24
Finished May 28 02:47:09 PM PDT 24
Peak memory 222344 kb
Host smart-81f897f0-05fd-46ff-b99a-cd4c32e60d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104247358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.1104247358
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2567284115
Short name T41
Test name
Test status
Simulation time 18730335759 ps
CPU time 184.25 seconds
Started May 28 02:46:54 PM PDT 24
Finished May 28 02:50:11 PM PDT 24
Peak memory 277128 kb
Host smart-e104606b-b68e-402b-ab88-69835cd80750
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567284115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2567284115
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.4023656609
Short name T759
Test name
Test status
Simulation time 68293087 ps
CPU time 0.91 seconds
Started May 28 02:46:54 PM PDT 24
Finished May 28 02:47:06 PM PDT 24
Peak memory 212584 kb
Host smart-d104937c-c200-4caf-a5da-7d8895421fa3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023656609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.4023656609
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.372554579
Short name T434
Test name
Test status
Simulation time 23175294 ps
CPU time 1.22 seconds
Started May 28 02:46:57 PM PDT 24
Finished May 28 02:47:11 PM PDT 24
Peak memory 209412 kb
Host smart-a1885670-6008-41f6-9e9b-154d28acb9b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372554579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.372554579
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.3223242609
Short name T457
Test name
Test status
Simulation time 2846619327 ps
CPU time 14.43 seconds
Started May 28 02:46:54 PM PDT 24
Finished May 28 02:47:21 PM PDT 24
Peak memory 217988 kb
Host smart-d877db20-ffab-42ee-a449-9f70eb926a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223242609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.3223242609
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.915926190
Short name T819
Test name
Test status
Simulation time 5092584943 ps
CPU time 11.85 seconds
Started May 28 02:46:57 PM PDT 24
Finished May 28 02:47:22 PM PDT 24
Peak memory 209552 kb
Host smart-d6dc6d74-28b8-41e4-bb9e-f5f1bcaa1278
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915926190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.915926190
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.222511277
Short name T242
Test name
Test status
Simulation time 7736680392 ps
CPU time 45.19 seconds
Started May 28 02:46:54 PM PDT 24
Finished May 28 02:47:51 PM PDT 24
Peak memory 218588 kb
Host smart-8d4784d0-04d8-4970-9b76-c4c94d45dfa1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222511277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.222511277
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1329658961
Short name T264
Test name
Test status
Simulation time 1890364471 ps
CPU time 8.23 seconds
Started May 28 02:46:57 PM PDT 24
Finished May 28 02:47:18 PM PDT 24
Peak memory 217084 kb
Host smart-73cb6b0a-ad64-40a5-b7f3-3b5b4368a830
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329658961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
329658961
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3750267948
Short name T682
Test name
Test status
Simulation time 58670844 ps
CPU time 1.81 seconds
Started May 28 02:46:54 PM PDT 24
Finished May 28 02:47:09 PM PDT 24
Peak memory 217796 kb
Host smart-77c19b67-5a96-4187-a37f-b07b45c64e7a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750267948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3750267948
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.8452091
Short name T283
Test name
Test status
Simulation time 2810647150 ps
CPU time 19.24 seconds
Started May 28 02:46:55 PM PDT 24
Finished May 28 02:47:26 PM PDT 24
Peak memory 213112 kb
Host smart-6e48ccc1-8163-4387-a701-22f77a42fc29
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8452091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_re
gwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_regwen_during_op.8452091
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.643251734
Short name T745
Test name
Test status
Simulation time 918167399 ps
CPU time 5.35 seconds
Started May 28 02:46:55 PM PDT 24
Finished May 28 02:47:12 PM PDT 24
Peak memory 213044 kb
Host smart-df91103d-b6c9-44b7-943c-78ae3b301246
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643251734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.643251734
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.589939284
Short name T157
Test name
Test status
Simulation time 9811435368 ps
CPU time 100.41 seconds
Started May 28 02:46:55 PM PDT 24
Finished May 28 02:48:48 PM PDT 24
Peak memory 277632 kb
Host smart-8dd54ad5-2510-4d47-b750-d345baf15bee
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589939284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_state_failure.589939284
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3848068267
Short name T825
Test name
Test status
Simulation time 643552514 ps
CPU time 14.47 seconds
Started May 28 02:46:56 PM PDT 24
Finished May 28 02:47:24 PM PDT 24
Peak memory 249996 kb
Host smart-ac9f6bb3-c934-48ea-9340-738212a05753
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848068267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3848068267
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3001172771
Short name T704
Test name
Test status
Simulation time 135973826 ps
CPU time 3.41 seconds
Started May 28 02:46:58 PM PDT 24
Finished May 28 02:47:14 PM PDT 24
Peak memory 217888 kb
Host smart-ecc64d7d-1096-40a4-9673-5b4824ad6245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001172771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3001172771
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.3468182075
Short name T577
Test name
Test status
Simulation time 267930224 ps
CPU time 14.8 seconds
Started May 28 02:46:57 PM PDT 24
Finished May 28 02:47:25 PM PDT 24
Peak memory 213568 kb
Host smart-b90a8d61-3a37-4af2-8132-f0af5a9da59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468182075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.3468182075
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1896474112
Short name T339
Test name
Test status
Simulation time 962516760 ps
CPU time 19.19 seconds
Started May 28 02:46:55 PM PDT 24
Finished May 28 02:47:27 PM PDT 24
Peak memory 225940 kb
Host smart-5cec3db7-9454-497b-a485-d04822973d2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896474112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1896474112
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.24525235
Short name T780
Test name
Test status
Simulation time 423396173 ps
CPU time 11.12 seconds
Started May 28 02:46:57 PM PDT 24
Finished May 28 02:47:21 PM PDT 24
Peak memory 217868 kb
Host smart-dddba2b5-83d3-4287-98f5-24611f231526
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24525235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_dige
st.24525235
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.153200304
Short name T796
Test name
Test status
Simulation time 1189917822 ps
CPU time 7.4 seconds
Started May 28 02:46:54 PM PDT 24
Finished May 28 02:47:14 PM PDT 24
Peak memory 217836 kb
Host smart-68b3f73e-fb7f-42cd-b46f-3e52063b8548
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153200304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.153200304
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2945900616
Short name T219
Test name
Test status
Simulation time 498778829 ps
CPU time 8.76 seconds
Started May 28 02:46:57 PM PDT 24
Finished May 28 02:47:18 PM PDT 24
Peak memory 224700 kb
Host smart-4b8f136c-5a14-4f00-9a58-56638afe1ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945900616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2945900616
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.3899743638
Short name T65
Test name
Test status
Simulation time 428636501 ps
CPU time 3.08 seconds
Started May 28 02:46:56 PM PDT 24
Finished May 28 02:47:12 PM PDT 24
Peak memory 214112 kb
Host smart-3f7baf5e-1711-4d85-9c9f-f5125a3934c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899743638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.3899743638
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.1863536265
Short name T221
Test name
Test status
Simulation time 447798189 ps
CPU time 31.24 seconds
Started May 28 02:46:55 PM PDT 24
Finished May 28 02:47:39 PM PDT 24
Peak memory 250860 kb
Host smart-8cc53b89-8d2e-4f6a-ab54-542a25d37287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863536265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.1863536265
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2674061609
Short name T818
Test name
Test status
Simulation time 1188054451 ps
CPU time 7.65 seconds
Started May 28 02:46:54 PM PDT 24
Finished May 28 02:47:14 PM PDT 24
Peak memory 250828 kb
Host smart-ce02a178-fc90-4251-a2fc-d03e5f0719fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674061609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2674061609
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1180367881
Short name T313
Test name
Test status
Simulation time 4912020778 ps
CPU time 111.63 seconds
Started May 28 02:46:55 PM PDT 24
Finished May 28 02:49:00 PM PDT 24
Peak memory 247992 kb
Host smart-8a49a032-7fdc-4d6c-8b27-5b99ec8fbef9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180367881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1180367881
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3542568003
Short name T364
Test name
Test status
Simulation time 62263468 ps
CPU time 1.03 seconds
Started May 28 02:46:55 PM PDT 24
Finished May 28 02:47:08 PM PDT 24
Peak memory 212580 kb
Host smart-48922950-a5d7-4dfe-b01d-cf26aeafb516
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542568003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3542568003
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.3063763830
Short name T479
Test name
Test status
Simulation time 31658299 ps
CPU time 1.1 seconds
Started May 28 02:46:58 PM PDT 24
Finished May 28 02:47:12 PM PDT 24
Peak memory 209116 kb
Host smart-5af1cd90-af34-4f18-89cc-625347229deb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063763830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.3063763830
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3586448010
Short name T655
Test name
Test status
Simulation time 582501242 ps
CPU time 13.37 seconds
Started May 28 02:46:58 PM PDT 24
Finished May 28 02:47:24 PM PDT 24
Peak memory 217756 kb
Host smart-34306133-523b-4556-88b1-4ecc3bb05ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586448010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3586448010
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.84987684
Short name T856
Test name
Test status
Simulation time 329284322 ps
CPU time 2.4 seconds
Started May 28 02:47:01 PM PDT 24
Finished May 28 02:47:15 PM PDT 24
Peak memory 209324 kb
Host smart-dd185fa7-d726-4a6d-96b7-30376ff359b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84987684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.84987684
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.1903352034
Short name T703
Test name
Test status
Simulation time 7284694066 ps
CPU time 38.65 seconds
Started May 28 02:47:02 PM PDT 24
Finished May 28 02:47:52 PM PDT 24
Peak memory 217916 kb
Host smart-36e4be47-8fc4-43c0-aa2a-8b20089a049b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903352034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.1903352034
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.1212504700
Short name T474
Test name
Test status
Simulation time 919721567 ps
CPU time 8.35 seconds
Started May 28 02:46:55 PM PDT 24
Finished May 28 02:47:16 PM PDT 24
Peak memory 217048 kb
Host smart-77dda22b-edf3-4c96-b3d9-069b78b76799
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212504700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.1
212504700
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2912413441
Short name T657
Test name
Test status
Simulation time 885873256 ps
CPU time 4.5 seconds
Started May 28 02:46:57 PM PDT 24
Finished May 28 02:47:15 PM PDT 24
Peak memory 217680 kb
Host smart-b0fe2f33-a98e-4396-bf58-f98c7efa2f6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912413441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2912413441
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.1098170077
Short name T505
Test name
Test status
Simulation time 2004412654 ps
CPU time 16.43 seconds
Started May 28 02:47:02 PM PDT 24
Finished May 28 02:47:30 PM PDT 24
Peak memory 213140 kb
Host smart-507bbf07-a01b-4227-bde5-b6a9a235222c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098170077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.1098170077
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.1624571568
Short name T21
Test name
Test status
Simulation time 134917019 ps
CPU time 1.67 seconds
Started May 28 02:47:02 PM PDT 24
Finished May 28 02:47:15 PM PDT 24
Peak memory 217224 kb
Host smart-81786f4d-9b20-43df-bbba-bdd65424823a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624571568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
1624571568
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.478025079
Short name T407
Test name
Test status
Simulation time 3399648364 ps
CPU time 45.71 seconds
Started May 28 02:46:58 PM PDT 24
Finished May 28 02:47:57 PM PDT 24
Peak memory 267340 kb
Host smart-90004a8a-d179-4072-8a69-92152c182f40
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478025079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.478025079
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2976177699
Short name T436
Test name
Test status
Simulation time 762494730 ps
CPU time 11.9 seconds
Started May 28 02:47:02 PM PDT 24
Finished May 28 02:47:25 PM PDT 24
Peak memory 250772 kb
Host smart-34c686a5-b598-4088-8fcc-1a91436934b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976177699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2976177699
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3223089385
Short name T694
Test name
Test status
Simulation time 77670489 ps
CPU time 2.72 seconds
Started May 28 02:46:55 PM PDT 24
Finished May 28 02:47:10 PM PDT 24
Peak memory 217836 kb
Host smart-bc5d1638-4a8b-4060-8a64-732a72f2609d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223089385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3223089385
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.1252485081
Short name T671
Test name
Test status
Simulation time 1114852264 ps
CPU time 7.58 seconds
Started May 28 02:46:56 PM PDT 24
Finished May 28 02:47:17 PM PDT 24
Peak memory 214004 kb
Host smart-4ec91b52-c57c-4d0f-8371-57c2244447e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252485081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.1252485081
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2798792084
Short name T224
Test name
Test status
Simulation time 235688976 ps
CPU time 9 seconds
Started May 28 02:46:58 PM PDT 24
Finished May 28 02:47:20 PM PDT 24
Peak memory 217604 kb
Host smart-5d93d209-2f1d-4dc4-b95c-e00bacdd019f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798792084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2798792084
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3212532401
Short name T739
Test name
Test status
Simulation time 820165658 ps
CPU time 9.45 seconds
Started May 28 02:47:02 PM PDT 24
Finished May 28 02:47:23 PM PDT 24
Peak memory 217852 kb
Host smart-3e1db0a5-3cc4-42f8-8b3c-582a0073f004
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212532401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3212532401
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.4188082297
Short name T519
Test name
Test status
Simulation time 475380709 ps
CPU time 8.94 seconds
Started May 28 02:46:58 PM PDT 24
Finished May 28 02:47:19 PM PDT 24
Peak memory 217852 kb
Host smart-d3b21bca-7ef9-46c0-adaf-2e34a3b3226b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188082297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.4
188082297
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2998677953
Short name T562
Test name
Test status
Simulation time 375534076 ps
CPU time 14.37 seconds
Started May 28 02:46:58 PM PDT 24
Finished May 28 02:47:25 PM PDT 24
Peak memory 217884 kb
Host smart-c4d60f2c-ab36-450a-b057-3ed3f7f4b6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998677953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2998677953
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1115601571
Short name T82
Test name
Test status
Simulation time 48346322 ps
CPU time 2.88 seconds
Started May 28 02:46:58 PM PDT 24
Finished May 28 02:47:14 PM PDT 24
Peak memory 213884 kb
Host smart-d68c595c-5c91-4d35-af92-911e6baa3e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115601571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1115601571
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3567388200
Short name T670
Test name
Test status
Simulation time 301678068 ps
CPU time 17.02 seconds
Started May 28 02:46:53 PM PDT 24
Finished May 28 02:47:22 PM PDT 24
Peak memory 250848 kb
Host smart-fed64419-c62c-4b88-93b4-b8dc5cd9d2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567388200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3567388200
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.38830215
Short name T226
Test name
Test status
Simulation time 83069052 ps
CPU time 3.33 seconds
Started May 28 02:46:55 PM PDT 24
Finished May 28 02:47:10 PM PDT 24
Peak memory 222280 kb
Host smart-4f4d5471-0c5b-49c5-8e8b-2c9de0cc6f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38830215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.38830215
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.2802344858
Short name T544
Test name
Test status
Simulation time 52751378888 ps
CPU time 213.44 seconds
Started May 28 02:47:02 PM PDT 24
Finished May 28 02:50:47 PM PDT 24
Peak memory 267344 kb
Host smart-155829b4-3ca9-410d-a98d-30d0f17804be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802344858 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.2802344858
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2087637274
Short name T644
Test name
Test status
Simulation time 27983292 ps
CPU time 0.87 seconds
Started May 28 02:46:55 PM PDT 24
Finished May 28 02:47:09 PM PDT 24
Peak memory 211476 kb
Host smart-3ba654ef-f791-414d-8ae1-e7d9a340d1cd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087637274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.2087637274
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2044184329
Short name T159
Test name
Test status
Simulation time 18313950 ps
CPU time 0.94 seconds
Started May 28 02:47:09 PM PDT 24
Finished May 28 02:47:23 PM PDT 24
Peak memory 209608 kb
Host smart-dd6941fd-4524-41c4-b0df-5c86882638f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044184329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2044184329
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.3679872020
Short name T212
Test name
Test status
Simulation time 20279424 ps
CPU time 0.94 seconds
Started May 28 02:47:12 PM PDT 24
Finished May 28 02:47:25 PM PDT 24
Peak memory 209436 kb
Host smart-d89b04fa-c399-46bd-a175-ccdf6767b718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679872020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.3679872020
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.689454396
Short name T877
Test name
Test status
Simulation time 607137707 ps
CPU time 13.89 seconds
Started May 28 02:46:57 PM PDT 24
Finished May 28 02:47:25 PM PDT 24
Peak memory 217780 kb
Host smart-f5b617ba-3d30-424b-9209-56f74d25fdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689454396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.689454396
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3827872465
Short name T631
Test name
Test status
Simulation time 958744402 ps
CPU time 3.52 seconds
Started May 28 02:47:08 PM PDT 24
Finished May 28 02:47:24 PM PDT 24
Peak memory 209512 kb
Host smart-77bec65b-9d4b-4938-84bc-6c6b67bdeee3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827872465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3827872465
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2079835300
Short name T514
Test name
Test status
Simulation time 6449910770 ps
CPU time 40.96 seconds
Started May 28 02:47:10 PM PDT 24
Finished May 28 02:48:03 PM PDT 24
Peak memory 218852 kb
Host smart-9e1a42b4-a9f1-417b-b3da-f96a6c3971a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079835300 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2079835300
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.606581189
Short name T379
Test name
Test status
Simulation time 1005958432 ps
CPU time 2.38 seconds
Started May 28 02:47:04 PM PDT 24
Finished May 28 02:47:18 PM PDT 24
Peak memory 217268 kb
Host smart-8f9109a7-ab7b-4ff1-941c-215168216bd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606581189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.606581189
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.869735354
Short name T619
Test name
Test status
Simulation time 117951430 ps
CPU time 3.15 seconds
Started May 28 02:47:10 PM PDT 24
Finished May 28 02:47:25 PM PDT 24
Peak memory 217808 kb
Host smart-824d5c9a-f52a-47ec-aa1a-a967db0d6c48
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869735354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.869735354
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3080892713
Short name T533
Test name
Test status
Simulation time 802642568 ps
CPU time 11 seconds
Started May 28 02:47:06 PM PDT 24
Finished May 28 02:47:28 PM PDT 24
Peak memory 212856 kb
Host smart-eb5fe8fe-453e-49e1-93ae-c5a8ca5d336f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080892713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3080892713
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2827275138
Short name T240
Test name
Test status
Simulation time 98850397 ps
CPU time 2.2 seconds
Started May 28 02:47:04 PM PDT 24
Finished May 28 02:47:18 PM PDT 24
Peak memory 212928 kb
Host smart-4c9b5c63-bcf1-4a53-a231-2e8863ad260e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827275138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2827275138
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.3319484769
Short name T263
Test name
Test status
Simulation time 3963990661 ps
CPU time 48.22 seconds
Started May 28 02:47:08 PM PDT 24
Finished May 28 02:48:08 PM PDT 24
Peak memory 276472 kb
Host smart-4c9251f9-02de-484e-b693-71e6aeafc717
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319484769 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.3319484769
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.3611482872
Short name T820
Test name
Test status
Simulation time 244594770 ps
CPU time 11.27 seconds
Started May 28 02:47:04 PM PDT 24
Finished May 28 02:47:27 PM PDT 24
Peak memory 250740 kb
Host smart-92956dff-d4eb-49bd-a483-c4d754f784a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611482872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.3611482872
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.2709560286
Short name T742
Test name
Test status
Simulation time 121870604 ps
CPU time 3.26 seconds
Started May 28 02:46:56 PM PDT 24
Finished May 28 02:47:12 PM PDT 24
Peak memory 217856 kb
Host smart-ae734663-b52d-4b36-81da-eb92c8afc693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709560286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.2709560286
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.1846374190
Short name T555
Test name
Test status
Simulation time 2505915445 ps
CPU time 16.95 seconds
Started May 28 02:47:05 PM PDT 24
Finished May 28 02:47:33 PM PDT 24
Peak memory 213828 kb
Host smart-c6651315-01d0-4cec-a992-612373f98b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846374190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.1846374190
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.203467273
Short name T706
Test name
Test status
Simulation time 174102128 ps
CPU time 7.84 seconds
Started May 28 02:47:10 PM PDT 24
Finished May 28 02:47:30 PM PDT 24
Peak memory 217864 kb
Host smart-ba18ecd3-5e28-4813-870a-72b770a3e85f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203467273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.203467273
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.4076939217
Short name T327
Test name
Test status
Simulation time 1656254424 ps
CPU time 8.2 seconds
Started May 28 02:47:06 PM PDT 24
Finished May 28 02:47:25 PM PDT 24
Peak memory 217856 kb
Host smart-aeee127b-cfb9-49dc-bb81-84bda9b12d67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076939217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.4076939217
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.932395168
Short name T258
Test name
Test status
Simulation time 1050293265 ps
CPU time 8.54 seconds
Started May 28 02:47:08 PM PDT 24
Finished May 28 02:47:29 PM PDT 24
Peak memory 217900 kb
Host smart-57f496b8-f931-4f28-9df8-8fb9b4bb30e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932395168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.932395168
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.1059429160
Short name T55
Test name
Test status
Simulation time 301407367 ps
CPU time 12.37 seconds
Started May 28 02:46:57 PM PDT 24
Finished May 28 02:47:22 PM PDT 24
Peak memory 218000 kb
Host smart-6ed7b56a-c269-4a4f-9b36-276686ac37b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059429160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.1059429160
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1430475584
Short name T63
Test name
Test status
Simulation time 23355727 ps
CPU time 2.02 seconds
Started May 28 02:47:02 PM PDT 24
Finished May 28 02:47:15 PM PDT 24
Peak memory 213468 kb
Host smart-8b927f39-9d06-4600-9b45-463f0244881c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430475584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1430475584
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3907822973
Short name T558
Test name
Test status
Simulation time 335789053 ps
CPU time 25.5 seconds
Started May 28 02:47:01 PM PDT 24
Finished May 28 02:47:38 PM PDT 24
Peak memory 250844 kb
Host smart-6db11c01-db2c-429a-b692-aa1318aaa3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907822973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3907822973
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3366302509
Short name T405
Test name
Test status
Simulation time 299260701 ps
CPU time 3.37 seconds
Started May 28 02:47:00 PM PDT 24
Finished May 28 02:47:16 PM PDT 24
Peak memory 222840 kb
Host smart-6fdade1c-776c-453a-bd5e-b1e53b9b90b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366302509 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3366302509
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3109755131
Short name T171
Test name
Test status
Simulation time 11133248911 ps
CPU time 111.89 seconds
Started May 28 02:47:04 PM PDT 24
Finished May 28 02:49:07 PM PDT 24
Peak memory 248820 kb
Host smart-eb6dddd3-eeac-4434-a3aa-2cdb4900e989
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109755131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3109755131
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.2813729585
Short name T46
Test name
Test status
Simulation time 129675796576 ps
CPU time 1040.91 seconds
Started May 28 02:47:09 PM PDT 24
Finished May 28 03:04:42 PM PDT 24
Peak memory 300192 kb
Host smart-8bc74dd3-f32a-47be-865d-a27167d439cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2813729585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.2813729585
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3190475379
Short name T857
Test name
Test status
Simulation time 13216929 ps
CPU time 0.94 seconds
Started May 28 02:46:55 PM PDT 24
Finished May 28 02:47:08 PM PDT 24
Peak memory 211516 kb
Host smart-9ff0eade-6076-4b7a-8143-e12e12a62a67
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190475379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3190475379
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3335337659
Short name T298
Test name
Test status
Simulation time 28745123 ps
CPU time 1.02 seconds
Started May 28 02:47:08 PM PDT 24
Finished May 28 02:47:21 PM PDT 24
Peak memory 209316 kb
Host smart-087d4100-1106-4381-8675-677eeb2aea94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335337659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3335337659
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2304231311
Short name T211
Test name
Test status
Simulation time 38907269 ps
CPU time 0.84 seconds
Started May 28 02:47:07 PM PDT 24
Finished May 28 02:47:18 PM PDT 24
Peak memory 209376 kb
Host smart-b5d3dd48-2396-4775-afd7-f8c3da6d2a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304231311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2304231311
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3382229612
Short name T145
Test name
Test status
Simulation time 978952687 ps
CPU time 11.19 seconds
Started May 28 02:47:09 PM PDT 24
Finished May 28 02:47:33 PM PDT 24
Peak memory 217768 kb
Host smart-757b4d56-e6c8-414a-aa14-87ba878668a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382229612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3382229612
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.539329974
Short name T30
Test name
Test status
Simulation time 375961113 ps
CPU time 1.51 seconds
Started May 28 02:47:04 PM PDT 24
Finished May 28 02:47:17 PM PDT 24
Peak memory 216792 kb
Host smart-df5a7b39-10c5-4500-8d75-8ac5bae10897
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539329974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.539329974
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.1568034217
Short name T269
Test name
Test status
Simulation time 1809242695 ps
CPU time 18.1 seconds
Started May 28 02:47:08 PM PDT 24
Finished May 28 02:47:38 PM PDT 24
Peak memory 217796 kb
Host smart-d9bee807-25eb-417a-9c79-c5e8767f1313
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568034217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.1568034217
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.767750966
Short name T385
Test name
Test status
Simulation time 281910077 ps
CPU time 6.1 seconds
Started May 28 02:47:15 PM PDT 24
Finished May 28 02:47:33 PM PDT 24
Peak memory 217600 kb
Host smart-fc7c47c2-9dae-42b2-83b8-8a0272f4fb62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767750966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.767750966
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1827783666
Short name T220
Test name
Test status
Simulation time 2616131802 ps
CPU time 10.84 seconds
Started May 28 02:47:04 PM PDT 24
Finished May 28 02:47:26 PM PDT 24
Peak memory 217888 kb
Host smart-52cfd611-fc45-4265-b9e6-cdcc41cbb95b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827783666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1827783666
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3948631710
Short name T74
Test name
Test status
Simulation time 8392802603 ps
CPU time 11.08 seconds
Started May 28 02:47:08 PM PDT 24
Finished May 28 02:47:31 PM PDT 24
Peak memory 213616 kb
Host smart-b424c950-929a-4d7d-beb9-1bd927101c5c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948631710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.3948631710
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2742392786
Short name T711
Test name
Test status
Simulation time 281026113 ps
CPU time 7.07 seconds
Started May 28 02:47:08 PM PDT 24
Finished May 28 02:47:27 PM PDT 24
Peak memory 212940 kb
Host smart-aaf5a77f-449e-420b-9dcd-c65d17fa09a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742392786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2742392786
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.2698652524
Short name T726
Test name
Test status
Simulation time 24372312476 ps
CPU time 35.78 seconds
Started May 28 02:47:10 PM PDT 24
Finished May 28 02:47:58 PM PDT 24
Peak memory 267180 kb
Host smart-b158372b-2418-471e-8846-b0fedcbf1395
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698652524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.2698652524
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.1740273126
Short name T754
Test name
Test status
Simulation time 1363654480 ps
CPU time 16.92 seconds
Started May 28 02:47:15 PM PDT 24
Finished May 28 02:47:44 PM PDT 24
Peak memory 246416 kb
Host smart-04787176-b531-4adb-8a10-b6d710ac5ab1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740273126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.1740273126
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1060805735
Short name T390
Test name
Test status
Simulation time 167015407 ps
CPU time 2.57 seconds
Started May 28 02:47:08 PM PDT 24
Finished May 28 02:47:23 PM PDT 24
Peak memory 217872 kb
Host smart-25f0677d-382d-4212-a594-52b42f2f2121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060805735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1060805735
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2205565849
Short name T467
Test name
Test status
Simulation time 382442177 ps
CPU time 24.77 seconds
Started May 28 02:47:04 PM PDT 24
Finished May 28 02:47:40 PM PDT 24
Peak memory 218132 kb
Host smart-2398bfad-3631-4009-91c4-10f6e7372263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205565849 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2205565849
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.2513998476
Short name T821
Test name
Test status
Simulation time 405572824 ps
CPU time 7.69 seconds
Started May 28 02:47:09 PM PDT 24
Finished May 28 02:47:29 PM PDT 24
Peak memory 225952 kb
Host smart-a260d965-4444-46d0-88ce-23b1c9a9dc69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513998476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2513998476
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1084677061
Short name T747
Test name
Test status
Simulation time 506862848 ps
CPU time 12.52 seconds
Started May 28 02:47:10 PM PDT 24
Finished May 28 02:47:35 PM PDT 24
Peak memory 218036 kb
Host smart-3d5512ec-bbb8-4012-85ab-2b0f5fb892cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084677061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1084677061
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.588395179
Short name T223
Test name
Test status
Simulation time 725180578 ps
CPU time 8.67 seconds
Started May 28 02:47:11 PM PDT 24
Finished May 28 02:47:31 PM PDT 24
Peak memory 217868 kb
Host smart-7c34f730-f62a-47aa-9e56-2fb437176e9b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588395179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.588395179
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.2284230412
Short name T588
Test name
Test status
Simulation time 1287769144 ps
CPU time 8.69 seconds
Started May 28 02:47:11 PM PDT 24
Finished May 28 02:47:31 PM PDT 24
Peak memory 217920 kb
Host smart-a56bcb4b-2b09-41ea-8436-ef908f0b8098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284230412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.2284230412
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1618507418
Short name T79
Test name
Test status
Simulation time 78655775 ps
CPU time 2.62 seconds
Started May 28 02:47:06 PM PDT 24
Finished May 28 02:47:20 PM PDT 24
Peak memory 214212 kb
Host smart-a1a18a9b-6f9a-4c20-9a67-82a6361a2575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618507418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1618507418
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.4204106850
Short name T340
Test name
Test status
Simulation time 273271148 ps
CPU time 26.54 seconds
Started May 28 02:47:04 PM PDT 24
Finished May 28 02:47:43 PM PDT 24
Peak memory 250836 kb
Host smart-ef5b65b4-f283-4680-9b2f-ab21c6a95b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204106850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.4204106850
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1887000603
Short name T423
Test name
Test status
Simulation time 209250912 ps
CPU time 7.26 seconds
Started May 28 02:47:06 PM PDT 24
Finished May 28 02:47:24 PM PDT 24
Peak memory 250292 kb
Host smart-01ad7361-d2b3-4b9a-9ecc-d9a9bac4842f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887000603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1887000603
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.1345858373
Short name T314
Test name
Test status
Simulation time 1231372541 ps
CPU time 27.6 seconds
Started May 28 02:47:10 PM PDT 24
Finished May 28 02:47:50 PM PDT 24
Peak memory 250764 kb
Host smart-51749f80-61d3-4f8b-bbb2-f500960e7308
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345858373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.1345858373
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1565004112
Short name T872
Test name
Test status
Simulation time 14218339 ps
CPU time 1.05 seconds
Started May 28 02:47:06 PM PDT 24
Finished May 28 02:47:19 PM PDT 24
Peak memory 211464 kb
Host smart-3be591ae-f0c7-424f-b6af-9c0602e21844
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565004112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1565004112
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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