Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54797 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
1948 |
1 |
|
|
T16 |
4 |
|
T17 |
8 |
|
T18 |
53 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56040 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
705 |
1 |
|
|
T44 |
10 |
|
T45 |
7 |
|
T60 |
23 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54612 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
2133 |
1 |
|
|
T1 |
1 |
|
T5 |
10 |
|
T23 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54667 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
2078 |
1 |
|
|
T5 |
10 |
|
T27 |
4 |
|
T18 |
8 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54593 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
2152 |
1 |
|
|
T5 |
17 |
|
T23 |
3 |
|
T27 |
6 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
51651 |
1 |
|
|
T1 |
5 |
|
T2 |
5 |
|
T3 |
88 |
no_err_inj |
5094 |
1 |
|
|
T1 |
7 |
|
T2 |
8 |
|
T11 |
14 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54714 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
2031 |
1 |
|
|
T16 |
5 |
|
T17 |
6 |
|
T18 |
60 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55982 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
763 |
1 |
|
|
T44 |
14 |
|
T45 |
16 |
|
T60 |
14 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
38909 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
17836 |
1 |
|
|
T4 |
6 |
|
T5 |
85 |
|
T16 |
63 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54685 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
2060 |
1 |
|
|
T1 |
1 |
|
T5 |
5 |
|
T23 |
1 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54684 |
1 |
|
|
T1 |
11 |
|
T2 |
12 |
|
T3 |
88 |
auto[1] |
2061 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T5 |
8 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54666 |
1 |
|
|
T1 |
11 |
|
T2 |
11 |
|
T3 |
88 |
auto[1] |
2079 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T5 |
13 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54795 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
1950 |
1 |
|
|
T16 |
5 |
|
T17 |
9 |
|
T18 |
49 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54545 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
2200 |
1 |
|
|
T18 |
45 |
|
T25 |
57 |
|
T38 |
10 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
55978 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
767 |
1 |
|
|
T44 |
15 |
|
T45 |
10 |
|
T60 |
16 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56010 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
735 |
1 |
|
|
T44 |
20 |
|
T45 |
13 |
|
T60 |
16 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56043 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
702 |
1 |
|
|
T44 |
12 |
|
T45 |
10 |
|
T60 |
16 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53984 |
1 |
|
|
T3 |
88 |
|
T10 |
97 |
|
T11 |
14 |
auto[1] |
2761 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T23 |
12 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53073 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T11 |
14 |
auto[1] |
3672 |
1 |
|
|
T3 |
88 |
|
T10 |
97 |
|
T49 |
93 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54636 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
2109 |
1 |
|
|
T1 |
1 |
|
T5 |
9 |
|
T23 |
1 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54667 |
1 |
|
|
T1 |
12 |
|
T2 |
12 |
|
T3 |
88 |
auto[1] |
2078 |
1 |
|
|
T2 |
1 |
|
T5 |
5 |
|
T23 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54654 |
1 |
|
|
T1 |
12 |
|
T2 |
12 |
|
T3 |
88 |
auto[1] |
2091 |
1 |
|
|
T2 |
1 |
|
T5 |
8 |
|
T23 |
1 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54698 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
2047 |
1 |
|
|
T16 |
8 |
|
T17 |
11 |
|
T18 |
59 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51150 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
5595 |
1 |
|
|
T14 |
63 |
|
T16 |
13 |
|
T17 |
5 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53018 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
3727 |
1 |
|
|
T12 |
75 |
|
T24 |
98 |
|
T41 |
50 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
56745 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54814 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
1931 |
1 |
|
|
T16 |
7 |
|
T17 |
8 |
|
T18 |
50 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54745 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
2000 |
1 |
|
|
T16 |
9 |
|
T17 |
11 |
|
T18 |
49 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54708 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[1] |
2037 |
1 |
|
|
T16 |
12 |
|
T17 |
3 |
|
T18 |
68 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
50269 |
1 |
|
|
T3 |
88 |
|
T10 |
97 |
|
T12 |
75 |
auto[0] |
no_err_inj |
3715 |
1 |
|
|
T11 |
14 |
|
T13 |
7 |
|
T4 |
6 |
auto[1] |
err_inj |
1382 |
1 |
|
|
T1 |
5 |
|
T2 |
5 |
|
T23 |
8 |
auto[1] |
no_err_inj |
1379 |
1 |
|
|
T1 |
7 |
|
T2 |
8 |
|
T23 |
4 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52073 |
1 |
|
|
T3 |
88 |
|
T10 |
97 |
|
T11 |
14 |
auto[0] |
auto[1] |
1911 |
1 |
|
|
T5 |
5 |
|
T27 |
9 |
|
T18 |
8 |
auto[1] |
auto[0] |
2594 |
1 |
|
|
T1 |
12 |
|
T2 |
12 |
|
T23 |
11 |
auto[1] |
auto[1] |
167 |
1 |
|
|
T2 |
1 |
|
T23 |
1 |
|
T18 |
4 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52063 |
1 |
|
|
T3 |
88 |
|
T10 |
97 |
|
T11 |
14 |
auto[0] |
auto[1] |
1921 |
1 |
|
|
T5 |
8 |
|
T27 |
8 |
|
T18 |
9 |
auto[1] |
auto[0] |
2621 |
1 |
|
|
T1 |
11 |
|
T2 |
12 |
|
T23 |
12 |
auto[1] |
auto[1] |
140 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T18 |
3 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52054 |
1 |
|
|
T3 |
88 |
|
T10 |
97 |
|
T11 |
14 |
auto[0] |
auto[1] |
1930 |
1 |
|
|
T5 |
8 |
|
T27 |
8 |
|
T18 |
6 |
auto[1] |
auto[0] |
2600 |
1 |
|
|
T1 |
12 |
|
T2 |
12 |
|
T23 |
11 |
auto[1] |
auto[1] |
161 |
1 |
|
|
T2 |
1 |
|
T23 |
1 |
|
T18 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
52062 |
1 |
|
|
T3 |
88 |
|
T10 |
97 |
|
T11 |
14 |
auto[0] |
auto[1] |
1922 |
1 |
|
|
T5 |
10 |
|
T27 |
4 |
|
T18 |
8 |
auto[1] |
auto[0] |
2605 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T23 |
12 |
auto[1] |
auto[1] |
156 |
1 |
|
|
T25 |
1 |
|
T37 |
2 |
|
T40 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51999 |
1 |
|
|
T3 |
88 |
|
T10 |
97 |
|
T11 |
14 |
auto[0] |
auto[1] |
1985 |
1 |
|
|
T5 |
17 |
|
T27 |
6 |
|
T18 |
13 |
auto[1] |
auto[0] |
2594 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T23 |
9 |
auto[1] |
auto[1] |
167 |
1 |
|
|
T23 |
3 |
|
T37 |
2 |
|
T39 |
2 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
51999 |
1 |
|
|
T3 |
88 |
|
T10 |
97 |
|
T11 |
14 |
auto[0] |
auto[1] |
1985 |
1 |
|
|
T5 |
10 |
|
T27 |
2 |
|
T18 |
5 |
auto[1] |
auto[0] |
2613 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T23 |
11 |
auto[1] |
auto[1] |
148 |
1 |
|
|
T1 |
1 |
|
T23 |
1 |
|
T18 |
5 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37724 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[0] |
auto[1] |
1185 |
1 |
|
|
T18 |
28 |
|
T25 |
18 |
|
T46 |
12 |
auto[1] |
auto[0] |
17073 |
1 |
|
|
T4 |
6 |
|
T5 |
85 |
|
T16 |
59 |
auto[1] |
auto[1] |
763 |
1 |
|
|
T16 |
4 |
|
T17 |
8 |
|
T18 |
25 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37691 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[0] |
auto[1] |
1218 |
1 |
|
|
T18 |
27 |
|
T25 |
21 |
|
T46 |
17 |
auto[1] |
auto[0] |
17023 |
1 |
|
|
T4 |
6 |
|
T5 |
85 |
|
T16 |
58 |
auto[1] |
auto[1] |
813 |
1 |
|
|
T16 |
5 |
|
T17 |
6 |
|
T18 |
33 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37759 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[0] |
auto[1] |
1150 |
1 |
|
|
T18 |
30 |
|
T38 |
10 |
|
T47 |
31 |
auto[1] |
auto[0] |
16786 |
1 |
|
|
T4 |
6 |
|
T5 |
85 |
|
T16 |
63 |
auto[1] |
auto[1] |
1050 |
1 |
|
|
T18 |
15 |
|
T25 |
57 |
|
T28 |
12 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37713 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[0] |
auto[1] |
1196 |
1 |
|
|
T18 |
22 |
|
T25 |
18 |
|
T46 |
14 |
auto[1] |
auto[0] |
17082 |
1 |
|
|
T4 |
6 |
|
T5 |
85 |
|
T16 |
58 |
auto[1] |
auto[1] |
754 |
1 |
|
|
T16 |
5 |
|
T17 |
9 |
|
T18 |
27 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34100 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[0] |
auto[1] |
4809 |
1 |
|
|
T14 |
63 |
|
T26 |
96 |
|
T18 |
29 |
auto[1] |
auto[0] |
17050 |
1 |
|
|
T4 |
6 |
|
T5 |
85 |
|
T16 |
50 |
auto[1] |
auto[1] |
786 |
1 |
|
|
T16 |
13 |
|
T17 |
5 |
|
T18 |
16 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37763 |
1 |
|
|
T1 |
12 |
|
T2 |
12 |
|
T3 |
88 |
auto[0] |
auto[1] |
1146 |
1 |
|
|
T2 |
1 |
|
T23 |
1 |
|
T18 |
4 |
auto[1] |
auto[0] |
16904 |
1 |
|
|
T4 |
6 |
|
T5 |
80 |
|
T16 |
63 |
auto[1] |
auto[1] |
932 |
1 |
|
|
T5 |
5 |
|
T27 |
9 |
|
T18 |
8 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37754 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T3 |
88 |
auto[0] |
auto[1] |
1155 |
1 |
|
|
T1 |
1 |
|
T23 |
1 |
|
T18 |
1 |
auto[1] |
auto[0] |
16882 |
1 |
|
|
T4 |
6 |
|
T5 |
76 |
|
T16 |
63 |
auto[1] |
auto[1] |
954 |
1 |
|
|
T5 |
9 |
|
T27 |
8 |
|
T18 |
13 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37742 |
1 |
|
|
T1 |
11 |
|
T2 |
12 |
|
T3 |
88 |
auto[0] |
auto[1] |
1167 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T18 |
3 |
auto[1] |
auto[0] |
16942 |
1 |
|
|
T4 |
6 |
|
T5 |
77 |
|
T16 |
63 |
auto[1] |
auto[1] |
894 |
1 |
|
|
T5 |
8 |
|
T27 |
8 |
|
T18 |
9 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37760 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T3 |
88 |
auto[0] |
auto[1] |
1149 |
1 |
|
|
T1 |
1 |
|
T23 |
1 |
|
T18 |
1 |
auto[1] |
auto[0] |
16925 |
1 |
|
|
T4 |
6 |
|
T5 |
80 |
|
T16 |
63 |
auto[1] |
auto[1] |
911 |
1 |
|
|
T5 |
5 |
|
T27 |
5 |
|
T18 |
7 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37764 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[0] |
auto[1] |
1145 |
1 |
|
|
T25 |
13 |
|
T37 |
2 |
|
T40 |
1 |
auto[1] |
auto[0] |
16903 |
1 |
|
|
T4 |
6 |
|
T5 |
75 |
|
T16 |
63 |
auto[1] |
auto[1] |
933 |
1 |
|
|
T5 |
10 |
|
T27 |
4 |
|
T18 |
8 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37708 |
1 |
|
|
T1 |
11 |
|
T2 |
13 |
|
T3 |
88 |
auto[0] |
auto[1] |
1201 |
1 |
|
|
T1 |
1 |
|
T23 |
1 |
|
T18 |
5 |
auto[1] |
auto[0] |
16904 |
1 |
|
|
T4 |
6 |
|
T5 |
75 |
|
T16 |
63 |
auto[1] |
auto[1] |
932 |
1 |
|
|
T5 |
10 |
|
T27 |
2 |
|
T18 |
5 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37662 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[0] |
auto[1] |
1247 |
1 |
|
|
T18 |
32 |
|
T25 |
16 |
|
T46 |
22 |
auto[1] |
auto[0] |
17046 |
1 |
|
|
T4 |
6 |
|
T5 |
85 |
|
T16 |
51 |
auto[1] |
auto[1] |
790 |
1 |
|
|
T16 |
12 |
|
T17 |
3 |
|
T18 |
36 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37659 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T3 |
88 |
auto[0] |
auto[1] |
1250 |
1 |
|
|
T18 |
23 |
|
T25 |
16 |
|
T46 |
12 |
auto[1] |
auto[0] |
17086 |
1 |
|
|
T4 |
6 |
|
T5 |
85 |
|
T16 |
54 |
auto[1] |
auto[1] |
750 |
1 |
|
|
T16 |
9 |
|
T17 |
11 |
|
T18 |
26 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
37223 |
1 |
|
|
T3 |
88 |
|
T10 |
97 |
|
T11 |
14 |
auto[0] |
auto[1] |
1686 |
1 |
|
|
T1 |
12 |
|
T2 |
13 |
|
T23 |
12 |
auto[1] |
auto[0] |
16761 |
1 |
|
|
T4 |
6 |
|
T5 |
85 |
|
T16 |
63 |
auto[1] |
auto[1] |
1075 |
1 |
|
|
T39 |
15 |
|
T47 |
13 |
|
T19 |
15 |