Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119015606

1

T1

4845

T2

7574

T3

19900

auto[1]

1477818

1

T1

198

T3

10301

T10

10015

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

119033575

1

T1

4845

T2

7376

T3

20242

auto[1]

1459849

1

T1

198

T2

198

T3

9959

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	8048904	1			T1	1233		T2	1466		T3	10440
auto[IdleSt]	24746750	1			T1	1150		T2	979		T3	2903
auto[ClkMuxSt]	36845	1			T1	7		T2	8		T3	82
auto[CntIncrSt]	36566	1			T1	7		T2	8		T3	81
auto[CntProgSt]	1714281	1			T1	115		T2	1401		T3	1542
auto[TransCheckSt]	28651	1			T1	7		T2	8		T3	32
auto[TokenHashSt]	48266759	1			T1	177		T2	404		T3	296
auto[FlashRmaSt]	29586	1			T1	7		T2	8		T3	37
auto[TokenCheck0St]	13229	1			T1	7		T2	8		T3	25
auto[TokenCheck1St]	9779	1			T1	7		T2	8		T3	25
auto[TransProgSt]	457953	1			T1	145		T2	1413		T3	50
auto[PostTransSt]	14570065	1			T1	1167		T2	1362		T3	2
auto[ScrapSt]	169381	1			T3	3		T10	3		T15	68
auto[EscalateSt]	7776200	1			T1	743		T2	325		T3	14683
auto[InvalidSt]	14586344	1			T1	270		T2	175		T5	176497

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2131	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	14586344	1			T1	270		T2	175		T5	176497
EscalateSt	7776200	1			T1	743		T2	325		T3	14683
ScrapSt	169381	1			T3	3		T10	3		T15	68
PostTransSt	14570065	1			T1	1167		T2	1362		T3	2
TransProgSt	457953	1			T1	145		T2	1413		T3	50
TokenCheck1St	9779	1			T1	7		T2	8		T3	25
TokenCheck0St	13229	1			T1	7		T2	8		T3	25
FlashRmaSt	29586	1			T1	7		T2	8		T3	37
TokenHashSt	48266759	1			T1	177		T2	404		T3	296
TransCheckSt	28651	1			T1	7		T2	8		T3	32
CntProgSt	1714281	1			T1	115		T2	1401		T3	1542
CntIncrSt	36566	1			T1	7		T2	8		T3	81
ClkMuxSt	36845	1			T1	7		T2	8		T3	82
IdleSt	24746750	1			T1	1150		T2	979		T3	2903
ResetSt	8048904	1			T1	1233		T2	1466		T3	10440
arcs[ResetSt=>IdleSt]	56935	1			T1	12		T2	12		T3	84
arcs[IdleSt=>ScrapSt]	273	1			T3	1		T10	1		T15	2
arcs[IdleSt=>ClkMuxSt]	36620	1			T1	7		T2	8		T3	82
arcs[ClkMuxSt=>CntIncrSt]	36566	1			T1	7		T2	8		T3	81
arcs[CntIncrSt=>PostTransSt]	2004	1			T16	9		T17	11		T18	49
arcs[CntIncrSt=>CntProgSt]	34497	1			T1	7		T2	8		T3	77
arcs[CntProgSt=>PostTransSt]	4806	1			T16	4		T17	8		T18	93
arcs[CntProgSt=>TransCheckSt]	28651	1			T1	7		T2	8		T3	32
arcs[TransCheckSt=>PostTransSt]	3915	1			T12	40		T16	12		T17	3
arcs[TransCheckSt=>TokenHashSt]	24598	1			T1	7		T2	8		T3	32
arcs[TokenHashSt=>PostTransSt]	10581	1			T12	8		T14	63		T21	1
arcs[TokenHashSt=>FlashRmaSt]	13324	1			T1	7		T2	8		T3	25
arcs[FlashRmaSt=>TokenCheck0St]	13229	1			T1	7		T2	8		T3	25
arcs[TokenCheck0St=>PostTransSt]	3424	1			T12	19		T16	5		T17	5
arcs[TokenCheck0St=>TokenCheck1St]	9779	1			T1	7		T2	8		T3	25
arcs[TokenCheck1St=>PostTransSt]	683	1			T12	8		T17	1		T24	8
arcs[TransProgSt=>PostTransSt]	8222	1			T1	7		T2	8		T3	1
arcs[IdleSt=>EscalateSt]	206	1			T49	6		T50	6		T51	5
arcs[ClkMuxSt=>EscalateSt]	54	1			T3	1		T49	2		T50	1
arcs[CntIncrSt=>EscalateSt]	65	1			T3	4		T49	1		T50	1
arcs[CntProgSt=>EscalateSt]	1040	1			T3	45		T10	8		T49	34
arcs[TransCheckSt=>EscalateSt]	138	1			T10	7		T51	1		T56	3
arcs[TokenHashSt=>EscalateSt]	693	1			T3	7		T10	36		T18	1
arcs[FlashRmaSt=>EscalateSt]	95	1			T10	2		T49	2		T50	4
arcs[TokenCheck0St=>EscalateSt]	26	1			T10	1		T51	1		T55	2
arcs[TokenCheck1St=>EscalateSt]	171	1			T3	4		T10	5		T49	5
arcs[TransProgSt=>EscalateSt]	703	1			T3	20		T10	12		T49	25
arcs[PostTransSt=>EscalateSt]	5048	1			T3	1		T10	17		T16	4
arcs[InvalidSt=>EscalateSt]	15417	1			T1	4		T2	2		T5	64

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8048742	1			T1	1233		T2	1466		T3	10438
auto[0]	auto[IdleSt]	24746620	1			T1	1150		T2	979		T3	2903
auto[0]	auto[ClkMuxSt]	36805	1			T1	7		T2	8		T3	81
auto[0]	auto[CntIncrSt]	36523	1			T1	7		T2	8		T3	78
auto[0]	auto[CntProgSt]	1713596	1			T1	115		T2	1401		T3	1508
auto[0]	auto[TransCheckSt]	28556	1			T1	7		T2	8		T3	32
auto[0]	auto[TokenHashSt]	48266291	1			T1	177		T2	404		T3	292
auto[0]	auto[FlashRmaSt]	29521	1			T1	7		T2	8		T3	37
auto[0]	auto[TokenCheck0St]	13214	1			T1	7		T2	8		T3	25
auto[0]	auto[TokenCheck1St]	9659	1			T1	7		T2	8		T3	22
auto[0]	auto[TransProgSt]	457471	1			T1	145		T2	1413		T3	37
auto[0]	auto[PostTransSt]	14567475	1			T1	1167		T2	1362		T3	1
auto[0]	auto[ScrapSt]	169346	1			T3	3		T10	2		T15	68
auto[0]	auto[EscalateSt]	6311050	1			T1	547		T2	325		T3	4443
auto[0]	auto[InvalidSt]	14578606	1			T1	268		T2	175		T5	176462
auto[1]	auto[ResetSt]	162	1			T3	2		T10	6		T49	4
auto[1]	auto[IdleSt]	130	1			T49	2		T50	5		T51	3
auto[1]	auto[ClkMuxSt]	40	1			T3	1		T49	1		T50	1
auto[1]	auto[CntIncrSt]	43	1			T3	3		T51	1		T55	1
auto[1]	auto[CntProgSt]	685	1			T3	34		T10	5		T49	24
auto[1]	auto[TransCheckSt]	95	1			T10	3		T51	1		T56	1
auto[1]	auto[TokenHashSt]	468	1			T3	4		T10	25		T18	1
auto[1]	auto[FlashRmaSt]	65	1			T10	1		T49	2		T50	3
auto[1]	auto[TokenCheck0St]	15	1			T10	1		T55	2		T211	1
auto[1]	auto[TokenCheck1St]	120	1			T3	3		T10	4		T49	2
auto[1]	auto[TransProgSt]	482	1			T3	13		T10	7		T49	19
auto[1]	auto[PostTransSt]	2590	1			T3	1		T10	9		T16	2
auto[1]	auto[ScrapSt]	35	1			T10	1		T50	1		T212	1
auto[1]	auto[EscalateSt]	1465150	1			T1	196		T3	10240		T10	9953
auto[1]	auto[InvalidSt]	7738	1			T1	2		T5	35		T23	2

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	8048733	1			T1	1233		T2	1466		T3	10436
auto[0]	auto[IdleSt]	24746604	1			T1	1150		T2	979		T3	2903
auto[0]	auto[ClkMuxSt]	36815	1			T1	7		T2	8		T3	81
auto[0]	auto[CntIncrSt]	36523	1			T1	7		T2	8		T3	78
auto[0]	auto[CntProgSt]	1713599	1			T1	115		T2	1401		T3	1513
auto[0]	auto[TransCheckSt]	28560	1			T1	7		T2	8		T3	32
auto[0]	auto[TokenHashSt]	48266316	1			T1	177		T2	404		T3	292
auto[0]	auto[FlashRmaSt]	29521	1			T1	7		T2	8		T3	37
auto[0]	auto[TokenCheck0St]	13212	1			T1	7		T2	8		T3	25
auto[0]	auto[TokenCheck1St]	9666	1			T1	7		T2	8		T3	23
auto[0]	auto[TransProgSt]	457497	1			T1	145		T2	1413		T3	36
auto[0]	auto[PostTransSt]	14567535	1			T1	1167		T2	1362		T3	1
auto[0]	auto[ScrapSt]	169349	1			T3	2		T10	3		T15	68
auto[0]	auto[EscalateSt]	6328849	1			T1	547		T2	129		T3	4783
auto[0]	auto[InvalidSt]	14578665	1			T1	268		T2	173		T5	176468
auto[1]	auto[ResetSt]	171	1			T3	4		T10	4		T49	4
auto[1]	auto[IdleSt]	146	1			T49	5		T50	3		T51	4
auto[1]	auto[ClkMuxSt]	30	1			T3	1		T49	1		T50	1
auto[1]	auto[CntIncrSt]	43	1			T3	3		T49	1		T50	1
auto[1]	auto[CntProgSt]	682	1			T3	29		T10	7		T49	27
auto[1]	auto[TransCheckSt]	91	1			T10	5		T51	1		T56	2
auto[1]	auto[TokenHashSt]	443	1			T3	4		T10	17		T25	2
auto[1]	auto[FlashRmaSt]	65	1			T10	1		T49	1		T50	2
auto[1]	auto[TokenCheck0St]	17	1			T10	1		T51	1		T211	1
auto[1]	auto[TokenCheck1St]	113	1			T3	2		T10	4		T49	5
auto[1]	auto[TransProgSt]	456	1			T3	14		T10	8		T49	18
auto[1]	auto[PostTransSt]	2530	1			T3	1		T10	14		T16	2
auto[1]	auto[ScrapSt]	32	1			T3	1		T212	1		T211	1
auto[1]	auto[EscalateSt]	1447351	1			T1	196		T2	196		T3	9900
auto[1]	auto[InvalidSt]	7679	1			T1	2		T2	2		T5	29