Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52831 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[1] |
1834 |
1 |
|
|
T10 |
10 |
|
T11 |
6 |
|
T12 |
10 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53942 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[1] |
723 |
1 |
|
|
T23 |
9 |
|
T37 |
24 |
|
T59 |
15 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52696 |
1 |
|
|
T2 |
53 |
|
T3 |
9 |
|
T4 |
11 |
auto[1] |
1969 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T25 |
6 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52728 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[1] |
1937 |
1 |
|
|
T25 |
5 |
|
T17 |
7 |
|
T26 |
15 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52718 |
1 |
|
|
T2 |
53 |
|
T3 |
9 |
|
T4 |
9 |
auto[1] |
1947 |
1 |
|
|
T3 |
1 |
|
T4 |
3 |
|
T25 |
8 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
49769 |
1 |
|
|
T2 |
53 |
|
T3 |
6 |
|
T4 |
9 |
no_err_inj |
4896 |
1 |
|
|
T3 |
4 |
|
T4 |
3 |
|
T5 |
18 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52880 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[1] |
1785 |
1 |
|
|
T10 |
11 |
|
T11 |
4 |
|
T12 |
13 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53976 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[1] |
689 |
1 |
|
|
T23 |
13 |
|
T37 |
18 |
|
T59 |
18 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
36854 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[1] |
17811 |
1 |
|
|
T5 |
18 |
|
T10 |
71 |
|
T17 |
55 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52754 |
1 |
|
|
T2 |
53 |
|
T3 |
9 |
|
T4 |
10 |
auto[1] |
1911 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T25 |
4 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52704 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
11 |
auto[1] |
1961 |
1 |
|
|
T4 |
1 |
|
T25 |
6 |
|
T17 |
7 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52691 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[1] |
1974 |
1 |
|
|
T25 |
5 |
|
T17 |
12 |
|
T26 |
9 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52851 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[1] |
1814 |
1 |
|
|
T10 |
10 |
|
T11 |
6 |
|
T12 |
12 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51805 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[1] |
2860 |
1 |
|
|
T9 |
11 |
|
T27 |
12 |
|
T58 |
18 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53927 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[1] |
738 |
1 |
|
|
T23 |
15 |
|
T37 |
19 |
|
T59 |
21 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53903 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[1] |
762 |
1 |
|
|
T23 |
18 |
|
T37 |
12 |
|
T59 |
15 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
53962 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[1] |
703 |
1 |
|
|
T23 |
12 |
|
T37 |
20 |
|
T59 |
19 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
51668 |
1 |
|
|
T2 |
53 |
|
T5 |
18 |
|
T9 |
11 |
auto[1] |
2997 |
1 |
|
|
T3 |
10 |
|
T4 |
12 |
|
T17 |
13 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50968 |
1 |
|
|
T3 |
10 |
|
T4 |
12 |
|
T5 |
18 |
auto[1] |
3697 |
1 |
|
|
T2 |
53 |
|
T16 |
82 |
|
T35 |
67 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52697 |
1 |
|
|
T2 |
53 |
|
T3 |
9 |
|
T4 |
11 |
auto[1] |
1968 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T25 |
10 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52684 |
1 |
|
|
T2 |
53 |
|
T3 |
9 |
|
T4 |
11 |
auto[1] |
1981 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T25 |
3 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52687 |
1 |
|
|
T2 |
53 |
|
T3 |
9 |
|
T4 |
12 |
auto[1] |
1978 |
1 |
|
|
T3 |
1 |
|
T25 |
6 |
|
T17 |
4 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52806 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[1] |
1859 |
1 |
|
|
T10 |
9 |
|
T11 |
5 |
|
T12 |
11 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
49091 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[1] |
5574 |
1 |
|
|
T10 |
6 |
|
T11 |
4 |
|
T52 |
54 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
50969 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[1] |
3696 |
1 |
|
|
T18 |
99 |
|
T50 |
63 |
|
T14 |
87 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
54665 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52892 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[1] |
1773 |
1 |
|
|
T10 |
7 |
|
T11 |
7 |
|
T12 |
15 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52841 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[1] |
1824 |
1 |
|
|
T10 |
7 |
|
T11 |
14 |
|
T12 |
7 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
52853 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[1] |
1812 |
1 |
|
|
T10 |
11 |
|
T11 |
7 |
|
T12 |
14 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
48285 |
1 |
|
|
T2 |
53 |
|
T9 |
11 |
|
T10 |
71 |
auto[0] |
no_err_inj |
3383 |
1 |
|
|
T5 |
18 |
|
T17 |
7 |
|
T24 |
8 |
auto[1] |
err_inj |
1484 |
1 |
|
|
T3 |
6 |
|
T4 |
9 |
|
T17 |
5 |
auto[1] |
no_err_inj |
1513 |
1 |
|
|
T3 |
4 |
|
T4 |
3 |
|
T17 |
8 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49859 |
1 |
|
|
T2 |
53 |
|
T5 |
18 |
|
T9 |
11 |
auto[0] |
auto[1] |
1809 |
1 |
|
|
T25 |
3 |
|
T17 |
8 |
|
T26 |
8 |
auto[1] |
auto[0] |
2825 |
1 |
|
|
T3 |
9 |
|
T4 |
11 |
|
T17 |
13 |
auto[1] |
auto[1] |
172 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T24 |
1 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49876 |
1 |
|
|
T2 |
53 |
|
T5 |
18 |
|
T9 |
11 |
auto[0] |
auto[1] |
1792 |
1 |
|
|
T25 |
6 |
|
T17 |
7 |
|
T26 |
7 |
auto[1] |
auto[0] |
2828 |
1 |
|
|
T3 |
10 |
|
T4 |
11 |
|
T17 |
13 |
auto[1] |
auto[1] |
169 |
1 |
|
|
T4 |
1 |
|
T24 |
2 |
|
T220 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49876 |
1 |
|
|
T2 |
53 |
|
T5 |
18 |
|
T9 |
11 |
auto[0] |
auto[1] |
1792 |
1 |
|
|
T25 |
6 |
|
T17 |
4 |
|
T26 |
10 |
auto[1] |
auto[0] |
2811 |
1 |
|
|
T3 |
9 |
|
T4 |
12 |
|
T17 |
13 |
auto[1] |
auto[1] |
186 |
1 |
|
|
T3 |
1 |
|
T24 |
2 |
|
T82 |
3 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49896 |
1 |
|
|
T2 |
53 |
|
T5 |
18 |
|
T9 |
11 |
auto[0] |
auto[1] |
1772 |
1 |
|
|
T25 |
5 |
|
T17 |
6 |
|
T26 |
15 |
auto[1] |
auto[0] |
2832 |
1 |
|
|
T3 |
10 |
|
T4 |
12 |
|
T17 |
12 |
auto[1] |
auto[1] |
165 |
1 |
|
|
T17 |
1 |
|
T24 |
1 |
|
T82 |
1 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49881 |
1 |
|
|
T2 |
53 |
|
T5 |
18 |
|
T9 |
11 |
auto[0] |
auto[1] |
1787 |
1 |
|
|
T25 |
8 |
|
T17 |
4 |
|
T26 |
11 |
auto[1] |
auto[0] |
2837 |
1 |
|
|
T3 |
9 |
|
T4 |
9 |
|
T17 |
13 |
auto[1] |
auto[1] |
160 |
1 |
|
|
T3 |
1 |
|
T4 |
3 |
|
T24 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
49853 |
1 |
|
|
T2 |
53 |
|
T5 |
18 |
|
T9 |
11 |
auto[0] |
auto[1] |
1815 |
1 |
|
|
T25 |
6 |
|
T17 |
4 |
|
T26 |
10 |
auto[1] |
auto[0] |
2843 |
1 |
|
|
T3 |
9 |
|
T4 |
11 |
|
T17 |
12 |
auto[1] |
auto[1] |
154 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T17 |
1 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35820 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[0] |
auto[1] |
1034 |
1 |
|
|
T11 |
6 |
|
T51 |
8 |
|
T221 |
8 |
auto[1] |
auto[0] |
17011 |
1 |
|
|
T5 |
18 |
|
T10 |
61 |
|
T17 |
55 |
auto[1] |
auto[1] |
800 |
1 |
|
|
T10 |
10 |
|
T12 |
10 |
|
T83 |
8 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35858 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[0] |
auto[1] |
996 |
1 |
|
|
T11 |
4 |
|
T51 |
7 |
|
T221 |
5 |
auto[1] |
auto[0] |
17022 |
1 |
|
|
T5 |
18 |
|
T10 |
60 |
|
T17 |
55 |
auto[1] |
auto[1] |
789 |
1 |
|
|
T10 |
11 |
|
T12 |
13 |
|
T83 |
7 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35119 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[0] |
auto[1] |
1735 |
1 |
|
|
T9 |
11 |
|
T222 |
13 |
|
T36 |
25 |
auto[1] |
auto[0] |
16686 |
1 |
|
|
T5 |
18 |
|
T10 |
71 |
|
T17 |
55 |
auto[1] |
auto[1] |
1125 |
1 |
|
|
T27 |
12 |
|
T58 |
18 |
|
T36 |
8 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35816 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[0] |
auto[1] |
1038 |
1 |
|
|
T11 |
6 |
|
T51 |
5 |
|
T221 |
5 |
auto[1] |
auto[0] |
17035 |
1 |
|
|
T5 |
18 |
|
T10 |
61 |
|
T17 |
55 |
auto[1] |
auto[1] |
776 |
1 |
|
|
T10 |
10 |
|
T12 |
12 |
|
T83 |
3 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
32112 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[0] |
auto[1] |
4742 |
1 |
|
|
T11 |
4 |
|
T52 |
54 |
|
T223 |
92 |
auto[1] |
auto[0] |
16979 |
1 |
|
|
T5 |
18 |
|
T10 |
65 |
|
T17 |
55 |
auto[1] |
auto[1] |
832 |
1 |
|
|
T10 |
6 |
|
T12 |
15 |
|
T83 |
7 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35794 |
1 |
|
|
T2 |
53 |
|
T3 |
9 |
|
T4 |
11 |
auto[0] |
auto[1] |
1060 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T25 |
3 |
auto[1] |
auto[0] |
16890 |
1 |
|
|
T5 |
18 |
|
T10 |
71 |
|
T17 |
47 |
auto[1] |
auto[1] |
921 |
1 |
|
|
T17 |
8 |
|
T26 |
8 |
|
T220 |
1 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35823 |
1 |
|
|
T2 |
53 |
|
T3 |
9 |
|
T4 |
11 |
auto[0] |
auto[1] |
1031 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T25 |
10 |
auto[1] |
auto[0] |
16874 |
1 |
|
|
T5 |
18 |
|
T10 |
71 |
|
T17 |
49 |
auto[1] |
auto[1] |
937 |
1 |
|
|
T17 |
6 |
|
T26 |
13 |
|
T224 |
1 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35780 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
11 |
auto[0] |
auto[1] |
1074 |
1 |
|
|
T4 |
1 |
|
T25 |
6 |
|
T24 |
11 |
auto[1] |
auto[0] |
16924 |
1 |
|
|
T5 |
18 |
|
T10 |
71 |
|
T17 |
48 |
auto[1] |
auto[1] |
887 |
1 |
|
|
T17 |
7 |
|
T26 |
7 |
|
T220 |
1 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35884 |
1 |
|
|
T2 |
53 |
|
T3 |
9 |
|
T4 |
10 |
auto[0] |
auto[1] |
970 |
1 |
|
|
T3 |
1 |
|
T4 |
2 |
|
T25 |
4 |
auto[1] |
auto[0] |
16870 |
1 |
|
|
T5 |
18 |
|
T10 |
71 |
|
T17 |
49 |
auto[1] |
auto[1] |
941 |
1 |
|
|
T17 |
6 |
|
T26 |
12 |
|
T224 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35784 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[0] |
auto[1] |
1070 |
1 |
|
|
T25 |
5 |
|
T17 |
1 |
|
T24 |
15 |
auto[1] |
auto[0] |
16944 |
1 |
|
|
T5 |
18 |
|
T10 |
71 |
|
T17 |
49 |
auto[1] |
auto[1] |
867 |
1 |
|
|
T17 |
6 |
|
T26 |
15 |
|
T220 |
1 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35801 |
1 |
|
|
T2 |
53 |
|
T3 |
9 |
|
T4 |
11 |
auto[0] |
auto[1] |
1053 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T25 |
6 |
auto[1] |
auto[0] |
16895 |
1 |
|
|
T5 |
18 |
|
T10 |
71 |
|
T17 |
51 |
auto[1] |
auto[1] |
916 |
1 |
|
|
T17 |
4 |
|
T26 |
10 |
|
T220 |
1 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35881 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[0] |
auto[1] |
973 |
1 |
|
|
T11 |
7 |
|
T51 |
5 |
|
T221 |
9 |
auto[1] |
auto[0] |
16972 |
1 |
|
|
T5 |
18 |
|
T10 |
60 |
|
T17 |
55 |
auto[1] |
auto[1] |
839 |
1 |
|
|
T10 |
11 |
|
T12 |
14 |
|
T83 |
9 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35833 |
1 |
|
|
T2 |
53 |
|
T3 |
10 |
|
T4 |
12 |
auto[0] |
auto[1] |
1021 |
1 |
|
|
T11 |
14 |
|
T51 |
8 |
|
T221 |
3 |
auto[1] |
auto[0] |
17008 |
1 |
|
|
T5 |
18 |
|
T10 |
64 |
|
T17 |
55 |
auto[1] |
auto[1] |
803 |
1 |
|
|
T10 |
7 |
|
T12 |
7 |
|
T83 |
5 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
35077 |
1 |
|
|
T2 |
53 |
|
T9 |
11 |
|
T25 |
53 |
auto[0] |
auto[1] |
1777 |
1 |
|
|
T3 |
10 |
|
T4 |
12 |
|
T17 |
13 |
auto[1] |
auto[0] |
16591 |
1 |
|
|
T5 |
18 |
|
T10 |
71 |
|
T17 |
55 |
auto[1] |
auto[1] |
1220 |
1 |
|
|
T220 |
13 |
|
T77 |
28 |
|
T224 |
12 |