Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102092622

1

T1

12539

T2

14544

T3

5007

auto[1]

1429549

1

T2

7632

T3

297

T4

495

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

102085993

1

T1

12539

T2

16453

T3

5106

auto[1]

1436178

1

T2

5723

T3

198

T4

396

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7781036	1			T1	79		T2	5349		T3	1060
auto[IdleSt]	23299631	1			T1	12460		T2	4392		T3	1087
auto[ClkMuxSt]	35937	1			T2	43		T3	4		T4	3
auto[CntIncrSt]	35649	1			T2	41		T3	4		T4	3
auto[CntProgSt]	1549657	1			T2	1519		T3	40		T4	6
auto[TransCheckSt]	27250	1			T2	20		T3	4		T4	3
auto[TokenHashSt]	36252734	1			T2	354		T3	85		T4	2369
auto[FlashRmaSt]	28361	1			T2	34		T3	4		T4	3
auto[TokenCheck0St]	12563	1			T2	13		T3	4		T4	3
auto[TokenCheck1St]	9380	1			T2	13		T3	4		T4	3
auto[TransProgSt]	354964	1			T2	24		T3	39		T4	6
auto[PostTransSt]	13808527	1			T3	1100		T4	528		T5	5443
auto[ScrapSt]	222921	1			T5	1026		T16	3		T35	3
auto[EscalateSt]	7279070	1			T2	10374		T3	1187		T4	1599
auto[InvalidSt]	12822456	1			T3	682		T4	685		T25	5695

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2035	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	12822456	1			T3	682		T4	685		T25	5695
EscalateSt	7279070	1			T2	10374		T3	1187		T4	1599
ScrapSt	222921	1			T5	1026		T16	3		T35	3
PostTransSt	13808527	1			T3	1100		T4	528		T5	5443
TransProgSt	354964	1			T2	24		T3	39		T4	6
TokenCheck1St	9380	1			T2	13		T3	4		T4	3
TokenCheck0St	12563	1			T2	13		T3	4		T4	3
FlashRmaSt	28361	1			T2	34		T3	4		T4	3
TokenHashSt	36252734	1			T2	354		T3	85		T4	2369
TransCheckSt	27250	1			T2	20		T3	4		T4	3
CntProgSt	1549657	1			T2	1519		T3	40		T4	6
CntIncrSt	35649	1			T2	41		T3	4		T4	3
ClkMuxSt	35937	1			T2	43		T3	4		T4	3
IdleSt	23299631	1			T1	12460		T2	4392		T3	1087
ResetSt	7781036	1			T1	79		T2	5349		T3	1060
arcs[ResetSt=>IdleSt]	54858	1			T1	1		T2	49		T3	11
arcs[IdleSt=>ScrapSt]	279	1			T5	2		T16	1		T35	1
arcs[IdleSt=>ClkMuxSt]	35704	1			T2	43		T3	4		T4	3
arcs[ClkMuxSt=>CntIncrSt]	35649	1			T2	41		T3	4		T4	3
arcs[CntIncrSt=>PostTransSt]	1825	1			T10	7		T11	14		T12	7
arcs[CntIncrSt=>CntProgSt]	33751	1			T2	40		T3	4		T4	3
arcs[CntProgSt=>PostTransSt]	5361	1			T9	11		T10	10		T23	9
arcs[CntProgSt=>TransCheckSt]	27250	1			T2	20		T3	4		T4	3
arcs[TransCheckSt=>PostTransSt]	3640	1			T10	11		T18	49		T11	7
arcs[TransCheckSt=>TokenHashSt]	23510	1			T2	20		T3	4		T4	3
arcs[TokenHashSt=>PostTransSt]	10185	1			T10	22		T13	1		T18	12
arcs[TokenHashSt=>FlashRmaSt]	12647	1			T2	14		T3	4		T4	3
arcs[FlashRmaSt=>TokenCheck0St]	12563	1			T2	13		T3	4		T4	3
arcs[TokenCheck0St=>PostTransSt]	3158	1			T10	11		T18	28		T23	11
arcs[TokenCheck0St=>TokenCheck1St]	9380	1			T2	13		T3	4		T4	3
arcs[TokenCheck1St=>PostTransSt]	656	1			T18	10		T50	4		T51	1
arcs[TransProgSt=>PostTransSt]	7871	1			T3	4		T4	3		T5	16
arcs[IdleSt=>EscalateSt]	174	1			T2	5		T16	8		T44	5
arcs[ClkMuxSt=>EscalateSt]	55	1			T2	2		T16	2		T35	1
arcs[CntIncrSt=>EscalateSt]	73	1			T2	1		T16	3		T35	2
arcs[CntProgSt=>EscalateSt]	1140	1			T2	20		T16	17		T35	23
arcs[TransCheckSt=>EscalateSt]	100	1			T16	8		T35	1		T48	2
arcs[TokenHashSt=>EscalateSt]	678	1			T2	6		T16	20		T35	11
arcs[FlashRmaSt=>EscalateSt]	84	1			T2	1		T16	3		T44	1
arcs[TokenCheck0St=>EscalateSt]	25	1			T48	2		T21	2		T49	2
arcs[TokenCheck1St=>EscalateSt]	132	1			T2	3		T16	2		T35	3
arcs[TransProgSt=>EscalateSt]	721	1			T2	10		T16	8		T35	22
arcs[PostTransSt=>EscalateSt]	5598	1			T9	11		T10	10		T16	6
arcs[InvalidSt=>EscalateSt]	14450	1			T3	5		T4	9		T25	42

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7780852	1			T1	79		T2	5346		T3	1060
auto[0]	auto[IdleSt]	23299514	1			T1	12460		T2	4387		T3	1087
auto[0]	auto[ClkMuxSt]	35899	1			T2	41		T3	4		T4	3
auto[0]	auto[CntIncrSt]	35599	1			T2	41		T3	4		T4	3
auto[0]	auto[CntProgSt]	1548902	1			T2	1505		T3	40		T4	6
auto[0]	auto[TransCheckSt]	27188	1			T2	20		T3	4		T4	3
auto[0]	auto[TokenHashSt]	36252294	1			T2	350		T3	85		T4	2369
auto[0]	auto[FlashRmaSt]	28307	1			T2	34		T3	4		T4	3
auto[0]	auto[TokenCheck0St]	12547	1			T2	13		T3	4		T4	3
auto[0]	auto[TokenCheck1St]	9291	1			T2	11		T3	4		T4	3
auto[0]	auto[TransProgSt]	354469	1			T2	15		T3	39		T4	6
auto[0]	auto[PostTransSt]	13805657	1			T3	1100		T4	528		T5	5443
auto[0]	auto[ScrapSt]	222885	1			T5	1026		T16	2		T35	2
auto[0]	auto[EscalateSt]	5861869	1			T2	2781		T3	893		T4	1109
auto[0]	auto[InvalidSt]	12815314	1			T3	679		T4	680		T25	5668
auto[1]	auto[ResetSt]	184	1			T2	3		T16	1		T35	2
auto[1]	auto[IdleSt]	117	1			T2	5		T16	4		T44	3
auto[1]	auto[ClkMuxSt]	38	1			T2	2		T35	1		T48	1
auto[1]	auto[CntIncrSt]	50	1			T16	2		T35	2		T44	1
auto[1]	auto[CntProgSt]	755	1			T2	14		T16	6		T35	16
auto[1]	auto[TransCheckSt]	62	1			T16	6		T48	1		T21	1
auto[1]	auto[TokenHashSt]	440	1			T2	4		T16	14		T35	5
auto[1]	auto[FlashRmaSt]	54	1			T16	3		T21	3		T49	2
auto[1]	auto[TokenCheck0St]	16	1			T48	2		T21	1		T49	1
auto[1]	auto[TokenCheck1St]	89	1			T2	2		T16	1		T35	2
auto[1]	auto[TransProgSt]	495	1			T2	9		T16	5		T35	16
auto[1]	auto[PostTransSt]	2870	1			T9	6		T10	7		T16	4
auto[1]	auto[ScrapSt]	36	1			T16	1		T35	1		T219	1
auto[1]	auto[EscalateSt]	1417201	1			T2	7593		T3	294		T4	490
auto[1]	auto[InvalidSt]	7142	1			T3	3		T4	5		T25	27

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7780849	1			T1	79		T2	5346		T3	1060
auto[0]	auto[IdleSt]	23299525	1			T1	12460		T2	4390		T3	1087
auto[0]	auto[ClkMuxSt]	35895	1			T2	42		T3	4		T4	3
auto[0]	auto[CntIncrSt]	35600	1			T2	40		T3	4		T4	3
auto[0]	auto[CntProgSt]	1548896	1			T2	1509		T3	40		T4	6
auto[0]	auto[TransCheckSt]	27187	1			T2	20		T3	4		T4	3
auto[0]	auto[TokenHashSt]	36252285	1			T2	350		T3	85		T4	2369
auto[0]	auto[FlashRmaSt]	28304	1			T2	33		T3	4		T4	3
auto[0]	auto[TokenCheck0St]	12546	1			T2	13		T3	4		T4	3
auto[0]	auto[TokenCheck1St]	9290	1			T2	11		T3	4		T4	3
auto[0]	auto[TransProgSt]	354489	1			T2	19		T3	39		T4	6
auto[0]	auto[PostTransSt]	13805742	1			T3	1100		T4	528		T5	5443
auto[0]	auto[ScrapSt]	222884	1			T5	1026		T16	2		T35	3
auto[0]	auto[EscalateSt]	5855318	1			T2	4680		T3	991		T4	1207
auto[0]	auto[InvalidSt]	12815148	1			T3	680		T4	681		T25	5680
auto[1]	auto[ResetSt]	187	1			T2	3		T16	4		T35	2
auto[1]	auto[IdleSt]	106	1			T2	2		T16	5		T44	5
auto[1]	auto[ClkMuxSt]	42	1			T2	1		T16	2		T48	1
auto[1]	auto[CntIncrSt]	49	1			T2	1		T16	1		T35	1
auto[1]	auto[CntProgSt]	761	1			T2	10		T16	12		T35	20
auto[1]	auto[TransCheckSt]	63	1			T16	2		T35	1		T48	2
auto[1]	auto[TokenHashSt]	449	1			T2	4		T16	16		T35	9
auto[1]	auto[FlashRmaSt]	57	1			T2	1		T16	1		T44	1
auto[1]	auto[TokenCheck0St]	17	1			T48	1		T21	2		T49	2
auto[1]	auto[TokenCheck1St]	90	1			T2	2		T16	1		T35	2
auto[1]	auto[TransProgSt]	475	1			T2	5		T16	6		T35	17
auto[1]	auto[PostTransSt]	2785	1			T9	5		T10	3		T16	3
auto[1]	auto[ScrapSt]	37	1			T16	1		T44	1		T48	1
auto[1]	auto[EscalateSt]	1423752	1			T2	5694		T3	196		T4	392
auto[1]	auto[InvalidSt]	7308	1			T3	2		T4	4		T25	15