Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.18 97.82 95.84 93.31 100.00 98.52 98.51 96.29


Total test records in report: 1004
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T133 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4153547117 Jun 02 03:05:50 PM PDT 24 Jun 02 03:05:54 PM PDT 24 484033954 ps
T1003 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1151052739 Jun 02 03:05:48 PM PDT 24 Jun 02 03:05:49 PM PDT 24 53759756 ps
T127 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1167449762 Jun 02 03:06:00 PM PDT 24 Jun 02 03:06:03 PM PDT 24 229762037 ps
T1004 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3035794934 Jun 02 03:05:36 PM PDT 24 Jun 02 03:05:38 PM PDT 24 30664826 ps

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1611997279
Short name T10
Test name
Test status
Simulation time 8012351812 ps
CPU time 58 seconds
Started Jun 02 03:12:20 PM PDT 24
Finished Jun 02 03:13:19 PM PDT 24
Peak memory 219996 kb
Host smart-92697384-e1c1-457a-8046-f528238a76bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611997279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1611997279
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3762318464
Short name T16
Test name
Test status
Simulation time 1245482060 ps
CPU time 8.8 seconds
Started Jun 02 03:13:18 PM PDT 24
Finished Jun 02 03:13:27 PM PDT 24
Peak memory 218540 kb
Host smart-499542c4-3229-4928-a2a3-e14778fd2d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762318464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3762318464
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1068397131
Short name T25
Test name
Test status
Simulation time 983049648 ps
CPU time 22.01 seconds
Started Jun 02 03:15:09 PM PDT 24
Finished Jun 02 03:15:32 PM PDT 24
Peak memory 251324 kb
Host smart-f37ba5fd-3ace-429b-b144-672920ec1542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068397131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1068397131
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.842612353
Short name T24
Test name
Test status
Simulation time 3324916287 ps
CPU time 100.91 seconds
Started Jun 02 03:12:09 PM PDT 24
Finished Jun 02 03:13:51 PM PDT 24
Peak memory 267784 kb
Host smart-2df200da-b315-428a-8a9b-6e4dc76c914c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842612353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.842612353
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.859061662
Short name T37
Test name
Test status
Simulation time 300696942 ps
CPU time 16.15 seconds
Started Jun 02 03:13:38 PM PDT 24
Finished Jun 02 03:13:54 PM PDT 24
Peak memory 218512 kb
Host smart-e5915aba-5839-4f07-90fa-ef8741704cff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859061662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.859061662
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.1655540175
Short name T79
Test name
Test status
Simulation time 29119718779 ps
CPU time 589.21 seconds
Started Jun 02 03:14:34 PM PDT 24
Finished Jun 02 03:24:24 PM PDT 24
Peak memory 541904 kb
Host smart-01b5739f-39e2-4102-ae73-3240cbdaf4b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1655540175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.1655540175
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2049698193
Short name T108
Test name
Test status
Simulation time 24109038 ps
CPU time 1.76 seconds
Started Jun 02 03:05:39 PM PDT 24
Finished Jun 02 03:05:41 PM PDT 24
Peak memory 219948 kb
Host smart-13225d18-5ec9-44ce-8bae-f9d623cade42
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049698193 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2049698193
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.1355402023
Short name T15
Test name
Test status
Simulation time 99088970133 ps
CPU time 377.71 seconds
Started Jun 02 03:14:39 PM PDT 24
Finished Jun 02 03:20:57 PM PDT 24
Peak memory 316984 kb
Host smart-27ffbed9-0871-4786-b522-c5c8a7c9eb1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355402023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.1355402023
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.1315129826
Short name T91
Test name
Test status
Simulation time 712152565 ps
CPU time 26.94 seconds
Started Jun 02 03:12:20 PM PDT 24
Finished Jun 02 03:12:49 PM PDT 24
Peak memory 282976 kb
Host smart-9da1a0aa-cd43-422d-8f56-17d67e3ad0c6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315129826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.1315129826
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.522850984
Short name T6
Test name
Test status
Simulation time 333800981 ps
CPU time 4 seconds
Started Jun 02 03:13:12 PM PDT 24
Finished Jun 02 03:13:17 PM PDT 24
Peak memory 217324 kb
Host smart-3b105952-2dbc-4713-a188-014e5658d923
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522850984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.522850984
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.1172794314
Short name T361
Test name
Test status
Simulation time 1202453618 ps
CPU time 9.31 seconds
Started Jun 02 03:12:08 PM PDT 24
Finished Jun 02 03:12:18 PM PDT 24
Peak memory 218412 kb
Host smart-48453018-1c54-4552-92b3-1f17129725ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172794314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.1172794314
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1985128811
Short name T105
Test name
Test status
Simulation time 74670257 ps
CPU time 2.64 seconds
Started Jun 02 03:05:54 PM PDT 24
Finished Jun 02 03:05:57 PM PDT 24
Peak memory 222804 kb
Host smart-2fa624bd-d9f3-4d6e-a1e4-0e85639ab402
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985128811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.1985128811
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.3072900418
Short name T155
Test name
Test status
Simulation time 475080970 ps
CPU time 14.06 seconds
Started Jun 02 03:14:22 PM PDT 24
Finished Jun 02 03:14:37 PM PDT 24
Peak memory 226476 kb
Host smart-11c50860-191b-45c0-b303-cb35b968c001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072900418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.3072900418
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.2439562034
Short name T18
Test name
Test status
Simulation time 315606124 ps
CPU time 12.6 seconds
Started Jun 02 03:13:21 PM PDT 24
Finished Jun 02 03:13:34 PM PDT 24
Peak memory 225528 kb
Host smart-39724a45-084f-4086-8ac7-019dd2f8138c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439562034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
2439562034
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.3019038655
Short name T85
Test name
Test status
Simulation time 28393867 ps
CPU time 1.06 seconds
Started Jun 02 03:13:48 PM PDT 24
Finished Jun 02 03:13:49 PM PDT 24
Peak memory 209120 kb
Host smart-aea78d51-12f4-497b-9168-7dd5c7b2cc01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019038655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.3019038655
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2471872715
Short name T880
Test name
Test status
Simulation time 423221716 ps
CPU time 3.11 seconds
Started Jun 02 03:05:31 PM PDT 24
Finished Jun 02 03:05:35 PM PDT 24
Peak memory 218420 kb
Host smart-ea92bb89-ab17-4e4a-b299-8233f5c9b877
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247187
2715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2471872715
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.4181919197
Short name T200
Test name
Test status
Simulation time 13817913 ps
CPU time 1 seconds
Started Jun 02 03:06:13 PM PDT 24
Finished Jun 02 03:06:15 PM PDT 24
Peak memory 209776 kb
Host smart-bca45509-4033-41f1-91ea-73b4ff8d93cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181919197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.4181919197
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2855951224
Short name T126
Test name
Test status
Simulation time 292791844 ps
CPU time 3.54 seconds
Started Jun 02 03:05:50 PM PDT 24
Finished Jun 02 03:05:54 PM PDT 24
Peak memory 218140 kb
Host smart-9b31948e-2db1-416f-8e36-c05e34c5e742
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855951224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2855951224
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1700663563
Short name T119
Test name
Test status
Simulation time 232795415 ps
CPU time 2.18 seconds
Started Jun 02 03:05:37 PM PDT 24
Finished Jun 02 03:05:40 PM PDT 24
Peak memory 218284 kb
Host smart-757000f1-f300-4763-8d97-95e00cc25015
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700663563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1700663563
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3936590856
Short name T39
Test name
Test status
Simulation time 9790309279 ps
CPU time 304.11 seconds
Started Jun 02 03:13:33 PM PDT 24
Finished Jun 02 03:18:38 PM PDT 24
Peak memory 280732 kb
Host smart-0d1eed70-1fba-48d6-a54a-83a5123162da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936590856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3936590856
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.3245337459
Short name T117
Test name
Test status
Simulation time 441354728 ps
CPU time 3.25 seconds
Started Jun 02 03:05:32 PM PDT 24
Finished Jun 02 03:05:36 PM PDT 24
Peak memory 218088 kb
Host smart-fcc77182-6465-45e1-9e95-110592cc1094
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245337459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.3245337459
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.3860891462
Short name T100
Test name
Test status
Simulation time 1513773218 ps
CPU time 30.3 seconds
Started Jun 02 03:14:24 PM PDT 24
Finished Jun 02 03:14:55 PM PDT 24
Peak memory 251332 kb
Host smart-619c7a7b-4ada-4404-ae5b-6c19c6fadd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860891462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.3860891462
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4153547117
Short name T133
Test name
Test status
Simulation time 484033954 ps
CPU time 4.31 seconds
Started Jun 02 03:05:50 PM PDT 24
Finished Jun 02 03:05:54 PM PDT 24
Peak memory 218204 kb
Host smart-b73e7fb0-f970-499f-826c-83d6e8100894
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153547117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.4153547117
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.399766055
Short name T205
Test name
Test status
Simulation time 17167296 ps
CPU time 0.97 seconds
Started Jun 02 03:06:05 PM PDT 24
Finished Jun 02 03:06:07 PM PDT 24
Peak memory 209932 kb
Host smart-f0e8f7a4-dbb0-4fd4-aba2-569aba98d31d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399766055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.399766055
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2587946903
Short name T189
Test name
Test status
Simulation time 1596267440 ps
CPU time 5.85 seconds
Started Jun 02 03:12:10 PM PDT 24
Finished Jun 02 03:12:16 PM PDT 24
Peak memory 209864 kb
Host smart-2efae8cc-0e56-476d-ba14-813e0dda0d73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587946903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2587946903
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3960558148
Short name T11
Test name
Test status
Simulation time 838435389 ps
CPU time 7.57 seconds
Started Jun 02 03:12:53 PM PDT 24
Finished Jun 02 03:13:01 PM PDT 24
Peak memory 218348 kb
Host smart-17a1b5aa-c09e-4a5b-8496-eb2bc0ce3993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960558148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3960558148
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.837855365
Short name T13
Test name
Test status
Simulation time 47855363 ps
CPU time 0.99 seconds
Started Jun 02 03:13:21 PM PDT 24
Finished Jun 02 03:13:23 PM PDT 24
Peak memory 211948 kb
Host smart-ef321c82-4ac8-46d4-835c-c5016f9ba4dc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837855365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.837855365
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3327668043
Short name T129
Test name
Test status
Simulation time 46711172 ps
CPU time 2.44 seconds
Started Jun 02 03:06:02 PM PDT 24
Finished Jun 02 03:06:05 PM PDT 24
Peak memory 222512 kb
Host smart-a07831a0-3b20-4782-aa25-efb262a61791
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327668043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3327668043
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1577473876
Short name T132
Test name
Test status
Simulation time 114429083 ps
CPU time 1.92 seconds
Started Jun 02 03:05:45 PM PDT 24
Finished Jun 02 03:05:48 PM PDT 24
Peak memory 222544 kb
Host smart-6c16484b-1042-48ae-bff1-b5df30fc8f73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577473876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.1577473876
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.1928640136
Short name T175
Test name
Test status
Simulation time 15013697 ps
CPU time 0.85 seconds
Started Jun 02 03:12:10 PM PDT 24
Finished Jun 02 03:12:11 PM PDT 24
Peak memory 209076 kb
Host smart-16d2ebca-e36d-45b7-8963-362195d46dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928640136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.1928640136
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.1341198753
Short name T215
Test name
Test status
Simulation time 14440005 ps
CPU time 0.83 seconds
Started Jun 02 03:12:09 PM PDT 24
Finished Jun 02 03:12:10 PM PDT 24
Peak memory 208856 kb
Host smart-850de751-56a6-4b20-a32f-049b4504a775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341198753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.1341198753
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.1742384396
Short name T148
Test name
Test status
Simulation time 12086150 ps
CPU time 0.83 seconds
Started Jun 02 03:12:15 PM PDT 24
Finished Jun 02 03:12:17 PM PDT 24
Peak memory 208840 kb
Host smart-71051ffb-6048-41d0-aba2-8afbee69e345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742384396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.1742384396
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.533559259
Short name T216
Test name
Test status
Simulation time 12971163 ps
CPU time 0.98 seconds
Started Jun 02 03:12:45 PM PDT 24
Finished Jun 02 03:12:46 PM PDT 24
Peak memory 209136 kb
Host smart-a8bbb3a9-65ef-42b2-9f3c-574447060185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533559259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.533559259
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2206501266
Short name T130
Test name
Test status
Simulation time 193119061 ps
CPU time 2.67 seconds
Started Jun 02 03:06:01 PM PDT 24
Finished Jun 02 03:06:04 PM PDT 24
Peak memory 222684 kb
Host smart-17c49eff-b5df-4f1e-80c1-73c099741f1d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206501266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.2206501266
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1730590939
Short name T131
Test name
Test status
Simulation time 584201440 ps
CPU time 3.35 seconds
Started Jun 02 03:06:01 PM PDT 24
Finished Jun 02 03:06:05 PM PDT 24
Peak memory 218124 kb
Host smart-c4abf3ce-fd48-48de-9de4-3278da67a6c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730590939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1730590939
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1053434121
Short name T116
Test name
Test status
Simulation time 492502702 ps
CPU time 2.28 seconds
Started Jun 02 03:06:02 PM PDT 24
Finished Jun 02 03:06:05 PM PDT 24
Peak memory 218116 kb
Host smart-9d166950-766c-453e-9b28-0f55a93cb4d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053434121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1053434121
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2812370997
Short name T128
Test name
Test status
Simulation time 88510009 ps
CPU time 2.13 seconds
Started Jun 02 03:06:01 PM PDT 24
Finished Jun 02 03:06:03 PM PDT 24
Peak memory 222372 kb
Host smart-e25d2755-9fd5-403e-9e21-2f86b25c43a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812370997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2812370997
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2006657022
Short name T124
Test name
Test status
Simulation time 101261182 ps
CPU time 3.91 seconds
Started Jun 02 03:05:54 PM PDT 24
Finished Jun 02 03:05:59 PM PDT 24
Peak memory 218124 kb
Host smart-a17eae62-038d-46e2-9cd0-87b1f815bdd7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006657022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2006657022
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.2680958760
Short name T43
Test name
Test status
Simulation time 27610045230 ps
CPU time 186.82 seconds
Started Jun 02 03:14:22 PM PDT 24
Finished Jun 02 03:17:30 PM PDT 24
Peak memory 243180 kb
Host smart-0605a5e8-e557-48f6-920e-6b6e9594459d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680958760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.2680958760
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.549851436
Short name T50
Test name
Test status
Simulation time 2784887761 ps
CPU time 16.96 seconds
Started Jun 02 03:14:49 PM PDT 24
Finished Jun 02 03:15:06 PM PDT 24
Peak memory 226568 kb
Host smart-4169f734-f747-466d-be83-950000cb76f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549851436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.549851436
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.377587973
Short name T19
Test name
Test status
Simulation time 973451750 ps
CPU time 14.93 seconds
Started Jun 02 03:12:21 PM PDT 24
Finished Jun 02 03:12:37 PM PDT 24
Peak memory 218016 kb
Host smart-ecdafcdb-372c-4c6a-84b6-57e31c09559e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377587973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_regwen_during_op.377587973
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1960988403
Short name T877
Test name
Test status
Simulation time 28328321 ps
CPU time 1.39 seconds
Started Jun 02 03:05:35 PM PDT 24
Finished Jun 02 03:05:37 PM PDT 24
Peak memory 209788 kb
Host smart-adf3f834-f404-4dd6-8192-77c51f25a99c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960988403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.1960988403
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3024430981
Short name T988
Test name
Test status
Simulation time 38263791 ps
CPU time 1.78 seconds
Started Jun 02 03:05:34 PM PDT 24
Finished Jun 02 03:05:36 PM PDT 24
Peak memory 209784 kb
Host smart-5af738f5-892a-48ff-98b1-1cdaf6b41d53
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024430981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3024430981
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2980759430
Short name T195
Test name
Test status
Simulation time 34377189 ps
CPU time 1.26 seconds
Started Jun 02 03:05:31 PM PDT 24
Finished Jun 02 03:05:33 PM PDT 24
Peak memory 212196 kb
Host smart-3b1b7f54-6daa-4272-abda-453fadfe43e1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980759430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2980759430
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2550445120
Short name T917
Test name
Test status
Simulation time 20671270 ps
CPU time 1.65 seconds
Started Jun 02 03:05:33 PM PDT 24
Finished Jun 02 03:05:35 PM PDT 24
Peak memory 218296 kb
Host smart-39f83c36-a0a8-4547-9a4f-041944001d09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550445120 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2550445120
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2351239229
Short name T918
Test name
Test status
Simulation time 172156757 ps
CPU time 0.94 seconds
Started Jun 02 03:05:34 PM PDT 24
Finished Jun 02 03:05:35 PM PDT 24
Peak memory 209460 kb
Host smart-614b769b-cfb2-473e-b6a2-8065d148375f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351239229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2351239229
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3980383332
Short name T934
Test name
Test status
Simulation time 126460074 ps
CPU time 1.02 seconds
Started Jun 02 03:05:33 PM PDT 24
Finished Jun 02 03:05:35 PM PDT 24
Peak memory 209676 kb
Host smart-8dce309b-a138-4454-a171-5651bd4d7a02
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980383332 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3980383332
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.2411159877
Short name T884
Test name
Test status
Simulation time 2622659790 ps
CPU time 6.45 seconds
Started Jun 02 03:05:30 PM PDT 24
Finished Jun 02 03:05:37 PM PDT 24
Peak memory 209716 kb
Host smart-eda77dde-5396-4b65-a745-2fb89153a65c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411159877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.2411159877
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1559197392
Short name T944
Test name
Test status
Simulation time 3212312103 ps
CPU time 9.3 seconds
Started Jun 02 03:05:32 PM PDT 24
Finished Jun 02 03:05:41 PM PDT 24
Peak memory 209720 kb
Host smart-f2e57e30-c63e-4f69-beb9-ae63a8927a05
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559197392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.1559197392
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1438085302
Short name T964
Test name
Test status
Simulation time 145296228 ps
CPU time 2.71 seconds
Started Jun 02 03:05:33 PM PDT 24
Finished Jun 02 03:05:36 PM PDT 24
Peak memory 217928 kb
Host smart-413345e5-6f66-4805-a777-277d7d5a4766
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438085302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1438085302
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3456850150
Short name T994
Test name
Test status
Simulation time 224812890 ps
CPU time 3.56 seconds
Started Jun 02 03:05:28 PM PDT 24
Finished Jun 02 03:05:32 PM PDT 24
Peak memory 209756 kb
Host smart-eee0de24-b956-40ef-ae58-fbc671f7f171
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456850150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3456850150
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3037815796
Short name T928
Test name
Test status
Simulation time 30624872 ps
CPU time 1.22 seconds
Started Jun 02 03:05:31 PM PDT 24
Finished Jun 02 03:05:33 PM PDT 24
Peak memory 218100 kb
Host smart-abe1547b-cb22-4f0d-bea6-7d8ec1d0b242
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037815796 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3037815796
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3605874960
Short name T963
Test name
Test status
Simulation time 66550075 ps
CPU time 1.18 seconds
Started Jun 02 03:05:35 PM PDT 24
Finished Jun 02 03:05:36 PM PDT 24
Peak memory 209888 kb
Host smart-0b770ae5-491e-4027-a67e-3153f9413735
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605874960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.3605874960
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.4217625750
Short name T888
Test name
Test status
Simulation time 38732264 ps
CPU time 1.64 seconds
Started Jun 02 03:05:30 PM PDT 24
Finished Jun 02 03:05:33 PM PDT 24
Peak memory 218520 kb
Host smart-c7238059-ae96-462e-9e65-890e1b7ccee2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217625750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.4217625750
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.489224637
Short name T897
Test name
Test status
Simulation time 21190272 ps
CPU time 1.27 seconds
Started Jun 02 03:05:42 PM PDT 24
Finished Jun 02 03:05:44 PM PDT 24
Peak memory 209800 kb
Host smart-6c457565-ed5f-43bc-86a5-8b9da43d69cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489224637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.489224637
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1332335661
Short name T908
Test name
Test status
Simulation time 80009239 ps
CPU time 1.37 seconds
Started Jun 02 03:05:36 PM PDT 24
Finished Jun 02 03:05:38 PM PDT 24
Peak memory 209756 kb
Host smart-4964823f-9985-4cbf-843a-19134ffb1cb4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332335661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.1332335661
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.659973713
Short name T120
Test name
Test status
Simulation time 14672312 ps
CPU time 0.93 seconds
Started Jun 02 03:05:38 PM PDT 24
Finished Jun 02 03:05:40 PM PDT 24
Peak memory 210132 kb
Host smart-3eeffc2e-ef4d-4efa-8aed-d760ea7f0ab1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659973713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_reset
.659973713
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2517300601
Short name T201
Test name
Test status
Simulation time 17322666 ps
CPU time 0.92 seconds
Started Jun 02 03:05:38 PM PDT 24
Finished Jun 02 03:05:40 PM PDT 24
Peak memory 209724 kb
Host smart-b877749b-0a62-4e23-9464-04ec4042babb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517300601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2517300601
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.2643986893
Short name T913
Test name
Test status
Simulation time 59891866 ps
CPU time 1.16 seconds
Started Jun 02 03:05:33 PM PDT 24
Finished Jun 02 03:05:34 PM PDT 24
Peak memory 209736 kb
Host smart-0b72e805-97a1-4b15-8613-b61ff4900edb
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643986893 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.2643986893
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.783109544
Short name T992
Test name
Test status
Simulation time 521328290 ps
CPU time 3.19 seconds
Started Jun 02 03:05:33 PM PDT 24
Finished Jun 02 03:05:37 PM PDT 24
Peak memory 209488 kb
Host smart-542182f7-b105-4494-b657-eb612682acaa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783109544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.783109544
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2548842328
Short name T137
Test name
Test status
Simulation time 5125710100 ps
CPU time 30.38 seconds
Started Jun 02 03:05:34 PM PDT 24
Finished Jun 02 03:06:04 PM PDT 24
Peak memory 209844 kb
Host smart-51b74011-5c9b-49e0-a292-bfc6b26c6079
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548842328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.2548842328
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1457271737
Short name T932
Test name
Test status
Simulation time 177331053 ps
CPU time 1.74 seconds
Started Jun 02 03:05:31 PM PDT 24
Finished Jun 02 03:05:33 PM PDT 24
Peak memory 211128 kb
Host smart-6255132a-21c0-402c-8345-3b9b79ae361c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457271737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1457271737
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3128234528
Short name T979
Test name
Test status
Simulation time 638558056 ps
CPU time 6.18 seconds
Started Jun 02 03:05:35 PM PDT 24
Finished Jun 02 03:05:42 PM PDT 24
Peak memory 225896 kb
Host smart-d3409348-25ea-4d96-86b0-68899934a6f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312823
4528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3128234528
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.3907711879
Short name T891
Test name
Test status
Simulation time 508255392 ps
CPU time 2.82 seconds
Started Jun 02 03:05:32 PM PDT 24
Finished Jun 02 03:05:35 PM PDT 24
Peak memory 209716 kb
Host smart-086f2b7a-fb31-430b-8e6a-8f78ac367f2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907711879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.3907711879
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2561768174
Short name T916
Test name
Test status
Simulation time 20362670 ps
CPU time 1.19 seconds
Started Jun 02 03:05:33 PM PDT 24
Finished Jun 02 03:05:35 PM PDT 24
Peak memory 218164 kb
Host smart-41d15858-b27c-4a55-b966-62b20ea2300a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561768174 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2561768174
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2869013515
Short name T960
Test name
Test status
Simulation time 28747005 ps
CPU time 1.5 seconds
Started Jun 02 03:05:37 PM PDT 24
Finished Jun 02 03:05:39 PM PDT 24
Peak memory 209900 kb
Host smart-1df53d4e-442a-4770-bfb7-e7b27bdf5c9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869013515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.2869013515
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2413511935
Short name T923
Test name
Test status
Simulation time 789252216 ps
CPU time 3.03 seconds
Started Jun 02 03:05:39 PM PDT 24
Finished Jun 02 03:05:42 PM PDT 24
Peak memory 218132 kb
Host smart-69fe5653-a9d2-479b-a161-c99cd6120502
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413511935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.2413511935
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.3197241829
Short name T159
Test name
Test status
Simulation time 51005851 ps
CPU time 1.01 seconds
Started Jun 02 03:06:01 PM PDT 24
Finished Jun 02 03:06:03 PM PDT 24
Peak memory 218228 kb
Host smart-39a098db-f779-4fa3-9345-5a708aa0bcda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197241829 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.3197241829
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2245361213
Short name T199
Test name
Test status
Simulation time 13452184 ps
CPU time 1 seconds
Started Jun 02 03:06:02 PM PDT 24
Finished Jun 02 03:06:04 PM PDT 24
Peak memory 209920 kb
Host smart-1d326006-1c42-4ffe-be9e-5579c80c2688
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245361213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2245361213
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.2440047441
Short name T952
Test name
Test status
Simulation time 73255820 ps
CPU time 1.12 seconds
Started Jun 02 03:06:02 PM PDT 24
Finished Jun 02 03:06:04 PM PDT 24
Peak memory 209908 kb
Host smart-36e4c72d-a918-4889-b2de-d507e644f0ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440047441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.2440047441
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.350981156
Short name T977
Test name
Test status
Simulation time 164839713 ps
CPU time 3.49 seconds
Started Jun 02 03:06:04 PM PDT 24
Finished Jun 02 03:06:08 PM PDT 24
Peak memory 218288 kb
Host smart-685f9241-de97-40ea-b61b-b76d4bf30b6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350981156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.350981156
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.498868829
Short name T951
Test name
Test status
Simulation time 250722725 ps
CPU time 2.79 seconds
Started Jun 02 03:06:01 PM PDT 24
Finished Jun 02 03:06:05 PM PDT 24
Peak memory 218124 kb
Host smart-ef9c4598-fff5-4c59-a594-7bf8e6d3429d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498868829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg_
err.498868829
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.722531790
Short name T904
Test name
Test status
Simulation time 99057497 ps
CPU time 1.79 seconds
Started Jun 02 03:06:04 PM PDT 24
Finished Jun 02 03:06:06 PM PDT 24
Peak memory 219576 kb
Host smart-86c49368-6cf3-45ad-951d-6c4738e31cb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722531790 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.722531790
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.4182043805
Short name T895
Test name
Test status
Simulation time 30538568 ps
CPU time 0.89 seconds
Started Jun 02 03:06:01 PM PDT 24
Finished Jun 02 03:06:03 PM PDT 24
Peak memory 209772 kb
Host smart-5c8bd7bf-d1e4-455e-aa82-3255e0cfa4ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182043805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.4182043805
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.1841038583
Short name T983
Test name
Test status
Simulation time 22717417 ps
CPU time 1.1 seconds
Started Jun 02 03:06:02 PM PDT 24
Finished Jun 02 03:06:04 PM PDT 24
Peak memory 209892 kb
Host smart-f3f2a647-ba9c-4926-bdd6-5ef56e3a4dbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841038583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.1841038583
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.2948268811
Short name T123
Test name
Test status
Simulation time 109945798 ps
CPU time 1.76 seconds
Started Jun 02 03:06:04 PM PDT 24
Finished Jun 02 03:06:06 PM PDT 24
Peak memory 218408 kb
Host smart-e5d3d9e7-af9f-41d2-afae-9d60ee6ac59f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948268811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.2948268811
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.543520464
Short name T967
Test name
Test status
Simulation time 64291700 ps
CPU time 1.46 seconds
Started Jun 02 03:06:04 PM PDT 24
Finished Jun 02 03:06:06 PM PDT 24
Peak memory 219204 kb
Host smart-ef86db93-7c5b-4ae4-8820-d8578b0df089
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543520464 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.543520464
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2253252668
Short name T196
Test name
Test status
Simulation time 19802194 ps
CPU time 1.02 seconds
Started Jun 02 03:06:04 PM PDT 24
Finished Jun 02 03:06:05 PM PDT 24
Peak memory 209964 kb
Host smart-30b94a55-3878-4da2-9256-b47518495bb5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253252668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2253252668
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3544209696
Short name T987
Test name
Test status
Simulation time 225975085 ps
CPU time 1.39 seconds
Started Jun 02 03:06:00 PM PDT 24
Finished Jun 02 03:06:02 PM PDT 24
Peak memory 209912 kb
Host smart-4b28f8ba-99c9-43a7-873b-83f9b112c2f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544209696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.3544209696
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1537087493
Short name T942
Test name
Test status
Simulation time 26320794 ps
CPU time 1.64 seconds
Started Jun 02 03:06:00 PM PDT 24
Finished Jun 02 03:06:02 PM PDT 24
Peak memory 218160 kb
Host smart-7c3a1d36-e57c-4a3f-9125-bc5a6a7ea34a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537087493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1537087493
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1477062431
Short name T981
Test name
Test status
Simulation time 24818956 ps
CPU time 1.65 seconds
Started Jun 02 03:06:05 PM PDT 24
Finished Jun 02 03:06:07 PM PDT 24
Peak memory 218260 kb
Host smart-9b4db215-32d9-4c7d-9437-c0b31e699da6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477062431 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1477062431
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.1896607368
Short name T945
Test name
Test status
Simulation time 47831833 ps
CPU time 0.9 seconds
Started Jun 02 03:06:00 PM PDT 24
Finished Jun 02 03:06:02 PM PDT 24
Peak memory 209044 kb
Host smart-8f7adf35-58ab-4b6d-9ece-cc07e6cadfac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896607368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.1896607368
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1767342559
Short name T985
Test name
Test status
Simulation time 59468659 ps
CPU time 1.66 seconds
Started Jun 02 03:06:00 PM PDT 24
Finished Jun 02 03:06:02 PM PDT 24
Peak memory 218076 kb
Host smart-ebeee03f-b0fc-4ee8-b98a-6b44e3d89959
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767342559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1767342559
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3240706336
Short name T974
Test name
Test status
Simulation time 125037317 ps
CPU time 2.82 seconds
Started Jun 02 03:06:03 PM PDT 24
Finished Jun 02 03:06:07 PM PDT 24
Peak memory 218148 kb
Host smart-1653bc0f-c81b-445d-b8a0-d5d55daf7bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240706336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3240706336
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.552541647
Short name T1002
Test name
Test status
Simulation time 88334591 ps
CPU time 1.52 seconds
Started Jun 02 03:06:03 PM PDT 24
Finished Jun 02 03:06:06 PM PDT 24
Peak memory 218256 kb
Host smart-b00e193e-1bb3-441c-a54c-bdfbb607eb90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552541647 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.552541647
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4124027961
Short name T902
Test name
Test status
Simulation time 17721258 ps
CPU time 0.99 seconds
Started Jun 02 03:06:02 PM PDT 24
Finished Jun 02 03:06:03 PM PDT 24
Peak memory 209856 kb
Host smart-8124ba1a-3e5a-4a1b-b036-12b7edb85c41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124027961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.4124027961
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2711485209
Short name T927
Test name
Test status
Simulation time 29449691 ps
CPU time 1.53 seconds
Started Jun 02 03:06:01 PM PDT 24
Finished Jun 02 03:06:03 PM PDT 24
Peak memory 209892 kb
Host smart-57f01556-1816-4e0b-91a8-a84272f5a208
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711485209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2711485209
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.458933583
Short name T103
Test name
Test status
Simulation time 137928924 ps
CPU time 2.45 seconds
Started Jun 02 03:06:04 PM PDT 24
Finished Jun 02 03:06:07 PM PDT 24
Peak memory 218188 kb
Host smart-21509f89-dd55-48fe-a96d-067ba0e0bf9b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458933583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.458933583
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.192669312
Short name T939
Test name
Test status
Simulation time 26562775 ps
CPU time 1.97 seconds
Started Jun 02 03:06:01 PM PDT 24
Finished Jun 02 03:06:03 PM PDT 24
Peak memory 218264 kb
Host smart-c6fb1691-ed5a-4b6c-a2ec-81f54bc7cd07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192669312 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.192669312
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.2404639185
Short name T889
Test name
Test status
Simulation time 78425657 ps
CPU time 0.81 seconds
Started Jun 02 03:06:01 PM PDT 24
Finished Jun 02 03:06:03 PM PDT 24
Peak memory 209632 kb
Host smart-3a5fe449-5c1e-41aa-8333-c2a83b7cd791
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404639185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.2404639185
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.3745704564
Short name T924
Test name
Test status
Simulation time 118370492 ps
CPU time 3.18 seconds
Started Jun 02 03:06:00 PM PDT 24
Finished Jun 02 03:06:04 PM PDT 24
Peak memory 218184 kb
Host smart-f2d4687c-e66e-462d-8bf6-4ec10c7cbe48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745704564 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.3745704564
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1665337653
Short name T134
Test name
Test status
Simulation time 170811504 ps
CPU time 2.36 seconds
Started Jun 02 03:06:01 PM PDT 24
Finished Jun 02 03:06:04 PM PDT 24
Peak memory 222480 kb
Host smart-502a29d6-17ea-493a-8529-bd135038a557
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665337653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.1665337653
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2391816541
Short name T135
Test name
Test status
Simulation time 266872723 ps
CPU time 1.42 seconds
Started Jun 02 03:06:04 PM PDT 24
Finished Jun 02 03:06:06 PM PDT 24
Peak memory 220244 kb
Host smart-25a3c59b-4cd7-44c6-aca3-92b4abb265c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391816541 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2391816541
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.2625142020
Short name T896
Test name
Test status
Simulation time 82575920 ps
CPU time 0.99 seconds
Started Jun 02 03:06:04 PM PDT 24
Finished Jun 02 03:06:06 PM PDT 24
Peak memory 210112 kb
Host smart-a6d9dc6e-2381-4d6e-bcfc-a715f7d9dc82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625142020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.2625142020
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3084218246
Short name T208
Test name
Test status
Simulation time 64974608 ps
CPU time 1.83 seconds
Started Jun 02 03:06:01 PM PDT 24
Finished Jun 02 03:06:04 PM PDT 24
Peak memory 209940 kb
Host smart-bba7a9ad-90c4-484e-b7c7-023bccc36659
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084218246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3084218246
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2251303450
Short name T991
Test name
Test status
Simulation time 106865922 ps
CPU time 1.98 seconds
Started Jun 02 03:06:28 PM PDT 24
Finished Jun 02 03:06:30 PM PDT 24
Peak memory 218392 kb
Host smart-004080d0-864d-4c29-8007-1d4544c3e6b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251303450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.2251303450
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.1817214621
Short name T949
Test name
Test status
Simulation time 50031134 ps
CPU time 1.16 seconds
Started Jun 02 03:06:06 PM PDT 24
Finished Jun 02 03:06:07 PM PDT 24
Peak memory 218172 kb
Host smart-ae124744-3a33-4b66-b089-dd2543a32c71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817214621 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.1817214621
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2224181222
Short name T905
Test name
Test status
Simulation time 63264684 ps
CPU time 0.86 seconds
Started Jun 02 03:06:10 PM PDT 24
Finished Jun 02 03:06:12 PM PDT 24
Peak memory 209160 kb
Host smart-d8a3eaf1-1fd4-4efe-833e-fb6fa6274bc1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224181222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2224181222
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.244371027
Short name T910
Test name
Test status
Simulation time 256229149 ps
CPU time 2.12 seconds
Started Jun 02 03:06:05 PM PDT 24
Finished Jun 02 03:06:07 PM PDT 24
Peak memory 212152 kb
Host smart-afec960b-fd25-48fc-88c6-15d7fc4720a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244371027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.244371027
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2442209461
Short name T109
Test name
Test status
Simulation time 631228963 ps
CPU time 3.96 seconds
Started Jun 02 03:06:01 PM PDT 24
Finished Jun 02 03:06:06 PM PDT 24
Peak memory 218232 kb
Host smart-a2ebd753-5d7d-486d-a116-972f20865005
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442209461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2442209461
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.1167449762
Short name T127
Test name
Test status
Simulation time 229762037 ps
CPU time 2.09 seconds
Started Jun 02 03:06:00 PM PDT 24
Finished Jun 02 03:06:03 PM PDT 24
Peak memory 222644 kb
Host smart-7c7fdf5d-9486-401f-8874-bb6c06a9502e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167449762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.1167449762
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3431274497
Short name T961
Test name
Test status
Simulation time 148612576 ps
CPU time 1.45 seconds
Started Jun 02 03:06:05 PM PDT 24
Finished Jun 02 03:06:07 PM PDT 24
Peak memory 218264 kb
Host smart-929d2cea-81c6-4bf1-8552-50fcb14cd5b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431274497 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3431274497
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.2227991282
Short name T933
Test name
Test status
Simulation time 21372676 ps
CPU time 1.46 seconds
Started Jun 02 03:06:05 PM PDT 24
Finished Jun 02 03:06:07 PM PDT 24
Peak memory 211876 kb
Host smart-aba5a73a-425d-4796-8469-0b6b90d1bb4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227991282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.2227991282
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1192964908
Short name T911
Test name
Test status
Simulation time 413178225 ps
CPU time 4.46 seconds
Started Jun 02 03:06:12 PM PDT 24
Finished Jun 02 03:06:17 PM PDT 24
Peak memory 218100 kb
Host smart-a0e107cb-73d1-4a1f-bd9b-40bd72277821
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192964908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1192964908
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.2389256103
Short name T118
Test name
Test status
Simulation time 237679274 ps
CPU time 3.34 seconds
Started Jun 02 03:06:05 PM PDT 24
Finished Jun 02 03:06:10 PM PDT 24
Peak memory 222700 kb
Host smart-8a7eb236-0c59-49da-a32e-272a6bbefac9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389256103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.2389256103
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2590975023
Short name T879
Test name
Test status
Simulation time 52673902 ps
CPU time 1.4 seconds
Started Jun 02 03:06:12 PM PDT 24
Finished Jun 02 03:06:14 PM PDT 24
Peak memory 222764 kb
Host smart-4188fe0b-3411-490b-b776-8b3d8f1c4d67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590975023 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2590975023
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.3222776155
Short name T197
Test name
Test status
Simulation time 41109524 ps
CPU time 1.03 seconds
Started Jun 02 03:06:07 PM PDT 24
Finished Jun 02 03:06:09 PM PDT 24
Peak memory 209784 kb
Host smart-d20ac053-f946-4256-b152-5453f59f1d58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222776155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.3222776155
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.3037543545
Short name T937
Test name
Test status
Simulation time 36463769 ps
CPU time 1.34 seconds
Started Jun 02 03:06:06 PM PDT 24
Finished Jun 02 03:06:08 PM PDT 24
Peak memory 217776 kb
Host smart-c7baab72-d08b-4554-be24-b5a94a26fb0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037543545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.3037543545
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2245730344
Short name T973
Test name
Test status
Simulation time 68634365 ps
CPU time 2.27 seconds
Started Jun 02 03:06:10 PM PDT 24
Finished Jun 02 03:06:13 PM PDT 24
Peak memory 218692 kb
Host smart-7f00387e-3409-4eaa-98a9-c96ad86c4aa0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245730344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2245730344
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1539087314
Short name T110
Test name
Test status
Simulation time 157278666 ps
CPU time 1.72 seconds
Started Jun 02 03:06:05 PM PDT 24
Finished Jun 02 03:06:08 PM PDT 24
Peak memory 222072 kb
Host smart-b8102843-da99-41a0-ae75-d28a63883582
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539087314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1539087314
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3961506782
Short name T193
Test name
Test status
Simulation time 111551435 ps
CPU time 1.02 seconds
Started Jun 02 03:05:44 PM PDT 24
Finished Jun 02 03:05:46 PM PDT 24
Peak memory 209796 kb
Host smart-a956f154-8fff-483c-96bb-3bdbfdbe7ebb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961506782 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3961506782
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.443317126
Short name T966
Test name
Test status
Simulation time 30640639 ps
CPU time 1.8 seconds
Started Jun 02 03:05:45 PM PDT 24
Finished Jun 02 03:05:48 PM PDT 24
Peak memory 209724 kb
Host smart-ba2b3dbc-235f-4abf-b9c6-3a05da7bbbfe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443317126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash
.443317126
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.3206021725
Short name T194
Test name
Test status
Simulation time 42580081 ps
CPU time 1.07 seconds
Started Jun 02 03:05:38 PM PDT 24
Finished Jun 02 03:05:40 PM PDT 24
Peak memory 210380 kb
Host smart-d7af3be0-f9d6-4839-aa7e-a2f9618ad5f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206021725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.3206021725
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3035794934
Short name T1004
Test name
Test status
Simulation time 30664826 ps
CPU time 1.05 seconds
Started Jun 02 03:05:36 PM PDT 24
Finished Jun 02 03:05:38 PM PDT 24
Peak memory 218196 kb
Host smart-ab519840-dad5-48da-840e-9ff6bf040e3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035794934 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.3035794934
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3978818647
Short name T919
Test name
Test status
Simulation time 35310708 ps
CPU time 0.81 seconds
Started Jun 02 03:05:39 PM PDT 24
Finished Jun 02 03:05:40 PM PDT 24
Peak memory 208848 kb
Host smart-43d1dd67-c20e-4ad0-8f09-36014a98fe7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978818647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.3978818647
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.648117429
Short name T886
Test name
Test status
Simulation time 23975325 ps
CPU time 0.95 seconds
Started Jun 02 03:05:38 PM PDT 24
Finished Jun 02 03:05:40 PM PDT 24
Peak memory 209620 kb
Host smart-c8a72b8d-1615-4ba1-8269-c9443b3adaab
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648117429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 2.lc_ctrl_jtag_alert_test.648117429
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1167674475
Short name T953
Test name
Test status
Simulation time 441214734 ps
CPU time 7.74 seconds
Started Jun 02 03:05:37 PM PDT 24
Finished Jun 02 03:05:45 PM PDT 24
Peak memory 209476 kb
Host smart-83042db9-6c24-46e9-9357-bd1153e197e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167674475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1167674475
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.236239115
Short name T876
Test name
Test status
Simulation time 3327275954 ps
CPU time 17.77 seconds
Started Jun 02 03:05:40 PM PDT 24
Finished Jun 02 03:05:58 PM PDT 24
Peak memory 209800 kb
Host smart-a25115f0-a26c-4034-9bf3-a01ad5ced131
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236239115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.236239115
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.1513484275
Short name T948
Test name
Test status
Simulation time 99420370 ps
CPU time 1.59 seconds
Started Jun 02 03:05:38 PM PDT 24
Finished Jun 02 03:05:41 PM PDT 24
Peak memory 217916 kb
Host smart-3a0d0851-1c0b-4dfe-8266-24c813fd7605
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513484275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.1513484275
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3508175362
Short name T968
Test name
Test status
Simulation time 718932310 ps
CPU time 2.54 seconds
Started Jun 02 03:05:37 PM PDT 24
Finished Jun 02 03:05:41 PM PDT 24
Peak memory 218264 kb
Host smart-2ff9ce1e-2fd2-4fdb-a212-75bdce2d87d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350817
5362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3508175362
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.3412036799
Short name T890
Test name
Test status
Simulation time 227926547 ps
CPU time 1.2 seconds
Started Jun 02 03:05:38 PM PDT 24
Finished Jun 02 03:05:40 PM PDT 24
Peak memory 209796 kb
Host smart-c2a73de1-d3fc-4f04-bbc9-2996facaf883
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412036799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.3412036799
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2319043636
Short name T946
Test name
Test status
Simulation time 86351181 ps
CPU time 0.99 seconds
Started Jun 02 03:05:43 PM PDT 24
Finished Jun 02 03:05:45 PM PDT 24
Peak memory 209900 kb
Host smart-9f8c1eb3-0378-4290-bf37-179563f71ad8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319043636 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.2319043636
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3899353156
Short name T969
Test name
Test status
Simulation time 185618901 ps
CPU time 1.35 seconds
Started Jun 02 03:05:44 PM PDT 24
Finished Jun 02 03:05:46 PM PDT 24
Peak memory 209860 kb
Host smart-21ba2c15-c905-4a57-91ff-fc894d0d2f9b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899353156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3899353156
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.276259115
Short name T925
Test name
Test status
Simulation time 305509011 ps
CPU time 3.46 seconds
Started Jun 02 03:05:37 PM PDT 24
Finished Jun 02 03:05:42 PM PDT 24
Peak memory 218140 kb
Host smart-0d26f09a-91bc-4afd-9073-f21374a400f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276259115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.276259115
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.868000183
Short name T218
Test name
Test status
Simulation time 119518699 ps
CPU time 2.08 seconds
Started Jun 02 03:05:36 PM PDT 24
Finished Jun 02 03:05:39 PM PDT 24
Peak memory 222320 kb
Host smart-3a44dfd8-efdf-484c-8601-8c8984ba7e20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868000183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e
rr.868000183
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3772674700
Short name T912
Test name
Test status
Simulation time 254865526 ps
CPU time 1.63 seconds
Started Jun 02 03:05:43 PM PDT 24
Finished Jun 02 03:05:46 PM PDT 24
Peak memory 209464 kb
Host smart-f718b986-bf2c-401d-8c5b-7aee1e61453f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772674700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3772674700
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.481198689
Short name T203
Test name
Test status
Simulation time 30465147 ps
CPU time 1.53 seconds
Started Jun 02 03:05:49 PM PDT 24
Finished Jun 02 03:05:51 PM PDT 24
Peak memory 217972 kb
Host smart-19a2e684-4708-4a89-8c58-eeaf841a8225
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481198689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bash
.481198689
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.1044616058
Short name T121
Test name
Test status
Simulation time 25831263 ps
CPU time 1.06 seconds
Started Jun 02 03:05:41 PM PDT 24
Finished Jun 02 03:05:42 PM PDT 24
Peak memory 210408 kb
Host smart-e090a23c-4fb6-4b25-b66b-bdbb4a74a876
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044616058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.1044616058
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2618622304
Short name T899
Test name
Test status
Simulation time 22020513 ps
CPU time 1.11 seconds
Started Jun 02 03:05:49 PM PDT 24
Finished Jun 02 03:05:50 PM PDT 24
Peak memory 218604 kb
Host smart-002db5e9-75aa-4903-81de-f63fdab1f366
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618622304 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2618622304
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1758684786
Short name T989
Test name
Test status
Simulation time 36822502 ps
CPU time 0.83 seconds
Started Jun 02 03:05:45 PM PDT 24
Finished Jun 02 03:05:47 PM PDT 24
Peak memory 209696 kb
Host smart-0e277240-b8be-4aa4-bf75-7107b26b1502
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758684786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1758684786
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.2562138069
Short name T926
Test name
Test status
Simulation time 92014322 ps
CPU time 0.91 seconds
Started Jun 02 03:05:37 PM PDT 24
Finished Jun 02 03:05:39 PM PDT 24
Peak memory 209676 kb
Host smart-13aa240d-8c5f-4195-9484-72d1b50d58b3
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562138069 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.2562138069
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1768991736
Short name T1000
Test name
Test status
Simulation time 441901225 ps
CPU time 10.51 seconds
Started Jun 02 03:05:43 PM PDT 24
Finished Jun 02 03:05:55 PM PDT 24
Peak memory 217556 kb
Host smart-c02c3aed-af3d-4722-a1e0-18bc8c3e7b67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768991736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.1768991736
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4147031613
Short name T962
Test name
Test status
Simulation time 4394596637 ps
CPU time 11.14 seconds
Started Jun 02 03:05:45 PM PDT 24
Finished Jun 02 03:05:57 PM PDT 24
Peak memory 209772 kb
Host smart-401cbdbd-d86e-41eb-86c7-2bbc38276b68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147031613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.4147031613
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2957597982
Short name T885
Test name
Test status
Simulation time 801225613 ps
CPU time 1.39 seconds
Started Jun 02 03:05:36 PM PDT 24
Finished Jun 02 03:05:38 PM PDT 24
Peak memory 211300 kb
Host smart-f404a555-26b5-4ed7-980d-a951159ff2a8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957597982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.2957597982
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.838157061
Short name T938
Test name
Test status
Simulation time 295806215 ps
CPU time 2.81 seconds
Started Jun 02 03:05:42 PM PDT 24
Finished Jun 02 03:05:46 PM PDT 24
Peak memory 218188 kb
Host smart-0f5e8341-7e72-42d3-87d2-450df2a10f74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838157
061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.838157061
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3300601711
Short name T136
Test name
Test status
Simulation time 75979347 ps
CPU time 2.44 seconds
Started Jun 02 03:05:44 PM PDT 24
Finished Jun 02 03:05:48 PM PDT 24
Peak memory 209732 kb
Host smart-d6881226-7fb7-4d4f-b7c6-f79dd6b4948f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300601711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3300601711
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1932016433
Short name T211
Test name
Test status
Simulation time 24231750 ps
CPU time 1.46 seconds
Started Jun 02 03:05:37 PM PDT 24
Finished Jun 02 03:05:39 PM PDT 24
Peak memory 218164 kb
Host smart-b75d812f-fd8b-4d27-aad1-8249da664625
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932016433 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1932016433
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1706495045
Short name T212
Test name
Test status
Simulation time 35216238 ps
CPU time 1.44 seconds
Started Jun 02 03:05:45 PM PDT 24
Finished Jun 02 03:05:47 PM PDT 24
Peak memory 209924 kb
Host smart-a4d39f49-5aa1-4a37-badd-98b00320319e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706495045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1706495045
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4077118751
Short name T906
Test name
Test status
Simulation time 249312352 ps
CPU time 1.57 seconds
Started Jun 02 03:05:43 PM PDT 24
Finished Jun 02 03:05:46 PM PDT 24
Peak memory 218168 kb
Host smart-2b93188d-0009-49df-b8ba-37f707a22342
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077118751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.4077118751
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1151052739
Short name T1003
Test name
Test status
Simulation time 53759756 ps
CPU time 0.99 seconds
Started Jun 02 03:05:48 PM PDT 24
Finished Jun 02 03:05:49 PM PDT 24
Peak memory 209836 kb
Host smart-e796ff30-0274-4a00-8024-2a9662dbc9cf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151052739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.1151052739
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.1559518454
Short name T202
Test name
Test status
Simulation time 26595076 ps
CPU time 1.49 seconds
Started Jun 02 03:05:46 PM PDT 24
Finished Jun 02 03:05:48 PM PDT 24
Peak memory 209860 kb
Host smart-19d4560c-3ea7-4b8e-82b1-5bc014c0a45a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559518454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.1559518454
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.137602971
Short name T920
Test name
Test status
Simulation time 55327375 ps
CPU time 1.16 seconds
Started Jun 02 03:05:47 PM PDT 24
Finished Jun 02 03:05:48 PM PDT 24
Peak memory 210404 kb
Host smart-d912ed40-ea24-4008-a098-f1229e29b47b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137602971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.137602971
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3322369501
Short name T115
Test name
Test status
Simulation time 321459637 ps
CPU time 1.17 seconds
Started Jun 02 03:05:46 PM PDT 24
Finished Jun 02 03:05:48 PM PDT 24
Peak memory 218212 kb
Host smart-76c5d0b8-d9d0-4cf7-a525-9c5e0266cdae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322369501 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3322369501
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.4148559416
Short name T898
Test name
Test status
Simulation time 16462707 ps
CPU time 1.14 seconds
Started Jun 02 03:05:47 PM PDT 24
Finished Jun 02 03:05:49 PM PDT 24
Peak memory 209276 kb
Host smart-144ace1a-dfe8-4c7f-8d16-d6d10028821c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148559416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.4148559416
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.768726089
Short name T931
Test name
Test status
Simulation time 130262158 ps
CPU time 1.46 seconds
Started Jun 02 03:05:43 PM PDT 24
Finished Jun 02 03:05:46 PM PDT 24
Peak memory 209740 kb
Host smart-4cd6a1c6-a4e5-44db-a94b-cbfec40adece
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768726089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 4.lc_ctrl_jtag_alert_test.768726089
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.4178080427
Short name T995
Test name
Test status
Simulation time 2395299648 ps
CPU time 6.61 seconds
Started Jun 02 03:05:42 PM PDT 24
Finished Jun 02 03:05:49 PM PDT 24
Peak memory 217568 kb
Host smart-2d4f6eee-dcea-49e8-aaf7-58d9ab7a8e46
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178080427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.4178080427
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2037981649
Short name T984
Test name
Test status
Simulation time 777628905 ps
CPU time 10.36 seconds
Started Jun 02 03:05:45 PM PDT 24
Finished Jun 02 03:05:57 PM PDT 24
Peak memory 217556 kb
Host smart-90be30cf-99a4-4e9f-a8b0-cc1971829608
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037981649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.2037981649
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.415205756
Short name T878
Test name
Test status
Simulation time 94629639 ps
CPU time 3.05 seconds
Started Jun 02 03:05:44 PM PDT 24
Finished Jun 02 03:05:47 PM PDT 24
Peak memory 217988 kb
Host smart-088833bf-abd9-4712-a686-c448aa62dfb0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415205756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.415205756
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2254505706
Short name T935
Test name
Test status
Simulation time 302287192 ps
CPU time 3.17 seconds
Started Jun 02 03:05:43 PM PDT 24
Finished Jun 02 03:05:47 PM PDT 24
Peak memory 219644 kb
Host smart-eba029af-34c8-46a8-aed1-25699ede0fe7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225450
5706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2254505706
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1714632469
Short name T956
Test name
Test status
Simulation time 128936139 ps
CPU time 2.05 seconds
Started Jun 02 03:05:49 PM PDT 24
Finished Jun 02 03:05:51 PM PDT 24
Peak memory 217844 kb
Host smart-9acb2196-c724-4840-b07e-c679380cf066
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714632469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1714632469
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.977029186
Short name T907
Test name
Test status
Simulation time 43761676 ps
CPU time 1.45 seconds
Started Jun 02 03:05:45 PM PDT 24
Finished Jun 02 03:05:48 PM PDT 24
Peak memory 218112 kb
Host smart-490f21cf-b1fb-4f06-a325-54aa03dc01fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977029186 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.977029186
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1380400592
Short name T207
Test name
Test status
Simulation time 21831902 ps
CPU time 1.23 seconds
Started Jun 02 03:05:50 PM PDT 24
Finished Jun 02 03:05:52 PM PDT 24
Peak memory 212028 kb
Host smart-df2daa91-323a-4856-a54b-6236f0f38054
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380400592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1380400592
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1609931139
Short name T104
Test name
Test status
Simulation time 188254616 ps
CPU time 1.76 seconds
Started Jun 02 03:05:45 PM PDT 24
Finished Jun 02 03:05:48 PM PDT 24
Peak memory 218984 kb
Host smart-66efcb88-64ab-4fad-865d-c3e726c7f907
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609931139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1609931139
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.2809591523
Short name T125
Test name
Test status
Simulation time 2178189105 ps
CPU time 5.36 seconds
Started Jun 02 03:05:48 PM PDT 24
Finished Jun 02 03:05:54 PM PDT 24
Peak memory 218224 kb
Host smart-cd272cde-ddc9-48ec-a060-bb11ad9d4275
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809591523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.2809591523
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.3083913473
Short name T915
Test name
Test status
Simulation time 44967259 ps
CPU time 1.29 seconds
Started Jun 02 03:05:52 PM PDT 24
Finished Jun 02 03:05:53 PM PDT 24
Peak memory 219768 kb
Host smart-babcac17-b2ee-4c2c-9a60-907663664fbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083913473 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.3083913473
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.759693952
Short name T198
Test name
Test status
Simulation time 27189945 ps
CPU time 0.84 seconds
Started Jun 02 03:05:49 PM PDT 24
Finished Jun 02 03:05:50 PM PDT 24
Peak memory 209112 kb
Host smart-84e78679-affd-4561-8803-bcc2ab0b9ea7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759693952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.759693952
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.2856619276
Short name T955
Test name
Test status
Simulation time 234096785 ps
CPU time 2.1 seconds
Started Jun 02 03:05:46 PM PDT 24
Finished Jun 02 03:05:49 PM PDT 24
Peak memory 209692 kb
Host smart-88f61ff9-ade5-41b8-b901-62eb6e81a9db
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856619276 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.2856619276
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.4098461857
Short name T112
Test name
Test status
Simulation time 370974708 ps
CPU time 4.95 seconds
Started Jun 02 03:05:45 PM PDT 24
Finished Jun 02 03:05:51 PM PDT 24
Peak memory 209392 kb
Host smart-8e21302c-eaed-4dc6-8c4d-eb3e4382e21f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098461857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.4098461857
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2894068661
Short name T947
Test name
Test status
Simulation time 1932420293 ps
CPU time 22.85 seconds
Started Jun 02 03:05:46 PM PDT 24
Finished Jun 02 03:06:09 PM PDT 24
Peak memory 209672 kb
Host smart-5d1ae70c-57f9-418d-88ec-77c64dc155ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894068661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2894068661
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1301107263
Short name T882
Test name
Test status
Simulation time 208507811 ps
CPU time 1.36 seconds
Started Jun 02 03:05:48 PM PDT 24
Finished Jun 02 03:05:50 PM PDT 24
Peak memory 211172 kb
Host smart-f10cde8c-39bd-4f4b-861d-240abc8571d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301107263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1301107263
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2331864878
Short name T894
Test name
Test status
Simulation time 89700101 ps
CPU time 3.19 seconds
Started Jun 02 03:05:49 PM PDT 24
Finished Jun 02 03:05:52 PM PDT 24
Peak memory 218184 kb
Host smart-00fdb2a9-a486-4dc0-a9c0-21db6ec314c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233186
4878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2331864878
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2227946549
Short name T996
Test name
Test status
Simulation time 246847089 ps
CPU time 1.13 seconds
Started Jun 02 03:05:49 PM PDT 24
Finished Jun 02 03:05:51 PM PDT 24
Peak memory 217792 kb
Host smart-c2cd22b8-b10a-4e93-8dc1-a27d71b382fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227946549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2227946549
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2142188461
Short name T206
Test name
Test status
Simulation time 133072322 ps
CPU time 1.42 seconds
Started Jun 02 03:05:44 PM PDT 24
Finished Jun 02 03:05:46 PM PDT 24
Peak memory 211940 kb
Host smart-b7302f4f-7286-4e77-a25a-585160f589d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142188461 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2142188461
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.4024709220
Short name T209
Test name
Test status
Simulation time 255667720 ps
CPU time 1.84 seconds
Started Jun 02 03:05:53 PM PDT 24
Finished Jun 02 03:05:56 PM PDT 24
Peak memory 218132 kb
Host smart-1bda16bc-4ee1-4123-ad93-77cd22302c7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024709220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.4024709220
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3721303076
Short name T990
Test name
Test status
Simulation time 96063298 ps
CPU time 2.38 seconds
Started Jun 02 03:05:48 PM PDT 24
Finished Jun 02 03:05:51 PM PDT 24
Peak memory 218236 kb
Host smart-7d4267aa-055c-4698-8b86-fd25273a3565
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721303076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3721303076
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.1243161328
Short name T980
Test name
Test status
Simulation time 31139936 ps
CPU time 1.29 seconds
Started Jun 02 03:05:52 PM PDT 24
Finished Jun 02 03:05:54 PM PDT 24
Peak memory 219632 kb
Host smart-289836c4-5bd8-4c35-a63c-042b952232c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243161328 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.1243161328
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2960319888
Short name T929
Test name
Test status
Simulation time 14706684 ps
CPU time 1.09 seconds
Started Jun 02 03:05:50 PM PDT 24
Finished Jun 02 03:05:52 PM PDT 24
Peak memory 209852 kb
Host smart-439d7b6d-4730-47d4-bc9c-60dafedd68bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960319888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.2960319888
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.4151884163
Short name T940
Test name
Test status
Simulation time 34463039 ps
CPU time 1.12 seconds
Started Jun 02 03:05:49 PM PDT 24
Finished Jun 02 03:05:51 PM PDT 24
Peak memory 209164 kb
Host smart-325719e8-f318-435b-b185-5f997d8bd1e5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151884163 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.4151884163
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.2048263384
Short name T997
Test name
Test status
Simulation time 519939855 ps
CPU time 5.77 seconds
Started Jun 02 03:05:49 PM PDT 24
Finished Jun 02 03:05:56 PM PDT 24
Peak memory 209456 kb
Host smart-dcf1fe01-3731-4d40-9d55-bfcd4e0cb21b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048263384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.2048263384
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.843471745
Short name T893
Test name
Test status
Simulation time 759510149 ps
CPU time 11.27 seconds
Started Jun 02 03:05:49 PM PDT 24
Finished Jun 02 03:06:01 PM PDT 24
Peak memory 209500 kb
Host smart-a98b07ed-9a61-4882-9857-81f82909d216
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843471745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.843471745
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2170776827
Short name T903
Test name
Test status
Simulation time 635307309 ps
CPU time 1.84 seconds
Started Jun 02 03:05:49 PM PDT 24
Finished Jun 02 03:05:51 PM PDT 24
Peak memory 217900 kb
Host smart-d07c7f22-3f1f-46f1-a289-25b2c4e7747d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170776827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2170776827
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1244611546
Short name T957
Test name
Test status
Simulation time 1122337555 ps
CPU time 7.6 seconds
Started Jun 02 03:05:52 PM PDT 24
Finished Jun 02 03:06:00 PM PDT 24
Peak memory 219100 kb
Host smart-1bead621-5efd-4d60-8fe6-23d740fd7417
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124461
1546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1244611546
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1920009784
Short name T943
Test name
Test status
Simulation time 46593743 ps
CPU time 1.51 seconds
Started Jun 02 03:05:51 PM PDT 24
Finished Jun 02 03:05:53 PM PDT 24
Peak memory 209744 kb
Host smart-5939c1cc-5ed9-423d-a9e2-d999c148e813
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920009784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1920009784
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1300310407
Short name T113
Test name
Test status
Simulation time 66186713 ps
CPU time 1.25 seconds
Started Jun 02 03:05:50 PM PDT 24
Finished Jun 02 03:05:52 PM PDT 24
Peak memory 209824 kb
Host smart-b54c54e0-c7ce-4475-9be2-8cba09ff065f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300310407 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1300310407
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3505117425
Short name T998
Test name
Test status
Simulation time 86367520 ps
CPU time 1.02 seconds
Started Jun 02 03:05:50 PM PDT 24
Finished Jun 02 03:05:51 PM PDT 24
Peak memory 209868 kb
Host smart-ecb90511-740b-4a42-869d-4b7e3483db55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505117425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3505117425
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.569313659
Short name T941
Test name
Test status
Simulation time 54639085 ps
CPU time 1.93 seconds
Started Jun 02 03:05:54 PM PDT 24
Finished Jun 02 03:05:56 PM PDT 24
Peak memory 218212 kb
Host smart-8ba20baa-a222-47a8-b7b7-6ad2e9386718
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569313659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.569313659
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2507549467
Short name T978
Test name
Test status
Simulation time 22428542 ps
CPU time 1.38 seconds
Started Jun 02 03:05:55 PM PDT 24
Finished Jun 02 03:05:57 PM PDT 24
Peak memory 219280 kb
Host smart-9e64b470-65bf-40e7-a95a-9ba4500c3615
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507549467 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2507549467
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4095832688
Short name T883
Test name
Test status
Simulation time 12616421 ps
CPU time 0.88 seconds
Started Jun 02 03:05:55 PM PDT 24
Finished Jun 02 03:05:56 PM PDT 24
Peak memory 208900 kb
Host smart-e1e62694-16fb-4f20-8f62-0bc727783b51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095832688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.4095832688
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1312567426
Short name T881
Test name
Test status
Simulation time 446678396 ps
CPU time 1.46 seconds
Started Jun 02 03:05:56 PM PDT 24
Finished Jun 02 03:05:58 PM PDT 24
Peak memory 209380 kb
Host smart-36006e77-e848-4c9e-8e91-2bfd511f5016
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312567426 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1312567426
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2285008737
Short name T887
Test name
Test status
Simulation time 523363710 ps
CPU time 3.23 seconds
Started Jun 02 03:05:54 PM PDT 24
Finished Jun 02 03:05:58 PM PDT 24
Peak memory 209472 kb
Host smart-8e550019-29f3-4748-9e7c-c5409f9d5195
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285008737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2285008737
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2942773776
Short name T122
Test name
Test status
Simulation time 5140921179 ps
CPU time 23.67 seconds
Started Jun 02 03:05:49 PM PDT 24
Finished Jun 02 03:06:14 PM PDT 24
Peak memory 209832 kb
Host smart-88e15e16-bb41-45a6-abdf-bdb3abcd1de9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942773776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2942773776
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.1612098605
Short name T986
Test name
Test status
Simulation time 95041202 ps
CPU time 1.85 seconds
Started Jun 02 03:05:53 PM PDT 24
Finished Jun 02 03:05:55 PM PDT 24
Peak memory 211220 kb
Host smart-b40df840-2720-419f-bac9-91c9ee019cd1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612098605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.1612098605
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4068482728
Short name T970
Test name
Test status
Simulation time 232713214 ps
CPU time 1.55 seconds
Started Jun 02 03:05:54 PM PDT 24
Finished Jun 02 03:05:56 PM PDT 24
Peak memory 218212 kb
Host smart-d50f4db1-293a-4929-ba3f-86eba84006fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406848
2728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4068482728
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.307074420
Short name T914
Test name
Test status
Simulation time 270131295 ps
CPU time 1.35 seconds
Started Jun 02 03:05:50 PM PDT 24
Finished Jun 02 03:05:52 PM PDT 24
Peak memory 209764 kb
Host smart-9c5ee302-c51b-4994-ae73-e74a4c790723
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307074420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.307074420
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1826297601
Short name T210
Test name
Test status
Simulation time 41193726 ps
CPU time 0.98 seconds
Started Jun 02 03:05:54 PM PDT 24
Finished Jun 02 03:05:55 PM PDT 24
Peak memory 209916 kb
Host smart-656be98d-57fb-453d-a527-b61822822294
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826297601 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.1826297601
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3146702252
Short name T982
Test name
Test status
Simulation time 164163345 ps
CPU time 1.34 seconds
Started Jun 02 03:05:54 PM PDT 24
Finished Jun 02 03:05:56 PM PDT 24
Peak memory 209828 kb
Host smart-ea51115d-09e1-4590-bad8-ddef29a413f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146702252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3146702252
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.61064183
Short name T901
Test name
Test status
Simulation time 341469776 ps
CPU time 3.28 seconds
Started Jun 02 03:05:59 PM PDT 24
Finished Jun 02 03:06:03 PM PDT 24
Peak memory 218172 kb
Host smart-3453bb20-9d0d-4727-89a8-09d17da9b764
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61064183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.61064183
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3324129833
Short name T993
Test name
Test status
Simulation time 68532046 ps
CPU time 1.34 seconds
Started Jun 02 03:05:56 PM PDT 24
Finished Jun 02 03:05:58 PM PDT 24
Peak memory 218204 kb
Host smart-210d6cc8-4f8d-4870-99cf-2a11ad1dbab5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324129833 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3324129833
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.1221178336
Short name T975
Test name
Test status
Simulation time 45330413 ps
CPU time 1.08 seconds
Started Jun 02 03:05:55 PM PDT 24
Finished Jun 02 03:05:56 PM PDT 24
Peak memory 209848 kb
Host smart-f8c5d5ee-2999-4676-825a-f0c4e14abb00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221178336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.1221178336
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2829020520
Short name T950
Test name
Test status
Simulation time 67795223 ps
CPU time 1.44 seconds
Started Jun 02 03:05:54 PM PDT 24
Finished Jun 02 03:05:56 PM PDT 24
Peak memory 209228 kb
Host smart-bda5e9ad-38f4-4951-baca-387280979914
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829020520 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2829020520
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1625303137
Short name T921
Test name
Test status
Simulation time 1789385643 ps
CPU time 4.33 seconds
Started Jun 02 03:05:55 PM PDT 24
Finished Jun 02 03:06:00 PM PDT 24
Peak memory 209396 kb
Host smart-21d376c0-ca4b-43ef-8823-aa3294fe2baf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625303137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1625303137
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1962747633
Short name T892
Test name
Test status
Simulation time 9607276610 ps
CPU time 48.75 seconds
Started Jun 02 03:05:54 PM PDT 24
Finished Jun 02 03:06:43 PM PDT 24
Peak memory 209876 kb
Host smart-ce30e20b-8b8c-4e94-a053-9094ffb5d1a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962747633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.1962747633
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2348030056
Short name T114
Test name
Test status
Simulation time 214145472 ps
CPU time 3.19 seconds
Started Jun 02 03:05:55 PM PDT 24
Finished Jun 02 03:05:59 PM PDT 24
Peak memory 211512 kb
Host smart-3e30111d-c10a-43a3-a525-6511e0cb59c5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348030056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2348030056
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3853542314
Short name T900
Test name
Test status
Simulation time 142784505 ps
CPU time 3 seconds
Started Jun 02 03:05:59 PM PDT 24
Finished Jun 02 03:06:03 PM PDT 24
Peak memory 219304 kb
Host smart-12f02d5b-ec9f-425e-bd51-baca209f874e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385354
2314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3853542314
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.312626534
Short name T959
Test name
Test status
Simulation time 33447025 ps
CPU time 1.57 seconds
Started Jun 02 03:05:58 PM PDT 24
Finished Jun 02 03:06:00 PM PDT 24
Peak memory 217852 kb
Host smart-8ec3706f-96b1-429d-9e2e-e3a0df9d71f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312626534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.312626534
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2508096843
Short name T999
Test name
Test status
Simulation time 59647237 ps
CPU time 1.32 seconds
Started Jun 02 03:05:55 PM PDT 24
Finished Jun 02 03:05:57 PM PDT 24
Peak memory 218012 kb
Host smart-62045063-cd01-4e57-9a64-9aa9f809ca81
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508096843 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.2508096843
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.130700874
Short name T965
Test name
Test status
Simulation time 101746937 ps
CPU time 1.2 seconds
Started Jun 02 03:05:55 PM PDT 24
Finished Jun 02 03:05:56 PM PDT 24
Peak memory 217724 kb
Host smart-4db5dd5a-fbb0-4afc-a2f4-555989e1b4fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130700874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.130700874
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.623912079
Short name T971
Test name
Test status
Simulation time 57641836 ps
CPU time 2.75 seconds
Started Jun 02 03:05:57 PM PDT 24
Finished Jun 02 03:06:00 PM PDT 24
Peak memory 218128 kb
Host smart-2b1561b0-ed21-486d-b803-7661e7d5d41a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623912079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.623912079
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.769691043
Short name T936
Test name
Test status
Simulation time 29717674 ps
CPU time 1.71 seconds
Started Jun 02 03:06:01 PM PDT 24
Finished Jun 02 03:06:04 PM PDT 24
Peak memory 219660 kb
Host smart-bb71c762-bc09-44b9-96ce-aa202027fc9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769691043 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.769691043
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.644686771
Short name T954
Test name
Test status
Simulation time 12451031 ps
CPU time 0.87 seconds
Started Jun 02 03:05:58 PM PDT 24
Finished Jun 02 03:05:59 PM PDT 24
Peak memory 209648 kb
Host smart-c31888eb-84b2-4feb-91ea-606430ab77b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644686771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.644686771
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.369339666
Short name T875
Test name
Test status
Simulation time 24112296 ps
CPU time 1.24 seconds
Started Jun 02 03:05:56 PM PDT 24
Finished Jun 02 03:05:58 PM PDT 24
Peak memory 209616 kb
Host smart-860ab2ad-da64-4adc-a6cd-8317b7c73906
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369339666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.369339666
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1851851252
Short name T958
Test name
Test status
Simulation time 1073930743 ps
CPU time 3.15 seconds
Started Jun 02 03:05:58 PM PDT 24
Finished Jun 02 03:06:02 PM PDT 24
Peak memory 217500 kb
Host smart-1942eb26-3d41-4db3-9eb8-5fe9a224eda6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851851252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1851851252
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.921461847
Short name T972
Test name
Test status
Simulation time 4359161146 ps
CPU time 6.32 seconds
Started Jun 02 03:05:56 PM PDT 24
Finished Jun 02 03:06:03 PM PDT 24
Peak memory 210000 kb
Host smart-dfe08edb-1eb2-41b8-83c3-6178a9850448
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921461847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.921461847
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3854619322
Short name T922
Test name
Test status
Simulation time 112103903 ps
CPU time 1.35 seconds
Started Jun 02 03:05:54 PM PDT 24
Finished Jun 02 03:05:56 PM PDT 24
Peak memory 211088 kb
Host smart-0a911288-c034-462e-94e4-6bb967636e0f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854619322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3854619322
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1818351868
Short name T1001
Test name
Test status
Simulation time 80057829 ps
CPU time 2.71 seconds
Started Jun 02 03:05:55 PM PDT 24
Finished Jun 02 03:05:59 PM PDT 24
Peak memory 218264 kb
Host smart-8b5f9297-0884-49b4-b9fc-10be5aeb908b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181835
1868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1818351868
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.16846384
Short name T976
Test name
Test status
Simulation time 385180380 ps
CPU time 1.29 seconds
Started Jun 02 03:05:54 PM PDT 24
Finished Jun 02 03:05:56 PM PDT 24
Peak memory 209724 kb
Host smart-3af1c7cb-ce1a-42f3-a163-b9a652698a5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16846384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 9.lc_ctrl_jtag_csr_rw.16846384
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.4243576510
Short name T930
Test name
Test status
Simulation time 151472315 ps
CPU time 1.47 seconds
Started Jun 02 03:05:55 PM PDT 24
Finished Jun 02 03:05:57 PM PDT 24
Peak memory 218100 kb
Host smart-68bac8f3-99bb-42f4-b407-92b67d4de49f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243576510 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.4243576510
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.4069226980
Short name T204
Test name
Test status
Simulation time 27396406 ps
CPU time 1.2 seconds
Started Jun 02 03:06:02 PM PDT 24
Finished Jun 02 03:06:04 PM PDT 24
Peak memory 209928 kb
Host smart-35149061-a9e2-4a33-90be-37fe6ed48951
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069226980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.4069226980
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1111344566
Short name T909
Test name
Test status
Simulation time 30804931 ps
CPU time 2.13 seconds
Started Jun 02 03:05:58 PM PDT 24
Finished Jun 02 03:06:01 PM PDT 24
Peak memory 218324 kb
Host smart-d509c672-4c8c-48ce-832e-9d22b714782d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111344566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1111344566
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3469058167
Short name T111
Test name
Test status
Simulation time 216968687 ps
CPU time 1.9 seconds
Started Jun 02 03:05:55 PM PDT 24
Finished Jun 02 03:05:58 PM PDT 24
Peak memory 213512 kb
Host smart-cc359411-9593-4998-8eb9-baf2e2453e5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469058167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.3469058167
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3929691848
Short name T757
Test name
Test status
Simulation time 55747142 ps
CPU time 1.3 seconds
Started Jun 02 03:12:11 PM PDT 24
Finished Jun 02 03:12:13 PM PDT 24
Peak memory 209960 kb
Host smart-d7240ac7-8469-4616-99fc-9361dcc9bb3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929691848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3929691848
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.1306163479
Short name T149
Test name
Test status
Simulation time 213497970 ps
CPU time 9.58 seconds
Started Jun 02 03:12:10 PM PDT 24
Finished Jun 02 03:12:20 PM PDT 24
Peak memory 218412 kb
Host smart-50bf1c39-4dd7-4a08-8988-638662d8c070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1306163479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.1306163479
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.3512306481
Short name T528
Test name
Test status
Simulation time 12890504838 ps
CPU time 37.8 seconds
Started Jun 02 03:12:08 PM PDT 24
Finished Jun 02 03:12:46 PM PDT 24
Peak memory 219288 kb
Host smart-b8212bee-4ad0-4fb4-911b-99b50758cc56
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512306481 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.3512306481
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.3653816209
Short name T776
Test name
Test status
Simulation time 1280380894 ps
CPU time 15.39 seconds
Started Jun 02 03:12:11 PM PDT 24
Finished Jun 02 03:12:28 PM PDT 24
Peak memory 218168 kb
Host smart-fe6835a1-fc7c-4fa9-afaa-1c0a9d7cf509
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653816209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.3
653816209
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3092099205
Short name T599
Test name
Test status
Simulation time 650644354 ps
CPU time 11.08 seconds
Started Jun 02 03:12:09 PM PDT 24
Finished Jun 02 03:12:20 PM PDT 24
Peak memory 218396 kb
Host smart-930195f5-61e3-4790-b437-04ef16a4aa85
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092099205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3092099205
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2548392733
Short name T873
Test name
Test status
Simulation time 1370315983 ps
CPU time 38.54 seconds
Started Jun 02 03:12:10 PM PDT 24
Finished Jun 02 03:12:49 PM PDT 24
Peak memory 218124 kb
Host smart-e6fe9205-151f-41bf-b1f4-756a96dc7926
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548392733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2548392733
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1442390812
Short name T747
Test name
Test status
Simulation time 630164700 ps
CPU time 1.64 seconds
Started Jun 02 03:12:08 PM PDT 24
Finished Jun 02 03:12:11 PM PDT 24
Peak memory 218104 kb
Host smart-da367adc-e466-4a60-9e8a-d7861c32c210
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442390812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1442390812
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.596387978
Short name T469
Test name
Test status
Simulation time 836401378 ps
CPU time 31.44 seconds
Started Jun 02 03:12:11 PM PDT 24
Finished Jun 02 03:12:43 PM PDT 24
Peak memory 251232 kb
Host smart-13ffdad0-2d64-4f39-8407-9f0c2b48fd03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596387978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_state_failure.596387978
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.3883559496
Short name T324
Test name
Test status
Simulation time 3933585615 ps
CPU time 31.29 seconds
Started Jun 02 03:12:08 PM PDT 24
Finished Jun 02 03:12:40 PM PDT 24
Peak memory 250032 kb
Host smart-c1b74f14-1f7e-4ced-8047-2b225f10a892
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883559496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.3883559496
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.765854991
Short name T96
Test name
Test status
Simulation time 349439854 ps
CPU time 2.73 seconds
Started Jun 02 03:12:04 PM PDT 24
Finished Jun 02 03:12:08 PM PDT 24
Peak memory 218376 kb
Host smart-38a7758d-6bd6-48b6-94a5-8403def075d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765854991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.765854991
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1615234728
Short name T338
Test name
Test status
Simulation time 529980706 ps
CPU time 19.46 seconds
Started Jun 02 03:12:08 PM PDT 24
Finished Jun 02 03:12:28 PM PDT 24
Peak memory 214812 kb
Host smart-4b308e42-a23c-4c98-8de3-8316639a32ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615234728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1615234728
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2068637636
Short name T45
Test name
Test status
Simulation time 291869254 ps
CPU time 24.15 seconds
Started Jun 02 03:12:10 PM PDT 24
Finished Jun 02 03:12:35 PM PDT 24
Peak memory 284516 kb
Host smart-a53cb855-c25f-4e54-b094-73b72fbfbef2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068637636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2068637636
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.2380377909
Short name T483
Test name
Test status
Simulation time 1294566970 ps
CPU time 12.22 seconds
Started Jun 02 03:12:11 PM PDT 24
Finished Jun 02 03:12:24 PM PDT 24
Peak memory 219340 kb
Host smart-0dcf39c2-73d5-496d-851c-783a54d75e54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380377909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.2380377909
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.2922708240
Short name T656
Test name
Test status
Simulation time 1864613645 ps
CPU time 11.36 seconds
Started Jun 02 03:12:08 PM PDT 24
Finished Jun 02 03:12:20 PM PDT 24
Peak memory 226296 kb
Host smart-e8627345-1010-47f0-9f02-69304e92a8af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922708240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.2922708240
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.2044142253
Short name T622
Test name
Test status
Simulation time 334383628 ps
CPU time 9.14 seconds
Started Jun 02 03:12:11 PM PDT 24
Finished Jun 02 03:12:21 PM PDT 24
Peak memory 225412 kb
Host smart-8ec0899a-a262-46fb-9aff-71e19cc72e62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044142253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.2
044142253
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.845714583
Short name T790
Test name
Test status
Simulation time 527878924 ps
CPU time 9.98 seconds
Started Jun 02 03:12:10 PM PDT 24
Finished Jun 02 03:12:21 PM PDT 24
Peak memory 218484 kb
Host smart-1238ce32-f3b4-4aa8-97c6-d755082237eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845714583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.845714583
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.3181586614
Short name T629
Test name
Test status
Simulation time 27600661 ps
CPU time 1.47 seconds
Started Jun 02 03:12:04 PM PDT 24
Finished Jun 02 03:12:06 PM PDT 24
Peak memory 213936 kb
Host smart-52d6f032-59e9-4ae8-a7f4-ec4e3c7609f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181586614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.3181586614
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2297352874
Short name T313
Test name
Test status
Simulation time 1057955598 ps
CPU time 23.68 seconds
Started Jun 02 03:12:05 PM PDT 24
Finished Jun 02 03:12:29 PM PDT 24
Peak memory 251332 kb
Host smart-fbbe6735-4473-4ee9-a12a-df6346c018d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297352874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2297352874
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3849235457
Short name T357
Test name
Test status
Simulation time 84000966 ps
CPU time 3.49 seconds
Started Jun 02 03:12:04 PM PDT 24
Finished Jun 02 03:12:09 PM PDT 24
Peak memory 218372 kb
Host smart-2d923308-b897-4c50-bd9d-b5afb66d13f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849235457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3849235457
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.219759199
Short name T754
Test name
Test status
Simulation time 14785723 ps
CPU time 0.95 seconds
Started Jun 02 03:12:06 PM PDT 24
Finished Jun 02 03:12:07 PM PDT 24
Peak memory 211980 kb
Host smart-5870c2d4-0910-4d2c-b607-82c22c35a2d7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219759199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctr
l_volatile_unlock_smoke.219759199
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.2720811013
Short name T830
Test name
Test status
Simulation time 18755557 ps
CPU time 0.95 seconds
Started Jun 02 03:12:14 PM PDT 24
Finished Jun 02 03:12:15 PM PDT 24
Peak memory 209024 kb
Host smart-5e69d9eb-f853-4c3c-8d2d-529a8a9641b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720811013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.2720811013
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3755438422
Short name T580
Test name
Test status
Simulation time 514981092 ps
CPU time 12.3 seconds
Started Jun 02 03:12:09 PM PDT 24
Finished Jun 02 03:12:22 PM PDT 24
Peak memory 218420 kb
Host smart-fe494311-26ea-4060-9530-aa2f882f5aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755438422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3755438422
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.3223153465
Short name T530
Test name
Test status
Simulation time 3258285277 ps
CPU time 10.73 seconds
Started Jun 02 03:12:15 PM PDT 24
Finished Jun 02 03:12:27 PM PDT 24
Peak memory 209980 kb
Host smart-98820362-234c-4c1f-b977-73de38f5b527
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223153465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.3223153465
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1624345521
Short name T467
Test name
Test status
Simulation time 9740276794 ps
CPU time 68.62 seconds
Started Jun 02 03:12:17 PM PDT 24
Finished Jun 02 03:13:26 PM PDT 24
Peak memory 219028 kb
Host smart-ad5983c6-7cf2-42d9-a2af-33e2073ca6e0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624345521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1624345521
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.3028631334
Short name T300
Test name
Test status
Simulation time 783556460 ps
CPU time 10.84 seconds
Started Jun 02 03:12:13 PM PDT 24
Finished Jun 02 03:12:25 PM PDT 24
Peak memory 217944 kb
Host smart-40511ca9-981e-49ed-a71a-5b8570c11ff0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028631334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.3
028631334
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.2020334441
Short name T684
Test name
Test status
Simulation time 1747328728 ps
CPU time 7.43 seconds
Started Jun 02 03:12:20 PM PDT 24
Finished Jun 02 03:12:28 PM PDT 24
Peak memory 218316 kb
Host smart-e8a37cf2-f80a-40b1-8239-015bbf624cd7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020334441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.2020334441
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.642659101
Short name T730
Test name
Test status
Simulation time 265381839 ps
CPU time 7.34 seconds
Started Jun 02 03:12:14 PM PDT 24
Finished Jun 02 03:12:22 PM PDT 24
Peak memory 218040 kb
Host smart-40ee1cf0-ed98-4a3f-9c1f-29115964b8ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642659101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.642659101
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.1446076231
Short name T440
Test name
Test status
Simulation time 7822902942 ps
CPU time 122.64 seconds
Started Jun 02 03:12:14 PM PDT 24
Finished Jun 02 03:14:18 PM PDT 24
Peak memory 284068 kb
Host smart-05e642f3-ac47-4948-93f7-ab5ab9963866
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446076231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.1446076231
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1730239385
Short name T720
Test name
Test status
Simulation time 265191762 ps
CPU time 9.7 seconds
Started Jun 02 03:12:14 PM PDT 24
Finished Jun 02 03:12:25 PM PDT 24
Peak memory 218340 kb
Host smart-9ab29fc7-9fdf-4cee-abfd-0043b30ae275
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730239385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1730239385
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2383678793
Short name T780
Test name
Test status
Simulation time 67545943 ps
CPU time 3.35 seconds
Started Jun 02 03:12:06 PM PDT 24
Finished Jun 02 03:12:10 PM PDT 24
Peak memory 218428 kb
Host smart-5a572b24-2705-4b67-b929-048fb219b915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383678793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2383678793
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2284244121
Short name T729
Test name
Test status
Simulation time 1003418681 ps
CPU time 16.61 seconds
Started Jun 02 03:12:09 PM PDT 24
Finished Jun 02 03:12:26 PM PDT 24
Peak memory 215064 kb
Host smart-36397933-0ee1-49cf-9f60-3ae20d532c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284244121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2284244121
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.434340338
Short name T84
Test name
Test status
Simulation time 1440664006 ps
CPU time 39.09 seconds
Started Jun 02 03:12:15 PM PDT 24
Finished Jun 02 03:12:55 PM PDT 24
Peak memory 271320 kb
Host smart-57629300-cea2-49d1-95e0-cd5c681fab46
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434340338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.434340338
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.226529066
Short name T765
Test name
Test status
Simulation time 1462378354 ps
CPU time 10.58 seconds
Started Jun 02 03:12:12 PM PDT 24
Finished Jun 02 03:12:23 PM PDT 24
Peak memory 219348 kb
Host smart-bef99d3b-9909-4d3a-8f18-30884142f356
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226529066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.226529066
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1331335378
Short name T709
Test name
Test status
Simulation time 1657417145 ps
CPU time 10.47 seconds
Started Jun 02 03:12:20 PM PDT 24
Finished Jun 02 03:12:31 PM PDT 24
Peak memory 226476 kb
Host smart-eefd44e4-371e-4ece-8afa-37789f0c6f08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331335378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1331335378
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1944711084
Short name T488
Test name
Test status
Simulation time 4262884101 ps
CPU time 9.41 seconds
Started Jun 02 03:12:20 PM PDT 24
Finished Jun 02 03:12:31 PM PDT 24
Peak memory 226556 kb
Host smart-7c2ab73e-0726-4625-92ee-ecca7dec303a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944711084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
944711084
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.1347463510
Short name T857
Test name
Test status
Simulation time 33566578 ps
CPU time 1.51 seconds
Started Jun 02 03:12:11 PM PDT 24
Finished Jun 02 03:12:14 PM PDT 24
Peak memory 213852 kb
Host smart-6f87ed11-2a56-40ae-a84e-787af87f920b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347463510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.1347463510
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.1316037437
Short name T542
Test name
Test status
Simulation time 168882609 ps
CPU time 18.72 seconds
Started Jun 02 03:12:08 PM PDT 24
Finished Jun 02 03:12:27 PM PDT 24
Peak memory 251332 kb
Host smart-3d160b6b-fb53-4356-921b-07839c088fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316037437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.1316037437
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3121994844
Short name T566
Test name
Test status
Simulation time 64617794 ps
CPU time 3.65 seconds
Started Jun 02 03:12:09 PM PDT 24
Finished Jun 02 03:12:13 PM PDT 24
Peak memory 218408 kb
Host smart-8b061ab2-9f77-40e9-9f3a-804a55b0586b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121994844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3121994844
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.1503364286
Short name T421
Test name
Test status
Simulation time 19805733212 ps
CPU time 175.06 seconds
Started Jun 02 03:12:15 PM PDT 24
Finished Jun 02 03:15:10 PM PDT 24
Peak memory 251192 kb
Host smart-b30c43d0-5571-4e33-8a29-d7538d74c1b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503364286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.1503364286
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.1287052439
Short name T152
Test name
Test status
Simulation time 18351101384 ps
CPU time 578.53 seconds
Started Jun 02 03:12:20 PM PDT 24
Finished Jun 02 03:22:00 PM PDT 24
Peak memory 267888 kb
Host smart-448aae64-62ed-48e3-818f-ddec128a2155
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1287052439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.1287052439
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1647769701
Short name T371
Test name
Test status
Simulation time 59619030 ps
CPU time 0.98 seconds
Started Jun 02 03:12:10 PM PDT 24
Finished Jun 02 03:12:12 PM PDT 24
Peak memory 211996 kb
Host smart-154e00d0-d1c3-486f-941c-60ed0fec5e66
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647769701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1647769701
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.1773255988
Short name T523
Test name
Test status
Simulation time 88421560 ps
CPU time 1.18 seconds
Started Jun 02 03:12:58 PM PDT 24
Finished Jun 02 03:13:00 PM PDT 24
Peak memory 209160 kb
Host smart-8096cc6d-0338-472a-8b5f-ead5eb4edb8b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773255988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.1773255988
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.189641184
Short name T462
Test name
Test status
Simulation time 1874215708 ps
CPU time 10.78 seconds
Started Jun 02 03:12:58 PM PDT 24
Finished Jun 02 03:13:09 PM PDT 24
Peak memory 209924 kb
Host smart-96fbb003-13cd-4568-8c51-d6341e23ed18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189641184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.189641184
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2779342129
Short name T770
Test name
Test status
Simulation time 982629106 ps
CPU time 20.14 seconds
Started Jun 02 03:12:57 PM PDT 24
Finished Jun 02 03:13:18 PM PDT 24
Peak memory 218324 kb
Host smart-677ec18c-ddab-4271-8215-fceb90a92869
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779342129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2779342129
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2892349819
Short name T546
Test name
Test status
Simulation time 2096236794 ps
CPU time 7.56 seconds
Started Jun 02 03:12:53 PM PDT 24
Finished Jun 02 03:13:01 PM PDT 24
Peak memory 218376 kb
Host smart-5c183f09-8eee-4920-bcab-9f67950fdd09
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892349819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2892349819
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.2552474205
Short name T691
Test name
Test status
Simulation time 130420558 ps
CPU time 4.5 seconds
Started Jun 02 03:12:52 PM PDT 24
Finished Jun 02 03:12:57 PM PDT 24
Peak memory 218068 kb
Host smart-41876c10-2893-47f4-bcb6-5fcbf25e89fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552474205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.2552474205
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.1705411160
Short name T262
Test name
Test status
Simulation time 4582373046 ps
CPU time 75.86 seconds
Started Jun 02 03:12:54 PM PDT 24
Finished Jun 02 03:14:11 PM PDT 24
Peak memory 283632 kb
Host smart-30c4be64-da43-4ee2-a8b6-ab50e286eef7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705411160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.1705411160
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.3333982202
Short name T473
Test name
Test status
Simulation time 3000601706 ps
CPU time 23.11 seconds
Started Jun 02 03:12:54 PM PDT 24
Finished Jun 02 03:13:18 PM PDT 24
Peak memory 224628 kb
Host smart-09969d94-fb5d-44c6-a83b-e301ecc5d0a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333982202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.3333982202
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2589439681
Short name T298
Test name
Test status
Simulation time 206834788 ps
CPU time 2.67 seconds
Started Jun 02 03:12:55 PM PDT 24
Finished Jun 02 03:12:58 PM PDT 24
Peak memory 218396 kb
Host smart-0e8bd31d-b3a9-4bd6-9153-5fbb98720455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589439681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2589439681
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.4116128382
Short name T481
Test name
Test status
Simulation time 244461921 ps
CPU time 10.66 seconds
Started Jun 02 03:12:58 PM PDT 24
Finished Jun 02 03:13:09 PM PDT 24
Peak memory 218540 kb
Host smart-dec0c37f-5706-4523-9601-f2488862c1b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116128382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.4116128382
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.2134235152
Short name T660
Test name
Test status
Simulation time 329353400 ps
CPU time 11.9 seconds
Started Jun 02 03:12:57 PM PDT 24
Finished Jun 02 03:13:09 PM PDT 24
Peak memory 226584 kb
Host smart-89629c47-dcc4-4317-8d3d-a7cd0988cf73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134235152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.2134235152
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1242661807
Short name T815
Test name
Test status
Simulation time 308013819 ps
CPU time 10.17 seconds
Started Jun 02 03:12:57 PM PDT 24
Finished Jun 02 03:13:08 PM PDT 24
Peak memory 225136 kb
Host smart-2c3ac4b4-0eef-4026-9232-a53c168a99e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242661807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1242661807
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.531958205
Short name T593
Test name
Test status
Simulation time 1637923091 ps
CPU time 10.06 seconds
Started Jun 02 03:12:55 PM PDT 24
Finished Jun 02 03:13:06 PM PDT 24
Peak memory 225356 kb
Host smart-78ee65e4-dc7f-4f70-9c7b-46da13fd62a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531958205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.531958205
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3118937650
Short name T634
Test name
Test status
Simulation time 22909881 ps
CPU time 1.41 seconds
Started Jun 02 03:12:54 PM PDT 24
Finished Jun 02 03:12:56 PM PDT 24
Peak memory 213928 kb
Host smart-4ddf357c-ed58-4676-a9c2-c67c5bb81a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118937650 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3118937650
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.4181725520
Short name T259
Test name
Test status
Simulation time 229850700 ps
CPU time 23.52 seconds
Started Jun 02 03:12:54 PM PDT 24
Finished Jun 02 03:13:18 PM PDT 24
Peak memory 251060 kb
Host smart-c759fee2-dfd4-42b2-a4f7-d2e55e9f67b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181725520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.4181725520
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2184846578
Short name T818
Test name
Test status
Simulation time 67095623 ps
CPU time 7.34 seconds
Started Jun 02 03:12:56 PM PDT 24
Finished Jun 02 03:13:04 PM PDT 24
Peak memory 250912 kb
Host smart-0a2e8bb0-c659-49fd-8d89-019f731b144a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184846578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2184846578
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.223482862
Short name T516
Test name
Test status
Simulation time 10412663116 ps
CPU time 362.86 seconds
Started Jun 02 03:12:59 PM PDT 24
Finished Jun 02 03:19:03 PM PDT 24
Peak memory 310912 kb
Host smart-a3c061c2-4148-4075-b9fe-3e3dbb9d687a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223482862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.223482862
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.1758600223
Short name T236
Test name
Test status
Simulation time 35105863 ps
CPU time 0.87 seconds
Started Jun 02 03:12:55 PM PDT 24
Finished Jun 02 03:12:56 PM PDT 24
Peak memory 211904 kb
Host smart-761768ab-1012-4656-9ab8-e347c9aba68b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758600223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.1758600223
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2029501253
Short name T655
Test name
Test status
Simulation time 23948798 ps
CPU time 1.05 seconds
Started Jun 02 03:13:01 PM PDT 24
Finished Jun 02 03:13:03 PM PDT 24
Peak memory 209964 kb
Host smart-de763c54-d41f-4324-b130-91be12b64f06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029501253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2029501253
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.2018451255
Short name T866
Test name
Test status
Simulation time 615698146 ps
CPU time 13.86 seconds
Started Jun 02 03:12:56 PM PDT 24
Finished Jun 02 03:13:11 PM PDT 24
Peak memory 218480 kb
Host smart-a3476b81-1d92-4ffd-96e4-ab8b0dc26b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018451255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.2018451255
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.3388093692
Short name T550
Test name
Test status
Simulation time 2177339034 ps
CPU time 11.72 seconds
Started Jun 02 03:13:02 PM PDT 24
Finished Jun 02 03:13:14 PM PDT 24
Peak memory 217572 kb
Host smart-a1189c29-1d05-4e7d-b981-b49b64e0801e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388093692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.3388093692
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.3200709003
Short name T41
Test name
Test status
Simulation time 2527972470 ps
CPU time 28.55 seconds
Started Jun 02 03:13:03 PM PDT 24
Finished Jun 02 03:13:33 PM PDT 24
Peak memory 219344 kb
Host smart-55c41667-8716-42a8-893c-e15c0d202453
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200709003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.3200709003
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.466009059
Short name T288
Test name
Test status
Simulation time 3553151250 ps
CPU time 5.08 seconds
Started Jun 02 03:13:03 PM PDT 24
Finished Jun 02 03:13:09 PM PDT 24
Peak memory 218380 kb
Host smart-5f323087-6849-4dd4-a943-760269bb6f54
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466009059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.466009059
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.1176291454
Short name T258
Test name
Test status
Simulation time 482616808 ps
CPU time 4.28 seconds
Started Jun 02 03:12:59 PM PDT 24
Finished Jun 02 03:13:03 PM PDT 24
Peak memory 218032 kb
Host smart-40671c56-f3fd-4afc-99d7-670f86d85328
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176291454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.1176291454
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.562112896
Short name T541
Test name
Test status
Simulation time 5783814798 ps
CPU time 40.09 seconds
Started Jun 02 03:13:05 PM PDT 24
Finished Jun 02 03:13:45 PM PDT 24
Peak memory 275980 kb
Host smart-a1c434be-a73a-4b4c-9e1e-a83aa29d5ea4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562112896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_state_failure.562112896
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3381297292
Short name T249
Test name
Test status
Simulation time 526058819 ps
CPU time 17.5 seconds
Started Jun 02 03:13:04 PM PDT 24
Finished Jun 02 03:13:22 PM PDT 24
Peak memory 250604 kb
Host smart-741101ff-aae4-465a-9a04-309d41bacd7e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381297292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3381297292
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1959634452
Short name T726
Test name
Test status
Simulation time 50411340 ps
CPU time 2.5 seconds
Started Jun 02 03:12:58 PM PDT 24
Finished Jun 02 03:13:01 PM PDT 24
Peak memory 218352 kb
Host smart-082e0021-c554-4620-b989-bae85ae360ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959634452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1959634452
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.989255208
Short name T864
Test name
Test status
Simulation time 720335348 ps
CPU time 10.21 seconds
Started Jun 02 03:13:02 PM PDT 24
Finished Jun 02 03:13:13 PM PDT 24
Peak memory 218600 kb
Host smart-f16af536-6733-4288-bb36-b376bd2aa0d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989255208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.989255208
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.4232315084
Short name T833
Test name
Test status
Simulation time 1765046044 ps
CPU time 17.68 seconds
Started Jun 02 03:13:03 PM PDT 24
Finished Jun 02 03:13:21 PM PDT 24
Peak memory 226448 kb
Host smart-7765df96-b357-4974-a15e-ce84e8be9db2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232315084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.4232315084
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.2206242852
Short name T676
Test name
Test status
Simulation time 550646887 ps
CPU time 6.24 seconds
Started Jun 02 03:13:04 PM PDT 24
Finished Jun 02 03:13:11 PM PDT 24
Peak memory 224924 kb
Host smart-776e8be9-c6d4-4366-8026-99f9b795acba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206242852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
2206242852
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2501898497
Short name T377
Test name
Test status
Simulation time 276857271 ps
CPU time 8.44 seconds
Started Jun 02 03:12:57 PM PDT 24
Finished Jun 02 03:13:06 PM PDT 24
Peak memory 218476 kb
Host smart-403a5916-5bbb-48f1-8220-2f84d2d14234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501898497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2501898497
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.1810424816
Short name T380
Test name
Test status
Simulation time 56910718 ps
CPU time 4.06 seconds
Started Jun 02 03:13:00 PM PDT 24
Finished Jun 02 03:13:04 PM PDT 24
Peak memory 218172 kb
Host smart-d9f2a476-2e81-4620-a3e5-6e9a29ca2e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810424816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1810424816
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3881266588
Short name T653
Test name
Test status
Simulation time 229027564 ps
CPU time 24.31 seconds
Started Jun 02 03:12:58 PM PDT 24
Finished Jun 02 03:13:23 PM PDT 24
Peak memory 251388 kb
Host smart-f1ddda2b-3483-4988-8c53-30cbc086d937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881266588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3881266588
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.52788774
Short name T637
Test name
Test status
Simulation time 153924556 ps
CPU time 3.03 seconds
Started Jun 02 03:12:58 PM PDT 24
Finished Jun 02 03:13:02 PM PDT 24
Peak memory 218348 kb
Host smart-be1e7c46-d18c-40a2-bede-6eb450d4a78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52788774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.52788774
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2043131486
Short name T275
Test name
Test status
Simulation time 7706314658 ps
CPU time 93.96 seconds
Started Jun 02 03:13:01 PM PDT 24
Finished Jun 02 03:14:36 PM PDT 24
Peak memory 279104 kb
Host smart-ef8e4c5f-4a95-4ced-95cb-c99c54f882de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043131486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2043131486
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.2040385230
Short name T285
Test name
Test status
Simulation time 14027902 ps
CPU time 1.03 seconds
Started Jun 02 03:12:56 PM PDT 24
Finished Jun 02 03:12:58 PM PDT 24
Peak memory 211892 kb
Host smart-36a7e1d9-fc0c-4170-b8ac-09fadf075c60
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040385230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.2040385230
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.1861567994
Short name T8
Test name
Test status
Simulation time 20135192 ps
CPU time 0.94 seconds
Started Jun 02 03:13:10 PM PDT 24
Finished Jun 02 03:13:12 PM PDT 24
Peak memory 209128 kb
Host smart-013e5429-d0c8-40c8-b909-b7c874ad1227
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861567994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.1861567994
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3817171794
Short name T178
Test name
Test status
Simulation time 445533722 ps
CPU time 11.89 seconds
Started Jun 02 03:13:03 PM PDT 24
Finished Jun 02 03:13:16 PM PDT 24
Peak memory 218356 kb
Host smart-c2a0321c-73ab-4106-99e5-4cf149259aef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817171794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3817171794
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.19530259
Short name T821
Test name
Test status
Simulation time 798362734 ps
CPU time 6.13 seconds
Started Jun 02 03:13:09 PM PDT 24
Finished Jun 02 03:13:15 PM PDT 24
Peak memory 217344 kb
Host smart-cca354b6-afca-4e55-9172-22bd843f67ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19530259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.19530259
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.958185087
Short name T403
Test name
Test status
Simulation time 18777717192 ps
CPU time 33.04 seconds
Started Jun 02 03:13:08 PM PDT 24
Finished Jun 02 03:13:41 PM PDT 24
Peak memory 218728 kb
Host smart-ecd21094-a5e4-4492-8eac-8746b634c529
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958185087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_er
rors.958185087
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1059905680
Short name T408
Test name
Test status
Simulation time 457753750 ps
CPU time 4.86 seconds
Started Jun 02 03:13:05 PM PDT 24
Finished Jun 02 03:13:10 PM PDT 24
Peak memory 218296 kb
Host smart-cb5c0042-a742-4d1d-a246-1740e60945e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059905680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1059905680
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.4062200900
Short name T253
Test name
Test status
Simulation time 359017222 ps
CPU time 9.83 seconds
Started Jun 02 03:13:03 PM PDT 24
Finished Jun 02 03:13:14 PM PDT 24
Peak memory 218060 kb
Host smart-58fac88c-ef3e-489a-ad25-48415fb88603
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062200900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.4062200900
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.610750298
Short name T429
Test name
Test status
Simulation time 2864649712 ps
CPU time 37.42 seconds
Started Jun 02 03:13:07 PM PDT 24
Finished Jun 02 03:13:44 PM PDT 24
Peak memory 275892 kb
Host smart-f4073921-0af3-4644-bcf8-98672fa7002b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610750298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_state_failure.610750298
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.270274874
Short name T220
Test name
Test status
Simulation time 6605219186 ps
CPU time 32.14 seconds
Started Jun 02 03:13:06 PM PDT 24
Finished Jun 02 03:13:39 PM PDT 24
Peak memory 250984 kb
Host smart-3e77934a-b963-4abf-9d69-f87d4db198f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270274874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.270274874
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1467420503
Short name T444
Test name
Test status
Simulation time 268526878 ps
CPU time 2.15 seconds
Started Jun 02 03:13:08 PM PDT 24
Finished Jun 02 03:13:11 PM PDT 24
Peak memory 218420 kb
Host smart-76ebfc72-dc35-4e47-b88a-47668f640a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1467420503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1467420503
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.841645556
Short name T248
Test name
Test status
Simulation time 981609816 ps
CPU time 11.25 seconds
Started Jun 02 03:13:08 PM PDT 24
Finished Jun 02 03:13:20 PM PDT 24
Peak memory 219300 kb
Host smart-721d8aa2-e3ab-4777-b10f-e588b60cdd26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841645556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.841645556
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2188069096
Short name T260
Test name
Test status
Simulation time 377252443 ps
CPU time 15.06 seconds
Started Jun 02 03:13:08 PM PDT 24
Finished Jun 02 03:13:24 PM PDT 24
Peak memory 225832 kb
Host smart-d4ef0394-ef28-4aa1-bc51-740972cf0c77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188069096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2188069096
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.355738142
Short name T734
Test name
Test status
Simulation time 740015153 ps
CPU time 7.51 seconds
Started Jun 02 03:13:08 PM PDT 24
Finished Jun 02 03:13:16 PM PDT 24
Peak memory 225120 kb
Host smart-7a9175d4-7a1d-4e0a-847a-d0e30c75823a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355738142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.355738142
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.627408005
Short name T604
Test name
Test status
Simulation time 431675407 ps
CPU time 14.56 seconds
Started Jun 02 03:13:03 PM PDT 24
Finished Jun 02 03:13:18 PM PDT 24
Peak memory 218548 kb
Host smart-b865be0c-c023-482a-b784-36d8dd016efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627408005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.627408005
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.3570133695
Short name T184
Test name
Test status
Simulation time 2798696769 ps
CPU time 3.98 seconds
Started Jun 02 03:13:03 PM PDT 24
Finished Jun 02 03:13:08 PM PDT 24
Peak memory 218172 kb
Host smart-8c532d5c-76c7-4695-a58e-40950b03ce92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570133695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.3570133695
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.4030224825
Short name T694
Test name
Test status
Simulation time 387140964 ps
CPU time 24.78 seconds
Started Jun 02 03:13:02 PM PDT 24
Finished Jun 02 03:13:28 PM PDT 24
Peak memory 251336 kb
Host smart-f25a39bd-bfba-4bf3-acb6-c918e8e99567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030224825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.4030224825
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2725235021
Short name T164
Test name
Test status
Simulation time 54609962 ps
CPU time 8.61 seconds
Started Jun 02 03:13:02 PM PDT 24
Finished Jun 02 03:13:12 PM PDT 24
Peak memory 251316 kb
Host smart-a21b65c5-6348-4b5a-b482-2903940d1449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725235021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2725235021
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.1486878973
Short name T760
Test name
Test status
Simulation time 10398480626 ps
CPU time 113.6 seconds
Started Jun 02 03:13:10 PM PDT 24
Finished Jun 02 03:15:04 PM PDT 24
Peak memory 274932 kb
Host smart-a6b5c367-e84f-4371-b048-e080aeb2abc4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486878973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.1486878973
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.3122167768
Short name T140
Test name
Test status
Simulation time 279551931847 ps
CPU time 453.63 seconds
Started Jun 02 03:13:10 PM PDT 24
Finished Jun 02 03:20:44 PM PDT 24
Peak memory 300608 kb
Host smart-157bc0c6-d9f0-4370-b489-ca374e47fae7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3122167768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.3122167768
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.982657542
Short name T225
Test name
Test status
Simulation time 11774737 ps
CPU time 1.05 seconds
Started Jun 02 03:13:03 PM PDT 24
Finished Jun 02 03:13:04 PM PDT 24
Peak memory 211968 kb
Host smart-00a273b9-03aa-44de-9c01-ca28ea02d878
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982657542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ct
rl_volatile_unlock_smoke.982657542
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.445262909
Short name T346
Test name
Test status
Simulation time 47601277 ps
CPU time 1.3 seconds
Started Jun 02 03:13:14 PM PDT 24
Finished Jun 02 03:13:16 PM PDT 24
Peak memory 209204 kb
Host smart-412c3a9b-7487-4de6-9106-2c15a4402b87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445262909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.445262909
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2588068819
Short name T160
Test name
Test status
Simulation time 571094618 ps
CPU time 13.23 seconds
Started Jun 02 03:13:07 PM PDT 24
Finished Jun 02 03:13:21 PM PDT 24
Peak memory 218420 kb
Host smart-d55417f2-7809-4e5b-8b3a-53ca8f0bb32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588068819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2588068819
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.309906609
Short name T289
Test name
Test status
Simulation time 1885088686 ps
CPU time 10.97 seconds
Started Jun 02 03:13:14 PM PDT 24
Finished Jun 02 03:13:25 PM PDT 24
Peak memory 217444 kb
Host smart-31465019-7216-4de2-ab4f-c50364f2c3a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309906609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.309906609
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.2177305086
Short name T715
Test name
Test status
Simulation time 3925251098 ps
CPU time 58.62 seconds
Started Jun 02 03:13:13 PM PDT 24
Finished Jun 02 03:14:12 PM PDT 24
Peak memory 219356 kb
Host smart-cd4e3909-6de8-4483-94fa-842246b12f52
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177305086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.2177305086
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2883559230
Short name T27
Test name
Test status
Simulation time 612192495 ps
CPU time 9 seconds
Started Jun 02 03:13:14 PM PDT 24
Finished Jun 02 03:13:23 PM PDT 24
Peak memory 218216 kb
Host smart-4514b0c6-217c-4ccc-8d28-1fb2466fccbb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883559230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2883559230
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.1401020862
Short name T478
Test name
Test status
Simulation time 3102242042 ps
CPU time 10.02 seconds
Started Jun 02 03:13:08 PM PDT 24
Finished Jun 02 03:13:19 PM PDT 24
Peak memory 218032 kb
Host smart-fcb4f0e6-67c3-4868-9074-871f540ca2e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401020862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.1401020862
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3994379425
Short name T279
Test name
Test status
Simulation time 1669680415 ps
CPU time 48.53 seconds
Started Jun 02 03:13:13 PM PDT 24
Finished Jun 02 03:14:02 PM PDT 24
Peak memory 274024 kb
Host smart-4a631be5-659f-43dc-8155-5ea22fc1d0dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994379425 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3994379425
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.14336877
Short name T442
Test name
Test status
Simulation time 4505176449 ps
CPU time 35.33 seconds
Started Jun 02 03:13:16 PM PDT 24
Finished Jun 02 03:13:51 PM PDT 24
Peak memory 250900 kb
Host smart-b8b26022-5b13-4b48-a018-24de57218c21
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14336877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_j
tag_state_post_trans.14336877
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3447670809
Short name T445
Test name
Test status
Simulation time 77727480 ps
CPU time 3.86 seconds
Started Jun 02 03:13:10 PM PDT 24
Finished Jun 02 03:13:14 PM PDT 24
Peak memory 218372 kb
Host smart-a28dbf5c-b6aa-453e-a997-bac8d98a67e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447670809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3447670809
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1355799371
Short name T364
Test name
Test status
Simulation time 1452610218 ps
CPU time 15.13 seconds
Started Jun 02 03:13:13 PM PDT 24
Finished Jun 02 03:13:29 PM PDT 24
Peak memory 219356 kb
Host smart-f1628871-68a4-4fc8-a9e5-5b2a1255a12a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355799371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1355799371
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.1370359345
Short name T792
Test name
Test status
Simulation time 924955976 ps
CPU time 11.96 seconds
Started Jun 02 03:13:12 PM PDT 24
Finished Jun 02 03:13:24 PM PDT 24
Peak memory 225380 kb
Host smart-525c8cfb-d8fd-42c0-af63-31a82570d1d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370359345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.1370359345
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2078875967
Short name T567
Test name
Test status
Simulation time 2942802049 ps
CPU time 8.52 seconds
Started Jun 02 03:13:14 PM PDT 24
Finished Jun 02 03:13:23 PM PDT 24
Peak memory 226560 kb
Host smart-b38e0cb6-1149-436b-a279-7a2f6c89613c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078875967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2078875967
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.4084188634
Short name T472
Test name
Test status
Simulation time 414740748 ps
CPU time 10.95 seconds
Started Jun 02 03:13:06 PM PDT 24
Finished Jun 02 03:13:17 PM PDT 24
Peak memory 218548 kb
Host smart-c97c7ec1-b2b4-4dec-ab09-6841aece971a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084188634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.4084188634
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1668471211
Short name T56
Test name
Test status
Simulation time 54701429 ps
CPU time 3.03 seconds
Started Jun 02 03:13:07 PM PDT 24
Finished Jun 02 03:13:11 PM PDT 24
Peak memory 214884 kb
Host smart-d18085bc-5cbb-4915-8181-efdab2958ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668471211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1668471211
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2893165182
Short name T399
Test name
Test status
Simulation time 241157193 ps
CPU time 30.34 seconds
Started Jun 02 03:13:09 PM PDT 24
Finished Jun 02 03:13:40 PM PDT 24
Peak memory 251392 kb
Host smart-140f6683-15d8-491d-a51b-72b5cb435fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893165182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2893165182
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.4190899016
Short name T419
Test name
Test status
Simulation time 141694799 ps
CPU time 11.04 seconds
Started Jun 02 03:13:06 PM PDT 24
Finished Jun 02 03:13:18 PM PDT 24
Peak memory 251324 kb
Host smart-d5520856-a637-4987-8b73-44aba22024c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190899016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.4190899016
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.3795161606
Short name T425
Test name
Test status
Simulation time 3529493423 ps
CPU time 87.53 seconds
Started Jun 02 03:13:14 PM PDT 24
Finished Jun 02 03:14:42 PM PDT 24
Peak memory 276440 kb
Host smart-2b1e1575-042a-458a-bdf2-df2d059cd22c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795161606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.3795161606
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.339899240
Short name T213
Test name
Test status
Simulation time 8747582954 ps
CPU time 286.8 seconds
Started Jun 02 03:13:14 PM PDT 24
Finished Jun 02 03:18:01 PM PDT 24
Peak memory 438888 kb
Host smart-4097cd9c-1df4-4bb3-af74-2b2d69c14e34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=339899240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_stress_all_with_rand_reset.339899240
Directory /workspace/13.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2119536284
Short name T226
Test name
Test status
Simulation time 48854140 ps
CPU time 0.9 seconds
Started Jun 02 03:13:09 PM PDT 24
Finished Jun 02 03:13:10 PM PDT 24
Peak memory 212028 kb
Host smart-8b67e8b2-080e-4fc3-ae15-e68c8806f6c4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119536284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.2119536284
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.3748522169
Short name T540
Test name
Test status
Simulation time 49324975 ps
CPU time 1.15 seconds
Started Jun 02 03:13:18 PM PDT 24
Finished Jun 02 03:13:20 PM PDT 24
Peak memory 209104 kb
Host smart-76318f58-b425-4e35-b2f8-9d31669a7d90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748522169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.3748522169
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.4209974211
Short name T662
Test name
Test status
Simulation time 374232647 ps
CPU time 8.84 seconds
Started Jun 02 03:13:12 PM PDT 24
Finished Jun 02 03:13:22 PM PDT 24
Peak memory 218480 kb
Host smart-3fe728c6-edef-4c41-8996-78d7bf396b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209974211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.4209974211
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.1115439021
Short name T406
Test name
Test status
Simulation time 4658400214 ps
CPU time 52.65 seconds
Started Jun 02 03:13:14 PM PDT 24
Finished Jun 02 03:14:07 PM PDT 24
Peak memory 218412 kb
Host smart-69828f9a-789a-4701-8ba1-4aed09a5b51d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115439021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.1115439021
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.358487141
Short name T716
Test name
Test status
Simulation time 477481371 ps
CPU time 3.1 seconds
Started Jun 02 03:13:13 PM PDT 24
Finished Jun 02 03:13:16 PM PDT 24
Peak memory 218280 kb
Host smart-81a03536-fb32-4d76-bbad-6b885c0fc08c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358487141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.358487141
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2093361176
Short name T544
Test name
Test status
Simulation time 3462987929 ps
CPU time 15.96 seconds
Started Jun 02 03:13:13 PM PDT 24
Finished Jun 02 03:13:30 PM PDT 24
Peak memory 218244 kb
Host smart-ae5594e9-a89b-451d-a4ba-19392337e575
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093361176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2093361176
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1958435820
Short name T26
Test name
Test status
Simulation time 1855507584 ps
CPU time 74.9 seconds
Started Jun 02 03:13:12 PM PDT 24
Finished Jun 02 03:14:27 PM PDT 24
Peak memory 275852 kb
Host smart-1a681bbe-3599-4c1f-b678-4199a8d68623
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958435820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1958435820
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1516565318
Short name T678
Test name
Test status
Simulation time 476621367 ps
CPU time 9.12 seconds
Started Jun 02 03:13:14 PM PDT 24
Finished Jun 02 03:13:24 PM PDT 24
Peak memory 224304 kb
Host smart-a887aa4d-359c-4db1-b7a7-8b4589b3a1ca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516565318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1516565318
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.1731399553
Short name T547
Test name
Test status
Simulation time 125989541 ps
CPU time 3.17 seconds
Started Jun 02 03:13:12 PM PDT 24
Finished Jun 02 03:13:16 PM PDT 24
Peak memory 218428 kb
Host smart-eb4c055f-6906-4776-8561-1559a91b20ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731399553 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.1731399553
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.732268902
Short name T589
Test name
Test status
Simulation time 739670981 ps
CPU time 14.32 seconds
Started Jun 02 03:13:18 PM PDT 24
Finished Jun 02 03:13:33 PM PDT 24
Peak memory 226504 kb
Host smart-9440feb1-e4a6-4902-9cff-0133d3a0e2ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732268902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.732268902
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.389337814
Short name T493
Test name
Test status
Simulation time 4078701206 ps
CPU time 8.78 seconds
Started Jun 02 03:13:17 PM PDT 24
Finished Jun 02 03:13:27 PM PDT 24
Peak memory 226248 kb
Host smart-e633144a-584c-43df-8ca6-58e17bdaa17a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389337814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.389337814
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.3464944307
Short name T327
Test name
Test status
Simulation time 1300677548 ps
CPU time 11.82 seconds
Started Jun 02 03:13:18 PM PDT 24
Finished Jun 02 03:13:30 PM PDT 24
Peak memory 218296 kb
Host smart-0f0dd502-4db6-4827-97bb-c9d9ca4da231
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464944307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
3464944307
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.4194144342
Short name T464
Test name
Test status
Simulation time 540092532 ps
CPU time 10.09 seconds
Started Jun 02 03:13:13 PM PDT 24
Finished Jun 02 03:13:23 PM PDT 24
Peak memory 218472 kb
Host smart-7c53dfee-600d-4c61-aac6-17f0a31921a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194144342 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.4194144342
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3425631119
Short name T376
Test name
Test status
Simulation time 191363155 ps
CPU time 3.74 seconds
Started Jun 02 03:13:13 PM PDT 24
Finished Jun 02 03:13:17 PM PDT 24
Peak memory 218100 kb
Host smart-bac51bff-807b-4675-adc4-b0d1d89396fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425631119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3425631119
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.714200094
Short name T251
Test name
Test status
Simulation time 282044681 ps
CPU time 23.5 seconds
Started Jun 02 03:13:11 PM PDT 24
Finished Jun 02 03:13:35 PM PDT 24
Peak memory 251320 kb
Host smart-637e20f3-ecfa-485e-8c05-9e12bae9a845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714200094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.714200094
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3773649245
Short name T350
Test name
Test status
Simulation time 115270214 ps
CPU time 7.81 seconds
Started Jun 02 03:13:13 PM PDT 24
Finished Jun 02 03:13:21 PM PDT 24
Peak memory 251396 kb
Host smart-c148df99-948e-4c63-99bd-32cb884748d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773649245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3773649245
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.1912865948
Short name T632
Test name
Test status
Simulation time 1220410041 ps
CPU time 25.33 seconds
Started Jun 02 03:13:19 PM PDT 24
Finished Jun 02 03:13:45 PM PDT 24
Peak memory 251312 kb
Host smart-7cb74302-a11f-406f-8c3d-69f2db575e27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912865948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.1912865948
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.870830900
Short name T139
Test name
Test status
Simulation time 34783504198 ps
CPU time 624.34 seconds
Started Jun 02 03:13:17 PM PDT 24
Finished Jun 02 03:23:42 PM PDT 24
Peak memory 497188 kb
Host smart-0d3cf506-1ab4-4fb4-9217-54381e8ac820
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=870830900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_stress_all_with_rand_reset.870830900
Directory /workspace/14.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.485266740
Short name T733
Test name
Test status
Simulation time 57367574 ps
CPU time 0.9 seconds
Started Jun 02 03:13:14 PM PDT 24
Finished Jun 02 03:13:15 PM PDT 24
Peak memory 212276 kb
Host smart-bc2fec9a-bd2d-475d-9e14-23a3621467cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485266740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.485266740
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.817502471
Short name T635
Test name
Test status
Simulation time 22992927 ps
CPU time 0.82 seconds
Started Jun 02 03:13:28 PM PDT 24
Finished Jun 02 03:13:30 PM PDT 24
Peak memory 208932 kb
Host smart-3c8c1d5e-3455-418e-a95f-d1c1549ebd29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817502471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.817502471
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.921539239
Short name T813
Test name
Test status
Simulation time 1002718506 ps
CPU time 25.31 seconds
Started Jun 02 03:13:17 PM PDT 24
Finished Jun 02 03:13:43 PM PDT 24
Peak memory 218404 kb
Host smart-5d212859-e4ca-42a2-b739-43f1242cecb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921539239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.921539239
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2118104273
Short name T612
Test name
Test status
Simulation time 262956599 ps
CPU time 6.82 seconds
Started Jun 02 03:13:29 PM PDT 24
Finished Jun 02 03:13:36 PM PDT 24
Peak memory 209900 kb
Host smart-5658e741-44e8-4d5a-8dc2-cb38b115eff9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118104273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2118104273
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1875586860
Short name T668
Test name
Test status
Simulation time 2769101293 ps
CPU time 77.08 seconds
Started Jun 02 03:13:26 PM PDT 24
Finished Jun 02 03:14:44 PM PDT 24
Peak memory 219296 kb
Host smart-d32e4446-fb39-45c4-a956-fba80250d6cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875586860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1875586860
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.596193653
Short name T58
Test name
Test status
Simulation time 1521306272 ps
CPU time 10.68 seconds
Started Jun 02 03:13:16 PM PDT 24
Finished Jun 02 03:13:27 PM PDT 24
Peak memory 218480 kb
Host smart-3d2c2a8f-e98c-4e96-a725-340458da52b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596193653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag
_prog_failure.596193653
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.668544320
Short name T394
Test name
Test status
Simulation time 255673730 ps
CPU time 6.58 seconds
Started Jun 02 03:13:18 PM PDT 24
Finished Jun 02 03:13:25 PM PDT 24
Peak memory 218056 kb
Host smart-1a7f3c46-b922-42f7-9b77-2e59d4fcdd8a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668544320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke.
668544320
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1662233675
Short name T286
Test name
Test status
Simulation time 3063452964 ps
CPU time 42.78 seconds
Started Jun 02 03:13:18 PM PDT 24
Finished Jun 02 03:14:01 PM PDT 24
Peak memory 254636 kb
Host smart-8958fff7-b2f6-4ae2-8e6d-b81d13934c05
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662233675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1662233675
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.86385443
Short name T486
Test name
Test status
Simulation time 335830281 ps
CPU time 11.52 seconds
Started Jun 02 03:13:17 PM PDT 24
Finished Jun 02 03:13:28 PM PDT 24
Peak memory 224328 kb
Host smart-033ae7e2-f446-462a-a45d-b018ca1349e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86385443 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_j
tag_state_post_trans.86385443
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.739803843
Short name T378
Test name
Test status
Simulation time 113366695 ps
CPU time 1.79 seconds
Started Jun 02 03:13:19 PM PDT 24
Finished Jun 02 03:13:21 PM PDT 24
Peak memory 218496 kb
Host smart-4bb0a6a6-69cc-4a45-bc93-2a19ce6c6c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739803843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.739803843
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.1145784611
Short name T636
Test name
Test status
Simulation time 11699395698 ps
CPU time 26.18 seconds
Started Jun 02 03:13:20 PM PDT 24
Finished Jun 02 03:13:46 PM PDT 24
Peak memory 226564 kb
Host smart-37c579dd-0377-47b9-a07c-65cdc794e193
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145784611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.1145784611
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1442600466
Short name T822
Test name
Test status
Simulation time 507199017 ps
CPU time 13.19 seconds
Started Jun 02 03:13:20 PM PDT 24
Finished Jun 02 03:13:34 PM PDT 24
Peak memory 218424 kb
Host smart-ddd6e45b-e4a5-4ad3-a9e6-dd24e794758a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442600466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.1442600466
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.1873548248
Short name T853
Test name
Test status
Simulation time 37650580 ps
CPU time 1.89 seconds
Started Jun 02 03:13:17 PM PDT 24
Finished Jun 02 03:13:20 PM PDT 24
Peak memory 214284 kb
Host smart-5f741106-040d-4b08-822d-75d2c85ffe97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873548248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.1873548248
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.31039030
Short name T681
Test name
Test status
Simulation time 188431370 ps
CPU time 20.68 seconds
Started Jun 02 03:13:18 PM PDT 24
Finished Jun 02 03:13:39 PM PDT 24
Peak memory 251332 kb
Host smart-14180838-0e15-4f04-87c5-6a35b5771932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31039030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.31039030
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.460534233
Short name T270
Test name
Test status
Simulation time 76981326 ps
CPU time 7.28 seconds
Started Jun 02 03:13:19 PM PDT 24
Finished Jun 02 03:13:26 PM PDT 24
Peak memory 247244 kb
Host smart-5cbe5ff8-b729-4ccd-bbae-34e0d2236dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460534233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.460534233
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3828517619
Short name T180
Test name
Test status
Simulation time 2737795533 ps
CPU time 15 seconds
Started Jun 02 03:13:24 PM PDT 24
Finished Jun 02 03:13:39 PM PDT 24
Peak memory 224484 kb
Host smart-1ac5c34e-a858-43b9-be45-9bee6abbe8ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828517619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3828517619
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1213715570
Short name T573
Test name
Test status
Simulation time 37321782 ps
CPU time 0.81 seconds
Started Jun 02 03:13:17 PM PDT 24
Finished Jun 02 03:13:19 PM PDT 24
Peak memory 212016 kb
Host smart-d679830e-c09e-46ab-9180-59205580a0c6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213715570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1213715570
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.4011658247
Short name T229
Test name
Test status
Simulation time 54545705 ps
CPU time 0.8 seconds
Started Jun 02 03:13:28 PM PDT 24
Finished Jun 02 03:13:29 PM PDT 24
Peak memory 208988 kb
Host smart-52f3fdea-05a1-4c20-ad2f-312f063b1f27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011658247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.4011658247
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3681995132
Short name T748
Test name
Test status
Simulation time 2042527893 ps
CPU time 16.88 seconds
Started Jun 02 03:13:22 PM PDT 24
Finished Jun 02 03:13:39 PM PDT 24
Peak memory 218396 kb
Host smart-615d0f51-2f88-4e01-8eef-0e933ee4c067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681995132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3681995132
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3521684957
Short name T283
Test name
Test status
Simulation time 335678654 ps
CPU time 8.38 seconds
Started Jun 02 03:13:29 PM PDT 24
Finished Jun 02 03:13:38 PM PDT 24
Peak memory 217428 kb
Host smart-d01ccdd1-3672-4ff3-93c9-15f87df8839c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521684957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3521684957
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.1777392258
Short name T460
Test name
Test status
Simulation time 1788808830 ps
CPU time 32.81 seconds
Started Jun 02 03:13:23 PM PDT 24
Finished Jun 02 03:13:56 PM PDT 24
Peak memory 218336 kb
Host smart-846067d2-a22d-46b7-9906-b39800b46715
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777392258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.1777392258
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.1937541948
Short name T639
Test name
Test status
Simulation time 494286693 ps
CPU time 8.23 seconds
Started Jun 02 03:13:22 PM PDT 24
Finished Jun 02 03:13:30 PM PDT 24
Peak memory 218316 kb
Host smart-fd981686-0a11-4f71-9776-fd43af7149f0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937541948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.1937541948
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2393050391
Short name T870
Test name
Test status
Simulation time 2336630547 ps
CPU time 14.62 seconds
Started Jun 02 03:13:28 PM PDT 24
Finished Jun 02 03:13:43 PM PDT 24
Peak memory 217932 kb
Host smart-a01a0c57-8004-40eb-9df5-04c24985fd55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393050391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2393050391
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.1060608471
Short name T238
Test name
Test status
Simulation time 20641012257 ps
CPU time 50.3 seconds
Started Jun 02 03:13:21 PM PDT 24
Finished Jun 02 03:14:12 PM PDT 24
Peak memory 251376 kb
Host smart-5b822d72-e4c0-48bb-81cc-22da9c0f4457
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060608471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.1060608471
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3385014340
Short name T696
Test name
Test status
Simulation time 772166216 ps
CPU time 26.6 seconds
Started Jun 02 03:13:23 PM PDT 24
Finished Jun 02 03:13:50 PM PDT 24
Peak memory 251272 kb
Host smart-13f551df-d6bc-4797-a15f-7d0428b1451f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385014340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3385014340
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1410185352
Short name T351
Test name
Test status
Simulation time 37377649 ps
CPU time 2.02 seconds
Started Jun 02 03:13:22 PM PDT 24
Finished Jun 02 03:13:24 PM PDT 24
Peak memory 218548 kb
Host smart-51461327-2325-411b-9f04-2c4a62ab021d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410185352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1410185352
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3592760435
Short name T518
Test name
Test status
Simulation time 384162828 ps
CPU time 11.06 seconds
Started Jun 02 03:13:21 PM PDT 24
Finished Jun 02 03:13:33 PM PDT 24
Peak memory 218512 kb
Host smart-6cc9801d-72f1-4e83-88f9-e240d37b9555
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592760435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3592760435
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2536183262
Short name T168
Test name
Test status
Simulation time 822808596 ps
CPU time 13.66 seconds
Started Jun 02 03:13:29 PM PDT 24
Finished Jun 02 03:13:43 PM PDT 24
Peak memory 226484 kb
Host smart-6bf4a9c9-89f4-49f5-ab37-e90f76485daa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536183262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2536183262
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.94737483
Short name T329
Test name
Test status
Simulation time 2838515061 ps
CPU time 13.9 seconds
Started Jun 02 03:13:28 PM PDT 24
Finished Jun 02 03:13:42 PM PDT 24
Peak memory 225476 kb
Host smart-8669d9f6-1675-4a79-8d09-7e0545f429c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94737483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.94737483
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.482535702
Short name T692
Test name
Test status
Simulation time 502740347 ps
CPU time 10.35 seconds
Started Jun 02 03:13:28 PM PDT 24
Finished Jun 02 03:13:39 PM PDT 24
Peak memory 218288 kb
Host smart-134f4cb6-1cbe-4fec-b74e-ff262d2f96be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482535702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.482535702
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.1698342232
Short name T789
Test name
Test status
Simulation time 340924196 ps
CPU time 2.09 seconds
Started Jun 02 03:13:24 PM PDT 24
Finished Jun 02 03:13:26 PM PDT 24
Peak memory 218104 kb
Host smart-b71328ad-0ca5-47a4-b282-e587548ca6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698342232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.1698342232
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1839189074
Short name T560
Test name
Test status
Simulation time 293179700 ps
CPU time 23.21 seconds
Started Jun 02 03:13:22 PM PDT 24
Finished Jun 02 03:13:45 PM PDT 24
Peak memory 251532 kb
Host smart-0ce0675b-bb9e-482b-a00a-0bf2aed7f2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839189074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1839189074
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.2618789313
Short name T623
Test name
Test status
Simulation time 662236063 ps
CPU time 7.28 seconds
Started Jun 02 03:13:22 PM PDT 24
Finished Jun 02 03:13:30 PM PDT 24
Peak memory 251400 kb
Host smart-8d1c3932-0fb4-4698-817e-e9423253e955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618789313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.2618789313
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.1985794698
Short name T756
Test name
Test status
Simulation time 4110536137 ps
CPU time 42.49 seconds
Started Jun 02 03:13:27 PM PDT 24
Finished Jun 02 03:14:11 PM PDT 24
Peak memory 251148 kb
Host smart-882c6616-bf24-45db-a42b-8e3c20a87a87
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985794698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.1985794698
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.349437814
Short name T78
Test name
Test status
Simulation time 74428792467 ps
CPU time 366.05 seconds
Started Jun 02 03:13:21 PM PDT 24
Finished Jun 02 03:19:28 PM PDT 24
Peak memory 284272 kb
Host smart-dcf1f81e-9032-4957-9df4-62152005f076
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=349437814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.349437814
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1065162195
Short name T592
Test name
Test status
Simulation time 42557455 ps
CPU time 0.9 seconds
Started Jun 02 03:13:23 PM PDT 24
Finished Jun 02 03:13:24 PM PDT 24
Peak memory 212160 kb
Host smart-f50a45f7-2115-4e6b-8f9f-399a123c5e7e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065162195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1065162195
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.997496008
Short name T677
Test name
Test status
Simulation time 47688265 ps
CPU time 1.06 seconds
Started Jun 02 03:13:27 PM PDT 24
Finished Jun 02 03:13:28 PM PDT 24
Peak memory 209164 kb
Host smart-c77c56f8-71e6-49a0-a22a-f447dfd33551
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997496008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.997496008
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.346583224
Short name T372
Test name
Test status
Simulation time 828935404 ps
CPU time 8.44 seconds
Started Jun 02 03:13:29 PM PDT 24
Finished Jun 02 03:13:38 PM PDT 24
Peak memory 218480 kb
Host smart-a40a34b0-4f67-4875-bd6a-f65d14257cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346583224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.346583224
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.582677317
Short name T601
Test name
Test status
Simulation time 1255954710 ps
CPU time 11.39 seconds
Started Jun 02 03:13:26 PM PDT 24
Finished Jun 02 03:13:37 PM PDT 24
Peak memory 217528 kb
Host smart-7786487b-b1ab-44a9-8962-aad25ece0d15
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582677317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.582677317
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3419424914
Short name T837
Test name
Test status
Simulation time 27380705734 ps
CPU time 113.98 seconds
Started Jun 02 03:13:28 PM PDT 24
Finished Jun 02 03:15:23 PM PDT 24
Peak memory 220352 kb
Host smart-dd593635-6942-4fcb-ad67-92e564c6f588
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419424914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3419424914
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.4229908165
Short name T736
Test name
Test status
Simulation time 2561634611 ps
CPU time 5.3 seconds
Started Jun 02 03:13:24 PM PDT 24
Finished Jun 02 03:13:30 PM PDT 24
Peak memory 218432 kb
Host smart-9cec54bc-b626-450c-b15a-efabb9771d41
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229908165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.4229908165
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.36999517
Short name T247
Test name
Test status
Simulation time 610115432 ps
CPU time 4.9 seconds
Started Jun 02 03:13:27 PM PDT 24
Finished Jun 02 03:13:33 PM PDT 24
Peak memory 218072 kb
Host smart-a27ad81b-37e6-445a-8f4d-6b6e53107672
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36999517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.36999517
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3847012568
Short name T490
Test name
Test status
Simulation time 2545738191 ps
CPU time 56.92 seconds
Started Jun 02 03:13:27 PM PDT 24
Finished Jun 02 03:14:24 PM PDT 24
Peak memory 278372 kb
Host smart-c36e311a-a340-4d0a-a37b-503ffb61b5d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847012568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3847012568
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1406813298
Short name T641
Test name
Test status
Simulation time 990466598 ps
CPU time 14.68 seconds
Started Jun 02 03:13:27 PM PDT 24
Finished Jun 02 03:13:43 PM PDT 24
Peak memory 251196 kb
Host smart-4d45d020-87e8-4f39-9cc8-dedee4354c08
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406813298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1406813298
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3186092735
Short name T359
Test name
Test status
Simulation time 294610862 ps
CPU time 3.32 seconds
Started Jun 02 03:13:26 PM PDT 24
Finished Jun 02 03:13:30 PM PDT 24
Peak memory 218364 kb
Host smart-63b87513-c7a1-48f4-a26a-63285023c169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186092735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3186092735
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.2435109467
Short name T308
Test name
Test status
Simulation time 1400820160 ps
CPU time 14.87 seconds
Started Jun 02 03:13:29 PM PDT 24
Finished Jun 02 03:13:44 PM PDT 24
Peak memory 219348 kb
Host smart-8d550171-6099-40a8-8b25-0ebdbd9e998e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435109467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2435109467
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.3403936920
Short name T267
Test name
Test status
Simulation time 750013250 ps
CPU time 16.69 seconds
Started Jun 02 03:13:25 PM PDT 24
Finished Jun 02 03:13:42 PM PDT 24
Peak memory 226496 kb
Host smart-7236d8a6-1e42-437e-aef3-42dcb48e9b33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403936920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.3403936920
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.2628746526
Short name T553
Test name
Test status
Simulation time 600045423 ps
CPU time 11.98 seconds
Started Jun 02 03:13:27 PM PDT 24
Finished Jun 02 03:13:40 PM PDT 24
Peak memory 226480 kb
Host smart-27f21cca-1163-4c3d-9462-cd02ec8c3b64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628746526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
2628746526
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.2488162598
Short name T474
Test name
Test status
Simulation time 2023420236 ps
CPU time 9.99 seconds
Started Jun 02 03:13:30 PM PDT 24
Finished Jun 02 03:13:40 PM PDT 24
Peak memory 224784 kb
Host smart-977a9f04-4aa8-4329-8f1e-a3cee9748e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488162598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.2488162598
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.928214188
Short name T626
Test name
Test status
Simulation time 68555845 ps
CPU time 2.67 seconds
Started Jun 02 03:13:20 PM PDT 24
Finished Jun 02 03:13:23 PM PDT 24
Peak memory 218096 kb
Host smart-8822edc6-f41c-4f56-aca5-813372b88be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928214188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.928214188
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1113595609
Short name T322
Test name
Test status
Simulation time 278844374 ps
CPU time 32.15 seconds
Started Jun 02 03:13:21 PM PDT 24
Finished Jun 02 03:13:53 PM PDT 24
Peak memory 251284 kb
Host smart-94f2be62-84ad-4ce4-8368-3d579239a328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113595609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1113595609
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.392361442
Short name T638
Test name
Test status
Simulation time 322186435 ps
CPU time 7.62 seconds
Started Jun 02 03:13:29 PM PDT 24
Finished Jun 02 03:13:37 PM PDT 24
Peak memory 251332 kb
Host smart-dd5b6ec0-c0a4-4cae-a2a0-782b0a45e12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392361442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.392361442
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3864758237
Short name T787
Test name
Test status
Simulation time 21835845036 ps
CPU time 117.62 seconds
Started Jun 02 03:13:26 PM PDT 24
Finished Jun 02 03:15:25 PM PDT 24
Peak memory 270252 kb
Host smart-0ee08f6e-6b51-48ea-a9da-3686b9274832
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864758237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3864758237
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.878641095
Short name T154
Test name
Test status
Simulation time 44225848043 ps
CPU time 304.11 seconds
Started Jun 02 03:13:27 PM PDT 24
Finished Jun 02 03:18:32 PM PDT 24
Peak memory 267908 kb
Host smart-55d05d05-feec-4ffb-8e03-9291f37a3d2b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=878641095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.878641095
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.3375638996
Short name T373
Test name
Test status
Simulation time 23324557 ps
CPU time 1.01 seconds
Started Jun 02 03:13:33 PM PDT 24
Finished Jun 02 03:13:35 PM PDT 24
Peak memory 209144 kb
Host smart-9f4a5b38-9172-4446-be3d-82f8533b7712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375638996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.3375638996
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2857177542
Short name T814
Test name
Test status
Simulation time 2704982693 ps
CPU time 11.77 seconds
Started Jun 02 03:13:28 PM PDT 24
Finished Jun 02 03:13:41 PM PDT 24
Peak memory 218428 kb
Host smart-62ca3299-6833-4db8-90e3-adc20a62f025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857177542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2857177542
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.4014467844
Short name T30
Test name
Test status
Simulation time 1869118662 ps
CPU time 11.55 seconds
Started Jun 02 03:13:33 PM PDT 24
Finished Jun 02 03:13:45 PM PDT 24
Peak memory 209920 kb
Host smart-796d96fc-781c-4c5f-b354-813638f444f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014467844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.4014467844
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2355640743
Short name T657
Test name
Test status
Simulation time 57591660411 ps
CPU time 122.31 seconds
Started Jun 02 03:13:43 PM PDT 24
Finished Jun 02 03:15:46 PM PDT 24
Peak memory 220108 kb
Host smart-ffd74b2f-b60d-4fff-be0d-8a238ab673c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355640743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2355640743
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2032438445
Short name T459
Test name
Test status
Simulation time 373043971 ps
CPU time 5.92 seconds
Started Jun 02 03:13:33 PM PDT 24
Finished Jun 02 03:13:39 PM PDT 24
Peak memory 218304 kb
Host smart-a5a46828-1cc6-4e30-bbc1-e2d281e4b7fe
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032438445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2032438445
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.380933201
Short name T397
Test name
Test status
Simulation time 160690098 ps
CPU time 5.28 seconds
Started Jun 02 03:13:31 PM PDT 24
Finished Jun 02 03:13:37 PM PDT 24
Peak memory 218064 kb
Host smart-27d16f29-e680-4f1f-8cc6-c3770c834181
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380933201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke.
380933201
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3955218286
Short name T414
Test name
Test status
Simulation time 5315198133 ps
CPU time 39.74 seconds
Started Jun 02 03:13:33 PM PDT 24
Finished Jun 02 03:14:13 PM PDT 24
Peak memory 275888 kb
Host smart-06f47bca-f913-43ff-803d-4797612a7574
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955218286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3955218286
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.3093611027
Short name T585
Test name
Test status
Simulation time 1500330426 ps
CPU time 25.63 seconds
Started Jun 02 03:13:31 PM PDT 24
Finished Jun 02 03:13:57 PM PDT 24
Peak memory 250772 kb
Host smart-e8729105-548b-4b98-bef3-6181f4f16d77
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093611027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.3093611027
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3929256630
Short name T674
Test name
Test status
Simulation time 185451243 ps
CPU time 4.63 seconds
Started Jun 02 03:13:27 PM PDT 24
Finished Jun 02 03:13:33 PM PDT 24
Peak memory 218348 kb
Host smart-1830b917-932e-44c8-8180-0b844d9a4496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929256630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3929256630
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.2424191724
Short name T261
Test name
Test status
Simulation time 840330130 ps
CPU time 13.73 seconds
Started Jun 02 03:13:34 PM PDT 24
Finished Jun 02 03:13:48 PM PDT 24
Peak memory 226468 kb
Host smart-4074da11-4807-4c43-a297-e494cd90dbf3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424191724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.2424191724
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1170397371
Short name T449
Test name
Test status
Simulation time 3582756073 ps
CPU time 10.74 seconds
Started Jun 02 03:13:33 PM PDT 24
Finished Jun 02 03:13:44 PM PDT 24
Peak memory 226564 kb
Host smart-359ef676-bce9-4505-a8cb-9bc4085d2b99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170397371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1170397371
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.914202922
Short name T767
Test name
Test status
Simulation time 207331803 ps
CPU time 5.82 seconds
Started Jun 02 03:13:36 PM PDT 24
Finished Jun 02 03:13:42 PM PDT 24
Peak memory 226452 kb
Host smart-4be3e9f4-73c9-4920-ac02-528003844e56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914202922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.914202922
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.1575998195
Short name T535
Test name
Test status
Simulation time 1388975428 ps
CPU time 9.45 seconds
Started Jun 02 03:13:33 PM PDT 24
Finished Jun 02 03:13:43 PM PDT 24
Peak memory 225404 kb
Host smart-fe5d060c-3205-4242-a4b5-9e184c07ff4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575998195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.1575998195
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1832653847
Short name T620
Test name
Test status
Simulation time 186692244 ps
CPU time 3.17 seconds
Started Jun 02 03:13:28 PM PDT 24
Finished Jun 02 03:13:32 PM PDT 24
Peak memory 215012 kb
Host smart-41fb9384-7004-47dd-aaec-8822fbb245b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832653847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1832653847
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1476942347
Short name T609
Test name
Test status
Simulation time 483371127 ps
CPU time 31.76 seconds
Started Jun 02 03:13:26 PM PDT 24
Finished Jun 02 03:13:58 PM PDT 24
Peak memory 251332 kb
Host smart-7442a970-f975-4e1b-b571-ce3280efdedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476942347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1476942347
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.58172667
Short name T342
Test name
Test status
Simulation time 132611071 ps
CPU time 7.6 seconds
Started Jun 02 03:13:34 PM PDT 24
Finished Jun 02 03:13:42 PM PDT 24
Peak memory 250864 kb
Host smart-ae36ff9b-5791-4ccc-be1c-d79e241682ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58172667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.58172667
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3802217610
Short name T360
Test name
Test status
Simulation time 41265832 ps
CPU time 0.84 seconds
Started Jun 02 03:13:27 PM PDT 24
Finished Jun 02 03:13:29 PM PDT 24
Peak memory 211964 kb
Host smart-c86438ad-dbb6-40ad-8034-adc4ebea43d9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802217610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.3802217610
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1295859167
Short name T332
Test name
Test status
Simulation time 83630248 ps
CPU time 1.14 seconds
Started Jun 02 03:13:37 PM PDT 24
Finished Jun 02 03:13:39 PM PDT 24
Peak memory 209980 kb
Host smart-98706b09-41bc-489e-9a5d-a02f850f7b07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295859167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1295859167
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1925788669
Short name T163
Test name
Test status
Simulation time 397869845 ps
CPU time 18.11 seconds
Started Jun 02 03:13:42 PM PDT 24
Finished Jun 02 03:14:01 PM PDT 24
Peak memory 218368 kb
Host smart-86f6f2a8-7907-47d4-8aad-e868faeea59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925788669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1925788669
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1949208817
Short name T32
Test name
Test status
Simulation time 1268496898 ps
CPU time 4.54 seconds
Started Jun 02 03:13:42 PM PDT 24
Finished Jun 02 03:13:48 PM PDT 24
Peak memory 209880 kb
Host smart-aeac1f23-3cce-432a-8a56-c975cc080bf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949208817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1949208817
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.313378242
Short name T171
Test name
Test status
Simulation time 9360471346 ps
CPU time 65.43 seconds
Started Jun 02 03:13:41 PM PDT 24
Finished Jun 02 03:14:47 PM PDT 24
Peak memory 218392 kb
Host smart-062faa18-26a9-40e7-badb-25c0bb4f2cb9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313378242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_er
rors.313378242
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.2204644098
Short name T555
Test name
Test status
Simulation time 953144059 ps
CPU time 7.45 seconds
Started Jun 02 03:13:37 PM PDT 24
Finished Jun 02 03:13:45 PM PDT 24
Peak memory 218400 kb
Host smart-66a12a26-ac1d-43b0-9246-d84df82d30e7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204644098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.2204644098
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.2436857978
Short name T74
Test name
Test status
Simulation time 1258359866 ps
CPU time 5.58 seconds
Started Jun 02 03:13:34 PM PDT 24
Finished Jun 02 03:13:40 PM PDT 24
Peak memory 218052 kb
Host smart-93c6b6db-a299-4e05-adb1-779694c1b40f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436857978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.2436857978
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.3437761211
Short name T600
Test name
Test status
Simulation time 2728192237 ps
CPU time 72.78 seconds
Started Jun 02 03:13:36 PM PDT 24
Finished Jun 02 03:14:49 PM PDT 24
Peak memory 267672 kb
Host smart-6aa6d4dd-c5af-4f8e-b766-fe4614111eae
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437761211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.3437761211
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.516886420
Short name T704
Test name
Test status
Simulation time 569919702 ps
CPU time 14.91 seconds
Started Jun 02 03:13:39 PM PDT 24
Finished Jun 02 03:13:54 PM PDT 24
Peak memory 250824 kb
Host smart-19b1ec05-772e-42d7-9bf1-124ce68019d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516886420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.516886420
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.4188479745
Short name T584
Test name
Test status
Simulation time 64121566 ps
CPU time 2.45 seconds
Started Jun 02 03:13:33 PM PDT 24
Finished Jun 02 03:13:36 PM PDT 24
Peak memory 218428 kb
Host smart-d0c85bf1-025e-42b1-821b-6dfe9de9122b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188479745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.4188479745
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.1236411855
Short name T594
Test name
Test status
Simulation time 944106724 ps
CPU time 16.43 seconds
Started Jun 02 03:13:40 PM PDT 24
Finished Jun 02 03:13:56 PM PDT 24
Peak memory 226464 kb
Host smart-4c4deecd-e7cc-4f39-9872-4ce221e942f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236411855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.1236411855
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2151432878
Short name T339
Test name
Test status
Simulation time 1975707057 ps
CPU time 6.87 seconds
Started Jun 02 03:13:38 PM PDT 24
Finished Jun 02 03:13:45 PM PDT 24
Peak memory 225508 kb
Host smart-95ebd52b-6a26-44f3-9098-ef6bc514b247
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151432878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2151432878
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.905092468
Short name T630
Test name
Test status
Simulation time 249630442 ps
CPU time 10.31 seconds
Started Jun 02 03:13:33 PM PDT 24
Finished Jun 02 03:13:44 PM PDT 24
Peak memory 218508 kb
Host smart-8eced095-9bd3-4f0f-9b74-c13b19618b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905092468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.905092468
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.4085728148
Short name T499
Test name
Test status
Simulation time 348019618 ps
CPU time 3.07 seconds
Started Jun 02 03:13:32 PM PDT 24
Finished Jun 02 03:13:35 PM PDT 24
Peak memory 214804 kb
Host smart-5e7c4ee4-af36-4196-9cf1-c695fbe825ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4085728148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.4085728148
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.3919285017
Short name T287
Test name
Test status
Simulation time 254927255 ps
CPU time 24.64 seconds
Started Jun 02 03:13:31 PM PDT 24
Finished Jun 02 03:13:57 PM PDT 24
Peak memory 251332 kb
Host smart-c8af5894-de05-48e1-877b-6adc2f30297b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919285017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.3919285017
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.589651453
Short name T874
Test name
Test status
Simulation time 429562901 ps
CPU time 6.69 seconds
Started Jun 02 03:13:35 PM PDT 24
Finished Jun 02 03:13:42 PM PDT 24
Peak memory 247180 kb
Host smart-0262729d-1412-4f5c-9c4d-55f2396f09ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589651453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.589651453
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.1937498901
Short name T672
Test name
Test status
Simulation time 24691680099 ps
CPU time 108.58 seconds
Started Jun 02 03:13:43 PM PDT 24
Finished Jun 02 03:15:32 PM PDT 24
Peak memory 252596 kb
Host smart-69e84995-4d60-4135-8ece-70a5a6705c33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937498901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.1937498901
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.1266621621
Short name T438
Test name
Test status
Simulation time 43562183586 ps
CPU time 686.81 seconds
Started Jun 02 03:13:37 PM PDT 24
Finished Jun 02 03:25:05 PM PDT 24
Peak memory 278844 kb
Host smart-d080d63f-9852-4538-a71a-dd2370ddda2c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1266621621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_stress_all_with_rand_reset.1266621621
Directory /workspace/19.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.3233333861
Short name T619
Test name
Test status
Simulation time 11121754 ps
CPU time 0.85 seconds
Started Jun 02 03:13:32 PM PDT 24
Finished Jun 02 03:13:33 PM PDT 24
Peak memory 212152 kb
Host smart-69d35a0d-5581-4ba3-9e40-b50bc9891cb7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233333861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.3233333861
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1752390626
Short name T843
Test name
Test status
Simulation time 21642028 ps
CPU time 0.94 seconds
Started Jun 02 03:12:18 PM PDT 24
Finished Jun 02 03:12:20 PM PDT 24
Peak memory 209136 kb
Host smart-f0721779-9302-4bba-aa3d-ddc2bd81f299
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752390626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1752390626
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.728229652
Short name T235
Test name
Test status
Simulation time 332849110 ps
CPU time 14.29 seconds
Started Jun 02 03:12:13 PM PDT 24
Finished Jun 02 03:12:27 PM PDT 24
Peak memory 218420 kb
Host smart-9f841387-82f8-45a8-9ba7-083567ab6149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728229652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.728229652
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.860237667
Short name T773
Test name
Test status
Simulation time 141329888 ps
CPU time 1.33 seconds
Started Jun 02 03:12:21 PM PDT 24
Finished Jun 02 03:12:23 PM PDT 24
Peak memory 217212 kb
Host smart-f74b42c1-6a0b-4336-b832-c7b330da268a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860237667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.860237667
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.4101721759
Short name T525
Test name
Test status
Simulation time 1824639039 ps
CPU time 16.32 seconds
Started Jun 02 03:12:19 PM PDT 24
Finished Jun 02 03:12:37 PM PDT 24
Peak memory 218268 kb
Host smart-df1f7da0-a9a7-4dd9-805f-7ea3acc43879
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101721759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.4
101721759
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.2171153760
Short name T539
Test name
Test status
Simulation time 355964056 ps
CPU time 4.14 seconds
Started Jun 02 03:12:14 PM PDT 24
Finished Jun 02 03:12:19 PM PDT 24
Peak memory 223060 kb
Host smart-b0eebda0-daa5-41f4-9266-5ab5c58d8d44
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171153760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.2171153760
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.586419008
Short name T239
Test name
Test status
Simulation time 3294861418 ps
CPU time 24.66 seconds
Started Jun 02 03:12:21 PM PDT 24
Finished Jun 02 03:12:47 PM PDT 24
Peak memory 218096 kb
Host smart-137f93d5-03ed-4063-8dd5-07d9e8e976e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586419008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.586419008
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.4039688361
Short name T838
Test name
Test status
Simulation time 131661948 ps
CPU time 4.74 seconds
Started Jun 02 03:12:13 PM PDT 24
Finished Jun 02 03:12:18 PM PDT 24
Peak memory 217992 kb
Host smart-b0873ab8-5e3f-4840-b06d-ae1f451c2a69
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039688361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
4039688361
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.77287398
Short name T834
Test name
Test status
Simulation time 6324130393 ps
CPU time 49.48 seconds
Started Jun 02 03:12:14 PM PDT 24
Finished Jun 02 03:13:04 PM PDT 24
Peak memory 267784 kb
Host smart-13a3cb62-669a-4147-92da-a53d508c4e55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77287398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
state_failure.77287398
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1331661570
Short name T305
Test name
Test status
Simulation time 2742115210 ps
CPU time 10.69 seconds
Started Jun 02 03:12:13 PM PDT 24
Finished Jun 02 03:12:24 PM PDT 24
Peak memory 246444 kb
Host smart-7702318f-f1d9-42f8-b6f7-8b39cfa42c0d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331661570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1331661570
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.899234430
Short name T658
Test name
Test status
Simulation time 22133826 ps
CPU time 1.85 seconds
Started Jun 02 03:12:15 PM PDT 24
Finished Jun 02 03:12:17 PM PDT 24
Peak memory 218392 kb
Host smart-b84cb233-b799-4705-8525-68fdf280f157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899234430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.899234430
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.2173417888
Short name T768
Test name
Test status
Simulation time 177692393 ps
CPU time 4.44 seconds
Started Jun 02 03:12:19 PM PDT 24
Finished Jun 02 03:12:25 PM PDT 24
Peak memory 218112 kb
Host smart-b953335a-1dfd-4a95-b722-4a1fe5fe923b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173417888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.2173417888
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.690940165
Short name T505
Test name
Test status
Simulation time 286892864 ps
CPU time 14.16 seconds
Started Jun 02 03:12:16 PM PDT 24
Finished Jun 02 03:12:31 PM PDT 24
Peak memory 219368 kb
Host smart-1f912853-261a-4bdf-bf42-d98c233edeed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690940165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.690940165
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.1981576661
Short name T358
Test name
Test status
Simulation time 1977994201 ps
CPU time 8.99 seconds
Started Jun 02 03:12:18 PM PDT 24
Finished Jun 02 03:12:28 PM PDT 24
Peak memory 225064 kb
Host smart-a5750417-9696-4d90-93d7-ea6637b07be6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981576661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.1981576661
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.2686053563
Short name T418
Test name
Test status
Simulation time 361732179 ps
CPU time 13.79 seconds
Started Jun 02 03:12:21 PM PDT 24
Finished Jun 02 03:12:36 PM PDT 24
Peak memory 225180 kb
Host smart-08d9201c-0387-4fea-a40c-6bebb294d160
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686053563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.2
686053563
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.1163981083
Short name T828
Test name
Test status
Simulation time 543748573 ps
CPU time 10.26 seconds
Started Jun 02 03:12:20 PM PDT 24
Finished Jun 02 03:12:31 PM PDT 24
Peak memory 218540 kb
Host smart-0a6ab432-03d2-4e02-9c49-d050f07f6165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163981083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.1163981083
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1076013398
Short name T605
Test name
Test status
Simulation time 366026380 ps
CPU time 3.32 seconds
Started Jun 02 03:12:14 PM PDT 24
Finished Jun 02 03:12:17 PM PDT 24
Peak memory 218108 kb
Host smart-af7d610c-e997-4b0b-8535-5f5f2cd9c8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076013398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1076013398
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.2618069771
Short name T809
Test name
Test status
Simulation time 229788352 ps
CPU time 23.26 seconds
Started Jun 02 03:12:15 PM PDT 24
Finished Jun 02 03:12:39 PM PDT 24
Peak memory 251416 kb
Host smart-2ee95765-fd65-4722-a2ac-0fd16ab4217c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618069771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.2618069771
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.690236918
Short name T841
Test name
Test status
Simulation time 68719044 ps
CPU time 6.84 seconds
Started Jun 02 03:12:16 PM PDT 24
Finished Jun 02 03:12:23 PM PDT 24
Peak memory 247380 kb
Host smart-9537fe5c-c007-4647-9055-075a8758661b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690236918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.690236918
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.2391016682
Short name T187
Test name
Test status
Simulation time 16395982388 ps
CPU time 264.96 seconds
Started Jun 02 03:12:18 PM PDT 24
Finished Jun 02 03:16:44 PM PDT 24
Peak memory 284156 kb
Host smart-52b69c9a-2ea7-4733-9f65-6ac82202ef9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391016682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.2391016682
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2442356526
Short name T697
Test name
Test status
Simulation time 26104602625 ps
CPU time 399.89 seconds
Started Jun 02 03:12:21 PM PDT 24
Finished Jun 02 03:19:02 PM PDT 24
Peak memory 300624 kb
Host smart-43f22c30-0ac0-42b7-bd4c-133d186c7019
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2442356526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.2442356526
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.1332250550
Short name T802
Test name
Test status
Simulation time 16121928 ps
CPU time 0.95 seconds
Started Jun 02 03:12:17 PM PDT 24
Finished Jun 02 03:12:19 PM PDT 24
Peak memory 212992 kb
Host smart-9f966afd-bf05-4c89-b416-ad5302e95e5c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332250550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.1332250550
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3669820765
Short name T648
Test name
Test status
Simulation time 36178391 ps
CPU time 1.41 seconds
Started Jun 02 03:13:42 PM PDT 24
Finished Jun 02 03:13:44 PM PDT 24
Peak memory 209184 kb
Host smart-bf2b928d-b1f1-45c4-88c6-35bc5240cd8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669820765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3669820765
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.301040368
Short name T533
Test name
Test status
Simulation time 2174820043 ps
CPU time 10.29 seconds
Started Jun 02 03:13:37 PM PDT 24
Finished Jun 02 03:13:48 PM PDT 24
Peak memory 218480 kb
Host smart-c712f94a-ee7e-47ce-b6ef-ae8b18377279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301040368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.301040368
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3398718497
Short name T744
Test name
Test status
Simulation time 817183180 ps
CPU time 5.55 seconds
Started Jun 02 03:13:38 PM PDT 24
Finished Jun 02 03:13:44 PM PDT 24
Peak memory 209984 kb
Host smart-81cdb6f8-4110-4cba-af13-e84de3861f89
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398718497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3398718497
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.1393205203
Short name T325
Test name
Test status
Simulation time 59334226 ps
CPU time 2.76 seconds
Started Jun 02 03:13:38 PM PDT 24
Finished Jun 02 03:13:42 PM PDT 24
Peak memory 218404 kb
Host smart-0ff0b0dd-f8bb-4ec0-addb-2ec29d1b485b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393205203 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.1393205203
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.862509906
Short name T284
Test name
Test status
Simulation time 829723619 ps
CPU time 10.68 seconds
Started Jun 02 03:13:36 PM PDT 24
Finished Jun 02 03:13:47 PM PDT 24
Peak memory 226492 kb
Host smart-68ecf33b-afe7-47b2-8e08-ebae858365e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862509906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.862509906
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.3033095521
Short name T591
Test name
Test status
Simulation time 2000514259 ps
CPU time 14.6 seconds
Started Jun 02 03:13:41 PM PDT 24
Finished Jun 02 03:13:56 PM PDT 24
Peak memory 226448 kb
Host smart-5cbbba59-4194-4cac-969b-a5178d7c1377
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033095521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.3033095521
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.408573597
Short name T778
Test name
Test status
Simulation time 330065506 ps
CPU time 11.17 seconds
Started Jun 02 03:13:38 PM PDT 24
Finished Jun 02 03:13:49 PM PDT 24
Peak memory 225612 kb
Host smart-0368e913-082d-4dc5-aede-57d7e38d4143
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408573597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.408573597
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.635018070
Short name T439
Test name
Test status
Simulation time 336626728 ps
CPU time 9.27 seconds
Started Jun 02 03:13:41 PM PDT 24
Finished Jun 02 03:13:51 PM PDT 24
Peak memory 225212 kb
Host smart-85c79727-b759-4c33-8556-71416bd69f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635018070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.635018070
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.463209493
Short name T179
Test name
Test status
Simulation time 22065242 ps
CPU time 1.89 seconds
Started Jun 02 03:13:37 PM PDT 24
Finished Jun 02 03:13:40 PM PDT 24
Peak memory 213904 kb
Host smart-9fd8a830-93c7-422f-8138-b75f2eb0cb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463209493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.463209493
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2819782631
Short name T819
Test name
Test status
Simulation time 1184273035 ps
CPU time 19.92 seconds
Started Jun 02 03:13:37 PM PDT 24
Finished Jun 02 03:13:57 PM PDT 24
Peak memory 251304 kb
Host smart-2aeaa865-05b2-401e-9ff1-989eb83a931b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819782631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2819782631
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2883179288
Short name T579
Test name
Test status
Simulation time 113564392 ps
CPU time 3.39 seconds
Started Jun 02 03:13:36 PM PDT 24
Finished Jun 02 03:13:40 PM PDT 24
Peak memory 222704 kb
Host smart-1b778145-ca47-4916-8e4d-8222baab7aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883179288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2883179288
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.2368455577
Short name T858
Test name
Test status
Simulation time 4216371577 ps
CPU time 138.86 seconds
Started Jun 02 03:13:38 PM PDT 24
Finished Jun 02 03:15:57 PM PDT 24
Peak memory 251320 kb
Host smart-f6d1dd74-fce8-4705-a073-a53aa14e9442
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2368455577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.2368455577
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2569108843
Short name T611
Test name
Test status
Simulation time 63313941 ps
CPU time 0.81 seconds
Started Jun 02 03:13:38 PM PDT 24
Finished Jun 02 03:13:39 PM PDT 24
Peak memory 212016 kb
Host smart-52080d0b-4100-4dfa-b781-04e87f55d472
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569108843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.2569108843
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.3637348290
Short name T365
Test name
Test status
Simulation time 20554687 ps
CPU time 0.92 seconds
Started Jun 02 03:13:42 PM PDT 24
Finished Jun 02 03:13:44 PM PDT 24
Peak memory 209172 kb
Host smart-5a03cc60-547f-4302-9e99-b21b171c6cc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637348290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.3637348290
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.966856469
Short name T536
Test name
Test status
Simulation time 224642800 ps
CPU time 9.63 seconds
Started Jun 02 03:13:47 PM PDT 24
Finished Jun 02 03:13:57 PM PDT 24
Peak memory 218452 kb
Host smart-ef37d5f9-625b-4245-a15a-df0d1d86d9b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966856469 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.966856469
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1336400714
Short name T34
Test name
Test status
Simulation time 708986912 ps
CPU time 6.93 seconds
Started Jun 02 03:13:42 PM PDT 24
Finished Jun 02 03:13:50 PM PDT 24
Peak memory 217644 kb
Host smart-5342cc82-28e6-497a-84d7-c911590ed112
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336400714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1336400714
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2300264018
Short name T475
Test name
Test status
Simulation time 396562851 ps
CPU time 3.06 seconds
Started Jun 02 03:13:42 PM PDT 24
Finished Jun 02 03:13:45 PM PDT 24
Peak memory 218424 kb
Host smart-3e543bcf-79a9-420f-9292-aea8df43cc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300264018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2300264018
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2629656308
Short name T749
Test name
Test status
Simulation time 1155454787 ps
CPU time 12.13 seconds
Started Jun 02 03:13:46 PM PDT 24
Finished Jun 02 03:13:59 PM PDT 24
Peak memory 226484 kb
Host smart-f8ba9d14-42c8-4939-8a19-64280c5956c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629656308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2629656308
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1137741839
Short name T161
Test name
Test status
Simulation time 1147262545 ps
CPU time 13.97 seconds
Started Jun 02 03:13:47 PM PDT 24
Finished Jun 02 03:14:02 PM PDT 24
Peak memory 225180 kb
Host smart-d25359d9-e398-44e1-8827-ae783e208a45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137741839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1137741839
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.1575177128
Short name T315
Test name
Test status
Simulation time 334761646 ps
CPU time 12.35 seconds
Started Jun 02 03:13:41 PM PDT 24
Finished Jun 02 03:13:54 PM PDT 24
Peak memory 225300 kb
Host smart-f83f6f5b-b4bd-4ae2-a724-cb19c6e2c418
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575177128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
1575177128
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.2790319852
Short name T848
Test name
Test status
Simulation time 1568471672 ps
CPU time 10.31 seconds
Started Jun 02 03:13:46 PM PDT 24
Finished Jun 02 03:13:56 PM PDT 24
Peak memory 218468 kb
Host smart-7146ba34-fb33-4874-9083-b20c80e86e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790319852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.2790319852
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.4066450311
Short name T68
Test name
Test status
Simulation time 300289863 ps
CPU time 3.83 seconds
Started Jun 02 03:13:43 PM PDT 24
Finished Jun 02 03:13:47 PM PDT 24
Peak memory 218096 kb
Host smart-00516cc7-8bc8-4e49-a90b-1a445531e39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066450311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.4066450311
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.725156899
Short name T785
Test name
Test status
Simulation time 3378674084 ps
CPU time 24.27 seconds
Started Jun 02 03:13:43 PM PDT 24
Finished Jun 02 03:14:08 PM PDT 24
Peak memory 251416 kb
Host smart-9e23caaa-f6a6-4dec-a62f-edfa66e19fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725156899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.725156899
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2779295153
Short name T4
Test name
Test status
Simulation time 79702355 ps
CPU time 7.56 seconds
Started Jun 02 03:13:42 PM PDT 24
Finished Jun 02 03:13:50 PM PDT 24
Peak memory 251324 kb
Host smart-428406ae-4a55-460f-bc68-b480e55d8bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779295153 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2779295153
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.622817219
Short name T271
Test name
Test status
Simulation time 1553541339 ps
CPU time 83.17 seconds
Started Jun 02 03:13:44 PM PDT 24
Finished Jun 02 03:15:08 PM PDT 24
Peak memory 277652 kb
Host smart-e8fbcd63-2b37-4f5a-9bb4-7c47a1106408
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622817219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.622817219
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.990855824
Short name T524
Test name
Test status
Simulation time 49279857977 ps
CPU time 262.43 seconds
Started Jun 02 03:13:47 PM PDT 24
Finished Jun 02 03:18:10 PM PDT 24
Peak memory 267768 kb
Host smart-7b61d581-496e-46ff-b550-23b596647123
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=990855824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.990855824
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.462548634
Short name T412
Test name
Test status
Simulation time 37450617 ps
CPU time 1.02 seconds
Started Jun 02 03:13:42 PM PDT 24
Finished Jun 02 03:13:44 PM PDT 24
Peak memory 213164 kb
Host smart-3b516be6-97f2-4813-99b7-bd6a3bc1cf60
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462548634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ct
rl_volatile_unlock_smoke.462548634
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.2039828485
Short name T670
Test name
Test status
Simulation time 1494518151 ps
CPU time 16.79 seconds
Started Jun 02 03:13:44 PM PDT 24
Finished Jun 02 03:14:02 PM PDT 24
Peak memory 218392 kb
Host smart-e3a3a9be-9bc0-432f-8ee8-8025fb82c95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039828485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.2039828485
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.1167688826
Short name T7
Test name
Test status
Simulation time 713554278 ps
CPU time 17.79 seconds
Started Jun 02 03:13:43 PM PDT 24
Finished Jun 02 03:14:01 PM PDT 24
Peak memory 217520 kb
Host smart-3354abbf-4ef1-48aa-a92d-70bf0c796a1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167688826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.1167688826
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.3170892999
Short name T344
Test name
Test status
Simulation time 239251462 ps
CPU time 2.56 seconds
Started Jun 02 03:13:43 PM PDT 24
Finished Jun 02 03:13:47 PM PDT 24
Peak memory 218424 kb
Host smart-27bc972d-0126-42bb-9d86-9650ec716146
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170892999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.3170892999
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1598995777
Short name T432
Test name
Test status
Simulation time 335014182 ps
CPU time 14.78 seconds
Started Jun 02 03:13:49 PM PDT 24
Finished Jun 02 03:14:04 PM PDT 24
Peak memory 219340 kb
Host smart-4d3e8296-2ded-4cbb-a08b-a12627bc157a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598995777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1598995777
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3076930775
Short name T52
Test name
Test status
Simulation time 250581355 ps
CPU time 8.18 seconds
Started Jun 02 03:13:47 PM PDT 24
Finished Jun 02 03:13:56 PM PDT 24
Peak memory 226492 kb
Host smart-232354a2-6691-493d-a661-dc32b7140912
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076930775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3076930775
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.844357156
Short name T328
Test name
Test status
Simulation time 514076737 ps
CPU time 13.47 seconds
Started Jun 02 03:13:48 PM PDT 24
Finished Jun 02 03:14:02 PM PDT 24
Peak memory 226480 kb
Host smart-13513857-43d9-461b-bb3d-fe1d45433d4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844357156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.844357156
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3200395208
Short name T556
Test name
Test status
Simulation time 342584366 ps
CPU time 8.4 seconds
Started Jun 02 03:13:42 PM PDT 24
Finished Jun 02 03:13:51 PM PDT 24
Peak memory 225156 kb
Host smart-9acda810-37d4-475e-8721-c77893235dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200395208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3200395208
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.2115382845
Short name T343
Test name
Test status
Simulation time 71702837 ps
CPU time 2.27 seconds
Started Jun 02 03:13:41 PM PDT 24
Finished Jun 02 03:13:44 PM PDT 24
Peak memory 218108 kb
Host smart-c76a06b7-eeb1-4c3f-80f4-84dfe8dbd502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115382845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.2115382845
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3053683348
Short name T725
Test name
Test status
Simulation time 1106607126 ps
CPU time 39.75 seconds
Started Jun 02 03:13:45 PM PDT 24
Finished Jun 02 03:14:25 PM PDT 24
Peak memory 251408 kb
Host smart-e4cf632e-5c43-4085-be80-28243202b4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053683348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3053683348
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.3219654295
Short name T3
Test name
Test status
Simulation time 221069528 ps
CPU time 7.27 seconds
Started Jun 02 03:13:43 PM PDT 24
Finished Jun 02 03:13:51 PM PDT 24
Peak memory 251328 kb
Host smart-ebf598ed-f0ed-49d3-8852-0fdf3738dfe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219654295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.3219654295
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.2536146500
Short name T77
Test name
Test status
Simulation time 5728904812 ps
CPU time 40.58 seconds
Started Jun 02 03:13:48 PM PDT 24
Finished Jun 02 03:14:29 PM PDT 24
Peak memory 251364 kb
Host smart-071f76bb-b1e8-4f7f-a772-1af0d0a86cce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536146500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.2536146500
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.2752438631
Short name T87
Test name
Test status
Simulation time 48583209922 ps
CPU time 303.44 seconds
Started Jun 02 03:13:46 PM PDT 24
Finished Jun 02 03:18:50 PM PDT 24
Peak memory 284196 kb
Host smart-8f2683ba-0903-4c5e-a9fa-ae3a3d3bbb6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2752438631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.2752438631
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1508147998
Short name T241
Test name
Test status
Simulation time 25850588 ps
CPU time 1.03 seconds
Started Jun 02 03:13:43 PM PDT 24
Finished Jun 02 03:13:44 PM PDT 24
Peak memory 211876 kb
Host smart-55f2d23a-b3f7-4abe-9fa9-f02753001d14
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508147998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.1508147998
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.1990266106
Short name T293
Test name
Test status
Simulation time 74005067 ps
CPU time 0.98 seconds
Started Jun 02 03:13:54 PM PDT 24
Finished Jun 02 03:13:56 PM PDT 24
Peak memory 209092 kb
Host smart-c3d04250-9aba-40f5-8475-1d5b42b6fe35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990266106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.1990266106
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2297657279
Short name T221
Test name
Test status
Simulation time 1332960133 ps
CPU time 11.85 seconds
Started Jun 02 03:13:48 PM PDT 24
Finished Jun 02 03:14:00 PM PDT 24
Peak memory 218412 kb
Host smart-2ced76bd-d904-4489-8fd0-a985fd8a08c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297657279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2297657279
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.1374718618
Short name T268
Test name
Test status
Simulation time 288424141 ps
CPU time 4.02 seconds
Started Jun 02 03:13:47 PM PDT 24
Finished Jun 02 03:13:52 PM PDT 24
Peak memory 209936 kb
Host smart-1ccb9fb9-ad1a-4ac2-ac7c-23ee57b39c07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374718618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.1374718618
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.330774408
Short name T231
Test name
Test status
Simulation time 122682396 ps
CPU time 3.77 seconds
Started Jun 02 03:13:48 PM PDT 24
Finished Jun 02 03:13:52 PM PDT 24
Peak memory 218480 kb
Host smart-44f4ad65-fefd-4eef-b974-6fe723b2a0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330774408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.330774408
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1449155628
Short name T309
Test name
Test status
Simulation time 875828420 ps
CPU time 10.6 seconds
Started Jun 02 03:13:46 PM PDT 24
Finished Jun 02 03:13:57 PM PDT 24
Peak memory 226512 kb
Host smart-0e881cca-a533-4210-b372-ad9502bb9bc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449155628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1449155628
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.210399408
Short name T497
Test name
Test status
Simulation time 665627758 ps
CPU time 16.45 seconds
Started Jun 02 03:13:47 PM PDT 24
Finished Jun 02 03:14:05 PM PDT 24
Peak memory 226500 kb
Host smart-681b76a9-6e23-44e7-84ce-e1b2d013592e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210399408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.210399408
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1857780627
Short name T682
Test name
Test status
Simulation time 255506737 ps
CPU time 7.62 seconds
Started Jun 02 03:13:47 PM PDT 24
Finished Jun 02 03:13:55 PM PDT 24
Peak memory 226504 kb
Host smart-743af053-a902-4d3f-884f-a8ffca133838
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857780627 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1857780627
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.385928730
Short name T2
Test name
Test status
Simulation time 452584669 ps
CPU time 6.89 seconds
Started Jun 02 03:13:47 PM PDT 24
Finished Jun 02 03:13:55 PM PDT 24
Peak memory 224356 kb
Host smart-2fbb00db-4086-4989-b83f-8f0d70096f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385928730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.385928730
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1048067246
Short name T633
Test name
Test status
Simulation time 193533083 ps
CPU time 8.53 seconds
Started Jun 02 03:13:47 PM PDT 24
Finished Jun 02 03:13:56 PM PDT 24
Peak memory 218072 kb
Host smart-e6973a05-bb20-472f-8f39-43aa82e970b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048067246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1048067246
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.2094339588
Short name T98
Test name
Test status
Simulation time 241887406 ps
CPU time 27.86 seconds
Started Jun 02 03:13:49 PM PDT 24
Finished Jun 02 03:14:17 PM PDT 24
Peak memory 251320 kb
Host smart-8f3ce491-7dc3-4ba5-8823-94c49ef5d647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094339588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.2094339588
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2950536322
Short name T281
Test name
Test status
Simulation time 68590171 ps
CPU time 6.54 seconds
Started Jun 02 03:13:47 PM PDT 24
Finished Jun 02 03:13:54 PM PDT 24
Peak memory 247428 kb
Host smart-987de840-0f05-4090-a943-23f730e39cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950536322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2950536322
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3775257271
Short name T274
Test name
Test status
Simulation time 2080537938 ps
CPU time 52.03 seconds
Started Jun 02 03:13:50 PM PDT 24
Finished Jun 02 03:14:42 PM PDT 24
Peak memory 226480 kb
Host smart-11ca997f-256e-445d-bc82-7d7c862b6723
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775257271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3775257271
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.1466902129
Short name T825
Test name
Test status
Simulation time 18026529 ps
CPU time 0.83 seconds
Started Jun 02 03:13:47 PM PDT 24
Finished Jun 02 03:13:48 PM PDT 24
Peak memory 211952 kb
Host smart-3170acab-0cc0-4a34-8a57-21d0ba0af365
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466902129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.1466902129
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.2427470892
Short name T240
Test name
Test status
Simulation time 32179319 ps
CPU time 1.02 seconds
Started Jun 02 03:13:53 PM PDT 24
Finished Jun 02 03:13:55 PM PDT 24
Peak memory 208984 kb
Host smart-a990df1e-42da-4b32-9c08-13cbbb458736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427470892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.2427470892
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2969742932
Short name T557
Test name
Test status
Simulation time 306274682 ps
CPU time 12.07 seconds
Started Jun 02 03:13:53 PM PDT 24
Finished Jun 02 03:14:06 PM PDT 24
Peak memory 218500 kb
Host smart-a04f9fbe-9dcd-4cd0-b2a7-68f2a5a7278f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969742932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2969742932
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2357041961
Short name T29
Test name
Test status
Simulation time 3363537085 ps
CPU time 3.41 seconds
Started Jun 02 03:13:52 PM PDT 24
Finished Jun 02 03:13:56 PM PDT 24
Peak memory 209992 kb
Host smart-acc7a72e-d74f-483b-bb42-b07db09fd6a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357041961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2357041961
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.149141230
Short name T295
Test name
Test status
Simulation time 78951856 ps
CPU time 3.5 seconds
Started Jun 02 03:13:53 PM PDT 24
Finished Jun 02 03:13:57 PM PDT 24
Peak memory 218400 kb
Host smart-e0c36f8a-ef9e-4dcb-971a-b67356a782d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149141230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.149141230
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.3576861471
Short name T59
Test name
Test status
Simulation time 418137598 ps
CPU time 18.83 seconds
Started Jun 02 03:13:54 PM PDT 24
Finished Jun 02 03:14:13 PM PDT 24
Peak memory 219352 kb
Host smart-b6f0d81e-3565-4bad-98e7-a7aa055f36c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576861471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3576861471
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1851363436
Short name T860
Test name
Test status
Simulation time 288157680 ps
CPU time 12.93 seconds
Started Jun 02 03:13:53 PM PDT 24
Finished Jun 02 03:14:07 PM PDT 24
Peak memory 226440 kb
Host smart-51a514fd-019d-4af9-a85e-63ab690e30d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851363436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1851363436
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.711592008
Short name T624
Test name
Test status
Simulation time 289082340 ps
CPU time 11.11 seconds
Started Jun 02 03:13:54 PM PDT 24
Finished Jun 02 03:14:05 PM PDT 24
Peak memory 225720 kb
Host smart-8b961581-a09d-48c1-a6ba-20810d517296
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711592008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.711592008
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.312533070
Short name T21
Test name
Test status
Simulation time 1282023394 ps
CPU time 8.92 seconds
Started Jun 02 03:13:53 PM PDT 24
Finished Jun 02 03:14:03 PM PDT 24
Peak memory 225460 kb
Host smart-b0726508-4518-4605-aaa9-7136d891486c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312533070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.312533070
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3041104033
Short name T666
Test name
Test status
Simulation time 19955983 ps
CPU time 1.25 seconds
Started Jun 02 03:13:52 PM PDT 24
Finished Jun 02 03:13:54 PM PDT 24
Peak memory 218112 kb
Host smart-680dd56b-f18a-4d25-8ca4-310eb0d237d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041104033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3041104033
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1285585794
Short name T89
Test name
Test status
Simulation time 452546249 ps
CPU time 22 seconds
Started Jun 02 03:13:54 PM PDT 24
Finished Jun 02 03:14:17 PM PDT 24
Peak memory 251320 kb
Host smart-0bd7e837-bca2-4c81-973d-2bb6473c6f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285585794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1285585794
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3009081312
Short name T147
Test name
Test status
Simulation time 41371734 ps
CPU time 6.44 seconds
Started Jun 02 03:13:53 PM PDT 24
Finished Jun 02 03:14:00 PM PDT 24
Peak memory 250748 kb
Host smart-c6e70dc5-bca2-46e8-99b5-bc7a965b9d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009081312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3009081312
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.3036103933
Short name T728
Test name
Test status
Simulation time 3477275887 ps
CPU time 110.44 seconds
Started Jun 02 03:13:57 PM PDT 24
Finished Jun 02 03:15:48 PM PDT 24
Peak memory 284112 kb
Host smart-f0095813-2376-487e-a2e2-87949649521b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036103933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.3036103933
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.420646809
Short name T850
Test name
Test status
Simulation time 39458720 ps
CPU time 0.84 seconds
Started Jun 02 03:13:52 PM PDT 24
Finished Jun 02 03:13:54 PM PDT 24
Peak memory 211916 kb
Host smart-678c0b04-96f0-4225-9d1d-37e502496d61
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420646809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ct
rl_volatile_unlock_smoke.420646809
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2646375871
Short name T832
Test name
Test status
Simulation time 149277178 ps
CPU time 1.46 seconds
Started Jun 02 03:13:58 PM PDT 24
Finished Jun 02 03:14:01 PM PDT 24
Peak memory 209964 kb
Host smart-7d93d1a2-acae-43af-b265-6791029360b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646375871 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2646375871
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.99076540
Short name T846
Test name
Test status
Simulation time 561573819 ps
CPU time 14.58 seconds
Started Jun 02 03:13:52 PM PDT 24
Finished Jun 02 03:14:08 PM PDT 24
Peak memory 218480 kb
Host smart-bb4668cd-6ee8-469f-97cb-4fc6315b4c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99076540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.99076540
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1390341740
Short name T192
Test name
Test status
Simulation time 5770965280 ps
CPU time 8.58 seconds
Started Jun 02 03:13:55 PM PDT 24
Finished Jun 02 03:14:04 PM PDT 24
Peak memory 210032 kb
Host smart-0132d0d1-e2ad-4dc0-b844-6c27328db488
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390341740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1390341740
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.3692140874
Short name T302
Test name
Test status
Simulation time 68133773 ps
CPU time 2.76 seconds
Started Jun 02 03:13:52 PM PDT 24
Finished Jun 02 03:13:56 PM PDT 24
Peak memory 218380 kb
Host smart-86f8f3c8-fbbb-4596-856b-6e8f85c6db79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692140874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.3692140874
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.3177372327
Short name T389
Test name
Test status
Simulation time 254323621 ps
CPU time 12.29 seconds
Started Jun 02 03:13:52 PM PDT 24
Finished Jun 02 03:14:05 PM PDT 24
Peak memory 219364 kb
Host smart-82f051da-cfb1-4a64-8f73-cf5e95ce9424
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177372327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.3177372327
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2549737265
Short name T223
Test name
Test status
Simulation time 420448124 ps
CPU time 14.93 seconds
Started Jun 02 03:13:56 PM PDT 24
Finished Jun 02 03:14:12 PM PDT 24
Peak memory 226488 kb
Host smart-fa598a5c-5da0-4644-9eb3-253caff40ac3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549737265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2549737265
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1272413785
Short name T282
Test name
Test status
Simulation time 517380877 ps
CPU time 8.46 seconds
Started Jun 02 03:14:05 PM PDT 24
Finished Jun 02 03:14:14 PM PDT 24
Peak memory 226472 kb
Host smart-71f5abc5-9a29-4a9a-8690-28bf0f48f24c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272413785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1272413785
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.2195823972
Short name T854
Test name
Test status
Simulation time 266840015 ps
CPU time 10.52 seconds
Started Jun 02 03:13:53 PM PDT 24
Finished Jun 02 03:14:04 PM PDT 24
Peak memory 225768 kb
Host smart-005e5375-724f-4088-92d2-a1c89ca26c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195823972 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.2195823972
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.74372038
Short name T732
Test name
Test status
Simulation time 84942594 ps
CPU time 2.97 seconds
Started Jun 02 03:13:57 PM PDT 24
Finished Jun 02 03:14:00 PM PDT 24
Peak memory 214724 kb
Host smart-bf9cdd42-5653-46a7-acb1-0851f7cb7826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74372038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.74372038
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.2310186201
Short name T398
Test name
Test status
Simulation time 513426123 ps
CPU time 38.22 seconds
Started Jun 02 03:13:55 PM PDT 24
Finished Jun 02 03:14:34 PM PDT 24
Peak memory 251324 kb
Host smart-33e2fcb0-326e-4d7d-80fa-2fa7c0056248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310186201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.2310186201
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.996008998
Short name T565
Test name
Test status
Simulation time 56099252 ps
CPU time 7.7 seconds
Started Jun 02 03:13:56 PM PDT 24
Finished Jun 02 03:14:04 PM PDT 24
Peak memory 251244 kb
Host smart-29cf0fba-3cc1-40cd-92d1-35381a0a01fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996008998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.996008998
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.4085321205
Short name T665
Test name
Test status
Simulation time 2528808208 ps
CPU time 78.74 seconds
Started Jun 02 03:13:58 PM PDT 24
Finished Jun 02 03:15:18 PM PDT 24
Peak memory 271964 kb
Host smart-0b3a478e-5145-412d-a7cf-66292cde536e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085321205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.4085321205
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.1840228670
Short name T144
Test name
Test status
Simulation time 23526378 ps
CPU time 0.84 seconds
Started Jun 02 03:13:53 PM PDT 24
Finished Jun 02 03:13:55 PM PDT 24
Peak memory 211956 kb
Host smart-721620fb-d80f-4267-ac69-18a20fcbcd67
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840228670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.1840228670
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.1024991008
Short name T689
Test name
Test status
Simulation time 161257314 ps
CPU time 1.02 seconds
Started Jun 02 03:13:59 PM PDT 24
Finished Jun 02 03:14:00 PM PDT 24
Peak memory 209080 kb
Host smart-389d2048-4687-4ad3-814a-cfc9483909b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024991008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.1024991008
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3264478142
Short name T233
Test name
Test status
Simulation time 283914836 ps
CPU time 14.59 seconds
Started Jun 02 03:13:59 PM PDT 24
Finished Jun 02 03:14:14 PM PDT 24
Peak memory 218412 kb
Host smart-42542b97-25e4-44d4-8261-2fda6f08176b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264478142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3264478142
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.1779886503
Short name T396
Test name
Test status
Simulation time 3714747758 ps
CPU time 7.88 seconds
Started Jun 02 03:14:02 PM PDT 24
Finished Jun 02 03:14:10 PM PDT 24
Peak memory 209952 kb
Host smart-51301ea8-9ad7-4365-bc78-3afe6115d91b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779886503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.1779886503
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.1229881638
Short name T277
Test name
Test status
Simulation time 77222571 ps
CPU time 3.65 seconds
Started Jun 02 03:13:59 PM PDT 24
Finished Jun 02 03:14:03 PM PDT 24
Peak memory 218320 kb
Host smart-e19a01f2-4f91-4940-ba66-52998e5b313b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229881638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.1229881638
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.2435272956
Short name T759
Test name
Test status
Simulation time 3857137670 ps
CPU time 12.13 seconds
Started Jun 02 03:13:57 PM PDT 24
Finished Jun 02 03:14:10 PM PDT 24
Peak memory 226548 kb
Host smart-4989225b-b2b0-4db6-b405-9ec8ad9a14d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435272956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.2435272956
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2919478335
Short name T234
Test name
Test status
Simulation time 804482737 ps
CPU time 18.73 seconds
Started Jun 02 03:13:58 PM PDT 24
Finished Jun 02 03:14:17 PM PDT 24
Peak memory 225364 kb
Host smart-91c3f59f-070e-45f2-aae6-c2bdf9dee370
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919478335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2919478335
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.3624125923
Short name T640
Test name
Test status
Simulation time 1056001352 ps
CPU time 11.21 seconds
Started Jun 02 03:13:57 PM PDT 24
Finished Jun 02 03:14:09 PM PDT 24
Peak memory 225640 kb
Host smart-9d07954d-3e8a-44eb-8c9f-d2e6dae6e24e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624125923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
3624125923
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.750667053
Short name T458
Test name
Test status
Simulation time 609058892 ps
CPU time 9.61 seconds
Started Jun 02 03:13:57 PM PDT 24
Finished Jun 02 03:14:07 PM PDT 24
Peak memory 225244 kb
Host smart-8b2cfe7a-92dd-4722-8e5a-13e329425396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750667053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.750667053
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.886702667
Short name T568
Test name
Test status
Simulation time 146214920 ps
CPU time 3 seconds
Started Jun 02 03:13:58 PM PDT 24
Finished Jun 02 03:14:01 PM PDT 24
Peak memory 218056 kb
Host smart-0c65d5be-97be-4780-b20c-3578c7d9bf32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886702667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.886702667
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1257927998
Short name T81
Test name
Test status
Simulation time 1050238920 ps
CPU time 23.52 seconds
Started Jun 02 03:14:00 PM PDT 24
Finished Jun 02 03:14:24 PM PDT 24
Peak memory 251308 kb
Host smart-6869c312-5efb-40bf-ac2f-3439414b4cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257927998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1257927998
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.2446057844
Short name T374
Test name
Test status
Simulation time 556933394 ps
CPU time 8.61 seconds
Started Jun 02 03:13:59 PM PDT 24
Finished Jun 02 03:14:08 PM PDT 24
Peak memory 251324 kb
Host smart-50dc0aeb-1837-4e7f-a000-2df1b2ba9483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446057844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.2446057844
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.3387347163
Short name T451
Test name
Test status
Simulation time 6179856355 ps
CPU time 44.42 seconds
Started Jun 02 03:13:59 PM PDT 24
Finished Jun 02 03:14:44 PM PDT 24
Peak memory 236080 kb
Host smart-9962f66c-85b2-45d8-b96f-44b90842aaf8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387347163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.3387347163
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all_with_rand_reset.604644392
Short name T107
Test name
Test status
Simulation time 34453731905 ps
CPU time 753.72 seconds
Started Jun 02 03:13:59 PM PDT 24
Finished Jun 02 03:26:33 PM PDT 24
Peak memory 497216 kb
Host smart-23ac34ee-b4e0-4c8e-9dee-eb22ecad6561
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=604644392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_stress_all_with_rand_reset.604644392
Directory /workspace/26.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.446252915
Short name T642
Test name
Test status
Simulation time 13324847 ps
CPU time 0.96 seconds
Started Jun 02 03:14:00 PM PDT 24
Finished Jun 02 03:14:02 PM PDT 24
Peak memory 211984 kb
Host smart-d71bc9bf-d407-4a16-9a5f-14bae419d8cf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446252915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ct
rl_volatile_unlock_smoke.446252915
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2071360205
Short name T312
Test name
Test status
Simulation time 252209845 ps
CPU time 1.3 seconds
Started Jun 02 03:14:06 PM PDT 24
Finished Jun 02 03:14:08 PM PDT 24
Peak memory 209152 kb
Host smart-33ca4052-c27b-4d7b-b88a-289eea13e9d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071360205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2071360205
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1046624762
Short name T534
Test name
Test status
Simulation time 464638673 ps
CPU time 10.42 seconds
Started Jun 02 03:13:57 PM PDT 24
Finished Jun 02 03:14:08 PM PDT 24
Peak memory 218496 kb
Host smart-5212dc5a-6c83-4cd9-89ed-8e4c864d37ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046624762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1046624762
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.441446127
Short name T751
Test name
Test status
Simulation time 178391222 ps
CPU time 2.05 seconds
Started Jun 02 03:14:04 PM PDT 24
Finished Jun 02 03:14:06 PM PDT 24
Peak memory 209984 kb
Host smart-3c1e6f48-1835-4fb2-82cd-f3a73d2d0473
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441446127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.441446127
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.2736475822
Short name T417
Test name
Test status
Simulation time 100914505 ps
CPU time 4.51 seconds
Started Jun 02 03:13:57 PM PDT 24
Finished Jun 02 03:14:02 PM PDT 24
Peak memory 218344 kb
Host smart-25335d8c-0cd9-4d5c-98e1-2c1e361f3d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736475822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.2736475822
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.4148442724
Short name T436
Test name
Test status
Simulation time 3264947980 ps
CPU time 19.13 seconds
Started Jun 02 03:14:05 PM PDT 24
Finished Jun 02 03:14:24 PM PDT 24
Peak memory 220092 kb
Host smart-75cfb447-6227-4896-b898-7204d6ae8329
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148442724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.4148442724
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3354576670
Short name T552
Test name
Test status
Simulation time 923264382 ps
CPU time 8.63 seconds
Started Jun 02 03:14:04 PM PDT 24
Finished Jun 02 03:14:13 PM PDT 24
Peak memory 225448 kb
Host smart-47672133-12bb-4943-8334-518f829ea99f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354576670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3354576670
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1638688575
Short name T661
Test name
Test status
Simulation time 957044267 ps
CPU time 11.47 seconds
Started Jun 02 03:14:05 PM PDT 24
Finished Jun 02 03:14:17 PM PDT 24
Peak memory 225384 kb
Host smart-80bcb13e-456d-49a8-bf4a-375e55254c17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638688575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1638688575
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.9942331
Short name T603
Test name
Test status
Simulation time 228486640 ps
CPU time 6.8 seconds
Started Jun 02 03:14:05 PM PDT 24
Finished Jun 02 03:14:12 PM PDT 24
Peak memory 218540 kb
Host smart-8f4a5968-03b9-41d4-8fe4-7c8cc609c819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9942331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.9942331
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.3293663185
Short name T707
Test name
Test status
Simulation time 23352318 ps
CPU time 1.92 seconds
Started Jun 02 03:14:05 PM PDT 24
Finished Jun 02 03:14:07 PM PDT 24
Peak memory 218164 kb
Host smart-c8f6a900-80fb-4c52-92b7-02542c445ef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293663185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.3293663185
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.2196255869
Short name T501
Test name
Test status
Simulation time 260007120 ps
CPU time 21.52 seconds
Started Jun 02 03:13:57 PM PDT 24
Finished Jun 02 03:14:20 PM PDT 24
Peak memory 251360 kb
Host smart-b904e5e7-a25b-4fb2-b50f-4dad2c4b53cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196255869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.2196255869
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.2991064024
Short name T645
Test name
Test status
Simulation time 128576288 ps
CPU time 8.08 seconds
Started Jun 02 03:13:59 PM PDT 24
Finished Jun 02 03:14:08 PM PDT 24
Peak memory 251300 kb
Host smart-65d9da49-8125-4e82-9363-2966d5754c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991064024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2991064024
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.3347962127
Short name T158
Test name
Test status
Simulation time 34693534438 ps
CPU time 265.25 seconds
Started Jun 02 03:14:06 PM PDT 24
Finished Jun 02 03:18:32 PM PDT 24
Peak memory 277420 kb
Host smart-5b6454fe-a83c-45d7-b101-cc8a3697cf2d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347962127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.3347962127
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.4028070695
Short name T816
Test name
Test status
Simulation time 16776229 ps
CPU time 0.97 seconds
Started Jun 02 03:14:07 PM PDT 24
Finished Jun 02 03:14:09 PM PDT 24
Peak memory 211980 kb
Host smart-b4b6c34c-f83a-4c48-bc99-13eb51c2a019
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028070695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.4028070695
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.707856147
Short name T793
Test name
Test status
Simulation time 108932635 ps
CPU time 0.85 seconds
Started Jun 02 03:14:08 PM PDT 24
Finished Jun 02 03:14:10 PM PDT 24
Peak memory 209820 kb
Host smart-e2f0dce8-778f-4b4e-a0ea-0591d67b5397
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707856147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.707856147
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.768790361
Short name T761
Test name
Test status
Simulation time 421921459 ps
CPU time 12.02 seconds
Started Jun 02 03:14:04 PM PDT 24
Finished Jun 02 03:14:17 PM PDT 24
Peak memory 218392 kb
Host smart-cd149eff-eb72-44c6-a8da-a33872c1efb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768790361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.768790361
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.2727727687
Short name T735
Test name
Test status
Simulation time 472791940 ps
CPU time 5.41 seconds
Started Jun 02 03:14:06 PM PDT 24
Finished Jun 02 03:14:11 PM PDT 24
Peak memory 209912 kb
Host smart-a5089ead-851e-480a-b8b5-05fb94a4c97b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727727687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.2727727687
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2076417725
Short name T314
Test name
Test status
Simulation time 97440351 ps
CPU time 2.59 seconds
Started Jun 02 03:14:03 PM PDT 24
Finished Jun 02 03:14:06 PM PDT 24
Peak memory 218416 kb
Host smart-6df16a10-a5d1-4c0d-987b-14fa1f1e620c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076417725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2076417725
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.918654944
Short name T318
Test name
Test status
Simulation time 4934491712 ps
CPU time 13.88 seconds
Started Jun 02 03:14:05 PM PDT 24
Finished Jun 02 03:14:20 PM PDT 24
Peak memory 219312 kb
Host smart-f1b28bb7-d3ef-47aa-a866-3c93ebf0499b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918654944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.918654944
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1800790836
Short name T416
Test name
Test status
Simulation time 380563658 ps
CPU time 11.22 seconds
Started Jun 02 03:14:04 PM PDT 24
Finished Jun 02 03:14:15 PM PDT 24
Peak memory 226508 kb
Host smart-73b3d12c-e42e-4cfb-a422-f220088ed396
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800790836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1800790836
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1916710496
Short name T456
Test name
Test status
Simulation time 235257657 ps
CPU time 7 seconds
Started Jun 02 03:14:05 PM PDT 24
Finished Jun 02 03:14:12 PM PDT 24
Peak memory 225212 kb
Host smart-ea212b3c-ab06-41bc-8569-e9ca2dbe4184
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916710496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1916710496
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1643971132
Short name T44
Test name
Test status
Simulation time 910603181 ps
CPU time 6.69 seconds
Started Jun 02 03:14:04 PM PDT 24
Finished Jun 02 03:14:11 PM PDT 24
Peak memory 225296 kb
Host smart-ca0c7b6e-7a91-4aa3-a602-6dcdce2811d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643971132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1643971132
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.2510954747
Short name T57
Test name
Test status
Simulation time 322724916 ps
CPU time 2.08 seconds
Started Jun 02 03:14:07 PM PDT 24
Finished Jun 02 03:14:09 PM PDT 24
Peak memory 218080 kb
Host smart-bf29c466-d2bf-427a-96e8-18fb62cf749a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510954747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.2510954747
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2253478969
Short name T777
Test name
Test status
Simulation time 413176782 ps
CPU time 22.11 seconds
Started Jun 02 03:14:03 PM PDT 24
Finished Jun 02 03:14:25 PM PDT 24
Peak memory 251340 kb
Host smart-7b542672-3f7f-4b3b-ac8e-c4a421eee244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253478969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2253478969
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.518981584
Short name T345
Test name
Test status
Simulation time 173817855 ps
CPU time 2.46 seconds
Started Jun 02 03:14:04 PM PDT 24
Finished Jun 02 03:14:07 PM PDT 24
Peak memory 226748 kb
Host smart-3df1d283-8cc1-40c7-9d74-ef2b9700cb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518981584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.518981584
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3668567670
Short name T177
Test name
Test status
Simulation time 19259745503 ps
CPU time 71.37 seconds
Started Jun 02 03:14:08 PM PDT 24
Finished Jun 02 03:15:20 PM PDT 24
Peak memory 270644 kb
Host smart-1266427b-4399-408a-a20d-8d02d45ed150
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668567670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3668567670
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1874390353
Short name T145
Test name
Test status
Simulation time 85450711 ps
CPU time 0.97 seconds
Started Jun 02 03:14:07 PM PDT 24
Finished Jun 02 03:14:08 PM PDT 24
Peak memory 213012 kb
Host smart-4ed2f519-769f-4c5d-9da8-ad92dd424ce2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874390353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1874390353
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1073466521
Short name T228
Test name
Test status
Simulation time 125702816 ps
CPU time 0.95 seconds
Started Jun 02 03:14:12 PM PDT 24
Finished Jun 02 03:14:14 PM PDT 24
Peak memory 209988 kb
Host smart-560e2ccb-a6fa-4002-a623-977eb1278bde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073466521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1073466521
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2596314985
Short name T659
Test name
Test status
Simulation time 376553680 ps
CPU time 16.58 seconds
Started Jun 02 03:14:09 PM PDT 24
Finished Jun 02 03:14:26 PM PDT 24
Peak memory 218400 kb
Host smart-1da0dceb-2f08-4ba7-83d1-159c1b4e8080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596314985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2596314985
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.1786068599
Short name T470
Test name
Test status
Simulation time 1277012338 ps
CPU time 4.7 seconds
Started Jun 02 03:14:11 PM PDT 24
Finished Jun 02 03:14:16 PM PDT 24
Peak memory 217652 kb
Host smart-3258f972-59cc-4436-89a9-058338c91b2e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786068599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.1786068599
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3963629108
Short name T549
Test name
Test status
Simulation time 78352382 ps
CPU time 2.01 seconds
Started Jun 02 03:14:09 PM PDT 24
Finished Jun 02 03:14:12 PM PDT 24
Peak memory 218480 kb
Host smart-f1b0d349-f221-4c1e-b02e-bc7dc82e90be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963629108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3963629108
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.1074612338
Short name T517
Test name
Test status
Simulation time 239438738 ps
CPU time 8.94 seconds
Started Jun 02 03:14:13 PM PDT 24
Finished Jun 02 03:14:23 PM PDT 24
Peak memory 226776 kb
Host smart-5d1a5897-7d4a-43da-a128-1bd8432d0dfd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074612338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.1074612338
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.2634510046
Short name T514
Test name
Test status
Simulation time 868154575 ps
CPU time 12.96 seconds
Started Jun 02 03:14:09 PM PDT 24
Finished Jun 02 03:14:22 PM PDT 24
Peak memory 226492 kb
Host smart-a1078aa8-2e3d-4202-ae85-e0adbc042199
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634510046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.2634510046
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3914401757
Short name T722
Test name
Test status
Simulation time 756187138 ps
CPU time 9.38 seconds
Started Jun 02 03:14:09 PM PDT 24
Finished Jun 02 03:14:18 PM PDT 24
Peak memory 226440 kb
Host smart-63e3ff5f-92bc-461d-95ea-8406499c30c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914401757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3914401757
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2464325415
Short name T849
Test name
Test status
Simulation time 1214392807 ps
CPU time 6.49 seconds
Started Jun 02 03:14:08 PM PDT 24
Finished Jun 02 03:14:15 PM PDT 24
Peak memory 224652 kb
Host smart-36656fc8-03ec-448b-a8f7-40766fcfab1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464325415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2464325415
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.248984467
Short name T788
Test name
Test status
Simulation time 245610948 ps
CPU time 4.15 seconds
Started Jun 02 03:14:12 PM PDT 24
Finished Jun 02 03:14:17 PM PDT 24
Peak memory 218140 kb
Host smart-dd32ae21-dea5-4c44-b4f7-0e1ca35d3103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248984467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.248984467
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2172819681
Short name T871
Test name
Test status
Simulation time 306760972 ps
CPU time 32.12 seconds
Started Jun 02 03:14:08 PM PDT 24
Finished Jun 02 03:14:41 PM PDT 24
Peak memory 251340 kb
Host smart-a581e500-4d3f-474d-8e89-e21d173c9e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172819681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2172819681
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2337381855
Short name T706
Test name
Test status
Simulation time 115654607 ps
CPU time 6.84 seconds
Started Jun 02 03:14:11 PM PDT 24
Finished Jun 02 03:14:18 PM PDT 24
Peak memory 244956 kb
Host smart-dd348eab-feeb-477a-b3cc-7e80e19da449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337381855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2337381855
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1060239908
Short name T855
Test name
Test status
Simulation time 5715263173 ps
CPU time 112 seconds
Started Jun 02 03:14:10 PM PDT 24
Finished Jun 02 03:16:02 PM PDT 24
Peak memory 251340 kb
Host smart-a5fc3a32-6edb-450d-bc36-6eca42802e2a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060239908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1060239908
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.1609739771
Short name T40
Test name
Test status
Simulation time 27944348059 ps
CPU time 894.85 seconds
Started Jun 02 03:14:10 PM PDT 24
Finished Jun 02 03:29:06 PM PDT 24
Peak memory 775888 kb
Host smart-19a98860-5a44-41d0-af8a-9ab6a5ecb1e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1609739771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.1609739771
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.1181586921
Short name T457
Test name
Test status
Simulation time 35121148 ps
CPU time 0.91 seconds
Started Jun 02 03:14:10 PM PDT 24
Finished Jun 02 03:14:11 PM PDT 24
Peak memory 213264 kb
Host smart-5780ad96-76b6-4e1c-a210-068516e2640a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181586921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.1181586921
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3744824773
Short name T596
Test name
Test status
Simulation time 70705158 ps
CPU time 1.13 seconds
Started Jun 02 03:12:23 PM PDT 24
Finished Jun 02 03:12:24 PM PDT 24
Peak memory 209976 kb
Host smart-e06a70a4-1848-444a-954f-03188134f90e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744824773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3744824773
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3032746288
Short name T217
Test name
Test status
Simulation time 44001723 ps
CPU time 0.8 seconds
Started Jun 02 03:12:17 PM PDT 24
Finished Jun 02 03:12:18 PM PDT 24
Peak memory 209084 kb
Host smart-df9665a0-1c26-44ad-ac61-9e528b3e7a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032746288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3032746288
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.3070046399
Short name T51
Test name
Test status
Simulation time 1897409308 ps
CPU time 8.47 seconds
Started Jun 02 03:12:20 PM PDT 24
Finished Jun 02 03:12:29 PM PDT 24
Peak memory 218436 kb
Host smart-013fd462-e05f-4727-9ef2-5a4e0f6f7be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070046399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.3070046399
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3651125667
Short name T714
Test name
Test status
Simulation time 1431491597 ps
CPU time 4.17 seconds
Started Jun 02 03:12:20 PM PDT 24
Finished Jun 02 03:12:26 PM PDT 24
Peak memory 209896 kb
Host smart-32678760-d10e-4574-ac24-349ca05a99df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651125667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3651125667
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.3171419123
Short name T143
Test name
Test status
Simulation time 2173856852 ps
CPU time 28 seconds
Started Jun 02 03:12:20 PM PDT 24
Finished Jun 02 03:12:49 PM PDT 24
Peak memory 218344 kb
Host smart-c82bdf0b-a849-477b-bd30-54c2e9588353
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171419123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.3171419123
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.2076152126
Short name T60
Test name
Test status
Simulation time 699155010 ps
CPU time 8.89 seconds
Started Jun 02 03:12:23 PM PDT 24
Finished Jun 02 03:12:32 PM PDT 24
Peak memory 217808 kb
Host smart-684bf3b2-ce4a-428a-8c84-73c9ee43d3cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076152126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.2
076152126
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.377052702
Short name T607
Test name
Test status
Simulation time 1090602672 ps
CPU time 4.5 seconds
Started Jun 02 03:12:22 PM PDT 24
Finished Jun 02 03:12:27 PM PDT 24
Peak memory 218292 kb
Host smart-14ef2b07-60ae-4c49-b373-5b57977461d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377052702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
prog_failure.377052702
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.3804274973
Short name T70
Test name
Test status
Simulation time 3262954593 ps
CPU time 11.34 seconds
Started Jun 02 03:12:30 PM PDT 24
Finished Jun 02 03:12:43 PM PDT 24
Peak memory 218048 kb
Host smart-67265214-6c09-4f36-9df8-8c3e72dbdfc7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804274973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.3804274973
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.4072122760
Short name T512
Test name
Test status
Simulation time 168329102 ps
CPU time 3.47 seconds
Started Jun 02 03:12:20 PM PDT 24
Finished Jun 02 03:12:24 PM PDT 24
Peak memory 218048 kb
Host smart-cd3c68ff-6461-44c3-9e25-7d2a4c4d79a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072122760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
4072122760
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.3281050649
Short name T278
Test name
Test status
Simulation time 3070675039 ps
CPU time 38.98 seconds
Started Jun 02 03:12:19 PM PDT 24
Finished Jun 02 03:12:58 PM PDT 24
Peak memory 251328 kb
Host smart-ab65242d-21af-4400-9241-a9c75964bccc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281050649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.3281050649
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.215350343
Short name T803
Test name
Test status
Simulation time 1986055243 ps
CPU time 14.08 seconds
Started Jun 02 03:12:21 PM PDT 24
Finished Jun 02 03:12:37 PM PDT 24
Peak memory 251176 kb
Host smart-84b0e0ba-ed1e-4ed9-adca-1e0ecb7ffdb5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215350343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.215350343
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.2193430155
Short name T9
Test name
Test status
Simulation time 55258576 ps
CPU time 2.59 seconds
Started Jun 02 03:12:22 PM PDT 24
Finished Jun 02 03:12:25 PM PDT 24
Peak memory 218404 kb
Host smart-bf633bf3-d431-413d-b03e-a813c8bbe890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193430155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.2193430155
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1236155198
Short name T724
Test name
Test status
Simulation time 382892286 ps
CPU time 20.96 seconds
Started Jun 02 03:12:22 PM PDT 24
Finished Jun 02 03:12:43 PM PDT 24
Peak memory 218168 kb
Host smart-1670d884-d538-4d67-9acc-b3091ff7551c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236155198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1236155198
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2039005096
Short name T46
Test name
Test status
Simulation time 112533080 ps
CPU time 22.58 seconds
Started Jun 02 03:12:30 PM PDT 24
Finished Jun 02 03:12:54 PM PDT 24
Peak memory 282880 kb
Host smart-e203cf11-58c1-401f-a54a-e4f34ec94f33
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039005096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2039005096
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.3374555669
Short name T430
Test name
Test status
Simulation time 841518550 ps
CPU time 21.01 seconds
Started Jun 02 03:12:24 PM PDT 24
Finished Jun 02 03:12:46 PM PDT 24
Peak memory 226472 kb
Host smart-14b7698b-640b-4f1a-80bb-27b5fb51cc4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374555669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.3374555669
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2396830219
Short name T572
Test name
Test status
Simulation time 846314434 ps
CPU time 8.47 seconds
Started Jun 02 03:12:27 PM PDT 24
Finished Jun 02 03:12:37 PM PDT 24
Peak memory 226476 kb
Host smart-19566d65-c99d-415e-82bc-f89712ebeba4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396830219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2396830219
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.1577276061
Short name T54
Test name
Test status
Simulation time 469582800 ps
CPU time 6.68 seconds
Started Jun 02 03:12:24 PM PDT 24
Finished Jun 02 03:12:31 PM PDT 24
Peak memory 225092 kb
Host smart-fb3451b6-93f2-4d3a-b076-65a92caac2f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577276061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.1
577276061
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.586636745
Short name T869
Test name
Test status
Simulation time 3479300674 ps
CPU time 11.72 seconds
Started Jun 02 03:12:20 PM PDT 24
Finished Jun 02 03:12:33 PM PDT 24
Peak memory 218720 kb
Host smart-b83c9905-2b7b-4c53-8f95-43126357435f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586636745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.586636745
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.121580322
Short name T755
Test name
Test status
Simulation time 56687687 ps
CPU time 3.15 seconds
Started Jun 02 03:12:16 PM PDT 24
Finished Jun 02 03:12:20 PM PDT 24
Peak memory 214576 kb
Host smart-1f8a8c01-6861-4ec7-8482-7658b6cb62b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121580322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.121580322
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.539662336
Short name T80
Test name
Test status
Simulation time 299666141 ps
CPU time 28.52 seconds
Started Jun 02 03:12:19 PM PDT 24
Finished Jun 02 03:12:49 PM PDT 24
Peak memory 251396 kb
Host smart-ce45c89b-c168-43b0-a859-d693b16815b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539662336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.539662336
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.2775979579
Short name T146
Test name
Test status
Simulation time 431378545 ps
CPU time 8.92 seconds
Started Jun 02 03:12:20 PM PDT 24
Finished Jun 02 03:12:30 PM PDT 24
Peak memory 251324 kb
Host smart-83cce135-d842-4325-84d9-90c67452e640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775979579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.2775979579
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.558266427
Short name T669
Test name
Test status
Simulation time 17249870408 ps
CPU time 81.9 seconds
Started Jun 02 03:12:22 PM PDT 24
Finished Jun 02 03:13:45 PM PDT 24
Peak memory 251388 kb
Host smart-5065bd44-41bd-464d-90e0-bb7dcb0d807b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558266427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.558266427
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.2271770956
Short name T106
Test name
Test status
Simulation time 119438143356 ps
CPU time 828.37 seconds
Started Jun 02 03:12:30 PM PDT 24
Finished Jun 02 03:26:20 PM PDT 24
Peak memory 333096 kb
Host smart-9c149cac-c6eb-470e-9fc1-ae8553eb7cb6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2271770956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.2271770956
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1659305550
Short name T840
Test name
Test status
Simulation time 13877371 ps
CPU time 1.09 seconds
Started Jun 02 03:12:18 PM PDT 24
Finished Jun 02 03:12:19 PM PDT 24
Peak memory 211932 kb
Host smart-e708fae8-2b9e-4313-b9ec-5efec0897880
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659305550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.1659305550
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1767743294
Short name T621
Test name
Test status
Simulation time 21531992 ps
CPU time 0.94 seconds
Started Jun 02 03:14:15 PM PDT 24
Finished Jun 02 03:14:16 PM PDT 24
Peak memory 209144 kb
Host smart-1369db7f-cedc-43ab-86f8-0aa1895196ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767743294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1767743294
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2730820164
Short name T717
Test name
Test status
Simulation time 4736560455 ps
CPU time 14.33 seconds
Started Jun 02 03:14:14 PM PDT 24
Finished Jun 02 03:14:28 PM PDT 24
Peak memory 218884 kb
Host smart-10f2015b-44a7-43b8-ba43-b2319249f025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730820164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2730820164
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2488113927
Short name T190
Test name
Test status
Simulation time 548582128 ps
CPU time 2.2 seconds
Started Jun 02 03:14:09 PM PDT 24
Finished Jun 02 03:14:12 PM PDT 24
Peak memory 209916 kb
Host smart-40cd6838-df6e-421d-99f1-733d1b59d3b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488113927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2488113927
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2515797523
Short name T506
Test name
Test status
Simulation time 93909010 ps
CPU time 3.07 seconds
Started Jun 02 03:14:08 PM PDT 24
Finished Jun 02 03:14:11 PM PDT 24
Peak memory 218320 kb
Host smart-c1587fe2-cd2f-4ec8-bfeb-3ead9b3aa915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515797523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2515797523
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.3203697049
Short name T331
Test name
Test status
Simulation time 366796690 ps
CPU time 15.71 seconds
Started Jun 02 03:14:14 PM PDT 24
Finished Jun 02 03:14:31 PM PDT 24
Peak memory 219344 kb
Host smart-b58730e6-f87c-46fb-88e8-998f9408b4b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203697049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.3203697049
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.2074687215
Short name T273
Test name
Test status
Simulation time 1899421301 ps
CPU time 8.39 seconds
Started Jun 02 03:14:13 PM PDT 24
Finished Jun 02 03:14:22 PM PDT 24
Peak memory 226108 kb
Host smart-b5def0e3-d945-426c-85e9-6bac498a84dc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074687215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.2074687215
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.2318060371
Short name T667
Test name
Test status
Simulation time 4239286471 ps
CPU time 8.44 seconds
Started Jun 02 03:14:12 PM PDT 24
Finished Jun 02 03:14:21 PM PDT 24
Peak memory 226556 kb
Host smart-c8096fd9-b0a1-4b35-aea7-91d7f73d4a14
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318060371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
2318060371
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.2919658874
Short name T49
Test name
Test status
Simulation time 410927122 ps
CPU time 9.7 seconds
Started Jun 02 03:14:12 PM PDT 24
Finished Jun 02 03:14:22 PM PDT 24
Peak memory 226488 kb
Host smart-43b4a1c0-e97a-4298-b2b6-4ef2571dddb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919658874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.2919658874
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1888554815
Short name T561
Test name
Test status
Simulation time 71932065 ps
CPU time 3.27 seconds
Started Jun 02 03:14:11 PM PDT 24
Finished Jun 02 03:14:15 PM PDT 24
Peak memory 214800 kb
Host smart-8411ca5c-25bb-4a23-be70-6e0b267964ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888554815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1888554815
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3301380465
Short name T88
Test name
Test status
Simulation time 194033499 ps
CPU time 18.31 seconds
Started Jun 02 03:14:09 PM PDT 24
Finished Jun 02 03:14:28 PM PDT 24
Peak memory 251308 kb
Host smart-5977121b-c1b8-4b34-b540-b3d0615f6fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301380465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3301380465
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.2746219208
Short name T752
Test name
Test status
Simulation time 280293609 ps
CPU time 4.61 seconds
Started Jun 02 03:14:13 PM PDT 24
Finished Jun 02 03:14:18 PM PDT 24
Peak memory 223480 kb
Host smart-090a1e6e-294d-41f8-8a66-1ffa180765e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746219208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.2746219208
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.1878704272
Short name T188
Test name
Test status
Simulation time 29018178679 ps
CPU time 219.63 seconds
Started Jun 02 03:14:13 PM PDT 24
Finished Jun 02 03:17:53 PM PDT 24
Peak memory 405080 kb
Host smart-31a95ab8-d20c-46dd-93eb-0f6852cc7663
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878704272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.1878704272
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all_with_rand_reset.1473357734
Short name T798
Test name
Test status
Simulation time 181030156883 ps
CPU time 431.85 seconds
Started Jun 02 03:14:14 PM PDT 24
Finished Jun 02 03:21:26 PM PDT 24
Peak memory 284256 kb
Host smart-a5c542b7-d02d-41fa-a8e2-bbe19dc12bf6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1473357734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_stress_all_with_rand_reset.1473357734
Directory /workspace/30.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.582185739
Short name T779
Test name
Test status
Simulation time 39456577 ps
CPU time 0.9 seconds
Started Jun 02 03:14:11 PM PDT 24
Finished Jun 02 03:14:12 PM PDT 24
Peak memory 212100 kb
Host smart-3d8dbb27-40a8-482e-ae3d-b127efda127c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582185739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.582185739
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3491993597
Short name T407
Test name
Test status
Simulation time 284281481 ps
CPU time 0.98 seconds
Started Jun 02 03:14:15 PM PDT 24
Finished Jun 02 03:14:17 PM PDT 24
Peak memory 209224 kb
Host smart-7790736d-c374-4b3a-9929-a4b91db69c3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491993597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3491993597
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.1074513313
Short name T420
Test name
Test status
Simulation time 664243476 ps
CPU time 13.41 seconds
Started Jun 02 03:14:14 PM PDT 24
Finished Jun 02 03:14:28 PM PDT 24
Peak memory 218424 kb
Host smart-06c75713-7b54-4956-b730-002d740a78e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074513313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.1074513313
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.295095975
Short name T335
Test name
Test status
Simulation time 705690189 ps
CPU time 9.73 seconds
Started Jun 02 03:14:13 PM PDT 24
Finished Jun 02 03:14:23 PM PDT 24
Peak memory 209948 kb
Host smart-429dc9d6-eebc-42d5-96ed-d5b062b11668
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295095975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.295095975
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3783705067
Short name T334
Test name
Test status
Simulation time 59459703 ps
CPU time 3.28 seconds
Started Jun 02 03:14:13 PM PDT 24
Finished Jun 02 03:14:17 PM PDT 24
Peak memory 218496 kb
Host smart-ff40d7f1-5952-4264-b1b9-861641fb58a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783705067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3783705067
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.704540204
Short name T427
Test name
Test status
Simulation time 1722409896 ps
CPU time 18.72 seconds
Started Jun 02 03:14:13 PM PDT 24
Finished Jun 02 03:14:32 PM PDT 24
Peak memory 219364 kb
Host smart-f638ec4a-e764-4984-8cb4-f28957ea3d7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704540204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.704540204
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.3131329626
Short name T185
Test name
Test status
Simulation time 343912465 ps
CPU time 7.17 seconds
Started Jun 02 03:14:15 PM PDT 24
Finished Jun 02 03:14:23 PM PDT 24
Peak memory 226432 kb
Host smart-b071586e-ebcd-4673-b479-ea6f515ee45d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131329626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.3131329626
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.4216738268
Short name T859
Test name
Test status
Simulation time 1006309920 ps
CPU time 7.7 seconds
Started Jun 02 03:14:15 PM PDT 24
Finished Jun 02 03:14:23 PM PDT 24
Peak memory 225168 kb
Host smart-fb1bd8fc-352a-49b3-a34d-4e423a67f308
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216738268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
4216738268
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1888482743
Short name T454
Test name
Test status
Simulation time 1382299805 ps
CPU time 7.94 seconds
Started Jun 02 03:14:12 PM PDT 24
Finished Jun 02 03:14:21 PM PDT 24
Peak memory 224956 kb
Host smart-984ce077-fb9f-45b0-b0e9-53f57d11c113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888482743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1888482743
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.342111183
Short name T758
Test name
Test status
Simulation time 52972556 ps
CPU time 2.42 seconds
Started Jun 02 03:14:13 PM PDT 24
Finished Jun 02 03:14:16 PM PDT 24
Peak memory 214360 kb
Host smart-3e189efb-923a-4244-aede-a750db61a68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342111183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.342111183
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.1447082435
Short name T319
Test name
Test status
Simulation time 259612684 ps
CPU time 32.96 seconds
Started Jun 02 03:14:14 PM PDT 24
Finished Jun 02 03:14:48 PM PDT 24
Peak memory 251308 kb
Host smart-808f3fea-0e7e-424f-a86b-f9604a9c5fe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447082435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.1447082435
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3305562630
Short name T320
Test name
Test status
Simulation time 672342714 ps
CPU time 8.07 seconds
Started Jun 02 03:14:14 PM PDT 24
Finished Jun 02 03:14:23 PM PDT 24
Peak memory 247500 kb
Host smart-103a884f-b592-4ca6-a2ec-12b6f7ba2a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305562630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3305562630
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2256896504
Short name T485
Test name
Test status
Simulation time 31781573574 ps
CPU time 156.49 seconds
Started Jun 02 03:14:17 PM PDT 24
Finished Jun 02 03:16:54 PM PDT 24
Peak memory 263284 kb
Host smart-214c719a-a1fd-48f2-9f7c-f20cdc64eaf0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256896504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2256896504
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all_with_rand_reset.2033337844
Short name T823
Test name
Test status
Simulation time 14964503836 ps
CPU time 413.34 seconds
Started Jun 02 03:14:14 PM PDT 24
Finished Jun 02 03:21:08 PM PDT 24
Peak memory 317052 kb
Host smart-787d119b-91b1-466c-9aad-70f8b83e5c98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2033337844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_stress_all_with_rand_reset.2033337844
Directory /workspace/31.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.3076232876
Short name T182
Test name
Test status
Simulation time 30366172 ps
CPU time 0.86 seconds
Started Jun 02 03:14:16 PM PDT 24
Finished Jun 02 03:14:17 PM PDT 24
Peak memory 211956 kb
Host smart-fc4496e6-71ca-4662-9a3d-00291f3b94ed
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076232876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.3076232876
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.533858240
Short name T290
Test name
Test status
Simulation time 17739624 ps
CPU time 0.91 seconds
Started Jun 02 03:14:22 PM PDT 24
Finished Jun 02 03:14:24 PM PDT 24
Peak memory 209068 kb
Host smart-9a1bbedf-302b-44f1-8086-4d4d66c72429
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533858240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.533858240
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.2379342118
Short name T654
Test name
Test status
Simulation time 303701958 ps
CPU time 10.7 seconds
Started Jun 02 03:14:20 PM PDT 24
Finished Jun 02 03:14:31 PM PDT 24
Peak memory 218380 kb
Host smart-3a02156d-c441-47fb-a048-7a9ef0151246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379342118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.2379342118
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2164687635
Short name T28
Test name
Test status
Simulation time 1815045787 ps
CPU time 6.11 seconds
Started Jun 02 03:14:20 PM PDT 24
Finished Jun 02 03:14:26 PM PDT 24
Peak memory 217560 kb
Host smart-19ef42e9-10e2-482c-a810-28553839bf27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164687635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2164687635
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.2133213429
Short name T341
Test name
Test status
Simulation time 358736271 ps
CPU time 1.92 seconds
Started Jun 02 03:14:14 PM PDT 24
Finished Jun 02 03:14:17 PM PDT 24
Peak memory 218404 kb
Host smart-bdbf385a-725e-457a-88af-743970c916eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133213429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2133213429
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.950192733
Short name T503
Test name
Test status
Simulation time 377041576 ps
CPU time 13.37 seconds
Started Jun 02 03:14:18 PM PDT 24
Finished Jun 02 03:14:32 PM PDT 24
Peak memory 218860 kb
Host smart-97da0591-6d44-4bfa-a592-8b9aeca33381
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950192733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.950192733
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.3878026918
Short name T590
Test name
Test status
Simulation time 3514520163 ps
CPU time 8.14 seconds
Started Jun 02 03:14:19 PM PDT 24
Finished Jun 02 03:14:28 PM PDT 24
Peak memory 226556 kb
Host smart-201086b1-8396-4378-a4b5-4f245e885310
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878026918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.3878026918
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.1473870649
Short name T690
Test name
Test status
Simulation time 1141176438 ps
CPU time 8.24 seconds
Started Jun 02 03:14:19 PM PDT 24
Finished Jun 02 03:14:28 PM PDT 24
Peak memory 225120 kb
Host smart-2b3cfb97-fba1-4d8e-8df0-28ce5c505acf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473870649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
1473870649
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.2489264921
Short name T762
Test name
Test status
Simulation time 1752180429 ps
CPU time 14.41 seconds
Started Jun 02 03:14:22 PM PDT 24
Finished Jun 02 03:14:37 PM PDT 24
Peak memory 218484 kb
Host smart-00ab93b2-f46f-4027-9699-982799b678ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489264921 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.2489264921
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.1418717668
Short name T644
Test name
Test status
Simulation time 22123988 ps
CPU time 1.16 seconds
Started Jun 02 03:14:14 PM PDT 24
Finished Jun 02 03:14:16 PM PDT 24
Peak memory 218104 kb
Host smart-7b58b8f2-d7d4-46fe-bbf5-233d6cdff161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418717668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1418717668
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.666250814
Short name T362
Test name
Test status
Simulation time 541227516 ps
CPU time 29.04 seconds
Started Jun 02 03:14:16 PM PDT 24
Finished Jun 02 03:14:45 PM PDT 24
Peak memory 251520 kb
Host smart-a33b3f77-dbe4-4cd3-89c3-f2619193177f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666250814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.666250814
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1278888462
Short name T781
Test name
Test status
Simulation time 284655327 ps
CPU time 10.6 seconds
Started Jun 02 03:14:14 PM PDT 24
Finished Jun 02 03:14:25 PM PDT 24
Peak memory 251332 kb
Host smart-fdaaffe2-782d-4211-9b96-240403da99b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278888462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1278888462
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.1334419201
Short name T17
Test name
Test status
Simulation time 6520549692 ps
CPU time 61.85 seconds
Started Jun 02 03:14:17 PM PDT 24
Finished Jun 02 03:15:20 PM PDT 24
Peak memory 275784 kb
Host smart-5679954e-d826-42f0-bc76-239c865fb96c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334419201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.1334419201
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.3111002263
Short name T400
Test name
Test status
Simulation time 18382251 ps
CPU time 0.98 seconds
Started Jun 02 03:14:14 PM PDT 24
Finished Jun 02 03:14:16 PM PDT 24
Peak memory 211988 kb
Host smart-c0162492-991d-497a-bb5a-853922d11354
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111002263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.3111002263
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1456422361
Short name T237
Test name
Test status
Simulation time 43452443 ps
CPU time 0.98 seconds
Started Jun 02 03:14:23 PM PDT 24
Finished Jun 02 03:14:24 PM PDT 24
Peak memory 209988 kb
Host smart-06d694ae-3bc1-4a6e-8f1e-f4d53530df17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456422361 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1456422361
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3210787370
Short name T687
Test name
Test status
Simulation time 194739131 ps
CPU time 9.42 seconds
Started Jun 02 03:14:24 PM PDT 24
Finished Jun 02 03:14:34 PM PDT 24
Peak memory 218376 kb
Host smart-aa4f720c-825c-478e-9577-7acfca36147b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210787370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3210787370
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.964942201
Short name T872
Test name
Test status
Simulation time 1344262383 ps
CPU time 16.29 seconds
Started Jun 02 03:14:20 PM PDT 24
Finished Jun 02 03:14:37 PM PDT 24
Peak memory 209916 kb
Host smart-4b233712-af39-40fe-a586-00717e787b61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964942201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.964942201
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2834196576
Short name T415
Test name
Test status
Simulation time 44398872 ps
CPU time 1.41 seconds
Started Jun 02 03:14:19 PM PDT 24
Finished Jun 02 03:14:21 PM PDT 24
Peak memory 218392 kb
Host smart-fd3ef9ce-0fbe-4fe3-b671-55ac895aa7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834196576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2834196576
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1952115027
Short name T443
Test name
Test status
Simulation time 1271305756 ps
CPU time 12.31 seconds
Started Jun 02 03:14:19 PM PDT 24
Finished Jun 02 03:14:32 PM PDT 24
Peak memory 218552 kb
Host smart-7267628d-4320-47e7-9532-875799306d4a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952115027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1952115027
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.1693579398
Short name T97
Test name
Test status
Simulation time 448652598 ps
CPU time 12.09 seconds
Started Jun 02 03:14:24 PM PDT 24
Finished Jun 02 03:14:37 PM PDT 24
Peak memory 226344 kb
Host smart-11886ed1-6385-4102-8174-922093ec4d70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693579398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.1693579398
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3557082102
Short name T500
Test name
Test status
Simulation time 2337783163 ps
CPU time 10.78 seconds
Started Jun 02 03:14:19 PM PDT 24
Finished Jun 02 03:14:30 PM PDT 24
Peak memory 225940 kb
Host smart-6aff2d8e-cd44-4b99-bcc1-c630e058c602
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3557082102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3557082102
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.2934286158
Short name T53
Test name
Test status
Simulation time 407973047 ps
CPU time 9.96 seconds
Started Jun 02 03:14:24 PM PDT 24
Finished Jun 02 03:14:34 PM PDT 24
Peak memory 225252 kb
Host smart-d0dcac77-7d03-4799-a0a7-9469502cd59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934286158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.2934286158
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1847566783
Short name T543
Test name
Test status
Simulation time 34973276 ps
CPU time 2.17 seconds
Started Jun 02 03:14:18 PM PDT 24
Finished Jun 02 03:14:20 PM PDT 24
Peak memory 214456 kb
Host smart-b634eef0-ae3c-4cd2-8f60-5fd35c59314a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1847566783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1847566783
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.71800130
Short name T796
Test name
Test status
Simulation time 2033581360 ps
CPU time 29.89 seconds
Started Jun 02 03:14:23 PM PDT 24
Finished Jun 02 03:14:54 PM PDT 24
Peak memory 251288 kb
Host smart-0f2b14bc-37d7-4cab-a257-28a8c32e75f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71800130 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.71800130
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.4199196923
Short name T804
Test name
Test status
Simulation time 203782603 ps
CPU time 3.6 seconds
Started Jun 02 03:14:22 PM PDT 24
Finished Jun 02 03:14:26 PM PDT 24
Peak memory 222968 kb
Host smart-0c088622-c850-4ad9-9ed7-85dddec23dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199196923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.4199196923
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.4248809188
Short name T280
Test name
Test status
Simulation time 6966922777 ps
CPU time 263.9 seconds
Started Jun 02 03:14:18 PM PDT 24
Finished Jun 02 03:18:42 PM PDT 24
Peak memory 270792 kb
Host smart-3bf3ada2-6f5d-4b4d-bb19-f7d6c90ca6e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248809188 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.4248809188
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2994942335
Short name T852
Test name
Test status
Simulation time 11593303 ps
CPU time 0.85 seconds
Started Jun 02 03:14:18 PM PDT 24
Finished Jun 02 03:14:19 PM PDT 24
Peak memory 211908 kb
Host smart-17ac7a9c-f1ba-4f4b-8c0c-fca5769cf451
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994942335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2994942335
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.1981573563
Short name T323
Test name
Test status
Simulation time 103092862 ps
CPU time 1.47 seconds
Started Jun 02 03:14:24 PM PDT 24
Finished Jun 02 03:14:26 PM PDT 24
Peak memory 209192 kb
Host smart-ffaac867-f317-4ee0-89af-cc1302304f07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981573563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.1981573563
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.4179577109
Short name T375
Test name
Test status
Simulation time 404964986 ps
CPU time 11.47 seconds
Started Jun 02 03:14:16 PM PDT 24
Finished Jun 02 03:14:28 PM PDT 24
Peak memory 218364 kb
Host smart-630c6e0d-d8b0-4005-b9f6-8c623ec2077e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179577109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.4179577109
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.532307062
Short name T306
Test name
Test status
Simulation time 282497294 ps
CPU time 2.43 seconds
Started Jun 02 03:14:20 PM PDT 24
Finished Jun 02 03:14:23 PM PDT 24
Peak memory 209972 kb
Host smart-d6151be4-3c7a-4fd4-803c-380f27da8df6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=532307062 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.532307062
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.939188118
Short name T521
Test name
Test status
Simulation time 279945300 ps
CPU time 2.87 seconds
Started Jun 02 03:14:23 PM PDT 24
Finished Jun 02 03:14:26 PM PDT 24
Peak memory 218420 kb
Host smart-fc6cb245-9253-44db-94e2-6198433ee3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939188118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.939188118
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.2108316499
Short name T316
Test name
Test status
Simulation time 2917964112 ps
CPU time 9.22 seconds
Started Jun 02 03:14:23 PM PDT 24
Finished Jun 02 03:14:33 PM PDT 24
Peak memory 226576 kb
Host smart-f167ca9b-3969-4837-a741-9533e49b69f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108316499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2108316499
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.3797361866
Short name T326
Test name
Test status
Simulation time 1977750041 ps
CPU time 16.75 seconds
Started Jun 02 03:14:23 PM PDT 24
Finished Jun 02 03:14:41 PM PDT 24
Peak memory 226492 kb
Host smart-5d553976-c38f-482b-bcdc-aa4c4c5b44b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797361866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.3797361866
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.1150740689
Short name T353
Test name
Test status
Simulation time 570150287 ps
CPU time 13.8 seconds
Started Jun 02 03:14:23 PM PDT 24
Finished Jun 02 03:14:37 PM PDT 24
Peak memory 218400 kb
Host smart-708bc7a7-83a2-44e3-8d3a-ceb8d1aff331
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150740689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
1150740689
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.796519702
Short name T311
Test name
Test status
Simulation time 574196807 ps
CPU time 11.58 seconds
Started Jun 02 03:14:17 PM PDT 24
Finished Jun 02 03:14:29 PM PDT 24
Peak memory 218556 kb
Host smart-86cc391a-d74a-46a1-ac3f-f83e01f0c8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796519702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.796519702
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2189969672
Short name T72
Test name
Test status
Simulation time 63444466 ps
CPU time 3.44 seconds
Started Jun 02 03:14:19 PM PDT 24
Finished Jun 02 03:14:23 PM PDT 24
Peak memory 218116 kb
Host smart-a208f122-5713-40d2-80f6-2857efceb32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189969672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2189969672
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.1918526671
Short name T731
Test name
Test status
Simulation time 368432107 ps
CPU time 25.19 seconds
Started Jun 02 03:14:22 PM PDT 24
Finished Jun 02 03:14:48 PM PDT 24
Peak memory 251308 kb
Host smart-b4fc486a-6322-430f-b879-145c7b73a928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918526671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.1918526671
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3280997372
Short name T703
Test name
Test status
Simulation time 132850468 ps
CPU time 6.75 seconds
Started Jun 02 03:14:18 PM PDT 24
Finished Jun 02 03:14:25 PM PDT 24
Peak memory 250800 kb
Host smart-6fa7587d-15bf-4d6e-a109-c47e88b5f2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280997372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3280997372
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.1046271898
Short name T102
Test name
Test status
Simulation time 69015163085 ps
CPU time 574.04 seconds
Started Jun 02 03:14:27 PM PDT 24
Finished Jun 02 03:24:01 PM PDT 24
Peak memory 284364 kb
Host smart-99c73831-a37d-4bf6-92d3-865105231f20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1046271898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.1046271898
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2583924095
Short name T347
Test name
Test status
Simulation time 18639162 ps
CPU time 0.98 seconds
Started Jun 02 03:14:20 PM PDT 24
Finished Jun 02 03:14:22 PM PDT 24
Peak memory 212060 kb
Host smart-5d9e674a-05eb-4095-9e6e-4487bda1086f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583924095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2583924095
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.2591590020
Short name T583
Test name
Test status
Simulation time 88670510 ps
CPU time 1.07 seconds
Started Jun 02 03:14:28 PM PDT 24
Finished Jun 02 03:14:30 PM PDT 24
Peak memory 209192 kb
Host smart-62fc715c-6458-481e-a5a4-744d22ecd4a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591590020 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.2591590020
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.643525537
Short name T479
Test name
Test status
Simulation time 436479368 ps
CPU time 12.48 seconds
Started Jun 02 03:14:22 PM PDT 24
Finished Jun 02 03:14:36 PM PDT 24
Peak memory 218396 kb
Host smart-f46b8fce-acf6-45c6-9120-b53ee584ebc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643525537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.643525537
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3356668441
Short name T826
Test name
Test status
Simulation time 1376348894 ps
CPU time 4.94 seconds
Started Jun 02 03:14:24 PM PDT 24
Finished Jun 02 03:14:30 PM PDT 24
Peak memory 217448 kb
Host smart-f08f48f6-bdad-45ea-bded-cb1911746b7b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356668441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3356668441
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.4101104485
Short name T404
Test name
Test status
Simulation time 76252325 ps
CPU time 3.27 seconds
Started Jun 02 03:14:24 PM PDT 24
Finished Jun 02 03:14:27 PM PDT 24
Peak memory 218428 kb
Host smart-be7e6458-c5ea-4eee-9500-b04e11830c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101104485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.4101104485
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1469141156
Short name T299
Test name
Test status
Simulation time 338260379 ps
CPU time 10.79 seconds
Started Jun 02 03:14:24 PM PDT 24
Finished Jun 02 03:14:35 PM PDT 24
Peak memory 219340 kb
Host smart-8071dc9c-0aff-495b-8393-3be60ffdb43e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469141156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1469141156
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2311073719
Short name T663
Test name
Test status
Simulation time 1157088539 ps
CPU time 11.87 seconds
Started Jun 02 03:14:31 PM PDT 24
Finished Jun 02 03:14:43 PM PDT 24
Peak memory 218664 kb
Host smart-69753afc-178d-4463-b0d0-f09fa90c1cee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311073719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2311073719
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2871804243
Short name T799
Test name
Test status
Simulation time 4536324046 ps
CPU time 13.81 seconds
Started Jun 02 03:14:26 PM PDT 24
Finished Jun 02 03:14:40 PM PDT 24
Peak memory 226512 kb
Host smart-728ea8a0-3200-4463-bdde-f0555a457201
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871804243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2871804243
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.3477337659
Short name T391
Test name
Test status
Simulation time 36388276 ps
CPU time 2.23 seconds
Started Jun 02 03:14:23 PM PDT 24
Finished Jun 02 03:14:26 PM PDT 24
Peak memory 218056 kb
Host smart-b87601b7-3ce0-4d81-bfe6-085282c2f641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477337659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.3477337659
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.2062202710
Short name T673
Test name
Test status
Simulation time 467850529 ps
CPU time 10.17 seconds
Started Jun 02 03:14:23 PM PDT 24
Finished Jun 02 03:14:34 PM PDT 24
Peak memory 251316 kb
Host smart-432e1aa6-376a-4a89-a6ec-06fec528e9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062202710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2062202710
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2535460465
Short name T772
Test name
Test status
Simulation time 1727538086 ps
CPU time 72.97 seconds
Started Jun 02 03:14:29 PM PDT 24
Finished Jun 02 03:15:42 PM PDT 24
Peak memory 277464 kb
Host smart-647aa162-b96f-4a84-a27f-80a8d84d4d18
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535460465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2535460465
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.2661607154
Short name T151
Test name
Test status
Simulation time 54966325843 ps
CPU time 1501.17 seconds
Started Jun 02 03:14:27 PM PDT 24
Finished Jun 02 03:39:28 PM PDT 24
Peak memory 513672 kb
Host smart-c7dd2af6-4d1a-4adc-8750-2a445554fb9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2661607154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.2661607154
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.2324278639
Short name T172
Test name
Test status
Simulation time 43734282 ps
CPU time 0.99 seconds
Started Jun 02 03:14:26 PM PDT 24
Finished Jun 02 03:14:27 PM PDT 24
Peak memory 213140 kb
Host smart-deef1b57-5b35-410e-ad63-26421134c742
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324278639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.2324278639
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.2501470012
Short name T263
Test name
Test status
Simulation time 145365589 ps
CPU time 1.12 seconds
Started Jun 02 03:14:29 PM PDT 24
Finished Jun 02 03:14:31 PM PDT 24
Peak memory 209920 kb
Host smart-9d3e71e1-dea7-44b7-829b-43dd421ae2ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501470012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.2501470012
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.3304517456
Short name T508
Test name
Test status
Simulation time 1444469574 ps
CPU time 10.26 seconds
Started Jun 02 03:14:32 PM PDT 24
Finished Jun 02 03:14:42 PM PDT 24
Peak memory 218408 kb
Host smart-46b08ec2-ab75-486a-876d-afa90bebfa9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304517456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.3304517456
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1301376670
Short name T562
Test name
Test status
Simulation time 1045250780 ps
CPU time 12.27 seconds
Started Jun 02 03:14:28 PM PDT 24
Finished Jun 02 03:14:41 PM PDT 24
Peak memory 217532 kb
Host smart-8209ad50-61bf-4b38-9258-1c80f0366813
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301376670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1301376670
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3435235799
Short name T783
Test name
Test status
Simulation time 54623076 ps
CPU time 1.78 seconds
Started Jun 02 03:14:30 PM PDT 24
Finished Jun 02 03:14:32 PM PDT 24
Peak memory 218392 kb
Host smart-a8620e19-e95b-4522-9f40-e4d5ad76f5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435235799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3435235799
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1944017233
Short name T737
Test name
Test status
Simulation time 1125414250 ps
CPU time 12.39 seconds
Started Jun 02 03:14:28 PM PDT 24
Finished Jun 02 03:14:41 PM PDT 24
Peak memory 219288 kb
Host smart-a248a9d7-cdce-4b00-9acc-87b59931d12d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944017233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1944017233
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.373057705
Short name T255
Test name
Test status
Simulation time 1436239117 ps
CPU time 11.85 seconds
Started Jun 02 03:14:28 PM PDT 24
Finished Jun 02 03:14:40 PM PDT 24
Peak memory 226508 kb
Host smart-b15eb83e-33ba-4cdc-87cd-6c6e46d6ad26
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=373057705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.373057705
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.3990352257
Short name T723
Test name
Test status
Simulation time 212351725 ps
CPU time 8.46 seconds
Started Jun 02 03:14:27 PM PDT 24
Finished Jun 02 03:14:36 PM PDT 24
Peak memory 225084 kb
Host smart-650b1ad6-e215-4843-a0a8-48bf47e4b08f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990352257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
3990352257
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.97895633
Short name T48
Test name
Test status
Simulation time 569809867 ps
CPU time 7.01 seconds
Started Jun 02 03:14:28 PM PDT 24
Finished Jun 02 03:14:36 PM PDT 24
Peak memory 218468 kb
Host smart-512292c8-7120-4701-ad89-f60dbdd5f408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97895633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.97895633
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.3612847579
Short name T746
Test name
Test status
Simulation time 105629910 ps
CPU time 2.18 seconds
Started Jun 02 03:14:29 PM PDT 24
Finished Jun 02 03:14:32 PM PDT 24
Peak memory 218172 kb
Host smart-47b2d2f2-fe4f-4db1-b8d0-790a9ebb598e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612847579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.3612847579
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3552033674
Short name T495
Test name
Test status
Simulation time 171059562 ps
CPU time 23.09 seconds
Started Jun 02 03:14:32 PM PDT 24
Finished Jun 02 03:14:55 PM PDT 24
Peak memory 251356 kb
Host smart-61d1f706-5b36-4437-aa3f-c1bdda86438d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552033674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3552033674
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3357052364
Short name T296
Test name
Test status
Simulation time 486387873 ps
CPU time 8.29 seconds
Started Jun 02 03:14:30 PM PDT 24
Finished Jun 02 03:14:38 PM PDT 24
Peak memory 251328 kb
Host smart-555966ea-b65f-46b9-843e-157998371fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357052364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3357052364
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.78708192
Short name T847
Test name
Test status
Simulation time 14909518518 ps
CPU time 143.94 seconds
Started Jun 02 03:14:28 PM PDT 24
Finished Jun 02 03:16:53 PM PDT 24
Peak memory 273540 kb
Host smart-3414d37f-b6c0-4ebc-920e-b275d15dfbd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78708192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.lc_ctrl_stress_all.78708192
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.344099736
Short name T545
Test name
Test status
Simulation time 12840639 ps
CPU time 1.06 seconds
Started Jun 02 03:14:31 PM PDT 24
Finished Jun 02 03:14:32 PM PDT 24
Peak memory 211940 kb
Host smart-b0e7f129-1f30-4c53-89ec-b4541385a521
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344099736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.344099736
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.1872093820
Short name T65
Test name
Test status
Simulation time 12198313 ps
CPU time 0.87 seconds
Started Jun 02 03:14:35 PM PDT 24
Finished Jun 02 03:14:37 PM PDT 24
Peak memory 209940 kb
Host smart-cc9b7d30-45e4-47c6-9447-2620aa9749d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872093820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.1872093820
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1922719249
Short name T352
Test name
Test status
Simulation time 188803786 ps
CPU time 10.04 seconds
Started Jun 02 03:14:34 PM PDT 24
Finished Jun 02 03:14:44 PM PDT 24
Peak memory 218464 kb
Host smart-8beeacfd-e775-4e5c-af06-4246f4e077b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922719249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1922719249
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1095119297
Short name T466
Test name
Test status
Simulation time 268037657 ps
CPU time 4.06 seconds
Started Jun 02 03:14:33 PM PDT 24
Finished Jun 02 03:14:38 PM PDT 24
Peak memory 209928 kb
Host smart-33d56081-b214-422a-be62-d981112910f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095119297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1095119297
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3173451191
Short name T650
Test name
Test status
Simulation time 99046868 ps
CPU time 2.37 seconds
Started Jun 02 03:14:35 PM PDT 24
Finished Jun 02 03:14:38 PM PDT 24
Peak memory 218404 kb
Host smart-d389161f-71fc-4c9e-b031-9aecf5c80093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173451191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3173451191
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.2907402791
Short name T529
Test name
Test status
Simulation time 795724016 ps
CPU time 12.41 seconds
Started Jun 02 03:14:33 PM PDT 24
Finished Jun 02 03:14:46 PM PDT 24
Peak memory 219340 kb
Host smart-820ce5c3-bbb0-41b9-a150-e789ab8382b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907402791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.2907402791
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.4137461801
Short name T750
Test name
Test status
Simulation time 476585214 ps
CPU time 12.41 seconds
Started Jun 02 03:14:33 PM PDT 24
Finished Jun 02 03:14:46 PM PDT 24
Peak memory 225428 kb
Host smart-e0daf59c-ef6d-48ec-b77b-2dee510b465c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137461801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.4137461801
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1547829750
Short name T477
Test name
Test status
Simulation time 377523147 ps
CPU time 13.8 seconds
Started Jun 02 03:14:34 PM PDT 24
Finished Jun 02 03:14:48 PM PDT 24
Peak memory 226496 kb
Host smart-b6e4fb87-1707-4642-8694-e6329d233b45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547829750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1547829750
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.3582369388
Short name T471
Test name
Test status
Simulation time 485100026 ps
CPU time 8.81 seconds
Started Jun 02 03:14:32 PM PDT 24
Finished Jun 02 03:14:41 PM PDT 24
Peak memory 225088 kb
Host smart-80c08a6a-7248-479e-898d-8e0ccf120743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582369388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.3582369388
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.3912398141
Short name T317
Test name
Test status
Simulation time 87991408 ps
CPU time 3.4 seconds
Started Jun 02 03:14:33 PM PDT 24
Finished Jun 02 03:14:36 PM PDT 24
Peak memory 218112 kb
Host smart-d56f42af-4c23-464c-87d5-b6201d524aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912398141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.3912398141
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.4158361401
Short name T162
Test name
Test status
Simulation time 1532897771 ps
CPU time 27.63 seconds
Started Jun 02 03:14:34 PM PDT 24
Finished Jun 02 03:15:02 PM PDT 24
Peak memory 251272 kb
Host smart-4a763ae0-b939-4730-9d7c-d9644d8a7176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158361401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.4158361401
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.3758572205
Short name T741
Test name
Test status
Simulation time 257013607 ps
CPU time 3.76 seconds
Started Jun 02 03:14:33 PM PDT 24
Finished Jun 02 03:14:37 PM PDT 24
Peak memory 218416 kb
Host smart-a84c1107-c24e-4092-838b-7a30eae8a6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758572205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.3758572205
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.1145316602
Short name T801
Test name
Test status
Simulation time 2091819296 ps
CPU time 25.52 seconds
Started Jun 02 03:14:35 PM PDT 24
Finished Jun 02 03:15:01 PM PDT 24
Peak memory 244256 kb
Host smart-01b4f0b6-cb25-4c11-9c2c-e67586ff366e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145316602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.1145316602
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.2001187640
Short name T410
Test name
Test status
Simulation time 11945475 ps
CPU time 0.84 seconds
Started Jun 02 03:14:33 PM PDT 24
Finished Jun 02 03:14:34 PM PDT 24
Peak memory 211948 kb
Host smart-fbfec658-b1d5-4158-874d-418cfb61f482
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001187640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.2001187640
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.312159426
Short name T183
Test name
Test status
Simulation time 17726283 ps
CPU time 0.93 seconds
Started Jun 02 03:14:39 PM PDT 24
Finished Jun 02 03:14:40 PM PDT 24
Peak memory 209024 kb
Host smart-acd487e6-c8e1-43c4-8e12-24aced576c90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312159426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.312159426
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1348575546
Short name T297
Test name
Test status
Simulation time 987268477 ps
CPU time 15.26 seconds
Started Jun 02 03:14:33 PM PDT 24
Finished Jun 02 03:14:49 PM PDT 24
Peak memory 218404 kb
Host smart-4aebf34d-f33f-44e2-85ba-67158c20a0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348575546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1348575546
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.4098845554
Short name T310
Test name
Test status
Simulation time 2261479354 ps
CPU time 13.61 seconds
Started Jun 02 03:14:35 PM PDT 24
Finished Jun 02 03:14:49 PM PDT 24
Peak memory 217672 kb
Host smart-ec9295b4-0129-41f7-adea-988d7326ab63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098845554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.4098845554
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.938035833
Short name T856
Test name
Test status
Simulation time 163459694 ps
CPU time 2.93 seconds
Started Jun 02 03:14:35 PM PDT 24
Finished Jun 02 03:14:38 PM PDT 24
Peak memory 218468 kb
Host smart-5c1428c9-8a87-4fb0-9a59-d53ad90bc117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938035833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.938035833
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.1757695538
Short name T745
Test name
Test status
Simulation time 230173894 ps
CPU time 10.13 seconds
Started Jun 02 03:14:40 PM PDT 24
Finished Jun 02 03:14:51 PM PDT 24
Peak memory 218572 kb
Host smart-725d33e0-458b-4542-baf9-84b619f85e7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757695538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.1757695538
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3255367638
Short name T695
Test name
Test status
Simulation time 1218053649 ps
CPU time 11.07 seconds
Started Jun 02 03:14:39 PM PDT 24
Finished Jun 02 03:14:51 PM PDT 24
Peak memory 218444 kb
Host smart-8dbcd1fb-4d2b-45ce-8265-12db668cdcb2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255367638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3255367638
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.4233699140
Short name T868
Test name
Test status
Simulation time 342421694 ps
CPU time 9.8 seconds
Started Jun 02 03:14:37 PM PDT 24
Finished Jun 02 03:14:48 PM PDT 24
Peak memory 226516 kb
Host smart-15bf1a25-6330-4a3c-9dfd-aae8833d84ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233699140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
4233699140
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.1443244129
Short name T219
Test name
Test status
Simulation time 1073371045 ps
CPU time 7.54 seconds
Started Jun 02 03:14:34 PM PDT 24
Finished Jun 02 03:14:42 PM PDT 24
Peak memory 218464 kb
Host smart-ec96af1f-0cf6-4660-813d-bb065c82e6fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443244129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.1443244129
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.1698878016
Short name T75
Test name
Test status
Simulation time 412041459 ps
CPU time 6.11 seconds
Started Jun 02 03:14:35 PM PDT 24
Finished Jun 02 03:14:41 PM PDT 24
Peak memory 218092 kb
Host smart-39273212-def3-4527-a56d-4d0f4862349a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698878016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.1698878016
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2956793411
Short name T401
Test name
Test status
Simulation time 269670433 ps
CPU time 31.21 seconds
Started Jun 02 03:14:34 PM PDT 24
Finished Jun 02 03:15:06 PM PDT 24
Peak memory 251180 kb
Host smart-cd3e34bb-1131-4013-a6b2-55e780101338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956793411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2956793411
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.2631202001
Short name T411
Test name
Test status
Simulation time 51147178 ps
CPU time 6.45 seconds
Started Jun 02 03:14:36 PM PDT 24
Finished Jun 02 03:14:43 PM PDT 24
Peak memory 250896 kb
Host smart-6c2eeebf-bf98-48ec-a8e3-e85dcd01af44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631202001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.2631202001
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.1348021275
Short name T291
Test name
Test status
Simulation time 7294009461 ps
CPU time 227.46 seconds
Started Jun 02 03:14:38 PM PDT 24
Finished Jun 02 03:18:25 PM PDT 24
Peak memory 259584 kb
Host smart-34598e9f-a349-45c9-acfc-c7bab2aee440
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348021275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.1348021275
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.1658111736
Short name T42
Test name
Test status
Simulation time 73974162996 ps
CPU time 658.44 seconds
Started Jun 02 03:14:40 PM PDT 24
Finished Jun 02 03:25:39 PM PDT 24
Peak memory 325016 kb
Host smart-811c7a25-2bed-433c-a54d-e3bfdb6c0a01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1658111736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_stress_all_with_rand_reset.1658111736
Directory /workspace/38.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.3037119096
Short name T578
Test name
Test status
Simulation time 13821851 ps
CPU time 1.13 seconds
Started Jun 02 03:14:35 PM PDT 24
Finished Jun 02 03:14:37 PM PDT 24
Peak memory 211980 kb
Host smart-5225cad7-680e-49c7-ac49-ab91f395facb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037119096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.3037119096
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.4190110540
Short name T355
Test name
Test status
Simulation time 15119423 ps
CPU time 0.99 seconds
Started Jun 02 03:14:40 PM PDT 24
Finished Jun 02 03:14:42 PM PDT 24
Peak memory 209052 kb
Host smart-11d443aa-1a3e-4b05-9a3c-c81c0e93c853
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190110540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.4190110540
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.3320320399
Short name T22
Test name
Test status
Simulation time 249484031 ps
CPU time 12.4 seconds
Started Jun 02 03:14:39 PM PDT 24
Finished Jun 02 03:14:52 PM PDT 24
Peak memory 218400 kb
Host smart-93c29ef8-ebf3-4e11-a753-bfae4978bd21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320320399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.3320320399
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2696367908
Short name T618
Test name
Test status
Simulation time 433688927 ps
CPU time 2.75 seconds
Started Jun 02 03:14:43 PM PDT 24
Finished Jun 02 03:14:46 PM PDT 24
Peak memory 209840 kb
Host smart-652a0024-b166-4dd2-8e6b-60de6251a5f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696367908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2696367908
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.180188962
Short name T222
Test name
Test status
Simulation time 967725854 ps
CPU time 2.46 seconds
Started Jun 02 03:14:43 PM PDT 24
Finished Jun 02 03:14:46 PM PDT 24
Peak memory 218400 kb
Host smart-bd0c63aa-107c-44dc-995d-40e4871168b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180188962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.180188962
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2818391640
Short name T712
Test name
Test status
Simulation time 203708597 ps
CPU time 9.54 seconds
Started Jun 02 03:14:41 PM PDT 24
Finished Jun 02 03:14:51 PM PDT 24
Peak memory 218576 kb
Host smart-1e7f7a69-b252-4d94-9aca-754b71362f41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818391640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2818391640
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.2681891721
Short name T569
Test name
Test status
Simulation time 12653404570 ps
CPU time 17.86 seconds
Started Jun 02 03:14:41 PM PDT 24
Finished Jun 02 03:14:59 PM PDT 24
Peak memory 226528 kb
Host smart-054169f9-ae3a-4c9f-b52b-65cec014e2e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681891721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.2681891721
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2327150851
Short name T303
Test name
Test status
Simulation time 2120364076 ps
CPU time 12.04 seconds
Started Jun 02 03:14:38 PM PDT 24
Finished Jun 02 03:14:50 PM PDT 24
Peak memory 218420 kb
Host smart-c262a812-bed8-45e8-a809-d34d0ee0a4e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327150851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2327150851
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.192297608
Short name T817
Test name
Test status
Simulation time 4721834568 ps
CPU time 12.8 seconds
Started Jun 02 03:14:38 PM PDT 24
Finished Jun 02 03:14:51 PM PDT 24
Peak memory 218616 kb
Host smart-269457c9-4d49-4b80-9573-f95a6d8f9265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192297608 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.192297608
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2343531617
Short name T526
Test name
Test status
Simulation time 46670528 ps
CPU time 1.78 seconds
Started Jun 02 03:14:37 PM PDT 24
Finished Jun 02 03:14:39 PM PDT 24
Peak memory 214516 kb
Host smart-61fa2251-317e-4ede-8a02-36b23ff58eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2343531617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2343531617
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3216097965
Short name T742
Test name
Test status
Simulation time 336133081 ps
CPU time 30.9 seconds
Started Jun 02 03:14:40 PM PDT 24
Finished Jun 02 03:15:11 PM PDT 24
Peak memory 247748 kb
Host smart-5a01c920-f71f-45b2-af0c-f6e1edae8731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216097965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3216097965
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.4115691751
Short name T227
Test name
Test status
Simulation time 74136598 ps
CPU time 7.24 seconds
Started Jun 02 03:14:38 PM PDT 24
Finished Jun 02 03:14:46 PM PDT 24
Peak memory 250844 kb
Host smart-efca52bd-fe82-4bfe-b0e1-7d3a818b9b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115691751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.4115691751
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.2085355415
Short name T250
Test name
Test status
Simulation time 45381792 ps
CPU time 0.93 seconds
Started Jun 02 03:14:36 PM PDT 24
Finished Jun 02 03:14:38 PM PDT 24
Peak memory 213008 kb
Host smart-6c8ae963-b055-4a02-83c8-9e43231256f9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085355415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.2085355415
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.1807348546
Short name T232
Test name
Test status
Simulation time 160670797 ps
CPU time 1.18 seconds
Started Jun 02 03:12:30 PM PDT 24
Finished Jun 02 03:12:31 PM PDT 24
Peak memory 209100 kb
Host smart-4d5ae69c-1cd3-4be7-b91e-255dfd53a587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807348546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.1807348546
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.3961647292
Short name T791
Test name
Test status
Simulation time 16727745 ps
CPU time 0.87 seconds
Started Jun 02 03:12:26 PM PDT 24
Finished Jun 02 03:12:27 PM PDT 24
Peak memory 209064 kb
Host smart-75fdfc6a-3192-4ec0-9f30-ebc475596db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961647292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.3961647292
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.1377837295
Short name T167
Test name
Test status
Simulation time 843961784 ps
CPU time 25.25 seconds
Started Jun 02 03:12:24 PM PDT 24
Finished Jun 02 03:12:50 PM PDT 24
Peak memory 218468 kb
Host smart-0c1987c5-8c51-467d-bc6b-5d16a4300793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377837295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.1377837295
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3744665193
Short name T304
Test name
Test status
Simulation time 4219130315 ps
CPU time 7.63 seconds
Started Jun 02 03:12:23 PM PDT 24
Finished Jun 02 03:12:32 PM PDT 24
Peak memory 210000 kb
Host smart-031d94aa-b7ef-440a-95a9-97f403731664
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744665193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3744665193
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.556789879
Short name T382
Test name
Test status
Simulation time 2442106607 ps
CPU time 32.37 seconds
Started Jun 02 03:12:22 PM PDT 24
Finished Jun 02 03:12:55 PM PDT 24
Peak memory 219292 kb
Host smart-e58fcf8f-bbb4-4e93-88e7-d0bfc0d21734
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556789879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.556789879
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1596989255
Short name T433
Test name
Test status
Simulation time 1032373770 ps
CPU time 6.27 seconds
Started Jun 02 03:12:24 PM PDT 24
Finished Jun 02 03:12:31 PM PDT 24
Peak memory 218104 kb
Host smart-e7d2973d-7ca0-466a-af56-038b74e05e1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596989255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
596989255
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.2786087655
Short name T649
Test name
Test status
Simulation time 967065689 ps
CPU time 4.7 seconds
Started Jun 02 03:12:23 PM PDT 24
Finished Jun 02 03:12:29 PM PDT 24
Peak memory 218324 kb
Host smart-0c616285-3b87-4b6f-990a-3920935ab349
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786087655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.2786087655
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.241719046
Short name T452
Test name
Test status
Simulation time 1396340206 ps
CPU time 7.06 seconds
Started Jun 02 03:12:31 PM PDT 24
Finished Jun 02 03:12:39 PM PDT 24
Peak memory 218040 kb
Host smart-1e8d307d-3433-4af5-905d-08a105bad0cd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241719046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.241719046
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.738957063
Short name T489
Test name
Test status
Simulation time 5254485526 ps
CPU time 10.04 seconds
Started Jun 02 03:12:23 PM PDT 24
Finished Jun 02 03:12:34 PM PDT 24
Peak memory 218064 kb
Host smart-9f3b3c31-5d01-4f85-a021-099db16bbe1d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738957063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.738957063
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3704467212
Short name T766
Test name
Test status
Simulation time 7608665917 ps
CPU time 68.98 seconds
Started Jun 02 03:12:24 PM PDT 24
Finished Jun 02 03:13:34 PM PDT 24
Peak memory 284016 kb
Host smart-41d9850f-acdf-4835-88fb-a530851ae98a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704467212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3704467212
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.3236306529
Short name T786
Test name
Test status
Simulation time 2660551331 ps
CPU time 13.19 seconds
Started Jun 02 03:12:23 PM PDT 24
Finished Jun 02 03:12:37 PM PDT 24
Peak memory 251324 kb
Host smart-2159f388-7ae8-49da-9d5d-b2dd72c382c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236306529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.3236306529
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3680616390
Short name T150
Test name
Test status
Simulation time 212161469 ps
CPU time 3.45 seconds
Started Jun 02 03:12:24 PM PDT 24
Finished Jun 02 03:12:28 PM PDT 24
Peak memory 218360 kb
Host smart-18aaa9c9-b830-4550-93c5-360450e246de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680616390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3680616390
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.4086630954
Short name T55
Test name
Test status
Simulation time 295121237 ps
CPU time 18.94 seconds
Started Jun 02 03:12:27 PM PDT 24
Finished Jun 02 03:12:47 PM PDT 24
Peak memory 214256 kb
Host smart-bd7d7013-8699-4224-8329-e13471c3f855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086630954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.4086630954
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3528418675
Short name T47
Test name
Test status
Simulation time 216518514 ps
CPU time 36.95 seconds
Started Jun 02 03:12:30 PM PDT 24
Finished Jun 02 03:13:08 PM PDT 24
Peak memory 269232 kb
Host smart-dc8a372d-1b4e-4459-afb9-fa5d7ce1777b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3528418675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3528418675
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2472272809
Short name T169
Test name
Test status
Simulation time 2908047874 ps
CPU time 7.65 seconds
Started Jun 02 03:12:29 PM PDT 24
Finished Jun 02 03:12:37 PM PDT 24
Peak memory 218612 kb
Host smart-9ea17e3c-ded3-4f67-8a52-b5a2a27c6a2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472272809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2472272809
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1332602822
Short name T254
Test name
Test status
Simulation time 1701221807 ps
CPU time 16.78 seconds
Started Jun 02 03:12:30 PM PDT 24
Finished Jun 02 03:12:47 PM PDT 24
Peak memory 226520 kb
Host smart-aa700bea-fd80-4912-b768-d85e5c88d147
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332602822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1332602822
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.1939937884
Short name T266
Test name
Test status
Simulation time 277482662 ps
CPU time 6.86 seconds
Started Jun 02 03:12:28 PM PDT 24
Finished Jun 02 03:12:35 PM PDT 24
Peak memory 225528 kb
Host smart-5eed3e02-3d8b-4608-94d4-86d4c8496903
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939937884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.1
939937884
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.695390031
Short name T35
Test name
Test status
Simulation time 222410108 ps
CPU time 10.26 seconds
Started Jun 02 03:12:26 PM PDT 24
Finished Jun 02 03:12:36 PM PDT 24
Peak memory 226504 kb
Host smart-bb072f89-ae5f-400d-b11a-f70fcd70b47a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695390031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.695390031
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.523671115
Short name T73
Test name
Test status
Simulation time 1053985904 ps
CPU time 2.93 seconds
Started Jun 02 03:12:30 PM PDT 24
Finished Jun 02 03:12:34 PM PDT 24
Peak memory 214648 kb
Host smart-e73f03b9-f4b7-4be8-bd78-daee9c4acdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523671115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.523671115
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3373484298
Short name T763
Test name
Test status
Simulation time 1603665432 ps
CPU time 22.82 seconds
Started Jun 02 03:12:27 PM PDT 24
Finished Jun 02 03:12:51 PM PDT 24
Peak memory 251284 kb
Host smart-d5bd301c-81fb-49ec-980a-dbf04f03be15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373484298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3373484298
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1208300695
Short name T453
Test name
Test status
Simulation time 104825366 ps
CPU time 8.86 seconds
Started Jun 02 03:12:30 PM PDT 24
Finished Jun 02 03:12:40 PM PDT 24
Peak memory 251264 kb
Host smart-a53bd1d2-b869-48ee-b774-d13968da4f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208300695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1208300695
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.787101817
Short name T538
Test name
Test status
Simulation time 1229507832 ps
CPU time 61.77 seconds
Started Jun 02 03:12:29 PM PDT 24
Finished Jun 02 03:13:31 PM PDT 24
Peak memory 267124 kb
Host smart-6a6a6690-87c3-47dd-8c31-b5ffd1b55b7a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787101817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.787101817
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.2380936697
Short name T66
Test name
Test status
Simulation time 121631788146 ps
CPU time 1002.94 seconds
Started Jun 02 03:12:29 PM PDT 24
Finished Jun 02 03:29:13 PM PDT 24
Peak memory 320824 kb
Host smart-9e9bfcfd-7a69-4c0b-a85f-68ed77a76feb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2380936697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_stress_all_with_rand_reset.2380936697
Directory /workspace/4.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.1180998640
Short name T491
Test name
Test status
Simulation time 21941815 ps
CPU time 0.85 seconds
Started Jun 02 03:12:26 PM PDT 24
Finished Jun 02 03:12:27 PM PDT 24
Peak memory 212064 kb
Host smart-dc026ec9-c073-45db-882d-1c38c0ffa3a0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180998640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.1180998640
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3644108145
Short name T698
Test name
Test status
Simulation time 13590069 ps
CPU time 0.81 seconds
Started Jun 02 03:14:44 PM PDT 24
Finished Jun 02 03:14:45 PM PDT 24
Peak memory 208912 kb
Host smart-7a8bd92f-122c-4e58-921b-6a5c561397b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644108145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3644108145
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.1264017218
Short name T366
Test name
Test status
Simulation time 356195030 ps
CPU time 15.42 seconds
Started Jun 02 03:14:44 PM PDT 24
Finished Jun 02 03:15:00 PM PDT 24
Peak memory 218472 kb
Host smart-8dc868d9-8d77-4ac2-9837-b8821de730af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264017218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.1264017218
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2945433000
Short name T721
Test name
Test status
Simulation time 1161711014 ps
CPU time 4.93 seconds
Started Jun 02 03:14:42 PM PDT 24
Finished Jun 02 03:14:48 PM PDT 24
Peak memory 209864 kb
Host smart-57b9ce89-07ef-46cb-8237-8d0238fe3ab3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945433000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2945433000
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.3006354055
Short name T354
Test name
Test status
Simulation time 52160927 ps
CPU time 2.38 seconds
Started Jun 02 03:14:47 PM PDT 24
Finished Jun 02 03:14:50 PM PDT 24
Peak memory 218496 kb
Host smart-ad03573c-15f5-4e34-9a75-c41fe1b2c096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006354055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.3006354055
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2481405486
Short name T513
Test name
Test status
Simulation time 1215670485 ps
CPU time 14.09 seconds
Started Jun 02 03:14:45 PM PDT 24
Finished Jun 02 03:15:00 PM PDT 24
Peak memory 226472 kb
Host smart-bb84180a-5dc1-4469-8504-831b2e2718cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481405486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2481405486
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.2748646537
Short name T333
Test name
Test status
Simulation time 775741040 ps
CPU time 13.91 seconds
Started Jun 02 03:14:45 PM PDT 24
Finished Jun 02 03:14:59 PM PDT 24
Peak memory 226492 kb
Host smart-696d2dfc-355a-4e41-a7b1-ff49a700aadc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748646537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.2748646537
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.493529328
Short name T272
Test name
Test status
Simulation time 853919208 ps
CPU time 15.94 seconds
Started Jun 02 03:14:43 PM PDT 24
Finished Jun 02 03:15:00 PM PDT 24
Peak memory 225336 kb
Host smart-e85fb4e5-c4f1-4b2f-8999-93934251e833
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493529328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.493529328
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1220223610
Short name T675
Test name
Test status
Simulation time 961679464 ps
CPU time 7.15 seconds
Started Jun 02 03:14:46 PM PDT 24
Finished Jun 02 03:14:53 PM PDT 24
Peak memory 224808 kb
Host smart-9daa3b36-46b8-498b-832c-84dd1f75fa40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220223610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1220223610
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.630810339
Short name T563
Test name
Test status
Simulation time 130434481 ps
CPU time 1.98 seconds
Started Jun 02 03:14:42 PM PDT 24
Finished Jun 02 03:14:45 PM PDT 24
Peak memory 214308 kb
Host smart-5c525cff-da26-408b-9200-eced9ec68e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630810339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.630810339
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1075382816
Short name T340
Test name
Test status
Simulation time 161300895 ps
CPU time 19.83 seconds
Started Jun 02 03:14:43 PM PDT 24
Finished Jun 02 03:15:04 PM PDT 24
Peak memory 251328 kb
Host smart-436604b4-2161-4ee6-8cc3-3b34074b056e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075382816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1075382816
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.4191248677
Short name T829
Test name
Test status
Simulation time 314620177 ps
CPU time 8.58 seconds
Started Jun 02 03:14:43 PM PDT 24
Finished Jun 02 03:14:52 PM PDT 24
Peak memory 251240 kb
Host smart-f0d45704-0fc8-44ad-822b-990ccc988133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191248677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.4191248677
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.3060071546
Short name T494
Test name
Test status
Simulation time 53588589753 ps
CPU time 280.74 seconds
Started Jun 02 03:14:43 PM PDT 24
Finished Jun 02 03:19:25 PM PDT 24
Peak memory 273996 kb
Host smart-44d5f060-90a5-46af-b930-510efad2110f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060071546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.3060071546
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.774202609
Short name T141
Test name
Test status
Simulation time 121207682788 ps
CPU time 607.81 seconds
Started Jun 02 03:14:46 PM PDT 24
Finished Jun 02 03:24:54 PM PDT 24
Peak memory 497232 kb
Host smart-1329fd3c-5297-44d2-9e2c-32af923e0b91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=774202609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.774202609
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.500634577
Short name T614
Test name
Test status
Simulation time 20802747 ps
CPU time 0.86 seconds
Started Jun 02 03:14:46 PM PDT 24
Finished Jun 02 03:14:48 PM PDT 24
Peak memory 211948 kb
Host smart-72b1168d-d834-4543-87b6-c5ef7e5fd6b2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500634577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ct
rl_volatile_unlock_smoke.500634577
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.3863420376
Short name T63
Test name
Test status
Simulation time 60098523 ps
CPU time 0.93 seconds
Started Jun 02 03:14:50 PM PDT 24
Finished Jun 02 03:14:51 PM PDT 24
Peak memory 209916 kb
Host smart-4743e36f-0909-4815-a9f9-26c246479eed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863420376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.3863420376
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2320733892
Short name T627
Test name
Test status
Simulation time 805316856 ps
CPU time 10.27 seconds
Started Jun 02 03:14:45 PM PDT 24
Finished Jun 02 03:14:55 PM PDT 24
Peak memory 218408 kb
Host smart-4636bc83-8606-47ee-9bc4-a42a8f17ac9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320733892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2320733892
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.3696029883
Short name T851
Test name
Test status
Simulation time 566265083 ps
CPU time 3.99 seconds
Started Jun 02 03:14:42 PM PDT 24
Finished Jun 02 03:14:47 PM PDT 24
Peak memory 209932 kb
Host smart-a952b033-dc30-4ce0-849e-8b3b3b31ca71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696029883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.3696029883
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2013306876
Short name T349
Test name
Test status
Simulation time 54922022 ps
CPU time 2.5 seconds
Started Jun 02 03:14:53 PM PDT 24
Finished Jun 02 03:14:57 PM PDT 24
Peak memory 218252 kb
Host smart-f1d9e941-0a80-4704-ab20-32d82cc2f7d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013306876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2013306876
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1065789048
Short name T571
Test name
Test status
Simulation time 249610244 ps
CPU time 8.44 seconds
Started Jun 02 03:14:42 PM PDT 24
Finished Jun 02 03:14:51 PM PDT 24
Peak memory 219360 kb
Host smart-f1314901-fe4e-4625-a119-83723d23ba44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065789048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1065789048
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1165995492
Short name T800
Test name
Test status
Simulation time 374804177 ps
CPU time 8.99 seconds
Started Jun 02 03:14:53 PM PDT 24
Finished Jun 02 03:15:03 PM PDT 24
Peak memory 225224 kb
Host smart-8e69fc10-da52-4007-8ae6-bb5091fa78f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165995492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1165995492
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.1705988440
Short name T842
Test name
Test status
Simulation time 3135722167 ps
CPU time 20.53 seconds
Started Jun 02 03:14:44 PM PDT 24
Finished Jun 02 03:15:05 PM PDT 24
Peak memory 226536 kb
Host smart-1a60010a-a682-45bf-9183-ee9f07a8b0f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705988440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
1705988440
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.1016240485
Short name T831
Test name
Test status
Simulation time 238775532 ps
CPU time 7.51 seconds
Started Jun 02 03:14:43 PM PDT 24
Finished Jun 02 03:14:51 PM PDT 24
Peak memory 224824 kb
Host smart-4c2e6831-ecab-403b-bc34-34df40397ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016240485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.1016240485
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1932169133
Short name T76
Test name
Test status
Simulation time 336174804 ps
CPU time 6.77 seconds
Started Jun 02 03:14:46 PM PDT 24
Finished Jun 02 03:14:53 PM PDT 24
Peak memory 218096 kb
Host smart-98599a2b-d367-455d-868a-a706057e6810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932169133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1932169133
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.972081307
Short name T686
Test name
Test status
Simulation time 929442225 ps
CPU time 25.65 seconds
Started Jun 02 03:14:43 PM PDT 24
Finished Jun 02 03:15:09 PM PDT 24
Peak memory 251324 kb
Host smart-3c46c7e9-f0ea-45ca-96d2-ed00f8858894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972081307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.972081307
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3393488129
Short name T807
Test name
Test status
Simulation time 242429101 ps
CPU time 6.3 seconds
Started Jun 02 03:14:43 PM PDT 24
Finished Jun 02 03:14:50 PM PDT 24
Peak memory 247144 kb
Host smart-94b7d47a-11cb-487f-914d-3bbe61931f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393488129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3393488129
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1300756306
Short name T863
Test name
Test status
Simulation time 23119246081 ps
CPU time 195.59 seconds
Started Jun 02 03:14:53 PM PDT 24
Finished Jun 02 03:18:10 PM PDT 24
Peak memory 283976 kb
Host smart-934627dc-3245-4e8b-b98e-3eff18f97015
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300756306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1300756306
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.3135846521
Short name T101
Test name
Test status
Simulation time 19800573567 ps
CPU time 604.74 seconds
Started Jun 02 03:14:47 PM PDT 24
Finished Jun 02 03:24:53 PM PDT 24
Peak memory 283564 kb
Host smart-b1d13de5-b57b-4ea3-a988-85cc77393d10
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3135846521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.3135846521
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1415500331
Short name T393
Test name
Test status
Simulation time 25066527 ps
CPU time 1.05 seconds
Started Jun 02 03:14:53 PM PDT 24
Finished Jun 02 03:14:55 PM PDT 24
Peak memory 211884 kb
Host smart-23c5f63c-9c57-472f-a84b-52fb3a25d171
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415500331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1415500331
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1720598348
Short name T679
Test name
Test status
Simulation time 82055369 ps
CPU time 1.26 seconds
Started Jun 02 03:14:47 PM PDT 24
Finished Jun 02 03:14:49 PM PDT 24
Peak memory 209296 kb
Host smart-b7d0cd47-b899-4f64-98dd-5b7316e90a18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720598348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1720598348
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3865585435
Short name T685
Test name
Test status
Simulation time 1133778436 ps
CPU time 11.03 seconds
Started Jun 02 03:14:48 PM PDT 24
Finished Jun 02 03:14:59 PM PDT 24
Peak memory 218556 kb
Host smart-2747dd31-4c75-4d5b-ab1f-770d06b54265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865585435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3865585435
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1733799022
Short name T613
Test name
Test status
Simulation time 308692176 ps
CPU time 4.61 seconds
Started Jun 02 03:14:49 PM PDT 24
Finished Jun 02 03:14:54 PM PDT 24
Peak memory 217312 kb
Host smart-d6425cbd-f1c3-4f51-ab0b-6b08c77e3d00
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733799022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1733799022
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.2123368492
Short name T99
Test name
Test status
Simulation time 237908687 ps
CPU time 2.79 seconds
Started Jun 02 03:14:48 PM PDT 24
Finished Jun 02 03:14:51 PM PDT 24
Peak memory 218464 kb
Host smart-7622315a-29a3-4b78-9b47-d3806dd3fc8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123368492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.2123368492
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.2874281133
Short name T608
Test name
Test status
Simulation time 504131370 ps
CPU time 15.12 seconds
Started Jun 02 03:14:51 PM PDT 24
Finished Jun 02 03:15:06 PM PDT 24
Peak memory 226500 kb
Host smart-456354fb-1184-4134-9347-ed2c3f8a037c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874281133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2874281133
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2718572214
Short name T532
Test name
Test status
Simulation time 1886063531 ps
CPU time 13.32 seconds
Started Jun 02 03:14:49 PM PDT 24
Finished Jun 02 03:15:03 PM PDT 24
Peak memory 226492 kb
Host smart-0ca9882f-d641-425f-aadb-f841f16ee0d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718572214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2718572214
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3732916757
Short name T865
Test name
Test status
Simulation time 1531376649 ps
CPU time 14.66 seconds
Started Jun 02 03:14:49 PM PDT 24
Finished Jun 02 03:15:04 PM PDT 24
Peak memory 218496 kb
Host smart-6a2b00b9-e19b-4376-989d-09292ba2c22e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732916757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3732916757
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2171145755
Short name T62
Test name
Test status
Simulation time 228816226 ps
CPU time 2.12 seconds
Started Jun 02 03:14:49 PM PDT 24
Finished Jun 02 03:14:52 PM PDT 24
Peak memory 214552 kb
Host smart-1e3997a5-3e66-4828-a0f5-3ad1e87e8255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171145755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2171145755
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.382910831
Short name T368
Test name
Test status
Simulation time 843546108 ps
CPU time 25.79 seconds
Started Jun 02 03:14:51 PM PDT 24
Finished Jun 02 03:15:17 PM PDT 24
Peak memory 251336 kb
Host smart-aea6e839-fbb7-4eab-85d8-a750befc6212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382910831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.382910831
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.1245384562
Short name T142
Test name
Test status
Simulation time 68075625 ps
CPU time 7.67 seconds
Started Jun 02 03:14:50 PM PDT 24
Finished Jun 02 03:14:58 PM PDT 24
Peak memory 251248 kb
Host smart-e6479d85-87eb-4958-a5c2-74a8749d4dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245384562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.1245384562
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2497927885
Short name T269
Test name
Test status
Simulation time 7491024619 ps
CPU time 179 seconds
Started Jun 02 03:14:50 PM PDT 24
Finished Jun 02 03:17:49 PM PDT 24
Peak memory 284108 kb
Host smart-7a4919f3-ff6b-4f68-8aca-3c1d6c774113
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497927885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2497927885
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.2664799490
Short name T214
Test name
Test status
Simulation time 13338477 ps
CPU time 1.06 seconds
Started Jun 02 03:14:50 PM PDT 24
Finished Jun 02 03:14:52 PM PDT 24
Peak memory 211940 kb
Host smart-bf6cc33f-367b-4289-a063-20f077551634
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664799490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.2664799490
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2217452535
Short name T680
Test name
Test status
Simulation time 17921380 ps
CPU time 0.88 seconds
Started Jun 02 03:14:54 PM PDT 24
Finished Jun 02 03:14:56 PM PDT 24
Peak memory 209076 kb
Host smart-f1334c1e-d796-4157-bfad-0845e45b3e36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217452535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2217452535
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.3810534402
Short name T387
Test name
Test status
Simulation time 344698671 ps
CPU time 7.54 seconds
Started Jun 02 03:14:47 PM PDT 24
Finished Jun 02 03:14:55 PM PDT 24
Peak memory 218424 kb
Host smart-21b9cd2c-89aa-4244-a4f8-83c9c964ceb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810534402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.3810534402
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3301198763
Short name T33
Test name
Test status
Simulation time 340169076 ps
CPU time 5.1 seconds
Started Jun 02 03:14:51 PM PDT 24
Finished Jun 02 03:14:56 PM PDT 24
Peak memory 217308 kb
Host smart-0c1e2bc9-4e32-47e9-8ccd-6439b374db19
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301198763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3301198763
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1716437602
Short name T337
Test name
Test status
Simulation time 104426231 ps
CPU time 3.41 seconds
Started Jun 02 03:14:51 PM PDT 24
Finished Jun 02 03:14:55 PM PDT 24
Peak memory 218412 kb
Host smart-05af37e1-9611-4de6-ac82-413969ca92e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716437602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1716437602
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.617960219
Short name T23
Test name
Test status
Simulation time 338427307 ps
CPU time 11.08 seconds
Started Jun 02 03:14:50 PM PDT 24
Finished Jun 02 03:15:01 PM PDT 24
Peak memory 219308 kb
Host smart-9e14e45b-790b-4553-b139-5910a529dd9a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617960219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.617960219
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3047601091
Short name T515
Test name
Test status
Simulation time 768842890 ps
CPU time 11.36 seconds
Started Jun 02 03:14:52 PM PDT 24
Finished Jun 02 03:15:04 PM PDT 24
Peak memory 226560 kb
Host smart-7ddb3865-1e17-4f44-8b30-efde96726831
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047601091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3047601091
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1523934772
Short name T422
Test name
Test status
Simulation time 1252040402 ps
CPU time 12.24 seconds
Started Jun 02 03:14:55 PM PDT 24
Finished Jun 02 03:15:08 PM PDT 24
Peak memory 226500 kb
Host smart-94f93208-cc30-425f-85ef-ca9642b7b00d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523934772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1523934772
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1423298409
Short name T181
Test name
Test status
Simulation time 963339840 ps
CPU time 9.64 seconds
Started Jun 02 03:14:49 PM PDT 24
Finished Jun 02 03:14:59 PM PDT 24
Peak memory 226516 kb
Host smart-0bf308fc-b5c6-4c96-8422-4852a5c100d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423298409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1423298409
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.635411673
Short name T805
Test name
Test status
Simulation time 43534951 ps
CPU time 1.1 seconds
Started Jun 02 03:14:48 PM PDT 24
Finished Jun 02 03:14:49 PM PDT 24
Peak memory 213676 kb
Host smart-942f3368-98b2-4935-8d43-35821e71d02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635411673 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.635411673
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.1004050411
Short name T90
Test name
Test status
Simulation time 541191789 ps
CPU time 21.9 seconds
Started Jun 02 03:14:47 PM PDT 24
Finished Jun 02 03:15:09 PM PDT 24
Peak memory 251404 kb
Host smart-dba3abb4-a05f-4915-bc65-7f6545fdf3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004050411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.1004050411
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.3675576917
Short name T671
Test name
Test status
Simulation time 97602651 ps
CPU time 4.63 seconds
Started Jun 02 03:14:47 PM PDT 24
Finished Jun 02 03:14:53 PM PDT 24
Peak memory 223016 kb
Host smart-e88beaa7-443a-4bac-a136-d6874d9819f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675576917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.3675576917
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.1364935336
Short name T615
Test name
Test status
Simulation time 7615492226 ps
CPU time 30.57 seconds
Started Jun 02 03:14:55 PM PDT 24
Finished Jun 02 03:15:26 PM PDT 24
Peak memory 246952 kb
Host smart-d0d6223e-f2fe-44da-8f4f-92b959bbfa43
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364935336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.1364935336
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.1884364946
Short name T806
Test name
Test status
Simulation time 61522216 ps
CPU time 0.88 seconds
Started Jun 02 03:14:49 PM PDT 24
Finished Jun 02 03:14:51 PM PDT 24
Peak memory 213132 kb
Host smart-7f4f23f6-4ff1-4ea5-8e07-0f79a4739e77
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884364946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.1884364946
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.4029236432
Short name T446
Test name
Test status
Simulation time 68216590 ps
CPU time 1.02 seconds
Started Jun 02 03:14:53 PM PDT 24
Finished Jun 02 03:14:54 PM PDT 24
Peak memory 209184 kb
Host smart-43d879fb-e5b6-4347-bff1-af441117422a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029236432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.4029236432
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.1522328431
Short name T246
Test name
Test status
Simulation time 2020367870 ps
CPU time 9.17 seconds
Started Jun 02 03:14:54 PM PDT 24
Finished Jun 02 03:15:04 PM PDT 24
Peak memory 218496 kb
Host smart-d8730fde-7d63-4e20-afb1-435dfbbcf278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522328431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.1522328431
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.44334953
Short name T480
Test name
Test status
Simulation time 822426466 ps
CPU time 6.26 seconds
Started Jun 02 03:14:53 PM PDT 24
Finished Jun 02 03:15:00 PM PDT 24
Peak memory 209904 kb
Host smart-305d359f-2ddc-432a-b897-d96bdce84bde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44334953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.44334953
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.395323590
Short name T548
Test name
Test status
Simulation time 73349459 ps
CPU time 2.08 seconds
Started Jun 02 03:14:52 PM PDT 24
Finished Jun 02 03:14:55 PM PDT 24
Peak memory 218492 kb
Host smart-562669a2-9888-492a-9e7f-9882d1572906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395323590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.395323590
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.2250243719
Short name T527
Test name
Test status
Simulation time 692720022 ps
CPU time 28.33 seconds
Started Jun 02 03:14:56 PM PDT 24
Finished Jun 02 03:15:25 PM PDT 24
Peak memory 226464 kb
Host smart-34ce62d6-2388-4773-9af1-f14f5c4095ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250243719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.2250243719
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1005560392
Short name T348
Test name
Test status
Simulation time 502109248 ps
CPU time 8.48 seconds
Started Jun 02 03:14:55 PM PDT 24
Finished Jun 02 03:15:04 PM PDT 24
Peak memory 225252 kb
Host smart-3a876b22-c973-486b-9ee6-f1b5f359407e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005560392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1005560392
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.4241483596
Short name T616
Test name
Test status
Simulation time 1230591636 ps
CPU time 8.48 seconds
Started Jun 02 03:14:56 PM PDT 24
Finished Jun 02 03:15:05 PM PDT 24
Peak memory 226488 kb
Host smart-dff00463-6267-497c-91b9-53d5d635e229
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241483596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
4241483596
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.484219038
Short name T784
Test name
Test status
Simulation time 514493204 ps
CPU time 10.69 seconds
Started Jun 02 03:14:51 PM PDT 24
Finished Jun 02 03:15:03 PM PDT 24
Peak memory 218468 kb
Host smart-a6ba152b-4445-4920-bb11-5e4e9004b16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484219038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.484219038
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.1872332008
Short name T64
Test name
Test status
Simulation time 124963027 ps
CPU time 2.4 seconds
Started Jun 02 03:14:54 PM PDT 24
Finished Jun 02 03:14:57 PM PDT 24
Peak memory 214744 kb
Host smart-33a10e27-c0f8-4e88-83d6-8c989877d03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872332008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.1872332008
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.1940733604
Short name T738
Test name
Test status
Simulation time 906995631 ps
CPU time 27.24 seconds
Started Jun 02 03:14:56 PM PDT 24
Finished Jun 02 03:15:24 PM PDT 24
Peak memory 251240 kb
Host smart-b3e6a74e-5374-4898-8914-ccc998c98e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940733604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.1940733604
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3378812449
Short name T448
Test name
Test status
Simulation time 470006498 ps
CPU time 7.59 seconds
Started Jun 02 03:14:55 PM PDT 24
Finished Jun 02 03:15:04 PM PDT 24
Peak memory 251060 kb
Host smart-29bf82bc-5267-42d9-aa70-417ab456ff59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378812449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3378812449
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.4276119407
Short name T743
Test name
Test status
Simulation time 5435109227 ps
CPU time 148.69 seconds
Started Jun 02 03:14:56 PM PDT 24
Finished Jun 02 03:17:25 PM PDT 24
Peak memory 284128 kb
Host smart-85bc25f4-2875-4f52-9798-bd215728b529
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276119407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.4276119407
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.274792839
Short name T20
Test name
Test status
Simulation time 14854101 ps
CPU time 0.95 seconds
Started Jun 02 03:14:54 PM PDT 24
Finished Jun 02 03:14:56 PM PDT 24
Peak memory 212000 kb
Host smart-39b84fc1-0fd7-4bef-a565-8d2bf1eeceaf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274792839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.274792839
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3024914983
Short name T392
Test name
Test status
Simulation time 120439364 ps
CPU time 0.82 seconds
Started Jun 02 03:14:58 PM PDT 24
Finished Jun 02 03:14:59 PM PDT 24
Peak memory 208964 kb
Host smart-2fdb5173-8fc1-4a4d-b227-a2f32dc178d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024914983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3024914983
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.3404530591
Short name T705
Test name
Test status
Simulation time 1653703212 ps
CPU time 15.75 seconds
Started Jun 02 03:14:53 PM PDT 24
Finished Jun 02 03:15:10 PM PDT 24
Peak memory 218396 kb
Host smart-63d732ef-7680-4a46-9e39-1d857fd72e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404530591 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.3404530591
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.3885862889
Short name T836
Test name
Test status
Simulation time 1826258504 ps
CPU time 2.6 seconds
Started Jun 02 03:14:51 PM PDT 24
Finished Jun 02 03:14:55 PM PDT 24
Peak memory 209872 kb
Host smart-feff9c45-1fdf-4ec6-bb12-766f71239075
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885862889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.3885862889
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2046562373
Short name T664
Test name
Test status
Simulation time 134988588 ps
CPU time 3.51 seconds
Started Jun 02 03:14:58 PM PDT 24
Finished Jun 02 03:15:02 PM PDT 24
Peak memory 218460 kb
Host smart-dfe03f80-51b0-4a08-90be-04679a61efe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046562373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2046562373
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1204424873
Short name T606
Test name
Test status
Simulation time 210264373 ps
CPU time 9.03 seconds
Started Jun 02 03:14:58 PM PDT 24
Finished Jun 02 03:15:07 PM PDT 24
Peak memory 218552 kb
Host smart-7ee24e0a-5b8e-47b9-b577-d5b272ed1924
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204424873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1204424873
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2050784580
Short name T292
Test name
Test status
Simulation time 537381265 ps
CPU time 12.12 seconds
Started Jun 02 03:15:01 PM PDT 24
Finished Jun 02 03:15:14 PM PDT 24
Peak memory 226404 kb
Host smart-501fa71a-ffd8-4ed0-ae6e-dbcc8e9ab0be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050784580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2050784580
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.2650476632
Short name T771
Test name
Test status
Simulation time 1329570503 ps
CPU time 12.53 seconds
Started Jun 02 03:15:00 PM PDT 24
Finished Jun 02 03:15:13 PM PDT 24
Peak memory 225376 kb
Host smart-41e563ef-d89b-4a75-86c7-2d95ef8f7af8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650476632 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
2650476632
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1879166794
Short name T502
Test name
Test status
Simulation time 1759738288 ps
CPU time 11.53 seconds
Started Jun 02 03:14:54 PM PDT 24
Finished Jun 02 03:15:06 PM PDT 24
Peak memory 226500 kb
Host smart-87f93799-793f-4bfd-b7ad-d10c6a302a06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879166794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1879166794
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.2104143998
Short name T810
Test name
Test status
Simulation time 25194453 ps
CPU time 1.46 seconds
Started Jun 02 03:14:52 PM PDT 24
Finished Jun 02 03:14:54 PM PDT 24
Peak memory 213844 kb
Host smart-a67a7ed2-ff8c-4185-a82e-9f67a7d74006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104143998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.2104143998
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.564712117
Short name T434
Test name
Test status
Simulation time 248021444 ps
CPU time 27.96 seconds
Started Jun 02 03:14:52 PM PDT 24
Finished Jun 02 03:15:21 PM PDT 24
Peak memory 251324 kb
Host smart-768e5c20-e8be-4ea1-b069-072468576245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564712117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.564712117
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.1594497524
Short name T683
Test name
Test status
Simulation time 82830152 ps
CPU time 7.39 seconds
Started Jun 02 03:14:56 PM PDT 24
Finished Jun 02 03:15:04 PM PDT 24
Peak memory 251092 kb
Host smart-016fd7af-8806-4a43-82a4-1d3b1aabbd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594497524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.1594497524
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.1944609526
Short name T244
Test name
Test status
Simulation time 2252369582 ps
CPU time 39.06 seconds
Started Jun 02 03:15:04 PM PDT 24
Finished Jun 02 03:15:44 PM PDT 24
Peak memory 251372 kb
Host smart-2a7cf541-aa7d-4836-8280-cf503de86f3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944609526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.1944609526
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.939992420
Short name T424
Test name
Test status
Simulation time 23706640 ps
CPU time 0.89 seconds
Started Jun 02 03:14:52 PM PDT 24
Finished Jun 02 03:14:54 PM PDT 24
Peak memory 212004 kb
Host smart-36539b33-eb42-4ffd-8809-0d8fa1f93c02
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939992420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.939992420
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3923714275
Short name T230
Test name
Test status
Simulation time 33134181 ps
CPU time 0.84 seconds
Started Jun 02 03:15:13 PM PDT 24
Finished Jun 02 03:15:14 PM PDT 24
Peak memory 209348 kb
Host smart-fea77c27-d800-4293-9617-c1a55a113e9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923714275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3923714275
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2299622226
Short name T482
Test name
Test status
Simulation time 3096864888 ps
CPU time 12.25 seconds
Started Jun 02 03:14:57 PM PDT 24
Finished Jun 02 03:15:09 PM PDT 24
Peak memory 218468 kb
Host smart-d32796e0-fcb7-43d8-9547-1b9ffbf83187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299622226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2299622226
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.3178164753
Short name T31
Test name
Test status
Simulation time 1334345716 ps
CPU time 17.19 seconds
Started Jun 02 03:15:00 PM PDT 24
Finished Jun 02 03:15:18 PM PDT 24
Peak memory 209920 kb
Host smart-c1ea2bf7-6e36-4a7a-8c43-0f93cff4a93e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178164753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.3178164753
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.447290350
Short name T174
Test name
Test status
Simulation time 144778103 ps
CPU time 3.53 seconds
Started Jun 02 03:14:57 PM PDT 24
Finished Jun 02 03:15:01 PM PDT 24
Peak memory 218352 kb
Host smart-5d4d852d-719f-4500-a0ca-da4a443e3d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447290350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.447290350
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.3369808989
Short name T558
Test name
Test status
Simulation time 1583272140 ps
CPU time 12.09 seconds
Started Jun 02 03:15:00 PM PDT 24
Finished Jun 02 03:15:12 PM PDT 24
Peak memory 218808 kb
Host smart-d0af1d2f-a798-4907-9ba5-85645701576e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369808989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.3369808989
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.4125386571
Short name T423
Test name
Test status
Simulation time 2710632906 ps
CPU time 14.36 seconds
Started Jun 02 03:15:00 PM PDT 24
Finished Jun 02 03:15:15 PM PDT 24
Peak memory 226568 kb
Host smart-c47b77c5-5dfa-4318-a8af-b6653d3ca2c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125386571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.4125386571
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.4109084379
Short name T537
Test name
Test status
Simulation time 208859521 ps
CPU time 7.85 seconds
Started Jun 02 03:15:00 PM PDT 24
Finished Jun 02 03:15:09 PM PDT 24
Peak memory 224816 kb
Host smart-f21d5173-a358-42ff-acca-819383ded0ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109084379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
4109084379
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.625145729
Short name T509
Test name
Test status
Simulation time 1583190340 ps
CPU time 10 seconds
Started Jun 02 03:15:04 PM PDT 24
Finished Jun 02 03:15:15 PM PDT 24
Peak memory 225432 kb
Host smart-41a1e233-b918-49c4-ae5a-501746a44a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625145729 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.625145729
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.74782171
Short name T437
Test name
Test status
Simulation time 27124677 ps
CPU time 2.13 seconds
Started Jun 02 03:15:13 PM PDT 24
Finished Jun 02 03:15:15 PM PDT 24
Peak memory 214152 kb
Host smart-f0c70b0a-1b94-4fac-8f3c-8a2787aa32d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74782171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.74782171
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.404783289
Short name T519
Test name
Test status
Simulation time 857590888 ps
CPU time 21.65 seconds
Started Jun 02 03:14:59 PM PDT 24
Finished Jun 02 03:15:21 PM PDT 24
Peak memory 251304 kb
Host smart-922b876d-826c-4d84-9892-52faf8c0a8df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404783289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.404783289
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1410398081
Short name T739
Test name
Test status
Simulation time 1065733014 ps
CPU time 9.49 seconds
Started Jun 02 03:14:57 PM PDT 24
Finished Jun 02 03:15:07 PM PDT 24
Peak memory 251272 kb
Host smart-bf2acc93-7f88-4f94-8b8a-3302002e267e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410398081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1410398081
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.270392182
Short name T711
Test name
Test status
Simulation time 14530663550 ps
CPU time 225.47 seconds
Started Jun 02 03:14:57 PM PDT 24
Finished Jun 02 03:18:43 PM PDT 24
Peak memory 251256 kb
Host smart-c0cab212-c1be-48bf-93b8-3f2e3d805ae7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270392182 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.270392182
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all_with_rand_reset.4030494861
Short name T138
Test name
Test status
Simulation time 46038357558 ps
CPU time 611.81 seconds
Started Jun 02 03:15:13 PM PDT 24
Finished Jun 02 03:25:25 PM PDT 24
Peak memory 447932 kb
Host smart-0b99e488-b495-41d3-8f95-71f9e37d626b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4030494861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_stress_all_with_rand_reset.4030494861
Directory /workspace/46.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3755613092
Short name T643
Test name
Test status
Simulation time 39137557 ps
CPU time 0.85 seconds
Started Jun 02 03:15:03 PM PDT 24
Finished Jun 02 03:15:04 PM PDT 24
Peak memory 212040 kb
Host smart-1dac126c-cd76-4203-84a9-e0d6470dbcee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755613092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3755613092
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.388006812
Short name T384
Test name
Test status
Simulation time 17698087 ps
CPU time 0.98 seconds
Started Jun 02 03:15:02 PM PDT 24
Finished Jun 02 03:15:04 PM PDT 24
Peak memory 209152 kb
Host smart-816aa90f-61ba-4fdd-9d42-e4d9f1109814
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388006812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.388006812
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.503988581
Short name T484
Test name
Test status
Simulation time 469117890 ps
CPU time 19.01 seconds
Started Jun 02 03:14:57 PM PDT 24
Finished Jun 02 03:15:17 PM PDT 24
Peak memory 218344 kb
Host smart-7e82b931-a3f2-4d84-9e48-cc98f839ee6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503988581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.503988581
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1104545848
Short name T646
Test name
Test status
Simulation time 1951819074 ps
CPU time 6.32 seconds
Started Jun 02 03:15:13 PM PDT 24
Finished Jun 02 03:15:20 PM PDT 24
Peak memory 217048 kb
Host smart-96378e8a-ff48-41b1-b418-f46038be0a47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104545848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.1104545848
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.2060849086
Short name T688
Test name
Test status
Simulation time 395227809 ps
CPU time 4.32 seconds
Started Jun 02 03:15:01 PM PDT 24
Finished Jun 02 03:15:05 PM PDT 24
Peak memory 218356 kb
Host smart-25077d1b-cda9-4174-afb7-38e099de671f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060849086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.2060849086
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.507135594
Short name T625
Test name
Test status
Simulation time 361565478 ps
CPU time 15.01 seconds
Started Jun 02 03:15:00 PM PDT 24
Finished Jun 02 03:15:15 PM PDT 24
Peak memory 226696 kb
Host smart-dee83f4b-8838-4c3d-a658-152fb8f7f2cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507135594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.507135594
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.72407976
Short name T867
Test name
Test status
Simulation time 385437237 ps
CPU time 8.61 seconds
Started Jun 02 03:15:07 PM PDT 24
Finished Jun 02 03:15:16 PM PDT 24
Peak memory 225364 kb
Host smart-0ec5e1e8-e7e2-4f4f-a9ab-473d5800d516
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72407976 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_dig
est.72407976
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.2365912779
Short name T383
Test name
Test status
Simulation time 652745870 ps
CPU time 20.21 seconds
Started Jun 02 03:15:05 PM PDT 24
Finished Jun 02 03:15:26 PM PDT 24
Peak memory 226508 kb
Host smart-f990d214-23c4-4e12-95ee-ca214e51bae4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365912779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
2365912779
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3054539622
Short name T764
Test name
Test status
Simulation time 293686189 ps
CPU time 12.15 seconds
Started Jun 02 03:14:58 PM PDT 24
Finished Jun 02 03:15:11 PM PDT 24
Peak memory 218484 kb
Host smart-0dc288b6-6000-496e-8035-122c5a9d683a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054539622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3054539622
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.1035624317
Short name T795
Test name
Test status
Simulation time 39376618 ps
CPU time 2.85 seconds
Started Jun 02 03:15:01 PM PDT 24
Finished Jun 02 03:15:04 PM PDT 24
Peak memory 218036 kb
Host smart-58e21397-fc94-4d7b-918b-affd6495c73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035624317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.1035624317
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2083985690
Short name T827
Test name
Test status
Simulation time 322387933 ps
CPU time 17.22 seconds
Started Jun 02 03:15:13 PM PDT 24
Finished Jun 02 03:15:31 PM PDT 24
Peak memory 251168 kb
Host smart-0f6fd593-bb7f-4580-92c7-275fcec3e6ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083985690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2083985690
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.964535587
Short name T82
Test name
Test status
Simulation time 190880781 ps
CPU time 6.17 seconds
Started Jun 02 03:15:13 PM PDT 24
Finished Jun 02 03:15:19 PM PDT 24
Peak memory 250656 kb
Host smart-3996368f-deb8-4d4b-8a1b-4f724a79afe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964535587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.964535587
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.220341918
Short name T276
Test name
Test status
Simulation time 12725469878 ps
CPU time 106.91 seconds
Started Jun 02 03:15:05 PM PDT 24
Finished Jun 02 03:16:53 PM PDT 24
Peak memory 280636 kb
Host smart-991da143-c858-4c36-9d55-f817f6bca812
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220341918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.220341918
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.2371387414
Short name T153
Test name
Test status
Simulation time 16838512762 ps
CPU time 501.24 seconds
Started Jun 02 03:15:04 PM PDT 24
Finished Jun 02 03:23:26 PM PDT 24
Peak memory 284264 kb
Host smart-2ef55921-cacf-4347-8a8d-e5524ec30bd8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2371387414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.2371387414
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3274276679
Short name T782
Test name
Test status
Simulation time 18725426 ps
CPU time 1 seconds
Started Jun 02 03:15:13 PM PDT 24
Finished Jun 02 03:15:14 PM PDT 24
Peak memory 211792 kb
Host smart-6705d307-1de5-493a-8e20-9060324ba0d3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3274276679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.3274276679
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.183755995
Short name T586
Test name
Test status
Simulation time 130891741 ps
CPU time 1.45 seconds
Started Jun 02 03:15:04 PM PDT 24
Finished Jun 02 03:15:06 PM PDT 24
Peak memory 209056 kb
Host smart-065e7eb8-3b61-47d4-9ef0-d5efccc37919
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183755995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.183755995
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.468117543
Short name T701
Test name
Test status
Simulation time 1316868821 ps
CPU time 13.66 seconds
Started Jun 02 03:15:04 PM PDT 24
Finished Jun 02 03:15:19 PM PDT 24
Peak memory 218392 kb
Host smart-4273bb79-dfad-4376-9dd2-d04d1aae06ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468117543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.468117543
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3839078903
Short name T468
Test name
Test status
Simulation time 82973032 ps
CPU time 1.69 seconds
Started Jun 02 03:15:05 PM PDT 24
Finished Jun 02 03:15:07 PM PDT 24
Peak memory 217212 kb
Host smart-728b4ebd-20ca-489e-b4d1-6625d9ced2f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839078903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.3839078903
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.706688884
Short name T812
Test name
Test status
Simulation time 49207040 ps
CPU time 1.97 seconds
Started Jun 02 03:15:04 PM PDT 24
Finished Jun 02 03:15:07 PM PDT 24
Peak memory 218488 kb
Host smart-f3d61604-c17e-481b-a5a9-e04dd339a7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706688884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.706688884
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1929885587
Short name T294
Test name
Test status
Simulation time 2757434495 ps
CPU time 17.22 seconds
Started Jun 02 03:15:03 PM PDT 24
Finished Jun 02 03:15:20 PM PDT 24
Peak memory 219624 kb
Host smart-7bcd91ee-daba-4d08-a464-f1601b2ac833
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929885587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1929885587
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.3444105113
Short name T413
Test name
Test status
Simulation time 343205876 ps
CPU time 9 seconds
Started Jun 02 03:15:04 PM PDT 24
Finished Jun 02 03:15:14 PM PDT 24
Peak memory 226512 kb
Host smart-f49f5a93-f1c8-4b3e-83cb-8ffb0cbba362
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444105113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.3444105113
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.3519775367
Short name T252
Test name
Test status
Simulation time 1446712912 ps
CPU time 9.94 seconds
Started Jun 02 03:15:03 PM PDT 24
Finished Jun 02 03:15:14 PM PDT 24
Peak memory 226488 kb
Host smart-02fa4fa1-6a95-4e9a-994e-67dbee2e3a5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519775367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
3519775367
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2278079770
Short name T450
Test name
Test status
Simulation time 1628799249 ps
CPU time 6.3 seconds
Started Jun 02 03:15:03 PM PDT 24
Finished Jun 02 03:15:10 PM PDT 24
Peak memory 218488 kb
Host smart-1fb26e7f-7ad0-4b6b-9b8f-c096d9ead379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278079770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2278079770
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.651469513
Short name T71
Test name
Test status
Simulation time 34003159 ps
CPU time 1.78 seconds
Started Jun 02 03:15:04 PM PDT 24
Finished Jun 02 03:15:07 PM PDT 24
Peak memory 214100 kb
Host smart-bae2974b-5f6d-4287-af9f-831852c41f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651469513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.651469513
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1843980094
Short name T820
Test name
Test status
Simulation time 338673256 ps
CPU time 26.99 seconds
Started Jun 02 03:15:04 PM PDT 24
Finished Jun 02 03:15:31 PM PDT 24
Peak memory 251276 kb
Host smart-d0bd5b35-15bb-4aa6-bc4c-8e1e94144a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843980094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1843980094
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.3786228838
Short name T176
Test name
Test status
Simulation time 52200592 ps
CPU time 6.81 seconds
Started Jun 02 03:15:03 PM PDT 24
Finished Jun 02 03:15:11 PM PDT 24
Peak memory 247380 kb
Host smart-d398d275-432b-4923-b73a-c79d78d457c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786228838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.3786228838
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.284558757
Short name T12
Test name
Test status
Simulation time 1811915103 ps
CPU time 41.39 seconds
Started Jun 02 03:15:05 PM PDT 24
Finished Jun 02 03:15:47 PM PDT 24
Peak memory 251416 kb
Host smart-cb42a973-4020-4e6b-8fe3-d5e5349aa4ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284558757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.284558757
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.359320810
Short name T570
Test name
Test status
Simulation time 12249586 ps
CPU time 0.86 seconds
Started Jun 02 03:15:05 PM PDT 24
Finished Jun 02 03:15:06 PM PDT 24
Peak memory 212084 kb
Host smart-45b79eff-eb8c-46b3-94ec-06f70daacff1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359320810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct
rl_volatile_unlock_smoke.359320810
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1444047613
Short name T86
Test name
Test status
Simulation time 32662880 ps
CPU time 0.96 seconds
Started Jun 02 03:15:09 PM PDT 24
Finished Jun 02 03:15:10 PM PDT 24
Peak memory 209148 kb
Host smart-3a7c04ae-805e-46fa-bb37-e60c18fdebda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444047613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1444047613
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.4218784105
Short name T307
Test name
Test status
Simulation time 758768157 ps
CPU time 8.48 seconds
Started Jun 02 03:15:09 PM PDT 24
Finished Jun 02 03:15:18 PM PDT 24
Peak memory 218344 kb
Host smart-7fdf8e54-7c7b-4437-9cc5-09ebf10c84d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218784105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.4218784105
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1925846888
Short name T845
Test name
Test status
Simulation time 749522136 ps
CPU time 10.86 seconds
Started Jun 02 03:15:10 PM PDT 24
Finished Jun 02 03:15:22 PM PDT 24
Peak memory 209900 kb
Host smart-ed71301d-4f64-4aee-b22b-24e3340ee636
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925846888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1925846888
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2142404708
Short name T710
Test name
Test status
Simulation time 617064297 ps
CPU time 3.53 seconds
Started Jun 02 03:15:10 PM PDT 24
Finished Jun 02 03:15:15 PM PDT 24
Peak memory 218424 kb
Host smart-9b372de0-5ba5-4851-9e61-f104bd64cf1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142404708 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2142404708
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.1272381475
Short name T628
Test name
Test status
Simulation time 631407255 ps
CPU time 26.2 seconds
Started Jun 02 03:15:10 PM PDT 24
Finished Jun 02 03:15:37 PM PDT 24
Peak memory 226508 kb
Host smart-8afed582-e212-408a-b31e-0454209145d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272381475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.1272381475
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.121583692
Short name T602
Test name
Test status
Simulation time 273144036 ps
CPU time 7.88 seconds
Started Jun 02 03:15:09 PM PDT 24
Finished Jun 02 03:15:17 PM PDT 24
Peak memory 226508 kb
Host smart-42ec91ef-c88b-4057-ac18-ec5e55abbafa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121583692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_di
gest.121583692
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.2979598329
Short name T264
Test name
Test status
Simulation time 2086951635 ps
CPU time 14.79 seconds
Started Jun 02 03:15:09 PM PDT 24
Finished Jun 02 03:15:25 PM PDT 24
Peak memory 226164 kb
Host smart-7ba4025b-93cf-475a-b088-0b78aab8c5cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979598329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
2979598329
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3379428593
Short name T811
Test name
Test status
Simulation time 1596208586 ps
CPU time 13.91 seconds
Started Jun 02 03:15:08 PM PDT 24
Finished Jun 02 03:15:23 PM PDT 24
Peak memory 218540 kb
Host smart-f0af8988-b245-41ef-a3c9-ebe0707903d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379428593 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3379428593
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2380031347
Short name T95
Test name
Test status
Simulation time 18135059 ps
CPU time 1.28 seconds
Started Jun 02 03:15:03 PM PDT 24
Finished Jun 02 03:15:05 PM PDT 24
Peak memory 213812 kb
Host smart-dbb13b65-88e3-4d0b-8b3d-0a16f31ae7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380031347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2380031347
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.1253798172
Short name T463
Test name
Test status
Simulation time 254723999 ps
CPU time 8 seconds
Started Jun 02 03:15:09 PM PDT 24
Finished Jun 02 03:15:18 PM PDT 24
Peak memory 251332 kb
Host smart-6b5c72d7-a137-436e-b95f-bd0b57c10051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253798172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.1253798172
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.1207544389
Short name T186
Test name
Test status
Simulation time 8851113888 ps
CPU time 146.1 seconds
Started Jun 02 03:15:09 PM PDT 24
Finished Jun 02 03:17:36 PM PDT 24
Peak memory 293996 kb
Host smart-7d62fa34-516a-4e72-ae43-f4703df08def
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207544389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.1207544389
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.4236824091
Short name T531
Test name
Test status
Simulation time 11764903 ps
CPU time 0.91 seconds
Started Jun 02 03:15:11 PM PDT 24
Finished Jun 02 03:15:13 PM PDT 24
Peak memory 212020 kb
Host smart-8610751a-1a40-4a94-877c-01bd63105db3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236824091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.4236824091
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.124239999
Short name T301
Test name
Test status
Simulation time 23280844 ps
CPU time 1.01 seconds
Started Jun 02 03:12:36 PM PDT 24
Finished Jun 02 03:12:37 PM PDT 24
Peak memory 209972 kb
Host smart-e94dd880-c55b-4a76-b5b0-869a8e538db9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124239999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.124239999
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.2107697544
Short name T564
Test name
Test status
Simulation time 35492849 ps
CPU time 0.8 seconds
Started Jun 02 03:12:29 PM PDT 24
Finished Jun 02 03:12:31 PM PDT 24
Peak memory 209028 kb
Host smart-e7983491-9152-482b-922c-9158ff6fc07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107697544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.2107697544
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2049036466
Short name T702
Test name
Test status
Simulation time 1308775204 ps
CPU time 14.58 seconds
Started Jun 02 03:12:30 PM PDT 24
Finished Jun 02 03:12:45 PM PDT 24
Peak memory 218332 kb
Host smart-82a5413b-842c-4173-961e-25d5b5b0eeea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049036466 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2049036466
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3854492132
Short name T719
Test name
Test status
Simulation time 36637494 ps
CPU time 1.21 seconds
Started Jun 02 03:12:33 PM PDT 24
Finished Jun 02 03:12:35 PM PDT 24
Peak memory 209896 kb
Host smart-2a3408bb-4644-4486-9239-381d86ebf652
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854492132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3854492132
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2968828703
Short name T824
Test name
Test status
Simulation time 12823344554 ps
CPU time 40.56 seconds
Started Jun 02 03:12:30 PM PDT 24
Finished Jun 02 03:13:12 PM PDT 24
Peak memory 218756 kb
Host smart-e1e45d20-51ff-4bcc-b231-f7bf619d97f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968828703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2968828703
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.105095095
Short name T575
Test name
Test status
Simulation time 565800692 ps
CPU time 2.21 seconds
Started Jun 02 03:12:33 PM PDT 24
Finished Jun 02 03:12:36 PM PDT 24
Peak memory 210004 kb
Host smart-bda7f5f1-a6a9-4c56-83ee-36c178cbcae7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105095095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.105095095
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.804134005
Short name T170
Test name
Test status
Simulation time 2075482645 ps
CPU time 11.01 seconds
Started Jun 02 03:12:29 PM PDT 24
Finished Jun 02 03:12:40 PM PDT 24
Peak memory 218244 kb
Host smart-6e2c6607-c63a-4b86-aacb-3e4cce7eb552
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804134005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_
prog_failure.804134005
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3164293296
Short name T165
Test name
Test status
Simulation time 2903843167 ps
CPU time 10.67 seconds
Started Jun 02 03:12:35 PM PDT 24
Finished Jun 02 03:12:46 PM PDT 24
Peak memory 218056 kb
Host smart-e01afc31-af48-4801-af81-acd30f292220
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164293296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3164293296
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3938378623
Short name T363
Test name
Test status
Simulation time 225941117 ps
CPU time 3.52 seconds
Started Jun 02 03:12:27 PM PDT 24
Finished Jun 02 03:12:32 PM PDT 24
Peak memory 218036 kb
Host smart-e4d571ef-2681-4a12-b3cc-8e13acfe2651
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938378623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3938378623
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.910081458
Short name T740
Test name
Test status
Simulation time 15134394973 ps
CPU time 128.7 seconds
Started Jun 02 03:12:29 PM PDT 24
Finished Jun 02 03:14:38 PM PDT 24
Peak memory 284068 kb
Host smart-4fc488bf-74bc-445a-9af8-05a45300a798
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910081458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_state_failure.910081458
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.287951949
Short name T839
Test name
Test status
Simulation time 2689433161 ps
CPU time 16.53 seconds
Started Jun 02 03:12:27 PM PDT 24
Finished Jun 02 03:12:44 PM PDT 24
Peak memory 251216 kb
Host smart-464f2f78-b86c-4bd7-82ea-b2fec839fd3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287951949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.287951949
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1983298501
Short name T581
Test name
Test status
Simulation time 294799851 ps
CPU time 3.14 seconds
Started Jun 02 03:12:27 PM PDT 24
Finished Jun 02 03:12:31 PM PDT 24
Peak memory 218428 kb
Host smart-4df043a5-3f9b-423e-8563-5996f3a2154c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983298501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1983298501
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2496467870
Short name T191
Test name
Test status
Simulation time 275489123 ps
CPU time 19.11 seconds
Started Jun 02 03:12:29 PM PDT 24
Finished Jun 02 03:12:49 PM PDT 24
Peak memory 214848 kb
Host smart-1bfb384f-76ef-4f33-80e9-1fb588a4fb45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496467870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2496467870
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2268138339
Short name T588
Test name
Test status
Simulation time 1525526653 ps
CPU time 12.19 seconds
Started Jun 02 03:12:33 PM PDT 24
Finished Jun 02 03:12:46 PM PDT 24
Peak memory 226444 kb
Host smart-3537bc1c-1a29-4e17-b30a-3c1446b9d55c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268138339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2268138339
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.386835853
Short name T651
Test name
Test status
Simulation time 1000388467 ps
CPU time 11.14 seconds
Started Jun 02 03:12:32 PM PDT 24
Finished Jun 02 03:12:44 PM PDT 24
Peak memory 226336 kb
Host smart-11a45d82-d79d-4fc4-9dcb-4a2728910c73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386835853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_dig
est.386835853
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3359001578
Short name T504
Test name
Test status
Simulation time 295574110 ps
CPU time 10.67 seconds
Started Jun 02 03:12:33 PM PDT 24
Finished Jun 02 03:12:45 PM PDT 24
Peak memory 226480 kb
Host smart-e5c0732d-0030-4994-8b9b-980a5b4ca59b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359001578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
359001578
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.606093377
Short name T461
Test name
Test status
Simulation time 357778515 ps
CPU time 8.36 seconds
Started Jun 02 03:12:30 PM PDT 24
Finished Jun 02 03:12:40 PM PDT 24
Peak memory 218484 kb
Host smart-e8884aeb-a081-4afb-b902-dac736349bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606093377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.606093377
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.2353663883
Short name T69
Test name
Test status
Simulation time 49284611 ps
CPU time 3.11 seconds
Started Jun 02 03:12:30 PM PDT 24
Finished Jun 02 03:12:33 PM PDT 24
Peak memory 218312 kb
Host smart-5642f20f-432d-4de1-a979-f9fd5b7bfbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353663883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.2353663883
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.3865226090
Short name T587
Test name
Test status
Simulation time 158537075 ps
CPU time 22.74 seconds
Started Jun 02 03:12:30 PM PDT 24
Finished Jun 02 03:12:53 PM PDT 24
Peak memory 251352 kb
Host smart-833431a1-abfe-4b50-9bb4-d086d0e0b193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865226090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.3865226090
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.2577895108
Short name T369
Test name
Test status
Simulation time 59154632 ps
CPU time 6.39 seconds
Started Jun 02 03:12:32 PM PDT 24
Finished Jun 02 03:12:39 PM PDT 24
Peak memory 247448 kb
Host smart-f6d25acd-e082-40d4-a1da-15fcf8b5b122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577895108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.2577895108
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.3341186780
Short name T336
Test name
Test status
Simulation time 3363444716 ps
CPU time 59.99 seconds
Started Jun 02 03:12:34 PM PDT 24
Finished Jun 02 03:13:35 PM PDT 24
Peak memory 276020 kb
Host smart-66cc9685-b685-4f9d-b084-0154bc9beb61
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341186780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.3341186780
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.4089372857
Short name T256
Test name
Test status
Simulation time 44720889 ps
CPU time 0.89 seconds
Started Jun 02 03:12:27 PM PDT 24
Finished Jun 02 03:12:29 PM PDT 24
Peak memory 211928 kb
Host smart-55a2099a-d86c-4b77-86ea-27992deaad47
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089372857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.4089372857
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.3911055962
Short name T242
Test name
Test status
Simulation time 138038466 ps
CPU time 0.91 seconds
Started Jun 02 03:12:39 PM PDT 24
Finished Jun 02 03:12:41 PM PDT 24
Peak memory 209216 kb
Host smart-2d4b82a0-db84-49ed-ba0e-002650f46394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911055962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.3911055962
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.863818198
Short name T431
Test name
Test status
Simulation time 15600255 ps
CPU time 0.93 seconds
Started Jun 02 03:12:35 PM PDT 24
Finished Jun 02 03:12:36 PM PDT 24
Peak memory 209076 kb
Host smart-27d7438f-ac95-40e6-822a-a2ebd4bec1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863818198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.863818198
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.1611363236
Short name T390
Test name
Test status
Simulation time 394882826 ps
CPU time 11.58 seconds
Started Jun 02 03:12:36 PM PDT 24
Finished Jun 02 03:12:48 PM PDT 24
Peak memory 218316 kb
Host smart-50811d9f-cd2d-413e-bfc6-226ec04014a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611363236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.1611363236
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1295020724
Short name T1
Test name
Test status
Simulation time 125409323 ps
CPU time 2.58 seconds
Started Jun 02 03:12:39 PM PDT 24
Finished Jun 02 03:12:42 PM PDT 24
Peak memory 217492 kb
Host smart-791724f9-e6e1-4c48-a2eb-56b95c60ccd7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295020724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1295020724
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3977512603
Short name T522
Test name
Test status
Simulation time 10834698495 ps
CPU time 27.39 seconds
Started Jun 02 03:12:42 PM PDT 24
Finished Jun 02 03:13:10 PM PDT 24
Peak memory 218372 kb
Host smart-e94981ce-507a-4a01-8e68-5d3716d68a2c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977512603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3977512603
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.326526659
Short name T713
Test name
Test status
Simulation time 2829847220 ps
CPU time 10.28 seconds
Started Jun 02 03:12:39 PM PDT 24
Finished Jun 02 03:12:50 PM PDT 24
Peak memory 218060 kb
Host smart-4527a954-b063-4b15-bfe1-612a7f73d2b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326526659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.326526659
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.3141657008
Short name T388
Test name
Test status
Simulation time 1722364647 ps
CPU time 14.28 seconds
Started Jun 02 03:12:35 PM PDT 24
Finished Jun 02 03:12:50 PM PDT 24
Peak memory 218396 kb
Host smart-280b37ca-679b-4230-beb6-14aa6cd07795
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141657008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.3141657008
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1786059785
Short name T245
Test name
Test status
Simulation time 2662152354 ps
CPU time 20.81 seconds
Started Jun 02 03:12:38 PM PDT 24
Finished Jun 02 03:12:59 PM PDT 24
Peak memory 218100 kb
Host smart-f94b22ad-b33a-4d6e-ac89-6b75192daba0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786059785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.1786059785
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.1633255765
Short name T507
Test name
Test status
Simulation time 608563456 ps
CPU time 9.31 seconds
Started Jun 02 03:12:35 PM PDT 24
Finished Jun 02 03:12:45 PM PDT 24
Peak memory 218040 kb
Host smart-5dae61e3-422a-4bb0-ac2c-010ed3cfbdcb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633255765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
1633255765
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2682980029
Short name T405
Test name
Test status
Simulation time 1256537487 ps
CPU time 39.24 seconds
Started Jun 02 03:12:34 PM PDT 24
Finished Jun 02 03:13:14 PM PDT 24
Peak memory 249604 kb
Host smart-ff7671d1-0f24-4374-a751-614ccc9f3c89
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682980029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2682980029
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.2709874950
Short name T224
Test name
Test status
Simulation time 571427326 ps
CPU time 21.22 seconds
Started Jun 02 03:12:32 PM PDT 24
Finished Jun 02 03:12:54 PM PDT 24
Peak memory 251208 kb
Host smart-d12ab134-e545-4588-ace8-b66130a32a19
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709874950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.2709874950
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.4075719202
Short name T435
Test name
Test status
Simulation time 76385651 ps
CPU time 3.96 seconds
Started Jun 02 03:12:34 PM PDT 24
Finished Jun 02 03:12:38 PM PDT 24
Peak memory 218412 kb
Host smart-326dea3d-93db-490b-a8c0-5fc551eb2c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075719202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.4075719202
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.4281231776
Short name T718
Test name
Test status
Simulation time 301905245 ps
CPU time 16.05 seconds
Started Jun 02 03:12:35 PM PDT 24
Finished Jun 02 03:12:51 PM PDT 24
Peak memory 214764 kb
Host smart-61036609-3ff5-4afe-ae2b-86be7b218279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281231776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.4281231776
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.1572856605
Short name T166
Test name
Test status
Simulation time 511847644 ps
CPU time 10.71 seconds
Started Jun 02 03:12:37 PM PDT 24
Finished Jun 02 03:12:49 PM PDT 24
Peak memory 218544 kb
Host smart-5658f518-b45e-4d89-9fad-643787aebc66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572856605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.1572856605
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3802852430
Short name T520
Test name
Test status
Simulation time 2164444971 ps
CPU time 19.12 seconds
Started Jun 02 03:12:39 PM PDT 24
Finished Jun 02 03:12:58 PM PDT 24
Peak memory 226556 kb
Host smart-a65d6f06-ee56-4a3b-b0b2-7d635d130575
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802852430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3802852430
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.640217819
Short name T14
Test name
Test status
Simulation time 1247122424 ps
CPU time 8.98 seconds
Started Jun 02 03:12:38 PM PDT 24
Finished Jun 02 03:12:47 PM PDT 24
Peak memory 225972 kb
Host smart-52e933b9-2d01-418a-961d-66d7fa1e8b80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640217819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.640217819
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2273852610
Short name T157
Test name
Test status
Simulation time 1736040499 ps
CPU time 11.74 seconds
Started Jun 02 03:12:35 PM PDT 24
Finished Jun 02 03:12:47 PM PDT 24
Peak memory 225200 kb
Host smart-4e025d67-b25b-4204-807d-1c27b668dbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273852610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2273852610
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.853615263
Short name T496
Test name
Test status
Simulation time 58804299 ps
CPU time 1.79 seconds
Started Jun 02 03:12:35 PM PDT 24
Finished Jun 02 03:12:37 PM PDT 24
Peak memory 213980 kb
Host smart-93701937-7045-4d1d-a02c-f9ec6608f687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853615263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.853615263
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3427963957
Short name T379
Test name
Test status
Simulation time 471037323 ps
CPU time 25.04 seconds
Started Jun 02 03:12:34 PM PDT 24
Finished Jun 02 03:12:59 PM PDT 24
Peak memory 251308 kb
Host smart-2bfb382f-5903-4f73-8310-233cfecddfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427963957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3427963957
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.4274186159
Short name T455
Test name
Test status
Simulation time 141844204 ps
CPU time 3.46 seconds
Started Jun 02 03:12:32 PM PDT 24
Finished Jun 02 03:12:36 PM PDT 24
Peak memory 222572 kb
Host smart-2e98854d-f4f6-4b2c-931a-5bd3206af466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274186159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.4274186159
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1047876489
Short name T582
Test name
Test status
Simulation time 3462821258 ps
CPU time 92.5 seconds
Started Jun 02 03:12:39 PM PDT 24
Finished Jun 02 03:14:12 PM PDT 24
Peak memory 284044 kb
Host smart-ba997c5e-e6e8-42f1-9f78-e9ebe796facc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047876489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1047876489
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.2427198517
Short name T597
Test name
Test status
Simulation time 44145149 ps
CPU time 0.84 seconds
Started Jun 02 03:12:34 PM PDT 24
Finished Jun 02 03:12:35 PM PDT 24
Peak memory 211976 kb
Host smart-c0f4883c-005c-44f5-9b7e-da1d6efe3ccb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427198517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.2427198517
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2859406526
Short name T367
Test name
Test status
Simulation time 114802278 ps
CPU time 0.99 seconds
Started Jun 02 03:12:47 PM PDT 24
Finished Jun 02 03:12:49 PM PDT 24
Peak memory 209172 kb
Host smart-1b40e772-b249-4e59-b83a-2314c21e5ed3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859406526 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2859406526
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.939174040
Short name T775
Test name
Test status
Simulation time 21070958 ps
CPU time 0.83 seconds
Started Jun 02 03:12:50 PM PDT 24
Finished Jun 02 03:12:51 PM PDT 24
Peak memory 209076 kb
Host smart-c448fcb3-bcb0-41ae-9a31-be13ee2013e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939174040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.939174040
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3794847878
Short name T774
Test name
Test status
Simulation time 486587738 ps
CPU time 12.49 seconds
Started Jun 02 03:12:42 PM PDT 24
Finished Jun 02 03:12:55 PM PDT 24
Peak memory 218412 kb
Host smart-6d4b0aaa-27d1-4863-bc4b-45eed48d022a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794847878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3794847878
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.3084837000
Short name T370
Test name
Test status
Simulation time 1164635684 ps
CPU time 14.7 seconds
Started Jun 02 03:12:44 PM PDT 24
Finished Jun 02 03:12:59 PM PDT 24
Peak memory 210016 kb
Host smart-70ea16ad-b56d-4a26-9427-72809a7ef4c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084837000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.3084837000
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.220922456
Short name T835
Test name
Test status
Simulation time 3387256072 ps
CPU time 45.74 seconds
Started Jun 02 03:12:50 PM PDT 24
Finished Jun 02 03:13:37 PM PDT 24
Peak memory 219992 kb
Host smart-8565a8f0-d86d-4162-a17d-0992f656f9b7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220922456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_err
ors.220922456
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2704365321
Short name T409
Test name
Test status
Simulation time 1000300505 ps
CPU time 23.23 seconds
Started Jun 02 03:12:47 PM PDT 24
Finished Jun 02 03:13:11 PM PDT 24
Peak memory 217732 kb
Host smart-1a3e9278-8c08-484b-82b1-16922d6cb278
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704365321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
704365321
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.1597410602
Short name T487
Test name
Test status
Simulation time 745765953 ps
CPU time 7.49 seconds
Started Jun 02 03:12:45 PM PDT 24
Finished Jun 02 03:12:53 PM PDT 24
Peak memory 218396 kb
Host smart-1f356872-3aca-4b59-b9bd-deab00302e10
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597410602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.1597410602
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3867427085
Short name T385
Test name
Test status
Simulation time 3662065153 ps
CPU time 16.53 seconds
Started Jun 02 03:12:48 PM PDT 24
Finished Jun 02 03:13:05 PM PDT 24
Peak memory 218104 kb
Host smart-565845bc-70c6-4d03-9add-e3e93485bdbb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867427085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3867427085
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.3975607737
Short name T94
Test name
Test status
Simulation time 353006748 ps
CPU time 5.7 seconds
Started Jun 02 03:12:47 PM PDT 24
Finished Jun 02 03:12:53 PM PDT 24
Peak memory 218032 kb
Host smart-1cb3b3d3-38a2-4142-8c34-e2a68b739d97
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975607737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
3975607737
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2035318611
Short name T426
Test name
Test status
Simulation time 1222573631 ps
CPU time 47.35 seconds
Started Jun 02 03:12:45 PM PDT 24
Finished Jun 02 03:13:33 PM PDT 24
Peak memory 267652 kb
Host smart-f6e246ef-0530-4cca-b5c4-d42361b534cb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035318611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2035318611
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.3716267436
Short name T257
Test name
Test status
Simulation time 569981403 ps
CPU time 13.19 seconds
Started Jun 02 03:12:46 PM PDT 24
Finished Jun 02 03:12:59 PM PDT 24
Peak memory 250828 kb
Host smart-2289042a-b0bd-4d55-ae06-76662eb71e1f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716267436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.3716267436
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.1702951971
Short name T844
Test name
Test status
Simulation time 683583681 ps
CPU time 3.91 seconds
Started Jun 02 03:12:38 PM PDT 24
Finished Jun 02 03:12:43 PM PDT 24
Peak memory 218404 kb
Host smart-c77ff7c8-05b0-4669-874e-64bf0613302d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702951971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.1702951971
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.4284907158
Short name T93
Test name
Test status
Simulation time 1006127983 ps
CPU time 6.97 seconds
Started Jun 02 03:12:40 PM PDT 24
Finished Jun 02 03:12:47 PM PDT 24
Peak memory 218048 kb
Host smart-b1d4c449-8fdb-4f7a-8489-5700b2edb8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284907158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.4284907158
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.909379826
Short name T386
Test name
Test status
Simulation time 845258596 ps
CPU time 10.93 seconds
Started Jun 02 03:12:45 PM PDT 24
Finished Jun 02 03:12:57 PM PDT 24
Peak memory 219364 kb
Host smart-d85745d2-6e4d-4e98-b93a-a08fd745f103
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909379826 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.909379826
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3884376031
Short name T321
Test name
Test status
Simulation time 1142791138 ps
CPU time 15.24 seconds
Started Jun 02 03:12:45 PM PDT 24
Finished Jun 02 03:13:01 PM PDT 24
Peak memory 226488 kb
Host smart-efe75249-8b43-41a5-954b-f7ea3424475e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884376031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3884376031
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1137384835
Short name T465
Test name
Test status
Simulation time 523023536 ps
CPU time 9.56 seconds
Started Jun 02 03:12:49 PM PDT 24
Finished Jun 02 03:12:59 PM PDT 24
Peak memory 225476 kb
Host smart-10fd98ff-9b24-4dcd-a37b-e21020f2d62b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137384835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
137384835
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.995774934
Short name T700
Test name
Test status
Simulation time 264525498 ps
CPU time 8.17 seconds
Started Jun 02 03:12:40 PM PDT 24
Finished Jun 02 03:12:49 PM PDT 24
Peak memory 218524 kb
Host smart-7ac15fea-3fa8-4ceb-a575-21690db23f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995774934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.995774934
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.2647215747
Short name T330
Test name
Test status
Simulation time 70957462 ps
CPU time 2.34 seconds
Started Jun 02 03:12:38 PM PDT 24
Finished Jun 02 03:12:41 PM PDT 24
Peak memory 218120 kb
Host smart-a8119657-33d2-4f2e-bc1b-ba661b59154d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647215747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.2647215747
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2361523954
Short name T708
Test name
Test status
Simulation time 1125128078 ps
CPU time 22.74 seconds
Started Jun 02 03:12:42 PM PDT 24
Finished Jun 02 03:13:06 PM PDT 24
Peak memory 251280 kb
Host smart-3e02dbd7-16d6-42de-abac-8fecb83d544a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361523954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2361523954
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.711086168
Short name T808
Test name
Test status
Simulation time 141804648 ps
CPU time 9.37 seconds
Started Jun 02 03:12:38 PM PDT 24
Finished Jun 02 03:12:48 PM PDT 24
Peak memory 251340 kb
Host smart-014e5902-2c8e-4c3e-82a1-8bf0895a51ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711086168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.711086168
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.1440769920
Short name T510
Test name
Test status
Simulation time 1900580546 ps
CPU time 60.56 seconds
Started Jun 02 03:12:44 PM PDT 24
Finished Jun 02 03:13:46 PM PDT 24
Peak memory 269168 kb
Host smart-7627b4d7-1016-49b2-8bc9-3bc5acd0d0e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440769920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.1440769920
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1921257242
Short name T554
Test name
Test status
Simulation time 17031822 ps
CPU time 0.73 seconds
Started Jun 02 03:12:42 PM PDT 24
Finished Jun 02 03:12:44 PM PDT 24
Peak memory 207620 kb
Host smart-99583d5f-59f7-4bca-b83a-0db47aadcbd7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921257242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1921257242
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.696935321
Short name T576
Test name
Test status
Simulation time 36595458 ps
CPU time 1.15 seconds
Started Jun 02 03:12:48 PM PDT 24
Finished Jun 02 03:12:50 PM PDT 24
Peak memory 209044 kb
Host smart-c47e2bb3-ef4c-4e51-a37f-d62967f44d5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696935321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.696935321
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1080961598
Short name T381
Test name
Test status
Simulation time 364886828 ps
CPU time 11.4 seconds
Started Jun 02 03:12:44 PM PDT 24
Finished Jun 02 03:12:56 PM PDT 24
Peak memory 218424 kb
Host smart-15b39d53-dda8-4e61-9952-007bbb9f5cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080961598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1080961598
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1309657733
Short name T862
Test name
Test status
Simulation time 1156046839 ps
CPU time 13.94 seconds
Started Jun 02 03:12:47 PM PDT 24
Finished Jun 02 03:13:02 PM PDT 24
Peak memory 209920 kb
Host smart-4027d905-1b64-4f62-b0a5-cbef04f4fff9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309657733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1309657733
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2734470322
Short name T83
Test name
Test status
Simulation time 2395474025 ps
CPU time 32.63 seconds
Started Jun 02 03:12:46 PM PDT 24
Finished Jun 02 03:13:20 PM PDT 24
Peak memory 219320 kb
Host smart-810c9650-117b-4b6b-80e2-99a41845919d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734470322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2734470322
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.3643282205
Short name T699
Test name
Test status
Simulation time 698678183 ps
CPU time 17.71 seconds
Started Jun 02 03:12:46 PM PDT 24
Finished Jun 02 03:13:05 PM PDT 24
Peak memory 217744 kb
Host smart-687b2094-37c3-49a4-b8b2-ee58a9402632
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643282205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.3
643282205
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.46323472
Short name T610
Test name
Test status
Simulation time 459710375 ps
CPU time 2.98 seconds
Started Jun 02 03:12:48 PM PDT 24
Finished Jun 02 03:12:52 PM PDT 24
Peak memory 218396 kb
Host smart-d1ff210d-5714-4e39-9260-9cbc4f83a48d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46323472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_p
rog_failure.46323472
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.2544196723
Short name T67
Test name
Test status
Simulation time 835453834 ps
CPU time 13.77 seconds
Started Jun 02 03:12:48 PM PDT 24
Finished Jun 02 03:13:03 PM PDT 24
Peak memory 218004 kb
Host smart-eee3bf95-fb6b-40ab-9b12-3c507ccb37d5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544196723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.2544196723
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.4105759313
Short name T402
Test name
Test status
Simulation time 4054045133 ps
CPU time 6.9 seconds
Started Jun 02 03:12:46 PM PDT 24
Finished Jun 02 03:12:53 PM PDT 24
Peak memory 218116 kb
Host smart-066b3c23-1c5a-4bae-adf8-0e1343df8ea1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105759313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
4105759313
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1661512575
Short name T861
Test name
Test status
Simulation time 2899585245 ps
CPU time 50.99 seconds
Started Jun 02 03:12:45 PM PDT 24
Finished Jun 02 03:13:36 PM PDT 24
Peak memory 267700 kb
Host smart-4b3c337f-c442-48f9-9619-c2ea79a6aa70
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661512575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1661512575
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2207928779
Short name T797
Test name
Test status
Simulation time 337748336 ps
CPU time 17 seconds
Started Jun 02 03:12:45 PM PDT 24
Finished Jun 02 03:13:03 PM PDT 24
Peak memory 251328 kb
Host smart-d115b2e6-efab-4e9f-a87c-5e4a6f995e5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207928779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2207928779
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.4082526984
Short name T498
Test name
Test status
Simulation time 35710695 ps
CPU time 2.41 seconds
Started Jun 02 03:12:45 PM PDT 24
Finished Jun 02 03:12:48 PM PDT 24
Peak memory 218492 kb
Host smart-1b4844c0-946b-4854-bff6-cf01e511da03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082526984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.4082526984
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.2413569371
Short name T794
Test name
Test status
Simulation time 322000750 ps
CPU time 20.3 seconds
Started Jun 02 03:12:45 PM PDT 24
Finished Jun 02 03:13:06 PM PDT 24
Peak memory 214952 kb
Host smart-e2366286-e1f4-4736-8247-2930da142981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413569371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.2413569371
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.866543311
Short name T595
Test name
Test status
Simulation time 1150929378 ps
CPU time 11.19 seconds
Started Jun 02 03:12:51 PM PDT 24
Finished Jun 02 03:13:03 PM PDT 24
Peak memory 219352 kb
Host smart-7517f624-aa96-4e57-8ec4-8ca44aa9eb7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866543311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.866543311
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2222967113
Short name T511
Test name
Test status
Simulation time 1762842959 ps
CPU time 21.65 seconds
Started Jun 02 03:12:47 PM PDT 24
Finished Jun 02 03:13:09 PM PDT 24
Peak memory 226516 kb
Host smart-1c7d36b3-a963-43d0-a3da-3a8817ace125
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222967113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2222967113
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.454660743
Short name T551
Test name
Test status
Simulation time 320160321 ps
CPU time 8.69 seconds
Started Jun 02 03:12:50 PM PDT 24
Finished Jun 02 03:13:00 PM PDT 24
Peak memory 226444 kb
Host smart-6e1c5090-1a86-485c-99e9-e129b36fc447
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454660743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.454660743
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.448396491
Short name T574
Test name
Test status
Simulation time 626947738 ps
CPU time 13.13 seconds
Started Jun 02 03:12:46 PM PDT 24
Finished Jun 02 03:13:00 PM PDT 24
Peak memory 225936 kb
Host smart-d8768f36-6f72-4dd8-9fdf-f52e67d4472b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448396491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.448396491
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.3182448718
Short name T727
Test name
Test status
Simulation time 46160399 ps
CPU time 1.15 seconds
Started Jun 02 03:12:49 PM PDT 24
Finished Jun 02 03:12:51 PM PDT 24
Peak memory 213688 kb
Host smart-67489122-6a65-4c38-9fa7-a57e222edbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182448718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.3182448718
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.3044994968
Short name T753
Test name
Test status
Simulation time 352680346 ps
CPU time 15.73 seconds
Started Jun 02 03:12:48 PM PDT 24
Finished Jun 02 03:13:05 PM PDT 24
Peak memory 251332 kb
Host smart-6ff528b5-e163-4594-a53e-bc6e2fa24bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044994968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.3044994968
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.143727109
Short name T243
Test name
Test status
Simulation time 86627915 ps
CPU time 7.38 seconds
Started Jun 02 03:12:47 PM PDT 24
Finished Jun 02 03:12:55 PM PDT 24
Peak memory 251412 kb
Host smart-21d9c21d-a324-46ad-a42c-c1fdbb888980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143727109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.143727109
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3698764562
Short name T36
Test name
Test status
Simulation time 2303723591 ps
CPU time 86.77 seconds
Started Jun 02 03:12:48 PM PDT 24
Finished Jun 02 03:14:16 PM PDT 24
Peak memory 246696 kb
Host smart-61dd6716-74c2-4bff-bff6-a77c92f9f392
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698764562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3698764562
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1214070517
Short name T447
Test name
Test status
Simulation time 58398176 ps
CPU time 1 seconds
Started Jun 02 03:12:46 PM PDT 24
Finished Jun 02 03:12:47 PM PDT 24
Peak memory 211924 kb
Host smart-94e16ebc-6de3-4d27-9304-1d01f6c0386a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214070517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1214070517
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.294425288
Short name T476
Test name
Test status
Simulation time 23028248 ps
CPU time 1.04 seconds
Started Jun 02 03:12:51 PM PDT 24
Finished Jun 02 03:12:53 PM PDT 24
Peak memory 209140 kb
Host smart-bd24a357-5b08-465d-bf8e-cbc78a571508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294425288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.294425288
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.2345167617
Short name T92
Test name
Test status
Simulation time 17747728 ps
CPU time 0.94 seconds
Started Jun 02 03:12:49 PM PDT 24
Finished Jun 02 03:12:51 PM PDT 24
Peak memory 209152 kb
Host smart-42dd3c3f-c2b3-4050-892b-bdda22e25978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345167617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.2345167617
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.2477362861
Short name T492
Test name
Test status
Simulation time 731824648 ps
CPU time 16.84 seconds
Started Jun 02 03:12:48 PM PDT 24
Finished Jun 02 03:13:06 PM PDT 24
Peak memory 218404 kb
Host smart-93b20f6d-c24f-46ea-b976-641d44c11b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477362861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.2477362861
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.2958708825
Short name T441
Test name
Test status
Simulation time 653806699 ps
CPU time 1.57 seconds
Started Jun 02 03:12:49 PM PDT 24
Finished Jun 02 03:12:51 PM PDT 24
Peak memory 217192 kb
Host smart-0e4cd538-d411-4f15-8937-f7f95da1f1e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958708825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2958708825
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.2564617711
Short name T617
Test name
Test status
Simulation time 33573291959 ps
CPU time 50.62 seconds
Started Jun 02 03:12:49 PM PDT 24
Finished Jun 02 03:13:41 PM PDT 24
Peak memory 218880 kb
Host smart-e4f8e2cf-eda8-4e50-9093-797b17892193
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564617711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.2564617711
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.4047466902
Short name T652
Test name
Test status
Simulation time 1031410578 ps
CPU time 12.9 seconds
Started Jun 02 03:12:51 PM PDT 24
Finished Jun 02 03:13:05 PM PDT 24
Peak memory 217424 kb
Host smart-e830af31-36ef-41e1-8917-3bc0b7745bb5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047466902 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.4
047466902
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.2825396171
Short name T395
Test name
Test status
Simulation time 326155946 ps
CPU time 2.39 seconds
Started Jun 02 03:12:51 PM PDT 24
Finished Jun 02 03:12:54 PM PDT 24
Peak memory 218396 kb
Host smart-147f4d60-7ef8-436d-9a28-508c33aa8355
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825396171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.2825396171
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2903121486
Short name T598
Test name
Test status
Simulation time 1883958635 ps
CPU time 24.68 seconds
Started Jun 02 03:12:51 PM PDT 24
Finished Jun 02 03:13:16 PM PDT 24
Peak memory 218016 kb
Host smart-ad7f32b5-8b4c-4253-88da-3ede0fd07ca9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903121486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2903121486
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.49952462
Short name T5
Test name
Test status
Simulation time 1558076238 ps
CPU time 5.99 seconds
Started Jun 02 03:12:49 PM PDT 24
Finished Jun 02 03:12:56 PM PDT 24
Peak memory 218072 kb
Host smart-cf0585ce-82b1-467e-a8dc-1fa8c4121209
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49952462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
moke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.49952462
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3540379480
Short name T647
Test name
Test status
Simulation time 1941647126 ps
CPU time 44.93 seconds
Started Jun 02 03:12:47 PM PDT 24
Finished Jun 02 03:13:32 PM PDT 24
Peak memory 270164 kb
Host smart-d67c7c98-70d1-409c-91dc-48bef90faf03
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540379480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3540379480
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2029494175
Short name T356
Test name
Test status
Simulation time 2137618001 ps
CPU time 10.77 seconds
Started Jun 02 03:12:49 PM PDT 24
Finished Jun 02 03:13:00 PM PDT 24
Peak memory 226680 kb
Host smart-c4c85de0-92e2-4f2b-9e55-cc98eb8d3521
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029494175 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2029494175
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.2445880945
Short name T265
Test name
Test status
Simulation time 69630156 ps
CPU time 2.43 seconds
Started Jun 02 03:12:49 PM PDT 24
Finished Jun 02 03:12:52 PM PDT 24
Peak memory 218416 kb
Host smart-1133158e-393a-4020-951f-098f04ede21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445880945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.2445880945
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.2851506936
Short name T173
Test name
Test status
Simulation time 315767571 ps
CPU time 12.54 seconds
Started Jun 02 03:12:51 PM PDT 24
Finished Jun 02 03:13:04 PM PDT 24
Peak memory 214188 kb
Host smart-ad3f9d8d-a252-4c7c-a5a1-3b85a39ebf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851506936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.2851506936
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.2470811531
Short name T38
Test name
Test status
Simulation time 573598939 ps
CPU time 12.36 seconds
Started Jun 02 03:12:53 PM PDT 24
Finished Jun 02 03:13:06 PM PDT 24
Peak memory 219288 kb
Host smart-f56583a9-9d26-4326-a41f-60ef7cb8c955
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470811531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2470811531
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.1782438089
Short name T769
Test name
Test status
Simulation time 922467705 ps
CPU time 9.66 seconds
Started Jun 02 03:12:54 PM PDT 24
Finished Jun 02 03:13:04 PM PDT 24
Peak memory 224980 kb
Host smart-393bf41e-4073-47dd-b905-20c3b995e577
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782438089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.1782438089
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2015625874
Short name T559
Test name
Test status
Simulation time 317005314 ps
CPU time 12.19 seconds
Started Jun 02 03:12:54 PM PDT 24
Finished Jun 02 03:13:07 PM PDT 24
Peak memory 226460 kb
Host smart-47c2367b-a934-456b-ad59-7cf2d0b2b212
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015625874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
015625874
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1280069576
Short name T156
Test name
Test status
Simulation time 863783739 ps
CPU time 11.89 seconds
Started Jun 02 03:12:49 PM PDT 24
Finished Jun 02 03:13:01 PM PDT 24
Peak memory 225540 kb
Host smart-1867b5e3-fe38-4c6f-96f5-cbfdfbac5d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280069576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1280069576
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3157484621
Short name T61
Test name
Test status
Simulation time 64847431 ps
CPU time 1.57 seconds
Started Jun 02 03:12:47 PM PDT 24
Finished Jun 02 03:12:50 PM PDT 24
Peak memory 213996 kb
Host smart-b8e575bb-dc0a-4ecc-8716-e238194602c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157484621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3157484621
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.746428011
Short name T693
Test name
Test status
Simulation time 543737618 ps
CPU time 27.41 seconds
Started Jun 02 03:12:49 PM PDT 24
Finished Jun 02 03:13:17 PM PDT 24
Peak memory 251248 kb
Host smart-84a3fc29-090e-47c4-9b5a-b1d470a089b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746428011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.746428011
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1647721378
Short name T631
Test name
Test status
Simulation time 93012650 ps
CPU time 3.13 seconds
Started Jun 02 03:12:48 PM PDT 24
Finished Jun 02 03:12:52 PM PDT 24
Peak memory 226720 kb
Host smart-b5d0fe4f-b18a-403c-84af-63a67f52313b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647721378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1647721378
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.702555244
Short name T428
Test name
Test status
Simulation time 26918615005 ps
CPU time 238.04 seconds
Started Jun 02 03:12:55 PM PDT 24
Finished Jun 02 03:16:54 PM PDT 24
Peak memory 276420 kb
Host smart-b5bcc10c-2071-40a7-8a41-0d1a7edbdf6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702555244 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.702555244
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.1665133636
Short name T577
Test name
Test status
Simulation time 32087640 ps
CPU time 0.89 seconds
Started Jun 02 03:12:47 PM PDT 24
Finished Jun 02 03:12:49 PM PDT 24
Peak memory 211960 kb
Host smart-793c3fc3-5d3a-449a-8965-fa63e3ddbef4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665133636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.1665133636
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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