Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46702 |
1 |
|
|
T1 |
151 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
1684 |
1 |
|
|
T1 |
9 |
|
T11 |
11 |
|
T5 |
7 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47626 |
1 |
|
|
T1 |
160 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
760 |
1 |
|
|
T41 |
15 |
|
T62 |
17 |
|
T34 |
18 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46918 |
1 |
|
|
T1 |
157 |
|
T2 |
67 |
|
T3 |
11 |
auto[1] |
1468 |
1 |
|
|
T1 |
3 |
|
T3 |
1 |
|
T9 |
11 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46798 |
1 |
|
|
T1 |
156 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
1588 |
1 |
|
|
T1 |
4 |
|
T9 |
15 |
|
T4 |
8 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46819 |
1 |
|
|
T1 |
156 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
1567 |
1 |
|
|
T1 |
4 |
|
T9 |
12 |
|
T4 |
5 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
44090 |
1 |
|
|
T1 |
114 |
|
T2 |
67 |
|
T3 |
6 |
no_err_inj |
4296 |
1 |
|
|
T1 |
46 |
|
T3 |
6 |
|
T5 |
25 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46716 |
1 |
|
|
T1 |
152 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
1670 |
1 |
|
|
T1 |
8 |
|
T11 |
9 |
|
T5 |
9 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47577 |
1 |
|
|
T1 |
160 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
809 |
1 |
|
|
T41 |
11 |
|
T62 |
17 |
|
T34 |
13 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
34780 |
1 |
|
|
T1 |
131 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
13606 |
1 |
|
|
T1 |
29 |
|
T4 |
50 |
|
T5 |
46 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46839 |
1 |
|
|
T1 |
159 |
|
T2 |
67 |
|
T3 |
11 |
auto[1] |
1547 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
8 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46884 |
1 |
|
|
T1 |
156 |
|
T2 |
67 |
|
T3 |
11 |
auto[1] |
1502 |
1 |
|
|
T1 |
4 |
|
T3 |
1 |
|
T9 |
14 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46892 |
1 |
|
|
T1 |
158 |
|
T2 |
67 |
|
T3 |
10 |
auto[1] |
1494 |
1 |
|
|
T1 |
2 |
|
T3 |
2 |
|
T9 |
14 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46791 |
1 |
|
|
T1 |
142 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
1595 |
1 |
|
|
T1 |
18 |
|
T11 |
20 |
|
T5 |
10 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46302 |
1 |
|
|
T1 |
160 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
2084 |
1 |
|
|
T5 |
32 |
|
T59 |
19 |
|
T60 |
17 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47596 |
1 |
|
|
T1 |
160 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
790 |
1 |
|
|
T41 |
11 |
|
T62 |
23 |
|
T34 |
8 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47636 |
1 |
|
|
T1 |
160 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
750 |
1 |
|
|
T41 |
13 |
|
T62 |
17 |
|
T34 |
9 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47589 |
1 |
|
|
T1 |
160 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
797 |
1 |
|
|
T41 |
20 |
|
T62 |
11 |
|
T34 |
13 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
45955 |
1 |
|
|
T1 |
108 |
|
T2 |
67 |
|
T9 |
95 |
auto[1] |
2431 |
1 |
|
|
T1 |
52 |
|
T3 |
12 |
|
T77 |
13 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
44553 |
1 |
|
|
T1 |
160 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
3833 |
1 |
|
|
T16 |
60 |
|
T20 |
80 |
|
T39 |
86 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46837 |
1 |
|
|
T1 |
156 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
1549 |
1 |
|
|
T1 |
4 |
|
T9 |
8 |
|
T4 |
7 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46920 |
1 |
|
|
T1 |
158 |
|
T2 |
67 |
|
T3 |
11 |
auto[1] |
1466 |
1 |
|
|
T1 |
2 |
|
T3 |
1 |
|
T9 |
11 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46883 |
1 |
|
|
T1 |
159 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
1503 |
1 |
|
|
T1 |
1 |
|
T9 |
2 |
|
T4 |
7 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46745 |
1 |
|
|
T1 |
147 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
1641 |
1 |
|
|
T1 |
13 |
|
T11 |
11 |
|
T5 |
9 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
43009 |
1 |
|
|
T1 |
147 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
5377 |
1 |
|
|
T1 |
13 |
|
T10 |
56 |
|
T11 |
16 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
44587 |
1 |
|
|
T1 |
160 |
|
T3 |
12 |
|
T9 |
95 |
auto[1] |
3799 |
1 |
|
|
T2 |
67 |
|
T46 |
64 |
|
T61 |
85 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48386 |
1 |
|
|
T1 |
160 |
|
T2 |
67 |
|
T3 |
12 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46759 |
1 |
|
|
T1 |
152 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
1627 |
1 |
|
|
T1 |
8 |
|
T11 |
8 |
|
T5 |
7 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46773 |
1 |
|
|
T1 |
148 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
1613 |
1 |
|
|
T1 |
12 |
|
T11 |
12 |
|
T5 |
3 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46809 |
1 |
|
|
T1 |
152 |
|
T2 |
67 |
|
T3 |
12 |
auto[1] |
1577 |
1 |
|
|
T1 |
8 |
|
T11 |
8 |
|
T5 |
8 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
42891 |
1 |
|
|
T1 |
89 |
|
T2 |
67 |
|
T9 |
95 |
auto[0] |
no_err_inj |
3064 |
1 |
|
|
T1 |
19 |
|
T5 |
25 |
|
T21 |
1 |
auto[1] |
err_inj |
1199 |
1 |
|
|
T1 |
25 |
|
T3 |
6 |
|
T77 |
7 |
auto[1] |
no_err_inj |
1232 |
1 |
|
|
T1 |
27 |
|
T3 |
6 |
|
T77 |
6 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
44633 |
1 |
|
|
T1 |
108 |
|
T2 |
67 |
|
T9 |
84 |
auto[0] |
auto[1] |
1322 |
1 |
|
|
T9 |
11 |
|
T4 |
2 |
|
T12 |
6 |
auto[1] |
auto[0] |
2287 |
1 |
|
|
T1 |
50 |
|
T3 |
11 |
|
T77 |
10 |
auto[1] |
auto[1] |
144 |
1 |
|
|
T1 |
2 |
|
T3 |
1 |
|
T77 |
3 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
44581 |
1 |
|
|
T1 |
108 |
|
T2 |
67 |
|
T9 |
81 |
auto[0] |
auto[1] |
1374 |
1 |
|
|
T9 |
14 |
|
T4 |
7 |
|
T12 |
5 |
auto[1] |
auto[0] |
2303 |
1 |
|
|
T1 |
48 |
|
T3 |
11 |
|
T77 |
11 |
auto[1] |
auto[1] |
128 |
1 |
|
|
T1 |
4 |
|
T3 |
1 |
|
T77 |
2 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
44582 |
1 |
|
|
T1 |
108 |
|
T2 |
67 |
|
T9 |
93 |
auto[0] |
auto[1] |
1373 |
1 |
|
|
T9 |
2 |
|
T4 |
7 |
|
T12 |
10 |
auto[1] |
auto[0] |
2301 |
1 |
|
|
T1 |
51 |
|
T3 |
12 |
|
T77 |
13 |
auto[1] |
auto[1] |
130 |
1 |
|
|
T1 |
1 |
|
T225 |
1 |
|
T64 |
1 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
44495 |
1 |
|
|
T1 |
108 |
|
T2 |
67 |
|
T9 |
80 |
auto[0] |
auto[1] |
1460 |
1 |
|
|
T9 |
15 |
|
T4 |
8 |
|
T12 |
7 |
auto[1] |
auto[0] |
2303 |
1 |
|
|
T1 |
48 |
|
T3 |
12 |
|
T77 |
12 |
auto[1] |
auto[1] |
128 |
1 |
|
|
T1 |
4 |
|
T77 |
1 |
|
T225 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
44529 |
1 |
|
|
T1 |
108 |
|
T2 |
67 |
|
T9 |
83 |
auto[0] |
auto[1] |
1426 |
1 |
|
|
T9 |
12 |
|
T4 |
5 |
|
T12 |
5 |
auto[1] |
auto[0] |
2290 |
1 |
|
|
T1 |
48 |
|
T3 |
12 |
|
T77 |
13 |
auto[1] |
auto[1] |
141 |
1 |
|
|
T1 |
4 |
|
T78 |
2 |
|
T194 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
44627 |
1 |
|
|
T1 |
108 |
|
T2 |
67 |
|
T9 |
84 |
auto[0] |
auto[1] |
1328 |
1 |
|
|
T9 |
11 |
|
T4 |
4 |
|
T12 |
5 |
auto[1] |
auto[0] |
2291 |
1 |
|
|
T1 |
49 |
|
T3 |
11 |
|
T77 |
13 |
auto[1] |
auto[1] |
140 |
1 |
|
|
T1 |
3 |
|
T3 |
1 |
|
T78 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33821 |
1 |
|
|
T1 |
122 |
|
T2 |
67 |
|
T3 |
12 |
auto[0] |
auto[1] |
959 |
1 |
|
|
T1 |
9 |
|
T11 |
11 |
|
T5 |
7 |
auto[1] |
auto[0] |
12881 |
1 |
|
|
T1 |
29 |
|
T4 |
50 |
|
T5 |
46 |
auto[1] |
auto[1] |
725 |
1 |
|
|
T22 |
12 |
|
T23 |
6 |
|
T14 |
10 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33816 |
1 |
|
|
T1 |
123 |
|
T2 |
67 |
|
T3 |
12 |
auto[0] |
auto[1] |
964 |
1 |
|
|
T1 |
8 |
|
T11 |
9 |
|
T5 |
9 |
auto[1] |
auto[0] |
12900 |
1 |
|
|
T1 |
29 |
|
T4 |
50 |
|
T5 |
46 |
auto[1] |
auto[1] |
706 |
1 |
|
|
T22 |
11 |
|
T23 |
10 |
|
T14 |
9 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33666 |
1 |
|
|
T1 |
131 |
|
T2 |
67 |
|
T3 |
12 |
auto[0] |
auto[1] |
1114 |
1 |
|
|
T59 |
19 |
|
T60 |
17 |
|
T226 |
8 |
auto[1] |
auto[0] |
12636 |
1 |
|
|
T1 |
29 |
|
T4 |
50 |
|
T5 |
14 |
auto[1] |
auto[1] |
970 |
1 |
|
|
T5 |
32 |
|
T40 |
6 |
|
T64 |
16 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33841 |
1 |
|
|
T1 |
113 |
|
T2 |
67 |
|
T3 |
12 |
auto[0] |
auto[1] |
939 |
1 |
|
|
T1 |
18 |
|
T11 |
20 |
|
T5 |
10 |
auto[1] |
auto[0] |
12950 |
1 |
|
|
T1 |
29 |
|
T4 |
50 |
|
T5 |
46 |
auto[1] |
auto[1] |
656 |
1 |
|
|
T22 |
10 |
|
T23 |
9 |
|
T14 |
13 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30086 |
1 |
|
|
T1 |
118 |
|
T2 |
67 |
|
T3 |
12 |
auto[0] |
auto[1] |
4694 |
1 |
|
|
T1 |
13 |
|
T10 |
56 |
|
T11 |
16 |
auto[1] |
auto[0] |
12923 |
1 |
|
|
T1 |
29 |
|
T4 |
50 |
|
T5 |
46 |
auto[1] |
auto[1] |
683 |
1 |
|
|
T22 |
13 |
|
T23 |
6 |
|
T14 |
6 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33863 |
1 |
|
|
T1 |
130 |
|
T2 |
67 |
|
T3 |
11 |
auto[0] |
auto[1] |
917 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
11 |
auto[1] |
auto[0] |
13057 |
1 |
|
|
T1 |
28 |
|
T4 |
48 |
|
T5 |
46 |
auto[1] |
auto[1] |
549 |
1 |
|
|
T1 |
1 |
|
T4 |
2 |
|
T25 |
1 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33848 |
1 |
|
|
T1 |
130 |
|
T2 |
67 |
|
T3 |
12 |
auto[0] |
auto[1] |
932 |
1 |
|
|
T1 |
1 |
|
T9 |
8 |
|
T12 |
7 |
auto[1] |
auto[0] |
12989 |
1 |
|
|
T1 |
26 |
|
T4 |
43 |
|
T5 |
46 |
auto[1] |
auto[1] |
617 |
1 |
|
|
T1 |
3 |
|
T4 |
7 |
|
T25 |
1 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33849 |
1 |
|
|
T1 |
130 |
|
T2 |
67 |
|
T3 |
11 |
auto[0] |
auto[1] |
931 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
14 |
auto[1] |
auto[0] |
13035 |
1 |
|
|
T1 |
26 |
|
T4 |
43 |
|
T5 |
46 |
auto[1] |
auto[1] |
571 |
1 |
|
|
T1 |
3 |
|
T4 |
7 |
|
T227 |
11 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33851 |
1 |
|
|
T1 |
131 |
|
T2 |
67 |
|
T3 |
11 |
auto[0] |
auto[1] |
929 |
1 |
|
|
T3 |
1 |
|
T9 |
8 |
|
T12 |
2 |
auto[1] |
auto[0] |
12988 |
1 |
|
|
T1 |
28 |
|
T4 |
45 |
|
T5 |
46 |
auto[1] |
auto[1] |
618 |
1 |
|
|
T1 |
1 |
|
T4 |
5 |
|
T25 |
1 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33807 |
1 |
|
|
T1 |
128 |
|
T2 |
67 |
|
T3 |
12 |
auto[0] |
auto[1] |
973 |
1 |
|
|
T1 |
3 |
|
T9 |
15 |
|
T12 |
7 |
auto[1] |
auto[0] |
12991 |
1 |
|
|
T1 |
28 |
|
T4 |
42 |
|
T5 |
46 |
auto[1] |
auto[1] |
615 |
1 |
|
|
T1 |
1 |
|
T4 |
8 |
|
T227 |
4 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33917 |
1 |
|
|
T1 |
130 |
|
T2 |
67 |
|
T3 |
11 |
auto[0] |
auto[1] |
863 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T9 |
11 |
auto[1] |
auto[0] |
13001 |
1 |
|
|
T1 |
27 |
|
T4 |
46 |
|
T5 |
46 |
auto[1] |
auto[1] |
605 |
1 |
|
|
T1 |
2 |
|
T4 |
4 |
|
T227 |
5 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33851 |
1 |
|
|
T1 |
123 |
|
T2 |
67 |
|
T3 |
12 |
auto[0] |
auto[1] |
929 |
1 |
|
|
T1 |
8 |
|
T11 |
8 |
|
T5 |
8 |
auto[1] |
auto[0] |
12958 |
1 |
|
|
T1 |
29 |
|
T4 |
50 |
|
T5 |
46 |
auto[1] |
auto[1] |
648 |
1 |
|
|
T22 |
14 |
|
T23 |
12 |
|
T14 |
8 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33817 |
1 |
|
|
T1 |
119 |
|
T2 |
67 |
|
T3 |
12 |
auto[0] |
auto[1] |
963 |
1 |
|
|
T1 |
12 |
|
T11 |
12 |
|
T5 |
3 |
auto[1] |
auto[0] |
12956 |
1 |
|
|
T1 |
29 |
|
T4 |
50 |
|
T5 |
46 |
auto[1] |
auto[1] |
650 |
1 |
|
|
T22 |
17 |
|
T23 |
8 |
|
T14 |
5 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
33379 |
1 |
|
|
T1 |
108 |
|
T2 |
67 |
|
T9 |
95 |
auto[0] |
auto[1] |
1401 |
1 |
|
|
T1 |
23 |
|
T3 |
12 |
|
T77 |
13 |
auto[1] |
auto[0] |
12576 |
1 |
|
|
T4 |
50 |
|
T5 |
46 |
|
T21 |
1 |
auto[1] |
auto[1] |
1030 |
1 |
|
|
T1 |
29 |
|
T25 |
13 |
|
T225 |
14 |