Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82462857

1

T1

188665

T2

50450

T3

5739

auto[1]

1238699

1

T1

1479

T3

198

T9

3861

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82435748

1

T1

188565

T2

50450

T3

5739

auto[1]

1265808

1

T1

1579

T3

198

T9

3960

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6342631	1			T1	17104		T2	6131		T3	1407
auto[IdleSt]	19583589	1			T1	25953		T2	2395		T3	1426
auto[ClkMuxSt]	33604	1			T1	133		T2	67		T3	6
auto[CntIncrSt]	33378	1			T1	133		T2	67		T3	6
auto[CntProgSt]	1337536	1			T1	708		T2	406		T3	102
auto[TransCheckSt]	25988	1			T1	112		T2	67		T3	6
auto[TokenHashSt]	29455026	1			T1	67535		T2	30961		T3	111
auto[FlashRmaSt]	26814	1			T1	135		T2	45		T3	6
auto[TokenCheck0St]	11981	1			T1	70		T2	28		T3	6
auto[TokenCheck1St]	8731	1			T1	62		T2	13		T3	6
auto[TransProgSt]	301016	1			T1	403		T3	66		T11	476
auto[PostTransSt]	11746249	1			T1	45272		T2	10270		T3	1359
auto[ScrapSt]	212019	1			T1	29		T39	9		T40	1176
auto[EscalateSt]	5687758	1			T1	18041		T3	923		T9	10859
auto[InvalidSt]	8893674	1			T1	14450		T3	506		T9	11017

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1562	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	8893674	1			T1	14450		T3	506		T9	11017
EscalateSt	5687758	1			T1	18041		T3	923		T9	10859
ScrapSt	212019	1			T1	29		T39	9		T40	1176
PostTransSt	11746249	1			T1	45272		T2	10270		T3	1359
TransProgSt	301016	1			T1	403		T3	66		T11	476
TokenCheck1St	8731	1			T1	62		T2	13		T3	6
TokenCheck0St	11981	1			T1	70		T2	28		T3	6
FlashRmaSt	26814	1			T1	135		T2	45		T3	6
TokenHashSt	29455026	1			T1	67535		T2	30961		T3	111
TransCheckSt	25988	1			T1	112		T2	67		T3	6
CntProgSt	1337536	1			T1	708		T2	406		T3	102
CntIncrSt	33378	1			T1	133		T2	67		T3	6
ClkMuxSt	33604	1			T1	133		T2	67		T3	6
IdleSt	19583589	1			T1	25953		T2	2395		T3	1426
ResetSt	6342631	1			T1	17104		T2	6131		T3	1407
arcs[ResetSt=>IdleSt]	48832	1			T1	164		T2	68		T3	11
arcs[IdleSt=>ScrapSt]	263	1			T1	2		T39	3		T40	4
arcs[IdleSt=>ClkMuxSt]	33443	1			T1	133		T2	67		T3	6
arcs[ClkMuxSt=>CntIncrSt]	33378	1			T1	133		T2	67		T3	6
arcs[CntIncrSt=>PostTransSt]	1616	1			T1	12		T11	12		T5	3
arcs[CntIncrSt=>CntProgSt]	31701	1			T1	121		T2	67		T3	6
arcs[CntProgSt=>PostTransSt]	4486	1			T1	9		T11	11		T5	39
arcs[CntProgSt=>TransCheckSt]	25988	1			T1	112		T2	67		T3	6
arcs[TransCheckSt=>PostTransSt]	3485	1			T1	8		T2	30		T11	8
arcs[TransCheckSt=>TokenHashSt]	22417	1			T1	104		T2	37		T3	6
arcs[TokenHashSt=>PostTransSt]	9624	1			T1	34		T2	9		T10	56
arcs[TokenHashSt=>FlashRmaSt]	12088	1			T1	70		T2	28		T3	6
arcs[FlashRmaSt=>TokenCheck0St]	11981	1			T1	70		T2	28		T3	6
arcs[TokenCheck0St=>PostTransSt]	3212	1			T1	8		T2	15		T11	8
arcs[TokenCheck0St=>TokenCheck1St]	8731	1			T1	62		T2	13		T3	6
arcs[TokenCheck1St=>PostTransSt]	645	1			T2	13		T5	1		T46	6
arcs[TransProgSt=>PostTransSt]	7141	1			T1	62		T3	6		T11	21
arcs[IdleSt=>EscalateSt]	119	1			T49	5		T50	7		T51	4
arcs[ClkMuxSt=>EscalateSt]	65	1			T16	1		T20	1		T39	2
arcs[CntIncrSt=>EscalateSt]	61	1			T16	1		T47	1		T48	1
arcs[CntProgSt=>EscalateSt]	1227	1			T16	24		T20	12		T39	31
arcs[TransCheckSt=>EscalateSt]	86	1			T16	1		T20	4		T47	6
arcs[TokenHashSt=>EscalateSt]	705	1			T16	7		T20	26		T19	1
arcs[FlashRmaSt=>EscalateSt]	107	1			T16	1		T20	2		T39	3
arcs[TokenCheck0St=>EscalateSt]	38	1			T16	1		T39	3		T47	2
arcs[TokenCheck1St=>EscalateSt]	139	1			T16	4		T20	3		T39	1
arcs[TransProgSt=>EscalateSt]	806	1			T16	15		T20	10		T19	1
arcs[PostTransSt=>EscalateSt]	4678	1			T1	9		T11	11		T5	39
arcs[InvalidSt=>EscalateSt]	11447	1			T1	22		T3	4		T9	79

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6342436	1			T1	17104		T2	6131		T3	1407
auto[0]	auto[IdleSt]	19583512	1			T1	25953		T2	2395		T3	1426
auto[0]	auto[ClkMuxSt]	33563	1			T1	133		T2	67		T3	6
auto[0]	auto[CntIncrSt]	33339	1			T1	133		T2	67		T3	6
auto[0]	auto[CntProgSt]	1336704	1			T1	708		T2	406		T3	102
auto[0]	auto[TransCheckSt]	25936	1			T1	112		T2	67		T3	6
auto[0]	auto[TokenHashSt]	29454569	1			T1	67535		T2	30961		T3	111
auto[0]	auto[FlashRmaSt]	26743	1			T1	135		T2	45		T3	6
auto[0]	auto[TokenCheck0St]	11955	1			T1	70		T2	28		T3	6
auto[0]	auto[TokenCheck1St]	8642	1			T1	62		T2	13		T3	6
auto[0]	auto[TransProgSt]	300483	1			T1	403		T3	66		T11	476
auto[0]	auto[PostTransSt]	11743844	1			T1	45266		T2	10270		T3	1359
auto[0]	auto[ScrapSt]	211977	1			T1	29		T39	6		T40	1176
auto[0]	auto[EscalateSt]	4459512	1			T1	16577		T3	727		T9	7037
auto[0]	auto[InvalidSt]	8888080	1			T1	14441		T3	504		T9	10978
auto[1]	auto[ResetSt]	195	1			T16	5		T20	5		T39	4
auto[1]	auto[IdleSt]	77	1			T49	4		T50	5		T51	3
auto[1]	auto[ClkMuxSt]	41	1			T47	1		T49	1		T48	1
auto[1]	auto[CntIncrSt]	39	1			T47	1		T48	1		T56	1
auto[1]	auto[CntProgSt]	832	1			T16	21		T20	10		T39	20
auto[1]	auto[TransCheckSt]	52	1			T16	1		T20	3		T47	3
auto[1]	auto[TokenHashSt]	457	1			T16	6		T20	14		T19	1
auto[1]	auto[FlashRmaSt]	71	1			T16	1		T39	3		T48	1
auto[1]	auto[TokenCheck0St]	26	1			T16	1		T39	2		T47	2
auto[1]	auto[TokenCheck1St]	89	1			T16	4		T20	2		T39	1
auto[1]	auto[TransProgSt]	533	1			T16	8		T20	6		T39	12
auto[1]	auto[PostTransSt]	2405	1			T1	6		T11	8		T5	17
auto[1]	auto[ScrapSt]	42	1			T39	3		T47	1		T49	1
auto[1]	auto[EscalateSt]	1228246	1			T1	1464		T3	196		T9	3822
auto[1]	auto[InvalidSt]	5594	1			T1	9		T3	2		T9	39

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6342446	1			T1	17104		T2	6131		T3	1407
auto[0]	auto[IdleSt]	19583503	1			T1	25953		T2	2395		T3	1426
auto[0]	auto[ClkMuxSt]	33564	1			T1	133		T2	67		T3	6
auto[0]	auto[CntIncrSt]	33339	1			T1	133		T2	67		T3	6
auto[0]	auto[CntProgSt]	1336718	1			T1	708		T2	406		T3	102
auto[0]	auto[TransCheckSt]	25931	1			T1	112		T2	67		T3	6
auto[0]	auto[TokenHashSt]	29454528	1			T1	67535		T2	30961		T3	111
auto[0]	auto[FlashRmaSt]	26739	1			T1	135		T2	45		T3	6
auto[0]	auto[TokenCheck0St]	11957	1			T1	70		T2	28		T3	6
auto[0]	auto[TokenCheck1St]	8642	1			T1	62		T2	13		T3	6
auto[0]	auto[TransProgSt]	300454	1			T1	403		T3	66		T11	476
auto[0]	auto[PostTransSt]	11743918	1			T1	45269		T2	10270		T3	1359
auto[0]	auto[ScrapSt]	211979	1			T1	29		T39	7		T40	1176
auto[0]	auto[EscalateSt]	4432647	1			T1	16478		T3	727		T9	6939
auto[0]	auto[InvalidSt]	8887821	1			T1	14437		T3	504		T9	10977
auto[1]	auto[ResetSt]	185	1			T16	1		T20	5		T39	3
auto[1]	auto[IdleSt]	86	1			T49	4		T50	5		T51	2
auto[1]	auto[ClkMuxSt]	40	1			T16	1		T20	1		T39	2
auto[1]	auto[CntIncrSt]	39	1			T16	1		T48	1		T224	1
auto[1]	auto[CntProgSt]	818	1			T16	12		T20	6		T39	24
auto[1]	auto[TransCheckSt]	57	1			T16	1		T20	2		T47	3
auto[1]	auto[TokenHashSt]	498	1			T16	4		T20	22		T39	7
auto[1]	auto[FlashRmaSt]	75	1			T16	1		T20	2		T39	1
auto[1]	auto[TokenCheck0St]	24	1			T16	1		T39	3		T47	1
auto[1]	auto[TokenCheck1St]	89	1			T16	2		T20	1		T39	1
auto[1]	auto[TransProgSt]	562	1			T16	13		T20	8		T19	1
auto[1]	auto[PostTransSt]	2331	1			T1	3		T11	3		T5	22
auto[1]	auto[ScrapSt]	40	1			T39	2		T49	3		T48	1
auto[1]	auto[EscalateSt]	1255111	1			T1	1563		T3	196		T9	3920
auto[1]	auto[InvalidSt]	5853	1			T1	13		T3	2		T9	40