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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.19 97.82 95.84 93.31 100.00 98.52 98.76 96.11


Total test records in report: 995
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T803 /workspace/coverage/default/22.lc_ctrl_sec_mubi.1056966933 Jun 04 02:16:22 PM PDT 24 Jun 04 02:16:39 PM PDT 24 1190538312 ps
T804 /workspace/coverage/default/6.lc_ctrl_jtag_access.356512087 Jun 04 02:14:10 PM PDT 24 Jun 04 02:14:18 PM PDT 24 219626548 ps
T805 /workspace/coverage/default/4.lc_ctrl_stress_all.3925496174 Jun 04 02:13:45 PM PDT 24 Jun 04 02:15:02 PM PDT 24 2235536018 ps
T806 /workspace/coverage/default/37.lc_ctrl_smoke.209320558 Jun 04 02:17:40 PM PDT 24 Jun 04 02:17:45 PM PDT 24 59641050 ps
T807 /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1692077524 Jun 04 02:17:21 PM PDT 24 Jun 04 02:17:32 PM PDT 24 1303356285 ps
T808 /workspace/coverage/default/13.lc_ctrl_prog_failure.581712739 Jun 04 02:15:15 PM PDT 24 Jun 04 02:15:19 PM PDT 24 232932562 ps
T809 /workspace/coverage/default/40.lc_ctrl_security_escalation.1766584316 Jun 04 02:17:59 PM PDT 24 Jun 04 02:18:07 PM PDT 24 450079372 ps
T810 /workspace/coverage/default/49.lc_ctrl_state_failure.1518867303 Jun 04 02:18:37 PM PDT 24 Jun 04 02:19:08 PM PDT 24 714360352 ps
T811 /workspace/coverage/default/47.lc_ctrl_state_failure.2963455061 Jun 04 02:18:23 PM PDT 24 Jun 04 02:18:50 PM PDT 24 3880383766 ps
T812 /workspace/coverage/default/0.lc_ctrl_prog_failure.1405925167 Jun 04 02:12:20 PM PDT 24 Jun 04 02:12:22 PM PDT 24 61337442 ps
T813 /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.664777772 Jun 04 02:17:49 PM PDT 24 Jun 04 02:17:51 PM PDT 24 14715517 ps
T814 /workspace/coverage/default/39.lc_ctrl_prog_failure.870932873 Jun 04 02:17:46 PM PDT 24 Jun 04 02:17:50 PM PDT 24 306153719 ps
T815 /workspace/coverage/default/44.lc_ctrl_sec_mubi.452630938 Jun 04 02:18:17 PM PDT 24 Jun 04 02:18:34 PM PDT 24 603708281 ps
T816 /workspace/coverage/default/6.lc_ctrl_jtag_priority.2227128651 Jun 04 02:14:10 PM PDT 24 Jun 04 02:14:15 PM PDT 24 5274344643 ps
T817 /workspace/coverage/default/47.lc_ctrl_alert_test.2383190332 Jun 04 02:18:30 PM PDT 24 Jun 04 02:18:31 PM PDT 24 21526149 ps
T818 /workspace/coverage/default/18.lc_ctrl_errors.1745254116 Jun 04 02:15:59 PM PDT 24 Jun 04 02:16:10 PM PDT 24 1658201685 ps
T819 /workspace/coverage/default/5.lc_ctrl_regwen_during_op.665482611 Jun 04 02:13:53 PM PDT 24 Jun 04 02:14:02 PM PDT 24 975426409 ps
T820 /workspace/coverage/default/4.lc_ctrl_sec_token_digest.356626503 Jun 04 02:13:51 PM PDT 24 Jun 04 02:14:02 PM PDT 24 446814321 ps
T821 /workspace/coverage/default/1.lc_ctrl_stress_all.2362644560 Jun 04 02:13:00 PM PDT 24 Jun 04 02:13:41 PM PDT 24 3162424902 ps
T171 /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.2473793339 Jun 04 02:17:10 PM PDT 24 Jun 04 02:25:26 PM PDT 24 62412670432 ps
T822 /workspace/coverage/default/15.lc_ctrl_stress_all.3284314910 Jun 04 02:15:44 PM PDT 24 Jun 04 02:16:19 PM PDT 24 2210436747 ps
T823 /workspace/coverage/default/8.lc_ctrl_sec_token_mux.4065654810 Jun 04 02:14:43 PM PDT 24 Jun 04 02:14:49 PM PDT 24 409230839 ps
T824 /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3614528255 Jun 04 02:16:23 PM PDT 24 Jun 04 02:16:32 PM PDT 24 1527838855 ps
T825 /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2337009314 Jun 04 02:15:47 PM PDT 24 Jun 04 02:15:58 PM PDT 24 1143870884 ps
T826 /workspace/coverage/default/45.lc_ctrl_sec_token_digest.290567488 Jun 04 02:18:24 PM PDT 24 Jun 04 02:18:45 PM PDT 24 1068541540 ps
T827 /workspace/coverage/default/14.lc_ctrl_jtag_access.3550204936 Jun 04 02:15:32 PM PDT 24 Jun 04 02:15:35 PM PDT 24 127513572 ps
T828 /workspace/coverage/default/19.lc_ctrl_security_escalation.591449102 Jun 04 02:16:01 PM PDT 24 Jun 04 02:16:15 PM PDT 24 819911164 ps
T829 /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3269454404 Jun 04 02:13:15 PM PDT 24 Jun 04 02:13:27 PM PDT 24 2719770571 ps
T830 /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1574813080 Jun 04 02:18:16 PM PDT 24 Jun 04 02:18:27 PM PDT 24 520845503 ps
T831 /workspace/coverage/default/22.lc_ctrl_alert_test.460887651 Jun 04 02:16:30 PM PDT 24 Jun 04 02:16:32 PM PDT 24 27393254 ps
T832 /workspace/coverage/default/32.lc_ctrl_state_post_trans.1667450055 Jun 04 02:17:17 PM PDT 24 Jun 04 02:17:25 PM PDT 24 312522089 ps
T833 /workspace/coverage/default/13.lc_ctrl_jtag_smoke.4006954559 Jun 04 02:15:21 PM PDT 24 Jun 04 02:15:24 PM PDT 24 95283417 ps
T834 /workspace/coverage/default/23.lc_ctrl_sec_mubi.2960517570 Jun 04 02:16:33 PM PDT 24 Jun 04 02:16:42 PM PDT 24 853008331 ps
T835 /workspace/coverage/default/49.lc_ctrl_prog_failure.1605322379 Jun 04 02:18:38 PM PDT 24 Jun 04 02:18:43 PM PDT 24 101698306 ps
T836 /workspace/coverage/default/6.lc_ctrl_errors.2670495637 Jun 04 02:14:12 PM PDT 24 Jun 04 02:14:31 PM PDT 24 2499583563 ps
T837 /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.4010812816 Jun 04 02:13:33 PM PDT 24 Jun 04 02:13:59 PM PDT 24 1196743580 ps
T838 /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2865777180 Jun 04 02:17:33 PM PDT 24 Jun 04 02:17:35 PM PDT 24 13714275 ps
T839 /workspace/coverage/default/28.lc_ctrl_state_post_trans.1249529641 Jun 04 02:16:53 PM PDT 24 Jun 04 02:17:01 PM PDT 24 194208316 ps
T840 /workspace/coverage/default/18.lc_ctrl_state_post_trans.3859825214 Jun 04 02:16:00 PM PDT 24 Jun 04 02:16:09 PM PDT 24 222789682 ps
T841 /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1348315239 Jun 04 02:15:05 PM PDT 24 Jun 04 02:15:06 PM PDT 24 20306460 ps
T842 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1513168998 Jun 04 02:18:17 PM PDT 24 Jun 04 02:18:28 PM PDT 24 363641708 ps
T843 /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3019523329 Jun 04 02:16:08 PM PDT 24 Jun 04 02:16:10 PM PDT 24 14522106 ps
T844 /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2274057538 Jun 04 02:16:25 PM PDT 24 Jun 04 02:16:34 PM PDT 24 1121069110 ps
T845 /workspace/coverage/default/41.lc_ctrl_jtag_access.1419647281 Jun 04 02:18:01 PM PDT 24 Jun 04 02:18:14 PM PDT 24 2168197963 ps
T846 /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2573480582 Jun 04 02:15:13 PM PDT 24 Jun 04 02:15:51 PM PDT 24 2846175935 ps
T847 /workspace/coverage/default/30.lc_ctrl_stress_all.4263916340 Jun 04 02:17:15 PM PDT 24 Jun 04 02:17:36 PM PDT 24 2199922397 ps
T848 /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.34768110 Jun 04 02:13:09 PM PDT 24 Jun 04 02:13:34 PM PDT 24 1616468678 ps
T849 /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1309200363 Jun 04 02:16:18 PM PDT 24 Jun 04 02:16:33 PM PDT 24 7322640990 ps
T850 /workspace/coverage/default/18.lc_ctrl_jtag_access.1772936999 Jun 04 02:16:00 PM PDT 24 Jun 04 02:16:09 PM PDT 24 778943455 ps
T851 /workspace/coverage/default/25.lc_ctrl_alert_test.2449635074 Jun 04 02:16:48 PM PDT 24 Jun 04 02:16:49 PM PDT 24 15585827 ps
T852 /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2362600832 Jun 04 02:14:08 PM PDT 24 Jun 04 02:14:19 PM PDT 24 390364175 ps
T853 /workspace/coverage/default/16.lc_ctrl_errors.290022172 Jun 04 02:15:45 PM PDT 24 Jun 04 02:15:57 PM PDT 24 942037705 ps
T854 /workspace/coverage/default/4.lc_ctrl_state_post_trans.1385426575 Jun 04 02:13:39 PM PDT 24 Jun 04 02:13:43 PM PDT 24 98210811 ps
T855 /workspace/coverage/default/12.lc_ctrl_state_post_trans.1811520793 Jun 04 02:15:05 PM PDT 24 Jun 04 02:15:09 PM PDT 24 424069914 ps
T856 /workspace/coverage/default/35.lc_ctrl_errors.613206403 Jun 04 02:17:34 PM PDT 24 Jun 04 02:17:49 PM PDT 24 332836699 ps
T857 /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.4095006439 Jun 04 02:15:15 PM PDT 24 Jun 04 02:15:21 PM PDT 24 277329774 ps
T858 /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2963080429 Jun 04 02:15:22 PM PDT 24 Jun 04 02:15:32 PM PDT 24 328042010 ps
T859 /workspace/coverage/default/41.lc_ctrl_errors.3862258649 Jun 04 02:18:03 PM PDT 24 Jun 04 02:18:14 PM PDT 24 192197795 ps
T860 /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3117108573 Jun 04 02:15:36 PM PDT 24 Jun 04 02:16:56 PM PDT 24 2442445228 ps
T861 /workspace/coverage/default/47.lc_ctrl_errors.1624112313 Jun 04 02:18:25 PM PDT 24 Jun 04 02:18:40 PM PDT 24 1291611917 ps
T121 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2636896688 Jun 04 01:18:06 PM PDT 24 Jun 04 01:18:08 PM PDT 24 17627397 ps
T127 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.604366540 Jun 04 01:16:56 PM PDT 24 Jun 04 01:17:24 PM PDT 24 4915048505 ps
T128 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3929468114 Jun 04 01:17:57 PM PDT 24 Jun 04 01:17:59 PM PDT 24 87394704 ps
T115 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1339282917 Jun 04 01:18:13 PM PDT 24 Jun 04 01:18:17 PM PDT 24 526747912 ps
T116 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.418253637 Jun 04 01:17:34 PM PDT 24 Jun 04 01:17:38 PM PDT 24 79763317 ps
T117 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2620709758 Jun 04 01:18:29 PM PDT 24 Jun 04 01:18:34 PM PDT 24 566790757 ps
T147 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.18040075 Jun 04 01:17:00 PM PDT 24 Jun 04 01:17:06 PM PDT 24 515446947 ps
T218 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2717171380 Jun 04 01:18:00 PM PDT 24 Jun 04 01:18:10 PM PDT 24 424051042 ps
T122 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.767308870 Jun 04 01:18:38 PM PDT 24 Jun 04 01:18:41 PM PDT 24 73561739 ps
T862 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3942375128 Jun 04 01:17:35 PM PDT 24 Jun 04 01:17:36 PM PDT 24 16819934 ps
T120 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3165259576 Jun 04 01:18:28 PM PDT 24 Jun 04 01:18:30 PM PDT 24 113017514 ps
T118 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.452409065 Jun 04 01:17:11 PM PDT 24 Jun 04 01:17:14 PM PDT 24 124135394 ps
T126 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1815996077 Jun 04 01:18:19 PM PDT 24 Jun 04 01:18:22 PM PDT 24 150755133 ps
T130 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2780047963 Jun 04 01:17:56 PM PDT 24 Jun 04 01:18:01 PM PDT 24 104026155 ps
T863 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1740079680 Jun 04 01:17:15 PM PDT 24 Jun 04 01:17:39 PM PDT 24 944450739 ps
T119 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2645602716 Jun 04 01:17:21 PM PDT 24 Jun 04 01:17:27 PM PDT 24 278172169 ps
T864 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2120822281 Jun 04 01:18:01 PM PDT 24 Jun 04 01:18:04 PM PDT 24 75667955 ps
T198 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.4175423535 Jun 04 01:17:21 PM PDT 24 Jun 04 01:17:23 PM PDT 24 127390140 ps
T209 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1544350273 Jun 04 01:17:50 PM PDT 24 Jun 04 01:17:52 PM PDT 24 73455108 ps
T210 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1130354663 Jun 04 01:18:27 PM PDT 24 Jun 04 01:18:30 PM PDT 24 39697849 ps
T865 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2733372266 Jun 04 01:17:05 PM PDT 24 Jun 04 01:17:08 PM PDT 24 292272218 ps
T144 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2917422504 Jun 04 01:18:05 PM PDT 24 Jun 04 01:18:10 PM PDT 24 118305033 ps
T123 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1764602759 Jun 04 01:18:18 PM PDT 24 Jun 04 01:18:21 PM PDT 24 61062480 ps
T132 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4274020376 Jun 04 01:17:54 PM PDT 24 Jun 04 01:17:57 PM PDT 24 104606802 ps
T866 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1289275084 Jun 04 01:17:06 PM PDT 24 Jun 04 01:17:10 PM PDT 24 181279210 ps
T199 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2010056596 Jun 04 01:17:51 PM PDT 24 Jun 04 01:17:53 PM PDT 24 38191739 ps
T211 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2196116336 Jun 04 01:18:28 PM PDT 24 Jun 04 01:18:30 PM PDT 24 20037729 ps
T200 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.715566231 Jun 04 01:17:06 PM PDT 24 Jun 04 01:17:08 PM PDT 24 13729504 ps
T170 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3369517660 Jun 04 01:18:06 PM PDT 24 Jun 04 01:18:08 PM PDT 24 62032389 ps
T145 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.737299391 Jun 04 01:18:05 PM PDT 24 Jun 04 01:18:07 PM PDT 24 64340920 ps
T867 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1523170446 Jun 04 01:18:27 PM PDT 24 Jun 04 01:18:29 PM PDT 24 13930129 ps
T868 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1668054878 Jun 04 01:17:27 PM PDT 24 Jun 04 01:17:33 PM PDT 24 169816274 ps
T146 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3623545756 Jun 04 01:17:50 PM PDT 24 Jun 04 01:17:53 PM PDT 24 57466825 ps
T212 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3071185681 Jun 04 01:17:58 PM PDT 24 Jun 04 01:18:00 PM PDT 24 103289028 ps
T140 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.4075265886 Jun 04 01:18:06 PM PDT 24 Jun 04 01:18:09 PM PDT 24 101044278 ps
T869 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.147479526 Jun 04 01:17:51 PM PDT 24 Jun 04 01:17:53 PM PDT 24 15612344 ps
T870 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.882544938 Jun 04 01:18:00 PM PDT 24 Jun 04 01:18:02 PM PDT 24 47252411 ps
T871 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1021920332 Jun 04 01:18:08 PM PDT 24 Jun 04 01:18:27 PM PDT 24 699445186 ps
T872 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.194637621 Jun 04 01:18:07 PM PDT 24 Jun 04 01:18:09 PM PDT 24 593461611 ps
T873 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.804991209 Jun 04 01:18:38 PM PDT 24 Jun 04 01:18:40 PM PDT 24 80410272 ps
T874 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.909197580 Jun 04 01:17:51 PM PDT 24 Jun 04 01:17:53 PM PDT 24 14458517 ps
T875 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2960113397 Jun 04 01:17:59 PM PDT 24 Jun 04 01:18:23 PM PDT 24 975397767 ps
T876 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2007072793 Jun 04 01:17:43 PM PDT 24 Jun 04 01:17:46 PM PDT 24 24508231 ps
T124 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3334274555 Jun 04 01:18:28 PM PDT 24 Jun 04 01:18:32 PM PDT 24 79044448 ps
T877 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1286120309 Jun 04 01:18:16 PM PDT 24 Jun 04 01:18:17 PM PDT 24 17527053 ps
T878 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3561176780 Jun 04 01:17:28 PM PDT 24 Jun 04 01:17:31 PM PDT 24 414714211 ps
T879 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.434307136 Jun 04 01:18:19 PM PDT 24 Jun 04 01:18:23 PM PDT 24 495303543 ps
T880 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3520008337 Jun 04 01:18:20 PM PDT 24 Jun 04 01:18:23 PM PDT 24 28697614 ps
T881 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.878545061 Jun 04 01:17:44 PM PDT 24 Jun 04 01:17:47 PM PDT 24 521854519 ps
T213 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1556977265 Jun 04 01:17:13 PM PDT 24 Jun 04 01:17:15 PM PDT 24 200106723 ps
T214 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2004932080 Jun 04 01:18:21 PM PDT 24 Jun 04 01:18:23 PM PDT 24 28141066 ps
T201 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.384360492 Jun 04 01:18:36 PM PDT 24 Jun 04 01:18:37 PM PDT 24 23998787 ps
T882 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1202508033 Jun 04 01:17:06 PM PDT 24 Jun 04 01:17:08 PM PDT 24 37685064 ps
T883 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2952231215 Jun 04 01:17:07 PM PDT 24 Jun 04 01:17:09 PM PDT 24 18531424 ps
T884 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2585677917 Jun 04 01:17:50 PM PDT 24 Jun 04 01:17:52 PM PDT 24 55343439 ps
T885 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3322092765 Jun 04 01:18:21 PM PDT 24 Jun 04 01:18:23 PM PDT 24 128013658 ps
T886 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3259490188 Jun 04 01:17:43 PM PDT 24 Jun 04 01:17:46 PM PDT 24 349428466 ps
T135 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1734071284 Jun 04 01:18:37 PM PDT 24 Jun 04 01:18:42 PM PDT 24 2301743228 ps
T887 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.608861212 Jun 04 01:18:28 PM PDT 24 Jun 04 01:18:31 PM PDT 24 29396002 ps
T215 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.870840197 Jun 04 01:18:07 PM PDT 24 Jun 04 01:18:08 PM PDT 24 55271202 ps
T888 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2584374543 Jun 04 01:17:06 PM PDT 24 Jun 04 01:17:09 PM PDT 24 73337791 ps
T889 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1064407124 Jun 04 01:17:22 PM PDT 24 Jun 04 01:17:29 PM PDT 24 209578723 ps
T890 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.4225235233 Jun 04 01:17:21 PM PDT 24 Jun 04 01:17:23 PM PDT 24 29717124 ps
T891 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.4032101415 Jun 04 01:18:19 PM PDT 24 Jun 04 01:18:21 PM PDT 24 21593328 ps
T892 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1032655709 Jun 04 01:18:15 PM PDT 24 Jun 04 01:18:17 PM PDT 24 83361343 ps
T202 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1692559148 Jun 04 01:17:35 PM PDT 24 Jun 04 01:17:36 PM PDT 24 16951402 ps
T203 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.475722872 Jun 04 01:17:15 PM PDT 24 Jun 04 01:17:17 PM PDT 24 123726150 ps
T893 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2783655491 Jun 04 01:17:59 PM PDT 24 Jun 04 01:18:18 PM PDT 24 3258272290 ps
T216 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3075074742 Jun 04 01:17:21 PM PDT 24 Jun 04 01:17:23 PM PDT 24 28709916 ps
T894 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1839588375 Jun 04 01:18:27 PM PDT 24 Jun 04 01:18:32 PM PDT 24 45703497 ps
T895 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3716326228 Jun 04 01:17:06 PM PDT 24 Jun 04 01:17:14 PM PDT 24 2817554448 ps
T896 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.4202431457 Jun 04 01:17:59 PM PDT 24 Jun 04 01:18:02 PM PDT 24 151029972 ps
T897 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3865740930 Jun 04 01:17:12 PM PDT 24 Jun 04 01:17:14 PM PDT 24 37762615 ps
T898 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.44163528 Jun 04 01:17:51 PM PDT 24 Jun 04 01:18:01 PM PDT 24 413738092 ps
T899 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3375648279 Jun 04 01:16:56 PM PDT 24 Jun 04 01:16:58 PM PDT 24 46105430 ps
T900 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.160113400 Jun 04 01:17:28 PM PDT 24 Jun 04 01:17:35 PM PDT 24 351802051 ps
T901 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1982120031 Jun 04 01:17:45 PM PDT 24 Jun 04 01:17:54 PM PDT 24 835567283 ps
T902 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3020227202 Jun 04 01:17:51 PM PDT 24 Jun 04 01:17:54 PM PDT 24 556554567 ps
T903 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2017243053 Jun 04 01:17:05 PM PDT 24 Jun 04 01:17:07 PM PDT 24 88099758 ps
T137 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.251002343 Jun 04 01:18:27 PM PDT 24 Jun 04 01:18:30 PM PDT 24 46279762 ps
T904 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3740503505 Jun 04 01:17:43 PM PDT 24 Jun 04 01:17:45 PM PDT 24 37365782 ps
T905 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1872750095 Jun 04 01:17:06 PM PDT 24 Jun 04 01:17:09 PM PDT 24 145298173 ps
T906 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.645787088 Jun 04 01:17:59 PM PDT 24 Jun 04 01:18:01 PM PDT 24 51403618 ps
T907 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4254175281 Jun 04 01:18:28 PM PDT 24 Jun 04 01:18:29 PM PDT 24 36774684 ps
T141 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2432401398 Jun 04 01:18:00 PM PDT 24 Jun 04 01:18:03 PM PDT 24 137874940 ps
T908 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.745351501 Jun 04 01:17:51 PM PDT 24 Jun 04 01:17:54 PM PDT 24 128505181 ps
T909 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2486080150 Jun 04 01:17:52 PM PDT 24 Jun 04 01:17:54 PM PDT 24 73241999 ps
T910 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.4280794327 Jun 04 01:17:20 PM PDT 24 Jun 04 01:17:21 PM PDT 24 58691604 ps
T125 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.986122640 Jun 04 01:17:42 PM PDT 24 Jun 04 01:17:47 PM PDT 24 85967651 ps
T911 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3074201241 Jun 04 01:18:37 PM PDT 24 Jun 04 01:18:39 PM PDT 24 165916327 ps
T912 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3150227161 Jun 04 01:18:09 PM PDT 24 Jun 04 01:18:12 PM PDT 24 31854267 ps
T913 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1647317989 Jun 04 01:17:58 PM PDT 24 Jun 04 01:18:00 PM PDT 24 227021789 ps
T914 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1056619299 Jun 04 01:18:20 PM PDT 24 Jun 04 01:18:22 PM PDT 24 37323117 ps
T915 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3267331785 Jun 04 01:18:16 PM PDT 24 Jun 04 01:18:19 PM PDT 24 83119897 ps
T916 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1013509387 Jun 04 01:18:27 PM PDT 24 Jun 04 01:18:30 PM PDT 24 31262245 ps
T917 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.958540540 Jun 04 01:17:53 PM PDT 24 Jun 04 01:18:10 PM PDT 24 1372736655 ps
T918 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3352394681 Jun 04 01:16:57 PM PDT 24 Jun 04 01:17:00 PM PDT 24 295498236 ps
T919 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2999423186 Jun 04 01:17:51 PM PDT 24 Jun 04 01:17:55 PM PDT 24 145463931 ps
T920 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.896851596 Jun 04 01:17:07 PM PDT 24 Jun 04 01:17:09 PM PDT 24 1542076636 ps
T921 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1995610799 Jun 04 01:17:12 PM PDT 24 Jun 04 01:17:15 PM PDT 24 126244574 ps
T922 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.709092483 Jun 04 01:17:28 PM PDT 24 Jun 04 01:17:35 PM PDT 24 3086117188 ps
T204 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2103728434 Jun 04 01:17:06 PM PDT 24 Jun 04 01:17:09 PM PDT 24 45776395 ps
T923 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1915245565 Jun 04 01:17:59 PM PDT 24 Jun 04 01:18:02 PM PDT 24 173873635 ps
T924 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2356143973 Jun 04 01:17:12 PM PDT 24 Jun 04 01:17:15 PM PDT 24 41885207 ps
T205 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3396748552 Jun 04 01:18:14 PM PDT 24 Jun 04 01:18:16 PM PDT 24 14636303 ps
T206 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1977845709 Jun 04 01:17:38 PM PDT 24 Jun 04 01:17:39 PM PDT 24 151946029 ps
T129 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2695955645 Jun 04 01:18:27 PM PDT 24 Jun 04 01:18:31 PM PDT 24 80049363 ps
T925 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2021864508 Jun 04 01:17:28 PM PDT 24 Jun 04 01:17:31 PM PDT 24 59102625 ps
T926 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2684745338 Jun 04 01:17:50 PM PDT 24 Jun 04 01:17:52 PM PDT 24 49872886 ps
T927 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3322896991 Jun 04 01:18:13 PM PDT 24 Jun 04 01:18:16 PM PDT 24 23250544 ps
T928 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2939274171 Jun 04 01:17:59 PM PDT 24 Jun 04 01:18:05 PM PDT 24 127297014 ps
T929 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3536127333 Jun 04 01:17:13 PM PDT 24 Jun 04 01:17:16 PM PDT 24 223794052 ps
T930 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2468897875 Jun 04 01:17:13 PM PDT 24 Jun 04 01:17:15 PM PDT 24 159075682 ps
T931 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2015565354 Jun 04 01:18:21 PM PDT 24 Jun 04 01:18:23 PM PDT 24 23189354 ps
T932 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4014574658 Jun 04 01:17:15 PM PDT 24 Jun 04 01:17:30 PM PDT 24 4030859430 ps
T933 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2838925938 Jun 04 01:18:22 PM PDT 24 Jun 04 01:18:25 PM PDT 24 20566035 ps
T934 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2986499398 Jun 04 01:17:59 PM PDT 24 Jun 04 01:18:01 PM PDT 24 29263091 ps
T935 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1287349646 Jun 04 01:17:51 PM PDT 24 Jun 04 01:17:53 PM PDT 24 44827310 ps
T936 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3174874047 Jun 04 01:17:35 PM PDT 24 Jun 04 01:17:37 PM PDT 24 67171404 ps
T138 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.884649448 Jun 04 01:18:14 PM PDT 24 Jun 04 01:18:18 PM PDT 24 142252151 ps
T937 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.570347864 Jun 04 01:18:13 PM PDT 24 Jun 04 01:18:15 PM PDT 24 81190818 ps
T938 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2105443354 Jun 04 01:17:53 PM PDT 24 Jun 04 01:17:58 PM PDT 24 3061761144 ps
T939 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.391893609 Jun 04 01:17:57 PM PDT 24 Jun 04 01:17:59 PM PDT 24 38389273 ps
T940 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2054807088 Jun 04 01:17:58 PM PDT 24 Jun 04 01:18:00 PM PDT 24 74528275 ps
T139 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1464254426 Jun 04 01:18:21 PM PDT 24 Jun 04 01:18:24 PM PDT 24 117921526 ps
T941 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2900891477 Jun 04 01:17:23 PM PDT 24 Jun 04 01:17:25 PM PDT 24 785820917 ps
T133 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3703667329 Jun 04 01:18:28 PM PDT 24 Jun 04 01:18:32 PM PDT 24 325912229 ps
T942 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1881099258 Jun 04 01:18:00 PM PDT 24 Jun 04 01:18:02 PM PDT 24 68092913 ps
T136 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1047516941 Jun 04 01:18:14 PM PDT 24 Jun 04 01:18:17 PM PDT 24 312815257 ps
T943 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1732492600 Jun 04 01:18:18 PM PDT 24 Jun 04 01:18:20 PM PDT 24 41388804 ps
T944 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3650288960 Jun 04 01:17:28 PM PDT 24 Jun 04 01:17:33 PM PDT 24 108604806 ps
T945 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1911804362 Jun 04 01:18:21 PM PDT 24 Jun 04 01:18:23 PM PDT 24 15893396 ps
T946 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1673229952 Jun 04 01:18:13 PM PDT 24 Jun 04 01:18:14 PM PDT 24 17335257 ps
T208 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3215767096 Jun 04 01:18:28 PM PDT 24 Jun 04 01:18:30 PM PDT 24 21910153 ps
T947 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3699233537 Jun 04 01:18:06 PM PDT 24 Jun 04 01:18:08 PM PDT 24 206997405 ps
T948 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1541142860 Jun 04 01:17:05 PM PDT 24 Jun 04 01:17:08 PM PDT 24 802856566 ps
T949 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2376041314 Jun 04 01:18:05 PM PDT 24 Jun 04 01:18:08 PM PDT 24 45358894 ps
T950 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1157285506 Jun 04 01:17:58 PM PDT 24 Jun 04 01:18:01 PM PDT 24 93793396 ps
T951 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1262196381 Jun 04 01:18:10 PM PDT 24 Jun 04 01:18:15 PM PDT 24 1753343433 ps
T952 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2629313201 Jun 04 01:18:21 PM PDT 24 Jun 04 01:18:23 PM PDT 24 48785456 ps
T953 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2515195960 Jun 04 01:17:51 PM PDT 24 Jun 04 01:17:53 PM PDT 24 81956834 ps
T954 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1588633069 Jun 04 01:17:44 PM PDT 24 Jun 04 01:17:45 PM PDT 24 51955455 ps
T955 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4138851236 Jun 04 01:17:49 PM PDT 24 Jun 04 01:17:54 PM PDT 24 114686894 ps
T956 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2121264400 Jun 04 01:18:19 PM PDT 24 Jun 04 01:18:23 PM PDT 24 480925965 ps
T957 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4250503344 Jun 04 01:18:05 PM PDT 24 Jun 04 01:18:08 PM PDT 24 71888747 ps
T958 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3236254150 Jun 04 01:18:07 PM PDT 24 Jun 04 01:18:09 PM PDT 24 78282292 ps
T959 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4256661779 Jun 04 01:17:58 PM PDT 24 Jun 04 01:18:18 PM PDT 24 1594778155 ps
T960 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3622096456 Jun 04 01:18:05 PM PDT 24 Jun 04 01:18:07 PM PDT 24 168834811 ps
T961 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.253309322 Jun 04 01:18:37 PM PDT 24 Jun 04 01:18:40 PM PDT 24 135584295 ps
T962 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2119085922 Jun 04 01:17:06 PM PDT 24 Jun 04 01:17:08 PM PDT 24 93582150 ps
T963 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3966738537 Jun 04 01:17:27 PM PDT 24 Jun 04 01:17:29 PM PDT 24 244702864 ps
T964 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3107541029 Jun 04 01:17:57 PM PDT 24 Jun 04 01:17:59 PM PDT 24 16374854 ps
T965 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3411174432 Jun 04 01:17:34 PM PDT 24 Jun 04 01:17:35 PM PDT 24 54219026 ps
T966 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3137252747 Jun 04 01:18:28 PM PDT 24 Jun 04 01:18:30 PM PDT 24 30720219 ps
T967 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2767637030 Jun 04 01:17:15 PM PDT 24 Jun 04 01:17:17 PM PDT 24 51650260 ps
T968 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2841471019 Jun 04 01:17:58 PM PDT 24 Jun 04 01:18:00 PM PDT 24 25169741 ps
T207 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1748626966 Jun 04 01:18:29 PM PDT 24 Jun 04 01:18:30 PM PDT 24 19581207 ps
T969 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3214410352 Jun 04 01:17:13 PM PDT 24 Jun 04 01:17:16 PM PDT 24 55378678 ps
T970 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4265785386 Jun 04 01:17:35 PM PDT 24 Jun 04 01:17:37 PM PDT 24 21365370 ps
T971 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.286385511 Jun 04 01:17:23 PM PDT 24 Jun 04 01:17:25 PM PDT 24 38228609 ps
T972 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.577777966 Jun 04 01:17:42 PM PDT 24 Jun 04 01:17:45 PM PDT 24 293255754 ps
T973 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3327869999 Jun 04 01:18:12 PM PDT 24 Jun 04 01:18:14 PM PDT 24 51451156 ps
T974 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3776657717 Jun 04 01:17:50 PM PDT 24 Jun 04 01:17:52 PM PDT 24 175331864 ps
T975 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3297772883 Jun 04 01:17:27 PM PDT 24 Jun 04 01:17:31 PM PDT 24 197858818 ps
T976 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3671705193 Jun 04 01:18:36 PM PDT 24 Jun 04 01:18:39 PM PDT 24 107801107 ps
T977 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3888744032 Jun 04 01:17:44 PM PDT 24 Jun 04 01:17:47 PM PDT 24 156631334 ps
T978 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2246146288 Jun 04 01:17:43 PM PDT 24 Jun 04 01:17:46 PM PDT 24 52814994 ps
T979 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.384574544 Jun 04 01:17:00 PM PDT 24 Jun 04 01:17:03 PM PDT 24 673986565 ps
T980 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1395643930 Jun 04 01:18:00 PM PDT 24 Jun 04 01:18:04 PM PDT 24 2120607267 ps
T981 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.664212412 Jun 04 01:17:59 PM PDT 24 Jun 04 01:18:02 PM PDT 24 152181796 ps
T142 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1226870137 Jun 04 01:18:20 PM PDT 24 Jun 04 01:18:24 PM PDT 24 108658194 ps
T982 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.958810426 Jun 04 01:17:52 PM PDT 24 Jun 04 01:18:17 PM PDT 24 8783072718 ps
T983 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1615828207 Jun 04 01:17:49 PM PDT 24 Jun 04 01:18:11 PM PDT 24 834345362 ps
T984 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.444807450 Jun 04 01:17:05 PM PDT 24 Jun 04 01:17:21 PM PDT 24 4270327309 ps
T985 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1363782580 Jun 04 01:17:36 PM PDT 24 Jun 04 01:17:39 PM PDT 24 123133536 ps
T986 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3212761945 Jun 04 01:17:21 PM PDT 24 Jun 04 01:17:25 PM PDT 24 345359991 ps
T987 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3572555391 Jun 04 01:17:12 PM PDT 24 Jun 04 01:17:15 PM PDT 24 25685556 ps
T988 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.41956969 Jun 04 01:17:14 PM PDT 24 Jun 04 01:17:16 PM PDT 24 289864029 ps
T989 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.16461204 Jun 04 01:18:21 PM PDT 24 Jun 04 01:18:23 PM PDT 24 45644756 ps
T990 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3246823168 Jun 04 01:17:06 PM PDT 24 Jun 04 01:17:10 PM PDT 24 1190226733 ps
T991 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2443703069 Jun 04 01:18:15 PM PDT 24 Jun 04 01:18:17 PM PDT 24 19592227 ps
T992 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.667349558 Jun 04 01:17:45 PM PDT 24 Jun 04 01:17:55 PM PDT 24 952834937 ps
T993 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1918989004 Jun 04 01:18:20 PM PDT 24 Jun 04 01:18:22 PM PDT 24 20507032 ps
T994 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.623875913 Jun 04 01:17:06 PM PDT 24 Jun 04 01:17:09 PM PDT 24 14662368 ps
T995 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3093996412 Jun 04 01:18:27 PM PDT 24 Jun 04 01:18:29 PM PDT 24 44241161 ps

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3985362519
Short name T5
Test name
Test status
Simulation time 36589208831 ps
CPU time 382.11 seconds
Started Jun 04 02:17:28 PM PDT 24
Finished Jun 04 02:23:51 PM PDT 24
Peak memory 250968 kb
Host smart-8621fed2-c2ad-4907-8828-ddaa6d5881a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985362519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3985362519
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.769402934
Short name T47
Test name
Test status
Simulation time 776157317 ps
CPU time 9.06 seconds
Started Jun 04 02:17:28 PM PDT 24
Finished Jun 04 02:17:38 PM PDT 24
Peak memory 218104 kb
Host smart-c16b7f8c-8d7b-4cfd-9949-43af93deaf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769402934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.769402934
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.2082472651
Short name T15
Test name
Test status
Simulation time 328706693 ps
CPU time 12.26 seconds
Started Jun 04 02:16:39 PM PDT 24
Finished Jun 04 02:16:52 PM PDT 24
Peak memory 226088 kb
Host smart-d9a6498e-afeb-4ad5-a46d-8226547f3f92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082472651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.2082472651
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.4249586437
Short name T90
Test name
Test status
Simulation time 72874070052 ps
CPU time 1418.78 seconds
Started Jun 04 02:15:46 PM PDT 24
Finished Jun 04 02:39:25 PM PDT 24
Peak memory 431356 kb
Host smart-8d8742ff-fb36-4b09-80a8-09e8b2b64936
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4249586437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_stress_all_with_rand_reset.4249586437
Directory /workspace/15.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.253135284
Short name T1
Test name
Test status
Simulation time 4753610098 ps
CPU time 54.49 seconds
Started Jun 04 02:15:53 PM PDT 24
Finished Jun 04 02:16:48 PM PDT 24
Peak memory 250960 kb
Host smart-e82b69e8-78d4-4f1d-8d5e-e7f9c0754e94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253135284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.253135284
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2780047963
Short name T130
Test name
Test status
Simulation time 104026155 ps
CPU time 3.89 seconds
Started Jun 04 01:17:56 PM PDT 24
Finished Jun 04 01:18:01 PM PDT 24
Peak memory 219300 kb
Host smart-1511574e-0cc9-4330-8fbd-0b60da80eddd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278004
7963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2780047963
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2233852186
Short name T53
Test name
Test status
Simulation time 125829242 ps
CPU time 26.63 seconds
Started Jun 04 02:13:18 PM PDT 24
Finished Jun 04 02:13:45 PM PDT 24
Peak memory 282460 kb
Host smart-14171da9-84ee-4934-82ef-b232910ba629
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233852186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2233852186
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.3054674780
Short name T7
Test name
Test status
Simulation time 444005647 ps
CPU time 9.67 seconds
Started Jun 04 02:12:27 PM PDT 24
Finished Jun 04 02:12:37 PM PDT 24
Peak memory 209532 kb
Host smart-51113408-70f5-4e16-bff3-c3cd5c8d7ecd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054674780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.3054674780
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3534828818
Short name T2
Test name
Test status
Simulation time 1009027279 ps
CPU time 12.8 seconds
Started Jun 04 02:17:13 PM PDT 24
Finished Jun 04 02:17:26 PM PDT 24
Peak memory 217928 kb
Host smart-31924c35-594f-4c97-9063-63f1eb9cf84c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534828818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3534828818
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1148862139
Short name T50
Test name
Test status
Simulation time 1541836698 ps
CPU time 13.53 seconds
Started Jun 04 02:16:42 PM PDT 24
Finished Jun 04 02:16:56 PM PDT 24
Peak memory 225496 kb
Host smart-64b2d792-21d9-4aa0-87ea-86528254847d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148862139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1148862139
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.452409065
Short name T118
Test name
Test status
Simulation time 124135394 ps
CPU time 2.95 seconds
Started Jun 04 01:17:11 PM PDT 24
Finished Jun 04 01:17:14 PM PDT 24
Peak memory 222604 kb
Host smart-1306b0d3-8adb-4058-98db-3307535400b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452409065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_e
rr.452409065
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.2601130348
Short name T168
Test name
Test status
Simulation time 6655383573 ps
CPU time 18.03 seconds
Started Jun 04 02:14:33 PM PDT 24
Finished Jun 04 02:14:52 PM PDT 24
Peak memory 218276 kb
Host smart-891ecddb-f9be-470e-b657-22aeaf5bd9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601130348 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.2601130348
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.414105664
Short name T13
Test name
Test status
Simulation time 19882927 ps
CPU time 0.87 seconds
Started Jun 04 02:17:12 PM PDT 24
Finished Jun 04 02:17:14 PM PDT 24
Peak memory 208504 kb
Host smart-7e58d468-187e-493d-9104-3faa2eec9976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414105664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.414105664
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.715566231
Short name T200
Test name
Test status
Simulation time 13729504 ps
CPU time 1.06 seconds
Started Jun 04 01:17:06 PM PDT 24
Finished Jun 04 01:17:08 PM PDT 24
Peak memory 209820 kb
Host smart-7940a9c9-59e6-407c-88b1-f9f959da015e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715566231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.715566231
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.3166328326
Short name T11
Test name
Test status
Simulation time 441573590 ps
CPU time 18.31 seconds
Started Jun 04 02:14:16 PM PDT 24
Finished Jun 04 02:14:36 PM PDT 24
Peak memory 218028 kb
Host smart-30857505-d41b-4ecd-a14a-fe4965bc3524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166328326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.3166328326
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.986122640
Short name T125
Test name
Test status
Simulation time 85967651 ps
CPU time 3.79 seconds
Started Jun 04 01:17:42 PM PDT 24
Finished Jun 04 01:17:47 PM PDT 24
Peak memory 218132 kb
Host smart-7355301b-2bba-4f08-8f79-aa1d652847b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986122640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e
rr.986122640
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.3352264616
Short name T43
Test name
Test status
Simulation time 194630049499 ps
CPU time 921.42 seconds
Started Jun 04 02:14:42 PM PDT 24
Finished Jun 04 02:30:04 PM PDT 24
Peak memory 308556 kb
Host smart-193bbefc-0794-4be9-b00b-130760ff2655
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3352264616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.3352264616
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1047516941
Short name T136
Test name
Test status
Simulation time 312815257 ps
CPU time 2.9 seconds
Started Jun 04 01:18:14 PM PDT 24
Finished Jun 04 01:18:17 PM PDT 24
Peak memory 222532 kb
Host smart-8eef56a3-e647-4a32-a34c-5567fcc5eee3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047516941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.1047516941
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1167585519
Short name T226
Test name
Test status
Simulation time 216541808 ps
CPU time 2.7 seconds
Started Jun 04 02:13:00 PM PDT 24
Finished Jun 04 02:13:03 PM PDT 24
Peak memory 218096 kb
Host smart-688c5248-5e30-40c7-9be0-44099d21e7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167585519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1167585519
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1734071284
Short name T135
Test name
Test status
Simulation time 2301743228 ps
CPU time 4.15 seconds
Started Jun 04 01:18:37 PM PDT 24
Finished Jun 04 01:18:42 PM PDT 24
Peak memory 218228 kb
Host smart-ed0a5f4c-17b9-49c4-a00c-bc2239e68cd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734071284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1734071284
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3165259576
Short name T120
Test name
Test status
Simulation time 113017514 ps
CPU time 1.89 seconds
Started Jun 04 01:18:28 PM PDT 24
Finished Jun 04 01:18:30 PM PDT 24
Peak memory 218204 kb
Host smart-1f3a0eaf-2780-4b3a-867e-56857f5a114a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165259576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3165259576
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3334274555
Short name T124
Test name
Test status
Simulation time 79044448 ps
CPU time 2.75 seconds
Started Jun 04 01:18:28 PM PDT 24
Finished Jun 04 01:18:32 PM PDT 24
Peak memory 222696 kb
Host smart-a94d067f-084e-4b31-b4c3-1f8b0c6dfc7e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334274555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3334274555
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2004932080
Short name T214
Test name
Test status
Simulation time 28141066 ps
CPU time 1.11 seconds
Started Jun 04 01:18:21 PM PDT 24
Finished Jun 04 01:18:23 PM PDT 24
Peak memory 217880 kb
Host smart-19934ac7-7a19-43ba-b680-3edd82afa488
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004932080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2004932080
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.3123322398
Short name T93
Test name
Test status
Simulation time 14791955245 ps
CPU time 540.44 seconds
Started Jun 04 02:16:31 PM PDT 24
Finished Jun 04 02:25:33 PM PDT 24
Peak memory 372544 kb
Host smart-46d41b7c-a610-49db-b959-24de70a44b8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3123322398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.3123322398
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3797873825
Short name T134
Test name
Test status
Simulation time 29000372 ps
CPU time 0.93 seconds
Started Jun 04 02:17:33 PM PDT 24
Finished Jun 04 02:17:35 PM PDT 24
Peak memory 212664 kb
Host smart-f2e32621-5daf-4fd0-b12b-59d8f1251e35
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797873825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3797873825
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.884649448
Short name T138
Test name
Test status
Simulation time 142252151 ps
CPU time 3.17 seconds
Started Jun 04 01:18:14 PM PDT 24
Finished Jun 04 01:18:18 PM PDT 24
Peak memory 222620 kb
Host smart-3bf96c95-223a-4007-9baa-fde2b6dba793
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884649448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_e
rr.884649448
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3690437647
Short name T221
Test name
Test status
Simulation time 33431047 ps
CPU time 0.95 seconds
Started Jun 04 02:12:20 PM PDT 24
Finished Jun 04 02:12:22 PM PDT 24
Peak memory 208624 kb
Host smart-b3941614-ba17-4e65-8c47-fff5284060ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690437647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3690437647
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.278606410
Short name T219
Test name
Test status
Simulation time 13774445 ps
CPU time 1.02 seconds
Started Jun 04 02:12:48 PM PDT 24
Finished Jun 04 02:12:50 PM PDT 24
Peak memory 208708 kb
Host smart-2f66d4eb-498e-4e12-af0f-0175fe7f1f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278606410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.278606410
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.2339910589
Short name T223
Test name
Test status
Simulation time 11550946 ps
CPU time 0.96 seconds
Started Jun 04 02:13:48 PM PDT 24
Finished Jun 04 02:13:50 PM PDT 24
Peak memory 208680 kb
Host smart-af01d862-0569-4498-b30c-81a5aefd7d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339910589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.2339910589
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.3069070483
Short name T54
Test name
Test status
Simulation time 1563115954 ps
CPU time 15.36 seconds
Started Jun 04 02:17:28 PM PDT 24
Finished Jun 04 02:17:44 PM PDT 24
Peak memory 226020 kb
Host smart-49f355fa-d23b-42a5-af01-f66c40bdee7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069070483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.3069070483
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3352394681
Short name T918
Test name
Test status
Simulation time 295498236 ps
CPU time 2.47 seconds
Started Jun 04 01:16:57 PM PDT 24
Finished Jun 04 01:17:00 PM PDT 24
Peak memory 209752 kb
Host smart-94f36e95-a5c8-4f1c-b204-5a1dfa03a206
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352394681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3352394681
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1226870137
Short name T142
Test name
Test status
Simulation time 108658194 ps
CPU time 2.98 seconds
Started Jun 04 01:18:20 PM PDT 24
Finished Jun 04 01:18:24 PM PDT 24
Peak memory 222704 kb
Host smart-3ea9fbe4-9008-48f5-82fd-d5751705eed5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226870137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1226870137
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1464254426
Short name T139
Test name
Test status
Simulation time 117921526 ps
CPU time 1.93 seconds
Started Jun 04 01:18:21 PM PDT 24
Finished Jun 04 01:18:24 PM PDT 24
Peak memory 222408 kb
Host smart-867fbe8b-e650-4ed7-b2db-797034a34c5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464254426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.1464254426
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2695955645
Short name T129
Test name
Test status
Simulation time 80049363 ps
CPU time 2.52 seconds
Started Jun 04 01:18:27 PM PDT 24
Finished Jun 04 01:18:31 PM PDT 24
Peak memory 218096 kb
Host smart-1158a0dd-ed71-4d17-920b-ade8fc41ed4e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695955645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2695955645
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.4274020376
Short name T132
Test name
Test status
Simulation time 104606802 ps
CPU time 2.86 seconds
Started Jun 04 01:17:54 PM PDT 24
Finished Jun 04 01:17:57 PM PDT 24
Peak memory 223012 kb
Host smart-4cc42391-5750-4479-8e55-59d68ed4d465
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274020376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.4274020376
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1842203184
Short name T39
Test name
Test status
Simulation time 1073725351 ps
CPU time 11.47 seconds
Started Jun 04 02:17:28 PM PDT 24
Finished Jun 04 02:17:40 PM PDT 24
Peak memory 218084 kb
Host smart-aa88ee61-40c0-4b2c-af35-2214a9de8eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842203184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1842203184
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.1340540612
Short name T10
Test name
Test status
Simulation time 490797802 ps
CPU time 10.41 seconds
Started Jun 04 02:13:01 PM PDT 24
Finished Jun 04 02:13:12 PM PDT 24
Peak memory 226036 kb
Host smart-c606befc-2d24-491b-9b50-acd1347b8ef6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340540612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.1340540612
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2952231215
Short name T883
Test name
Test status
Simulation time 18531424 ps
CPU time 1.18 seconds
Started Jun 04 01:17:07 PM PDT 24
Finished Jun 04 01:17:09 PM PDT 24
Peak memory 209752 kb
Host smart-9d71594d-d38d-4c68-865c-1277830fe1f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952231215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin
g.2952231215
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2017243053
Short name T903
Test name
Test status
Simulation time 88099758 ps
CPU time 1.45 seconds
Started Jun 04 01:17:05 PM PDT 24
Finished Jun 04 01:17:07 PM PDT 24
Peak memory 209812 kb
Host smart-cdb7efa8-fe97-4dc9-9377-61b1b3f49bde
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017243053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2017243053
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.2103728434
Short name T204
Test name
Test status
Simulation time 45776395 ps
CPU time 1.15 seconds
Started Jun 04 01:17:06 PM PDT 24
Finished Jun 04 01:17:09 PM PDT 24
Peak memory 218624 kb
Host smart-dc5ce02a-5640-4bf4-a2fd-53817ced1c9f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103728434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.2103728434
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.2584374543
Short name T888
Test name
Test status
Simulation time 73337791 ps
CPU time 1.56 seconds
Started Jun 04 01:17:06 PM PDT 24
Finished Jun 04 01:17:09 PM PDT 24
Peak memory 220392 kb
Host smart-dc766d8c-1ce0-4011-b1bb-d02b36a3c3fa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584374543 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.2584374543
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1202508033
Short name T882
Test name
Test status
Simulation time 37685064 ps
CPU time 1.61 seconds
Started Jun 04 01:17:06 PM PDT 24
Finished Jun 04 01:17:08 PM PDT 24
Peak memory 209236 kb
Host smart-d58e8aef-a92a-4c3f-8740-6c1f466ac292
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202508033 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1202508033
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.18040075
Short name T147
Test name
Test status
Simulation time 515446947 ps
CPU time 5.48 seconds
Started Jun 04 01:17:00 PM PDT 24
Finished Jun 04 01:17:06 PM PDT 24
Peak memory 217428 kb
Host smart-e97e62d0-622c-4ff1-af9c-9bfb962bfd57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18040075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 0.lc_ctrl_jtag_csr_aliasing.18040075
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.604366540
Short name T127
Test name
Test status
Simulation time 4915048505 ps
CPU time 26.71 seconds
Started Jun 04 01:16:56 PM PDT 24
Finished Jun 04 01:17:24 PM PDT 24
Peak memory 209840 kb
Host smart-396e8c3f-bb7b-4111-b548-7e35084a3f9b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604366540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.604366540
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.384574544
Short name T979
Test name
Test status
Simulation time 673986565 ps
CPU time 2.82 seconds
Started Jun 04 01:17:00 PM PDT 24
Finished Jun 04 01:17:03 PM PDT 24
Peak memory 211352 kb
Host smart-f269504f-5ca3-4ad5-88a6-fa959f364342
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384574544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.384574544
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3246823168
Short name T990
Test name
Test status
Simulation time 1190226733 ps
CPU time 2.53 seconds
Started Jun 04 01:17:06 PM PDT 24
Finished Jun 04 01:17:10 PM PDT 24
Peak memory 219352 kb
Host smart-e7f29005-c30e-457e-aea0-79f7f82fc2a9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324682
3168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3246823168
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3375648279
Short name T899
Test name
Test status
Simulation time 46105430 ps
CPU time 1.32 seconds
Started Jun 04 01:16:56 PM PDT 24
Finished Jun 04 01:16:58 PM PDT 24
Peak memory 209860 kb
Host smart-a4a3eb63-96a8-4b8f-bcd7-62e6462e9493
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375648279 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3375648279
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.2119085922
Short name T962
Test name
Test status
Simulation time 93582150 ps
CPU time 1.7 seconds
Started Jun 04 01:17:06 PM PDT 24
Finished Jun 04 01:17:08 PM PDT 24
Peak memory 211944 kb
Host smart-a972c17f-b64a-4c8a-872b-88d2d4e56fd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119085922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.2119085922
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1872750095
Short name T905
Test name
Test status
Simulation time 145298173 ps
CPU time 2.04 seconds
Started Jun 04 01:17:06 PM PDT 24
Finished Jun 04 01:17:09 PM PDT 24
Peak memory 218164 kb
Host smart-1a5e4e43-4c32-4f43-b1e9-0b80dd8aa847
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872750095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.1872750095
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1289275084
Short name T866
Test name
Test status
Simulation time 181279210 ps
CPU time 2.32 seconds
Started Jun 04 01:17:06 PM PDT 24
Finished Jun 04 01:17:10 PM PDT 24
Peak memory 222236 kb
Host smart-54ad52ff-86e0-4908-97fe-8c437e5b74a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289275084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1289275084
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.3214410352
Short name T969
Test name
Test status
Simulation time 55378678 ps
CPU time 1.45 seconds
Started Jun 04 01:17:13 PM PDT 24
Finished Jun 04 01:17:16 PM PDT 24
Peak memory 210008 kb
Host smart-9ca01eea-aabd-46c3-80ef-50ba8f79900d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214410352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.3214410352
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3572555391
Short name T987
Test name
Test status
Simulation time 25685556 ps
CPU time 1.62 seconds
Started Jun 04 01:17:12 PM PDT 24
Finished Jun 04 01:17:15 PM PDT 24
Peak memory 217276 kb
Host smart-7ed5b834-76b8-48d6-8327-e1a58fed61d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572555391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3572555391
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2767637030
Short name T967
Test name
Test status
Simulation time 51650260 ps
CPU time 0.9 seconds
Started Jun 04 01:17:15 PM PDT 24
Finished Jun 04 01:17:17 PM PDT 24
Peak memory 210148 kb
Host smart-428ae80f-1c70-430e-b537-c44623741e35
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767637030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2767637030
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2468897875
Short name T930
Test name
Test status
Simulation time 159075682 ps
CPU time 1.55 seconds
Started Jun 04 01:17:13 PM PDT 24
Finished Jun 04 01:17:15 PM PDT 24
Peak memory 218564 kb
Host smart-7c18051c-50d6-474f-83c4-9d9c73cda39f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468897875 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2468897875
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.475722872
Short name T203
Test name
Test status
Simulation time 123726150 ps
CPU time 1.01 seconds
Started Jun 04 01:17:15 PM PDT 24
Finished Jun 04 01:17:17 PM PDT 24
Peak memory 209776 kb
Host smart-cad0b56a-6008-4961-9c68-c31f70d9f167
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475722872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.475722872
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.1995610799
Short name T921
Test name
Test status
Simulation time 126244574 ps
CPU time 1.41 seconds
Started Jun 04 01:17:12 PM PDT 24
Finished Jun 04 01:17:15 PM PDT 24
Peak memory 209688 kb
Host smart-30510a54-e451-4b7f-b1e3-b4500e73bb13
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995610799 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.1995610799
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3716326228
Short name T895
Test name
Test status
Simulation time 2817554448 ps
CPU time 6.34 seconds
Started Jun 04 01:17:06 PM PDT 24
Finished Jun 04 01:17:14 PM PDT 24
Peak memory 209724 kb
Host smart-a5f0072b-49e0-4df4-a2b8-f88c3ee0b5ee
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716326228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3716326228
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.444807450
Short name T984
Test name
Test status
Simulation time 4270327309 ps
CPU time 14.76 seconds
Started Jun 04 01:17:05 PM PDT 24
Finished Jun 04 01:17:21 PM PDT 24
Peak memory 209816 kb
Host smart-f3171103-0a18-4c6d-8faa-aeca04003fe6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444807450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.444807450
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.896851596
Short name T920
Test name
Test status
Simulation time 1542076636 ps
CPU time 1.49 seconds
Started Jun 04 01:17:07 PM PDT 24
Finished Jun 04 01:17:09 PM PDT 24
Peak memory 211108 kb
Host smart-fdfdc428-974c-4656-80b4-f1a5a46bb5ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896851596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.896851596
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1541142860
Short name T948
Test name
Test status
Simulation time 802856566 ps
CPU time 2.44 seconds
Started Jun 04 01:17:05 PM PDT 24
Finished Jun 04 01:17:08 PM PDT 24
Peak memory 218128 kb
Host smart-aa234ce9-65e8-4bc9-83aa-fea40d1022dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154114
2860 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1541142860
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2733372266
Short name T865
Test name
Test status
Simulation time 292272218 ps
CPU time 1.47 seconds
Started Jun 04 01:17:05 PM PDT 24
Finished Jun 04 01:17:08 PM PDT 24
Peak memory 209724 kb
Host smart-d6907bb9-7849-4791-b09b-96909fb0d1fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733372266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2733372266
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.623875913
Short name T994
Test name
Test status
Simulation time 14662368 ps
CPU time 1.16 seconds
Started Jun 04 01:17:06 PM PDT 24
Finished Jun 04 01:17:09 PM PDT 24
Peak memory 209904 kb
Host smart-0dd64886-d349-49ff-adc7-717f7145f952
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623875913 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.623875913
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3865740930
Short name T897
Test name
Test status
Simulation time 37762615 ps
CPU time 1.73 seconds
Started Jun 04 01:17:12 PM PDT 24
Finished Jun 04 01:17:14 PM PDT 24
Peak memory 218296 kb
Host smart-c6663b0c-41c9-41a2-a96c-25d223c39561
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865740930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3865740930
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.2356143973
Short name T924
Test name
Test status
Simulation time 41885207 ps
CPU time 1.95 seconds
Started Jun 04 01:17:12 PM PDT 24
Finished Jun 04 01:17:15 PM PDT 24
Peak memory 219192 kb
Host smart-6abdedc9-0fca-485b-bcef-40fc1b382807
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356143973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.2356143973
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2443703069
Short name T991
Test name
Test status
Simulation time 19592227 ps
CPU time 1.05 seconds
Started Jun 04 01:18:15 PM PDT 24
Finished Jun 04 01:18:17 PM PDT 24
Peak memory 218156 kb
Host smart-f57d688d-6ab8-4bd3-a669-ee12ca9a3940
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443703069 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2443703069
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.1286120309
Short name T877
Test name
Test status
Simulation time 17527053 ps
CPU time 1.15 seconds
Started Jun 04 01:18:16 PM PDT 24
Finished Jun 04 01:18:17 PM PDT 24
Peak memory 217736 kb
Host smart-2aadd98b-c1b1-453b-9270-9222832cdac9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286120309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.1286120309
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.3327869999
Short name T973
Test name
Test status
Simulation time 51451156 ps
CPU time 1.08 seconds
Started Jun 04 01:18:12 PM PDT 24
Finished Jun 04 01:18:14 PM PDT 24
Peak memory 209912 kb
Host smart-c2e4a2a2-f93c-4de2-bf96-3eacd868b9c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327869999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.3327869999
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.434307136
Short name T879
Test name
Test status
Simulation time 495303543 ps
CPU time 3.38 seconds
Started Jun 04 01:18:19 PM PDT 24
Finished Jun 04 01:18:23 PM PDT 24
Peak memory 218188 kb
Host smart-dbcfd0b4-ffb0-4bf1-aa32-03e658204ba6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434307136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.434307136
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1764602759
Short name T123
Test name
Test status
Simulation time 61062480 ps
CPU time 2.31 seconds
Started Jun 04 01:18:18 PM PDT 24
Finished Jun 04 01:18:21 PM PDT 24
Peak memory 222708 kb
Host smart-cbced86f-1c7e-4308-9668-7ddd3ec3b56c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764602759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1764602759
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.1032655709
Short name T892
Test name
Test status
Simulation time 83361343 ps
CPU time 1.7 seconds
Started Jun 04 01:18:15 PM PDT 24
Finished Jun 04 01:18:17 PM PDT 24
Peak memory 219332 kb
Host smart-b7562c00-9c9c-41f0-a209-6afc4a0096b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032655709 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.1032655709
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1732492600
Short name T943
Test name
Test status
Simulation time 41388804 ps
CPU time 0.9 seconds
Started Jun 04 01:18:18 PM PDT 24
Finished Jun 04 01:18:20 PM PDT 24
Peak memory 209712 kb
Host smart-65489aa1-1533-403c-bfd5-9fc5025a969c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732492600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1732492600
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.3322896991
Short name T927
Test name
Test status
Simulation time 23250544 ps
CPU time 1.31 seconds
Started Jun 04 01:18:13 PM PDT 24
Finished Jun 04 01:18:16 PM PDT 24
Peak memory 209880 kb
Host smart-4a66407b-9fd7-4404-a3ea-934adc2c6a57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322896991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr
l_same_csr_outstanding.3322896991
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1339282917
Short name T115
Test name
Test status
Simulation time 526747912 ps
CPU time 3.09 seconds
Started Jun 04 01:18:13 PM PDT 24
Finished Jun 04 01:18:17 PM PDT 24
Peak memory 218188 kb
Host smart-da1cade1-0c9f-41db-9116-c9f75fb2cdcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339282917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.1339282917
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.3267331785
Short name T915
Test name
Test status
Simulation time 83119897 ps
CPU time 1.77 seconds
Started Jun 04 01:18:16 PM PDT 24
Finished Jun 04 01:18:19 PM PDT 24
Peak memory 218032 kb
Host smart-d6c77ca0-3230-4b4f-af14-58b9fe50ca59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267331785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.3267331785
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2015565354
Short name T931
Test name
Test status
Simulation time 23189354 ps
CPU time 1.43 seconds
Started Jun 04 01:18:21 PM PDT 24
Finished Jun 04 01:18:23 PM PDT 24
Peak memory 218556 kb
Host smart-abd67f64-932f-4de6-a1a5-7ce6c5c415c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015565354 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2015565354
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3322092765
Short name T885
Test name
Test status
Simulation time 128013658 ps
CPU time 1.01 seconds
Started Jun 04 01:18:21 PM PDT 24
Finished Jun 04 01:18:23 PM PDT 24
Peak memory 209444 kb
Host smart-3b30553e-720a-4f6c-847e-344e5e8d499e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322092765 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3322092765
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2838925938
Short name T933
Test name
Test status
Simulation time 20566035 ps
CPU time 1.54 seconds
Started Jun 04 01:18:22 PM PDT 24
Finished Jun 04 01:18:25 PM PDT 24
Peak memory 218168 kb
Host smart-89d3c115-2ac9-4207-93e4-5834e6b1261e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838925938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.2838925938
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.1815996077
Short name T126
Test name
Test status
Simulation time 150755133 ps
CPU time 2 seconds
Started Jun 04 01:18:19 PM PDT 24
Finished Jun 04 01:18:22 PM PDT 24
Peak memory 218220 kb
Host smart-fbd5ff8d-2130-4182-ad84-1fa94bd7d925
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815996077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.1815996077
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.4032101415
Short name T891
Test name
Test status
Simulation time 21593328 ps
CPU time 1.29 seconds
Started Jun 04 01:18:19 PM PDT 24
Finished Jun 04 01:18:21 PM PDT 24
Peak memory 218436 kb
Host smart-dce27bd4-73d4-47e2-bb6f-64784e3a1076
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032101415 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.4032101415
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2629313201
Short name T952
Test name
Test status
Simulation time 48785456 ps
CPU time 0.99 seconds
Started Jun 04 01:18:21 PM PDT 24
Finished Jun 04 01:18:23 PM PDT 24
Peak memory 209800 kb
Host smart-f34d635b-718a-46a0-8082-3684975a860e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629313201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2629313201
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.1056619299
Short name T914
Test name
Test status
Simulation time 37323117 ps
CPU time 1.87 seconds
Started Jun 04 01:18:20 PM PDT 24
Finished Jun 04 01:18:22 PM PDT 24
Peak memory 211860 kb
Host smart-a499c284-4dd7-42a9-b7ed-f1f643ca6ebe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056619299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.1056619299
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.3520008337
Short name T880
Test name
Test status
Simulation time 28697614 ps
CPU time 2.14 seconds
Started Jun 04 01:18:20 PM PDT 24
Finished Jun 04 01:18:23 PM PDT 24
Peak memory 219100 kb
Host smart-6c709fe1-751d-4775-91be-c61c6308495b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520008337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.3520008337
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.16461204
Short name T989
Test name
Test status
Simulation time 45644756 ps
CPU time 1.21 seconds
Started Jun 04 01:18:21 PM PDT 24
Finished Jun 04 01:18:23 PM PDT 24
Peak memory 222356 kb
Host smart-212175b1-3765-4f7f-a00c-ffe0667e237e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16461204 -assert nopostproc +UVM_TESTNAME=l
c_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.16461204
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.1911804362
Short name T945
Test name
Test status
Simulation time 15893396 ps
CPU time 1.12 seconds
Started Jun 04 01:18:21 PM PDT 24
Finished Jun 04 01:18:23 PM PDT 24
Peak memory 209620 kb
Host smart-5e5c4b03-9ccf-4b98-b2d8-5596fde31c64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911804362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.1911804362
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2121264400
Short name T956
Test name
Test status
Simulation time 480925965 ps
CPU time 3.33 seconds
Started Jun 04 01:18:19 PM PDT 24
Finished Jun 04 01:18:23 PM PDT 24
Peak memory 218088 kb
Host smart-dab28806-6954-4d41-a5b1-c4d3454ecb45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121264400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2121264400
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.3093996412
Short name T995
Test name
Test status
Simulation time 44241161 ps
CPU time 1.07 seconds
Started Jun 04 01:18:27 PM PDT 24
Finished Jun 04 01:18:29 PM PDT 24
Peak memory 218164 kb
Host smart-db36a43f-e97a-4d18-a97c-30c29862c5a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093996412 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.3093996412
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1523170446
Short name T867
Test name
Test status
Simulation time 13930129 ps
CPU time 1.03 seconds
Started Jun 04 01:18:27 PM PDT 24
Finished Jun 04 01:18:29 PM PDT 24
Peak memory 209712 kb
Host smart-de6a611a-f6be-472f-a3bb-c5d405078dd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523170446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.1523170446
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2196116336
Short name T211
Test name
Test status
Simulation time 20037729 ps
CPU time 1.38 seconds
Started Jun 04 01:18:28 PM PDT 24
Finished Jun 04 01:18:30 PM PDT 24
Peak memory 209616 kb
Host smart-07e0388e-03b1-4a33-a89d-e97373d20b33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196116336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2196116336
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1918989004
Short name T993
Test name
Test status
Simulation time 20507032 ps
CPU time 1.56 seconds
Started Jun 04 01:18:20 PM PDT 24
Finished Jun 04 01:18:22 PM PDT 24
Peak memory 218100 kb
Host smart-708c0f57-ceb3-426c-867b-e58289fd3e77
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918989004 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1918989004
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.251002343
Short name T137
Test name
Test status
Simulation time 46279762 ps
CPU time 2.3 seconds
Started Jun 04 01:18:27 PM PDT 24
Finished Jun 04 01:18:30 PM PDT 24
Peak memory 222044 kb
Host smart-6f1332b2-9871-4ac0-adb2-c179205c730c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251002343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg_
err.251002343
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1013509387
Short name T916
Test name
Test status
Simulation time 31262245 ps
CPU time 1.91 seconds
Started Jun 04 01:18:27 PM PDT 24
Finished Jun 04 01:18:30 PM PDT 24
Peak memory 220116 kb
Host smart-90f5fb56-3b8a-4ea5-898b-1c9d6b5c8a55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013509387 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1013509387
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1748626966
Short name T207
Test name
Test status
Simulation time 19581207 ps
CPU time 0.84 seconds
Started Jun 04 01:18:29 PM PDT 24
Finished Jun 04 01:18:30 PM PDT 24
Peak memory 209324 kb
Host smart-40c38817-5c2e-423b-8ecb-161a670b1a88
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748626966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1748626966
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3137252747
Short name T966
Test name
Test status
Simulation time 30720219 ps
CPU time 1.17 seconds
Started Jun 04 01:18:28 PM PDT 24
Finished Jun 04 01:18:30 PM PDT 24
Peak memory 209876 kb
Host smart-0f1700d6-4fb2-4293-a142-ed8fd4c22d3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137252747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3137252747
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.608861212
Short name T887
Test name
Test status
Simulation time 29396002 ps
CPU time 1.78 seconds
Started Jun 04 01:18:28 PM PDT 24
Finished Jun 04 01:18:31 PM PDT 24
Peak memory 219264 kb
Host smart-bd5e3c36-c719-4038-860d-9cb850670bcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608861212 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.608861212
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.4254175281
Short name T907
Test name
Test status
Simulation time 36774684 ps
CPU time 0.84 seconds
Started Jun 04 01:18:28 PM PDT 24
Finished Jun 04 01:18:29 PM PDT 24
Peak memory 209628 kb
Host smart-a6c2d75d-6635-4a25-b85a-dc32b09004a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254175281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.4254175281
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.1130354663
Short name T210
Test name
Test status
Simulation time 39697849 ps
CPU time 1.99 seconds
Started Jun 04 01:18:27 PM PDT 24
Finished Jun 04 01:18:30 PM PDT 24
Peak memory 211792 kb
Host smart-bc807a77-702d-42d4-af3c-427f403f3634
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130354663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.1130354663
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.2620709758
Short name T117
Test name
Test status
Simulation time 566790757 ps
CPU time 3.84 seconds
Started Jun 04 01:18:29 PM PDT 24
Finished Jun 04 01:18:34 PM PDT 24
Peak memory 218140 kb
Host smart-bd3317fa-e8f3-4066-a671-b82833897fe4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620709758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.2620709758
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3703667329
Short name T133
Test name
Test status
Simulation time 325912229 ps
CPU time 3.56 seconds
Started Jun 04 01:18:28 PM PDT 24
Finished Jun 04 01:18:32 PM PDT 24
Peak memory 223040 kb
Host smart-9d4667c2-f501-432b-8b76-74362952db5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703667329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3703667329
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.3671705193
Short name T976
Test name
Test status
Simulation time 107801107 ps
CPU time 1.6 seconds
Started Jun 04 01:18:36 PM PDT 24
Finished Jun 04 01:18:39 PM PDT 24
Peak memory 219652 kb
Host smart-21a31fbc-6896-45af-94dc-3d67d5bfdb54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671705193 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.3671705193
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.3215767096
Short name T208
Test name
Test status
Simulation time 21910153 ps
CPU time 1.02 seconds
Started Jun 04 01:18:28 PM PDT 24
Finished Jun 04 01:18:30 PM PDT 24
Peak memory 209772 kb
Host smart-97773be0-2227-4b96-ba45-998dd8e6ab79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215767096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.3215767096
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3074201241
Short name T911
Test name
Test status
Simulation time 165916327 ps
CPU time 1.13 seconds
Started Jun 04 01:18:37 PM PDT 24
Finished Jun 04 01:18:39 PM PDT 24
Peak memory 217860 kb
Host smart-e06acbcf-6b95-406c-92fe-d664ca8a4890
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074201241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3074201241
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.1839588375
Short name T894
Test name
Test status
Simulation time 45703497 ps
CPU time 3.53 seconds
Started Jun 04 01:18:27 PM PDT 24
Finished Jun 04 01:18:32 PM PDT 24
Peak memory 218356 kb
Host smart-1f3468fa-9705-4e8b-8db0-fd50b6b394ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839588375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.1839588375
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.804991209
Short name T873
Test name
Test status
Simulation time 80410272 ps
CPU time 1.1 seconds
Started Jun 04 01:18:38 PM PDT 24
Finished Jun 04 01:18:40 PM PDT 24
Peak memory 221040 kb
Host smart-0bbfce50-6805-4c41-89cd-f32ea08ace98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804991209 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.804991209
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.384360492
Short name T201
Test name
Test status
Simulation time 23998787 ps
CPU time 1.05 seconds
Started Jun 04 01:18:36 PM PDT 24
Finished Jun 04 01:18:37 PM PDT 24
Peak memory 209632 kb
Host smart-cc35ee12-7822-454e-8849-02352265a057
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384360492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.384360492
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.767308870
Short name T122
Test name
Test status
Simulation time 73561739 ps
CPU time 1.77 seconds
Started Jun 04 01:18:38 PM PDT 24
Finished Jun 04 01:18:41 PM PDT 24
Peak memory 211592 kb
Host smart-9711aa08-08c6-4a10-82ad-7910df961220
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767308870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_same_csr_outstanding.767308870
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.253309322
Short name T961
Test name
Test status
Simulation time 135584295 ps
CPU time 2.41 seconds
Started Jun 04 01:18:37 PM PDT 24
Finished Jun 04 01:18:40 PM PDT 24
Peak memory 218160 kb
Host smart-311c4e13-0671-497a-a332-50d1f57c9d43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253309322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.253309322
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.4175423535
Short name T198
Test name
Test status
Simulation time 127390140 ps
CPU time 1.28 seconds
Started Jun 04 01:17:21 PM PDT 24
Finished Jun 04 01:17:23 PM PDT 24
Peak memory 209804 kb
Host smart-727001be-1520-4080-b58c-a50b5995bcbb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175423535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.4175423535
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.286385511
Short name T971
Test name
Test status
Simulation time 38228609 ps
CPU time 1.19 seconds
Started Jun 04 01:17:23 PM PDT 24
Finished Jun 04 01:17:25 PM PDT 24
Peak memory 217368 kb
Host smart-8c73e874-8109-4c72-945a-12765fc12f90
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286385511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash
.286385511
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.4225235233
Short name T890
Test name
Test status
Simulation time 29717124 ps
CPU time 1.1 seconds
Started Jun 04 01:17:21 PM PDT 24
Finished Jun 04 01:17:23 PM PDT 24
Peak memory 210344 kb
Host smart-e2bfeca0-1c5a-4b64-b133-481552323339
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4225235233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.4225235233
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2021864508
Short name T925
Test name
Test status
Simulation time 59102625 ps
CPU time 1.19 seconds
Started Jun 04 01:17:28 PM PDT 24
Finished Jun 04 01:17:31 PM PDT 24
Peak memory 219932 kb
Host smart-a242041a-9497-445f-b3a9-c56f60c9aa2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021864508 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.2021864508
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.4280794327
Short name T910
Test name
Test status
Simulation time 58691604 ps
CPU time 0.91 seconds
Started Jun 04 01:17:20 PM PDT 24
Finished Jun 04 01:17:21 PM PDT 24
Peak memory 209388 kb
Host smart-49fdc6cc-a6a3-43f2-87d9-853139ee3429
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280794327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.4280794327
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2900891477
Short name T941
Test name
Test status
Simulation time 785820917 ps
CPU time 1.73 seconds
Started Jun 04 01:17:23 PM PDT 24
Finished Jun 04 01:17:25 PM PDT 24
Peak memory 209692 kb
Host smart-177ad6d6-d5b7-48cf-9006-f9ffdb6b117c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900891477 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2900891477
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1740079680
Short name T863
Test name
Test status
Simulation time 944450739 ps
CPU time 21.88 seconds
Started Jun 04 01:17:15 PM PDT 24
Finished Jun 04 01:17:39 PM PDT 24
Peak memory 209440 kb
Host smart-5d1ca347-c187-4f24-988f-e3e77f855c4a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740079680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1740079680
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4014574658
Short name T932
Test name
Test status
Simulation time 4030859430 ps
CPU time 13.42 seconds
Started Jun 04 01:17:15 PM PDT 24
Finished Jun 04 01:17:30 PM PDT 24
Peak memory 209780 kb
Host smart-75eb3f66-8dbd-4e73-a928-68ed34a8155c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014574658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.4014574658
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3536127333
Short name T929
Test name
Test status
Simulation time 223794052 ps
CPU time 1.34 seconds
Started Jun 04 01:17:13 PM PDT 24
Finished Jun 04 01:17:16 PM PDT 24
Peak memory 211072 kb
Host smart-4f8ee9da-e00c-4eb7-b4b5-4e483ef3f44c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536127333 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3536127333
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1064407124
Short name T889
Test name
Test status
Simulation time 209578723 ps
CPU time 5.85 seconds
Started Jun 04 01:17:22 PM PDT 24
Finished Jun 04 01:17:29 PM PDT 24
Peak memory 219844 kb
Host smart-11d739ae-772e-45a3-a0bb-59b1465d82d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106440
7124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1064407124
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.41956969
Short name T988
Test name
Test status
Simulation time 289864029 ps
CPU time 1.25 seconds
Started Jun 04 01:17:14 PM PDT 24
Finished Jun 04 01:17:16 PM PDT 24
Peak memory 217740 kb
Host smart-fa2a4805-4229-4030-8413-0617a1785537
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41956969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 2.lc_ctrl_jtag_csr_rw.41956969
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.1556977265
Short name T213
Test name
Test status
Simulation time 200106723 ps
CPU time 1.48 seconds
Started Jun 04 01:17:13 PM PDT 24
Finished Jun 04 01:17:15 PM PDT 24
Peak memory 209924 kb
Host smart-9e9c6916-63cb-4c6e-bcd0-7d2bbc8b28b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556977265 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.1556977265
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3075074742
Short name T216
Test name
Test status
Simulation time 28709916 ps
CPU time 1.02 seconds
Started Jun 04 01:17:21 PM PDT 24
Finished Jun 04 01:17:23 PM PDT 24
Peak memory 217620 kb
Host smart-9c06f3f7-70f8-4715-a832-3302e9875071
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075074742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.3075074742
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3212761945
Short name T986
Test name
Test status
Simulation time 345359991 ps
CPU time 2.67 seconds
Started Jun 04 01:17:21 PM PDT 24
Finished Jun 04 01:17:25 PM PDT 24
Peak memory 218284 kb
Host smart-54577aad-ed3c-4ece-9183-304f86d15300
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212761945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.3212761945
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2645602716
Short name T119
Test name
Test status
Simulation time 278172169 ps
CPU time 4.54 seconds
Started Jun 04 01:17:21 PM PDT 24
Finished Jun 04 01:17:27 PM PDT 24
Peak memory 218052 kb
Host smart-db2229ed-e6b6-428c-9fee-6f63605ffa36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645602716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.2645602716
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1977845709
Short name T206
Test name
Test status
Simulation time 151946029 ps
CPU time 1.14 seconds
Started Jun 04 01:17:38 PM PDT 24
Finished Jun 04 01:17:39 PM PDT 24
Peak memory 209976 kb
Host smart-8a8e2d2a-6539-406d-9e2c-968a5a562dc0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977845709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1977845709
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3174874047
Short name T936
Test name
Test status
Simulation time 67171404 ps
CPU time 1.83 seconds
Started Jun 04 01:17:35 PM PDT 24
Finished Jun 04 01:17:37 PM PDT 24
Peak memory 209796 kb
Host smart-c9fafca5-54c8-482a-bd01-bdc84204971d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174874047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3174874047
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3942375128
Short name T862
Test name
Test status
Simulation time 16819934 ps
CPU time 1.18 seconds
Started Jun 04 01:17:35 PM PDT 24
Finished Jun 04 01:17:36 PM PDT 24
Peak memory 210440 kb
Host smart-2cfa540a-1df1-4a7d-8c15-f1fa34c85a9c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942375128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3942375128
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1363782580
Short name T985
Test name
Test status
Simulation time 123133536 ps
CPU time 2.17 seconds
Started Jun 04 01:17:36 PM PDT 24
Finished Jun 04 01:17:39 PM PDT 24
Peak memory 224800 kb
Host smart-463be8f4-564c-42c5-a4da-6c3952c0a4ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363782580 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1363782580
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1692559148
Short name T202
Test name
Test status
Simulation time 16951402 ps
CPU time 0.96 seconds
Started Jun 04 01:17:35 PM PDT 24
Finished Jun 04 01:17:36 PM PDT 24
Peak memory 209792 kb
Host smart-ebea359c-ae38-4039-b867-74a31c34c4f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692559148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1692559148
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3966738537
Short name T963
Test name
Test status
Simulation time 244702864 ps
CPU time 1.7 seconds
Started Jun 04 01:17:27 PM PDT 24
Finished Jun 04 01:17:29 PM PDT 24
Peak memory 209176 kb
Host smart-7585084b-3bb6-419e-9769-fb5687149880
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966738537 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3966738537
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.709092483
Short name T922
Test name
Test status
Simulation time 3086117188 ps
CPU time 5.01 seconds
Started Jun 04 01:17:28 PM PDT 24
Finished Jun 04 01:17:35 PM PDT 24
Peak memory 209808 kb
Host smart-b6e0d97d-b2a6-47e3-bdf3-4d8d266adf34
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709092483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.709092483
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.160113400
Short name T900
Test name
Test status
Simulation time 351802051 ps
CPU time 5.08 seconds
Started Jun 04 01:17:28 PM PDT 24
Finished Jun 04 01:17:35 PM PDT 24
Peak memory 209464 kb
Host smart-2284826a-7eae-4487-9f16-263b8643e2f0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160113400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.160113400
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3650288960
Short name T944
Test name
Test status
Simulation time 108604806 ps
CPU time 3.17 seconds
Started Jun 04 01:17:28 PM PDT 24
Finished Jun 04 01:17:33 PM PDT 24
Peak memory 217932 kb
Host smart-8d3e520d-52b8-4568-ac6d-9508e843393d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650288960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3650288960
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1668054878
Short name T868
Test name
Test status
Simulation time 169816274 ps
CPU time 3.23 seconds
Started Jun 04 01:17:27 PM PDT 24
Finished Jun 04 01:17:33 PM PDT 24
Peak memory 222264 kb
Host smart-1f913ee7-289d-4b60-81ec-9967fd451dbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166805
4878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1668054878
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3561176780
Short name T878
Test name
Test status
Simulation time 414714211 ps
CPU time 1.39 seconds
Started Jun 04 01:17:28 PM PDT 24
Finished Jun 04 01:17:31 PM PDT 24
Peak memory 209744 kb
Host smart-ebaa084a-5ef2-4923-9f8b-57294f663df3
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561176780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.3561176780
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3297772883
Short name T975
Test name
Test status
Simulation time 197858818 ps
CPU time 1.34 seconds
Started Jun 04 01:17:27 PM PDT 24
Finished Jun 04 01:17:31 PM PDT 24
Peak memory 209948 kb
Host smart-a9112174-1702-4de6-a1c8-dc0b81e4b20e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297772883 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3297772883
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.3411174432
Short name T965
Test name
Test status
Simulation time 54219026 ps
CPU time 1.02 seconds
Started Jun 04 01:17:34 PM PDT 24
Finished Jun 04 01:17:35 PM PDT 24
Peak memory 209328 kb
Host smart-d7277c2c-a4ba-47d5-9353-63fb00cf8dfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411174432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.3411174432
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.4265785386
Short name T970
Test name
Test status
Simulation time 21365370 ps
CPU time 1.71 seconds
Started Jun 04 01:17:35 PM PDT 24
Finished Jun 04 01:17:37 PM PDT 24
Peak memory 218236 kb
Host smart-8d72437f-d514-42b3-b828-7712d5d370c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265785386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.4265785386
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.418253637
Short name T116
Test name
Test status
Simulation time 79763317 ps
CPU time 2.97 seconds
Started Jun 04 01:17:34 PM PDT 24
Finished Jun 04 01:17:38 PM PDT 24
Peak memory 218088 kb
Host smart-80730ddb-fabd-47d7-9701-f38098b28c1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418253637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_e
rr.418253637
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2010056596
Short name T199
Test name
Test status
Simulation time 38191739 ps
CPU time 1.39 seconds
Started Jun 04 01:17:51 PM PDT 24
Finished Jun 04 01:17:53 PM PDT 24
Peak memory 217976 kb
Host smart-939a0f89-ab3b-4ee4-aff1-a7b7237e68ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010056596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2010056596
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.2684745338
Short name T926
Test name
Test status
Simulation time 49872886 ps
CPU time 1.87 seconds
Started Jun 04 01:17:50 PM PDT 24
Finished Jun 04 01:17:52 PM PDT 24
Peak memory 209780 kb
Host smart-67b31048-191e-4610-9603-789221a8732d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684745338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.2684745338
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.3740503505
Short name T904
Test name
Test status
Simulation time 37365782 ps
CPU time 1.28 seconds
Started Jun 04 01:17:43 PM PDT 24
Finished Jun 04 01:17:45 PM PDT 24
Peak memory 212012 kb
Host smart-a36b2939-b566-4180-8e19-d2d9eaec88d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740503505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.3740503505
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2486080150
Short name T909
Test name
Test status
Simulation time 73241999 ps
CPU time 1.36 seconds
Started Jun 04 01:17:52 PM PDT 24
Finished Jun 04 01:17:54 PM PDT 24
Peak memory 218168 kb
Host smart-19b7c888-7e38-4219-b421-b5b75daa34f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486080150 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.2486080150
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1588633069
Short name T954
Test name
Test status
Simulation time 51955455 ps
CPU time 0.86 seconds
Started Jun 04 01:17:44 PM PDT 24
Finished Jun 04 01:17:45 PM PDT 24
Peak memory 208984 kb
Host smart-6c37a142-c58c-4521-8263-84bcc0888e1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588633069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1588633069
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3259490188
Short name T886
Test name
Test status
Simulation time 349428466 ps
CPU time 2.32 seconds
Started Jun 04 01:17:43 PM PDT 24
Finished Jun 04 01:17:46 PM PDT 24
Peak memory 208888 kb
Host smart-48c30df7-0fb1-40e6-b800-d904b8d4ed49
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259490188 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3259490188
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.667349558
Short name T992
Test name
Test status
Simulation time 952834937 ps
CPU time 8.91 seconds
Started Jun 04 01:17:45 PM PDT 24
Finished Jun 04 01:17:55 PM PDT 24
Peak memory 209392 kb
Host smart-8e8a8afd-b086-463e-b422-7f9d4cfe7353
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667349558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.667349558
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1982120031
Short name T901
Test name
Test status
Simulation time 835567283 ps
CPU time 8.6 seconds
Started Jun 04 01:17:45 PM PDT 24
Finished Jun 04 01:17:54 PM PDT 24
Peak memory 209492 kb
Host smart-c82d0766-d4e0-4a2e-91c2-3451e98924cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982120031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.1982120031
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.878545061
Short name T881
Test name
Test status
Simulation time 521854519 ps
CPU time 3.04 seconds
Started Jun 04 01:17:44 PM PDT 24
Finished Jun 04 01:17:47 PM PDT 24
Peak memory 217976 kb
Host smart-2e14af41-3aef-4d9c-915a-8cf3d2e78f05
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878545061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.878545061
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3888744032
Short name T977
Test name
Test status
Simulation time 156631334 ps
CPU time 2.16 seconds
Started Jun 04 01:17:44 PM PDT 24
Finished Jun 04 01:17:47 PM PDT 24
Peak memory 222076 kb
Host smart-d92ff8a8-8051-4bb8-bb77-fc88b864dbbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388874
4032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3888744032
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.577777966
Short name T972
Test name
Test status
Simulation time 293255754 ps
CPU time 2.5 seconds
Started Jun 04 01:17:42 PM PDT 24
Finished Jun 04 01:17:45 PM PDT 24
Peak memory 209672 kb
Host smart-30745813-e74b-4630-b377-28651399e94a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577777966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.577777966
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.2246146288
Short name T978
Test name
Test status
Simulation time 52814994 ps
CPU time 2.08 seconds
Started Jun 04 01:17:43 PM PDT 24
Finished Jun 04 01:17:46 PM PDT 24
Peak memory 209880 kb
Host smart-6d775ded-3edc-4d86-98ea-88f5185c4f1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246146288 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.2246146288
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2515195960
Short name T953
Test name
Test status
Simulation time 81956834 ps
CPU time 1.39 seconds
Started Jun 04 01:17:51 PM PDT 24
Finished Jun 04 01:17:53 PM PDT 24
Peak memory 211908 kb
Host smart-508d2e72-8f6d-41d4-8ca0-ee9b68764ecc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515195960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.2515195960
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2007072793
Short name T876
Test name
Test status
Simulation time 24508231 ps
CPU time 1.78 seconds
Started Jun 04 01:17:43 PM PDT 24
Finished Jun 04 01:17:46 PM PDT 24
Peak memory 219332 kb
Host smart-e8b0ec2d-069d-4088-9d46-7490e002f833
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007072793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.2007072793
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.147479526
Short name T869
Test name
Test status
Simulation time 15612344 ps
CPU time 1.07 seconds
Started Jun 04 01:17:51 PM PDT 24
Finished Jun 04 01:17:53 PM PDT 24
Peak memory 218164 kb
Host smart-50abdff9-a9d0-4a67-afd0-bd843092379f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147479526 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.147479526
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.909197580
Short name T874
Test name
Test status
Simulation time 14458517 ps
CPU time 0.85 seconds
Started Jun 04 01:17:51 PM PDT 24
Finished Jun 04 01:17:53 PM PDT 24
Peak memory 209712 kb
Host smart-5b6a6b26-c327-46ce-9663-42aa796f279b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909197580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.909197580
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.3020227202
Short name T902
Test name
Test status
Simulation time 556554567 ps
CPU time 1.83 seconds
Started Jun 04 01:17:51 PM PDT 24
Finished Jun 04 01:17:54 PM PDT 24
Peak memory 209704 kb
Host smart-8c6466f4-ba71-4bea-8d6f-75b1edbd0e4d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020227202 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.3020227202
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.44163528
Short name T898
Test name
Test status
Simulation time 413738092 ps
CPU time 8.71 seconds
Started Jun 04 01:17:51 PM PDT 24
Finished Jun 04 01:18:01 PM PDT 24
Peak memory 209420 kb
Host smart-ca420f09-7498-4df0-b4e1-dd24043237d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44163528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 5.lc_ctrl_jtag_csr_aliasing.44163528
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1615828207
Short name T983
Test name
Test status
Simulation time 834345362 ps
CPU time 21.23 seconds
Started Jun 04 01:17:49 PM PDT 24
Finished Jun 04 01:18:11 PM PDT 24
Peak memory 209320 kb
Host smart-5951efbd-d97f-4b0b-b71b-3b4493ca8d68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615828207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1615828207
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3776657717
Short name T974
Test name
Test status
Simulation time 175331864 ps
CPU time 1.39 seconds
Started Jun 04 01:17:50 PM PDT 24
Finished Jun 04 01:17:52 PM PDT 24
Peak memory 211172 kb
Host smart-be45efef-b2b3-41b8-ab20-c228b0ba20af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776657717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.3776657717
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4138851236
Short name T955
Test name
Test status
Simulation time 114686894 ps
CPU time 4.56 seconds
Started Jun 04 01:17:49 PM PDT 24
Finished Jun 04 01:17:54 PM PDT 24
Peak memory 218152 kb
Host smart-f6eedf45-0905-466f-b427-158aa5a69fa5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413885
1236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4138851236
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.2999423186
Short name T919
Test name
Test status
Simulation time 145463931 ps
CPU time 3.98 seconds
Started Jun 04 01:17:51 PM PDT 24
Finished Jun 04 01:17:55 PM PDT 24
Peak memory 209712 kb
Host smart-6bbd4ddd-51ec-415a-9f69-170946e977a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999423186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.2999423186
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1287349646
Short name T935
Test name
Test status
Simulation time 44827310 ps
CPU time 0.96 seconds
Started Jun 04 01:17:51 PM PDT 24
Finished Jun 04 01:17:53 PM PDT 24
Peak memory 209840 kb
Host smart-b07201e9-682d-423a-ae2e-365ecf0e629e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287349646 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.1287349646
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.745351501
Short name T908
Test name
Test status
Simulation time 128505181 ps
CPU time 1.77 seconds
Started Jun 04 01:17:51 PM PDT 24
Finished Jun 04 01:17:54 PM PDT 24
Peak memory 209880 kb
Host smart-17d10fa3-dfa5-4e6a-b094-ff389aaa0dc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745351501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
same_csr_outstanding.745351501
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2105443354
Short name T938
Test name
Test status
Simulation time 3061761144 ps
CPU time 4.02 seconds
Started Jun 04 01:17:53 PM PDT 24
Finished Jun 04 01:17:58 PM PDT 24
Peak memory 218260 kb
Host smart-62eb84a2-76fb-43fc-a37e-bcc8b58c4198
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105443354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2105443354
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.391893609
Short name T939
Test name
Test status
Simulation time 38389273 ps
CPU time 1 seconds
Started Jun 04 01:17:57 PM PDT 24
Finished Jun 04 01:17:59 PM PDT 24
Peak memory 219344 kb
Host smart-4a8ffc0a-1a7d-43e5-a25a-ea03409b178c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391893609 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.391893609
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3107541029
Short name T964
Test name
Test status
Simulation time 16374854 ps
CPU time 0.92 seconds
Started Jun 04 01:17:57 PM PDT 24
Finished Jun 04 01:17:59 PM PDT 24
Peak memory 209372 kb
Host smart-9ed56c65-5d9d-4c86-89e9-9c9492a22e47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107541029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3107541029
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1915245565
Short name T923
Test name
Test status
Simulation time 173873635 ps
CPU time 2.6 seconds
Started Jun 04 01:17:59 PM PDT 24
Finished Jun 04 01:18:02 PM PDT 24
Peak memory 209264 kb
Host smart-81cf8d91-70cd-4756-9346-3a5c3113b539
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915245565 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.1915245565
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.958810426
Short name T982
Test name
Test status
Simulation time 8783072718 ps
CPU time 23.51 seconds
Started Jun 04 01:17:52 PM PDT 24
Finished Jun 04 01:18:17 PM PDT 24
Peak memory 217864 kb
Host smart-d75005d6-3429-4f4d-8a10-c099c71a218f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958810426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.958810426
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.958540540
Short name T917
Test name
Test status
Simulation time 1372736655 ps
CPU time 15.68 seconds
Started Jun 04 01:17:53 PM PDT 24
Finished Jun 04 01:18:10 PM PDT 24
Peak memory 209420 kb
Host smart-1a975486-e9bc-411c-8a3c-81f7056671e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958540540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.958540540
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.2585677917
Short name T884
Test name
Test status
Simulation time 55343439 ps
CPU time 2.1 seconds
Started Jun 04 01:17:50 PM PDT 24
Finished Jun 04 01:17:52 PM PDT 24
Peak memory 217976 kb
Host smart-b7acbe60-e73d-43bb-b528-bc4bb66a001b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585677917 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.2585677917
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.3623545756
Short name T146
Test name
Test status
Simulation time 57466825 ps
CPU time 2.28 seconds
Started Jun 04 01:17:50 PM PDT 24
Finished Jun 04 01:17:53 PM PDT 24
Peak memory 217920 kb
Host smart-04b120de-5f31-40e5-ae09-5a2425d0b287
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623545756 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.3623545756
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1544350273
Short name T209
Test name
Test status
Simulation time 73455108 ps
CPU time 1.34 seconds
Started Jun 04 01:17:50 PM PDT 24
Finished Jun 04 01:17:52 PM PDT 24
Peak memory 209860 kb
Host smart-c7018968-8c72-4ae6-acdc-9ad4c326d339
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544350273 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1544350273
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3071185681
Short name T212
Test name
Test status
Simulation time 103289028 ps
CPU time 1.11 seconds
Started Jun 04 01:17:58 PM PDT 24
Finished Jun 04 01:18:00 PM PDT 24
Peak memory 209980 kb
Host smart-85ff06f3-a4e0-4d2b-9895-05247fb2b53f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071185681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3071185681
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.645787088
Short name T906
Test name
Test status
Simulation time 51403618 ps
CPU time 1.78 seconds
Started Jun 04 01:17:59 PM PDT 24
Finished Jun 04 01:18:01 PM PDT 24
Peak memory 218284 kb
Host smart-4f33d4ce-a784-4914-b940-550d6b987c0b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645787088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.645787088
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2432401398
Short name T141
Test name
Test status
Simulation time 137874940 ps
CPU time 2.13 seconds
Started Jun 04 01:18:00 PM PDT 24
Finished Jun 04 01:18:03 PM PDT 24
Peak memory 218052 kb
Host smart-ae352cd2-f257-424b-bc78-6df30b475ce1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432401398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.2432401398
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1157285506
Short name T950
Test name
Test status
Simulation time 93793396 ps
CPU time 1.56 seconds
Started Jun 04 01:17:58 PM PDT 24
Finished Jun 04 01:18:01 PM PDT 24
Peak memory 219196 kb
Host smart-5949f04a-c8d8-41cc-8d9b-3c9489d5b66a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157285506 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1157285506
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2986499398
Short name T934
Test name
Test status
Simulation time 29263091 ps
CPU time 0.91 seconds
Started Jun 04 01:17:59 PM PDT 24
Finished Jun 04 01:18:01 PM PDT 24
Peak memory 209484 kb
Host smart-843b4993-9a7f-4c56-ae81-c2d1bca96501
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986499398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2986499398
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.882544938
Short name T870
Test name
Test status
Simulation time 47252411 ps
CPU time 1.17 seconds
Started Jun 04 01:18:00 PM PDT 24
Finished Jun 04 01:18:02 PM PDT 24
Peak memory 209736 kb
Host smart-376931e7-98cf-4067-a5bb-b484b85ce6e7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882544938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 7.lc_ctrl_jtag_alert_test.882544938
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2783655491
Short name T893
Test name
Test status
Simulation time 3258272290 ps
CPU time 18.04 seconds
Started Jun 04 01:17:59 PM PDT 24
Finished Jun 04 01:18:18 PM PDT 24
Peak memory 209804 kb
Host smart-c6fc9e17-3a00-4e60-bec1-9914b72614bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783655491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2783655491
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2717171380
Short name T218
Test name
Test status
Simulation time 424051042 ps
CPU time 8.51 seconds
Started Jun 04 01:18:00 PM PDT 24
Finished Jun 04 01:18:10 PM PDT 24
Peak memory 209528 kb
Host smart-3a081bb8-0065-4874-a323-18b4489e01ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717171380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2717171380
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3929468114
Short name T128
Test name
Test status
Simulation time 87394704 ps
CPU time 1.21 seconds
Started Jun 04 01:17:57 PM PDT 24
Finished Jun 04 01:17:59 PM PDT 24
Peak memory 217988 kb
Host smart-2a99e48b-73b7-4ee8-be8d-f65da7121ee7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929468114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3929468114
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2054807088
Short name T940
Test name
Test status
Simulation time 74528275 ps
CPU time 1.7 seconds
Started Jun 04 01:17:58 PM PDT 24
Finished Jun 04 01:18:00 PM PDT 24
Peak memory 219292 kb
Host smart-3914369d-7263-4141-baea-b8d2b463ea8e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205480
7088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2054807088
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.2120822281
Short name T864
Test name
Test status
Simulation time 75667955 ps
CPU time 2.46 seconds
Started Jun 04 01:18:01 PM PDT 24
Finished Jun 04 01:18:04 PM PDT 24
Peak memory 209692 kb
Host smart-d84f469a-6481-4afd-bd5d-3d5ecbd5d50a
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120822281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.2120822281
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2841471019
Short name T968
Test name
Test status
Simulation time 25169741 ps
CPU time 1.39 seconds
Started Jun 04 01:17:58 PM PDT 24
Finished Jun 04 01:18:00 PM PDT 24
Peak memory 209828 kb
Host smart-954b5cf9-7fae-416a-b261-baad7a709d80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841471019 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2841471019
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1881099258
Short name T942
Test name
Test status
Simulation time 68092913 ps
CPU time 1.35 seconds
Started Jun 04 01:18:00 PM PDT 24
Finished Jun 04 01:18:02 PM PDT 24
Peak memory 209920 kb
Host smart-cf6beda4-6999-4c9b-8bce-df28b92cabc7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881099258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1881099258
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.664212412
Short name T981
Test name
Test status
Simulation time 152181796 ps
CPU time 2.6 seconds
Started Jun 04 01:17:59 PM PDT 24
Finished Jun 04 01:18:02 PM PDT 24
Peak memory 219160 kb
Host smart-a5cb2660-9878-40e0-94e3-9d08e438d4d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664212412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.664212412
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.2939274171
Short name T928
Test name
Test status
Simulation time 127297014 ps
CPU time 4.41 seconds
Started Jun 04 01:17:59 PM PDT 24
Finished Jun 04 01:18:05 PM PDT 24
Peak memory 218172 kb
Host smart-5f5f9693-21ab-4015-acd8-7d1557ea21f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939274171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.2939274171
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3369517660
Short name T170
Test name
Test status
Simulation time 62032389 ps
CPU time 1.25 seconds
Started Jun 04 01:18:06 PM PDT 24
Finished Jun 04 01:18:08 PM PDT 24
Peak memory 218356 kb
Host smart-ef24d750-3e5d-478c-8278-f7390e0e0b8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369517660 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3369517660
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.2636896688
Short name T121
Test name
Test status
Simulation time 17627397 ps
CPU time 1.15 seconds
Started Jun 04 01:18:06 PM PDT 24
Finished Jun 04 01:18:08 PM PDT 24
Peak memory 209812 kb
Host smart-5ec4a77e-a834-481d-999a-e64507660a17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636896688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.2636896688
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.194637621
Short name T872
Test name
Test status
Simulation time 593461611 ps
CPU time 1.19 seconds
Started Jun 04 01:18:07 PM PDT 24
Finished Jun 04 01:18:09 PM PDT 24
Peak memory 209888 kb
Host smart-6f890e92-8071-44ac-a990-c44e6bc5576d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194637621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.194637621
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4256661779
Short name T959
Test name
Test status
Simulation time 1594778155 ps
CPU time 19.85 seconds
Started Jun 04 01:17:58 PM PDT 24
Finished Jun 04 01:18:18 PM PDT 24
Peak memory 209688 kb
Host smart-4551d9b7-f63b-4b40-944f-658c73abfd68
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256661779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.4256661779
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2960113397
Short name T875
Test name
Test status
Simulation time 975397767 ps
CPU time 23.49 seconds
Started Jun 04 01:17:59 PM PDT 24
Finished Jun 04 01:18:23 PM PDT 24
Peak memory 209496 kb
Host smart-5c5d5a46-5c2d-44c6-af1b-beb8b96a2151
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960113397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2960113397
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1395643930
Short name T980
Test name
Test status
Simulation time 2120607267 ps
CPU time 2.66 seconds
Started Jun 04 01:18:00 PM PDT 24
Finished Jun 04 01:18:04 PM PDT 24
Peak memory 217976 kb
Host smart-4d71db72-c8db-4f24-bcbb-b952a1d4c20d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395643930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1395643930
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.737299391
Short name T145
Test name
Test status
Simulation time 64340920 ps
CPU time 1.84 seconds
Started Jun 04 01:18:05 PM PDT 24
Finished Jun 04 01:18:07 PM PDT 24
Peak memory 219268 kb
Host smart-0241f522-5a20-4a99-8a53-6d19655ea0db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737299
391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.737299391
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.4202431457
Short name T896
Test name
Test status
Simulation time 151029972 ps
CPU time 1.61 seconds
Started Jun 04 01:17:59 PM PDT 24
Finished Jun 04 01:18:02 PM PDT 24
Peak memory 209776 kb
Host smart-195d1522-05d2-4665-8a8a-5ffeec463924
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202431457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.4202431457
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1647317989
Short name T913
Test name
Test status
Simulation time 227021789 ps
CPU time 1.43 seconds
Started Jun 04 01:17:58 PM PDT 24
Finished Jun 04 01:18:00 PM PDT 24
Peak memory 218128 kb
Host smart-5e300ca3-2b45-4bc1-a009-5e4ec58d64f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647317989 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.1647317989
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.870840197
Short name T215
Test name
Test status
Simulation time 55271202 ps
CPU time 1.18 seconds
Started Jun 04 01:18:07 PM PDT 24
Finished Jun 04 01:18:08 PM PDT 24
Peak memory 209900 kb
Host smart-603fe7b9-1a13-4781-b008-2294f5d79935
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870840197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
same_csr_outstanding.870840197
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3150227161
Short name T912
Test name
Test status
Simulation time 31854267 ps
CPU time 2.26 seconds
Started Jun 04 01:18:09 PM PDT 24
Finished Jun 04 01:18:12 PM PDT 24
Peak memory 218648 kb
Host smart-93e97c77-31c5-4d8c-970b-c1db78f71876
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150227161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.3150227161
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.4075265886
Short name T140
Test name
Test status
Simulation time 101044278 ps
CPU time 2.48 seconds
Started Jun 04 01:18:06 PM PDT 24
Finished Jun 04 01:18:09 PM PDT 24
Peak memory 222308 kb
Host smart-211bcc56-f02e-4341-8e27-e2911f582993
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075265886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.4075265886
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.570347864
Short name T937
Test name
Test status
Simulation time 81190818 ps
CPU time 1.06 seconds
Started Jun 04 01:18:13 PM PDT 24
Finished Jun 04 01:18:15 PM PDT 24
Peak memory 218120 kb
Host smart-adf87faf-6a6d-408a-9737-b70f241a80b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570347864 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.570347864
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.3396748552
Short name T205
Test name
Test status
Simulation time 14636303 ps
CPU time 1.07 seconds
Started Jun 04 01:18:14 PM PDT 24
Finished Jun 04 01:18:16 PM PDT 24
Peak memory 209800 kb
Host smart-8028f73b-3c69-4033-87fb-f3c6daf26f12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396748552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.3396748552
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2376041314
Short name T949
Test name
Test status
Simulation time 45358894 ps
CPU time 1.79 seconds
Started Jun 04 01:18:05 PM PDT 24
Finished Jun 04 01:18:08 PM PDT 24
Peak memory 209260 kb
Host smart-40096363-1bfe-483b-8c5e-d6fc026b19a5
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376041314 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2376041314
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1262196381
Short name T951
Test name
Test status
Simulation time 1753343433 ps
CPU time 4.43 seconds
Started Jun 04 01:18:10 PM PDT 24
Finished Jun 04 01:18:15 PM PDT 24
Peak memory 209520 kb
Host smart-f78b0ec9-c428-43a0-9ea2-36138c3b9fd6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262196381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.1262196381
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1021920332
Short name T871
Test name
Test status
Simulation time 699445186 ps
CPU time 18.13 seconds
Started Jun 04 01:18:08 PM PDT 24
Finished Jun 04 01:18:27 PM PDT 24
Peak memory 217520 kb
Host smart-d2f0eb25-c82b-4fc9-91c5-f04d51c72daa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021920332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.1021920332
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3699233537
Short name T947
Test name
Test status
Simulation time 206997405 ps
CPU time 1.23 seconds
Started Jun 04 01:18:06 PM PDT 24
Finished Jun 04 01:18:08 PM PDT 24
Peak memory 211128 kb
Host smart-ebe78122-7920-4b21-8203-8b03afdc5a26
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699233537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3699233537
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2917422504
Short name T144
Test name
Test status
Simulation time 118305033 ps
CPU time 4.12 seconds
Started Jun 04 01:18:05 PM PDT 24
Finished Jun 04 01:18:10 PM PDT 24
Peak memory 218104 kb
Host smart-54782885-f879-49e3-872b-91b7a7c44460
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291742
2504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2917422504
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3622096456
Short name T960
Test name
Test status
Simulation time 168834811 ps
CPU time 1.35 seconds
Started Jun 04 01:18:05 PM PDT 24
Finished Jun 04 01:18:07 PM PDT 24
Peak memory 217780 kb
Host smart-632798f6-3a38-4305-b05a-e7c5ed575c53
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622096456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3622096456
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3236254150
Short name T958
Test name
Test status
Simulation time 78282292 ps
CPU time 1.76 seconds
Started Jun 04 01:18:07 PM PDT 24
Finished Jun 04 01:18:09 PM PDT 24
Peak memory 209908 kb
Host smart-138ac336-62b3-4c88-9007-a3b14e7e0cfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236254150 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3236254150
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.1673229952
Short name T946
Test name
Test status
Simulation time 17335257 ps
CPU time 1.19 seconds
Started Jun 04 01:18:13 PM PDT 24
Finished Jun 04 01:18:14 PM PDT 24
Peak memory 209928 kb
Host smart-c4faa5f9-960b-4020-b180-2cb55c29e94c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673229952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.1673229952
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.4250503344
Short name T957
Test name
Test status
Simulation time 71888747 ps
CPU time 2.68 seconds
Started Jun 04 01:18:05 PM PDT 24
Finished Jun 04 01:18:08 PM PDT 24
Peak memory 218660 kb
Host smart-c88e8ecb-4bdc-476d-8824-b3d0d6dd8a66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250503344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.4250503344
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.2801611420
Short name T338
Test name
Test status
Simulation time 50254177 ps
CPU time 1.03 seconds
Started Jun 04 02:12:47 PM PDT 24
Finished Jun 04 02:12:48 PM PDT 24
Peak memory 209568 kb
Host smart-fcfa5887-61df-43f7-9dc6-7ec133e200f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801611420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.2801611420
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.847219236
Short name T502
Test name
Test status
Simulation time 379117627 ps
CPU time 11.46 seconds
Started Jun 04 02:12:19 PM PDT 24
Finished Jun 04 02:12:31 PM PDT 24
Peak memory 218004 kb
Host smart-32d75d50-ced7-4e35-9116-c8e7b0410762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847219236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.847219236
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2021837316
Short name T191
Test name
Test status
Simulation time 1855098305 ps
CPU time 54.44 seconds
Started Jun 04 02:12:27 PM PDT 24
Finished Jun 04 02:13:22 PM PDT 24
Peak memory 218916 kb
Host smart-c48e43c8-6dcc-408a-8c86-ab836935d18f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021837316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2021837316
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.3846632844
Short name T486
Test name
Test status
Simulation time 1377081312 ps
CPU time 6.22 seconds
Started Jun 04 02:12:30 PM PDT 24
Finished Jun 04 02:12:36 PM PDT 24
Peak memory 217956 kb
Host smart-41c69323-0189-4a36-bcfd-f5204109db60
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846632844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.3846632844
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.2357065662
Short name T761
Test name
Test status
Simulation time 1208958369 ps
CPU time 18.92 seconds
Started Jun 04 02:12:27 PM PDT 24
Finished Jun 04 02:12:47 PM PDT 24
Peak memory 217620 kb
Host smart-e3b3706d-8f68-4ce8-a326-81d891ac0737
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357065662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.2357065662
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1926289385
Short name T21
Test name
Test status
Simulation time 301426287 ps
CPU time 1.71 seconds
Started Jun 04 02:12:21 PM PDT 24
Finished Jun 04 02:12:23 PM PDT 24
Peak memory 217644 kb
Host smart-b92b0217-4ea5-42a4-92e0-d7db6f75b8c9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926289385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1926289385
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3793055134
Short name T182
Test name
Test status
Simulation time 978089599 ps
CPU time 26.1 seconds
Started Jun 04 02:12:28 PM PDT 24
Finished Jun 04 02:12:55 PM PDT 24
Peak memory 267184 kb
Host smart-e9d3fe82-ba39-49ff-bbf8-07fadd757c93
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793055134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3793055134
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.3666518046
Short name T453
Test name
Test status
Simulation time 647707634 ps
CPU time 6.9 seconds
Started Jun 04 02:12:29 PM PDT 24
Finished Jun 04 02:12:36 PM PDT 24
Peak memory 222968 kb
Host smart-9954483f-4961-43cb-a9f7-a2bedf7c8a08
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666518046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.3666518046
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1405925167
Short name T812
Test name
Test status
Simulation time 61337442 ps
CPU time 1.72 seconds
Started Jun 04 02:12:20 PM PDT 24
Finished Jun 04 02:12:22 PM PDT 24
Peak memory 217980 kb
Host smart-8ad637b8-1d68-48ef-bcc8-24ccd5709c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405925167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1405925167
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.2368705028
Short name T342
Test name
Test status
Simulation time 271860682 ps
CPU time 18.28 seconds
Started Jun 04 02:12:20 PM PDT 24
Finished Jun 04 02:12:38 PM PDT 24
Peak memory 214436 kb
Host smart-04208f17-18e6-419d-80e6-948d23ba83c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368705028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.2368705028
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3483519401
Short name T105
Test name
Test status
Simulation time 167200985 ps
CPU time 22.55 seconds
Started Jun 04 02:12:48 PM PDT 24
Finished Jun 04 02:13:11 PM PDT 24
Peak memory 269292 kb
Host smart-02d6ed95-39dc-4d6e-9aea-ea48f2ce4d56
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483519401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3483519401
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.287499403
Short name T242
Test name
Test status
Simulation time 2287914681 ps
CPU time 17.36 seconds
Started Jun 04 02:12:30 PM PDT 24
Finished Jun 04 02:12:47 PM PDT 24
Peak memory 218968 kb
Host smart-773b1bcb-ef19-4cc9-84eb-89eb5edb1b4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287499403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.287499403
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1120221002
Short name T634
Test name
Test status
Simulation time 429432685 ps
CPU time 11.83 seconds
Started Jun 04 02:12:43 PM PDT 24
Finished Jun 04 02:12:55 PM PDT 24
Peak memory 226004 kb
Host smart-00310b73-6b1a-4387-9bc7-0cdb2ea41073
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120221002 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1120221002
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.247216771
Short name T272
Test name
Test status
Simulation time 297186035 ps
CPU time 12.03 seconds
Started Jun 04 02:12:42 PM PDT 24
Finished Jun 04 02:12:54 PM PDT 24
Peak memory 217900 kb
Host smart-46c38036-bd1e-4dd6-a313-89cfa220a21e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247216771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.247216771
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.2061463803
Short name T427
Test name
Test status
Simulation time 256990828 ps
CPU time 6.36 seconds
Started Jun 04 02:12:22 PM PDT 24
Finished Jun 04 02:12:29 PM PDT 24
Peak memory 224448 kb
Host smart-2633a4db-bd1f-4934-93c0-e95c0a77f945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061463803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.2061463803
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.779559033
Short name T640
Test name
Test status
Simulation time 32401176 ps
CPU time 1.11 seconds
Started Jun 04 02:12:14 PM PDT 24
Finished Jun 04 02:12:16 PM PDT 24
Peak memory 211724 kb
Host smart-05eab8e9-976d-4607-9458-c2e91edea0b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779559033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.779559033
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.2724435983
Short name T270
Test name
Test status
Simulation time 395934122 ps
CPU time 21.51 seconds
Started Jun 04 02:12:13 PM PDT 24
Finished Jun 04 02:12:35 PM PDT 24
Peak memory 250936 kb
Host smart-b2ef5174-8db5-468b-b3da-233a2811e3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724435983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.2724435983
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.2809037292
Short name T437
Test name
Test status
Simulation time 74035692 ps
CPU time 6.52 seconds
Started Jun 04 02:12:21 PM PDT 24
Finished Jun 04 02:12:28 PM PDT 24
Peak memory 250788 kb
Host smart-7479c9b4-ca03-4089-96fe-e2c9448fa835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809037292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.2809037292
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3217525909
Short name T65
Test name
Test status
Simulation time 3191583132 ps
CPU time 49.49 seconds
Started Jun 04 02:12:47 PM PDT 24
Finished Jun 04 02:13:37 PM PDT 24
Peak memory 226084 kb
Host smart-a893d868-38d0-4839-870f-2a226a8adee3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217525909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3217525909
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.916616793
Short name T152
Test name
Test status
Simulation time 31642556241 ps
CPU time 177.48 seconds
Started Jun 04 02:12:47 PM PDT 24
Finished Jun 04 02:15:45 PM PDT 24
Peak memory 269468 kb
Host smart-e8e43585-f9f4-4685-aeca-65820a1fb62a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=916616793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.916616793
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2237652677
Short name T85
Test name
Test status
Simulation time 14066618 ps
CPU time 0.99 seconds
Started Jun 04 02:12:14 PM PDT 24
Finished Jun 04 02:12:15 PM PDT 24
Peak memory 211436 kb
Host smart-9a4f2570-ba32-472e-bc4f-7176e6392c4b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237652677 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2237652677
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3437410046
Short name T602
Test name
Test status
Simulation time 136504688 ps
CPU time 0.98 seconds
Started Jun 04 02:13:03 PM PDT 24
Finished Jun 04 02:13:04 PM PDT 24
Peak memory 209576 kb
Host smart-369c9fd0-1c48-4fdb-b564-3b3dc99095be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437410046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3437410046
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.4230688516
Short name T310
Test name
Test status
Simulation time 940007501 ps
CPU time 12.57 seconds
Started Jun 04 02:13:11 PM PDT 24
Finished Jun 04 02:13:24 PM PDT 24
Peak memory 218116 kb
Host smart-b451cc59-a79e-4eb0-88ab-b4fdf4901750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230688516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.4230688516
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2003623343
Short name T590
Test name
Test status
Simulation time 462638437 ps
CPU time 7 seconds
Started Jun 04 02:12:57 PM PDT 24
Finished Jun 04 02:13:04 PM PDT 24
Peak memory 209524 kb
Host smart-654a80d8-90f0-4594-a5fc-27c997079a46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003623343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2003623343
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.2244770937
Short name T407
Test name
Test status
Simulation time 25010968296 ps
CPU time 84.64 seconds
Started Jun 04 02:12:53 PM PDT 24
Finished Jun 04 02:14:18 PM PDT 24
Peak memory 218432 kb
Host smart-4ca692fa-0073-40d9-a585-3e09af8f0dc3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244770937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.2244770937
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.344006610
Short name T414
Test name
Test status
Simulation time 902385118 ps
CPU time 13.64 seconds
Started Jun 04 02:12:55 PM PDT 24
Finished Jun 04 02:13:09 PM PDT 24
Peak memory 217452 kb
Host smart-0b8357ce-e981-4d75-b251-71d35f563c38
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344006610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.344006610
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3827617305
Short name T265
Test name
Test status
Simulation time 1614028457 ps
CPU time 11.98 seconds
Started Jun 04 02:12:56 PM PDT 24
Finished Jun 04 02:13:08 PM PDT 24
Peak memory 217888 kb
Host smart-3f3a8698-35ed-4dd4-9cf2-051ced82ec86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827617305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3827617305
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2601613639
Short name T772
Test name
Test status
Simulation time 2740394470 ps
CPU time 10.61 seconds
Started Jun 04 02:12:54 PM PDT 24
Finished Jun 04 02:13:05 PM PDT 24
Peak memory 217644 kb
Host smart-14ef06a3-1697-4693-b829-a30def712bd0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601613639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.2601613639
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.2808543943
Short name T668
Test name
Test status
Simulation time 1422718309 ps
CPU time 6.48 seconds
Started Jun 04 02:12:55 PM PDT 24
Finished Jun 04 02:13:02 PM PDT 24
Peak memory 217604 kb
Host smart-b8ecaf2c-351d-48b8-8add-24e4a921fbca
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808543943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
2808543943
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.1659150329
Short name T719
Test name
Test status
Simulation time 1185030581 ps
CPU time 49.48 seconds
Started Jun 04 02:12:54 PM PDT 24
Finished Jun 04 02:13:44 PM PDT 24
Peak memory 275420 kb
Host smart-b7fa42fe-7b32-4bf5-b096-e4b5b87ed82f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659150329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.1659150329
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.1664531833
Short name T693
Test name
Test status
Simulation time 940975247 ps
CPU time 12.32 seconds
Started Jun 04 02:12:55 PM PDT 24
Finished Jun 04 02:13:08 PM PDT 24
Peak memory 250056 kb
Host smart-6a000c42-04f4-4687-b9c7-24e356b8b70e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664531833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.1664531833
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.93195953
Short name T749
Test name
Test status
Simulation time 792665805 ps
CPU time 11.16 seconds
Started Jun 04 02:12:48 PM PDT 24
Finished Jun 04 02:13:00 PM PDT 24
Peak memory 217768 kb
Host smart-1132e114-94ef-4fc2-90a3-96b0b30d87dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93195953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.93195953
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.672774470
Short name T104
Test name
Test status
Simulation time 470435161 ps
CPU time 23.75 seconds
Started Jun 04 02:13:02 PM PDT 24
Finished Jun 04 02:13:26 PM PDT 24
Peak memory 281620 kb
Host smart-6763e266-5d93-4083-a89f-0eac619ecb81
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672774470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.672774470
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.1890348587
Short name T480
Test name
Test status
Simulation time 3230687890 ps
CPU time 18.33 seconds
Started Jun 04 02:12:56 PM PDT 24
Finished Jun 04 02:13:15 PM PDT 24
Peak memory 218992 kb
Host smart-b21562ee-e92c-4cca-a31f-b87f54e40ec8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890348587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.1890348587
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.337745357
Short name T565
Test name
Test status
Simulation time 333551965 ps
CPU time 10.79 seconds
Started Jun 04 02:13:02 PM PDT 24
Finished Jun 04 02:13:13 PM PDT 24
Peak memory 217924 kb
Host smart-664aab66-a969-4ccb-beba-6c598beb6648
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337745357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.337745357
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.182406919
Short name T49
Test name
Test status
Simulation time 478866585 ps
CPU time 8.89 seconds
Started Jun 04 02:12:47 PM PDT 24
Finished Jun 04 02:12:57 PM PDT 24
Peak memory 223992 kb
Host smart-9d62c449-bf0c-4cf2-98e3-479cd1d645ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182406919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.182406919
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2822986977
Short name T532
Test name
Test status
Simulation time 59447586 ps
CPU time 2.43 seconds
Started Jun 04 02:12:48 PM PDT 24
Finished Jun 04 02:12:51 PM PDT 24
Peak memory 214108 kb
Host smart-abd6ac72-9b23-4508-97ca-fa7ed01840c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822986977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2822986977
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.3924113123
Short name T792
Test name
Test status
Simulation time 345094781 ps
CPU time 25.67 seconds
Started Jun 04 02:12:47 PM PDT 24
Finished Jun 04 02:13:13 PM PDT 24
Peak memory 250904 kb
Host smart-fc749e2f-07f9-41a7-8dc8-55c8452bae3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924113123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.3924113123
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.2627249791
Short name T314
Test name
Test status
Simulation time 67175366 ps
CPU time 3.06 seconds
Started Jun 04 02:12:45 PM PDT 24
Finished Jun 04 02:12:48 PM PDT 24
Peak memory 222588 kb
Host smart-f4579da1-9f0b-4bc6-abb3-beb7a03b5de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627249791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.2627249791
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.2362644560
Short name T821
Test name
Test status
Simulation time 3162424902 ps
CPU time 40.3 seconds
Started Jun 04 02:13:00 PM PDT 24
Finished Jun 04 02:13:41 PM PDT 24
Peak memory 250944 kb
Host smart-52219641-f271-43e8-8851-6d4628c3ac62
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362644560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.2362644560
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.1946780546
Short name T151
Test name
Test status
Simulation time 30000517660 ps
CPU time 571.92 seconds
Started Jun 04 02:13:01 PM PDT 24
Finished Jun 04 02:22:33 PM PDT 24
Peak memory 300172 kb
Host smart-24449bda-7c7e-4105-a941-37f1c7e77bf5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1946780546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_stress_all_with_rand_reset.1946780546
Directory /workspace/1.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1176770231
Short name T36
Test name
Test status
Simulation time 29121288 ps
CPU time 0.84 seconds
Started Jun 04 02:12:47 PM PDT 24
Finished Jun 04 02:12:49 PM PDT 24
Peak memory 212496 kb
Host smart-f1e36035-bca2-4d14-bd2d-8f480587c750
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176770231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1176770231
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.669385252
Short name T776
Test name
Test status
Simulation time 23136377 ps
CPU time 1.27 seconds
Started Jun 04 02:15:07 PM PDT 24
Finished Jun 04 02:15:09 PM PDT 24
Peak memory 208768 kb
Host smart-36ace6fc-6315-46c3-b700-5b83d66425c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669385252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.669385252
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.77388926
Short name T360
Test name
Test status
Simulation time 565501122 ps
CPU time 15.98 seconds
Started Jun 04 02:15:00 PM PDT 24
Finished Jun 04 02:15:17 PM PDT 24
Peak memory 218104 kb
Host smart-c4865a9f-8bf0-4e39-b675-584a1867cc17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77388926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.77388926
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1936892846
Short name T515
Test name
Test status
Simulation time 573724331 ps
CPU time 14.1 seconds
Started Jun 04 02:15:00 PM PDT 24
Finished Jun 04 02:15:15 PM PDT 24
Peak memory 209484 kb
Host smart-0c875572-5240-4993-a7a6-b1c274ba60f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936892846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1936892846
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.2679724647
Short name T363
Test name
Test status
Simulation time 5179661660 ps
CPU time 66.44 seconds
Started Jun 04 02:14:57 PM PDT 24
Finished Jun 04 02:16:04 PM PDT 24
Peak memory 221252 kb
Host smart-e33cf358-3477-4f6d-a94e-899e2e4e3af7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679724647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.2679724647
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.527823429
Short name T268
Test name
Test status
Simulation time 1026828100 ps
CPU time 8.67 seconds
Started Jun 04 02:14:58 PM PDT 24
Finished Jun 04 02:15:07 PM PDT 24
Peak memory 217888 kb
Host smart-6c84c06b-936a-4699-b4f1-f22cf671c03f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527823429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_prog_failure.527823429
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.4098264911
Short name T359
Test name
Test status
Simulation time 7757055588 ps
CPU time 6.46 seconds
Started Jun 04 02:14:57 PM PDT 24
Finished Jun 04 02:15:03 PM PDT 24
Peak memory 217752 kb
Host smart-7afb09f2-6ffd-4bfc-9e43-9928432f65b6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098264911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.4098264911
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2639801473
Short name T579
Test name
Test status
Simulation time 4199791007 ps
CPU time 97.33 seconds
Started Jun 04 02:14:57 PM PDT 24
Finished Jun 04 02:16:35 PM PDT 24
Peak memory 283396 kb
Host smart-aa0264fe-325f-4d50-9a2e-55cbe4045e72
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2639801473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2639801473
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.875612737
Short name T699
Test name
Test status
Simulation time 4620141887 ps
CPU time 15.51 seconds
Started Jun 04 02:14:58 PM PDT 24
Finished Jun 04 02:15:14 PM PDT 24
Peak memory 226316 kb
Host smart-8c485fcb-589c-401c-851c-93dc81f51abb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875612737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_
jtag_state_post_trans.875612737
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2228179380
Short name T628
Test name
Test status
Simulation time 84793409 ps
CPU time 4.27 seconds
Started Jun 04 02:14:59 PM PDT 24
Finished Jun 04 02:15:03 PM PDT 24
Peak memory 218076 kb
Host smart-f24b9cb9-1ddc-400f-93b2-73f121e50c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228179380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2228179380
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.1616752419
Short name T99
Test name
Test status
Simulation time 2811692247 ps
CPU time 10.55 seconds
Started Jun 04 02:15:00 PM PDT 24
Finished Jun 04 02:15:11 PM PDT 24
Peak memory 219068 kb
Host smart-e6166e6e-6632-41c7-8f71-530100be3f6b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616752419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.1616752419
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3597441414
Short name T423
Test name
Test status
Simulation time 553040798 ps
CPU time 9.63 seconds
Started Jun 04 02:14:59 PM PDT 24
Finished Jun 04 02:15:09 PM PDT 24
Peak memory 226040 kb
Host smart-7e7da52f-b315-4e7d-9758-af56ce2a17b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597441414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3597441414
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.73856537
Short name T468
Test name
Test status
Simulation time 271593018 ps
CPU time 7.28 seconds
Started Jun 04 02:14:59 PM PDT 24
Finished Jun 04 02:15:07 PM PDT 24
Peak memory 217984 kb
Host smart-4ad6aab4-d0b4-4037-9d7f-a6b071843d42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73856537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.73856537
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.3350509973
Short name T178
Test name
Test status
Simulation time 285477268 ps
CPU time 11.58 seconds
Started Jun 04 02:14:58 PM PDT 24
Finished Jun 04 02:15:10 PM PDT 24
Peak memory 226080 kb
Host smart-226645a3-eb63-49b9-b1a8-1ab96e096854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350509973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.3350509973
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.649194819
Short name T367
Test name
Test status
Simulation time 24574315 ps
CPU time 1.26 seconds
Started Jun 04 02:14:58 PM PDT 24
Finished Jun 04 02:15:00 PM PDT 24
Peak memory 213340 kb
Host smart-be3f704a-31ae-4dad-b882-25c38d8e4bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649194819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.649194819
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.44482850
Short name T385
Test name
Test status
Simulation time 141635997 ps
CPU time 18.05 seconds
Started Jun 04 02:14:57 PM PDT 24
Finished Jun 04 02:15:15 PM PDT 24
Peak memory 250872 kb
Host smart-c256c229-47c7-4c43-921e-37396da0aa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44482850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.44482850
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1689470978
Short name T676
Test name
Test status
Simulation time 93490205 ps
CPU time 6.79 seconds
Started Jun 04 02:14:59 PM PDT 24
Finished Jun 04 02:15:06 PM PDT 24
Peak memory 246928 kb
Host smart-9be95815-38f8-4025-8c57-94e61864c3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689470978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1689470978
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.2879403345
Short name T648
Test name
Test status
Simulation time 14794297749 ps
CPU time 122.87 seconds
Started Jun 04 02:14:58 PM PDT 24
Finished Jun 04 02:17:02 PM PDT 24
Peak memory 250820 kb
Host smart-e634cf33-2196-454b-9ea7-3c37b995030e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879403345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.2879403345
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2142325510
Short name T286
Test name
Test status
Simulation time 12466221 ps
CPU time 0.83 seconds
Started Jun 04 02:14:59 PM PDT 24
Finished Jun 04 02:15:00 PM PDT 24
Peak memory 211476 kb
Host smart-a8a4f5c1-7207-4141-9df5-d4ebca3be61e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142325510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2142325510
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.1952883498
Short name T783
Test name
Test status
Simulation time 31098294 ps
CPU time 1.12 seconds
Started Jun 04 02:15:04 PM PDT 24
Finished Jun 04 02:15:06 PM PDT 24
Peak memory 209580 kb
Host smart-66643e92-9fc7-463f-83ea-25143f330080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952883498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.1952883498
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.3399954500
Short name T460
Test name
Test status
Simulation time 414338689 ps
CPU time 14.21 seconds
Started Jun 04 02:15:12 PM PDT 24
Finished Jun 04 02:15:26 PM PDT 24
Peak memory 217984 kb
Host smart-ffc89ab6-1fc7-41ba-9eb9-f4746731d6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399954500 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.3399954500
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1485792251
Short name T657
Test name
Test status
Simulation time 408422806 ps
CPU time 4.31 seconds
Started Jun 04 02:15:11 PM PDT 24
Finished Jun 04 02:15:16 PM PDT 24
Peak memory 209492 kb
Host smart-2021559c-d876-42e1-9058-04dbe5defccb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485792251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1485792251
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.990757019
Short name T748
Test name
Test status
Simulation time 9693493588 ps
CPU time 68.89 seconds
Started Jun 04 02:15:05 PM PDT 24
Finished Jun 04 02:16:15 PM PDT 24
Peak memory 218920 kb
Host smart-f6922f38-e103-4cd2-be7c-50c19fb5b5bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990757019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er
rors.990757019
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.2552258857
Short name T785
Test name
Test status
Simulation time 532825346 ps
CPU time 3.38 seconds
Started Jun 04 02:15:12 PM PDT 24
Finished Jun 04 02:15:16 PM PDT 24
Peak memory 217864 kb
Host smart-5f125077-5bd5-4fcb-bec9-ae0cf1ab74a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552258857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.2552258857
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.4264876163
Short name T493
Test name
Test status
Simulation time 1457235531 ps
CPU time 1.46 seconds
Started Jun 04 02:15:06 PM PDT 24
Finished Jun 04 02:15:09 PM PDT 24
Peak memory 217668 kb
Host smart-caba3198-d863-45a1-893b-f3a82a140f2f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264876163 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.4264876163
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2250056618
Short name T227
Test name
Test status
Simulation time 1424763358 ps
CPU time 37.29 seconds
Started Jun 04 02:15:06 PM PDT 24
Finished Jun 04 02:15:44 PM PDT 24
Peak memory 253420 kb
Host smart-724d752d-73c6-4414-8dd0-ca8d5c2c9a14
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250056618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2250056618
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.1750236970
Short name T254
Test name
Test status
Simulation time 2891812769 ps
CPU time 20.75 seconds
Started Jun 04 02:15:11 PM PDT 24
Finished Jun 04 02:15:32 PM PDT 24
Peak memory 250444 kb
Host smart-36a2ea06-4c4e-4d8c-ae58-4cdf69380790
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750236970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.1750236970
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1146632804
Short name T366
Test name
Test status
Simulation time 749919302 ps
CPU time 3.16 seconds
Started Jun 04 02:15:07 PM PDT 24
Finished Jun 04 02:15:11 PM PDT 24
Peak memory 217948 kb
Host smart-f3f748d3-90a8-4835-81bb-bc2b1a1e397d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146632804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1146632804
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.666100364
Short name T333
Test name
Test status
Simulation time 491244542 ps
CPU time 10.12 seconds
Started Jun 04 02:15:06 PM PDT 24
Finished Jun 04 02:15:17 PM PDT 24
Peak memory 218088 kb
Host smart-e55d5247-fca7-4ac3-ae01-f9fab15de8d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666100364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.666100364
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.661317239
Short name T754
Test name
Test status
Simulation time 5044605086 ps
CPU time 13.09 seconds
Started Jun 04 02:15:06 PM PDT 24
Finished Jun 04 02:15:20 PM PDT 24
Peak memory 226096 kb
Host smart-38431b58-374f-40fa-b7ed-0ee4956f9b9c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661317239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_di
gest.661317239
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.759917485
Short name T802
Test name
Test status
Simulation time 1253499088 ps
CPU time 13.22 seconds
Started Jun 04 02:15:06 PM PDT 24
Finished Jun 04 02:15:20 PM PDT 24
Peak memory 217936 kb
Host smart-36a9e072-ee86-48dc-ad36-80b29977d5e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759917485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.759917485
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2412502663
Short name T701
Test name
Test status
Simulation time 979036016 ps
CPU time 8.43 seconds
Started Jun 04 02:15:05 PM PDT 24
Finished Jun 04 02:15:14 PM PDT 24
Peak memory 218128 kb
Host smart-b64971b2-2f59-4c09-9ece-b22fcb129d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412502663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2412502663
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.1843904172
Short name T426
Test name
Test status
Simulation time 111795875 ps
CPU time 2.33 seconds
Started Jun 04 02:15:08 PM PDT 24
Finished Jun 04 02:15:11 PM PDT 24
Peak memory 214220 kb
Host smart-155f2c59-db8f-4fbe-9448-a3ebcdb672e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843904172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.1843904172
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.1593307041
Short name T622
Test name
Test status
Simulation time 179287673 ps
CPU time 21.59 seconds
Started Jun 04 02:15:07 PM PDT 24
Finished Jun 04 02:15:30 PM PDT 24
Peak memory 250876 kb
Host smart-ca58fd8b-6979-45e5-a8c7-13860fe0a3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593307041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.1593307041
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1891747476
Short name T755
Test name
Test status
Simulation time 46785636 ps
CPU time 6.12 seconds
Started Jun 04 02:15:06 PM PDT 24
Finished Jun 04 02:15:13 PM PDT 24
Peak memory 246756 kb
Host smart-48886490-3a71-499f-abe2-9a6b6d4bd144
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891747476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1891747476
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.2585877100
Short name T172
Test name
Test status
Simulation time 11696726362 ps
CPU time 83.51 seconds
Started Jun 04 02:15:10 PM PDT 24
Finished Jun 04 02:16:34 PM PDT 24
Peak memory 270492 kb
Host smart-6a4dfa4e-8d7f-443d-a2ba-2245c98a52e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585877100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.2585877100
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1022813979
Short name T382
Test name
Test status
Simulation time 12261728 ps
CPU time 0.88 seconds
Started Jun 04 02:15:04 PM PDT 24
Finished Jun 04 02:15:05 PM PDT 24
Peak memory 211456 kb
Host smart-ec955723-da90-4e26-839c-c6e9a2d31715
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022813979 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1022813979
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.759162718
Short name T294
Test name
Test status
Simulation time 67956372 ps
CPU time 0.83 seconds
Started Jun 04 02:15:13 PM PDT 24
Finished Jun 04 02:15:14 PM PDT 24
Peak memory 208692 kb
Host smart-e1328e76-7a1c-4127-b1b8-08cb9ad67193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759162718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.759162718
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2492637704
Short name T380
Test name
Test status
Simulation time 302555521 ps
CPU time 14.73 seconds
Started Jun 04 02:15:14 PM PDT 24
Finished Jun 04 02:15:30 PM PDT 24
Peak memory 218008 kb
Host smart-69761961-45f2-4390-b491-672361a9e275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492637704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2492637704
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.958074312
Short name T26
Test name
Test status
Simulation time 749465931 ps
CPU time 9.92 seconds
Started Jun 04 02:15:12 PM PDT 24
Finished Jun 04 02:15:23 PM PDT 24
Peak memory 209492 kb
Host smart-a535f2c9-d51c-4005-8cf3-6369753c57b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958074312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.958074312
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1394791477
Short name T455
Test name
Test status
Simulation time 6983494425 ps
CPU time 29.81 seconds
Started Jun 04 02:15:14 PM PDT 24
Finished Jun 04 02:15:44 PM PDT 24
Peak memory 218952 kb
Host smart-33b13dc9-d11d-4ded-88ef-8dafe1e9a94e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394791477 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1394791477
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.4095006439
Short name T857
Test name
Test status
Simulation time 277329774 ps
CPU time 5.37 seconds
Started Jun 04 02:15:15 PM PDT 24
Finished Jun 04 02:15:21 PM PDT 24
Peak memory 217924 kb
Host smart-1e5d16bc-8fda-49c2-bd1d-dc00be63df7f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095006439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.4095006439
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.3319157648
Short name T76
Test name
Test status
Simulation time 1822435087 ps
CPU time 2.22 seconds
Started Jun 04 02:15:13 PM PDT 24
Finished Jun 04 02:15:16 PM PDT 24
Peak memory 217636 kb
Host smart-cd31fd57-e699-4e0e-a2a9-cd5977a7e5f7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319157648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.3319157648
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2573480582
Short name T846
Test name
Test status
Simulation time 2846175935 ps
CPU time 37.69 seconds
Started Jun 04 02:15:13 PM PDT 24
Finished Jun 04 02:15:51 PM PDT 24
Peak memory 276040 kb
Host smart-d11bbca3-413a-45fb-b5ee-79b1ef5a8aac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573480582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2573480582
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.1490718855
Short name T276
Test name
Test status
Simulation time 310649222 ps
CPU time 6.67 seconds
Started Jun 04 02:15:13 PM PDT 24
Finished Jun 04 02:15:21 PM PDT 24
Peak memory 217956 kb
Host smart-5eed0c02-00fc-485d-be1c-ab897de84757
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490718855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.1490718855
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3922715912
Short name T378
Test name
Test status
Simulation time 68479111 ps
CPU time 1.82 seconds
Started Jun 04 02:15:04 PM PDT 24
Finished Jun 04 02:15:07 PM PDT 24
Peak memory 217960 kb
Host smart-7c9739c9-62ab-4a2a-a503-3b57447ca994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922715912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3922715912
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.2827306695
Short name T799
Test name
Test status
Simulation time 2031962744 ps
CPU time 15.26 seconds
Started Jun 04 02:15:14 PM PDT 24
Finished Jun 04 02:15:30 PM PDT 24
Peak memory 218192 kb
Host smart-8a8905ef-1027-4f59-95d9-3afed0471286
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827306695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.2827306695
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.2323679901
Short name T524
Test name
Test status
Simulation time 246403124 ps
CPU time 7.81 seconds
Started Jun 04 02:15:15 PM PDT 24
Finished Jun 04 02:15:24 PM PDT 24
Peak memory 226012 kb
Host smart-726d3d67-97fe-4220-bd94-cf255f148983
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323679901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.2323679901
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.197091030
Short name T789
Test name
Test status
Simulation time 1641187676 ps
CPU time 12.14 seconds
Started Jun 04 02:15:16 PM PDT 24
Finished Jun 04 02:15:29 PM PDT 24
Peak memory 217912 kb
Host smart-6c3e67f3-4eb8-43f5-bd74-9ef4deaf1b42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197091030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.197091030
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.965002408
Short name T48
Test name
Test status
Simulation time 871069235 ps
CPU time 11.78 seconds
Started Jun 04 02:15:13 PM PDT 24
Finished Jun 04 02:15:26 PM PDT 24
Peak memory 218032 kb
Host smart-ae1468bb-8afd-4104-b57c-9a1972c280a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965002408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.965002408
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.2401591998
Short name T724
Test name
Test status
Simulation time 34799805 ps
CPU time 2.84 seconds
Started Jun 04 02:15:05 PM PDT 24
Finished Jun 04 02:15:09 PM PDT 24
Peak memory 213836 kb
Host smart-64669125-9d30-47c7-aaf5-fe3da0ad9f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401591998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.2401591998
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.552453242
Short name T302
Test name
Test status
Simulation time 279942159 ps
CPU time 19.21 seconds
Started Jun 04 02:15:06 PM PDT 24
Finished Jun 04 02:15:26 PM PDT 24
Peak memory 250912 kb
Host smart-b5c982ff-f4e9-48e6-a108-c547d838a864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552453242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.552453242
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1811520793
Short name T855
Test name
Test status
Simulation time 424069914 ps
CPU time 3.53 seconds
Started Jun 04 02:15:05 PM PDT 24
Finished Jun 04 02:15:09 PM PDT 24
Peak memory 222372 kb
Host smart-6ff3b7ca-c0b8-4e3f-97f5-a8235d873f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811520793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1811520793
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.510754200
Short name T113
Test name
Test status
Simulation time 24103008716 ps
CPU time 200.18 seconds
Started Jun 04 02:15:13 PM PDT 24
Finished Jun 04 02:18:34 PM PDT 24
Peak memory 278272 kb
Host smart-540ba8a2-89d2-4304-ba5d-f2dfae4415d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510754200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.510754200
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.1348315239
Short name T841
Test name
Test status
Simulation time 20306460 ps
CPU time 0.85 seconds
Started Jun 04 02:15:05 PM PDT 24
Finished Jun 04 02:15:06 PM PDT 24
Peak memory 212516 kb
Host smart-817f203a-c119-4eec-99ec-d9887e5a66f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348315239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.1348315239
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2238183645
Short name T520
Test name
Test status
Simulation time 42193358 ps
CPU time 1.12 seconds
Started Jun 04 02:15:29 PM PDT 24
Finished Jun 04 02:15:31 PM PDT 24
Peak memory 208692 kb
Host smart-21d6cf5f-e6e1-4e8d-8104-040b2131d7e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238183645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2238183645
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3342018535
Short name T258
Test name
Test status
Simulation time 222643684 ps
CPU time 9.25 seconds
Started Jun 04 02:15:13 PM PDT 24
Finished Jun 04 02:15:23 PM PDT 24
Peak memory 217924 kb
Host smart-baf78225-a662-4c73-91fd-acdd88534f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342018535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3342018535
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.2517788213
Short name T27
Test name
Test status
Simulation time 809252893 ps
CPU time 18.92 seconds
Started Jun 04 02:15:27 PM PDT 24
Finished Jun 04 02:15:47 PM PDT 24
Peak memory 209464 kb
Host smart-c5b5d972-fa19-4852-b489-26a7173d0630
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517788213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.2517788213
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3455339825
Short name T581
Test name
Test status
Simulation time 2098940049 ps
CPU time 34.61 seconds
Started Jun 04 02:15:29 PM PDT 24
Finished Jun 04 02:16:05 PM PDT 24
Peak memory 217984 kb
Host smart-e664bdf0-b631-466e-a52b-1740ba4c2007
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455339825 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3455339825
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.2462210649
Short name T410
Test name
Test status
Simulation time 222163414 ps
CPU time 1.97 seconds
Started Jun 04 02:15:20 PM PDT 24
Finished Jun 04 02:15:22 PM PDT 24
Peak memory 217936 kb
Host smart-425ca0e6-be4c-42a8-9126-98c094993787
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462210649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.2462210649
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.4006954559
Short name T833
Test name
Test status
Simulation time 95283417 ps
CPU time 2.08 seconds
Started Jun 04 02:15:21 PM PDT 24
Finished Jun 04 02:15:24 PM PDT 24
Peak memory 217628 kb
Host smart-992bad44-e0b6-45b5-bbaa-772844d3090a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006954559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.4006954559
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3275172574
Short name T365
Test name
Test status
Simulation time 13960133092 ps
CPU time 79.46 seconds
Started Jun 04 02:15:21 PM PDT 24
Finished Jun 04 02:16:41 PM PDT 24
Peak memory 283652 kb
Host smart-2c2e6a94-0a61-4a5f-b1fd-925404049ce0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275172574 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3275172574
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.609957424
Short name T25
Test name
Test status
Simulation time 11621864162 ps
CPU time 15.24 seconds
Started Jun 04 02:15:20 PM PDT 24
Finished Jun 04 02:15:36 PM PDT 24
Peak memory 247996 kb
Host smart-c93c6e16-f5d8-44f8-ad77-79f3a32f092a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609957424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.609957424
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.581712739
Short name T808
Test name
Test status
Simulation time 232932562 ps
CPU time 2.85 seconds
Started Jun 04 02:15:15 PM PDT 24
Finished Jun 04 02:15:19 PM PDT 24
Peak memory 218004 kb
Host smart-db21d9de-87f4-4206-a95e-8f97e4e37ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581712739 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.581712739
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1213182987
Short name T306
Test name
Test status
Simulation time 763595793 ps
CPU time 10.11 seconds
Started Jun 04 02:15:29 PM PDT 24
Finished Jun 04 02:15:41 PM PDT 24
Peak memory 217944 kb
Host smart-fbd49d8f-c555-46a2-8507-6e52817496aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213182987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1213182987
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2963080429
Short name T858
Test name
Test status
Simulation time 328042010 ps
CPU time 9.58 seconds
Started Jun 04 02:15:22 PM PDT 24
Finished Jun 04 02:15:32 PM PDT 24
Peak memory 226072 kb
Host smart-8b3d16ec-d7c1-4b5e-9de9-4aefe0b34ffc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963080429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2963080429
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.1701542966
Short name T46
Test name
Test status
Simulation time 976603741 ps
CPU time 10.24 seconds
Started Jun 04 02:15:22 PM PDT 24
Finished Jun 04 02:15:33 PM PDT 24
Peak memory 217952 kb
Host smart-829d2700-180e-4577-b43d-20a5bb50a832
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701542966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
1701542966
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.3434484170
Short name T614
Test name
Test status
Simulation time 1037976330 ps
CPU time 7.41 seconds
Started Jun 04 02:15:22 PM PDT 24
Finished Jun 04 02:15:30 PM PDT 24
Peak memory 224644 kb
Host smart-c8bfde4f-3465-4b56-8af4-df195cb04511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434484170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.3434484170
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.1919544354
Short name T67
Test name
Test status
Simulation time 85727319 ps
CPU time 3.31 seconds
Started Jun 04 02:15:12 PM PDT 24
Finished Jun 04 02:15:15 PM PDT 24
Peak memory 217648 kb
Host smart-21f30aeb-cc04-49cc-8f28-dec47d369101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919544354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.1919544354
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.614884467
Short name T387
Test name
Test status
Simulation time 2338636549 ps
CPU time 26.1 seconds
Started Jun 04 02:15:13 PM PDT 24
Finished Jun 04 02:15:40 PM PDT 24
Peak memory 250952 kb
Host smart-be3460c0-a789-4b11-ba41-24db144388b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614884467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.614884467
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1116457840
Short name T446
Test name
Test status
Simulation time 65959886 ps
CPU time 6.08 seconds
Started Jun 04 02:15:13 PM PDT 24
Finished Jun 04 02:15:20 PM PDT 24
Peak memory 246924 kb
Host smart-90f2da4d-721d-49f5-aac4-7dc9cff5eb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116457840 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1116457840
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1662124128
Short name T177
Test name
Test status
Simulation time 19943934779 ps
CPU time 116.65 seconds
Started Jun 04 02:15:20 PM PDT 24
Finished Jun 04 02:17:18 PM PDT 24
Peak memory 270592 kb
Host smart-0416d1bb-a81d-4ec9-930e-ff9f73aa626d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662124128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1662124128
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3998918493
Short name T642
Test name
Test status
Simulation time 13454981 ps
CPU time 0.99 seconds
Started Jun 04 02:15:12 PM PDT 24
Finished Jun 04 02:15:14 PM PDT 24
Peak memory 211476 kb
Host smart-432b7da4-93b8-4c32-b85e-30a4f5fa0b55
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998918493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3998918493
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.4010491169
Short name T645
Test name
Test status
Simulation time 57644567 ps
CPU time 1.1 seconds
Started Jun 04 02:15:30 PM PDT 24
Finished Jun 04 02:15:32 PM PDT 24
Peak memory 209544 kb
Host smart-2b9e850d-2904-47f5-827f-a315f735d631
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010491169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.4010491169
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1704312772
Short name T154
Test name
Test status
Simulation time 1093819927 ps
CPU time 9.82 seconds
Started Jun 04 02:15:33 PM PDT 24
Finished Jun 04 02:15:43 PM PDT 24
Peak memory 218000 kb
Host smart-bfe432ee-db06-45cc-90a9-e9bfe45ed7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704312772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1704312772
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3550204936
Short name T827
Test name
Test status
Simulation time 127513572 ps
CPU time 2.23 seconds
Started Jun 04 02:15:32 PM PDT 24
Finished Jun 04 02:15:35 PM PDT 24
Peak memory 209488 kb
Host smart-be53a068-a101-4c60-adb2-58fff3ef9e5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550204936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3550204936
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2493372909
Short name T23
Test name
Test status
Simulation time 5621864410 ps
CPU time 44.42 seconds
Started Jun 04 02:15:29 PM PDT 24
Finished Jun 04 02:16:14 PM PDT 24
Peak memory 218888 kb
Host smart-158099ac-9989-4cb2-a71b-0e81a99d7f3d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493372909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2493372909
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.820125889
Short name T163
Test name
Test status
Simulation time 1858566437 ps
CPU time 13.1 seconds
Started Jun 04 02:15:28 PM PDT 24
Finished Jun 04 02:15:42 PM PDT 24
Peak memory 217920 kb
Host smart-8f8e5629-6b08-49d9-978c-e462bc330409
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820125889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.820125889
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3148283827
Short name T605
Test name
Test status
Simulation time 5377615058 ps
CPU time 8.8 seconds
Started Jun 04 02:15:29 PM PDT 24
Finished Jun 04 02:15:39 PM PDT 24
Peak memory 217680 kb
Host smart-59968801-6dbc-4469-94a4-dcab096306ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148283827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.3148283827
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.2170536606
Short name T405
Test name
Test status
Simulation time 2651916053 ps
CPU time 34.32 seconds
Started Jun 04 02:15:33 PM PDT 24
Finished Jun 04 02:16:08 PM PDT 24
Peak memory 251548 kb
Host smart-a457af2a-898f-466a-b30c-7250da83439f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170536606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.2170536606
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1606420223
Short name T800
Test name
Test status
Simulation time 3893765039 ps
CPU time 25.83 seconds
Started Jun 04 02:15:28 PM PDT 24
Finished Jun 04 02:15:55 PM PDT 24
Peak memory 250848 kb
Host smart-ff60be98-9cbf-42a6-8fae-4add0406c699
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606420223 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1606420223
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.208334597
Short name T596
Test name
Test status
Simulation time 162428491 ps
CPU time 1.79 seconds
Started Jun 04 02:15:29 PM PDT 24
Finished Jun 04 02:15:32 PM PDT 24
Peak memory 217944 kb
Host smart-8396ecc2-c742-4481-8380-c59d4f461f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208334597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.208334597
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.1614797000
Short name T164
Test name
Test status
Simulation time 395897144 ps
CPU time 16.54 seconds
Started Jun 04 02:15:28 PM PDT 24
Finished Jun 04 02:15:46 PM PDT 24
Peak memory 218896 kb
Host smart-3ea24a51-cd9a-41e6-bf9d-78d0d260039b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614797000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.1614797000
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.315236775
Short name T278
Test name
Test status
Simulation time 702394744 ps
CPU time 14.39 seconds
Started Jun 04 02:15:33 PM PDT 24
Finished Jun 04 02:15:48 PM PDT 24
Peak memory 225980 kb
Host smart-3fb8a3b2-ad08-4d7f-86ec-4a492c1ff039
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315236775 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.315236775
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.581731646
Short name T575
Test name
Test status
Simulation time 252063390 ps
CPU time 6.94 seconds
Started Jun 04 02:15:33 PM PDT 24
Finished Jun 04 02:15:41 PM PDT 24
Peak memory 217932 kb
Host smart-df023043-2cc2-45dd-ae2f-d46f67bf5377
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581731646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.581731646
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.3658811735
Short name T462
Test name
Test status
Simulation time 1447032854 ps
CPU time 14.41 seconds
Started Jun 04 02:15:30 PM PDT 24
Finished Jun 04 02:15:45 PM PDT 24
Peak memory 225564 kb
Host smart-0834ba8c-d13d-4357-9a3c-a9a98ab0b73e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658811735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.3658811735
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.2361044000
Short name T763
Test name
Test status
Simulation time 81493063 ps
CPU time 4.04 seconds
Started Jun 04 02:15:20 PM PDT 24
Finished Jun 04 02:15:24 PM PDT 24
Peak memory 217668 kb
Host smart-4964c4ff-d636-4a80-8171-ca2eb6ab6a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361044000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.2361044000
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.1554693891
Short name T439
Test name
Test status
Simulation time 247878165 ps
CPU time 23.58 seconds
Started Jun 04 02:15:21 PM PDT 24
Finished Jun 04 02:15:46 PM PDT 24
Peak memory 250876 kb
Host smart-d1e534ee-02b6-4112-b0a3-bdddff4e7e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554693891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.1554693891
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3000684543
Short name T458
Test name
Test status
Simulation time 103184086 ps
CPU time 6.52 seconds
Started Jun 04 02:15:30 PM PDT 24
Finished Jun 04 02:15:37 PM PDT 24
Peak memory 250488 kb
Host smart-88f0dab0-04f5-4655-a7ac-dca007e547e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000684543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3000684543
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.657780730
Short name T377
Test name
Test status
Simulation time 1923488597 ps
CPU time 22.37 seconds
Started Jun 04 02:15:28 PM PDT 24
Finished Jun 04 02:15:52 PM PDT 24
Peak memory 250848 kb
Host smart-74fe0f5d-3f4c-40df-aa4e-1a4e36c1aea0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657780730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.657780730
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.2295190065
Short name T618
Test name
Test status
Simulation time 12249248 ps
CPU time 0.88 seconds
Started Jun 04 02:15:22 PM PDT 24
Finished Jun 04 02:15:23 PM PDT 24
Peak memory 211504 kb
Host smart-54d0b671-0d3f-4d96-ba6e-de18ba9411cb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295190065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.2295190065
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.1447911330
Short name T341
Test name
Test status
Simulation time 32535867 ps
CPU time 0.87 seconds
Started Jun 04 02:15:44 PM PDT 24
Finished Jun 04 02:15:46 PM PDT 24
Peak memory 208672 kb
Host smart-d4e94e3b-e9da-4815-9885-d38e1c74fb0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447911330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.1447911330
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1002112557
Short name T519
Test name
Test status
Simulation time 1258746874 ps
CPU time 12.47 seconds
Started Jun 04 02:15:41 PM PDT 24
Finished Jun 04 02:15:54 PM PDT 24
Peak memory 218004 kb
Host smart-abd5d3b4-303f-4545-bce2-06c2eb6d2b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002112557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1002112557
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.1448563016
Short name T30
Test name
Test status
Simulation time 1773878056 ps
CPU time 8.64 seconds
Started Jun 04 02:15:36 PM PDT 24
Finished Jun 04 02:15:45 PM PDT 24
Peak memory 217200 kb
Host smart-397649f5-000a-4116-a176-15e69e0dba84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448563016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.1448563016
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.4193915197
Short name T697
Test name
Test status
Simulation time 12723526797 ps
CPU time 82.54 seconds
Started Jun 04 02:15:35 PM PDT 24
Finished Jun 04 02:16:59 PM PDT 24
Peak memory 218956 kb
Host smart-ef996473-fe45-49b8-8b81-fb166f66b629
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193915197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.4193915197
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.2331523918
Short name T744
Test name
Test status
Simulation time 2527530316 ps
CPU time 16.76 seconds
Started Jun 04 02:15:36 PM PDT 24
Finished Jun 04 02:15:54 PM PDT 24
Peak memory 217932 kb
Host smart-84168f0d-02f5-4545-8737-aec7016eb4a8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331523918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.2331523918
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.4185853798
Short name T356
Test name
Test status
Simulation time 334971215 ps
CPU time 5.41 seconds
Started Jun 04 02:15:36 PM PDT 24
Finished Jun 04 02:15:43 PM PDT 24
Peak memory 217576 kb
Host smart-f9eccb72-477e-4537-bbd7-66ca48716497
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185853798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.4185853798
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.3117108573
Short name T860
Test name
Test status
Simulation time 2442445228 ps
CPU time 79.01 seconds
Started Jun 04 02:15:36 PM PDT 24
Finished Jun 04 02:16:56 PM PDT 24
Peak memory 276004 kb
Host smart-67440464-7d79-464d-82e8-6c7557bd44e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117108573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.3117108573
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.5645866
Short name T241
Test name
Test status
Simulation time 3071762654 ps
CPU time 33.48 seconds
Started Jun 04 02:15:35 PM PDT 24
Finished Jun 04 02:16:10 PM PDT 24
Peak memory 250520 kb
Host smart-a0dba56b-47c5-42ac-acbf-627ebcfba4fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5645866 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_st
ate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_post_trans.5645866
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1875380710
Short name T110
Test name
Test status
Simulation time 98577251 ps
CPU time 3.91 seconds
Started Jun 04 02:15:29 PM PDT 24
Finished Jun 04 02:15:33 PM PDT 24
Peak memory 217976 kb
Host smart-caba756a-e509-4658-aedf-b7410cba225d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875380710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1875380710
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.637310059
Short name T41
Test name
Test status
Simulation time 1688863401 ps
CPU time 12.73 seconds
Started Jun 04 02:15:36 PM PDT 24
Finished Jun 04 02:15:50 PM PDT 24
Peak memory 219136 kb
Host smart-8bb6d3ac-2202-45f0-8987-e9ea029c1569
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637310059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.637310059
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.401825070
Short name T185
Test name
Test status
Simulation time 210960264 ps
CPU time 9.7 seconds
Started Jun 04 02:15:46 PM PDT 24
Finished Jun 04 02:15:56 PM PDT 24
Peak memory 225548 kb
Host smart-b50bb8c6-f788-49c9-ad53-847410b9d5a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401825070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_di
gest.401825070
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.346284847
Short name T739
Test name
Test status
Simulation time 1008916134 ps
CPU time 7.53 seconds
Started Jun 04 02:15:36 PM PDT 24
Finished Jun 04 02:15:44 PM PDT 24
Peak memory 217916 kb
Host smart-6847ba51-de17-4c1f-826a-7e3b6097e4f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346284847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.346284847
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.738932682
Short name T315
Test name
Test status
Simulation time 739058410 ps
CPU time 6.17 seconds
Started Jun 04 02:15:36 PM PDT 24
Finished Jun 04 02:15:43 PM PDT 24
Peak memory 224528 kb
Host smart-4dff8647-e3ba-4566-aeb7-ecffa8fa660a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738932682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.738932682
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.4022029245
Short name T570
Test name
Test status
Simulation time 760823856 ps
CPU time 3.18 seconds
Started Jun 04 02:15:30 PM PDT 24
Finished Jun 04 02:15:34 PM PDT 24
Peak memory 217812 kb
Host smart-0e03367b-7d97-4e0e-bd5c-f68a123b839d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022029245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.4022029245
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.12519745
Short name T607
Test name
Test status
Simulation time 1400409204 ps
CPU time 28.68 seconds
Started Jun 04 02:15:28 PM PDT 24
Finished Jun 04 02:15:58 PM PDT 24
Peak memory 250908 kb
Host smart-f6395149-bc9b-49f1-ad4b-7cf8c9fa296a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12519745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.12519745
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.541075436
Short name T706
Test name
Test status
Simulation time 142935152 ps
CPU time 7.54 seconds
Started Jun 04 02:15:29 PM PDT 24
Finished Jun 04 02:15:37 PM PDT 24
Peak memory 250844 kb
Host smart-17a96602-5838-41a6-a5d9-3120556b7b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541075436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.541075436
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3284314910
Short name T822
Test name
Test status
Simulation time 2210436747 ps
CPU time 34.1 seconds
Started Jun 04 02:15:44 PM PDT 24
Finished Jun 04 02:16:19 PM PDT 24
Peak memory 251040 kb
Host smart-c1129e34-3bcd-4dd3-a21d-be022641a5f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284314910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3284314910
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.1084092788
Short name T273
Test name
Test status
Simulation time 15079242 ps
CPU time 0.9 seconds
Started Jun 04 02:15:33 PM PDT 24
Finished Jun 04 02:15:34 PM PDT 24
Peak memory 211484 kb
Host smart-55d59920-d91b-473a-8509-2c3e88ae28e6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084092788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.1084092788
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.4085809974
Short name T673
Test name
Test status
Simulation time 38319125 ps
CPU time 0.96 seconds
Started Jun 04 02:15:52 PM PDT 24
Finished Jun 04 02:15:54 PM PDT 24
Peak memory 209536 kb
Host smart-02720095-0dcf-4d04-b3c7-d8c23f6e1649
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085809974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.4085809974
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.290022172
Short name T853
Test name
Test status
Simulation time 942037705 ps
CPU time 11.22 seconds
Started Jun 04 02:15:45 PM PDT 24
Finished Jun 04 02:15:57 PM PDT 24
Peak memory 217968 kb
Host smart-49157d35-080c-4b25-b5e7-aca7162b4b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290022172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.290022172
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.1328737987
Short name T31
Test name
Test status
Simulation time 269449753 ps
CPU time 2.68 seconds
Started Jun 04 02:15:48 PM PDT 24
Finished Jun 04 02:15:51 PM PDT 24
Peak memory 209508 kb
Host smart-8d507d7e-2b3d-42a3-8b21-0fc6162202e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328737987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.1328737987
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.2954066704
Short name T351
Test name
Test status
Simulation time 2393596633 ps
CPU time 35.94 seconds
Started Jun 04 02:15:45 PM PDT 24
Finished Jun 04 02:16:21 PM PDT 24
Peak memory 217924 kb
Host smart-631140ac-dc2b-47c8-be21-6a0c2846b508
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954066704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.2954066704
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.699064359
Short name T352
Test name
Test status
Simulation time 377315506 ps
CPU time 4.43 seconds
Started Jun 04 02:15:44 PM PDT 24
Finished Jun 04 02:15:49 PM PDT 24
Peak memory 217920 kb
Host smart-14a18411-ff45-4cdd-9a7b-589e3bbd95d9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699064359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag
_prog_failure.699064359
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.3911603375
Short name T542
Test name
Test status
Simulation time 1412913709 ps
CPU time 9.64 seconds
Started Jun 04 02:15:45 PM PDT 24
Finished Jun 04 02:15:56 PM PDT 24
Peak memory 217596 kb
Host smart-223b4f61-14ff-4ee7-8ee5-67113afb17fd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911603375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.3911603375
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.3227547059
Short name T4
Test name
Test status
Simulation time 4931773760 ps
CPU time 45.19 seconds
Started Jun 04 02:15:46 PM PDT 24
Finished Jun 04 02:16:32 PM PDT 24
Peak memory 253124 kb
Host smart-595597c3-a4c4-4d68-8147-efca92aa1c04
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227547059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.3227547059
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.2337009314
Short name T825
Test name
Test status
Simulation time 1143870884 ps
CPU time 10.16 seconds
Started Jun 04 02:15:47 PM PDT 24
Finished Jun 04 02:15:58 PM PDT 24
Peak memory 250436 kb
Host smart-55a645ca-cbd2-43fb-9de2-09313534dec5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337009314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.2337009314
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.1600673982
Short name T231
Test name
Test status
Simulation time 61130059 ps
CPU time 1.94 seconds
Started Jun 04 02:15:46 PM PDT 24
Finished Jun 04 02:15:48 PM PDT 24
Peak memory 217992 kb
Host smart-71b9c41c-ed23-44c2-9cf6-e3943141a903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600673982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.1600673982
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.3473122850
Short name T629
Test name
Test status
Simulation time 308120435 ps
CPU time 12.98 seconds
Started Jun 04 02:15:43 PM PDT 24
Finished Jun 04 02:15:56 PM PDT 24
Peak memory 218136 kb
Host smart-0bada7ad-a9e0-4394-a22b-5b8fb3ba5248
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473122850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.3473122850
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.2063713915
Short name T583
Test name
Test status
Simulation time 3801597617 ps
CPU time 18.44 seconds
Started Jun 04 02:15:57 PM PDT 24
Finished Jun 04 02:16:16 PM PDT 24
Peak memory 226092 kb
Host smart-f6bb5d2d-75d3-4672-a362-ef339ff33b8f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063713915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.2063713915
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1555753771
Short name T100
Test name
Test status
Simulation time 1120238657 ps
CPU time 7.69 seconds
Started Jun 04 02:15:54 PM PDT 24
Finished Jun 04 02:16:03 PM PDT 24
Peak memory 217952 kb
Host smart-228fe547-5eee-498a-85b2-85374f065922
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555753771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
1555753771
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3548470544
Short name T16
Test name
Test status
Simulation time 388926724 ps
CPU time 7.66 seconds
Started Jun 04 02:15:45 PM PDT 24
Finished Jun 04 02:15:53 PM PDT 24
Peak memory 224760 kb
Host smart-578a75bf-83a3-46a6-83f2-ec924373f418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548470544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3548470544
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.3820674411
Short name T747
Test name
Test status
Simulation time 94430158 ps
CPU time 3.29 seconds
Started Jun 04 02:15:44 PM PDT 24
Finished Jun 04 02:15:48 PM PDT 24
Peak memory 217760 kb
Host smart-3b49dd3b-f734-42a5-80f9-b95ed9914cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820674411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.3820674411
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1501650674
Short name T383
Test name
Test status
Simulation time 312630155 ps
CPU time 22.1 seconds
Started Jun 04 02:15:45 PM PDT 24
Finished Jun 04 02:16:08 PM PDT 24
Peak memory 250900 kb
Host smart-8454690b-bafa-4531-ab19-68914e43b7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501650674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1501650674
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3149904106
Short name T362
Test name
Test status
Simulation time 196670198 ps
CPU time 9.3 seconds
Started Jun 04 02:15:44 PM PDT 24
Finished Jun 04 02:15:54 PM PDT 24
Peak memory 250904 kb
Host smart-e4376c7a-6e0e-45de-b3ea-833fe7261a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149904106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3149904106
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.2345314995
Short name T388
Test name
Test status
Simulation time 38881173900 ps
CPU time 312.84 seconds
Started Jun 04 02:15:54 PM PDT 24
Finished Jun 04 02:21:08 PM PDT 24
Peak memory 272204 kb
Host smart-227296f0-ad29-4ea0-a896-af19ed705e80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345314995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.2345314995
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.470614190
Short name T587
Test name
Test status
Simulation time 32511301 ps
CPU time 0.85 seconds
Started Jun 04 02:15:45 PM PDT 24
Finished Jun 04 02:15:46 PM PDT 24
Peak memory 211588 kb
Host smart-5be45a52-108b-475d-a77d-63b9974fd1bc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470614190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ct
rl_volatile_unlock_smoke.470614190
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.3681790675
Short name T752
Test name
Test status
Simulation time 15177825 ps
CPU time 1.03 seconds
Started Jun 04 02:15:53 PM PDT 24
Finished Jun 04 02:15:55 PM PDT 24
Peak memory 208736 kb
Host smart-a63559c8-410e-41f8-aabd-55f7b74836d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681790675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.3681790675
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.1080232672
Short name T192
Test name
Test status
Simulation time 523048305 ps
CPU time 10.73 seconds
Started Jun 04 02:15:54 PM PDT 24
Finished Jun 04 02:16:05 PM PDT 24
Peak memory 217988 kb
Host smart-c464f10f-2dd9-4b30-9d66-3fec19c51fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080232672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.1080232672
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3562496809
Short name T484
Test name
Test status
Simulation time 1060342799 ps
CPU time 3.68 seconds
Started Jun 04 02:15:55 PM PDT 24
Finished Jun 04 02:15:59 PM PDT 24
Peak memory 209512 kb
Host smart-2b41e863-29ea-4a5e-b4bc-7b36aa3462e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562496809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3562496809
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.3713506355
Short name T422
Test name
Test status
Simulation time 1253883263 ps
CPU time 35.29 seconds
Started Jun 04 02:15:53 PM PDT 24
Finished Jun 04 02:16:28 PM PDT 24
Peak memory 217864 kb
Host smart-352a8a09-66ef-4af0-a0fa-2afa8ef8966d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713506355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.3713506355
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1877213078
Short name T348
Test name
Test status
Simulation time 716801714 ps
CPU time 11.96 seconds
Started Jun 04 02:15:53 PM PDT 24
Finished Jun 04 02:16:06 PM PDT 24
Peak memory 217904 kb
Host smart-00cb5241-a577-4755-9f47-d8d7feca359e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877213078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.1877213078
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.115976818
Short name T653
Test name
Test status
Simulation time 1006669666 ps
CPU time 7.45 seconds
Started Jun 04 02:15:53 PM PDT 24
Finished Jun 04 02:16:02 PM PDT 24
Peak memory 217628 kb
Host smart-ce51fb35-eef8-4b60-ac43-c3c4c435f255
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115976818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke.
115976818
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.2078231573
Short name T538
Test name
Test status
Simulation time 1869811095 ps
CPU time 43.85 seconds
Started Jun 04 02:15:53 PM PDT 24
Finished Jun 04 02:16:38 PM PDT 24
Peak memory 276196 kb
Host smart-54adc3fe-a023-4bd7-ba35-1fce80de5ce8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078231573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.2078231573
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1904960253
Short name T451
Test name
Test status
Simulation time 3799651925 ps
CPU time 29.15 seconds
Started Jun 04 02:15:53 PM PDT 24
Finished Jun 04 02:16:23 PM PDT 24
Peak memory 246572 kb
Host smart-d14048a6-34ae-4f15-9a40-26601813a093
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904960253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1904960253
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.1333338054
Short name T335
Test name
Test status
Simulation time 540194035 ps
CPU time 3.96 seconds
Started Jun 04 02:15:57 PM PDT 24
Finished Jun 04 02:16:01 PM PDT 24
Peak memory 217996 kb
Host smart-5ae0cace-10d8-4883-96d4-59994b5cc6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333338054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.1333338054
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.433466471
Short name T494
Test name
Test status
Simulation time 433298821 ps
CPU time 15.97 seconds
Started Jun 04 02:15:54 PM PDT 24
Finished Jun 04 02:16:11 PM PDT 24
Peak memory 218964 kb
Host smart-ddafc755-00e8-44bf-985c-7c0f6aabfb3f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433466471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.433466471
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2771325306
Short name T766
Test name
Test status
Simulation time 273152460 ps
CPU time 13.36 seconds
Started Jun 04 02:15:54 PM PDT 24
Finished Jun 04 02:16:09 PM PDT 24
Peak memory 225016 kb
Host smart-93c35ec6-268a-466a-bba2-3b2f29b2001e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771325306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2771325306
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3606294763
Short name T533
Test name
Test status
Simulation time 1604955831 ps
CPU time 10.77 seconds
Started Jun 04 02:15:54 PM PDT 24
Finished Jun 04 02:16:06 PM PDT 24
Peak memory 217900 kb
Host smart-25998e51-7858-46fe-a2a6-3924f4ec034d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606294763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3606294763
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.3706221159
Short name T507
Test name
Test status
Simulation time 786812259 ps
CPU time 11.68 seconds
Started Jun 04 02:15:56 PM PDT 24
Finished Jun 04 02:16:08 PM PDT 24
Peak memory 224852 kb
Host smart-54968eef-05ea-475a-9f38-ef847b47b6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706221159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.3706221159
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.3108467781
Short name T274
Test name
Test status
Simulation time 56508480 ps
CPU time 2.31 seconds
Started Jun 04 02:15:52 PM PDT 24
Finished Jun 04 02:15:55 PM PDT 24
Peak memory 217700 kb
Host smart-6c06195d-696b-406f-b406-034723c369f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108467781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.3108467781
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.4171575566
Short name T112
Test name
Test status
Simulation time 834697635 ps
CPU time 23.36 seconds
Started Jun 04 02:15:55 PM PDT 24
Finished Jun 04 02:16:19 PM PDT 24
Peak memory 250892 kb
Host smart-2417395b-2a49-40b9-b550-e1e7d301e95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171575566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.4171575566
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.2080303518
Short name T327
Test name
Test status
Simulation time 40282708 ps
CPU time 6.92 seconds
Started Jun 04 02:15:53 PM PDT 24
Finished Jun 04 02:16:01 PM PDT 24
Peak memory 250860 kb
Host smart-4138bde6-cc6a-45b3-b851-5cad5401ee31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080303518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.2080303518
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.2924407881
Short name T650
Test name
Test status
Simulation time 60447957310 ps
CPU time 532 seconds
Started Jun 04 02:15:54 PM PDT 24
Finished Jun 04 02:24:47 PM PDT 24
Peak memory 422112 kb
Host smart-da18cc4d-e4f3-408d-b091-332737f51af5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2924407881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.2924407881
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.173289829
Short name T322
Test name
Test status
Simulation time 38506653 ps
CPU time 0.98 seconds
Started Jun 04 02:15:58 PM PDT 24
Finished Jun 04 02:15:59 PM PDT 24
Peak memory 211624 kb
Host smart-08724f1e-70bb-491c-8850-1bf74f8740db
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173289829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ct
rl_volatile_unlock_smoke.173289829
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.1990031394
Short name T574
Test name
Test status
Simulation time 25937813 ps
CPU time 0.98 seconds
Started Jun 04 02:15:59 PM PDT 24
Finished Jun 04 02:16:01 PM PDT 24
Peak memory 208728 kb
Host smart-bb050be8-629b-4a2f-9bc4-c74b08736a3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990031394 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.1990031394
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.1745254116
Short name T818
Test name
Test status
Simulation time 1658201685 ps
CPU time 10.17 seconds
Started Jun 04 02:15:59 PM PDT 24
Finished Jun 04 02:16:10 PM PDT 24
Peak memory 217952 kb
Host smart-96f7b5d9-1d99-4048-8a1b-208297766966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745254116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.1745254116
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.1772936999
Short name T850
Test name
Test status
Simulation time 778943455 ps
CPU time 8.92 seconds
Started Jun 04 02:16:00 PM PDT 24
Finished Jun 04 02:16:09 PM PDT 24
Peak memory 217052 kb
Host smart-a2add9a7-d62f-4f85-b1b5-6e3c95349771
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772936999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.1772936999
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.2765627691
Short name T489
Test name
Test status
Simulation time 1112360782 ps
CPU time 19.04 seconds
Started Jun 04 02:16:00 PM PDT 24
Finished Jun 04 02:16:20 PM PDT 24
Peak memory 217840 kb
Host smart-c4dca2ed-6fb5-45f3-8a8b-a081dc900b98
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765627691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.2765627691
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2063464314
Short name T299
Test name
Test status
Simulation time 696732169 ps
CPU time 20.26 seconds
Started Jun 04 02:16:00 PM PDT 24
Finished Jun 04 02:16:21 PM PDT 24
Peak memory 217952 kb
Host smart-42f6fbe1-fc87-4932-9345-91ba2dc32603
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063464314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2063464314
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3468626177
Short name T256
Test name
Test status
Simulation time 1168072688 ps
CPU time 5.38 seconds
Started Jun 04 02:16:00 PM PDT 24
Finished Jun 04 02:16:07 PM PDT 24
Peak memory 217600 kb
Host smart-53e530a1-5ede-48d5-8755-7600f17e01ce
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468626177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3468626177
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.2589678792
Short name T521
Test name
Test status
Simulation time 7386738508 ps
CPU time 39.16 seconds
Started Jun 04 02:16:01 PM PDT 24
Finished Jun 04 02:16:41 PM PDT 24
Peak memory 283624 kb
Host smart-d0b0c409-8449-43b9-b73d-8564b0666d6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589678792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.2589678792
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2016958523
Short name T395
Test name
Test status
Simulation time 1081999523 ps
CPU time 11.45 seconds
Started Jun 04 02:16:01 PM PDT 24
Finished Jun 04 02:16:13 PM PDT 24
Peak memory 250828 kb
Host smart-2614200d-cc14-40a8-bd7e-62873b102b1f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016958523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2016958523
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3787126420
Short name T33
Test name
Test status
Simulation time 54927336 ps
CPU time 2.16 seconds
Started Jun 04 02:16:01 PM PDT 24
Finished Jun 04 02:16:04 PM PDT 24
Peak memory 218072 kb
Host smart-de3fc194-d7c3-49b7-b937-fc1f86bdf9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787126420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3787126420
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.1504174834
Short name T393
Test name
Test status
Simulation time 1660166489 ps
CPU time 11.01 seconds
Started Jun 04 02:16:01 PM PDT 24
Finished Jun 04 02:16:12 PM PDT 24
Peak memory 218916 kb
Host smart-5f5faf41-fcf9-4797-8d2b-e638f6427b3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504174834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.1504174834
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.2000436418
Short name T232
Test name
Test status
Simulation time 5646410308 ps
CPU time 28.08 seconds
Started Jun 04 02:16:00 PM PDT 24
Finished Jun 04 02:16:29 PM PDT 24
Peak memory 226084 kb
Host smart-df00e237-b9d4-4436-ad52-e86c60a5967c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000436418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.2000436418
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.1438149846
Short name T682
Test name
Test status
Simulation time 4127436120 ps
CPU time 10.42 seconds
Started Jun 04 02:16:02 PM PDT 24
Finished Jun 04 02:16:13 PM PDT 24
Peak memory 217964 kb
Host smart-0754df31-7a85-4a4f-896d-22d4d3769072
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438149846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
1438149846
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2966692844
Short name T750
Test name
Test status
Simulation time 462618981 ps
CPU time 16.95 seconds
Started Jun 04 02:16:01 PM PDT 24
Finished Jun 04 02:16:19 PM PDT 24
Peak memory 224952 kb
Host smart-092f3073-aa80-48ad-bc32-9ddb1be3db02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966692844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2966692844
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1615862579
Short name T620
Test name
Test status
Simulation time 165624046 ps
CPU time 1.82 seconds
Started Jun 04 02:15:58 PM PDT 24
Finished Jun 04 02:16:01 PM PDT 24
Peak memory 217696 kb
Host smart-e6e755bc-71de-43bd-89f5-e7c4f63e6bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615862579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1615862579
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.3770025495
Short name T793
Test name
Test status
Simulation time 1206933839 ps
CPU time 25.7 seconds
Started Jun 04 02:16:01 PM PDT 24
Finished Jun 04 02:16:28 PM PDT 24
Peak memory 250912 kb
Host smart-b45b5a8c-3214-4f2e-9d7f-1bc3c321c010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770025495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.3770025495
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.3859825214
Short name T840
Test name
Test status
Simulation time 222789682 ps
CPU time 8.36 seconds
Started Jun 04 02:16:00 PM PDT 24
Finished Jun 04 02:16:09 PM PDT 24
Peak memory 250932 kb
Host smart-87d80ffe-8fe1-4957-ba1a-2952bfbc20c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859825214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.3859825214
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.3780251592
Short name T547
Test name
Test status
Simulation time 1055448767 ps
CPU time 36.2 seconds
Started Jun 04 02:16:01 PM PDT 24
Finished Jun 04 02:16:38 PM PDT 24
Peak memory 247912 kb
Host smart-d1599d88-38de-439f-8ceb-d88c3808d681
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780251592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.3780251592
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2745405030
Short name T179
Test name
Test status
Simulation time 11151830 ps
CPU time 0.96 seconds
Started Jun 04 02:15:53 PM PDT 24
Finished Jun 04 02:15:55 PM PDT 24
Peak memory 211512 kb
Host smart-d9acc411-2a4a-4e38-a2d5-8409eb4f8e23
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745405030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2745405030
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1540801740
Short name T68
Test name
Test status
Simulation time 88305313 ps
CPU time 1.02 seconds
Started Jun 04 02:16:08 PM PDT 24
Finished Jun 04 02:16:10 PM PDT 24
Peak memory 209568 kb
Host smart-2a506710-59a2-4feb-ad34-8d9f7ae70d9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540801740 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1540801740
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2153748829
Short name T409
Test name
Test status
Simulation time 370192631 ps
CPU time 16.23 seconds
Started Jun 04 02:16:00 PM PDT 24
Finished Jun 04 02:16:17 PM PDT 24
Peak memory 217988 kb
Host smart-f751c18e-dec9-4d40-8268-701c8ea3f414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153748829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2153748829
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3175547984
Short name T28
Test name
Test status
Simulation time 3029735466 ps
CPU time 7.31 seconds
Started Jun 04 02:16:09 PM PDT 24
Finished Jun 04 02:16:17 PM PDT 24
Peak memory 209536 kb
Host smart-4373240c-53d8-4b00-851d-dd51d95909ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175547984 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3175547984
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.4160709298
Short name T237
Test name
Test status
Simulation time 3371240639 ps
CPU time 50.66 seconds
Started Jun 04 02:16:08 PM PDT 24
Finished Jun 04 02:17:00 PM PDT 24
Peak memory 218912 kb
Host smart-aa005411-1add-4c66-b305-43d0628031bd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160709298 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.4160709298
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.3058362071
Short name T760
Test name
Test status
Simulation time 2667048533 ps
CPU time 8.06 seconds
Started Jun 04 02:16:08 PM PDT 24
Finished Jun 04 02:16:16 PM PDT 24
Peak memory 218092 kb
Host smart-29782ade-9272-443b-9310-fbfc695d7348
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058362071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.3058362071
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.4275430967
Short name T400
Test name
Test status
Simulation time 216272760 ps
CPU time 3.58 seconds
Started Jun 04 02:16:00 PM PDT 24
Finished Jun 04 02:16:04 PM PDT 24
Peak memory 217588 kb
Host smart-4031ec58-591b-4224-a23c-5cb12ecce5bc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275430967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.4275430967
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1335193168
Short name T266
Test name
Test status
Simulation time 3278234794 ps
CPU time 43.38 seconds
Started Jun 04 02:16:01 PM PDT 24
Finished Jun 04 02:16:45 PM PDT 24
Peak memory 269184 kb
Host smart-395a64be-b69a-40f0-a27a-dbd01d57c0ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335193168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1335193168
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.3875821352
Short name T253
Test name
Test status
Simulation time 12138345599 ps
CPU time 17.43 seconds
Started Jun 04 02:16:08 PM PDT 24
Finished Jun 04 02:16:26 PM PDT 24
Peak memory 250740 kb
Host smart-054caa6a-a02c-4feb-a85e-9800e06e12e2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875821352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.3875821352
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.4088850730
Short name T281
Test name
Test status
Simulation time 18933856 ps
CPU time 1.53 seconds
Started Jun 04 02:16:01 PM PDT 24
Finished Jun 04 02:16:03 PM PDT 24
Peak memory 218076 kb
Host smart-ac3df0b5-1837-4921-ac17-39cc43da4acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088850730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.4088850730
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.2744658099
Short name T758
Test name
Test status
Simulation time 1503925613 ps
CPU time 7.98 seconds
Started Jun 04 02:16:10 PM PDT 24
Finished Jun 04 02:16:19 PM PDT 24
Peak memory 218508 kb
Host smart-93882601-1e82-4319-a343-346f7aca97f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744658099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.2744658099
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.4286269784
Short name T452
Test name
Test status
Simulation time 2157302394 ps
CPU time 11.09 seconds
Started Jun 04 02:16:08 PM PDT 24
Finished Jun 04 02:16:20 PM PDT 24
Peak memory 226032 kb
Host smart-95489afc-710f-49ae-8dc9-e5452961e9c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286269784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_d
igest.4286269784
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1110782893
Short name T401
Test name
Test status
Simulation time 1288675866 ps
CPU time 11.38 seconds
Started Jun 04 02:16:09 PM PDT 24
Finished Jun 04 02:16:21 PM PDT 24
Peak memory 217884 kb
Host smart-a8c92f6d-aa64-49ac-a076-02b14693b453
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110782893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1110782893
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.591449102
Short name T828
Test name
Test status
Simulation time 819911164 ps
CPU time 12.29 seconds
Started Jun 04 02:16:01 PM PDT 24
Finished Jun 04 02:16:15 PM PDT 24
Peak memory 225508 kb
Host smart-fbf17cd4-6e26-495a-ad52-11ba7f36b07a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591449102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.591449102
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.4000957941
Short name T328
Test name
Test status
Simulation time 315190298 ps
CPU time 2.81 seconds
Started Jun 04 02:16:01 PM PDT 24
Finished Jun 04 02:16:05 PM PDT 24
Peak memory 217720 kb
Host smart-fd705ce6-4dc6-4b50-a207-63e277d125f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000957941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.4000957941
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.579175699
Short name T252
Test name
Test status
Simulation time 1415240406 ps
CPU time 22.79 seconds
Started Jun 04 02:16:00 PM PDT 24
Finished Jun 04 02:16:24 PM PDT 24
Peak memory 250900 kb
Host smart-e21598bf-c63a-4a67-a82f-9bb5feefb6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579175699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.579175699
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.890079005
Short name T77
Test name
Test status
Simulation time 86742690 ps
CPU time 7.44 seconds
Started Jun 04 02:16:00 PM PDT 24
Finished Jun 04 02:16:09 PM PDT 24
Peak memory 244432 kb
Host smart-b9995972-8546-4de4-91e8-4da4b22e8769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890079005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.890079005
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.3568140506
Short name T548
Test name
Test status
Simulation time 24035445010 ps
CPU time 145.62 seconds
Started Jun 04 02:16:08 PM PDT 24
Finished Jun 04 02:18:34 PM PDT 24
Peak memory 283652 kb
Host smart-7448a848-9559-4c2f-b0ed-cd90e0c4eb27
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568140506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.3568140506
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.938761097
Short name T674
Test name
Test status
Simulation time 10673287 ps
CPU time 0.82 seconds
Started Jun 04 02:15:58 PM PDT 24
Finished Jun 04 02:16:00 PM PDT 24
Peak memory 208100 kb
Host smart-16ec1325-e9c4-451f-b4a8-dcefb5974b37
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938761097 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ct
rl_volatile_unlock_smoke.938761097
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.4194395108
Short name T727
Test name
Test status
Simulation time 82935879 ps
CPU time 1.07 seconds
Started Jun 04 02:13:17 PM PDT 24
Finished Jun 04 02:13:18 PM PDT 24
Peak memory 209568 kb
Host smart-cf99bd16-56a0-42fe-9dfd-cdbf8c821c66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194395108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.4194395108
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3662370207
Short name T222
Test name
Test status
Simulation time 14251076 ps
CPU time 0.79 seconds
Started Jun 04 02:13:13 PM PDT 24
Finished Jun 04 02:13:14 PM PDT 24
Peak memory 208452 kb
Host smart-de9ade92-60f7-4aaf-a55a-6da91f393252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662370207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3662370207
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.891095658
Short name T551
Test name
Test status
Simulation time 300553081 ps
CPU time 12.23 seconds
Started Jun 04 02:13:10 PM PDT 24
Finished Jun 04 02:13:23 PM PDT 24
Peak memory 218064 kb
Host smart-24fd4366-ea69-4514-b7a9-a0280a155e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891095658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.891095658
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1589778445
Short name T537
Test name
Test status
Simulation time 463232250 ps
CPU time 6.61 seconds
Started Jun 04 02:13:17 PM PDT 24
Finished Jun 04 02:13:24 PM PDT 24
Peak memory 209464 kb
Host smart-d398730e-1fe4-468f-bd3e-9f9dbdc6d60d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589778445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1589778445
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1561520474
Short name T175
Test name
Test status
Simulation time 2069153762 ps
CPU time 30.63 seconds
Started Jun 04 02:13:17 PM PDT 24
Finished Jun 04 02:13:48 PM PDT 24
Peak memory 217840 kb
Host smart-184e4cb1-24a0-405c-9b33-ce2ffb20fe62
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561520474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1561520474
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2799282444
Short name T586
Test name
Test status
Simulation time 170222581 ps
CPU time 4.72 seconds
Started Jun 04 02:13:18 PM PDT 24
Finished Jun 04 02:13:23 PM PDT 24
Peak memory 217116 kb
Host smart-8f9a628a-1173-4489-b855-bac6694ffa1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799282444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
799282444
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.3492630696
Short name T296
Test name
Test status
Simulation time 658081775 ps
CPU time 10.79 seconds
Started Jun 04 02:13:16 PM PDT 24
Finished Jun 04 02:13:27 PM PDT 24
Peak memory 217888 kb
Host smart-9e609091-ba9c-42f8-8218-07f5ae59f69e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492630696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.3492630696
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3269454404
Short name T829
Test name
Test status
Simulation time 2719770571 ps
CPU time 11.17 seconds
Started Jun 04 02:13:15 PM PDT 24
Finished Jun 04 02:13:27 PM PDT 24
Peak memory 217716 kb
Host smart-c44e0eb2-c15a-47b1-b6f2-271f7fea7eeb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269454404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_regwen_during_op.3269454404
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.1004426679
Short name T419
Test name
Test status
Simulation time 496747185 ps
CPU time 12.46 seconds
Started Jun 04 02:13:10 PM PDT 24
Finished Jun 04 02:13:23 PM PDT 24
Peak memory 217748 kb
Host smart-47ca9975-d044-41d3-bde3-d8b3747d7213
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004426679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
1004426679
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.2814798192
Short name T435
Test name
Test status
Simulation time 2749652469 ps
CPU time 84.17 seconds
Started Jun 04 02:13:10 PM PDT 24
Finished Jun 04 02:14:35 PM PDT 24
Peak memory 275932 kb
Host smart-e8d136b8-485b-4e45-90ba-7d93fdd17b6a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814798192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jta
g_state_failure.2814798192
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.34768110
Short name T848
Test name
Test status
Simulation time 1616468678 ps
CPU time 24.14 seconds
Started Jun 04 02:13:09 PM PDT 24
Finished Jun 04 02:13:34 PM PDT 24
Peak memory 223236 kb
Host smart-c4ef726a-2fef-4096-bd3d-c36b0e1ecb87
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34768110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jt
ag_state_post_trans.34768110
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.1748641859
Short name T474
Test name
Test status
Simulation time 95197512 ps
CPU time 3.88 seconds
Started Jun 04 02:13:10 PM PDT 24
Finished Jun 04 02:13:15 PM PDT 24
Peak memory 217972 kb
Host smart-c190cc4e-e797-4e79-93b8-29bea15eb991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748641859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.1748641859
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.3156848231
Short name T584
Test name
Test status
Simulation time 1816543136 ps
CPU time 11.86 seconds
Started Jun 04 02:13:12 PM PDT 24
Finished Jun 04 02:13:24 PM PDT 24
Peak memory 217788 kb
Host smart-f1ba150f-4cbd-40ff-9ac0-95c59649b700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156848231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.3156848231
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.3923918666
Short name T526
Test name
Test status
Simulation time 836420022 ps
CPU time 11.83 seconds
Started Jun 04 02:13:18 PM PDT 24
Finished Jun 04 02:13:30 PM PDT 24
Peak memory 218908 kb
Host smart-852594b7-f0e0-4e53-be19-c9de505c042a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923918666 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.3923918666
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.3060267927
Short name T630
Test name
Test status
Simulation time 554472002 ps
CPU time 13.93 seconds
Started Jun 04 02:13:17 PM PDT 24
Finished Jun 04 02:13:32 PM PDT 24
Peak memory 225988 kb
Host smart-7d2361f0-a957-409d-8456-7914b5daa045
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060267927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.3060267927
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.257624828
Short name T184
Test name
Test status
Simulation time 2129017364 ps
CPU time 12 seconds
Started Jun 04 02:13:19 PM PDT 24
Finished Jun 04 02:13:31 PM PDT 24
Peak memory 217932 kb
Host smart-a24fb5ab-2677-4aa4-8a8d-c2c2125f4536
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257624828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.257624828
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.308138350
Short name T764
Test name
Test status
Simulation time 418664017 ps
CPU time 9.66 seconds
Started Jun 04 02:13:12 PM PDT 24
Finished Jun 04 02:13:23 PM PDT 24
Peak memory 225280 kb
Host smart-67d55c34-9a61-4c6e-999e-d5b67b21ba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308138350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.308138350
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.1470908106
Short name T465
Test name
Test status
Simulation time 26740356 ps
CPU time 1.94 seconds
Started Jun 04 02:13:03 PM PDT 24
Finished Jun 04 02:13:05 PM PDT 24
Peak memory 213672 kb
Host smart-a8568ec6-fae4-4656-a475-3b3b7de08bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470908106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.1470908106
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.297862377
Short name T251
Test name
Test status
Simulation time 1005779712 ps
CPU time 24.39 seconds
Started Jun 04 02:13:01 PM PDT 24
Finished Jun 04 02:13:26 PM PDT 24
Peak memory 250940 kb
Host smart-a5df858d-a54d-4ee9-8da5-6276a38b12fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297862377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.297862377
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.641130595
Short name T275
Test name
Test status
Simulation time 287189485 ps
CPU time 8.5 seconds
Started Jun 04 02:13:10 PM PDT 24
Finished Jun 04 02:13:19 PM PDT 24
Peak memory 250784 kb
Host smart-f948d7dc-2385-4cc7-abb3-862ee582d307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641130595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.641130595
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.4170294891
Short name T544
Test name
Test status
Simulation time 13024410228 ps
CPU time 446.55 seconds
Started Jun 04 02:13:17 PM PDT 24
Finished Jun 04 02:20:44 PM PDT 24
Peak memory 332460 kb
Host smart-e8130d34-1910-4978-99d8-d10e8fbebf73
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170294891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.4170294891
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3898470935
Short name T153
Test name
Test status
Simulation time 13872796867 ps
CPU time 225.8 seconds
Started Jun 04 02:13:17 PM PDT 24
Finished Jun 04 02:17:03 PM PDT 24
Peak memory 283852 kb
Host smart-4b27574a-17b7-4766-b25e-055899ebd7a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3898470935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.3898470935
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3467255015
Short name T637
Test name
Test status
Simulation time 11278392 ps
CPU time 1.04 seconds
Started Jun 04 02:13:03 PM PDT 24
Finished Jun 04 02:13:05 PM PDT 24
Peak memory 211416 kb
Host smart-3d92efc0-5e56-4ac5-8281-47a735090f80
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467255015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3467255015
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.3889244709
Short name T686
Test name
Test status
Simulation time 76214606 ps
CPU time 0.96 seconds
Started Jun 04 02:16:17 PM PDT 24
Finished Jun 04 02:16:19 PM PDT 24
Peak memory 209496 kb
Host smart-d1bca261-0148-4ee6-af38-8088a5f36654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889244709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.3889244709
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.1267890929
Short name T647
Test name
Test status
Simulation time 609177070 ps
CPU time 10.73 seconds
Started Jun 04 02:16:23 PM PDT 24
Finished Jun 04 02:16:35 PM PDT 24
Peak memory 217980 kb
Host smart-e70a83d7-9ca4-4c5e-8347-d9bfa6a69ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267890929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.1267890929
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.875976384
Short name T397
Test name
Test status
Simulation time 2605551839 ps
CPU time 14.02 seconds
Started Jun 04 02:16:17 PM PDT 24
Finished Jun 04 02:16:32 PM PDT 24
Peak memory 209548 kb
Host smart-1b380344-4991-4434-b36f-1ad7dc546daf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875976384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.875976384
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2598365166
Short name T98
Test name
Test status
Simulation time 74002051 ps
CPU time 3.77 seconds
Started Jun 04 02:16:16 PM PDT 24
Finished Jun 04 02:16:22 PM PDT 24
Peak memory 218076 kb
Host smart-876a5ca7-211d-473e-8cd8-9a4e756d44a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598365166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2598365166
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.44786391
Short name T442
Test name
Test status
Simulation time 279183073 ps
CPU time 14.04 seconds
Started Jun 04 02:16:17 PM PDT 24
Finished Jun 04 02:16:33 PM PDT 24
Peak memory 218900 kb
Host smart-0bcd400c-24b0-468f-999e-5d9ef08a0a82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44786391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.44786391
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.4195924202
Short name T417
Test name
Test status
Simulation time 1204369473 ps
CPU time 21.24 seconds
Started Jun 04 02:16:16 PM PDT 24
Finished Jun 04 02:16:38 PM PDT 24
Peak memory 226028 kb
Host smart-2bc00efb-6a8b-4820-9607-48f80a305fbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195924202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.4195924202
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.1309200363
Short name T849
Test name
Test status
Simulation time 7322640990 ps
CPU time 14.25 seconds
Started Jun 04 02:16:18 PM PDT 24
Finished Jun 04 02:16:33 PM PDT 24
Peak memory 217960 kb
Host smart-4e43abf9-2006-4dcb-8dff-ec979992763d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309200363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
1309200363
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.449947113
Short name T702
Test name
Test status
Simulation time 309463806 ps
CPU time 8.47 seconds
Started Jun 04 02:16:15 PM PDT 24
Finished Jun 04 02:16:24 PM PDT 24
Peak memory 218028 kb
Host smart-6a68a3b9-8820-493e-9dc3-be26d2649ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449947113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.449947113
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.3485672370
Short name T79
Test name
Test status
Simulation time 48426293 ps
CPU time 3.14 seconds
Started Jun 04 02:16:09 PM PDT 24
Finished Jun 04 02:16:13 PM PDT 24
Peak memory 214444 kb
Host smart-7683f28a-2034-4a6c-9a6e-6342400a9c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485672370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.3485672370
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.2321473384
Short name T560
Test name
Test status
Simulation time 797325285 ps
CPU time 21.24 seconds
Started Jun 04 02:16:16 PM PDT 24
Finished Jun 04 02:16:39 PM PDT 24
Peak memory 250860 kb
Host smart-6c853a85-d45e-41b2-a398-cd3fb6ee7e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321473384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.2321473384
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.959162961
Short name T539
Test name
Test status
Simulation time 70228068 ps
CPU time 8.3 seconds
Started Jun 04 02:16:17 PM PDT 24
Finished Jun 04 02:16:27 PM PDT 24
Peak memory 251016 kb
Host smart-f327cad1-b94c-4f49-96d4-a2c0a3e2d970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959162961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.959162961
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3777324015
Short name T609
Test name
Test status
Simulation time 45191509532 ps
CPU time 113.9 seconds
Started Jun 04 02:16:20 PM PDT 24
Finished Jun 04 02:18:15 PM PDT 24
Peak memory 250692 kb
Host smart-4d04cb1e-358e-4603-b22c-25006d359193
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777324015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3777324015
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.3019523329
Short name T843
Test name
Test status
Simulation time 14522106 ps
CPU time 1.03 seconds
Started Jun 04 02:16:08 PM PDT 24
Finished Jun 04 02:16:10 PM PDT 24
Peak memory 211464 kb
Host smart-924e1a90-1f53-4e4c-86c8-ae8ac278e1e9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019523329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.3019523329
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.1038390600
Short name T703
Test name
Test status
Simulation time 39454047 ps
CPU time 0.91 seconds
Started Jun 04 02:16:22 PM PDT 24
Finished Jun 04 02:16:24 PM PDT 24
Peak memory 208756 kb
Host smart-7d7eac0e-e59e-466b-8d1f-edfbe2e68552
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038390600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.1038390600
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3554619096
Short name T108
Test name
Test status
Simulation time 270258403 ps
CPU time 8.31 seconds
Started Jun 04 02:16:25 PM PDT 24
Finished Jun 04 02:16:34 PM PDT 24
Peak memory 217996 kb
Host smart-22e438b7-a27e-4824-93b2-145b47b22e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554619096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3554619096
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.1776517032
Short name T707
Test name
Test status
Simulation time 1610589963 ps
CPU time 3.88 seconds
Started Jun 04 02:16:24 PM PDT 24
Finished Jun 04 02:16:28 PM PDT 24
Peak memory 217036 kb
Host smart-90deb262-5569-4267-bcbd-2d65391dd6fe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776517032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.1776517032
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2652970039
Short name T508
Test name
Test status
Simulation time 152797128 ps
CPU time 3.12 seconds
Started Jun 04 02:16:24 PM PDT 24
Finished Jun 04 02:16:28 PM PDT 24
Peak memory 217920 kb
Host smart-430bf320-3684-49d3-ae36-8e09031f43f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652970039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2652970039
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2355120427
Short name T357
Test name
Test status
Simulation time 793231830 ps
CPU time 18.47 seconds
Started Jun 04 02:16:23 PM PDT 24
Finished Jun 04 02:16:42 PM PDT 24
Peak memory 218928 kb
Host smart-15cade18-8036-4eeb-9598-44efd5744ff2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355120427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2355120427
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1249186603
Short name T594
Test name
Test status
Simulation time 715515132 ps
CPU time 6.9 seconds
Started Jun 04 02:16:33 PM PDT 24
Finished Jun 04 02:16:40 PM PDT 24
Peak memory 224880 kb
Host smart-59010409-314a-4176-93f5-393bd1fec783
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249186603 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1249186603
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.3614528255
Short name T824
Test name
Test status
Simulation time 1527838855 ps
CPU time 7.43 seconds
Started Jun 04 02:16:23 PM PDT 24
Finished Jun 04 02:16:32 PM PDT 24
Peak memory 217892 kb
Host smart-e1c453b3-2a96-427f-8a9f-89a78a75ab54
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614528255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
3614528255
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3888873638
Short name T573
Test name
Test status
Simulation time 229876101 ps
CPU time 8.46 seconds
Started Jun 04 02:16:25 PM PDT 24
Finished Jun 04 02:16:34 PM PDT 24
Peak memory 218024 kb
Host smart-4baf2b03-41bd-4d94-b31f-927f561fb8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888873638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3888873638
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.2718773696
Short name T463
Test name
Test status
Simulation time 1180174863 ps
CPU time 8.03 seconds
Started Jun 04 02:16:22 PM PDT 24
Finished Jun 04 02:16:30 PM PDT 24
Peak memory 217676 kb
Host smart-b4183805-41b5-48bd-b4c7-f648d43d47aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718773696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.2718773696
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.2638457169
Short name T445
Test name
Test status
Simulation time 2033906343 ps
CPU time 17.5 seconds
Started Jun 04 02:16:16 PM PDT 24
Finished Jun 04 02:16:35 PM PDT 24
Peak memory 250772 kb
Host smart-9fa6a2ba-d9f5-440e-929c-e4bf449dc00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638457169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.2638457169
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.3414076685
Short name T259
Test name
Test status
Simulation time 88702443 ps
CPU time 7.52 seconds
Started Jun 04 02:16:16 PM PDT 24
Finished Jun 04 02:16:25 PM PDT 24
Peak memory 246748 kb
Host smart-686f3b9e-9ee8-4b4d-93ff-dd5dba47a18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414076685 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.3414076685
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.3389619954
Short name T691
Test name
Test status
Simulation time 31394872 ps
CPU time 0.88 seconds
Started Jun 04 02:16:20 PM PDT 24
Finished Jun 04 02:16:22 PM PDT 24
Peak memory 211408 kb
Host smart-62213ed4-b72a-4a69-8797-c75316b6c1fa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389619954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.3389619954
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.460887651
Short name T831
Test name
Test status
Simulation time 27393254 ps
CPU time 1.23 seconds
Started Jun 04 02:16:30 PM PDT 24
Finished Jun 04 02:16:32 PM PDT 24
Peak memory 208736 kb
Host smart-9eb6897e-ae2a-4f99-a2d7-5a330e545f6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460887651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.460887651
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3274513375
Short name T741
Test name
Test status
Simulation time 441710983 ps
CPU time 13.16 seconds
Started Jun 04 02:16:24 PM PDT 24
Finished Jun 04 02:16:38 PM PDT 24
Peak memory 217940 kb
Host smart-17d8d91a-6776-442a-8fc6-0af16013eb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274513375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3274513375
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.3082336118
Short name T667
Test name
Test status
Simulation time 2985402211 ps
CPU time 8.62 seconds
Started Jun 04 02:16:33 PM PDT 24
Finished Jun 04 02:16:42 PM PDT 24
Peak memory 209444 kb
Host smart-430fd185-30c9-4dee-a4d7-3b314a7d778f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082336118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.3082336118
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2735807078
Short name T696
Test name
Test status
Simulation time 27732260 ps
CPU time 1.97 seconds
Started Jun 04 02:16:23 PM PDT 24
Finished Jun 04 02:16:26 PM PDT 24
Peak memory 218012 kb
Host smart-43300beb-3f84-4845-b2d8-6e7080e7dce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735807078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2735807078
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1056966933
Short name T803
Test name
Test status
Simulation time 1190538312 ps
CPU time 15.8 seconds
Started Jun 04 02:16:22 PM PDT 24
Finished Jun 04 02:16:39 PM PDT 24
Peak memory 218916 kb
Host smart-77950f14-dbf8-4b1f-b27f-8ba693945639
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056966933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1056966933
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.3677126369
Short name T18
Test name
Test status
Simulation time 1142557026 ps
CPU time 16.76 seconds
Started Jun 04 02:16:24 PM PDT 24
Finished Jun 04 02:16:41 PM PDT 24
Peak memory 225988 kb
Host smart-03b285f6-7475-4c7f-9f65-4649febd3bfd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677126369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.3677126369
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.2274057538
Short name T844
Test name
Test status
Simulation time 1121069110 ps
CPU time 8.65 seconds
Started Jun 04 02:16:25 PM PDT 24
Finished Jun 04 02:16:34 PM PDT 24
Peak memory 217972 kb
Host smart-add772fd-fce8-485d-8141-f9c195753906
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274057538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
2274057538
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.1190100573
Short name T681
Test name
Test status
Simulation time 217149409 ps
CPU time 8.83 seconds
Started Jun 04 02:16:23 PM PDT 24
Finished Jun 04 02:16:32 PM PDT 24
Peak memory 224924 kb
Host smart-760a2085-a95a-49cb-8bf7-c7189a4ef0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190100573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.1190100573
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1350339046
Short name T771
Test name
Test status
Simulation time 30582564 ps
CPU time 1.68 seconds
Started Jun 04 02:16:23 PM PDT 24
Finished Jun 04 02:16:25 PM PDT 24
Peak memory 213688 kb
Host smart-38a3711b-8458-40d8-98e4-d086ad2e5698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350339046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1350339046
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.4106324113
Short name T325
Test name
Test status
Simulation time 615731053 ps
CPU time 20.78 seconds
Started Jun 04 02:16:33 PM PDT 24
Finished Jun 04 02:16:54 PM PDT 24
Peak memory 250824 kb
Host smart-fda39610-b274-4170-986e-d2c118627247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106324113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.4106324113
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.1603924694
Short name T632
Test name
Test status
Simulation time 407122449 ps
CPU time 6.6 seconds
Started Jun 04 02:16:23 PM PDT 24
Finished Jun 04 02:16:31 PM PDT 24
Peak memory 246560 kb
Host smart-b757d5d7-4e1a-4b7d-b13c-497757a43c00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603924694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.1603924694
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3173913266
Short name T709
Test name
Test status
Simulation time 7845325311 ps
CPU time 137.92 seconds
Started Jun 04 02:16:31 PM PDT 24
Finished Jun 04 02:18:51 PM PDT 24
Peak memory 275880 kb
Host smart-92d77fb4-5770-4abd-8829-e54051f489ea
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173913266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3173913266
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2501572944
Short name T791
Test name
Test status
Simulation time 25531004 ps
CPU time 0.91 seconds
Started Jun 04 02:16:22 PM PDT 24
Finished Jun 04 02:16:23 PM PDT 24
Peak memory 211524 kb
Host smart-b68f16bc-254a-486f-94c6-0d9a8e91f55f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501572944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2501572944
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.4145228829
Short name T487
Test name
Test status
Simulation time 63497803 ps
CPU time 1.01 seconds
Started Jun 04 02:16:32 PM PDT 24
Finished Jun 04 02:16:34 PM PDT 24
Peak memory 208692 kb
Host smart-de3e0d46-67ef-4c68-a0e8-3473dfea080e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145228829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.4145228829
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.2420662490
Short name T337
Test name
Test status
Simulation time 301398445 ps
CPU time 10.61 seconds
Started Jun 04 02:16:38 PM PDT 24
Finished Jun 04 02:16:49 PM PDT 24
Peak memory 218108 kb
Host smart-094f07c0-7586-4299-900d-7e89b5f37e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420662490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.2420662490
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.3387465384
Short name T704
Test name
Test status
Simulation time 1095559211 ps
CPU time 7.69 seconds
Started Jun 04 02:16:37 PM PDT 24
Finished Jun 04 02:16:46 PM PDT 24
Peak memory 209444 kb
Host smart-0c3cae73-5e56-4b2f-91d7-3f43fa90e6ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387465384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.3387465384
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.3031469213
Short name T471
Test name
Test status
Simulation time 48334921 ps
CPU time 1.5 seconds
Started Jun 04 02:16:37 PM PDT 24
Finished Jun 04 02:16:39 PM PDT 24
Peak memory 217988 kb
Host smart-ce50734b-c415-4db3-ad1f-336b39036697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031469213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.3031469213
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.2960517570
Short name T834
Test name
Test status
Simulation time 853008331 ps
CPU time 8.68 seconds
Started Jun 04 02:16:33 PM PDT 24
Finished Jun 04 02:16:42 PM PDT 24
Peak memory 217976 kb
Host smart-d3f8b6ef-edea-42ff-a258-b1b265904a93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960517570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.2960517570
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.4057874083
Short name T563
Test name
Test status
Simulation time 282827569 ps
CPU time 12.97 seconds
Started Jun 04 02:16:34 PM PDT 24
Finished Jun 04 02:16:48 PM PDT 24
Peak memory 225924 kb
Host smart-f16c4d23-71a1-4136-a920-b3e57b22429f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057874083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.4057874083
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1469882332
Short name T606
Test name
Test status
Simulation time 606650640 ps
CPU time 7.96 seconds
Started Jun 04 02:16:30 PM PDT 24
Finished Jun 04 02:16:39 PM PDT 24
Peak memory 217924 kb
Host smart-eca3f8d5-dd46-434b-9d4a-ff2db23b74a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469882332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1469882332
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.672992166
Short name T561
Test name
Test status
Simulation time 1153948914 ps
CPU time 8.47 seconds
Started Jun 04 02:16:31 PM PDT 24
Finished Jun 04 02:16:40 PM PDT 24
Peak memory 225336 kb
Host smart-a0dfb74e-0a35-459c-8cf8-1e34061f76af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672992166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.672992166
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1245797013
Short name T166
Test name
Test status
Simulation time 400335371 ps
CPU time 2.83 seconds
Started Jun 04 02:16:32 PM PDT 24
Finished Jun 04 02:16:36 PM PDT 24
Peak memory 217808 kb
Host smart-7fa38dbe-182d-411a-b628-3e06b3b68ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245797013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1245797013
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1982631641
Short name T496
Test name
Test status
Simulation time 264320659 ps
CPU time 28.37 seconds
Started Jun 04 02:16:32 PM PDT 24
Finished Jun 04 02:17:02 PM PDT 24
Peak memory 250884 kb
Host smart-2088c65d-3090-4405-9a04-5c415a5119ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982631641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1982631641
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.2203354812
Short name T528
Test name
Test status
Simulation time 100583433 ps
CPU time 6.73 seconds
Started Jun 04 02:16:38 PM PDT 24
Finished Jun 04 02:16:46 PM PDT 24
Peak memory 246388 kb
Host smart-9d04b520-a7d9-4c07-a1a8-1a06239e23ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203354812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.2203354812
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.745362350
Short name T58
Test name
Test status
Simulation time 6966079032 ps
CPU time 372.68 seconds
Started Jun 04 02:16:37 PM PDT 24
Finished Jun 04 02:22:51 PM PDT 24
Peak memory 421880 kb
Host smart-9620afc7-9cc5-4d57-a1c1-794ae9a8744b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745362350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.745362350
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.4135216614
Short name T582
Test name
Test status
Simulation time 29229808 ps
CPU time 0.81 seconds
Started Jun 04 02:16:31 PM PDT 24
Finished Jun 04 02:16:33 PM PDT 24
Peak memory 211584 kb
Host smart-ece883b4-2da3-4c09-86cc-709aafb44d43
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135216614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.4135216614
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.4080897691
Short name T189
Test name
Test status
Simulation time 97457720 ps
CPU time 0.88 seconds
Started Jun 04 02:16:39 PM PDT 24
Finished Jun 04 02:16:41 PM PDT 24
Peak memory 208664 kb
Host smart-5ca8cc13-b886-407c-8c9b-0107e529a98e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080897691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.4080897691
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.2865361964
Short name T716
Test name
Test status
Simulation time 695086049 ps
CPU time 16.37 seconds
Started Jun 04 02:16:38 PM PDT 24
Finished Jun 04 02:16:56 PM PDT 24
Peak memory 217948 kb
Host smart-c041b282-be1f-4735-a240-713970c692ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865361964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.2865361964
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.1013998950
Short name T285
Test name
Test status
Simulation time 459618708 ps
CPU time 3.36 seconds
Started Jun 04 02:16:41 PM PDT 24
Finished Jun 04 02:16:45 PM PDT 24
Peak memory 217704 kb
Host smart-be19bce2-5894-4260-aa40-a4fbee1d23b8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013998950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.1013998950
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1924838409
Short name T687
Test name
Test status
Simulation time 34560673 ps
CPU time 1.96 seconds
Started Jun 04 02:16:39 PM PDT 24
Finished Jun 04 02:16:42 PM PDT 24
Peak memory 217972 kb
Host smart-bf6f8bfa-61a5-4bb6-a168-d654f6dfcd0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924838409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1924838409
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.2721841718
Short name T742
Test name
Test status
Simulation time 755958772 ps
CPU time 10.31 seconds
Started Jun 04 02:16:37 PM PDT 24
Finished Jun 04 02:16:48 PM PDT 24
Peak memory 217956 kb
Host smart-5298f54b-4f5a-4cd5-a763-49f2a0578d99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721841718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.2721841718
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.535219710
Short name T17
Test name
Test status
Simulation time 1562480289 ps
CPU time 18.43 seconds
Started Jun 04 02:16:39 PM PDT 24
Finished Jun 04 02:16:58 PM PDT 24
Peak memory 225308 kb
Host smart-c988ec55-9bd1-4b48-a38f-5eb0dfec0bf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535219710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.535219710
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.3180061178
Short name T801
Test name
Test status
Simulation time 605632001 ps
CPU time 9.3 seconds
Started Jun 04 02:16:39 PM PDT 24
Finished Jun 04 02:16:49 PM PDT 24
Peak memory 217908 kb
Host smart-af3be04a-f74a-4ba0-9660-7d5f469a35af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180061178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
3180061178
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.4124492668
Short name T623
Test name
Test status
Simulation time 649328900 ps
CPU time 11.88 seconds
Started Jun 04 02:16:39 PM PDT 24
Finished Jun 04 02:16:52 PM PDT 24
Peak memory 224864 kb
Host smart-d45ee09c-2d71-44f6-bd66-971574fa4959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124492668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.4124492668
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3665685134
Short name T431
Test name
Test status
Simulation time 47959377 ps
CPU time 3.49 seconds
Started Jun 04 02:16:40 PM PDT 24
Finished Jun 04 02:16:44 PM PDT 24
Peak memory 214948 kb
Host smart-ccea4d1f-339c-4680-b62c-16b8ba41875b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665685134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3665685134
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.1163040090
Short name T284
Test name
Test status
Simulation time 179038876 ps
CPU time 23.28 seconds
Started Jun 04 02:16:39 PM PDT 24
Finished Jun 04 02:17:03 PM PDT 24
Peak memory 250660 kb
Host smart-ffa684d0-58a9-4730-aabd-473bae8bd337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163040090 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.1163040090
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.327636043
Short name T157
Test name
Test status
Simulation time 489234243 ps
CPU time 8.03 seconds
Started Jun 04 02:16:38 PM PDT 24
Finished Jun 04 02:16:47 PM PDT 24
Peak memory 247340 kb
Host smart-e710ae9b-599b-4598-8994-ded307e4d0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327636043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.327636043
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.942171541
Short name T243
Test name
Test status
Simulation time 4636085234 ps
CPU time 187.45 seconds
Started Jun 04 02:16:39 PM PDT 24
Finished Jun 04 02:19:48 PM PDT 24
Peak memory 283732 kb
Host smart-fd5cea69-57aa-48fe-97b3-9b290fe8d547
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942171541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.942171541
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.1137567595
Short name T181
Test name
Test status
Simulation time 59893443732 ps
CPU time 255.06 seconds
Started Jun 04 02:16:41 PM PDT 24
Finished Jun 04 02:20:57 PM PDT 24
Peak memory 283848 kb
Host smart-17f50518-9705-4b7c-9b0a-05d5fae8f2d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1137567595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.1137567595
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.4125301933
Short name T162
Test name
Test status
Simulation time 11985543 ps
CPU time 1 seconds
Started Jun 04 02:16:40 PM PDT 24
Finished Jun 04 02:16:42 PM PDT 24
Peak memory 211436 kb
Host smart-f5aec82b-f199-4ddb-a940-467c096a9516
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125301933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.4125301933
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.2449635074
Short name T851
Test name
Test status
Simulation time 15585827 ps
CPU time 0.9 seconds
Started Jun 04 02:16:48 PM PDT 24
Finished Jun 04 02:16:49 PM PDT 24
Peak memory 208512 kb
Host smart-5789000f-93e1-4d23-b2bf-249f2086f83d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449635074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.2449635074
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.1984815349
Short name T44
Test name
Test status
Simulation time 741722964 ps
CPU time 11.56 seconds
Started Jun 04 02:16:38 PM PDT 24
Finished Jun 04 02:16:51 PM PDT 24
Peak memory 217976 kb
Host smart-8de2c600-6548-4af4-9bba-b1ca70d95754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984815349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.1984815349
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1083917422
Short name T535
Test name
Test status
Simulation time 2141551576 ps
CPU time 12.88 seconds
Started Jun 04 02:16:44 PM PDT 24
Finished Jun 04 02:16:57 PM PDT 24
Peak memory 209460 kb
Host smart-4a82bb12-41da-45ea-9a42-7122cfc17316
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083917422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1083917422
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1366901521
Short name T759
Test name
Test status
Simulation time 71322724 ps
CPU time 1.62 seconds
Started Jun 04 02:16:40 PM PDT 24
Finished Jun 04 02:16:42 PM PDT 24
Peak memory 217992 kb
Host smart-36f24ec3-1d97-431f-9cce-ab68a2a94db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366901521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1366901521
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.2026775357
Short name T708
Test name
Test status
Simulation time 331951212 ps
CPU time 8.59 seconds
Started Jun 04 02:16:47 PM PDT 24
Finished Jun 04 02:16:56 PM PDT 24
Peak memory 225996 kb
Host smart-043cda55-b170-4d80-a4f4-ba7cf96ce6ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026775357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.2026775357
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.1857630855
Short name T665
Test name
Test status
Simulation time 1166452350 ps
CPU time 12.82 seconds
Started Jun 04 02:16:46 PM PDT 24
Finished Jun 04 02:17:00 PM PDT 24
Peak memory 217896 kb
Host smart-3c5deccc-b599-45a5-8e77-bc6182af0d52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857630855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
1857630855
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.1778760167
Short name T781
Test name
Test status
Simulation time 36026642 ps
CPU time 2.15 seconds
Started Jun 04 02:16:39 PM PDT 24
Finished Jun 04 02:16:42 PM PDT 24
Peak memory 213784 kb
Host smart-3f2bea13-d7f6-4373-b431-b41fd24aea87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778760167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.1778760167
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3617320095
Short name T756
Test name
Test status
Simulation time 460590345 ps
CPU time 29.6 seconds
Started Jun 04 02:16:37 PM PDT 24
Finished Jun 04 02:17:08 PM PDT 24
Peak memory 250992 kb
Host smart-2765cc68-3557-45ef-9fb6-c5736966d67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617320095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3617320095
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.1505554753
Short name T78
Test name
Test status
Simulation time 79997547 ps
CPU time 10.67 seconds
Started Jun 04 02:16:37 PM PDT 24
Finished Jun 04 02:16:49 PM PDT 24
Peak memory 250672 kb
Host smart-7601ed0f-edbe-44cd-a8e2-5f4521884ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505554753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.1505554753
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1446068296
Short name T376
Test name
Test status
Simulation time 26125898808 ps
CPU time 103.28 seconds
Started Jun 04 02:16:49 PM PDT 24
Finished Jun 04 02:18:33 PM PDT 24
Peak memory 283696 kb
Host smart-6a6d9855-b8a0-4015-a53e-b31e8d386ca1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446068296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1446068296
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3674553734
Short name T371
Test name
Test status
Simulation time 17612879 ps
CPU time 0.82 seconds
Started Jun 04 02:16:41 PM PDT 24
Finished Jun 04 02:16:42 PM PDT 24
Peak memory 211404 kb
Host smart-2e3a2d0b-59d4-4c0f-a151-c573b8dda124
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674553734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.3674553734
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.4079392695
Short name T601
Test name
Test status
Simulation time 12356480 ps
CPU time 0.88 seconds
Started Jun 04 02:16:46 PM PDT 24
Finished Jun 04 02:16:48 PM PDT 24
Peak memory 208452 kb
Host smart-abd147d2-9414-480b-9ad5-1461518a1430
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079392695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.4079392695
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.273938274
Short name T723
Test name
Test status
Simulation time 528095570 ps
CPU time 13.74 seconds
Started Jun 04 02:16:45 PM PDT 24
Finished Jun 04 02:16:59 PM PDT 24
Peak memory 217936 kb
Host smart-783c5fbd-31e9-4280-816b-f0d5b1ce8a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273938274 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.273938274
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3188043507
Short name T488
Test name
Test status
Simulation time 429209828 ps
CPU time 11.53 seconds
Started Jun 04 02:16:47 PM PDT 24
Finished Jun 04 02:17:00 PM PDT 24
Peak memory 209520 kb
Host smart-72a61e37-2e95-4bb4-b341-24d9440ce138
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188043507 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3188043507
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.467482439
Short name T59
Test name
Test status
Simulation time 425591123 ps
CPU time 3.22 seconds
Started Jun 04 02:16:46 PM PDT 24
Finished Jun 04 02:16:49 PM PDT 24
Peak memory 217928 kb
Host smart-ac0a7bb8-df65-4f36-b003-e8d085a0c972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467482439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.467482439
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.3812971279
Short name T669
Test name
Test status
Simulation time 6758459446 ps
CPU time 11.68 seconds
Started Jun 04 02:16:47 PM PDT 24
Finished Jun 04 02:17:00 PM PDT 24
Peak memory 220128 kb
Host smart-c238d01a-99de-4e3a-a92b-3b0c56b4c47f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812971279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.3812971279
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2580685009
Short name T473
Test name
Test status
Simulation time 662949128 ps
CPU time 14.01 seconds
Started Jun 04 02:16:50 PM PDT 24
Finished Jun 04 02:17:05 PM PDT 24
Peak memory 225976 kb
Host smart-0ee4d853-ef53-44fe-9f78-a0115d9ff6ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580685009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2580685009
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1758301818
Short name T664
Test name
Test status
Simulation time 958646897 ps
CPU time 7.62 seconds
Started Jun 04 02:16:49 PM PDT 24
Finished Jun 04 02:16:57 PM PDT 24
Peak memory 217952 kb
Host smart-f0c276d6-1084-4a56-b0e3-250c113e526f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758301818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1758301818
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.1767298312
Short name T279
Test name
Test status
Simulation time 307361948 ps
CPU time 11.66 seconds
Started Jun 04 02:16:51 PM PDT 24
Finished Jun 04 02:17:03 PM PDT 24
Peak memory 225432 kb
Host smart-34ecaad3-1d8c-4219-af61-e9ccc5c53d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767298312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.1767298312
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.951119997
Short name T361
Test name
Test status
Simulation time 175864502 ps
CPU time 2.43 seconds
Started Jun 04 02:16:49 PM PDT 24
Finished Jun 04 02:16:52 PM PDT 24
Peak memory 217700 kb
Host smart-4b5721c3-aea7-4489-b9c6-8f297aec3136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951119997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.951119997
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.3813092158
Short name T428
Test name
Test status
Simulation time 1596161414 ps
CPU time 20.86 seconds
Started Jun 04 02:16:49 PM PDT 24
Finished Jun 04 02:17:10 PM PDT 24
Peak memory 250876 kb
Host smart-62871d9b-b282-4f49-9d89-04ed85b9ca86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813092158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.3813092158
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.172109846
Short name T109
Test name
Test status
Simulation time 245111690 ps
CPU time 3.23 seconds
Started Jun 04 02:16:47 PM PDT 24
Finished Jun 04 02:16:50 PM PDT 24
Peak memory 222672 kb
Host smart-4891ccb2-8b28-4e87-81b1-13f861e93cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172109846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.172109846
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.4203595822
Short name T297
Test name
Test status
Simulation time 64809472476 ps
CPU time 76 seconds
Started Jun 04 02:16:46 PM PDT 24
Finished Jun 04 02:18:03 PM PDT 24
Peak memory 267352 kb
Host smart-53d6f984-62a2-47e6-946b-c5dadd59a574
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203595822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.4203595822
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1053658610
Short name T386
Test name
Test status
Simulation time 18338275 ps
CPU time 0.91 seconds
Started Jun 04 02:16:50 PM PDT 24
Finished Jun 04 02:16:52 PM PDT 24
Peak memory 211508 kb
Host smart-67594e17-3796-49b1-8421-cb2500502848
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053658610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1053658610
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.4048924179
Short name T391
Test name
Test status
Simulation time 22364188 ps
CPU time 1.14 seconds
Started Jun 04 02:16:55 PM PDT 24
Finished Jun 04 02:16:56 PM PDT 24
Peak memory 208744 kb
Host smart-2d2bafee-1213-432a-b184-5b184542a56e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048924179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.4048924179
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.3997663135
Short name T684
Test name
Test status
Simulation time 1789312953 ps
CPU time 11.23 seconds
Started Jun 04 02:16:52 PM PDT 24
Finished Jun 04 02:17:04 PM PDT 24
Peak memory 217952 kb
Host smart-e86b3517-cd35-48f5-bd8b-0b052bd90938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997663135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.3997663135
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.2453981234
Short name T320
Test name
Test status
Simulation time 57843642 ps
CPU time 2.26 seconds
Started Jun 04 02:16:52 PM PDT 24
Finished Jun 04 02:16:56 PM PDT 24
Peak memory 209500 kb
Host smart-6c14c222-9177-461d-940a-7add12bd3304
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453981234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.2453981234
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.1259845931
Short name T626
Test name
Test status
Simulation time 63544177 ps
CPU time 2.62 seconds
Started Jun 04 02:16:53 PM PDT 24
Finished Jun 04 02:16:56 PM PDT 24
Peak memory 217964 kb
Host smart-3d1fe2d8-3f8b-42d8-90eb-65ae1f6f98ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259845931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.1259845931
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.689966544
Short name T775
Test name
Test status
Simulation time 1073782697 ps
CPU time 12.05 seconds
Started Jun 04 02:16:54 PM PDT 24
Finished Jun 04 02:17:06 PM PDT 24
Peak memory 218412 kb
Host smart-72a384aa-e2eb-48a9-b29d-24a8f1caf178
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689966544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.689966544
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.2473654262
Short name T550
Test name
Test status
Simulation time 331983962 ps
CPU time 12.25 seconds
Started Jun 04 02:16:54 PM PDT 24
Finished Jun 04 02:17:07 PM PDT 24
Peak memory 217928 kb
Host smart-3fac6c6e-b6dc-4f90-9399-834a9e13c64c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473654262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.2473654262
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.1209509691
Short name T511
Test name
Test status
Simulation time 485381583 ps
CPU time 7.73 seconds
Started Jun 04 02:16:52 PM PDT 24
Finished Jun 04 02:17:01 PM PDT 24
Peak memory 217904 kb
Host smart-a0dbbef2-8297-4a8a-b8a4-5399d4d71acf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209509691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
1209509691
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1634319346
Short name T312
Test name
Test status
Simulation time 618493621 ps
CPU time 12.45 seconds
Started Jun 04 02:16:53 PM PDT 24
Finished Jun 04 02:17:06 PM PDT 24
Peak memory 225596 kb
Host smart-fe5a6a45-e988-4a82-bfd7-d38b68b5c191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634319346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1634319346
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1935209010
Short name T421
Test name
Test status
Simulation time 32935875 ps
CPU time 1.82 seconds
Started Jun 04 02:16:46 PM PDT 24
Finished Jun 04 02:16:48 PM PDT 24
Peak memory 213616 kb
Host smart-b3c7e3c0-33c9-4ceb-8c87-c66f18a1c236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935209010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1935209010
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.454403502
Short name T477
Test name
Test status
Simulation time 922138307 ps
CPU time 26.6 seconds
Started Jun 04 02:16:48 PM PDT 24
Finished Jun 04 02:17:15 PM PDT 24
Peak memory 250920 kb
Host smart-6493307d-4455-4c70-a926-18f42404a6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454403502 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.454403502
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.3965220200
Short name T326
Test name
Test status
Simulation time 65241903 ps
CPU time 6.07 seconds
Started Jun 04 02:16:51 PM PDT 24
Finished Jun 04 02:16:57 PM PDT 24
Peak memory 242744 kb
Host smart-30e58756-6824-4ca9-9ee4-3b6a53cc527d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965220200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.3965220200
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.203043909
Short name T69
Test name
Test status
Simulation time 7201324766 ps
CPU time 61.66 seconds
Started Jun 04 02:16:52 PM PDT 24
Finished Jun 04 02:17:54 PM PDT 24
Peak memory 229940 kb
Host smart-1c5b89dd-9f4d-4ff5-9dcc-7654106b5c2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203043909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.203043909
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.4117943527
Short name T420
Test name
Test status
Simulation time 33312017 ps
CPU time 0.99 seconds
Started Jun 04 02:16:46 PM PDT 24
Finished Jun 04 02:16:47 PM PDT 24
Peak memory 212680 kb
Host smart-52e63a97-6624-45a1-b69e-4303045a188d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117943527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.4117943527
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1064938634
Short name T592
Test name
Test status
Simulation time 18919214 ps
CPU time 0.98 seconds
Started Jun 04 02:17:03 PM PDT 24
Finished Jun 04 02:17:05 PM PDT 24
Peak memory 209528 kb
Host smart-fb8325af-979a-4d2b-86f8-0bf713600437
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064938634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1064938634
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.1649236846
Short name T652
Test name
Test status
Simulation time 1731025403 ps
CPU time 11.75 seconds
Started Jun 04 02:17:06 PM PDT 24
Finished Jun 04 02:17:19 PM PDT 24
Peak memory 218044 kb
Host smart-4fdbf819-39fd-4ccc-9c38-5df932995e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649236846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.1649236846
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3217225768
Short name T195
Test name
Test status
Simulation time 826533134 ps
CPU time 6.64 seconds
Started Jun 04 02:17:05 PM PDT 24
Finished Jun 04 02:17:13 PM PDT 24
Peak memory 217268 kb
Host smart-77241956-e721-47df-ad49-42652e1aaaa5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217225768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3217225768
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2986591910
Short name T229
Test name
Test status
Simulation time 94310265 ps
CPU time 4.01 seconds
Started Jun 04 02:17:05 PM PDT 24
Finished Jun 04 02:17:10 PM PDT 24
Peak memory 217972 kb
Host smart-674f1e43-fea7-4cdf-8bcb-b2b4060a264f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986591910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2986591910
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3259372102
Short name T42
Test name
Test status
Simulation time 459215822 ps
CPU time 12.86 seconds
Started Jun 04 02:17:04 PM PDT 24
Finished Jun 04 02:17:19 PM PDT 24
Peak memory 218892 kb
Host smart-a5269f09-f353-4068-8488-e77b83efe8f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259372102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3259372102
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.1998735074
Short name T478
Test name
Test status
Simulation time 685742671 ps
CPU time 12.84 seconds
Started Jun 04 02:17:03 PM PDT 24
Finished Jun 04 02:17:18 PM PDT 24
Peak memory 226032 kb
Host smart-29bedddf-12c3-4b46-8aea-549056c206cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998735074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.1998735074
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.3011342491
Short name T430
Test name
Test status
Simulation time 2537566428 ps
CPU time 13.23 seconds
Started Jun 04 02:17:04 PM PDT 24
Finished Jun 04 02:17:19 PM PDT 24
Peak memory 217992 kb
Host smart-c21ef53a-b611-402c-83d1-33cd1db0e553
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011342491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
3011342491
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.1706052963
Short name T353
Test name
Test status
Simulation time 326143278 ps
CPU time 11.77 seconds
Started Jun 04 02:17:02 PM PDT 24
Finished Jun 04 02:17:15 PM PDT 24
Peak memory 226060 kb
Host smart-492a327a-35d3-41af-b481-0b9a7f19e58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706052963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.1706052963
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.3178578710
Short name T438
Test name
Test status
Simulation time 53399664 ps
CPU time 2.58 seconds
Started Jun 04 02:16:52 PM PDT 24
Finished Jun 04 02:16:55 PM PDT 24
Peak memory 214436 kb
Host smart-8bc4528d-7400-4c79-a07f-1330a36915c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178578710 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.3178578710
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.3782054881
Short name T9
Test name
Test status
Simulation time 338051346 ps
CPU time 34.96 seconds
Started Jun 04 02:16:53 PM PDT 24
Finished Jun 04 02:17:28 PM PDT 24
Peak memory 250944 kb
Host smart-013800da-ca4f-4744-80b5-0cdd4ea67072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782054881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.3782054881
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.1249529641
Short name T839
Test name
Test status
Simulation time 194208316 ps
CPU time 6.68 seconds
Started Jun 04 02:16:53 PM PDT 24
Finished Jun 04 02:17:01 PM PDT 24
Peak memory 248568 kb
Host smart-57b497f9-0599-442d-8d3a-869baa8c844d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249529641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.1249529641
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.3108467911
Short name T343
Test name
Test status
Simulation time 3248003717 ps
CPU time 120.22 seconds
Started Jun 04 02:17:04 PM PDT 24
Finished Jun 04 02:19:06 PM PDT 24
Peak memory 267588 kb
Host smart-f3a06ab9-a893-402e-ae43-024aa82fd362
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108467911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.3108467911
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.3654063266
Short name T149
Test name
Test status
Simulation time 22108698335 ps
CPU time 678.8 seconds
Started Jun 04 02:17:07 PM PDT 24
Finished Jun 04 02:28:27 PM PDT 24
Peak memory 278172 kb
Host smart-aa58519b-1f0c-45a2-8a14-d480daed2633
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3654063266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.3654063266
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3149758171
Short name T619
Test name
Test status
Simulation time 22841158 ps
CPU time 0.96 seconds
Started Jun 04 02:16:51 PM PDT 24
Finished Jun 04 02:16:53 PM PDT 24
Peak memory 211500 kb
Host smart-edcd9da7-80c5-4ebb-9641-1d9103832a83
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149758171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3149758171
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.2739189578
Short name T88
Test name
Test status
Simulation time 46490999 ps
CPU time 1.03 seconds
Started Jun 04 02:17:16 PM PDT 24
Finished Jun 04 02:17:17 PM PDT 24
Peak memory 208660 kb
Host smart-9c51e2ba-7fcd-4c6d-bb18-2fa97f64391a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739189578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.2739189578
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2847378919
Short name T301
Test name
Test status
Simulation time 302299656 ps
CPU time 9.31 seconds
Started Jun 04 02:17:04 PM PDT 24
Finished Jun 04 02:17:15 PM PDT 24
Peak memory 217928 kb
Host smart-eeaa1bde-4928-4cf9-9508-30582df5c31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847378919 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2847378919
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.289734397
Short name T329
Test name
Test status
Simulation time 535714253 ps
CPU time 5.42 seconds
Started Jun 04 02:17:05 PM PDT 24
Finished Jun 04 02:17:12 PM PDT 24
Peak memory 209516 kb
Host smart-ff575a58-24c5-4014-83f3-9d2845c6c6c7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289734397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.289734397
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.3425759351
Short name T733
Test name
Test status
Simulation time 191738566 ps
CPU time 2.13 seconds
Started Jun 04 02:17:02 PM PDT 24
Finished Jun 04 02:17:05 PM PDT 24
Peak memory 217976 kb
Host smart-53200f4c-5eb2-4376-856b-9f00e7ec277c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425759351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.3425759351
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.2539624827
Short name T506
Test name
Test status
Simulation time 652800351 ps
CPU time 24.62 seconds
Started Jun 04 02:17:10 PM PDT 24
Finished Jun 04 02:17:36 PM PDT 24
Peak memory 218880 kb
Host smart-d4ce906d-f5c3-4ff6-889b-aa1eccefbd0b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539624827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.2539624827
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1888411964
Short name T651
Test name
Test status
Simulation time 1471998200 ps
CPU time 21.76 seconds
Started Jun 04 02:17:11 PM PDT 24
Finished Jun 04 02:17:34 PM PDT 24
Peak memory 226036 kb
Host smart-759f8788-c6d7-42b1-9e87-079ec8c481bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888411964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1888411964
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.2330331162
Short name T562
Test name
Test status
Simulation time 347862270 ps
CPU time 7.64 seconds
Started Jun 04 02:17:11 PM PDT 24
Finished Jun 04 02:17:20 PM PDT 24
Peak memory 217920 kb
Host smart-8ab98637-3476-4592-956c-f7e938c7e178
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330331162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
2330331162
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2275199669
Short name T408
Test name
Test status
Simulation time 398163255 ps
CPU time 14.48 seconds
Started Jun 04 02:17:04 PM PDT 24
Finished Jun 04 02:17:20 PM PDT 24
Peak memory 226060 kb
Host smart-9ab1530f-9f3a-40d1-938a-c37b9b220725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275199669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2275199669
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.3484503516
Short name T71
Test name
Test status
Simulation time 202962879 ps
CPU time 6.18 seconds
Started Jun 04 02:17:03 PM PDT 24
Finished Jun 04 02:17:11 PM PDT 24
Peak memory 217788 kb
Host smart-1ad61fc9-0471-42bb-ac85-9136ee3ba3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484503516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.3484503516
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.2652307759
Short name T457
Test name
Test status
Simulation time 751176052 ps
CPU time 23 seconds
Started Jun 04 02:17:04 PM PDT 24
Finished Jun 04 02:17:29 PM PDT 24
Peak memory 250920 kb
Host smart-c5d4fdf5-bc29-44fb-9b15-e728fe9db0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652307759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.2652307759
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2663292086
Short name T599
Test name
Test status
Simulation time 683086863 ps
CPU time 3.74 seconds
Started Jun 04 02:17:03 PM PDT 24
Finished Jun 04 02:17:09 PM PDT 24
Peak memory 222752 kb
Host smart-7f9e4212-0602-4c41-8a44-e5b6150b8c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663292086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2663292086
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.2655244876
Short name T597
Test name
Test status
Simulation time 10279305649 ps
CPU time 126.31 seconds
Started Jun 04 02:17:17 PM PDT 24
Finished Jun 04 02:19:24 PM PDT 24
Peak memory 275464 kb
Host smart-86812d1f-798e-4f9c-a936-3bb80d827ce6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655244876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.2655244876
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.2473793339
Short name T171
Test name
Test status
Simulation time 62412670432 ps
CPU time 495.3 seconds
Started Jun 04 02:17:10 PM PDT 24
Finished Jun 04 02:25:26 PM PDT 24
Peak memory 283860 kb
Host smart-609d7444-850a-4f9b-be7b-167a76df2558
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2473793339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.2473793339
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.553496366
Short name T615
Test name
Test status
Simulation time 102305203 ps
CPU time 1.55 seconds
Started Jun 04 02:17:04 PM PDT 24
Finished Jun 04 02:17:07 PM PDT 24
Peak memory 213144 kb
Host smart-5289694b-3b74-44ef-a217-7fe3c17aafc5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553496366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.553496366
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.197983830
Short name T769
Test name
Test status
Simulation time 37690407 ps
CPU time 1.03 seconds
Started Jun 04 02:13:40 PM PDT 24
Finished Jun 04 02:13:42 PM PDT 24
Peak memory 209548 kb
Host smart-a4515836-870c-452c-924d-e165b3c5b861
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197983830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.197983830
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1207336896
Short name T220
Test name
Test status
Simulation time 34277239 ps
CPU time 0.81 seconds
Started Jun 04 02:13:28 PM PDT 24
Finished Jun 04 02:13:30 PM PDT 24
Peak memory 208716 kb
Host smart-35f82a4e-8cd1-487a-a2bd-4c110ac83fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207336896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1207336896
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.122480719
Short name T309
Test name
Test status
Simulation time 367538499 ps
CPU time 14.44 seconds
Started Jun 04 02:13:29 PM PDT 24
Finished Jun 04 02:13:44 PM PDT 24
Peak memory 217988 kb
Host smart-d4e39008-6d1b-43da-9fc6-26278061ea99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122480719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.122480719
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.2589831771
Short name T497
Test name
Test status
Simulation time 641427683 ps
CPU time 5.94 seconds
Started Jun 04 02:13:33 PM PDT 24
Finished Jun 04 02:13:40 PM PDT 24
Peak memory 209500 kb
Host smart-56b14355-5eb7-4d55-bc7c-f9da2507f9b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589831771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.2589831771
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.169210196
Short name T193
Test name
Test status
Simulation time 46604078397 ps
CPU time 49.86 seconds
Started Jun 04 02:13:32 PM PDT 24
Finished Jun 04 02:14:23 PM PDT 24
Peak memory 219408 kb
Host smart-d4702756-3095-4d31-ae13-da18919c08ad
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169210196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.169210196
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1884424762
Short name T479
Test name
Test status
Simulation time 1110704406 ps
CPU time 1.92 seconds
Started Jun 04 02:13:35 PM PDT 24
Finished Jun 04 02:13:37 PM PDT 24
Peak memory 217620 kb
Host smart-dde86422-0906-46dd-95b8-e27ac7b7c3b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884424762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1
884424762
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.2666847039
Short name T736
Test name
Test status
Simulation time 707103614 ps
CPU time 10.33 seconds
Started Jun 04 02:13:33 PM PDT 24
Finished Jun 04 02:13:44 PM PDT 24
Peak memory 217888 kb
Host smart-31b17f9b-bd33-4ebd-8d1d-a05855666ddd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666847039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.2666847039
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.4010812816
Short name T837
Test name
Test status
Simulation time 1196743580 ps
CPU time 26.03 seconds
Started Jun 04 02:13:33 PM PDT 24
Finished Jun 04 02:13:59 PM PDT 24
Peak memory 217628 kb
Host smart-1a5a8432-d461-48cc-b267-c102de15d42f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010812816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.4010812816
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.1608260663
Short name T633
Test name
Test status
Simulation time 689433153 ps
CPU time 9.68 seconds
Started Jun 04 02:13:27 PM PDT 24
Finished Jun 04 02:13:38 PM PDT 24
Peak memory 217636 kb
Host smart-408815c1-7d56-4cfc-818f-c0eef953d9c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608260663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
1608260663
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.4120363531
Short name T740
Test name
Test status
Simulation time 10911526070 ps
CPU time 88.19 seconds
Started Jun 04 02:13:33 PM PDT 24
Finished Jun 04 02:15:02 PM PDT 24
Peak memory 283660 kb
Host smart-c0323be5-288b-4588-90b3-6aa11c93cd58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120363531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jta
g_state_failure.4120363531
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.1577575991
Short name T454
Test name
Test status
Simulation time 529885143 ps
CPU time 20.4 seconds
Started Jun 04 02:13:31 PM PDT 24
Finished Jun 04 02:13:52 PM PDT 24
Peak memory 250832 kb
Host smart-4d450613-2d5e-4935-8ddd-34fe76019df9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577575991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.1577575991
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.459936724
Short name T568
Test name
Test status
Simulation time 412423508 ps
CPU time 3.39 seconds
Started Jun 04 02:13:32 PM PDT 24
Finished Jun 04 02:13:36 PM PDT 24
Peak memory 217988 kb
Host smart-73842366-0c67-4990-a550-206f4c1448e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459936724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.459936724
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1742991758
Short name T469
Test name
Test status
Simulation time 435333066 ps
CPU time 7.28 seconds
Started Jun 04 02:13:32 PM PDT 24
Finished Jun 04 02:13:40 PM PDT 24
Peak memory 213772 kb
Host smart-73925a36-88a1-4ec9-9901-f5d7ce4a4cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742991758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1742991758
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.2725225891
Short name T86
Test name
Test status
Simulation time 1099305709 ps
CPU time 26.92 seconds
Started Jun 04 02:13:32 PM PDT 24
Finished Jun 04 02:14:00 PM PDT 24
Peak memory 281904 kb
Host smart-8e25c1e4-d3b2-4825-9d25-a1e910806529
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725225891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.2725225891
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.2299652173
Short name T95
Test name
Test status
Simulation time 3206128353 ps
CPU time 15.81 seconds
Started Jun 04 02:13:34 PM PDT 24
Finished Jun 04 02:13:50 PM PDT 24
Peak memory 226104 kb
Host smart-8111604c-b3a1-40e9-a90b-ef62af73fdaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299652173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.2299652173
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1532378415
Short name T183
Test name
Test status
Simulation time 483147845 ps
CPU time 11.95 seconds
Started Jun 04 02:13:35 PM PDT 24
Finished Jun 04 02:13:47 PM PDT 24
Peak memory 226032 kb
Host smart-f10ee743-d967-4029-a706-a91eef618dc2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532378415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1532378415
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3870279954
Short name T720
Test name
Test status
Simulation time 365254804 ps
CPU time 9.46 seconds
Started Jun 04 02:13:35 PM PDT 24
Finished Jun 04 02:13:45 PM PDT 24
Peak memory 217844 kb
Host smart-bf5ed840-3487-4c02-b07c-ad619e663a66
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870279954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3
870279954
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3153034373
Short name T255
Test name
Test status
Simulation time 1122104677 ps
CPU time 9.04 seconds
Started Jun 04 02:13:30 PM PDT 24
Finished Jun 04 02:13:40 PM PDT 24
Peak memory 218024 kb
Host smart-8000c509-352b-4f6d-90dc-2c31ad345d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153034373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3153034373
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.254128178
Short name T84
Test name
Test status
Simulation time 780567669 ps
CPU time 4 seconds
Started Jun 04 02:13:29 PM PDT 24
Finished Jun 04 02:13:33 PM PDT 24
Peak memory 217740 kb
Host smart-ee73883b-80e9-47f0-ae2b-82442b36db7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254128178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.254128178
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3383101738
Short name T732
Test name
Test status
Simulation time 341959668 ps
CPU time 36.47 seconds
Started Jun 04 02:13:36 PM PDT 24
Finished Jun 04 02:14:13 PM PDT 24
Peak memory 251016 kb
Host smart-f3964118-d273-4786-b36c-a3a520721e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383101738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3383101738
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.3787737707
Short name T173
Test name
Test status
Simulation time 917563453 ps
CPU time 6.37 seconds
Started Jun 04 02:13:30 PM PDT 24
Finished Jun 04 02:13:37 PM PDT 24
Peak memory 250720 kb
Host smart-395192cf-6ded-44b2-83f4-ec3ae571f344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787737707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.3787737707
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.1597707041
Short name T196
Test name
Test status
Simulation time 44879778863 ps
CPU time 93.69 seconds
Started Jun 04 02:13:30 PM PDT 24
Finished Jun 04 02:15:04 PM PDT 24
Peak memory 225192 kb
Host smart-0d2f2354-41a5-4eeb-940a-82ed75860e77
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597707041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.1597707041
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3726806830
Short name T150
Test name
Test status
Simulation time 146088346743 ps
CPU time 580.38 seconds
Started Jun 04 02:13:33 PM PDT 24
Finished Jun 04 02:23:15 PM PDT 24
Peak memory 283872 kb
Host smart-30084026-e9b4-4713-b0b0-c41bc795bab8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3726806830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.3726806830
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2693960447
Short name T217
Test name
Test status
Simulation time 54468437 ps
CPU time 0.8 seconds
Started Jun 04 02:13:30 PM PDT 24
Finished Jun 04 02:13:31 PM PDT 24
Peak memory 211528 kb
Host smart-13ec5a3b-bb8f-4328-9546-0efd0ad9ba57
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693960447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2693960447
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.1705123534
Short name T773
Test name
Test status
Simulation time 311179608 ps
CPU time 12.02 seconds
Started Jun 04 02:17:13 PM PDT 24
Finished Jun 04 02:17:26 PM PDT 24
Peak memory 217984 kb
Host smart-d2c0848f-fc4c-4c82-87ab-a2ccfdf95445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705123534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.1705123534
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.2189711192
Short name T595
Test name
Test status
Simulation time 207594136 ps
CPU time 2.02 seconds
Started Jun 04 02:17:13 PM PDT 24
Finished Jun 04 02:17:16 PM PDT 24
Peak memory 209504 kb
Host smart-d876cda3-d88e-4188-87d4-83b1b7bcf256
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189711192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.2189711192
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.3717195588
Short name T155
Test name
Test status
Simulation time 54071271 ps
CPU time 3.14 seconds
Started Jun 04 02:17:10 PM PDT 24
Finished Jun 04 02:17:15 PM PDT 24
Peak memory 217996 kb
Host smart-26b2d07c-01cd-4acc-9429-575980451719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717195588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.3717195588
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.1777780217
Short name T264
Test name
Test status
Simulation time 750307048 ps
CPU time 11.3 seconds
Started Jun 04 02:17:10 PM PDT 24
Finished Jun 04 02:17:23 PM PDT 24
Peak memory 218948 kb
Host smart-0102a83a-2eff-44df-9873-2891c773eb44
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777780217 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.1777780217
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.4141029421
Short name T552
Test name
Test status
Simulation time 920800020 ps
CPU time 18.73 seconds
Started Jun 04 02:17:12 PM PDT 24
Finished Jun 04 02:17:32 PM PDT 24
Peak memory 226020 kb
Host smart-1263b9ed-6d14-4ac4-8f61-24289732698d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141029421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.4141029421
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.395550336
Short name T613
Test name
Test status
Simulation time 697341324 ps
CPU time 8.19 seconds
Started Jun 04 02:17:09 PM PDT 24
Finished Jun 04 02:17:18 PM PDT 24
Peak memory 217920 kb
Host smart-76a600cb-39be-4ba1-9f0c-9f609cc11f2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395550336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.395550336
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.427929008
Short name T604
Test name
Test status
Simulation time 420248988 ps
CPU time 11.71 seconds
Started Jun 04 02:17:13 PM PDT 24
Finished Jun 04 02:17:26 PM PDT 24
Peak memory 226100 kb
Host smart-8c062843-f100-4dcd-aa6f-b07dbaf88ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427929008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.427929008
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2380901594
Short name T313
Test name
Test status
Simulation time 1050744109 ps
CPU time 4.04 seconds
Started Jun 04 02:17:13 PM PDT 24
Finished Jun 04 02:17:17 PM PDT 24
Peak memory 217676 kb
Host smart-10bfabc2-05b7-4dcd-ba95-125dbdbfd5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380901594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2380901594
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.662141431
Short name T797
Test name
Test status
Simulation time 423381337 ps
CPU time 26.39 seconds
Started Jun 04 02:17:10 PM PDT 24
Finished Jun 04 02:17:38 PM PDT 24
Peak memory 246044 kb
Host smart-797d08e4-8d3b-4c23-b0ac-c790bee42e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662141431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.662141431
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.515578724
Short name T291
Test name
Test status
Simulation time 285568675 ps
CPU time 8.21 seconds
Started Jun 04 02:17:17 PM PDT 24
Finished Jun 04 02:17:26 PM PDT 24
Peak memory 250844 kb
Host smart-c5873df0-73ad-4ab7-8c52-d81926d52f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515578724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.515578724
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.4263916340
Short name T847
Test name
Test status
Simulation time 2199922397 ps
CPU time 19.95 seconds
Started Jun 04 02:17:15 PM PDT 24
Finished Jun 04 02:17:36 PM PDT 24
Peak memory 226056 kb
Host smart-699aa4a0-4d42-46cb-a24d-8ad8104175c9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263916340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.4263916340
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.1461691843
Short name T433
Test name
Test status
Simulation time 72292150 ps
CPU time 0.85 seconds
Started Jun 04 02:17:13 PM PDT 24
Finished Jun 04 02:17:15 PM PDT 24
Peak memory 212508 kb
Host smart-079aafc3-9aee-42f0-8e55-364030108bb4
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461691843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.1461691843
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.3684087003
Short name T569
Test name
Test status
Simulation time 17259964 ps
CPU time 1.11 seconds
Started Jun 04 02:17:21 PM PDT 24
Finished Jun 04 02:17:22 PM PDT 24
Peak memory 208636 kb
Host smart-6842fd2e-60e8-4775-a070-a1bb0e6029e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684087003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.3684087003
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.3928594248
Short name T447
Test name
Test status
Simulation time 398388885 ps
CPU time 14.26 seconds
Started Jun 04 02:17:12 PM PDT 24
Finished Jun 04 02:17:27 PM PDT 24
Peak memory 217980 kb
Host smart-97eb539c-0e13-4948-a0fe-a5f3120d4089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928594248 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.3928594248
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2705121975
Short name T354
Test name
Test status
Simulation time 623357169 ps
CPU time 4.64 seconds
Started Jun 04 02:17:10 PM PDT 24
Finished Jun 04 02:17:15 PM PDT 24
Peak memory 209468 kb
Host smart-b35d0816-ef42-4617-b75b-0c050eda10b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705121975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2705121975
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3448510104
Short name T753
Test name
Test status
Simulation time 44960318 ps
CPU time 1.94 seconds
Started Jun 04 02:17:16 PM PDT 24
Finished Jun 04 02:17:18 PM PDT 24
Peak memory 217932 kb
Host smart-604c4ba7-5182-46ad-9b82-2cf9fa62e8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448510104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3448510104
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.841356448
Short name T621
Test name
Test status
Simulation time 1274116235 ps
CPU time 14.96 seconds
Started Jun 04 02:17:11 PM PDT 24
Finished Jun 04 02:17:27 PM PDT 24
Peak memory 218956 kb
Host smart-96708dac-d79b-442e-9405-745665533f99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841356448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.841356448
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.4015028476
Short name T228
Test name
Test status
Simulation time 1202732110 ps
CPU time 9.84 seconds
Started Jun 04 02:17:13 PM PDT 24
Finished Jun 04 02:17:23 PM PDT 24
Peak memory 226016 kb
Host smart-ba9070d4-e0e3-4523-a75f-b74129cf877f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015028476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.4015028476
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2081462803
Short name T224
Test name
Test status
Simulation time 864859231 ps
CPU time 11.16 seconds
Started Jun 04 02:17:12 PM PDT 24
Finished Jun 04 02:17:24 PM PDT 24
Peak memory 224844 kb
Host smart-31bd47dd-44d0-493b-8853-40091b356c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081462803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2081462803
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.2600137375
Short name T531
Test name
Test status
Simulation time 55831263 ps
CPU time 0.98 seconds
Started Jun 04 02:17:10 PM PDT 24
Finished Jun 04 02:17:12 PM PDT 24
Peak memory 211972 kb
Host smart-d79e3922-f02f-4d7e-98c1-fbff1d6dad14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600137375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.2600137375
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2104694123
Short name T412
Test name
Test status
Simulation time 392905351 ps
CPU time 21.7 seconds
Started Jun 04 02:17:09 PM PDT 24
Finished Jun 04 02:17:32 PM PDT 24
Peak memory 250920 kb
Host smart-8e7efecb-2a10-4be2-92b3-43279092503f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104694123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2104694123
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.1070211442
Short name T194
Test name
Test status
Simulation time 1154700641 ps
CPU time 10.48 seconds
Started Jun 04 02:17:13 PM PDT 24
Finished Jun 04 02:17:24 PM PDT 24
Peak memory 250888 kb
Host smart-c340648c-3ffb-4809-ac3d-a8af6be038e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070211442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.1070211442
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2143141250
Short name T57
Test name
Test status
Simulation time 31587420966 ps
CPU time 146.83 seconds
Started Jun 04 02:17:14 PM PDT 24
Finished Jun 04 02:19:41 PM PDT 24
Peak memory 266300 kb
Host smart-3e262b6d-0109-433e-8047-df8a51102a1f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143141250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2143141250
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.498265314
Short name T617
Test name
Test status
Simulation time 15337434 ps
CPU time 0.92 seconds
Started Jun 04 02:17:11 PM PDT 24
Finished Jun 04 02:17:13 PM PDT 24
Peak memory 212576 kb
Host smart-f1bf320b-1a0a-4d25-8ae8-e5af4a75cafa
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498265314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ct
rl_volatile_unlock_smoke.498265314
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.308633111
Short name T70
Test name
Test status
Simulation time 50763227 ps
CPU time 1.05 seconds
Started Jun 04 02:17:19 PM PDT 24
Finished Jun 04 02:17:20 PM PDT 24
Peak memory 209556 kb
Host smart-ffd4507a-d5b0-4365-8824-cf7d40c61d12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308633111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.308633111
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1271919609
Short name T289
Test name
Test status
Simulation time 646543938 ps
CPU time 10.51 seconds
Started Jun 04 02:17:18 PM PDT 24
Finished Jun 04 02:17:29 PM PDT 24
Peak memory 218076 kb
Host smart-0b075847-0099-4205-b968-9c67eaadbff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271919609 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1271919609
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2409242491
Short name T32
Test name
Test status
Simulation time 169286633 ps
CPU time 2.76 seconds
Started Jun 04 02:17:22 PM PDT 24
Finished Jun 04 02:17:26 PM PDT 24
Peak memory 209460 kb
Host smart-6d937473-8672-4d54-bcf2-27fa6bd45825
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409242491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2409242491
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.2619642434
Short name T339
Test name
Test status
Simulation time 264973974 ps
CPU time 2.64 seconds
Started Jun 04 02:17:19 PM PDT 24
Finished Jun 04 02:17:22 PM PDT 24
Peak memory 217888 kb
Host smart-9a689048-260a-41f1-9853-505d64087741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619642434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.2619642434
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.277930310
Short name T107
Test name
Test status
Simulation time 506533504 ps
CPU time 10.14 seconds
Started Jun 04 02:17:19 PM PDT 24
Finished Jun 04 02:17:30 PM PDT 24
Peak memory 218944 kb
Host smart-d8e8bb76-52b2-4f05-9d90-bfc2a1008fd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277930310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.277930310
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1692077524
Short name T807
Test name
Test status
Simulation time 1303356285 ps
CPU time 10.49 seconds
Started Jun 04 02:17:21 PM PDT 24
Finished Jun 04 02:17:32 PM PDT 24
Peak memory 226028 kb
Host smart-3ef7715e-a95c-4e63-83de-2ba38d1c1663
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692077524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1692077524
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.895453447
Short name T589
Test name
Test status
Simulation time 563734426 ps
CPU time 8.85 seconds
Started Jun 04 02:17:20 PM PDT 24
Finished Jun 04 02:17:29 PM PDT 24
Peak memory 217924 kb
Host smart-106cca15-1d5c-481d-bf42-50e1470e77a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895453447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.895453447
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.3814289362
Short name T745
Test name
Test status
Simulation time 1460496987 ps
CPU time 11.57 seconds
Started Jun 04 02:17:22 PM PDT 24
Finished Jun 04 02:17:34 PM PDT 24
Peak memory 225264 kb
Host smart-75a15665-6bb4-480d-a0ff-0813f31188dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814289362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.3814289362
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.2518122424
Short name T73
Test name
Test status
Simulation time 38835374 ps
CPU time 2.52 seconds
Started Jun 04 02:17:21 PM PDT 24
Finished Jun 04 02:17:24 PM PDT 24
Peak memory 213980 kb
Host smart-a358925e-4483-4b4a-9119-e7e7bbb7b6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518122424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.2518122424
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.887140055
Short name T500
Test name
Test status
Simulation time 185646730 ps
CPU time 20.86 seconds
Started Jun 04 02:17:19 PM PDT 24
Finished Jun 04 02:17:41 PM PDT 24
Peak memory 250856 kb
Host smart-cbb29852-7ad2-47ca-9885-1a2e3c7d9d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887140055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.887140055
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.1667450055
Short name T832
Test name
Test status
Simulation time 312522089 ps
CPU time 7.57 seconds
Started Jun 04 02:17:17 PM PDT 24
Finished Jun 04 02:17:25 PM PDT 24
Peak memory 250832 kb
Host smart-fa08b06a-5a80-4c99-99ba-d8b70b7dedde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667450055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.1667450055
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.4093317467
Short name T186
Test name
Test status
Simulation time 2860655903 ps
CPU time 85.19 seconds
Started Jun 04 02:17:21 PM PDT 24
Finished Jun 04 02:18:46 PM PDT 24
Peak memory 217760 kb
Host smart-0225af82-6e24-4881-936d-ad34f111828b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093317467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.4093317467
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.543441106
Short name T148
Test name
Test status
Simulation time 52083379303 ps
CPU time 442.84 seconds
Started Jun 04 02:17:21 PM PDT 24
Finished Jun 04 02:24:44 PM PDT 24
Peak memory 260816 kb
Host smart-6a3ab1f7-49f5-4c03-9e8d-9da0be9133f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=543441106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.543441106
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2852593626
Short name T415
Test name
Test status
Simulation time 12752606 ps
CPU time 0.89 seconds
Started Jun 04 02:17:17 PM PDT 24
Finished Jun 04 02:17:18 PM PDT 24
Peak memory 211560 kb
Host smart-f8f1c508-0971-4150-b6bf-b199df53de1e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852593626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2852593626
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.107980864
Short name T718
Test name
Test status
Simulation time 22583883 ps
CPU time 1.25 seconds
Started Jun 04 02:17:25 PM PDT 24
Finished Jun 04 02:17:27 PM PDT 24
Peak memory 208712 kb
Host smart-6cab961c-0551-4404-a9cf-07c6d25b348d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107980864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.107980864
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3354467835
Short name T19
Test name
Test status
Simulation time 532405513 ps
CPU time 9.73 seconds
Started Jun 04 02:17:18 PM PDT 24
Finished Jun 04 02:17:28 PM PDT 24
Peak memory 217996 kb
Host smart-8d5b013d-d6cf-4e35-8177-0f931c5ffab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354467835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3354467835
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.1025507427
Short name T29
Test name
Test status
Simulation time 396419548 ps
CPU time 2.04 seconds
Started Jun 04 02:17:28 PM PDT 24
Finished Jun 04 02:17:30 PM PDT 24
Peak memory 209520 kb
Host smart-4317f713-c934-4a91-a2ad-0901a3a76a6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025507427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.1025507427
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2858244786
Short name T418
Test name
Test status
Simulation time 142579066 ps
CPU time 2.01 seconds
Started Jun 04 02:17:19 PM PDT 24
Finished Jun 04 02:17:21 PM PDT 24
Peak memory 218044 kb
Host smart-badf7315-9511-4e25-83b3-f3347eb3f151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858244786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2858244786
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1385130180
Short name T34
Test name
Test status
Simulation time 3129055958 ps
CPU time 10.44 seconds
Started Jun 04 02:17:28 PM PDT 24
Finished Jun 04 02:17:40 PM PDT 24
Peak memory 218216 kb
Host smart-253fbfe2-44b7-4767-baa3-ef79e3e6a740
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385130180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1385130180
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.4213416724
Short name T316
Test name
Test status
Simulation time 4060792776 ps
CPU time 12.1 seconds
Started Jun 04 02:17:32 PM PDT 24
Finished Jun 04 02:17:44 PM PDT 24
Peak memory 218008 kb
Host smart-92493971-37a1-42e3-935a-a36383e8466a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213416724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
4213416724
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.201358331
Short name T346
Test name
Test status
Simulation time 154640905 ps
CPU time 2.84 seconds
Started Jun 04 02:17:17 PM PDT 24
Finished Jun 04 02:17:21 PM PDT 24
Peak memory 214048 kb
Host smart-e173a5c5-80a6-475b-aef7-5c72c3b025fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201358331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.201358331
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.2155439200
Short name T588
Test name
Test status
Simulation time 395103941 ps
CPU time 37.23 seconds
Started Jun 04 02:17:21 PM PDT 24
Finished Jun 04 02:17:59 PM PDT 24
Peak memory 250908 kb
Host smart-1b86f5a3-26ea-4874-b3f8-2526305657b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155439200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.2155439200
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1292865842
Short name T603
Test name
Test status
Simulation time 176859886 ps
CPU time 9.85 seconds
Started Jun 04 02:17:18 PM PDT 24
Finished Jun 04 02:17:28 PM PDT 24
Peak memory 250860 kb
Host smart-dbfb7726-52f1-4635-8851-4c5c3605b37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292865842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1292865842
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.2664056275
Short name T514
Test name
Test status
Simulation time 26934414105 ps
CPU time 117.05 seconds
Started Jun 04 02:17:27 PM PDT 24
Finished Jun 04 02:19:25 PM PDT 24
Peak memory 250908 kb
Host smart-db8a99e4-b944-460e-8f15-b9109b5ec33d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664056275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.2664056275
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2326883773
Short name T245
Test name
Test status
Simulation time 14716364 ps
CPU time 0.94 seconds
Started Jun 04 02:17:20 PM PDT 24
Finished Jun 04 02:17:22 PM PDT 24
Peak memory 212664 kb
Host smart-60e62451-af2d-47d2-9b09-3c8715aafa79
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326883773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2326883773
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.101409554
Short name T541
Test name
Test status
Simulation time 48257780 ps
CPU time 0.86 seconds
Started Jun 04 02:17:26 PM PDT 24
Finished Jun 04 02:17:27 PM PDT 24
Peak memory 208492 kb
Host smart-b7a27989-60cc-4d8c-b90c-72a757ca86c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101409554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.101409554
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.509656584
Short name T512
Test name
Test status
Simulation time 264126536 ps
CPU time 11.88 seconds
Started Jun 04 02:17:27 PM PDT 24
Finished Jun 04 02:17:40 PM PDT 24
Peak memory 218004 kb
Host smart-003c2486-f9e0-4bcf-a528-494f70154311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509656584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.509656584
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.2927393716
Short name T641
Test name
Test status
Simulation time 650797174 ps
CPU time 8.2 seconds
Started Jun 04 02:17:26 PM PDT 24
Finished Jun 04 02:17:35 PM PDT 24
Peak memory 209504 kb
Host smart-b0602b2f-8a59-4bc8-b413-f7deb38ad269
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927393716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.2927393716
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1113691171
Short name T485
Test name
Test status
Simulation time 321766502 ps
CPU time 4.07 seconds
Started Jun 04 02:17:29 PM PDT 24
Finished Jun 04 02:17:34 PM PDT 24
Peak memory 218056 kb
Host smart-e9d68791-d810-47b0-a508-77d421a24a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113691171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1113691171
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.1156089841
Short name T55
Test name
Test status
Simulation time 511783055 ps
CPU time 11.97 seconds
Started Jun 04 02:17:25 PM PDT 24
Finished Jun 04 02:17:38 PM PDT 24
Peak memory 218096 kb
Host smart-66f58a89-48c7-4934-9a38-7abbbda413a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156089841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.1156089841
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2857331530
Short name T321
Test name
Test status
Simulation time 529042351 ps
CPU time 15.24 seconds
Started Jun 04 02:17:27 PM PDT 24
Finished Jun 04 02:17:43 PM PDT 24
Peak memory 226028 kb
Host smart-b219005b-9744-4754-a79e-8f4a6eae5ce9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857331530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2857331530
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.3245710804
Short name T239
Test name
Test status
Simulation time 444482230 ps
CPU time 8.8 seconds
Started Jun 04 02:17:27 PM PDT 24
Finished Jun 04 02:17:37 PM PDT 24
Peak memory 217872 kb
Host smart-e380a8ec-a507-4168-af3f-257325bf4e9e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245710804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.
3245710804
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.4266445288
Short name T449
Test name
Test status
Simulation time 242773746 ps
CPU time 1.78 seconds
Started Jun 04 02:17:32 PM PDT 24
Finished Jun 04 02:17:34 PM PDT 24
Peak memory 213564 kb
Host smart-c782d8d3-0e0b-435a-a7d7-e9e065c75d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266445288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.4266445288
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.3795415363
Short name T536
Test name
Test status
Simulation time 170834377 ps
CPU time 25.45 seconds
Started Jun 04 02:17:29 PM PDT 24
Finished Jun 04 02:17:55 PM PDT 24
Peak memory 245544 kb
Host smart-88ccb564-2eaf-404d-95ef-968f76f2238e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795415363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.3795415363
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.329057764
Short name T244
Test name
Test status
Simulation time 635730793 ps
CPU time 7.92 seconds
Started Jun 04 02:17:29 PM PDT 24
Finished Jun 04 02:17:38 PM PDT 24
Peak memory 250260 kb
Host smart-f0499b7d-670d-4ae9-8166-25fa61a3d0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329057764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.329057764
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2865777180
Short name T838
Test name
Test status
Simulation time 13714275 ps
CPU time 1.12 seconds
Started Jun 04 02:17:33 PM PDT 24
Finished Jun 04 02:17:35 PM PDT 24
Peak memory 211484 kb
Host smart-92f23c65-3db3-4789-9f4c-fe0458e8c48f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865777180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2865777180
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3479535540
Short name T317
Test name
Test status
Simulation time 16996381 ps
CPU time 1.09 seconds
Started Jun 04 02:17:33 PM PDT 24
Finished Jun 04 02:17:35 PM PDT 24
Peak memory 208736 kb
Host smart-ee5b3882-0d8b-403e-8bad-171059a0ac26
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479535540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3479535540
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.613206403
Short name T856
Test name
Test status
Simulation time 332836699 ps
CPU time 13.18 seconds
Started Jun 04 02:17:34 PM PDT 24
Finished Jun 04 02:17:49 PM PDT 24
Peak memory 217992 kb
Host smart-ac5f7000-67c8-40f5-aff4-23a57fad2742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613206403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.613206403
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.2012061554
Short name T635
Test name
Test status
Simulation time 1104570942 ps
CPU time 6.51 seconds
Started Jun 04 02:17:33 PM PDT 24
Finished Jun 04 02:17:41 PM PDT 24
Peak memory 216996 kb
Host smart-ec7da4c6-60c6-4407-9552-bf92a7db37b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012061554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.2012061554
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.2647042395
Short name T675
Test name
Test status
Simulation time 77589854 ps
CPU time 2.54 seconds
Started Jun 04 02:17:33 PM PDT 24
Finished Jun 04 02:17:37 PM PDT 24
Peak memory 218024 kb
Host smart-6212ec1f-0422-4989-892a-a402e571adc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647042395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.2647042395
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.1272244416
Short name T796
Test name
Test status
Simulation time 628131842 ps
CPU time 10.92 seconds
Started Jun 04 02:17:34 PM PDT 24
Finished Jun 04 02:17:46 PM PDT 24
Peak memory 218244 kb
Host smart-a151ea4b-ccd3-4844-b148-0f3f5737b5a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272244416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.1272244416
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.783535134
Short name T475
Test name
Test status
Simulation time 544607703 ps
CPU time 9.82 seconds
Started Jun 04 02:17:40 PM PDT 24
Finished Jun 04 02:17:51 PM PDT 24
Peak memory 225976 kb
Host smart-6b23ac0e-2472-4f81-a70c-5dad5aaf0ded
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783535134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_di
gest.783535134
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.4210005496
Short name T616
Test name
Test status
Simulation time 503026109 ps
CPU time 9.69 seconds
Started Jun 04 02:17:33 PM PDT 24
Finished Jun 04 02:17:44 PM PDT 24
Peak memory 217904 kb
Host smart-54f92566-36fd-406c-83d9-317e4fceb746
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210005496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
4210005496
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1674384174
Short name T370
Test name
Test status
Simulation time 1642881218 ps
CPU time 13.56 seconds
Started Jun 04 02:17:34 PM PDT 24
Finished Jun 04 02:17:49 PM PDT 24
Peak memory 225560 kb
Host smart-01a4f84b-2b82-4c23-b569-ef4127233f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674384174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1674384174
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2440447528
Short name T308
Test name
Test status
Simulation time 26493184 ps
CPU time 2.25 seconds
Started Jun 04 02:17:35 PM PDT 24
Finished Jun 04 02:17:38 PM PDT 24
Peak memory 214092 kb
Host smart-8250ed20-2c7d-4e2a-8b49-819dd3a37ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440447528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2440447528
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2435163181
Short name T114
Test name
Test status
Simulation time 1315166058 ps
CPU time 26.93 seconds
Started Jun 04 02:17:36 PM PDT 24
Finished Jun 04 02:18:03 PM PDT 24
Peak memory 250912 kb
Host smart-59016910-be08-45c2-9b11-ed586f84656b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435163181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2435163181
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.4134858200
Short name T330
Test name
Test status
Simulation time 456495312 ps
CPU time 8.56 seconds
Started Jun 04 02:17:32 PM PDT 24
Finished Jun 04 02:17:41 PM PDT 24
Peak memory 250916 kb
Host smart-8699c971-ac37-4591-a0d7-e2c4a551ff37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134858200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.4134858200
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.2056544793
Short name T40
Test name
Test status
Simulation time 7264084928 ps
CPU time 93.97 seconds
Started Jun 04 02:17:35 PM PDT 24
Finished Jun 04 02:19:10 PM PDT 24
Peak memory 249212 kb
Host smart-d48186ef-aeae-4e13-8358-2daf8870f42e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056544793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.2056544793
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.1030519250
Short name T715
Test name
Test status
Simulation time 12192749313 ps
CPU time 234.68 seconds
Started Jun 04 02:17:34 PM PDT 24
Finished Jun 04 02:21:30 PM PDT 24
Peak memory 283600 kb
Host smart-31ad48f0-f728-4102-af2f-bfcaf8b615f0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1030519250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_stress_all_with_rand_reset.1030519250
Directory /workspace/35.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.1393384027
Short name T375
Test name
Test status
Simulation time 100011236 ps
CPU time 1.03 seconds
Started Jun 04 02:17:33 PM PDT 24
Finished Jun 04 02:17:35 PM PDT 24
Peak memory 208748 kb
Host smart-94f3d618-0a6d-4ed3-b5e3-bb7553c010e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393384027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.1393384027
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.4273736232
Short name T787
Test name
Test status
Simulation time 516814012 ps
CPU time 8.84 seconds
Started Jun 04 02:17:34 PM PDT 24
Finished Jun 04 02:17:44 PM PDT 24
Peak memory 217932 kb
Host smart-658cda16-415a-4fb2-93b6-825cb968a670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273736232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.4273736232
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.1133180267
Short name T347
Test name
Test status
Simulation time 2395121525 ps
CPU time 14.19 seconds
Started Jun 04 02:17:34 PM PDT 24
Finished Jun 04 02:17:49 PM PDT 24
Peak memory 209552 kb
Host smart-c5e7b547-79b3-4625-967c-7ecd218f30f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133180267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.1133180267
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2236931124
Short name T734
Test name
Test status
Simulation time 89673149 ps
CPU time 2.94 seconds
Started Jun 04 02:17:34 PM PDT 24
Finished Jun 04 02:17:38 PM PDT 24
Peak memory 218028 kb
Host smart-f6279574-9615-4279-8df3-6db61ceb10fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236931124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2236931124
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1271739678
Short name T714
Test name
Test status
Simulation time 402995434 ps
CPU time 13.33 seconds
Started Jun 04 02:17:36 PM PDT 24
Finished Jun 04 02:17:50 PM PDT 24
Peak memory 218896 kb
Host smart-46c1aa3e-4cb3-4253-a5e9-f7ff546f5dc9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271739678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1271739678
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.386682955
Short name T530
Test name
Test status
Simulation time 239107438 ps
CPU time 7.11 seconds
Started Jun 04 02:17:37 PM PDT 24
Finished Jun 04 02:17:45 PM PDT 24
Peak memory 224904 kb
Host smart-d6c27cab-b4c2-441d-ab5e-94af4fab6ce9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386682955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.386682955
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2946168299
Short name T467
Test name
Test status
Simulation time 439941815 ps
CPU time 9.31 seconds
Started Jun 04 02:17:35 PM PDT 24
Finished Jun 04 02:17:45 PM PDT 24
Peak memory 217928 kb
Host smart-187a47c3-0528-450a-88c8-cc8e750f469d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946168299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2946168299
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.3612916132
Short name T311
Test name
Test status
Simulation time 1304107730 ps
CPU time 11.11 seconds
Started Jun 04 02:17:36 PM PDT 24
Finished Jun 04 02:17:48 PM PDT 24
Peak memory 226040 kb
Host smart-b6c1897e-5b9b-4b4d-bcb1-6120a19aa8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612916132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.3612916132
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.4194520033
Short name T784
Test name
Test status
Simulation time 333864874 ps
CPU time 3.11 seconds
Started Jun 04 02:17:35 PM PDT 24
Finished Jun 04 02:17:39 PM PDT 24
Peak memory 217700 kb
Host smart-116569f1-96d2-45b7-8c69-133b5e094ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194520033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.4194520033
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.60603704
Short name T509
Test name
Test status
Simulation time 1883285838 ps
CPU time 22.67 seconds
Started Jun 04 02:17:35 PM PDT 24
Finished Jun 04 02:17:58 PM PDT 24
Peak memory 250912 kb
Host smart-aa356217-8e63-487b-9fa5-cc85e476dd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60603704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.60603704
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.150637416
Short name T483
Test name
Test status
Simulation time 303941175 ps
CPU time 9.91 seconds
Started Jun 04 02:17:40 PM PDT 24
Finished Jun 04 02:17:51 PM PDT 24
Peak memory 250872 kb
Host smart-60f039a6-2ead-4724-b622-590a435b485d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150637416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.150637416
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.3469317101
Short name T743
Test name
Test status
Simulation time 43458613584 ps
CPU time 176.08 seconds
Started Jun 04 02:17:36 PM PDT 24
Finished Jun 04 02:20:33 PM PDT 24
Peak memory 221076 kb
Host smart-c16e115d-261d-46f7-946d-cebf45d065d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469317101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.3469317101
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.2876536066
Short name T639
Test name
Test status
Simulation time 180630609 ps
CPU time 0.85 seconds
Started Jun 04 02:17:33 PM PDT 24
Finished Jun 04 02:17:35 PM PDT 24
Peak memory 211472 kb
Host smart-d987bd58-ce83-45b2-8656-fffa40da89c6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876536066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.2876536066
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.2550107107
Short name T695
Test name
Test status
Simulation time 198485616 ps
CPU time 1.01 seconds
Started Jun 04 02:17:45 PM PDT 24
Finished Jun 04 02:17:46 PM PDT 24
Peak memory 208708 kb
Host smart-70031cec-9160-4d62-81f6-ad49baa4119c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550107107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.2550107107
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.1659157132
Short name T510
Test name
Test status
Simulation time 845974252 ps
CPU time 18.17 seconds
Started Jun 04 02:17:39 PM PDT 24
Finished Jun 04 02:17:58 PM PDT 24
Peak memory 217996 kb
Host smart-eebfc54d-6abe-4a54-a1a4-2521f9ba8166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659157132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.1659157132
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.210830878
Short name T698
Test name
Test status
Simulation time 2516943163 ps
CPU time 5.05 seconds
Started Jun 04 02:17:39 PM PDT 24
Finished Jun 04 02:17:45 PM PDT 24
Peak memory 217324 kb
Host smart-f81a68d2-76d0-4332-9b55-16b478aa5cfe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210830878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.210830878
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3999068505
Short name T757
Test name
Test status
Simulation time 102313138 ps
CPU time 3.23 seconds
Started Jun 04 02:17:40 PM PDT 24
Finished Jun 04 02:17:44 PM PDT 24
Peak memory 217956 kb
Host smart-c443e7b8-b940-4d72-ac96-d92685590f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999068505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3999068505
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.618289580
Short name T62
Test name
Test status
Simulation time 1528052409 ps
CPU time 13.83 seconds
Started Jun 04 02:17:44 PM PDT 24
Finished Jun 04 02:17:58 PM PDT 24
Peak memory 218888 kb
Host smart-7889b308-c2c3-4a15-9504-d7496a768efc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618289580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.618289580
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.4240634431
Short name T692
Test name
Test status
Simulation time 1609799298 ps
CPU time 12.39 seconds
Started Jun 04 02:17:39 PM PDT 24
Finished Jun 04 02:17:52 PM PDT 24
Peak memory 225032 kb
Host smart-066486b3-dc94-44a6-9923-687873a4bb02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240634431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.4240634431
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.3772434221
Short name T610
Test name
Test status
Simulation time 420914669 ps
CPU time 8.96 seconds
Started Jun 04 02:17:38 PM PDT 24
Finished Jun 04 02:17:47 PM PDT 24
Peak memory 217952 kb
Host smart-11b59408-e8b0-49d5-9ec2-5b1267772360
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772434221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
3772434221
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.390489705
Short name T624
Test name
Test status
Simulation time 821880506 ps
CPU time 5.86 seconds
Started Jun 04 02:17:41 PM PDT 24
Finished Jun 04 02:17:48 PM PDT 24
Peak memory 218084 kb
Host smart-c5f1acae-9755-4831-b379-e4826cb72bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390489705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.390489705
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.209320558
Short name T806
Test name
Test status
Simulation time 59641050 ps
CPU time 3.47 seconds
Started Jun 04 02:17:40 PM PDT 24
Finished Jun 04 02:17:45 PM PDT 24
Peak memory 214332 kb
Host smart-89409223-f429-47a3-a4fe-61c26342aae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209320558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.209320558
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3614995075
Short name T461
Test name
Test status
Simulation time 1433522146 ps
CPU time 21.11 seconds
Started Jun 04 02:17:42 PM PDT 24
Finished Jun 04 02:18:04 PM PDT 24
Peak memory 250876 kb
Host smart-ed44bf05-a1c2-472e-abc7-a00667ca0a07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614995075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3614995075
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.1071375918
Short name T778
Test name
Test status
Simulation time 69718532 ps
CPU time 6.97 seconds
Started Jun 04 02:17:44 PM PDT 24
Finished Jun 04 02:17:51 PM PDT 24
Peak memory 242676 kb
Host smart-296e269a-5f3c-4e86-82ec-5d3f157e48a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071375918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.1071375918
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.1354264435
Short name T566
Test name
Test status
Simulation time 19131998626 ps
CPU time 338.39 seconds
Started Jun 04 02:17:41 PM PDT 24
Finished Jun 04 02:23:20 PM PDT 24
Peak memory 249012 kb
Host smart-919d8492-e722-4bdf-bf7f-e0974ab7c2bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354264435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.1354264435
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.3001458706
Short name T161
Test name
Test status
Simulation time 29097895315 ps
CPU time 850.33 seconds
Started Jun 04 02:17:41 PM PDT 24
Finished Jun 04 02:31:52 PM PDT 24
Peak memory 273944 kb
Host smart-4a2ca3c7-7a2f-44e9-9038-96cabdb11c72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3001458706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_stress_all_with_rand_reset.3001458706
Directory /workspace/37.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.141087192
Short name T713
Test name
Test status
Simulation time 78522765 ps
CPU time 1.11 seconds
Started Jun 04 02:17:40 PM PDT 24
Finished Jun 04 02:17:42 PM PDT 24
Peak memory 212644 kb
Host smart-926057de-36b1-4329-bfcd-b578f67ce008
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141087192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.141087192
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2462124114
Short name T247
Test name
Test status
Simulation time 114697187 ps
CPU time 0.9 seconds
Started Jun 04 02:17:46 PM PDT 24
Finished Jun 04 02:17:48 PM PDT 24
Peak memory 208752 kb
Host smart-e3bf9a92-72d0-4e08-8a12-e87be68faee6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462124114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2462124114
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2849557093
Short name T293
Test name
Test status
Simulation time 2916984210 ps
CPU time 20.18 seconds
Started Jun 04 02:17:47 PM PDT 24
Finished Jun 04 02:18:08 PM PDT 24
Peak memory 217928 kb
Host smart-77e0a9ce-c7bc-4be5-b3a2-01a7dd69341d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849557093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2849557093
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.2778257877
Short name T6
Test name
Test status
Simulation time 156202345 ps
CPU time 4.75 seconds
Started Jun 04 02:17:48 PM PDT 24
Finished Jun 04 02:17:53 PM PDT 24
Peak memory 216884 kb
Host smart-10405513-7b0b-4eb6-af1d-0b6ddfa50e28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778257877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.2778257877
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.59592451
Short name T649
Test name
Test status
Simulation time 88076488 ps
CPU time 1.56 seconds
Started Jun 04 02:17:40 PM PDT 24
Finished Jun 04 02:17:43 PM PDT 24
Peak memory 217976 kb
Host smart-fc42c5ab-9fa4-406b-8599-ad07ae97be75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59592451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.59592451
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.975057083
Short name T156
Test name
Test status
Simulation time 631849442 ps
CPU time 14.29 seconds
Started Jun 04 02:17:48 PM PDT 24
Finished Jun 04 02:18:03 PM PDT 24
Peak memory 218908 kb
Host smart-8f8c3422-75f8-4f5d-bea4-8e6ef53dcccd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975057083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.975057083
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.3504684704
Short name T288
Test name
Test status
Simulation time 646338943 ps
CPU time 20.34 seconds
Started Jun 04 02:17:47 PM PDT 24
Finished Jun 04 02:18:09 PM PDT 24
Peak memory 226040 kb
Host smart-edfe8657-5306-49bd-b2dd-01d90d45ebf4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504684704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.3504684704
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2145034185
Short name T180
Test name
Test status
Simulation time 857264979 ps
CPU time 8.52 seconds
Started Jun 04 02:17:49 PM PDT 24
Finished Jun 04 02:17:58 PM PDT 24
Peak memory 225980 kb
Host smart-195f58f9-9986-4dce-9467-8741fb50a49a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145034185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2145034185
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.2146380833
Short name T267
Test name
Test status
Simulation time 1373602316 ps
CPU time 9.36 seconds
Started Jun 04 02:17:47 PM PDT 24
Finished Jun 04 02:17:57 PM PDT 24
Peak memory 218068 kb
Host smart-bcc0ace4-96d2-42c1-ae50-f5f4fc4283b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146380833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.2146380833
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3514693349
Short name T176
Test name
Test status
Simulation time 80731768 ps
CPU time 2.59 seconds
Started Jun 04 02:17:41 PM PDT 24
Finished Jun 04 02:17:44 PM PDT 24
Peak memory 217668 kb
Host smart-04ddf716-d3ac-4e6b-8120-0f82cf82b190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514693349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3514693349
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.774175160
Short name T600
Test name
Test status
Simulation time 1211098319 ps
CPU time 23.25 seconds
Started Jun 04 02:17:40 PM PDT 24
Finished Jun 04 02:18:05 PM PDT 24
Peak memory 250884 kb
Host smart-187d1ce1-5fad-4851-9d37-8de191ea44cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774175160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.774175160
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.367983582
Short name T282
Test name
Test status
Simulation time 82161818 ps
CPU time 6.54 seconds
Started Jun 04 02:17:43 PM PDT 24
Finished Jun 04 02:17:50 PM PDT 24
Peak memory 250644 kb
Host smart-d5d10850-e068-4f7d-a401-904b25a99937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367983582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.367983582
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3158793335
Short name T197
Test name
Test status
Simulation time 7992094327 ps
CPU time 40.46 seconds
Started Jun 04 02:17:50 PM PDT 24
Finished Jun 04 02:18:31 PM PDT 24
Peak memory 246940 kb
Host smart-93d0ceb2-5f89-46e3-ab94-757a8827845b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158793335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3158793335
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.4272840989
Short name T555
Test name
Test status
Simulation time 15523357 ps
CPU time 0.91 seconds
Started Jun 04 02:17:41 PM PDT 24
Finished Jun 04 02:17:43 PM PDT 24
Peak memory 207936 kb
Host smart-295a3f26-3b92-4767-80af-905890ae8698
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272840989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.4272840989
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.2102027245
Short name T390
Test name
Test status
Simulation time 28039299 ps
CPU time 0.9 seconds
Started Jun 04 02:18:01 PM PDT 24
Finished Jun 04 02:18:02 PM PDT 24
Peak memory 209376 kb
Host smart-141188d0-223b-4a82-923e-8fecf40b9490
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102027245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.2102027245
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.905613315
Short name T491
Test name
Test status
Simulation time 687709675 ps
CPU time 10.15 seconds
Started Jun 04 02:17:48 PM PDT 24
Finished Jun 04 02:17:59 PM PDT 24
Peak memory 217944 kb
Host smart-4dca9838-150c-49ac-b3bc-9703717a7308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905613315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.905613315
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.2018866942
Short name T8
Test name
Test status
Simulation time 248808993 ps
CPU time 6.95 seconds
Started Jun 04 02:17:58 PM PDT 24
Finished Jun 04 02:18:05 PM PDT 24
Peak memory 209508 kb
Host smart-bfef1cca-6930-4d4e-84a8-9d2266abc47c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018866942 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.2018866942
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.870932873
Short name T814
Test name
Test status
Simulation time 306153719 ps
CPU time 3.08 seconds
Started Jun 04 02:17:46 PM PDT 24
Finished Jun 04 02:17:50 PM PDT 24
Peak memory 218076 kb
Host smart-e341d239-5485-47c9-916e-acb0c8fb9e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870932873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.870932873
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.4149836103
Short name T770
Test name
Test status
Simulation time 389597649 ps
CPU time 17.19 seconds
Started Jun 04 02:18:00 PM PDT 24
Finished Jun 04 02:18:18 PM PDT 24
Peak memory 218912 kb
Host smart-cbb7e273-a472-4e28-bb23-d91f53f6337c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149836103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.4149836103
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.515638512
Short name T303
Test name
Test status
Simulation time 1895074171 ps
CPU time 15.19 seconds
Started Jun 04 02:18:00 PM PDT 24
Finished Jun 04 02:18:16 PM PDT 24
Peak memory 225988 kb
Host smart-87727639-f652-4adb-aa8e-57bd54b75347
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515638512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.515638512
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.2240560545
Short name T725
Test name
Test status
Simulation time 234524583 ps
CPU time 7.65 seconds
Started Jun 04 02:18:00 PM PDT 24
Finished Jun 04 02:18:08 PM PDT 24
Peak memory 217920 kb
Host smart-bc2db753-ead1-4eda-811a-a7949bbe19e5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240560545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
2240560545
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.1539423738
Short name T762
Test name
Test status
Simulation time 1218840143 ps
CPU time 11.92 seconds
Started Jun 04 02:17:47 PM PDT 24
Finished Jun 04 02:18:00 PM PDT 24
Peak memory 226084 kb
Host smart-39ced577-5c8f-4d7b-b295-9d7e792cddc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539423738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.1539423738
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.924766019
Short name T429
Test name
Test status
Simulation time 89962219 ps
CPU time 3.49 seconds
Started Jun 04 02:17:47 PM PDT 24
Finished Jun 04 02:17:51 PM PDT 24
Peak memory 217676 kb
Host smart-eb150306-2138-469d-9d75-27baf8e94ffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924766019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.924766019
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.2864229762
Short name T12
Test name
Test status
Simulation time 578382436 ps
CPU time 19.25 seconds
Started Jun 04 02:17:48 PM PDT 24
Finished Jun 04 02:18:08 PM PDT 24
Peak memory 250888 kb
Host smart-b70c67f1-a45a-4f05-915a-88a30172579d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864229762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.2864229762
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.3062808682
Short name T679
Test name
Test status
Simulation time 282266454 ps
CPU time 9.73 seconds
Started Jun 04 02:17:47 PM PDT 24
Finished Jun 04 02:17:58 PM PDT 24
Peak memory 250356 kb
Host smart-9bef279d-f03e-40e2-985d-32f64bea2967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062808682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.3062808682
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.451999964
Short name T91
Test name
Test status
Simulation time 1727941058 ps
CPU time 39.13 seconds
Started Jun 04 02:18:00 PM PDT 24
Finished Jun 04 02:18:40 PM PDT 24
Peak memory 248140 kb
Host smart-854e93e0-6fa0-489d-bb40-29bdec8863f6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451999964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.451999964
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.664777772
Short name T813
Test name
Test status
Simulation time 14715517 ps
CPU time 0.94 seconds
Started Jun 04 02:17:49 PM PDT 24
Finished Jun 04 02:17:51 PM PDT 24
Peak memory 212676 kb
Host smart-bb20668f-bd3e-425e-97b1-32e34b2a029a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664777772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ct
rl_volatile_unlock_smoke.664777772
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.686629966
Short name T608
Test name
Test status
Simulation time 47066367 ps
CPU time 1.04 seconds
Started Jun 04 02:13:45 PM PDT 24
Finished Jun 04 02:13:47 PM PDT 24
Peak memory 208712 kb
Host smart-b157e365-53f1-4416-bac7-82f20853c964
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686629966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.686629966
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.2314113686
Short name T413
Test name
Test status
Simulation time 325549424 ps
CPU time 11.16 seconds
Started Jun 04 02:13:45 PM PDT 24
Finished Jun 04 02:13:57 PM PDT 24
Peak memory 218084 kb
Host smart-29cd11c4-d712-41e0-b016-d827984ad100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314113686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.2314113686
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.2541205363
Short name T646
Test name
Test status
Simulation time 1874327899 ps
CPU time 6.46 seconds
Started Jun 04 02:13:50 PM PDT 24
Finished Jun 04 02:13:58 PM PDT 24
Peak memory 216956 kb
Host smart-ad84c2c0-25fe-46e5-a64c-97294f485ed0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541205363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.2541205363
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.3319351904
Short name T660
Test name
Test status
Simulation time 2238204865 ps
CPU time 40.19 seconds
Started Jun 04 02:13:46 PM PDT 24
Finished Jun 04 02:14:27 PM PDT 24
Peak memory 219992 kb
Host smart-18555883-039a-41af-a2ee-e86c63559f43
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319351904 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.3319351904
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1633096691
Short name T580
Test name
Test status
Simulation time 2224236345 ps
CPU time 11.17 seconds
Started Jun 04 02:13:45 PM PDT 24
Finished Jun 04 02:13:56 PM PDT 24
Peak memory 217132 kb
Host smart-b6f5a650-cf40-4d24-933f-68bfcd71b068
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633096691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
633096691
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.1035569934
Short name T683
Test name
Test status
Simulation time 293545685 ps
CPU time 5.42 seconds
Started Jun 04 02:13:46 PM PDT 24
Finished Jun 04 02:13:52 PM PDT 24
Peak memory 218136 kb
Host smart-717acf0c-5bb9-4dd5-9b40-819ad58554e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035569934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.1035569934
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.2926940046
Short name T368
Test name
Test status
Simulation time 4968036943 ps
CPU time 32.79 seconds
Started Jun 04 02:13:46 PM PDT 24
Finished Jun 04 02:14:19 PM PDT 24
Peak memory 217640 kb
Host smart-aadbe9d4-6fa6-490e-88d6-4c95cc18cfab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926940046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.2926940046
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.4174547611
Short name T74
Test name
Test status
Simulation time 174073713 ps
CPU time 2.93 seconds
Started Jun 04 02:13:46 PM PDT 24
Finished Jun 04 02:13:50 PM PDT 24
Peak memory 217684 kb
Host smart-7073abaa-93e4-428d-bc25-bab5ec3f0a18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174547611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
4174547611
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.3392149969
Short name T503
Test name
Test status
Simulation time 2585396115 ps
CPU time 58.17 seconds
Started Jun 04 02:13:51 PM PDT 24
Finished Jun 04 02:14:50 PM PDT 24
Peak memory 267656 kb
Host smart-191df02a-ac11-44d4-b7d0-1c98fc8f754a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392149969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.3392149969
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1824568372
Short name T225
Test name
Test status
Simulation time 1942963876 ps
CPU time 13.83 seconds
Started Jun 04 02:13:46 PM PDT 24
Finished Jun 04 02:14:00 PM PDT 24
Peak memory 250444 kb
Host smart-1e0c6e6c-5c58-456c-8b41-4f2ccb262ece
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824568372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1824568372
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2713044815
Short name T564
Test name
Test status
Simulation time 47750403 ps
CPU time 2.43 seconds
Started Jun 04 02:13:42 PM PDT 24
Finished Jun 04 02:13:45 PM PDT 24
Peak memory 218028 kb
Host smart-0429646f-1275-45dd-aaa1-537385742746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713044815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2713044815
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3669601155
Short name T81
Test name
Test status
Simulation time 569890411 ps
CPU time 11.61 seconds
Started Jun 04 02:13:47 PM PDT 24
Finished Jun 04 02:14:00 PM PDT 24
Peak memory 214432 kb
Host smart-84a676ac-a3dd-42e5-9ddf-637362c8bd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669601155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3669601155
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3113326607
Short name T52
Test name
Test status
Simulation time 224778674 ps
CPU time 34.78 seconds
Started Jun 04 02:13:48 PM PDT 24
Finished Jun 04 02:14:24 PM PDT 24
Peak memory 281964 kb
Host smart-bb45cac8-b941-453a-b1fd-00afd095159a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113326607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3113326607
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.4029720322
Short name T518
Test name
Test status
Simulation time 270349265 ps
CPU time 14.79 seconds
Started Jun 04 02:13:46 PM PDT 24
Finished Jun 04 02:14:01 PM PDT 24
Peak memory 218948 kb
Host smart-008d9414-fce6-484d-b116-e180ffbbfc72
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029720322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.4029720322
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.356626503
Short name T820
Test name
Test status
Simulation time 446814321 ps
CPU time 9.72 seconds
Started Jun 04 02:13:51 PM PDT 24
Finished Jun 04 02:14:02 PM PDT 24
Peak memory 225580 kb
Host smart-48bb5ba3-1b1b-40c7-8e4f-7039a2d90453
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356626503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_dig
est.356626503
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.746953751
Short name T738
Test name
Test status
Simulation time 553886108 ps
CPU time 7.68 seconds
Started Jun 04 02:13:48 PM PDT 24
Finished Jun 04 02:13:56 PM PDT 24
Peak memory 218032 kb
Host smart-8d089652-93d8-42a1-993a-e7769e1b48df
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746953751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.746953751
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.2934594241
Short name T672
Test name
Test status
Simulation time 1693350466 ps
CPU time 10.62 seconds
Started Jun 04 02:13:45 PM PDT 24
Finished Jun 04 02:13:56 PM PDT 24
Peak memory 218044 kb
Host smart-7613f12b-c118-410e-b43f-0dca1fc91c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934594241 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.2934594241
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.3390869672
Short name T82
Test name
Test status
Simulation time 90779243 ps
CPU time 1.46 seconds
Started Jun 04 02:13:39 PM PDT 24
Finished Jun 04 02:13:41 PM PDT 24
Peak memory 213464 kb
Host smart-5d3e1173-fece-4216-9872-4c5c981c3b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390869672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.3390869672
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.3956238220
Short name T261
Test name
Test status
Simulation time 362985106 ps
CPU time 20.59 seconds
Started Jun 04 02:13:41 PM PDT 24
Finished Jun 04 02:14:02 PM PDT 24
Peak memory 250844 kb
Host smart-f7911ab3-4332-4be2-982a-013e456f431b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956238220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.3956238220
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1385426575
Short name T854
Test name
Test status
Simulation time 98210811 ps
CPU time 3.45 seconds
Started Jun 04 02:13:39 PM PDT 24
Finished Jun 04 02:13:43 PM PDT 24
Peak memory 226404 kb
Host smart-a524f56a-4f7b-4d07-ac7c-77cd8bee8317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385426575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1385426575
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3925496174
Short name T805
Test name
Test status
Simulation time 2235536018 ps
CPU time 76.47 seconds
Started Jun 04 02:13:45 PM PDT 24
Finished Jun 04 02:15:02 PM PDT 24
Peak memory 250948 kb
Host smart-2a219c72-80f7-4e87-b0e0-3f4b38be984b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925496174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3925496174
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3308907694
Short name T611
Test name
Test status
Simulation time 70922766 ps
CPU time 0.8 seconds
Started Jun 04 02:13:38 PM PDT 24
Finished Jun 04 02:13:40 PM PDT 24
Peak memory 211428 kb
Host smart-b48e79b1-10ea-47ea-ab0f-d6be8dff3b6c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308907694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.3308907694
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.2829687078
Short name T280
Test name
Test status
Simulation time 51787118 ps
CPU time 1.22 seconds
Started Jun 04 02:18:03 PM PDT 24
Finished Jun 04 02:18:05 PM PDT 24
Peak memory 208668 kb
Host smart-293c6dcb-98e9-4271-a84d-f66200c2fe07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829687078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.2829687078
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2170300693
Short name T394
Test name
Test status
Simulation time 216069136 ps
CPU time 10.42 seconds
Started Jun 04 02:17:59 PM PDT 24
Finished Jun 04 02:18:10 PM PDT 24
Peak memory 217988 kb
Host smart-4a4ed18d-b866-4288-a208-71dc0e1c0404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170300693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2170300693
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.682965625
Short name T598
Test name
Test status
Simulation time 1032636481 ps
CPU time 23.54 seconds
Started Jun 04 02:17:59 PM PDT 24
Finished Jun 04 02:18:23 PM PDT 24
Peak memory 209508 kb
Host smart-0b10f0b1-cac1-4683-999c-a5280dd7b66e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682965625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.682965625
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.890559618
Short name T283
Test name
Test status
Simulation time 406946497 ps
CPU time 3.14 seconds
Started Jun 04 02:18:01 PM PDT 24
Finished Jun 04 02:18:05 PM PDT 24
Peak memory 218024 kb
Host smart-25fe90f7-2072-4a40-938a-083c00cb937b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890559618 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.890559618
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.425845117
Short name T572
Test name
Test status
Simulation time 294112793 ps
CPU time 11.66 seconds
Started Jun 04 02:18:00 PM PDT 24
Finished Jun 04 02:18:13 PM PDT 24
Peak memory 218948 kb
Host smart-30a70d34-6832-4f27-8123-c7090b0553bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425845117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.425845117
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1058637516
Short name T350
Test name
Test status
Simulation time 224126638 ps
CPU time 9.5 seconds
Started Jun 04 02:17:58 PM PDT 24
Finished Jun 04 02:18:08 PM PDT 24
Peak memory 217920 kb
Host smart-6012c3ca-7fc2-4248-9e65-1318fbf479eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058637516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1058637516
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.3746044730
Short name T441
Test name
Test status
Simulation time 192460083 ps
CPU time 7.39 seconds
Started Jun 04 02:17:59 PM PDT 24
Finished Jun 04 02:18:07 PM PDT 24
Peak memory 217964 kb
Host smart-45a40e8b-c7ba-4b42-b514-ae1e55961a0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746044730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
3746044730
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.1766584316
Short name T809
Test name
Test status
Simulation time 450079372 ps
CPU time 7.89 seconds
Started Jun 04 02:17:59 PM PDT 24
Finished Jun 04 02:18:07 PM PDT 24
Peak memory 225264 kb
Host smart-1ce05b84-3a49-464f-a77e-331fb2346cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766584316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.1766584316
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.1318841133
Short name T83
Test name
Test status
Simulation time 194349767 ps
CPU time 2.76 seconds
Started Jun 04 02:18:02 PM PDT 24
Finished Jun 04 02:18:05 PM PDT 24
Peak memory 214212 kb
Host smart-30b77920-2948-42e3-846f-d594b7907a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318841133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.1318841133
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.327826788
Short name T726
Test name
Test status
Simulation time 983577050 ps
CPU time 30.45 seconds
Started Jun 04 02:17:59 PM PDT 24
Finished Jun 04 02:18:30 PM PDT 24
Peak memory 250928 kb
Host smart-06083097-c534-4ca3-87ef-b31f3192c843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327826788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.327826788
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1944658751
Short name T260
Test name
Test status
Simulation time 229225848 ps
CPU time 3.19 seconds
Started Jun 04 02:18:00 PM PDT 24
Finished Jun 04 02:18:04 PM PDT 24
Peak memory 222404 kb
Host smart-1a8e7e9d-f84a-4ecd-b9f8-25a2d821bf6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944658751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1944658751
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2313683920
Short name T631
Test name
Test status
Simulation time 42299446 ps
CPU time 1.03 seconds
Started Jun 04 02:18:00 PM PDT 24
Finished Jun 04 02:18:02 PM PDT 24
Peak memory 211464 kb
Host smart-7cb8155d-9a0c-4c4c-8ce3-90928e63ba42
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313683920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2313683920
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.217643056
Short name T527
Test name
Test status
Simulation time 80695773 ps
CPU time 1.26 seconds
Started Jun 04 02:18:03 PM PDT 24
Finished Jun 04 02:18:05 PM PDT 24
Peak memory 208696 kb
Host smart-3a65caf4-c6fe-437b-bba6-ddc85f6c57e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217643056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.217643056
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3862258649
Short name T859
Test name
Test status
Simulation time 192197795 ps
CPU time 10.1 seconds
Started Jun 04 02:18:03 PM PDT 24
Finished Jun 04 02:18:14 PM PDT 24
Peak memory 218072 kb
Host smart-a82faf29-3c62-475a-b3c5-28980d343397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862258649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3862258649
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1419647281
Short name T845
Test name
Test status
Simulation time 2168197963 ps
CPU time 11.49 seconds
Started Jun 04 02:18:01 PM PDT 24
Finished Jun 04 02:18:14 PM PDT 24
Peak memory 209564 kb
Host smart-bc9502ae-cdc1-404c-8eac-7de06b65838d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419647281 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1419647281
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.2787190962
Short name T60
Test name
Test status
Simulation time 105522761 ps
CPU time 3.15 seconds
Started Jun 04 02:18:01 PM PDT 24
Finished Jun 04 02:18:05 PM PDT 24
Peak memory 217976 kb
Host smart-08738654-8d8c-4858-89c0-78cb6be11397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787190962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.2787190962
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1026665680
Short name T795
Test name
Test status
Simulation time 636929772 ps
CPU time 13.62 seconds
Started Jun 04 02:18:03 PM PDT 24
Finished Jun 04 02:18:17 PM PDT 24
Peak memory 226072 kb
Host smart-9bc05c93-cb7d-4c60-9484-c4e2fb2c546f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026665680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1026665680
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2497236351
Short name T677
Test name
Test status
Simulation time 228934040 ps
CPU time 11.73 seconds
Started Jun 04 02:18:01 PM PDT 24
Finished Jun 04 02:18:13 PM PDT 24
Peak memory 225984 kb
Host smart-6cc2c65f-745d-41a5-984e-4b45483348ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497236351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2497236351
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.3153309277
Short name T688
Test name
Test status
Simulation time 286647908 ps
CPU time 11.75 seconds
Started Jun 04 02:18:02 PM PDT 24
Finished Jun 04 02:18:14 PM PDT 24
Peak memory 217932 kb
Host smart-f50840c8-6b60-4cbd-9e6f-d13e0ec94f46
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153309277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
3153309277
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.4131920806
Short name T591
Test name
Test status
Simulation time 555316144 ps
CPU time 11.52 seconds
Started Jun 04 02:18:03 PM PDT 24
Finished Jun 04 02:18:15 PM PDT 24
Peak memory 218072 kb
Host smart-322c3ce7-c7f5-4669-b9ce-64477fb08e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131920806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.4131920806
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.1196468571
Short name T238
Test name
Test status
Simulation time 59646524 ps
CPU time 2.17 seconds
Started Jun 04 02:18:02 PM PDT 24
Finished Jun 04 02:18:05 PM PDT 24
Peak memory 213940 kb
Host smart-8ec6978b-a67c-4416-9f16-f29927be116a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196468571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.1196468571
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.557694579
Short name T106
Test name
Test status
Simulation time 218892735 ps
CPU time 21.07 seconds
Started Jun 04 02:18:05 PM PDT 24
Finished Jun 04 02:18:26 PM PDT 24
Peak memory 250892 kb
Host smart-133ed78c-f240-4c12-a576-e9ce69a2e6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=557694579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.557694579
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.2319816088
Short name T593
Test name
Test status
Simulation time 623211763 ps
CPU time 6.09 seconds
Started Jun 04 02:18:03 PM PDT 24
Finished Jun 04 02:18:10 PM PDT 24
Peak memory 246944 kb
Host smart-4f2deb87-f40a-40cd-adde-776b6458ec1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319816088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.2319816088
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.563009431
Short name T737
Test name
Test status
Simulation time 2325021409 ps
CPU time 105.59 seconds
Started Jun 04 02:18:03 PM PDT 24
Finished Jun 04 02:19:50 PM PDT 24
Peak memory 249148 kb
Host smart-bee1eddc-db2f-4844-9d16-c60bb8923558
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563009431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.563009431
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.2836390124
Short name T92
Test name
Test status
Simulation time 29370166029 ps
CPU time 131.51 seconds
Started Jun 04 02:18:03 PM PDT 24
Finished Jun 04 02:20:16 PM PDT 24
Peak memory 300016 kb
Host smart-f19bd4dc-d79a-46c4-80a2-5651a0a625ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2836390124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.2836390124
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1338947162
Short name T694
Test name
Test status
Simulation time 65034833 ps
CPU time 1.01 seconds
Started Jun 04 02:18:04 PM PDT 24
Finished Jun 04 02:18:06 PM PDT 24
Peak memory 211544 kb
Host smart-9d858568-8222-48ed-9206-2fc72130e712
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338947162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1338947162
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.3314013766
Short name T369
Test name
Test status
Simulation time 23617305 ps
CPU time 0.96 seconds
Started Jun 04 02:18:14 PM PDT 24
Finished Jun 04 02:18:15 PM PDT 24
Peak memory 208740 kb
Host smart-4322e378-475d-4a95-8c3d-4133e6da13bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314013766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.3314013766
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.3401029144
Short name T336
Test name
Test status
Simulation time 1705004920 ps
CPU time 25.51 seconds
Started Jun 04 02:18:04 PM PDT 24
Finished Jun 04 02:18:30 PM PDT 24
Peak memory 218044 kb
Host smart-5835e279-a382-42c7-ac9c-c83c6b09c4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401029144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.3401029144
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.1277808747
Short name T644
Test name
Test status
Simulation time 1293205164 ps
CPU time 9.71 seconds
Started Jun 04 02:18:09 PM PDT 24
Finished Jun 04 02:18:20 PM PDT 24
Peak memory 209520 kb
Host smart-e5dee296-a9de-4fcb-8c6b-a0ef4a122a52
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277808747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.1277808747
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.480571436
Short name T37
Test name
Test status
Simulation time 305231440 ps
CPU time 3.86 seconds
Started Jun 04 02:18:02 PM PDT 24
Finished Jun 04 02:18:06 PM PDT 24
Peak memory 217920 kb
Host smart-9c55fa77-7d4c-4e00-8de6-933364b7dfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480571436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.480571436
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.1182676516
Short name T358
Test name
Test status
Simulation time 431086662 ps
CPU time 18.22 seconds
Started Jun 04 02:18:08 PM PDT 24
Finished Jun 04 02:18:27 PM PDT 24
Peak memory 218952 kb
Host smart-8f25803a-3e04-42ff-9e56-a96bbc2c2f8d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182676516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.1182676516
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2796610743
Short name T774
Test name
Test status
Simulation time 564919366 ps
CPU time 12.23 seconds
Started Jun 04 02:18:11 PM PDT 24
Finished Jun 04 02:18:24 PM PDT 24
Peak memory 224648 kb
Host smart-e8a65e26-6708-4aec-a21b-881cadff55af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796610743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2796610743
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.151351862
Short name T636
Test name
Test status
Simulation time 322955595 ps
CPU time 6.85 seconds
Started Jun 04 02:18:16 PM PDT 24
Finished Jun 04 02:18:23 PM PDT 24
Peak memory 217996 kb
Host smart-790985d8-f4ff-40c7-9f6f-17e7caf4b3ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151351862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.151351862
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3166805487
Short name T523
Test name
Test status
Simulation time 1268834558 ps
CPU time 9.14 seconds
Started Jun 04 02:18:03 PM PDT 24
Finished Jun 04 02:18:13 PM PDT 24
Peak memory 225152 kb
Host smart-2ca83813-b704-49fd-9c33-6e66c66507c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166805487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3166805487
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2325589630
Short name T663
Test name
Test status
Simulation time 482943428 ps
CPU time 1.73 seconds
Started Jun 04 02:18:03 PM PDT 24
Finished Jun 04 02:18:05 PM PDT 24
Peak memory 217692 kb
Host smart-2a7e3af7-c559-47e1-8265-e15e7c4e74b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325589630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2325589630
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1242869541
Short name T798
Test name
Test status
Simulation time 215820354 ps
CPU time 28.09 seconds
Started Jun 04 02:18:02 PM PDT 24
Finished Jun 04 02:18:31 PM PDT 24
Peak memory 250868 kb
Host smart-f598aa7d-8ea8-4acf-9e4c-f3764b61545b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242869541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1242869541
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2471659301
Short name T381
Test name
Test status
Simulation time 134216872 ps
CPU time 9.94 seconds
Started Jun 04 02:18:03 PM PDT 24
Finished Jun 04 02:18:14 PM PDT 24
Peak memory 250904 kb
Host smart-5fa80212-639d-4b8e-afe5-653e3c589049
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471659301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2471659301
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.4068498462
Short name T323
Test name
Test status
Simulation time 2248388132 ps
CPU time 47.53 seconds
Started Jun 04 02:18:09 PM PDT 24
Finished Jun 04 02:18:57 PM PDT 24
Peak memory 250772 kb
Host smart-1f9e129a-bb57-4827-9fbf-78fa1967c918
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068498462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.4068498462
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1524840347
Short name T249
Test name
Test status
Simulation time 53985588 ps
CPU time 0.97 seconds
Started Jun 04 02:18:02 PM PDT 24
Finished Jun 04 02:18:04 PM PDT 24
Peak memory 211504 kb
Host smart-033d766d-5cac-4e54-967c-6e42d25d6067
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524840347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1524840347
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.712323422
Short name T246
Test name
Test status
Simulation time 21813587 ps
CPU time 1.04 seconds
Started Jun 04 02:18:17 PM PDT 24
Finished Jun 04 02:18:19 PM PDT 24
Peak memory 209504 kb
Host smart-1f73d1ed-599f-448c-9ad6-d690a0f45239
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712323422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.712323422
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.2510995581
Short name T662
Test name
Test status
Simulation time 828531776 ps
CPU time 10.7 seconds
Started Jun 04 02:18:11 PM PDT 24
Finished Jun 04 02:18:22 PM PDT 24
Peak memory 217992 kb
Host smart-95b939af-65f5-49ad-af1b-ce23058fdc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510995581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.2510995581
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3773991804
Short name T578
Test name
Test status
Simulation time 512227133 ps
CPU time 13.37 seconds
Started Jun 04 02:18:08 PM PDT 24
Finished Jun 04 02:18:22 PM PDT 24
Peak memory 209496 kb
Host smart-f071b11e-009b-43b5-8f54-835b3cb8892d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773991804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3773991804
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1156895935
Short name T233
Test name
Test status
Simulation time 144689235 ps
CPU time 3.55 seconds
Started Jun 04 02:18:11 PM PDT 24
Finished Jun 04 02:18:15 PM PDT 24
Peak memory 217984 kb
Host smart-57b239db-f3b6-49cd-87f2-72a55589d6a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156895935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1156895935
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.797948433
Short name T35
Test name
Test status
Simulation time 3159779804 ps
CPU time 17.41 seconds
Started Jun 04 02:18:09 PM PDT 24
Finished Jun 04 02:18:27 PM PDT 24
Peak memory 219284 kb
Host smart-f01e2f3a-678b-47a7-82f6-aafb52dd50ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797948433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.797948433
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.1393290771
Short name T456
Test name
Test status
Simulation time 324875463 ps
CPU time 13.75 seconds
Started Jun 04 02:18:09 PM PDT 24
Finished Jun 04 02:18:23 PM PDT 24
Peak memory 226032 kb
Host smart-4af3885a-2d36-4842-a001-6805a3c1acd6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393290771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.1393290771
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1574813080
Short name T830
Test name
Test status
Simulation time 520845503 ps
CPU time 10.97 seconds
Started Jun 04 02:18:16 PM PDT 24
Finished Jun 04 02:18:27 PM PDT 24
Peak memory 218000 kb
Host smart-642b1aed-7c1d-4e66-bbb1-4ec8c5d73071
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574813080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1574813080
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.1054222617
Short name T277
Test name
Test status
Simulation time 758518625 ps
CPU time 9.16 seconds
Started Jun 04 02:18:08 PM PDT 24
Finished Jun 04 02:18:18 PM PDT 24
Peak memory 224712 kb
Host smart-022f2461-02be-4ced-aa3e-1b23193c8fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054222617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.1054222617
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.3267132924
Short name T482
Test name
Test status
Simulation time 35314245 ps
CPU time 2.22 seconds
Started Jun 04 02:18:11 PM PDT 24
Finished Jun 04 02:18:14 PM PDT 24
Peak memory 213748 kb
Host smart-1ad04a78-c919-4133-9c5b-e410d455a75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267132924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.3267132924
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.120899235
Short name T786
Test name
Test status
Simulation time 248748141 ps
CPU time 21.84 seconds
Started Jun 04 02:18:10 PM PDT 24
Finished Jun 04 02:18:32 PM PDT 24
Peak memory 250980 kb
Host smart-f35dd5a2-2500-4a31-906b-2ea70b918fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120899235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.120899235
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1622508390
Short name T516
Test name
Test status
Simulation time 759180934 ps
CPU time 2.6 seconds
Started Jun 04 02:18:16 PM PDT 24
Finished Jun 04 02:18:19 PM PDT 24
Peak memory 226412 kb
Host smart-39599f00-8e01-4cb0-8d33-c00d06c06d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622508390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1622508390
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.3758013346
Short name T459
Test name
Test status
Simulation time 705185953 ps
CPU time 20.23 seconds
Started Jun 04 02:18:10 PM PDT 24
Finished Jun 04 02:18:31 PM PDT 24
Peak memory 250840 kb
Host smart-c966626c-b5f9-4766-9115-d15baf294ab2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758013346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.3758013346
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3526814380
Short name T143
Test name
Test status
Simulation time 16232772 ps
CPU time 0.9 seconds
Started Jun 04 02:18:10 PM PDT 24
Finished Jun 04 02:18:11 PM PDT 24
Peak memory 211504 kb
Host smart-77f3e845-0fb7-4faf-abe5-4c3bf177d1b0
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526814380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3526814380
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.1676163770
Short name T187
Test name
Test status
Simulation time 22932719 ps
CPU time 1.13 seconds
Started Jun 04 02:18:16 PM PDT 24
Finished Jun 04 02:18:19 PM PDT 24
Peak memory 208736 kb
Host smart-64536498-3f7d-48d4-bc4d-fffecb3faf64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676163770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.1676163770
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.3290937184
Short name T38
Test name
Test status
Simulation time 290172648 ps
CPU time 9.67 seconds
Started Jun 04 02:18:17 PM PDT 24
Finished Jun 04 02:18:27 PM PDT 24
Peak memory 217988 kb
Host smart-0504b8a2-a744-47ae-ba11-2a791583477c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290937184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3290937184
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.1711985156
Short name T513
Test name
Test status
Simulation time 283920668 ps
CPU time 7.36 seconds
Started Jun 04 02:18:17 PM PDT 24
Finished Jun 04 02:18:26 PM PDT 24
Peak memory 216976 kb
Host smart-ef300263-6697-4422-b64d-785558c946ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711985156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.1711985156
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.890033950
Short name T440
Test name
Test status
Simulation time 185036660 ps
CPU time 2.76 seconds
Started Jun 04 02:18:17 PM PDT 24
Finished Jun 04 02:18:21 PM PDT 24
Peak memory 218076 kb
Host smart-aff7c03e-9aa5-4520-a541-5ec3c9ff136c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890033950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.890033950
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.452630938
Short name T815
Test name
Test status
Simulation time 603708281 ps
CPU time 15.9 seconds
Started Jun 04 02:18:17 PM PDT 24
Finished Jun 04 02:18:34 PM PDT 24
Peak memory 218964 kb
Host smart-06ce6803-30f7-4fe9-a348-0f647032d9cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452630938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.452630938
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1663549144
Short name T556
Test name
Test status
Simulation time 3893632189 ps
CPU time 11.58 seconds
Started Jun 04 02:18:18 PM PDT 24
Finished Jun 04 02:18:31 PM PDT 24
Peak memory 225988 kb
Host smart-6dfc4c22-8d7f-4e0e-adb6-277b18bfbb8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663549144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1663549144
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.1602778431
Short name T319
Test name
Test status
Simulation time 569560464 ps
CPU time 6.85 seconds
Started Jun 04 02:18:20 PM PDT 24
Finished Jun 04 02:18:27 PM PDT 24
Peak memory 217976 kb
Host smart-1a9398de-513e-44e9-bfd5-7f7d95cebe53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602778431 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
1602778431
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.2257866741
Short name T298
Test name
Test status
Simulation time 379826090 ps
CPU time 9.21 seconds
Started Jun 04 02:18:17 PM PDT 24
Finished Jun 04 02:18:27 PM PDT 24
Peak memory 218064 kb
Host smart-871edb1c-eca0-477f-a1aa-d1b2723a051f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257866741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.2257866741
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.2670132577
Short name T577
Test name
Test status
Simulation time 127347198 ps
CPU time 2.7 seconds
Started Jun 04 02:18:18 PM PDT 24
Finished Jun 04 02:18:22 PM PDT 24
Peak memory 214500 kb
Host smart-0b42b9ad-6f36-43a4-a0fb-5abba491d7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670132577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.2670132577
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.2777419329
Short name T434
Test name
Test status
Simulation time 278047563 ps
CPU time 22.67 seconds
Started Jun 04 02:18:17 PM PDT 24
Finished Jun 04 02:18:40 PM PDT 24
Peak memory 250916 kb
Host smart-96ff153a-718c-491c-bed4-9a7e1d6b1865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777419329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.2777419329
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.480396821
Short name T411
Test name
Test status
Simulation time 111132181 ps
CPU time 8.06 seconds
Started Jun 04 02:18:16 PM PDT 24
Finished Jun 04 02:18:24 PM PDT 24
Peak memory 250824 kb
Host smart-91449c4f-c39d-438c-a809-8bc1a51801c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480396821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.480396821
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.1239197884
Short name T384
Test name
Test status
Simulation time 4034993565 ps
CPU time 104.58 seconds
Started Jun 04 02:18:18 PM PDT 24
Finished Jun 04 02:20:04 PM PDT 24
Peak memory 250912 kb
Host smart-c329e70c-8f28-4dde-b921-9ae8133c55ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239197884 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.1239197884
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.1077563072
Short name T349
Test name
Test status
Simulation time 78541219 ps
CPU time 0.86 seconds
Started Jun 04 02:18:16 PM PDT 24
Finished Jun 04 02:18:17 PM PDT 24
Peak memory 211516 kb
Host smart-26f20b32-da76-4bae-89c4-22288832a1ad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077563072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.1077563072
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.3216773698
Short name T558
Test name
Test status
Simulation time 40104892 ps
CPU time 0.99 seconds
Started Jun 04 02:18:28 PM PDT 24
Finished Jun 04 02:18:30 PM PDT 24
Peak memory 208656 kb
Host smart-94949fdb-66d0-428a-815e-0754f137ae64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216773698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.3216773698
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.128933255
Short name T522
Test name
Test status
Simulation time 799175152 ps
CPU time 10.34 seconds
Started Jun 04 02:18:17 PM PDT 24
Finished Jun 04 02:18:29 PM PDT 24
Peak memory 217944 kb
Host smart-9529d216-5d11-41cf-ac44-f3d8de781574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128933255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.128933255
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.2298535927
Short name T567
Test name
Test status
Simulation time 797546957 ps
CPU time 2.5 seconds
Started Jun 04 02:18:17 PM PDT 24
Finished Jun 04 02:18:21 PM PDT 24
Peak memory 209500 kb
Host smart-9b87e6e5-37af-48a0-9b03-196b60da74f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298535927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.2298535927
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.686582874
Short name T96
Test name
Test status
Simulation time 116414316 ps
CPU time 1.72 seconds
Started Jun 04 02:18:18 PM PDT 24
Finished Jun 04 02:18:21 PM PDT 24
Peak memory 217952 kb
Host smart-d499efe7-cf53-4df1-99ca-63edf796d17f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686582874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.686582874
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.2883991535
Short name T424
Test name
Test status
Simulation time 339532101 ps
CPU time 11.42 seconds
Started Jun 04 02:18:17 PM PDT 24
Finished Jun 04 02:18:29 PM PDT 24
Peak memory 218944 kb
Host smart-92070f51-0247-43da-af38-806c2f58e774
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883991535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.2883991535
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.290567488
Short name T826
Test name
Test status
Simulation time 1068541540 ps
CPU time 20.45 seconds
Started Jun 04 02:18:24 PM PDT 24
Finished Jun 04 02:18:45 PM PDT 24
Peak memory 224920 kb
Host smart-5b44d7cb-7e84-40c9-94bd-0d72365f5745
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290567488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_di
gest.290567488
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.1513168998
Short name T842
Test name
Test status
Simulation time 363641708 ps
CPU time 9.41 seconds
Started Jun 04 02:18:17 PM PDT 24
Finished Jun 04 02:18:28 PM PDT 24
Peak memory 217944 kb
Host smart-7a81d61f-7c29-423c-aa44-45b20649f923
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513168998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
1513168998
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.3521456883
Short name T56
Test name
Test status
Simulation time 2918416020 ps
CPU time 10.28 seconds
Started Jun 04 02:18:18 PM PDT 24
Finished Jun 04 02:18:29 PM PDT 24
Peak memory 218104 kb
Host smart-623a7950-5c45-4b68-863e-eb019908e928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521456883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.3521456883
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.1093251680
Short name T782
Test name
Test status
Simulation time 24984434 ps
CPU time 1.68 seconds
Started Jun 04 02:18:17 PM PDT 24
Finished Jun 04 02:18:20 PM PDT 24
Peak memory 217716 kb
Host smart-a415b702-e9ed-4ea5-9e93-da7d903aa226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093251680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.1093251680
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.3540696707
Short name T540
Test name
Test status
Simulation time 279718878 ps
CPU time 29.11 seconds
Started Jun 04 02:18:16 PM PDT 24
Finished Jun 04 02:18:46 PM PDT 24
Peak memory 250912 kb
Host smart-74082e39-ec9a-4992-a3f5-fd3d0eddfa70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540696707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.3540696707
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.1617708155
Short name T295
Test name
Test status
Simulation time 104200902 ps
CPU time 8.58 seconds
Started Jun 04 02:18:16 PM PDT 24
Finished Jun 04 02:18:25 PM PDT 24
Peak memory 250880 kb
Host smart-06134804-61f1-47ff-aa93-5c2c0ac2ef9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617708155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.1617708155
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.525255869
Short name T671
Test name
Test status
Simulation time 7797830067 ps
CPU time 95.19 seconds
Started Jun 04 02:18:26 PM PDT 24
Finished Jun 04 02:20:02 PM PDT 24
Peak memory 283556 kb
Host smart-41f39230-f2fb-4cbb-a20b-74e63fe08def
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525255869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.525255869
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.2403835395
Short name T680
Test name
Test status
Simulation time 22373594 ps
CPU time 0.94 seconds
Started Jun 04 02:18:16 PM PDT 24
Finished Jun 04 02:18:17 PM PDT 24
Peak memory 211468 kb
Host smart-da6660a2-08ee-4ab9-b68e-c2cb2313913b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403835395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.2403835395
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.3903751742
Short name T287
Test name
Test status
Simulation time 21137140 ps
CPU time 0.94 seconds
Started Jun 04 02:18:23 PM PDT 24
Finished Jun 04 02:18:25 PM PDT 24
Peak memory 209548 kb
Host smart-9d8d2fc0-0a50-4592-922e-314af348bc41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903751742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.3903751742
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.3764978211
Short name T717
Test name
Test status
Simulation time 198921350 ps
CPU time 10.03 seconds
Started Jun 04 02:18:26 PM PDT 24
Finished Jun 04 02:18:36 PM PDT 24
Peak memory 217808 kb
Host smart-b72716b0-869b-4540-bc75-4d8099413111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764978211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.3764978211
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.2570612493
Short name T481
Test name
Test status
Simulation time 2867732192 ps
CPU time 5.83 seconds
Started Jun 04 02:18:22 PM PDT 24
Finished Jun 04 02:18:28 PM PDT 24
Peak memory 209576 kb
Host smart-b04ced8d-ea19-42d2-8a6a-4f8d54b0b154
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570612493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2570612493
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3117790232
Short name T158
Test name
Test status
Simulation time 37924800 ps
CPU time 2.1 seconds
Started Jun 04 02:18:24 PM PDT 24
Finished Jun 04 02:18:26 PM PDT 24
Peak memory 217988 kb
Host smart-f2e9393a-4d2b-455c-9dca-2e2c40e608e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117790232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3117790232
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.454471750
Short name T257
Test name
Test status
Simulation time 335694006 ps
CPU time 12.48 seconds
Started Jun 04 02:18:27 PM PDT 24
Finished Jun 04 02:18:40 PM PDT 24
Peak memory 218944 kb
Host smart-87b98243-7ce0-46dc-a166-a810c5971e65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454471750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.454471750
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.3677197733
Short name T167
Test name
Test status
Simulation time 263679559 ps
CPU time 12.96 seconds
Started Jun 04 02:18:24 PM PDT 24
Finished Jun 04 02:18:38 PM PDT 24
Peak memory 226020 kb
Host smart-119b339b-8fee-4fa1-9d19-0ad80e1d1611
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677197733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.3677197733
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.311631612
Short name T466
Test name
Test status
Simulation time 1101717130 ps
CPU time 8.71 seconds
Started Jun 04 02:18:24 PM PDT 24
Finished Jun 04 02:18:34 PM PDT 24
Peak memory 217972 kb
Host smart-af613795-4466-45ed-9955-da4367bd583b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311631612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.311631612
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.4094760037
Short name T51
Test name
Test status
Simulation time 391305620 ps
CPU time 13.36 seconds
Started Jun 04 02:18:24 PM PDT 24
Finished Jun 04 02:18:38 PM PDT 24
Peak memory 224744 kb
Host smart-aa9b2d87-d5ce-48f5-aeb3-b217971001c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094760037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.4094760037
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.3659287693
Short name T398
Test name
Test status
Simulation time 48509336 ps
CPU time 2.34 seconds
Started Jun 04 02:18:24 PM PDT 24
Finished Jun 04 02:18:27 PM PDT 24
Peak memory 213968 kb
Host smart-b0694e96-079d-400e-ae39-4071e435595f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659287693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.3659287693
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.4116216270
Short name T292
Test name
Test status
Simulation time 573574152 ps
CPU time 25.35 seconds
Started Jun 04 02:18:23 PM PDT 24
Finished Jun 04 02:18:49 PM PDT 24
Peak memory 250916 kb
Host smart-091d8173-3214-4414-a6b4-29c295bec306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116216270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.4116216270
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.1295821419
Short name T262
Test name
Test status
Simulation time 72966943 ps
CPU time 9.14 seconds
Started Jun 04 02:18:25 PM PDT 24
Finished Jun 04 02:18:35 PM PDT 24
Peak memory 250908 kb
Host smart-1e680af0-5709-4397-bb3e-baff9f5967b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295821419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.1295821419
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.1037775280
Short name T45
Test name
Test status
Simulation time 27236168195 ps
CPU time 222.99 seconds
Started Jun 04 02:18:24 PM PDT 24
Finished Jun 04 02:22:08 PM PDT 24
Peak memory 267320 kb
Host smart-a50dea7f-141a-4618-bff8-ef2c2e5701f7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037775280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.1037775280
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.39280140
Short name T549
Test name
Test status
Simulation time 35729430 ps
CPU time 1.16 seconds
Started Jun 04 02:18:27 PM PDT 24
Finished Jun 04 02:18:29 PM PDT 24
Peak memory 212632 kb
Host smart-ba04d281-784f-4f64-9ea1-ffe5f55e8543
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39280140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctr
l_volatile_unlock_smoke.39280140
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.2383190332
Short name T817
Test name
Test status
Simulation time 21526149 ps
CPU time 0.95 seconds
Started Jun 04 02:18:30 PM PDT 24
Finished Jun 04 02:18:31 PM PDT 24
Peak memory 208660 kb
Host smart-f9af2308-2b46-4cbf-9689-88561a387b05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383190332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.2383190332
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.1624112313
Short name T861
Test name
Test status
Simulation time 1291611917 ps
CPU time 14.51 seconds
Started Jun 04 02:18:25 PM PDT 24
Finished Jun 04 02:18:40 PM PDT 24
Peak memory 217944 kb
Host smart-8e81914d-171b-4815-aa72-345744b4613b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624112313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.1624112313
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2587467757
Short name T728
Test name
Test status
Simulation time 1308143197 ps
CPU time 16.61 seconds
Started Jun 04 02:18:30 PM PDT 24
Finished Jun 04 02:18:47 PM PDT 24
Peak memory 217280 kb
Host smart-dc60735f-1718-490f-80e3-accbc69cb6b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587467757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2587467757
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.3394651667
Short name T553
Test name
Test status
Simulation time 764902002 ps
CPU time 3.37 seconds
Started Jun 04 02:18:22 PM PDT 24
Finished Jun 04 02:18:26 PM PDT 24
Peak memory 218000 kb
Host smart-c030a6fc-ce8c-4d02-b1af-d86a0ce0db82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394651667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3394651667
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3268195766
Short name T389
Test name
Test status
Simulation time 590025793 ps
CPU time 14.34 seconds
Started Jun 04 02:18:32 PM PDT 24
Finished Jun 04 02:18:47 PM PDT 24
Peak memory 218096 kb
Host smart-71f9a0da-0ca7-410b-be2e-314182855803
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268195766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3268195766
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.69239619
Short name T779
Test name
Test status
Simulation time 1503575250 ps
CPU time 10.61 seconds
Started Jun 04 02:18:30 PM PDT 24
Finished Jun 04 02:18:41 PM PDT 24
Peak memory 225992 kb
Host smart-8aa73ae0-5e80-4f4c-9ae5-2464a30847c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69239619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_dig
est.69239619
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1852392211
Short name T271
Test name
Test status
Simulation time 415557986 ps
CPU time 10.09 seconds
Started Jun 04 02:18:31 PM PDT 24
Finished Jun 04 02:18:41 PM PDT 24
Peak memory 217912 kb
Host smart-6bffa99d-b4c6-4071-9f0d-cd5c1a84a1f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852392211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1852392211
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.4193369501
Short name T332
Test name
Test status
Simulation time 539001900 ps
CPU time 11.33 seconds
Started Jun 04 02:18:33 PM PDT 24
Finished Jun 04 02:18:45 PM PDT 24
Peak memory 225076 kb
Host smart-5145338a-adb8-41f4-89f9-8568b72473b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193369501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.4193369501
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.411569508
Short name T75
Test name
Test status
Simulation time 339850543 ps
CPU time 5.76 seconds
Started Jun 04 02:18:23 PM PDT 24
Finished Jun 04 02:18:30 PM PDT 24
Peak memory 217732 kb
Host smart-7b9871b7-dcf6-4d14-87af-51e5cc838c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411569508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.411569508
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.2963455061
Short name T811
Test name
Test status
Simulation time 3880383766 ps
CPU time 27.1 seconds
Started Jun 04 02:18:23 PM PDT 24
Finished Jun 04 02:18:50 PM PDT 24
Peak memory 250972 kb
Host smart-10757cf0-46bc-431b-bc20-b083b02745db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963455061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.2963455061
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.2508973838
Short name T290
Test name
Test status
Simulation time 286018390 ps
CPU time 8.07 seconds
Started Jun 04 02:18:25 PM PDT 24
Finished Jun 04 02:18:34 PM PDT 24
Peak memory 250860 kb
Host smart-69fd954e-009d-4842-95ef-e38e5b08abd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508973838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.2508973838
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2212943035
Short name T731
Test name
Test status
Simulation time 4965945229 ps
CPU time 133.61 seconds
Started Jun 04 02:18:31 PM PDT 24
Finished Jun 04 02:20:45 PM PDT 24
Peak memory 280920 kb
Host smart-00e71ca4-1790-4d9d-a599-991388f405c6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212943035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2212943035
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.307784561
Short name T64
Test name
Test status
Simulation time 34577923834 ps
CPU time 214.85 seconds
Started Jun 04 02:18:30 PM PDT 24
Finished Jun 04 02:22:06 PM PDT 24
Peak memory 283292 kb
Host smart-b23effab-1694-47a8-8a4a-9c27749fbf2f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=307784561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.307784561
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.340378568
Short name T450
Test name
Test status
Simulation time 26857008 ps
CPU time 0.88 seconds
Started Jun 04 02:18:28 PM PDT 24
Finished Jun 04 02:18:30 PM PDT 24
Peak memory 211528 kb
Host smart-78161393-1dfe-4e2b-86fd-3e673a0f98ab
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340378568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ct
rl_volatile_unlock_smoke.340378568
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.2926588701
Short name T89
Test name
Test status
Simulation time 21438214 ps
CPU time 0.98 seconds
Started Jun 04 02:18:39 PM PDT 24
Finished Jun 04 02:18:41 PM PDT 24
Peak memory 209556 kb
Host smart-4c07b331-1e58-4629-85a4-97f84ca50075
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926588701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.2926588701
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1708117324
Short name T111
Test name
Test status
Simulation time 524844145 ps
CPU time 20.66 seconds
Started Jun 04 02:18:31 PM PDT 24
Finished Jun 04 02:18:53 PM PDT 24
Peak memory 217944 kb
Host smart-a9252a3d-feb0-4def-ab2e-1930817e3e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708117324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1708117324
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3727887070
Short name T780
Test name
Test status
Simulation time 2271200595 ps
CPU time 14.01 seconds
Started Jun 04 02:18:31 PM PDT 24
Finished Jun 04 02:18:45 PM PDT 24
Peak memory 209604 kb
Host smart-a3a38467-2077-440a-bc13-a839bc3676a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727887070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.3727887070
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.2563434162
Short name T700
Test name
Test status
Simulation time 142607596 ps
CPU time 2.85 seconds
Started Jun 04 02:18:30 PM PDT 24
Finished Jun 04 02:18:33 PM PDT 24
Peak memory 218048 kb
Host smart-cb2046f1-8639-46cf-a289-57f46a593eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563434162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.2563434162
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.1993437040
Short name T722
Test name
Test status
Simulation time 1969515014 ps
CPU time 16.37 seconds
Started Jun 04 02:18:33 PM PDT 24
Finished Jun 04 02:18:50 PM PDT 24
Peak memory 218632 kb
Host smart-11e3f348-3378-45ad-a280-831ea41fb46c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993437040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.1993437040
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.4278635531
Short name T543
Test name
Test status
Simulation time 263990714 ps
CPU time 9.23 seconds
Started Jun 04 02:18:30 PM PDT 24
Finished Jun 04 02:18:40 PM PDT 24
Peak memory 226004 kb
Host smart-8410c7c3-f80b-4aad-852a-d70f92949c65
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278635531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_d
igest.4278635531
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.124523404
Short name T61
Test name
Test status
Simulation time 650793015 ps
CPU time 9.72 seconds
Started Jun 04 02:18:29 PM PDT 24
Finished Jun 04 02:18:39 PM PDT 24
Peak memory 217884 kb
Host smart-4de0faf2-aa0f-49b0-9937-4b484fd47f9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124523404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.124523404
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.4133697331
Short name T416
Test name
Test status
Simulation time 262572226 ps
CPU time 9.87 seconds
Started Jun 04 02:18:34 PM PDT 24
Finished Jun 04 02:18:44 PM PDT 24
Peak memory 218040 kb
Host smart-8781975e-ff2f-4a40-a58b-2ab3e1753843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133697331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.4133697331
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3994546821
Short name T63
Test name
Test status
Simulation time 221178316 ps
CPU time 2.82 seconds
Started Jun 04 02:18:30 PM PDT 24
Finished Jun 04 02:18:33 PM PDT 24
Peak memory 214148 kb
Host smart-7fb1d8bf-842a-44a9-b4eb-a54485a41ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994546821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3994546821
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.1047587755
Short name T777
Test name
Test status
Simulation time 387362055 ps
CPU time 26.7 seconds
Started Jun 04 02:18:31 PM PDT 24
Finished Jun 04 02:18:58 PM PDT 24
Peak memory 250908 kb
Host smart-a3b9613f-4bc2-4f25-a259-88ad02087620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047587755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.1047587755
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.905539
Short name T263
Test name
Test status
Simulation time 367981926 ps
CPU time 6.88 seconds
Started Jun 04 02:18:30 PM PDT 24
Finished Jun 04 02:18:37 PM PDT 24
Peak memory 250416 kb
Host smart-263b6c69-1992-4fe7-864a-505f87c56c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.905539
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.638312828
Short name T476
Test name
Test status
Simulation time 2357878635 ps
CPU time 42.58 seconds
Started Jun 04 02:18:34 PM PDT 24
Finished Jun 04 02:19:17 PM PDT 24
Peak memory 250960 kb
Host smart-169d0ec0-60c3-477b-bf4e-3f7968482de9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638312828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.638312828
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.1357281099
Short name T94
Test name
Test status
Simulation time 169359397643 ps
CPU time 969.23 seconds
Started Jun 04 02:18:31 PM PDT 24
Finished Jun 04 02:34:41 PM PDT 24
Peak memory 288340 kb
Host smart-c5aa735b-f037-4a90-aa98-97917a280c4c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1357281099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.1357281099
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.618898687
Short name T300
Test name
Test status
Simulation time 15984509 ps
CPU time 0.86 seconds
Started Jun 04 02:18:29 PM PDT 24
Finished Jun 04 02:18:31 PM PDT 24
Peak memory 211448 kb
Host smart-63de0a98-7dbc-4a42-9106-7de0c41b867a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618898687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct
rl_volatile_unlock_smoke.618898687
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.132384105
Short name T666
Test name
Test status
Simulation time 21097665 ps
CPU time 1.04 seconds
Started Jun 04 02:18:38 PM PDT 24
Finished Jun 04 02:18:40 PM PDT 24
Peak memory 208712 kb
Host smart-d79f4b98-d61f-4c5c-b61f-edfa2b75b453
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132384105 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.132384105
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.1182797034
Short name T472
Test name
Test status
Simulation time 1352203788 ps
CPU time 16.7 seconds
Started Jun 04 02:18:38 PM PDT 24
Finished Jun 04 02:18:55 PM PDT 24
Peak memory 217920 kb
Host smart-1ebfe3b9-331f-40b6-97b8-a4d62643cecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182797034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.1182797034
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.1152085110
Short name T571
Test name
Test status
Simulation time 1870672901 ps
CPU time 3.81 seconds
Started Jun 04 02:18:37 PM PDT 24
Finished Jun 04 02:18:42 PM PDT 24
Peak memory 209500 kb
Host smart-c3b65f52-3387-4c1d-ba3e-9726bea6b9e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152085110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.1152085110
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.1605322379
Short name T835
Test name
Test status
Simulation time 101698306 ps
CPU time 4.18 seconds
Started Jun 04 02:18:38 PM PDT 24
Finished Jun 04 02:18:43 PM PDT 24
Peak memory 217996 kb
Host smart-412578ed-2df2-404f-8acd-85b0c06066d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605322379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.1605322379
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.561186110
Short name T678
Test name
Test status
Simulation time 1559584227 ps
CPU time 17.68 seconds
Started Jun 04 02:18:37 PM PDT 24
Finished Jun 04 02:18:55 PM PDT 24
Peak memory 218936 kb
Host smart-aef913c8-b16b-4c21-976e-943f54d24911
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561186110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.561186110
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1213015420
Short name T505
Test name
Test status
Simulation time 1019584512 ps
CPU time 19.67 seconds
Started Jun 04 02:18:37 PM PDT 24
Finished Jun 04 02:18:57 PM PDT 24
Peak memory 226004 kb
Host smart-d818a63b-eeac-4006-9fb6-ecc68c0f4f0e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213015420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1213015420
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.394131100
Short name T501
Test name
Test status
Simulation time 748242566 ps
CPU time 9.4 seconds
Started Jun 04 02:18:34 PM PDT 24
Finished Jun 04 02:18:44 PM PDT 24
Peak memory 217948 kb
Host smart-a3c50bfc-1e00-4a63-a3d9-8d8e188be791
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394131100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.394131100
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.2159416913
Short name T379
Test name
Test status
Simulation time 270273067 ps
CPU time 11.86 seconds
Started Jun 04 02:18:37 PM PDT 24
Finished Jun 04 02:18:49 PM PDT 24
Peak memory 224608 kb
Host smart-d7dff84e-162e-4c9b-a1c2-2ff0106b0099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159416913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.2159416913
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.2754981061
Short name T305
Test name
Test status
Simulation time 134881080 ps
CPU time 2.7 seconds
Started Jun 04 02:18:37 PM PDT 24
Finished Jun 04 02:18:40 PM PDT 24
Peak memory 214136 kb
Host smart-0d6e886f-7f37-480c-bb8d-defd9087fcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754981061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.2754981061
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.1518867303
Short name T810
Test name
Test status
Simulation time 714360352 ps
CPU time 29.41 seconds
Started Jun 04 02:18:37 PM PDT 24
Finished Jun 04 02:19:08 PM PDT 24
Peak memory 250908 kb
Host smart-e2c1d3d0-1c95-42ed-b5ac-3fc699338651
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518867303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.1518867303
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.4077057048
Short name T689
Test name
Test status
Simulation time 442332186 ps
CPU time 9.4 seconds
Started Jun 04 02:18:38 PM PDT 24
Finished Jun 04 02:18:48 PM PDT 24
Peak memory 250808 kb
Host smart-e27bd9c3-2279-47b0-9b4f-ebdcc9109603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077057048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.4077057048
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2173446897
Short name T659
Test name
Test status
Simulation time 4426870152 ps
CPU time 51.1 seconds
Started Jun 04 02:18:36 PM PDT 24
Finished Jun 04 02:19:28 PM PDT 24
Peak memory 246664 kb
Host smart-3ff86e91-cb84-46a2-aa11-f3bf110cf73d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173446897 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2173446897
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all_with_rand_reset.2246785367
Short name T160
Test name
Test status
Simulation time 4932938782 ps
CPU time 158.68 seconds
Started Jun 04 02:18:38 PM PDT 24
Finished Jun 04 02:21:17 PM PDT 24
Peak memory 251088 kb
Host smart-25927ae6-03a6-4344-a194-a9e7f40f653a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2246785367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_stress_all_with_rand_reset.2246785367
Directory /workspace/49.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.2939687221
Short name T396
Test name
Test status
Simulation time 16325824 ps
CPU time 0.91 seconds
Started Jun 04 02:18:37 PM PDT 24
Finished Jun 04 02:18:39 PM PDT 24
Peak memory 212568 kb
Host smart-b97497ee-1049-4d89-b4cd-0d151457c790
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939687221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.2939687221
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.3133127901
Short name T658
Test name
Test status
Simulation time 42469614 ps
CPU time 0.97 seconds
Started Jun 04 02:14:07 PM PDT 24
Finished Jun 04 02:14:08 PM PDT 24
Peak memory 209560 kb
Host smart-1fc2a58e-fc49-44cc-bcb0-4d4875f8b17f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133127901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.3133127901
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.3968846256
Short name T131
Test name
Test status
Simulation time 41615646 ps
CPU time 0.94 seconds
Started Jun 04 02:13:54 PM PDT 24
Finished Jun 04 02:13:56 PM PDT 24
Peak memory 208608 kb
Host smart-54e02f3c-3da3-4b9b-8364-4cb1f98fdc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968846256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.3968846256
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.2815173001
Short name T230
Test name
Test status
Simulation time 7012111058 ps
CPU time 9.64 seconds
Started Jun 04 02:13:54 PM PDT 24
Finished Jun 04 02:14:05 PM PDT 24
Peak memory 218124 kb
Host smart-e6011724-706f-4944-9c60-45677b22ed61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815173001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.2815173001
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.181881383
Short name T399
Test name
Test status
Simulation time 396912299 ps
CPU time 3.3 seconds
Started Jun 04 02:13:54 PM PDT 24
Finished Jun 04 02:13:58 PM PDT 24
Peak memory 209516 kb
Host smart-2dce09cf-e98e-432a-928d-e25adc612552
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181881383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.181881383
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.3829389497
Short name T643
Test name
Test status
Simulation time 4679865943 ps
CPU time 21.44 seconds
Started Jun 04 02:13:53 PM PDT 24
Finished Jun 04 02:14:16 PM PDT 24
Peak memory 218556 kb
Host smart-5330b420-703c-40c5-a007-36b6c9b63040
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829389497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.3829389497
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.2664628011
Short name T334
Test name
Test status
Simulation time 1119108105 ps
CPU time 2.63 seconds
Started Jun 04 02:13:53 PM PDT 24
Finished Jun 04 02:13:57 PM PDT 24
Peak memory 217116 kb
Host smart-314c5c96-a5b2-4efd-acd0-79955e0e4725
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664628011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.2
664628011
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.3287075606
Short name T721
Test name
Test status
Simulation time 258792685 ps
CPU time 8.15 seconds
Started Jun 04 02:13:55 PM PDT 24
Finished Jun 04 02:14:04 PM PDT 24
Peak memory 217948 kb
Host smart-f07387ea-3f2a-45f5-9d12-9362616dd8d1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287075606 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.3287075606
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3365400337
Short name T24
Test name
Test status
Simulation time 889072157 ps
CPU time 28.21 seconds
Started Jun 04 02:14:01 PM PDT 24
Finished Jun 04 02:14:30 PM PDT 24
Peak memory 217640 kb
Host smart-cbb28953-5297-4d03-a2c7-4798760a1a00
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365400337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3365400337
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1420778449
Short name T554
Test name
Test status
Simulation time 1108577314 ps
CPU time 10.69 seconds
Started Jun 04 02:13:53 PM PDT 24
Finished Jun 04 02:14:05 PM PDT 24
Peak memory 217624 kb
Host smart-fadf7f0e-f0c8-483f-9e4d-fb77e4f6b2a9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420778449 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1420778449
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.3485317998
Short name T101
Test name
Test status
Simulation time 2230247211 ps
CPU time 74.27 seconds
Started Jun 04 02:13:55 PM PDT 24
Finished Jun 04 02:15:10 PM PDT 24
Peak memory 277508 kb
Host smart-fb8c463b-dade-4376-8591-a5eac06792d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485317998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.3485317998
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.941663802
Short name T710
Test name
Test status
Simulation time 600485340 ps
CPU time 14.92 seconds
Started Jun 04 02:13:53 PM PDT 24
Finished Jun 04 02:14:09 PM PDT 24
Peak memory 250828 kb
Host smart-076c63cd-4480-419f-9908-71f18c7fb040
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941663802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_j
tag_state_post_trans.941663802
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.1165142427
Short name T794
Test name
Test status
Simulation time 337250641 ps
CPU time 3.25 seconds
Started Jun 04 02:13:53 PM PDT 24
Finished Jun 04 02:13:57 PM PDT 24
Peak memory 218000 kb
Host smart-249851ec-70e1-4a4b-b1d8-07de2be00487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165142427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.1165142427
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.665482611
Short name T819
Test name
Test status
Simulation time 975426409 ps
CPU time 8.74 seconds
Started Jun 04 02:13:53 PM PDT 24
Finished Jun 04 02:14:02 PM PDT 24
Peak memory 217692 kb
Host smart-826147aa-1986-4dcf-bc89-84ffd867b6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665482611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.665482611
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2629156189
Short name T534
Test name
Test status
Simulation time 623905016 ps
CPU time 10.49 seconds
Started Jun 04 02:14:06 PM PDT 24
Finished Jun 04 02:14:17 PM PDT 24
Peak memory 218940 kb
Host smart-a168f87c-ec2d-4c09-95c0-47bf9a530596
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629156189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2629156189
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3886759491
Short name T432
Test name
Test status
Simulation time 797800270 ps
CPU time 15.58 seconds
Started Jun 04 02:14:03 PM PDT 24
Finished Jun 04 02:14:20 PM PDT 24
Peak memory 226008 kb
Host smart-0acd9640-ce01-4064-951c-4acb398ae222
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886759491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3886759491
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.1152166171
Short name T331
Test name
Test status
Simulation time 3060170140 ps
CPU time 17.71 seconds
Started Jun 04 02:14:00 PM PDT 24
Finished Jun 04 02:14:19 PM PDT 24
Peak memory 217976 kb
Host smart-7989bf49-9f06-4c04-ada0-51b3ebeb034b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152166171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.1
152166171
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1874155753
Short name T464
Test name
Test status
Simulation time 1392211111 ps
CPU time 8.74 seconds
Started Jun 04 02:13:53 PM PDT 24
Finished Jun 04 02:14:03 PM PDT 24
Peak memory 218124 kb
Host smart-d897f863-a44c-4fc9-a1b0-b322acab329f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874155753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1874155753
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.473290405
Short name T627
Test name
Test status
Simulation time 24613459 ps
CPU time 1.38 seconds
Started Jun 04 02:13:46 PM PDT 24
Finished Jun 04 02:13:48 PM PDT 24
Peak memory 213388 kb
Host smart-d86b5e10-cf40-4e4a-95bf-403693c1278f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473290405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.473290405
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.4157285797
Short name T685
Test name
Test status
Simulation time 847007156 ps
CPU time 21.74 seconds
Started Jun 04 02:13:53 PM PDT 24
Finished Jun 04 02:14:15 PM PDT 24
Peak memory 250884 kb
Host smart-3befc656-970d-48dd-98ac-16da7a5443d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4157285797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.4157285797
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.3680419751
Short name T3
Test name
Test status
Simulation time 123705331 ps
CPU time 6.99 seconds
Started Jun 04 02:13:53 PM PDT 24
Finished Jun 04 02:14:01 PM PDT 24
Peak memory 250392 kb
Host smart-7240209c-3b03-4910-9406-daf14644beae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680419751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.3680419751
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.2269572467
Short name T169
Test name
Test status
Simulation time 23821915735 ps
CPU time 123.96 seconds
Started Jun 04 02:14:01 PM PDT 24
Finished Jun 04 02:16:06 PM PDT 24
Peak memory 253924 kb
Host smart-0667c4e8-6edd-48d2-a4b4-e14b39dd3590
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269572467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.2269572467
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2837698525
Short name T250
Test name
Test status
Simulation time 12657706 ps
CPU time 1.08 seconds
Started Jun 04 02:13:50 PM PDT 24
Finished Jun 04 02:13:52 PM PDT 24
Peak memory 211548 kb
Host smart-793f8ba1-9b20-4a0c-bb8f-e95e7463b07b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837698525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2837698525
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.656246909
Short name T492
Test name
Test status
Simulation time 22842352 ps
CPU time 1.25 seconds
Started Jun 04 02:14:20 PM PDT 24
Finished Jun 04 02:14:22 PM PDT 24
Peak memory 208716 kb
Host smart-c2a67936-38ac-475f-9545-a3cb51b30434
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656246909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.656246909
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3911044192
Short name T72
Test name
Test status
Simulation time 108835716 ps
CPU time 0.81 seconds
Started Jun 04 02:14:09 PM PDT 24
Finished Jun 04 02:14:11 PM PDT 24
Peak memory 208480 kb
Host smart-93650e52-70f7-48d2-a954-ec090b39ce38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911044192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3911044192
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.2670495637
Short name T836
Test name
Test status
Simulation time 2499583563 ps
CPU time 17.63 seconds
Started Jun 04 02:14:12 PM PDT 24
Finished Jun 04 02:14:31 PM PDT 24
Peak memory 217976 kb
Host smart-1a92d767-6496-4773-b451-6d0a1689976a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670495637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.2670495637
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.356512087
Short name T804
Test name
Test status
Simulation time 219626548 ps
CPU time 6.25 seconds
Started Jun 04 02:14:10 PM PDT 24
Finished Jun 04 02:14:18 PM PDT 24
Peak memory 217044 kb
Host smart-4670b47e-ad58-403b-b423-0e9c025f4727
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356512087 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.356512087
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.2698434889
Short name T14
Test name
Test status
Simulation time 1153560085 ps
CPU time 25.26 seconds
Started Jun 04 02:14:09 PM PDT 24
Finished Jun 04 02:14:36 PM PDT 24
Peak memory 217996 kb
Host smart-61f2d749-fa01-42a2-be57-0b2b066545b9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698434889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.2698434889
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.2227128651
Short name T816
Test name
Test status
Simulation time 5274344643 ps
CPU time 4.74 seconds
Started Jun 04 02:14:10 PM PDT 24
Finished Jun 04 02:14:15 PM PDT 24
Peak memory 217588 kb
Host smart-16e79a25-9166-4081-9ce8-0995bc1ee129
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227128651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.2
227128651
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.655941668
Short name T545
Test name
Test status
Simulation time 75899789 ps
CPU time 1.95 seconds
Started Jun 04 02:14:09 PM PDT 24
Finished Jun 04 02:14:12 PM PDT 24
Peak memory 218020 kb
Host smart-36e3af37-a0ea-454d-9efa-a493ab8c2bcd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655941668 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
prog_failure.655941668
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3010253056
Short name T655
Test name
Test status
Simulation time 2732412341 ps
CPU time 34.39 seconds
Started Jun 04 02:14:10 PM PDT 24
Finished Jun 04 02:14:45 PM PDT 24
Peak memory 217652 kb
Host smart-f552a6b5-ce90-4ce7-a516-6cbe2b2d2f51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010253056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.3010253056
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3426413636
Short name T188
Test name
Test status
Simulation time 1257928283 ps
CPU time 2.39 seconds
Started Jun 04 02:14:09 PM PDT 24
Finished Jun 04 02:14:12 PM PDT 24
Peak memory 217644 kb
Host smart-d23a3794-ca88-4c36-836c-0dee9c0dd8c5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426413636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3426413636
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.31101667
Short name T670
Test name
Test status
Simulation time 5286541023 ps
CPU time 33.76 seconds
Started Jun 04 02:14:10 PM PDT 24
Finished Jun 04 02:14:44 PM PDT 24
Peak memory 251860 kb
Host smart-1b78689f-f70b-4315-b615-b8476a12bcab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31101667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_
state_failure.31101667
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.3180658081
Short name T557
Test name
Test status
Simulation time 540154409 ps
CPU time 10.51 seconds
Started Jun 04 02:14:08 PM PDT 24
Finished Jun 04 02:14:19 PM PDT 24
Peak memory 247464 kb
Host smart-910a5d1c-aa36-412d-9bb9-d60a60bd36b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180658081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.3180658081
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3938755891
Short name T625
Test name
Test status
Simulation time 1102976390 ps
CPU time 2.82 seconds
Started Jun 04 02:14:00 PM PDT 24
Finished Jun 04 02:14:04 PM PDT 24
Peak memory 218020 kb
Host smart-d0d90d46-293f-408e-98bb-d781e9f6ddbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938755891 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3938755891
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.2431205570
Short name T656
Test name
Test status
Simulation time 892331107 ps
CPU time 5.97 seconds
Started Jun 04 02:14:09 PM PDT 24
Finished Jun 04 02:14:16 PM PDT 24
Peak memory 217732 kb
Host smart-5ebdec66-97f5-467b-94f6-32bca0ecc226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431205570 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.2431205570
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.4134023913
Short name T525
Test name
Test status
Simulation time 3768382802 ps
CPU time 16.31 seconds
Started Jun 04 02:14:12 PM PDT 24
Finished Jun 04 02:14:29 PM PDT 24
Peak memory 219268 kb
Host smart-775c3f20-53ed-4c83-9f1f-800c23b06688
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134023913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.4134023913
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.2362600832
Short name T852
Test name
Test status
Simulation time 390364175 ps
CPU time 10.44 seconds
Started Jun 04 02:14:08 PM PDT 24
Finished Jun 04 02:14:19 PM PDT 24
Peak memory 225992 kb
Host smart-e9a2389d-7d44-4b48-bf5a-70d29eef2f64
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362600832 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.2362600832
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.3907478410
Short name T190
Test name
Test status
Simulation time 1463180505 ps
CPU time 10.55 seconds
Started Jun 04 02:14:09 PM PDT 24
Finished Jun 04 02:14:20 PM PDT 24
Peak memory 217960 kb
Host smart-2cc2525a-5720-4586-84be-2a13445e5554
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907478410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.3
907478410
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2004303398
Short name T269
Test name
Test status
Simulation time 549442304 ps
CPU time 8.37 seconds
Started Jun 04 02:14:11 PM PDT 24
Finished Jun 04 02:14:21 PM PDT 24
Peak memory 224996 kb
Host smart-dd5cbf10-e56c-41c9-a4da-bf4f8eff31f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004303398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2004303398
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.131877922
Short name T612
Test name
Test status
Simulation time 123162695 ps
CPU time 3.86 seconds
Started Jun 04 02:14:03 PM PDT 24
Finished Jun 04 02:14:07 PM PDT 24
Peak memory 217692 kb
Host smart-c4f86dec-09a8-4be8-a03e-543b0e5e524b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131877922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.131877922
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.2626001747
Short name T240
Test name
Test status
Simulation time 777749314 ps
CPU time 27.35 seconds
Started Jun 04 02:14:02 PM PDT 24
Finished Jun 04 02:14:30 PM PDT 24
Peak memory 250984 kb
Host smart-54c39786-4b76-437c-83e6-9e677c026cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626001747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.2626001747
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2680134992
Short name T436
Test name
Test status
Simulation time 395042244 ps
CPU time 6.89 seconds
Started Jun 04 02:14:00 PM PDT 24
Finished Jun 04 02:14:08 PM PDT 24
Peak memory 250476 kb
Host smart-77f2c527-e627-430c-bb07-fbd1aaef3c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680134992 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2680134992
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.688122386
Short name T730
Test name
Test status
Simulation time 19999338798 ps
CPU time 298.9 seconds
Started Jun 04 02:14:10 PM PDT 24
Finished Jun 04 02:19:10 PM PDT 24
Peak memory 250988 kb
Host smart-99218291-29c0-4629-8da7-aaa2070db5eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688122386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.688122386
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3418378208
Short name T746
Test name
Test status
Simulation time 22781063 ps
CPU time 0.97 seconds
Started Jun 04 02:14:00 PM PDT 24
Finished Jun 04 02:14:02 PM PDT 24
Peak memory 211372 kb
Host smart-2163b80a-fa7c-4b12-992e-97d8f7cd2ab6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418378208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3418378208
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.2863106995
Short name T374
Test name
Test status
Simulation time 41438938 ps
CPU time 0.94 seconds
Started Jun 04 02:14:26 PM PDT 24
Finished Jun 04 02:14:27 PM PDT 24
Peak memory 209544 kb
Host smart-946e47f8-1e23-4e9c-aeb0-cef426f0e125
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863106995 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.2863106995
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3750407997
Short name T373
Test name
Test status
Simulation time 36699174 ps
CPU time 0.82 seconds
Started Jun 04 02:14:18 PM PDT 24
Finished Jun 04 02:14:19 PM PDT 24
Peak memory 208632 kb
Host smart-fc38a37e-93ac-43aa-9438-bab5e0142a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750407997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3750407997
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.898343420
Short name T788
Test name
Test status
Simulation time 2324215175 ps
CPU time 10.48 seconds
Started Jun 04 02:14:25 PM PDT 24
Finished Jun 04 02:14:36 PM PDT 24
Peak memory 217484 kb
Host smart-24096c21-10ed-4e63-832f-f52fe5d27a6e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898343420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.898343420
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3836555479
Short name T22
Test name
Test status
Simulation time 2984628833 ps
CPU time 74.38 seconds
Started Jun 04 02:14:27 PM PDT 24
Finished Jun 04 02:15:42 PM PDT 24
Peak memory 218936 kb
Host smart-9fc07b83-c4ce-4ac4-ac37-c3b733b2ec5d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836555479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3836555479
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.2260801962
Short name T97
Test name
Test status
Simulation time 349932557 ps
CPU time 3.09 seconds
Started Jun 04 02:14:24 PM PDT 24
Finished Jun 04 02:14:28 PM PDT 24
Peak memory 216964 kb
Host smart-76124ada-0713-4ed7-99f2-3be0895ee716
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260801962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.2
260801962
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2637267817
Short name T504
Test name
Test status
Simulation time 2824010339 ps
CPU time 7.33 seconds
Started Jun 04 02:14:17 PM PDT 24
Finished Jun 04 02:14:25 PM PDT 24
Peak memory 217972 kb
Host smart-08e69510-27db-428b-8968-b80532a66019
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637267817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2637267817
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.736499801
Short name T690
Test name
Test status
Simulation time 1282975381 ps
CPU time 15.84 seconds
Started Jun 04 02:14:24 PM PDT 24
Finished Jun 04 02:14:41 PM PDT 24
Peak memory 217592 kb
Host smart-17863ffe-9987-4fc6-9ad0-c2e15901d748
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736499801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_j
tag_regwen_during_op.736499801
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.209845160
Short name T444
Test name
Test status
Simulation time 364122416 ps
CPU time 5.98 seconds
Started Jun 04 02:14:17 PM PDT 24
Finished Jun 04 02:14:24 PM PDT 24
Peak memory 217616 kb
Host smart-fa21e1f6-a212-4f09-9d1d-511755460af9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209845160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.209845160
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.4149601536
Short name T585
Test name
Test status
Simulation time 1268900437 ps
CPU time 34.96 seconds
Started Jun 04 02:14:17 PM PDT 24
Finished Jun 04 02:14:53 PM PDT 24
Peak memory 251424 kb
Host smart-633d8a5a-79d0-4395-bb96-e0297c114a3d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149601536 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.4149601536
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2768677784
Short name T392
Test name
Test status
Simulation time 1246590200 ps
CPU time 11.43 seconds
Started Jun 04 02:14:19 PM PDT 24
Finished Jun 04 02:14:31 PM PDT 24
Peak memory 250836 kb
Host smart-fb7fecc1-4eda-40de-b260-9bfbf6934ae4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768677784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2768677784
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.4250187973
Short name T729
Test name
Test status
Simulation time 366718716 ps
CPU time 3.42 seconds
Started Jun 04 02:14:18 PM PDT 24
Finished Jun 04 02:14:22 PM PDT 24
Peak memory 218008 kb
Host smart-c3eaba58-0624-4403-964a-b660eb6e689a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250187973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.4250187973
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.4220057683
Short name T470
Test name
Test status
Simulation time 3759542081 ps
CPU time 18 seconds
Started Jun 04 02:14:16 PM PDT 24
Finished Jun 04 02:14:34 PM PDT 24
Peak memory 215012 kb
Host smart-ecdade0f-65bc-4b37-96bb-416f2cc13342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220057683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.4220057683
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2923920851
Short name T307
Test name
Test status
Simulation time 6133349208 ps
CPU time 13.77 seconds
Started Jun 04 02:14:25 PM PDT 24
Finished Jun 04 02:14:40 PM PDT 24
Peak memory 220084 kb
Host smart-e415a436-fbef-48a7-8a0d-af4fc01c2b4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923920851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2923920851
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.3200651951
Short name T735
Test name
Test status
Simulation time 283900986 ps
CPU time 8.05 seconds
Started Jun 04 02:14:24 PM PDT 24
Finished Jun 04 02:14:32 PM PDT 24
Peak memory 226008 kb
Host smart-e9a608d9-894e-48a7-ab87-27e0789da57c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200651951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.3200651951
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.3624472639
Short name T661
Test name
Test status
Simulation time 890587371 ps
CPU time 9.35 seconds
Started Jun 04 02:14:25 PM PDT 24
Finished Jun 04 02:14:35 PM PDT 24
Peak memory 218004 kb
Host smart-b1cea70d-99ff-478a-b4da-d82a6a786cbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624472639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.3
624472639
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2464884923
Short name T103
Test name
Test status
Simulation time 273457914 ps
CPU time 11.31 seconds
Started Jun 04 02:14:18 PM PDT 24
Finished Jun 04 02:14:30 PM PDT 24
Peak memory 225020 kb
Host smart-85055505-63a6-4cc6-a151-2b0c454c84d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464884923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2464884923
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.4292641465
Short name T654
Test name
Test status
Simulation time 220727564 ps
CPU time 2.44 seconds
Started Jun 04 02:14:18 PM PDT 24
Finished Jun 04 02:14:21 PM PDT 24
Peak memory 214332 kb
Host smart-191be855-6dc0-4f3f-9c83-772363dc1f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292641465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.4292641465
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.3719655949
Short name T711
Test name
Test status
Simulation time 1467880993 ps
CPU time 32.04 seconds
Started Jun 04 02:14:16 PM PDT 24
Finished Jun 04 02:14:49 PM PDT 24
Peak memory 250956 kb
Host smart-a329ac5b-7f04-4b31-89d4-d53bdbd9d020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719655949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.3719655949
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3470367046
Short name T318
Test name
Test status
Simulation time 1109344805 ps
CPU time 6.86 seconds
Started Jun 04 02:14:16 PM PDT 24
Finished Jun 04 02:14:24 PM PDT 24
Peak memory 250428 kb
Host smart-d66e5b34-c7d4-40ac-9e41-485044da3862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470367046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3470367046
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.701336901
Short name T517
Test name
Test status
Simulation time 14988959274 ps
CPU time 144.56 seconds
Started Jun 04 02:14:24 PM PDT 24
Finished Jun 04 02:16:49 PM PDT 24
Peak memory 281356 kb
Host smart-1b30d43a-c6b3-43a7-b8cd-005c112267a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701336901 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.lc_ctrl_stress_all.701336901
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.4280077559
Short name T324
Test name
Test status
Simulation time 22753328 ps
CPU time 1.03 seconds
Started Jun 04 02:14:19 PM PDT 24
Finished Jun 04 02:14:21 PM PDT 24
Peak memory 211440 kb
Host smart-fcef1045-7b5a-4754-8ccb-630c59c4e866
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280077559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.4280077559
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.2204859571
Short name T559
Test name
Test status
Simulation time 34965251 ps
CPU time 1.18 seconds
Started Jun 04 02:14:40 PM PDT 24
Finished Jun 04 02:14:42 PM PDT 24
Peak memory 208688 kb
Host smart-b77fc753-5535-4acb-a5fc-99d1a6d91481
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204859571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.2204859571
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2573285543
Short name T768
Test name
Test status
Simulation time 28983697 ps
CPU time 0.87 seconds
Started Jun 04 02:14:33 PM PDT 24
Finished Jun 04 02:14:35 PM PDT 24
Peak memory 208564 kb
Host smart-25f16193-ccbf-49e0-9a08-99afb1fd16fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573285543 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2573285543
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.2989785645
Short name T498
Test name
Test status
Simulation time 201478998 ps
CPU time 5.89 seconds
Started Jun 04 02:14:33 PM PDT 24
Finished Jun 04 02:14:39 PM PDT 24
Peak memory 209500 kb
Host smart-0e3ef370-0c52-4086-9a26-fc0d44969e48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989785645 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.2989785645
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.1017374106
Short name T705
Test name
Test status
Simulation time 2761185576 ps
CPU time 22.75 seconds
Started Jun 04 02:14:33 PM PDT 24
Finished Jun 04 02:14:56 PM PDT 24
Peak memory 218868 kb
Host smart-72dafca5-5219-4c04-85cd-b05ea26af977
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017374106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.1017374106
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.3984421382
Short name T372
Test name
Test status
Simulation time 663059505 ps
CPU time 3.62 seconds
Started Jun 04 02:14:32 PM PDT 24
Finished Jun 04 02:14:36 PM PDT 24
Peak memory 217212 kb
Host smart-f91caae6-030c-4942-b163-06f8833a70d6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984421382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.3
984421382
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.529549579
Short name T576
Test name
Test status
Simulation time 227844527 ps
CPU time 2.58 seconds
Started Jun 04 02:14:35 PM PDT 24
Finished Jun 04 02:14:38 PM PDT 24
Peak memory 217992 kb
Host smart-9982b51b-c84a-449a-8d0e-db8d81af9670
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529549579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_
prog_failure.529549579
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3253530471
Short name T355
Test name
Test status
Simulation time 3784294849 ps
CPU time 17.79 seconds
Started Jun 04 02:14:34 PM PDT 24
Finished Jun 04 02:14:52 PM PDT 24
Peak memory 217800 kb
Host smart-b0cd5f05-59f8-4af1-914e-a2ed26e92db7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253530471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3253530471
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.3958773234
Short name T80
Test name
Test status
Simulation time 2114008287 ps
CPU time 11.06 seconds
Started Jun 04 02:14:32 PM PDT 24
Finished Jun 04 02:14:44 PM PDT 24
Peak memory 217596 kb
Host smart-66d68f11-24cc-4012-a2c9-6b0d043fe340
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958773234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
3958773234
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.201478139
Short name T234
Test name
Test status
Simulation time 7303969214 ps
CPU time 66.63 seconds
Started Jun 04 02:14:33 PM PDT 24
Finished Jun 04 02:15:40 PM PDT 24
Peak memory 254480 kb
Host smart-11476fc8-7022-4269-a8fd-ffa231ea2303
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201478139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_state_failure.201478139
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.4102309999
Short name T448
Test name
Test status
Simulation time 1513782196 ps
CPU time 17.16 seconds
Started Jun 04 02:14:33 PM PDT 24
Finished Jun 04 02:14:51 PM PDT 24
Peak memory 250800 kb
Host smart-6294a9b4-b3c0-4bf8-bfdf-3abb8e7df27c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102309999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.4102309999
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.1451234930
Short name T638
Test name
Test status
Simulation time 143478799 ps
CPU time 2.54 seconds
Started Jun 04 02:14:24 PM PDT 24
Finished Jun 04 02:14:27 PM PDT 24
Peak memory 218072 kb
Host smart-91d0f7bb-7f1e-4211-aa90-6c9ffd937b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451234930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.1451234930
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3159225527
Short name T403
Test name
Test status
Simulation time 1439955134 ps
CPU time 11.51 seconds
Started Jun 04 02:14:33 PM PDT 24
Finished Jun 04 02:14:45 PM PDT 24
Peak memory 217676 kb
Host smart-50cf2625-a445-42e4-8142-ba8011d6ec22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159225527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3159225527
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3283668922
Short name T425
Test name
Test status
Simulation time 5142760442 ps
CPU time 21.14 seconds
Started Jun 04 02:14:32 PM PDT 24
Finished Jun 04 02:14:54 PM PDT 24
Peak memory 220064 kb
Host smart-a4aa8355-dc9f-41c6-9637-720de33bae24
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283668922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3283668922
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.2165539047
Short name T499
Test name
Test status
Simulation time 725562574 ps
CPU time 9.13 seconds
Started Jun 04 02:14:39 PM PDT 24
Finished Jun 04 02:14:49 PM PDT 24
Peak memory 217912 kb
Host smart-589c4315-9f47-45ee-bf69-c7e39211c4d8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165539047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.2165539047
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.4065654810
Short name T823
Test name
Test status
Simulation time 409230839 ps
CPU time 6.47 seconds
Started Jun 04 02:14:43 PM PDT 24
Finished Jun 04 02:14:49 PM PDT 24
Peak memory 217900 kb
Host smart-f337a8b2-2352-4bce-976e-a0c6e6c0f535
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065654810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.4
065654810
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.468583932
Short name T529
Test name
Test status
Simulation time 506228823 ps
CPU time 16.38 seconds
Started Jun 04 02:14:34 PM PDT 24
Finished Jun 04 02:14:51 PM PDT 24
Peak memory 218068 kb
Host smart-6846e602-2eb6-41ff-9e32-db9257b387b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468583932 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.468583932
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.300195259
Short name T248
Test name
Test status
Simulation time 120924951 ps
CPU time 8.39 seconds
Started Jun 04 02:14:25 PM PDT 24
Finished Jun 04 02:14:34 PM PDT 24
Peak memory 218204 kb
Host smart-ccb1d20d-440b-4494-8907-2306d6d915b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300195259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.300195259
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2011542925
Short name T364
Test name
Test status
Simulation time 191428602 ps
CPU time 21.81 seconds
Started Jun 04 02:14:25 PM PDT 24
Finished Jun 04 02:14:47 PM PDT 24
Peak memory 250908 kb
Host smart-a79fd149-9d09-4c5e-af18-14491ad2830b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011542925 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2011542925
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.2350299181
Short name T712
Test name
Test status
Simulation time 71098675 ps
CPU time 8.38 seconds
Started Jun 04 02:14:24 PM PDT 24
Finished Jun 04 02:14:33 PM PDT 24
Peak memory 251000 kb
Host smart-0d3b302b-3ed0-499a-bbcc-5ccd66bd3e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350299181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.2350299181
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.1713743819
Short name T340
Test name
Test status
Simulation time 2527790743 ps
CPU time 79.18 seconds
Started Jun 04 02:14:40 PM PDT 24
Finished Jun 04 02:16:00 PM PDT 24
Peak memory 268988 kb
Host smart-7ff4c6cb-2321-4c83-a4ad-4cb6b6a2fb76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713743819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.1713743819
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3755036359
Short name T235
Test name
Test status
Simulation time 66204354 ps
CPU time 0.93 seconds
Started Jun 04 02:14:25 PM PDT 24
Finished Jun 04 02:14:26 PM PDT 24
Peak memory 211448 kb
Host smart-e3f984f3-e767-4100-889d-6951761a221c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755036359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3755036359
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.2590754168
Short name T102
Test name
Test status
Simulation time 30276385 ps
CPU time 1.4 seconds
Started Jun 04 02:14:50 PM PDT 24
Finished Jun 04 02:14:51 PM PDT 24
Peak memory 208812 kb
Host smart-5eb07969-01cb-469a-945c-c394e271d166
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590754168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.2590754168
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.3703841014
Short name T767
Test name
Test status
Simulation time 55176812 ps
CPU time 0.88 seconds
Started Jun 04 02:14:42 PM PDT 24
Finished Jun 04 02:14:43 PM PDT 24
Peak memory 208660 kb
Host smart-c26daa0f-66c0-4f1d-90bf-34ce5e792fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703841014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.3703841014
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.3032313272
Short name T751
Test name
Test status
Simulation time 867339270 ps
CPU time 12.8 seconds
Started Jun 04 02:14:41 PM PDT 24
Finished Jun 04 02:14:54 PM PDT 24
Peak memory 218004 kb
Host smart-de312c55-ef53-45c3-8f6f-966fa775911f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032313272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.3032313272
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.2427833370
Short name T66
Test name
Test status
Simulation time 129392820 ps
CPU time 2.11 seconds
Started Jun 04 02:14:43 PM PDT 24
Finished Jun 04 02:14:46 PM PDT 24
Peak memory 209508 kb
Host smart-7e461522-d056-42ec-8476-4eaf4f93056d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427833370 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2427833370
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.351896268
Short name T490
Test name
Test status
Simulation time 1020481625 ps
CPU time 35.1 seconds
Started Jun 04 02:14:40 PM PDT 24
Finished Jun 04 02:15:16 PM PDT 24
Peak memory 217944 kb
Host smart-89b08801-a03e-4314-b972-650b73a04da7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351896268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_err
ors.351896268
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.4209958655
Short name T546
Test name
Test status
Simulation time 917831363 ps
CPU time 5.53 seconds
Started Jun 04 02:14:49 PM PDT 24
Finished Jun 04 02:14:55 PM PDT 24
Peak memory 217160 kb
Host smart-9b9c2882-31e6-4cea-81f1-24b0ffdeac1c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209958655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.4
209958655
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.3242465330
Short name T443
Test name
Test status
Simulation time 261014522 ps
CPU time 5.86 seconds
Started Jun 04 02:14:39 PM PDT 24
Finished Jun 04 02:14:45 PM PDT 24
Peak memory 217868 kb
Host smart-88645d4a-84e3-4ff1-b221-956c407da736
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242465330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.3242465330
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2605226067
Short name T304
Test name
Test status
Simulation time 2262274687 ps
CPU time 14.25 seconds
Started Jun 04 02:14:53 PM PDT 24
Finished Jun 04 02:15:08 PM PDT 24
Peak memory 217800 kb
Host smart-551528c0-98bb-4a0a-8c13-53a56bc7c6a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605226067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2605226067
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.2115705324
Short name T174
Test name
Test status
Simulation time 282743632 ps
CPU time 5.58 seconds
Started Jun 04 02:14:41 PM PDT 24
Finished Jun 04 02:14:47 PM PDT 24
Peak memory 217628 kb
Host smart-6a7c3dd8-872a-48a9-bfa1-cbac21e1d5dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115705324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
2115705324
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.1902386629
Short name T159
Test name
Test status
Simulation time 1547024791 ps
CPU time 63.1 seconds
Started Jun 04 02:14:40 PM PDT 24
Finished Jun 04 02:15:43 PM PDT 24
Peak memory 267260 kb
Host smart-b73dcb77-b919-4c72-970f-270163e5e4a0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902386629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.1902386629
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.2248168813
Short name T765
Test name
Test status
Simulation time 1863206804 ps
CPU time 15.87 seconds
Started Jun 04 02:14:43 PM PDT 24
Finished Jun 04 02:15:00 PM PDT 24
Peak memory 250848 kb
Host smart-dbc4aaf5-a3f3-4723-9372-d4bcc2cf12b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248168813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.2248168813
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1191385238
Short name T236
Test name
Test status
Simulation time 119245573 ps
CPU time 2.35 seconds
Started Jun 04 02:14:43 PM PDT 24
Finished Jun 04 02:14:46 PM PDT 24
Peak memory 218000 kb
Host smart-4e1220c5-dc2f-4dd6-8e63-d31107e6b84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191385238 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1191385238
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1555938689
Short name T404
Test name
Test status
Simulation time 405890312 ps
CPU time 15.43 seconds
Started Jun 04 02:14:41 PM PDT 24
Finished Jun 04 02:14:57 PM PDT 24
Peak memory 217696 kb
Host smart-148bf1e2-08e6-4463-9470-9a60e18410b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555938689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1555938689
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.2986282537
Short name T345
Test name
Test status
Simulation time 419111352 ps
CPU time 17.95 seconds
Started Jun 04 02:14:49 PM PDT 24
Finished Jun 04 02:15:08 PM PDT 24
Peak memory 218896 kb
Host smart-5444a31d-50bc-41c5-9d67-2b682fa9a4d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986282537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.2986282537
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2954187418
Short name T495
Test name
Test status
Simulation time 279870685 ps
CPU time 12.77 seconds
Started Jun 04 02:14:49 PM PDT 24
Finished Jun 04 02:15:02 PM PDT 24
Peak memory 226012 kb
Host smart-599176f0-c9f8-4a96-9962-ceb6ecdef16b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954187418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2954187418
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2962231744
Short name T165
Test name
Test status
Simulation time 1398622142 ps
CPU time 23.21 seconds
Started Jun 04 02:14:49 PM PDT 24
Finished Jun 04 02:15:13 PM PDT 24
Peak memory 217924 kb
Host smart-06ac14e8-4a50-487b-b0cc-c175e919d5e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962231744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
962231744
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1201337771
Short name T20
Test name
Test status
Simulation time 1033632937 ps
CPU time 10.64 seconds
Started Jun 04 02:14:39 PM PDT 24
Finished Jun 04 02:14:50 PM PDT 24
Peak memory 225504 kb
Host smart-ea9c46dc-615f-4477-a9a5-970542ec06d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201337771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1201337771
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.589752613
Short name T87
Test name
Test status
Simulation time 440347571 ps
CPU time 3.26 seconds
Started Jun 04 02:14:40 PM PDT 24
Finished Jun 04 02:14:44 PM PDT 24
Peak memory 217692 kb
Host smart-3ddd5004-0d2f-431f-8c92-01118f9c7e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589752613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.589752613
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.3647685801
Short name T344
Test name
Test status
Simulation time 256003409 ps
CPU time 28.08 seconds
Started Jun 04 02:14:39 PM PDT 24
Finished Jun 04 02:15:08 PM PDT 24
Peak memory 250940 kb
Host smart-5695efa2-9a27-4c8b-bd00-4c0f74d85294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647685801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.3647685801
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1621802834
Short name T406
Test name
Test status
Simulation time 230675085 ps
CPU time 3.33 seconds
Started Jun 04 02:14:44 PM PDT 24
Finished Jun 04 02:14:48 PM PDT 24
Peak memory 222204 kb
Host smart-21e6c77c-c410-490d-8b80-0d3dd2f78a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621802834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1621802834
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.3084416576
Short name T790
Test name
Test status
Simulation time 37814494097 ps
CPU time 98.91 seconds
Started Jun 04 02:14:48 PM PDT 24
Finished Jun 04 02:16:27 PM PDT 24
Peak memory 276508 kb
Host smart-de1a70c7-7492-4be0-ab22-40f3795bbfe9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084416576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.3084416576
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.2123279161
Short name T402
Test name
Test status
Simulation time 25180584 ps
CPU time 1.01 seconds
Started Jun 04 02:14:41 PM PDT 24
Finished Jun 04 02:14:43 PM PDT 24
Peak memory 211596 kb
Host smart-c71a3773-f2d1-451c-94c4-67631f07966e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123279161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.2123279161
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
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