Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96409462

1

T1

35653

T2

30487

T3

203070

auto[1]

1379166

1

T1

1683

T3

18953

T8

1584

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

96413323

1

T1

35653

T2

30487

T3

203216

auto[1]

1375305

1

T1

1683

T3

17493

T7

99

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7035683	1			T1	7680		T2	7354		T3	109897
auto[IdleSt]	21538246	1			T1	7661		T2	6711		T3	302638
auto[ClkMuxSt]	33192	1			T1	69		T2	80		T3	531
auto[CntIncrSt]	32994	1			T1	69		T2	80		T3	531
auto[CntProgSt]	1599452	1			T1	122		T2	402		T3	25527
auto[TransCheckSt]	26032	1			T1	53		T2	80		T3	396
auto[TokenHashSt]	36202790	1			T1	2461		T2	1694		T3	107046
auto[FlashRmaSt]	26203	1			T1	147		T3	305		T8	59
auto[TokenCheck0St]	11789	1			T1	43		T3	167		T8	50
auto[TokenCheck1St]	8673	1			T1	30		T3	124		T8	32
auto[TransProgSt]	417022	1			T1	53		T3	6972		T8	15235
auto[PostTransSt]	12486544	1			T1	11114		T2	14086		T3	240932
auto[ScrapSt]	166891	1			T3	474		T9	26		T19	453
auto[EscalateSt]	6642296	1			T1	4746		T3	99435		T7	153
auto[InvalidSt]	11558781	1			T1	3088		T3	191219		T8	2571

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	2040	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	11558781	1			T1	3088		T3	191219		T8	2571
EscalateSt	6642296	1			T1	4746		T3	99435		T7	153
ScrapSt	166891	1			T3	474		T9	26		T19	453
PostTransSt	12486544	1			T1	11114		T2	14086		T3	240932
TransProgSt	417022	1			T1	53		T3	6972		T8	15235
TokenCheck1St	8673	1			T1	30		T3	124		T8	32
TokenCheck0St	11789	1			T1	43		T3	167		T8	50
FlashRmaSt	26203	1			T1	147		T3	305		T8	59
TokenHashSt	36202790	1			T1	2461		T2	1694		T3	107046
TransCheckSt	26032	1			T1	53		T2	80		T3	396
CntProgSt	1599452	1			T1	122		T2	402		T3	25527
CntIncrSt	32994	1			T1	69		T2	80		T3	531
ClkMuxSt	33192	1			T1	69		T2	80		T3	531
IdleSt	21538246	1			T1	7661		T2	6711		T3	302638
ResetSt	7035683	1			T1	7680		T2	7354		T3	109897
arcs[ResetSt=>IdleSt]	51937	1			T1	88		T2	81		T3	878
arcs[IdleSt=>ScrapSt]	261	1			T3	3		T9	1		T19	1
arcs[IdleSt=>ClkMuxSt]	33054	1			T1	69		T2	80		T3	531
arcs[ClkMuxSt=>CntIncrSt]	32994	1			T1	69		T2	80		T3	531
arcs[CntIncrSt=>PostTransSt]	1696	1			T3	53		T12	6		T13	12
arcs[CntIncrSt=>CntProgSt]	31235	1			T1	69		T2	80		T3	478
arcs[CntProgSt=>PostTransSt]	4147	1			T1	16		T3	82		T7	1
arcs[CntProgSt=>TransCheckSt]	26032	1			T1	53		T2	80		T3	396
arcs[TransCheckSt=>PostTransSt]	3598	1			T3	53		T12	10		T38	40
arcs[TransCheckSt=>TokenHashSt]	22328	1			T1	53		T2	80		T3	343
arcs[TokenHashSt=>PostTransSt]	9729	1			T1	10		T2	80		T3	176
arcs[TokenHashSt=>FlashRmaSt]	11889	1			T1	43		T3	167		T8	50
arcs[FlashRmaSt=>TokenCheck0St]	11789	1			T1	43		T3	167		T8	50
arcs[TokenCheck0St=>PostTransSt]	3093	1			T1	13		T3	43		T8	18
arcs[TokenCheck0St=>TokenCheck1St]	8673	1			T1	30		T3	124		T8	32
arcs[TokenCheck1St=>PostTransSt]	685	1			T1	2		T3	6		T38	9
arcs[TransProgSt=>PostTransSt]	7060	1			T1	28		T3	118		T8	32
arcs[IdleSt=>EscalateSt]	154	1			T39	8		T40	9		T42	3
arcs[ClkMuxSt=>EscalateSt]	60	1			T39	3		T40	1		T15	2
arcs[CntIncrSt=>EscalateSt]	63	1			T41	4		T40	1		T15	1
arcs[CntProgSt=>EscalateSt]	1056	1			T39	19		T41	13		T40	33
arcs[TransCheckSt=>EscalateSt]	106	1			T41	12		T40	1		T42	6
arcs[TokenHashSt=>EscalateSt]	710	1			T39	9		T41	29		T40	6
arcs[FlashRmaSt=>EscalateSt]	100	1			T39	2		T40	2		T15	4
arcs[TokenCheck0St=>EscalateSt]	23	1			T40	1		T45	2		T46	2
arcs[TokenCheck1St=>EscalateSt]	162	1			T39	3		T41	3		T40	3
arcs[TransProgSt=>EscalateSt]	766	1			T39	21		T41	8		T40	18
arcs[PostTransSt=>EscalateSt]	4370	1			T1	16		T3	82		T7	1
arcs[InvalidSt=>EscalateSt]	14418	1			T1	18		T3	289		T8	15

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7035482	1			T1	7680		T2	7354		T3	109897
auto[0]	auto[IdleSt]	21538146	1			T1	7661		T2	6711		T3	302638
auto[0]	auto[ClkMuxSt]	33155	1			T1	69		T2	80		T3	531
auto[0]	auto[CntIncrSt]	32954	1			T1	69		T2	80		T3	531
auto[0]	auto[CntProgSt]	1598772	1			T1	122		T2	402		T3	25527
auto[0]	auto[TransCheckSt]	25965	1			T1	53		T2	80		T3	396
auto[0]	auto[TokenHashSt]	36202329	1			T1	2461		T2	1694		T3	107046
auto[0]	auto[FlashRmaSt]	26133	1			T1	147		T3	305		T8	59
auto[0]	auto[TokenCheck0St]	11773	1			T1	43		T3	167		T8	50
auto[0]	auto[TokenCheck1St]	8564	1			T1	30		T3	124		T8	32
auto[0]	auto[TransProgSt]	416511	1			T1	53		T3	6972		T8	15235
auto[0]	auto[PostTransSt]	12484262	1			T1	11105		T2	14086		T3	240888
auto[0]	auto[ScrapSt]	166846	1			T3	474		T9	26		T19	453
auto[0]	auto[EscalateSt]	5274982	1			T1	3080		T3	80675		T7	153
auto[0]	auto[InvalidSt]	11551548	1			T1	3080		T3	191070		T8	2563
auto[1]	auto[ResetSt]	201	1			T39	7		T41	4		T40	1
auto[1]	auto[IdleSt]	100	1			T39	4		T40	4		T42	1
auto[1]	auto[ClkMuxSt]	37	1			T39	3		T40	1		T15	1
auto[1]	auto[CntIncrSt]	40	1			T41	2		T15	1		T45	1
auto[1]	auto[CntProgSt]	680	1			T39	11		T41	9		T40	23
auto[1]	auto[TransCheckSt]	67	1			T41	8		T40	1		T42	4
auto[1]	auto[TokenHashSt]	461	1			T39	6		T41	20		T40	5
auto[1]	auto[FlashRmaSt]	70	1			T39	2		T40	2		T15	1
auto[1]	auto[TokenCheck0St]	16	1			T45	1		T46	1		T189	2
auto[1]	auto[TokenCheck1St]	109	1			T39	3		T41	2		T40	2
auto[1]	auto[TransProgSt]	511	1			T39	12		T41	6		T40	12
auto[1]	auto[PostTransSt]	2282	1			T1	9		T3	44		T8	8
auto[1]	auto[ScrapSt]	45	1			T39	1		T40	1		T15	3
auto[1]	auto[EscalateSt]	1367314	1			T1	1666		T3	18760		T8	1568
auto[1]	auto[InvalidSt]	7233	1			T1	8		T3	149		T8	8

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7035484	1			T1	7680		T2	7354		T3	109897
auto[0]	auto[IdleSt]	21538142	1			T1	7661		T2	6711		T3	302638
auto[0]	auto[ClkMuxSt]	33155	1			T1	69		T2	80		T3	531
auto[0]	auto[CntIncrSt]	32956	1			T1	69		T2	80		T3	531
auto[0]	auto[CntProgSt]	1598730	1			T1	122		T2	402		T3	25527
auto[0]	auto[TransCheckSt]	25963	1			T1	53		T2	80		T3	396
auto[0]	auto[TokenHashSt]	36202282	1			T1	2461		T2	1694		T3	107046
auto[0]	auto[FlashRmaSt]	26137	1			T1	147		T3	305		T8	59
auto[0]	auto[TokenCheck0St]	11772	1			T1	43		T3	167		T8	50
auto[0]	auto[TokenCheck1St]	8567	1			T1	30		T3	124		T8	32
auto[0]	auto[TransProgSt]	416530	1			T1	53		T3	6972		T8	15235
auto[0]	auto[PostTransSt]	12484377	1			T1	11107		T2	14086		T3	240894
auto[0]	auto[ScrapSt]	166852	1			T3	474		T9	26		T19	453
auto[0]	auto[EscalateSt]	5278740	1			T1	3080		T3	82120		T7	55
auto[0]	auto[InvalidSt]	11551596	1			T1	3078		T3	191079		T8	2564
auto[1]	auto[ResetSt]	199	1			T39	7		T41	3		T40	2
auto[1]	auto[IdleSt]	104	1			T39	8		T40	7		T42	2
auto[1]	auto[ClkMuxSt]	37	1			T15	1		T42	1		T45	2
auto[1]	auto[CntIncrSt]	38	1			T41	3		T40	1		T15	1
auto[1]	auto[CntProgSt]	722	1			T39	14		T41	6		T40	21
auto[1]	auto[TransCheckSt]	69	1			T41	7		T40	1		T42	3
auto[1]	auto[TokenHashSt]	508	1			T39	7		T41	15		T40	6
auto[1]	auto[FlashRmaSt]	66	1			T39	1		T40	1		T15	4
auto[1]	auto[TokenCheck0St]	17	1			T40	1		T45	2		T46	1
auto[1]	auto[TokenCheck1St]	106	1			T39	1		T41	1		T40	2
auto[1]	auto[TransProgSt]	492	1			T39	15		T41	6		T40	9
auto[1]	auto[PostTransSt]	2167	1			T1	7		T3	38		T7	1
auto[1]	auto[ScrapSt]	39	1			T40	2		T15	2		T190	1
auto[1]	auto[EscalateSt]	1363556	1			T1	1666		T3	17315		T7	98
auto[1]	auto[InvalidSt]	7185	1			T1	10		T3	140		T8	7