Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.92 97.82 95.93 93.31 97.62 98.52 98.76 96.47


Total test records in report: 997
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T812 /workspace/coverage/default/13.lc_ctrl_sec_mubi.3896903528 Jun 05 05:20:36 PM PDT 24 Jun 05 05:20:55 PM PDT 24 3274732752 ps
T813 /workspace/coverage/default/27.lc_ctrl_state_failure.1003376102 Jun 05 05:21:32 PM PDT 24 Jun 05 05:22:05 PM PDT 24 559703931 ps
T814 /workspace/coverage/default/20.lc_ctrl_jtag_access.4222389688 Jun 05 05:21:06 PM PDT 24 Jun 05 05:21:31 PM PDT 24 1967532718 ps
T815 /workspace/coverage/default/39.lc_ctrl_stress_all.272608827 Jun 05 05:22:08 PM PDT 24 Jun 05 05:23:56 PM PDT 24 39556183958 ps
T816 /workspace/coverage/default/43.lc_ctrl_smoke.1614855556 Jun 05 05:22:28 PM PDT 24 Jun 05 05:22:32 PM PDT 24 131449850 ps
T817 /workspace/coverage/default/14.lc_ctrl_jtag_errors.2047178565 Jun 05 05:20:36 PM PDT 24 Jun 05 05:21:19 PM PDT 24 9774184236 ps
T818 /workspace/coverage/default/3.lc_ctrl_sec_mubi.1066426629 Jun 05 05:19:34 PM PDT 24 Jun 05 05:19:48 PM PDT 24 283114128 ps
T819 /workspace/coverage/default/43.lc_ctrl_state_post_trans.2643872121 Jun 05 05:22:25 PM PDT 24 Jun 05 05:22:35 PM PDT 24 91033767 ps
T820 /workspace/coverage/default/11.lc_ctrl_prog_failure.716285793 Jun 05 05:20:17 PM PDT 24 Jun 05 05:20:20 PM PDT 24 43326295 ps
T821 /workspace/coverage/default/5.lc_ctrl_stress_all.1864087718 Jun 05 05:19:50 PM PDT 24 Jun 05 05:25:57 PM PDT 24 12884016269 ps
T822 /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1688994792 Jun 05 05:19:57 PM PDT 24 Jun 05 05:20:14 PM PDT 24 488677756 ps
T823 /workspace/coverage/default/20.lc_ctrl_security_escalation.3949442124 Jun 05 05:20:59 PM PDT 24 Jun 05 05:21:09 PM PDT 24 748564096 ps
T824 /workspace/coverage/default/13.lc_ctrl_stress_all.2194945957 Jun 05 05:20:36 PM PDT 24 Jun 05 05:21:47 PM PDT 24 14930969069 ps
T825 /workspace/coverage/default/1.lc_ctrl_state_post_trans.1285563032 Jun 05 05:19:26 PM PDT 24 Jun 05 05:19:33 PM PDT 24 49850877 ps
T826 /workspace/coverage/default/38.lc_ctrl_errors.2583510552 Jun 05 05:22:08 PM PDT 24 Jun 05 05:22:22 PM PDT 24 3303183519 ps
T827 /workspace/coverage/default/37.lc_ctrl_errors.795431401 Jun 05 05:22:01 PM PDT 24 Jun 05 05:22:17 PM PDT 24 1483231354 ps
T64 /workspace/coverage/default/27.lc_ctrl_alert_test.1752302257 Jun 05 05:21:31 PM PDT 24 Jun 05 05:21:33 PM PDT 24 26015207 ps
T828 /workspace/coverage/default/6.lc_ctrl_jtag_priority.833316929 Jun 05 05:19:57 PM PDT 24 Jun 05 05:20:09 PM PDT 24 4246320029 ps
T829 /workspace/coverage/default/22.lc_ctrl_security_escalation.3748059690 Jun 05 05:21:09 PM PDT 24 Jun 05 05:21:22 PM PDT 24 2399676329 ps
T830 /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3862216003 Jun 05 05:20:42 PM PDT 24 Jun 05 05:20:56 PM PDT 24 3536584039 ps
T831 /workspace/coverage/default/36.lc_ctrl_security_escalation.4037386261 Jun 05 05:22:01 PM PDT 24 Jun 05 05:22:17 PM PDT 24 1613185922 ps
T832 /workspace/coverage/default/0.lc_ctrl_jtag_smoke.842535537 Jun 05 05:19:18 PM PDT 24 Jun 05 05:19:21 PM PDT 24 77826200 ps
T833 /workspace/coverage/default/8.lc_ctrl_alert_test.1502475073 Jun 05 05:20:13 PM PDT 24 Jun 05 05:20:14 PM PDT 24 23522838 ps
T834 /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3389312987 Jun 05 05:21:51 PM PDT 24 Jun 05 05:22:03 PM PDT 24 1186007834 ps
T65 /workspace/coverage/default/12.lc_ctrl_stress_all.2979880966 Jun 05 05:20:28 PM PDT 24 Jun 05 05:22:18 PM PDT 24 33705208017 ps
T835 /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1809525510 Jun 05 05:21:04 PM PDT 24 Jun 05 05:21:16 PM PDT 24 1457254052 ps
T836 /workspace/coverage/default/40.lc_ctrl_smoke.2515010231 Jun 05 05:22:16 PM PDT 24 Jun 05 05:22:18 PM PDT 24 22129472 ps
T837 /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1985719957 Jun 05 05:22:44 PM PDT 24 Jun 05 05:22:58 PM PDT 24 1354750478 ps
T838 /workspace/coverage/default/23.lc_ctrl_sec_mubi.1141994581 Jun 05 05:21:16 PM PDT 24 Jun 05 05:21:40 PM PDT 24 502705357 ps
T839 /workspace/coverage/default/43.lc_ctrl_prog_failure.1854393058 Jun 05 05:22:28 PM PDT 24 Jun 05 05:22:32 PM PDT 24 58063248 ps
T840 /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1890485220 Jun 05 05:21:38 PM PDT 24 Jun 05 05:21:47 PM PDT 24 2054869293 ps
T841 /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2874872681 Jun 05 05:22:26 PM PDT 24 Jun 05 05:22:44 PM PDT 24 450117116 ps
T842 /workspace/coverage/default/35.lc_ctrl_state_post_trans.2836408345 Jun 05 05:21:53 PM PDT 24 Jun 05 05:22:01 PM PDT 24 203158905 ps
T843 /workspace/coverage/default/34.lc_ctrl_state_post_trans.3858638804 Jun 05 05:21:53 PM PDT 24 Jun 05 05:22:00 PM PDT 24 355191206 ps
T844 /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3602201377 Jun 05 05:19:50 PM PDT 24 Jun 05 05:20:32 PM PDT 24 1454141972 ps
T845 /workspace/coverage/default/48.lc_ctrl_errors.1909833251 Jun 05 05:22:42 PM PDT 24 Jun 05 05:22:55 PM PDT 24 291729157 ps
T846 /workspace/coverage/default/31.lc_ctrl_state_failure.2702995586 Jun 05 05:21:46 PM PDT 24 Jun 05 05:22:18 PM PDT 24 959365654 ps
T847 /workspace/coverage/default/3.lc_ctrl_stress_all.2191577493 Jun 05 05:19:34 PM PDT 24 Jun 05 05:22:53 PM PDT 24 9402597418 ps
T94 /workspace/coverage/default/2.lc_ctrl_sec_cm.2159728079 Jun 05 05:19:35 PM PDT 24 Jun 05 05:20:22 PM PDT 24 474069693 ps
T848 /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2059305642 Jun 05 05:20:19 PM PDT 24 Jun 05 05:21:11 PM PDT 24 7787553354 ps
T849 /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2900121029 Jun 05 05:22:27 PM PDT 24 Jun 05 05:22:29 PM PDT 24 11679734 ps
T850 /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2120289745 Jun 05 05:21:54 PM PDT 24 Jun 05 05:22:12 PM PDT 24 4705662198 ps
T851 /workspace/coverage/default/40.lc_ctrl_stress_all.1140031783 Jun 05 05:22:17 PM PDT 24 Jun 05 05:27:53 PM PDT 24 20329098425 ps
T852 /workspace/coverage/default/30.lc_ctrl_jtag_access.35463753 Jun 05 05:21:38 PM PDT 24 Jun 05 05:21:43 PM PDT 24 958148090 ps
T853 /workspace/coverage/default/41.lc_ctrl_state_post_trans.3075256669 Jun 05 05:22:18 PM PDT 24 Jun 05 05:22:27 PM PDT 24 99130488 ps
T854 /workspace/coverage/default/45.lc_ctrl_state_failure.2173935670 Jun 05 05:22:43 PM PDT 24 Jun 05 05:23:04 PM PDT 24 662896368 ps
T855 /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3101201256 Jun 05 05:21:27 PM PDT 24 Jun 05 05:21:37 PM PDT 24 200602136 ps
T856 /workspace/coverage/default/0.lc_ctrl_sec_mubi.4102076721 Jun 05 05:19:20 PM PDT 24 Jun 05 05:19:31 PM PDT 24 2928139466 ps
T857 /workspace/coverage/default/49.lc_ctrl_smoke.1533685519 Jun 05 05:22:43 PM PDT 24 Jun 05 05:22:46 PM PDT 24 151390861 ps
T858 /workspace/coverage/default/28.lc_ctrl_jtag_access.25180573 Jun 05 05:21:30 PM PDT 24 Jun 05 05:21:36 PM PDT 24 434712780 ps
T859 /workspace/coverage/default/25.lc_ctrl_stress_all.1356158432 Jun 05 05:21:23 PM PDT 24 Jun 05 05:27:17 PM PDT 24 20840561443 ps
T860 /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.540442848 Jun 05 05:21:38 PM PDT 24 Jun 05 05:21:40 PM PDT 24 12273461 ps
T861 /workspace/coverage/default/1.lc_ctrl_alert_test.3802762703 Jun 05 05:19:29 PM PDT 24 Jun 05 05:19:31 PM PDT 24 43484443 ps
T862 /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3858903156 Jun 05 05:21:16 PM PDT 24 Jun 05 05:21:26 PM PDT 24 936188736 ps
T863 /workspace/coverage/default/45.lc_ctrl_sec_token_mux.4251175376 Jun 05 05:22:41 PM PDT 24 Jun 05 05:22:53 PM PDT 24 413070262 ps
T864 /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3550927886 Jun 05 05:22:27 PM PDT 24 Jun 05 05:22:29 PM PDT 24 38865647 ps
T66 /workspace/coverage/default/7.lc_ctrl_jtag_smoke.4079046088 Jun 05 05:19:58 PM PDT 24 Jun 05 05:20:09 PM PDT 24 822789165 ps
T865 /workspace/coverage/default/25.lc_ctrl_smoke.2879287696 Jun 05 05:21:22 PM PDT 24 Jun 05 05:21:26 PM PDT 24 54632325 ps
T866 /workspace/coverage/default/16.lc_ctrl_state_failure.1724085643 Jun 05 05:20:44 PM PDT 24 Jun 05 05:21:08 PM PDT 24 4508903733 ps
T867 /workspace/coverage/default/6.lc_ctrl_prog_failure.1235858211 Jun 05 05:19:51 PM PDT 24 Jun 05 05:19:55 PM PDT 24 64234206 ps
T868 /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1132240314 Jun 05 05:21:40 PM PDT 24 Jun 05 05:21:52 PM PDT 24 5145171106 ps
T869 /workspace/coverage/default/34.lc_ctrl_smoke.2834652511 Jun 05 05:21:53 PM PDT 24 Jun 05 05:21:59 PM PDT 24 85823905 ps
T111 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3699563861 Jun 05 05:52:25 PM PDT 24 Jun 05 05:52:27 PM PDT 24 17927473 ps
T112 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3514512098 Jun 05 05:52:15 PM PDT 24 Jun 05 05:52:22 PM PDT 24 1170813715 ps
T103 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1387813240 Jun 05 05:52:29 PM PDT 24 Jun 05 05:52:31 PM PDT 24 121526668 ps
T113 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3425854634 Jun 05 05:52:33 PM PDT 24 Jun 05 05:52:36 PM PDT 24 181550838 ps
T104 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1132254693 Jun 05 05:52:27 PM PDT 24 Jun 05 05:52:33 PM PDT 24 116742926 ps
T181 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.329946156 Jun 05 05:52:28 PM PDT 24 Jun 05 05:52:30 PM PDT 24 35088398 ps
T136 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3753744848 Jun 05 05:52:23 PM PDT 24 Jun 05 05:52:25 PM PDT 24 36778340 ps
T106 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3571203854 Jun 05 05:52:31 PM PDT 24 Jun 05 05:52:33 PM PDT 24 41681562 ps
T146 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3766238566 Jun 05 05:52:19 PM PDT 24 Jun 05 05:52:22 PM PDT 24 27617757 ps
T173 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2273039851 Jun 05 05:52:16 PM PDT 24 Jun 05 05:52:18 PM PDT 24 66211026 ps
T133 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.4058371432 Jun 05 05:52:20 PM PDT 24 Jun 05 05:52:44 PM PDT 24 4794218022 ps
T870 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.875125483 Jun 05 05:52:32 PM PDT 24 Jun 05 05:52:34 PM PDT 24 30620801 ps
T105 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2283982440 Jun 05 05:52:25 PM PDT 24 Jun 05 05:52:27 PM PDT 24 19281591 ps
T174 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2970813822 Jun 05 05:52:24 PM PDT 24 Jun 05 05:52:27 PM PDT 24 48383224 ps
T147 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2439439597 Jun 05 05:52:37 PM PDT 24 Jun 05 05:52:39 PM PDT 24 29405546 ps
T117 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3190510179 Jun 05 05:52:22 PM PDT 24 Jun 05 05:52:25 PM PDT 24 28160596 ps
T135 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1236465210 Jun 05 05:52:19 PM PDT 24 Jun 05 05:52:34 PM PDT 24 2286381342 ps
T871 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2401672249 Jun 05 05:52:28 PM PDT 24 Jun 05 05:52:30 PM PDT 24 39033513 ps
T872 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2709883145 Jun 05 05:53:01 PM PDT 24 Jun 05 05:53:04 PM PDT 24 18287033 ps
T134 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1586245212 Jun 05 05:52:21 PM PDT 24 Jun 05 05:52:32 PM PDT 24 1379418389 ps
T118 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1147750248 Jun 05 05:52:51 PM PDT 24 Jun 05 05:52:53 PM PDT 24 85744894 ps
T873 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3549842200 Jun 05 05:52:17 PM PDT 24 Jun 05 05:52:20 PM PDT 24 263211201 ps
T874 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3689013159 Jun 05 05:52:28 PM PDT 24 Jun 05 05:52:31 PM PDT 24 657683207 ps
T875 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.488036330 Jun 05 05:52:16 PM PDT 24 Jun 05 05:52:18 PM PDT 24 819637644 ps
T161 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.447942211 Jun 05 05:53:01 PM PDT 24 Jun 05 05:53:03 PM PDT 24 24411299 ps
T148 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.267916369 Jun 05 05:52:29 PM PDT 24 Jun 05 05:52:32 PM PDT 24 159956555 ps
T876 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2085023857 Jun 05 05:52:28 PM PDT 24 Jun 05 05:52:41 PM PDT 24 448279601 ps
T175 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.690473645 Jun 05 05:52:30 PM PDT 24 Jun 05 05:52:33 PM PDT 24 112372970 ps
T176 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4120429514 Jun 05 05:52:18 PM PDT 24 Jun 05 05:52:20 PM PDT 24 17308183 ps
T877 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.919567674 Jun 05 05:52:20 PM PDT 24 Jun 05 05:52:41 PM PDT 24 17823973424 ps
T878 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1438609295 Jun 05 05:52:22 PM PDT 24 Jun 05 05:52:24 PM PDT 24 177428130 ps
T107 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3182364277 Jun 05 05:52:32 PM PDT 24 Jun 05 05:52:35 PM PDT 24 54930145 ps
T108 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2794299345 Jun 05 05:52:36 PM PDT 24 Jun 05 05:52:41 PM PDT 24 275837685 ps
T162 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4093996682 Jun 05 05:52:21 PM PDT 24 Jun 05 05:52:23 PM PDT 24 29000237 ps
T114 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3335776918 Jun 05 05:52:28 PM PDT 24 Jun 05 05:52:32 PM PDT 24 55748511 ps
T120 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.288327391 Jun 05 05:52:41 PM PDT 24 Jun 05 05:52:44 PM PDT 24 99376124 ps
T879 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.959641636 Jun 05 05:52:29 PM PDT 24 Jun 05 05:52:32 PM PDT 24 24976735 ps
T880 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2224327051 Jun 05 05:52:16 PM PDT 24 Jun 05 05:52:18 PM PDT 24 45649934 ps
T881 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.733577707 Jun 05 05:52:46 PM PDT 24 Jun 05 05:52:49 PM PDT 24 61459176 ps
T882 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2977766178 Jun 05 05:52:24 PM PDT 24 Jun 05 05:52:32 PM PDT 24 133214091 ps
T177 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.650513936 Jun 05 05:52:23 PM PDT 24 Jun 05 05:52:25 PM PDT 24 21584592 ps
T163 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2915061001 Jun 05 05:53:00 PM PDT 24 Jun 05 05:53:02 PM PDT 24 53379000 ps
T178 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1991992559 Jun 05 05:52:24 PM PDT 24 Jun 05 05:52:27 PM PDT 24 50708006 ps
T883 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.4280091872 Jun 05 05:52:34 PM PDT 24 Jun 05 05:52:36 PM PDT 24 93304601 ps
T884 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2836639382 Jun 05 05:52:32 PM PDT 24 Jun 05 05:52:35 PM PDT 24 163035192 ps
T164 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.130581138 Jun 05 05:52:31 PM PDT 24 Jun 05 05:52:33 PM PDT 24 25405013 ps
T885 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1595699747 Jun 05 05:52:16 PM PDT 24 Jun 05 05:52:18 PM PDT 24 20347797 ps
T886 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.384481768 Jun 05 05:52:14 PM PDT 24 Jun 05 05:52:15 PM PDT 24 59290078 ps
T887 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1299418190 Jun 05 05:52:24 PM PDT 24 Jun 05 05:52:28 PM PDT 24 60777318 ps
T109 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3852897636 Jun 05 05:52:43 PM PDT 24 Jun 05 05:52:46 PM PDT 24 119705048 ps
T179 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2903263209 Jun 05 05:52:20 PM PDT 24 Jun 05 05:52:22 PM PDT 24 38465780 ps
T888 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.4137234192 Jun 05 05:52:17 PM PDT 24 Jun 05 05:52:21 PM PDT 24 324466840 ps
T889 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.8765467 Jun 05 05:52:30 PM PDT 24 Jun 05 05:52:33 PM PDT 24 42416848 ps
T890 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1019208222 Jun 05 05:52:27 PM PDT 24 Jun 05 05:52:29 PM PDT 24 20348044 ps
T891 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.641863429 Jun 05 05:52:18 PM PDT 24 Jun 05 05:52:22 PM PDT 24 607282362 ps
T110 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3221835874 Jun 05 05:52:25 PM PDT 24 Jun 05 05:52:29 PM PDT 24 123055588 ps
T892 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.726942243 Jun 05 05:52:21 PM PDT 24 Jun 05 05:52:24 PM PDT 24 120828948 ps
T893 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2833729045 Jun 05 05:52:28 PM PDT 24 Jun 05 05:52:30 PM PDT 24 60280409 ps
T165 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1178841354 Jun 05 05:52:30 PM PDT 24 Jun 05 05:52:32 PM PDT 24 12543072 ps
T166 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3670518359 Jun 05 05:52:43 PM PDT 24 Jun 05 05:52:44 PM PDT 24 17546595 ps
T894 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.456820518 Jun 05 05:52:19 PM PDT 24 Jun 05 05:52:23 PM PDT 24 273488414 ps
T895 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.445135148 Jun 05 05:52:19 PM PDT 24 Jun 05 05:52:30 PM PDT 24 17495457452 ps
T896 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2052471177 Jun 05 05:52:25 PM PDT 24 Jun 05 05:52:28 PM PDT 24 29405253 ps
T897 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2884834202 Jun 05 05:52:36 PM PDT 24 Jun 05 05:52:38 PM PDT 24 79706688 ps
T898 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1197774926 Jun 05 05:52:18 PM PDT 24 Jun 05 05:52:24 PM PDT 24 1418361941 ps
T899 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1157136022 Jun 05 05:52:16 PM PDT 24 Jun 05 05:52:18 PM PDT 24 19644718 ps
T123 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3674289095 Jun 05 05:52:28 PM PDT 24 Jun 05 05:52:32 PM PDT 24 79199832 ps
T900 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.4220314028 Jun 05 05:52:17 PM PDT 24 Jun 05 05:52:20 PM PDT 24 57155091 ps
T901 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2375512540 Jun 05 05:52:23 PM PDT 24 Jun 05 05:52:34 PM PDT 24 2733560089 ps
T902 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2197875434 Jun 05 05:52:22 PM PDT 24 Jun 05 05:52:25 PM PDT 24 85484101 ps
T119 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3197539031 Jun 05 05:52:48 PM PDT 24 Jun 05 05:52:51 PM PDT 24 58618868 ps
T903 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1230170284 Jun 05 05:52:18 PM PDT 24 Jun 05 05:52:23 PM PDT 24 101882476 ps
T904 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1900892683 Jun 05 05:52:22 PM PDT 24 Jun 05 05:52:25 PM PDT 24 943649676 ps
T905 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.527162312 Jun 05 05:52:43 PM PDT 24 Jun 05 05:52:44 PM PDT 24 18573842 ps
T906 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3308563802 Jun 05 05:52:14 PM PDT 24 Jun 05 05:52:31 PM PDT 24 691058513 ps
T907 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.744318495 Jun 05 05:52:24 PM PDT 24 Jun 05 05:52:27 PM PDT 24 23888115 ps
T908 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3199479325 Jun 05 05:52:19 PM PDT 24 Jun 05 05:52:21 PM PDT 24 261035311 ps
T909 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1061047577 Jun 05 05:52:34 PM PDT 24 Jun 05 05:52:36 PM PDT 24 272612209 ps
T167 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3546086602 Jun 05 05:52:24 PM PDT 24 Jun 05 05:52:27 PM PDT 24 12565555 ps
T132 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.4221352716 Jun 05 05:52:33 PM PDT 24 Jun 05 05:52:36 PM PDT 24 122896865 ps
T910 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1076452124 Jun 05 05:52:21 PM PDT 24 Jun 05 05:52:31 PM PDT 24 370102692 ps
T911 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3060154414 Jun 05 05:52:21 PM PDT 24 Jun 05 05:52:23 PM PDT 24 67319943 ps
T912 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2396006674 Jun 05 05:52:52 PM PDT 24 Jun 05 05:52:54 PM PDT 24 15564059 ps
T913 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.705197741 Jun 05 05:52:37 PM PDT 24 Jun 05 05:52:39 PM PDT 24 77906206 ps
T914 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.972563222 Jun 05 05:52:49 PM PDT 24 Jun 05 05:52:50 PM PDT 24 51723349 ps
T915 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.828480612 Jun 05 05:52:18 PM PDT 24 Jun 05 05:52:21 PM PDT 24 133135524 ps
T916 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2417524800 Jun 05 05:52:25 PM PDT 24 Jun 05 05:52:35 PM PDT 24 970383605 ps
T917 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4069282320 Jun 05 05:52:37 PM PDT 24 Jun 05 05:52:41 PM PDT 24 138930284 ps
T918 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4166889170 Jun 05 05:52:21 PM PDT 24 Jun 05 05:52:32 PM PDT 24 4303276651 ps
T919 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.103302468 Jun 05 05:52:15 PM PDT 24 Jun 05 05:52:25 PM PDT 24 2179328734 ps
T920 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3059220859 Jun 05 05:52:28 PM PDT 24 Jun 05 05:52:31 PM PDT 24 83737943 ps
T130 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1646762588 Jun 05 05:52:16 PM PDT 24 Jun 05 05:52:20 PM PDT 24 143205068 ps
T921 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3639758837 Jun 05 05:52:43 PM PDT 24 Jun 05 05:52:47 PM PDT 24 111959161 ps
T922 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2991287420 Jun 05 05:52:26 PM PDT 24 Jun 05 05:52:28 PM PDT 24 15979392 ps
T127 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1889064397 Jun 05 05:52:29 PM PDT 24 Jun 05 05:52:34 PM PDT 24 341292831 ps
T923 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3097804996 Jun 05 05:52:20 PM PDT 24 Jun 05 05:52:32 PM PDT 24 822209402 ps
T924 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1662350247 Jun 05 05:52:59 PM PDT 24 Jun 05 05:53:01 PM PDT 24 32799868 ps
T925 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3876490271 Jun 05 05:52:36 PM PDT 24 Jun 05 05:52:37 PM PDT 24 43602906 ps
T926 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.191479155 Jun 05 05:52:23 PM PDT 24 Jun 05 05:52:25 PM PDT 24 83869322 ps
T927 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2662356761 Jun 05 05:52:33 PM PDT 24 Jun 05 05:52:46 PM PDT 24 228243629 ps
T928 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3241082833 Jun 05 05:52:45 PM PDT 24 Jun 05 05:52:47 PM PDT 24 37838345 ps
T929 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.457807963 Jun 05 05:52:27 PM PDT 24 Jun 05 05:52:29 PM PDT 24 41810192 ps
T930 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4152436649 Jun 05 05:52:22 PM PDT 24 Jun 05 05:52:25 PM PDT 24 183081035 ps
T931 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1105052654 Jun 05 05:52:17 PM PDT 24 Jun 05 05:52:20 PM PDT 24 58621560 ps
T124 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1726326799 Jun 05 05:52:24 PM PDT 24 Jun 05 05:52:29 PM PDT 24 78972120 ps
T932 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2090002965 Jun 05 05:52:34 PM PDT 24 Jun 05 05:52:36 PM PDT 24 15361323 ps
T168 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.47676597 Jun 05 05:52:24 PM PDT 24 Jun 05 05:52:27 PM PDT 24 372080900 ps
T933 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4139567716 Jun 05 05:52:23 PM PDT 24 Jun 05 05:52:27 PM PDT 24 183086843 ps
T934 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2638944785 Jun 05 05:52:19 PM PDT 24 Jun 05 05:52:22 PM PDT 24 392533614 ps
T125 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1119014378 Jun 05 05:52:31 PM PDT 24 Jun 05 05:52:45 PM PDT 24 268762410 ps
T121 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.738679920 Jun 05 05:52:30 PM PDT 24 Jun 05 05:52:34 PM PDT 24 992889904 ps
T935 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3128302403 Jun 05 05:52:18 PM PDT 24 Jun 05 05:52:21 PM PDT 24 72211407 ps
T936 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2398630299 Jun 05 05:52:19 PM PDT 24 Jun 05 05:52:22 PM PDT 24 29368189 ps
T122 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.917640279 Jun 05 05:52:23 PM PDT 24 Jun 05 05:52:27 PM PDT 24 307995713 ps
T937 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.721592676 Jun 05 05:52:26 PM PDT 24 Jun 05 05:52:28 PM PDT 24 191577040 ps
T938 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.564582869 Jun 05 05:52:23 PM PDT 24 Jun 05 05:52:25 PM PDT 24 16194802 ps
T939 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3841922535 Jun 05 05:52:22 PM PDT 24 Jun 05 05:52:24 PM PDT 24 49424927 ps
T940 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1655253980 Jun 05 05:52:31 PM PDT 24 Jun 05 05:52:33 PM PDT 24 85092324 ps
T941 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1809812544 Jun 05 05:52:17 PM PDT 24 Jun 05 05:52:21 PM PDT 24 203412787 ps
T942 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.18691847 Jun 05 05:52:28 PM PDT 24 Jun 05 05:52:30 PM PDT 24 46205977 ps
T943 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3346283879 Jun 05 05:52:27 PM PDT 24 Jun 05 05:52:29 PM PDT 24 73954114 ps
T944 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3241893762 Jun 05 05:52:30 PM PDT 24 Jun 05 05:52:34 PM PDT 24 211615623 ps
T945 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2983510398 Jun 05 05:52:24 PM PDT 24 Jun 05 05:52:28 PM PDT 24 239055749 ps
T946 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.711560207 Jun 05 05:52:20 PM PDT 24 Jun 05 05:52:23 PM PDT 24 514938117 ps
T947 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3630817060 Jun 05 05:52:21 PM PDT 24 Jun 05 05:52:25 PM PDT 24 1520158499 ps
T948 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.660110935 Jun 05 05:52:24 PM PDT 24 Jun 05 05:52:27 PM PDT 24 20770556 ps
T949 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.923541533 Jun 05 05:52:29 PM PDT 24 Jun 05 05:52:32 PM PDT 24 119012100 ps
T128 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1618568727 Jun 05 05:52:33 PM PDT 24 Jun 05 05:52:36 PM PDT 24 214126871 ps
T950 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1875409317 Jun 05 05:52:21 PM PDT 24 Jun 05 05:52:24 PM PDT 24 37009494 ps
T169 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1657525555 Jun 05 05:52:16 PM PDT 24 Jun 05 05:52:18 PM PDT 24 13633862 ps
T951 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3475407958 Jun 05 05:52:29 PM PDT 24 Jun 05 05:52:36 PM PDT 24 35878302 ps
T952 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1091814400 Jun 05 05:52:28 PM PDT 24 Jun 05 05:52:32 PM PDT 24 83768047 ps
T953 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.238169914 Jun 05 05:52:28 PM PDT 24 Jun 05 05:52:31 PM PDT 24 92159008 ps
T954 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3397320601 Jun 05 05:52:21 PM PDT 24 Jun 05 05:52:24 PM PDT 24 35474109 ps
T126 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.551424787 Jun 05 05:52:24 PM PDT 24 Jun 05 05:52:28 PM PDT 24 77548349 ps
T955 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2153853724 Jun 05 05:52:31 PM PDT 24 Jun 05 05:52:35 PM PDT 24 680493974 ps
T956 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3809089923 Jun 05 05:52:39 PM PDT 24 Jun 05 05:52:41 PM PDT 24 45822354 ps
T957 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1774224213 Jun 05 05:52:42 PM PDT 24 Jun 05 05:52:44 PM PDT 24 163946595 ps
T958 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.899030263 Jun 05 05:52:21 PM PDT 24 Jun 05 05:52:23 PM PDT 24 55983778 ps
T959 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3732575024 Jun 05 05:52:33 PM PDT 24 Jun 05 05:52:36 PM PDT 24 74960381 ps
T960 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1692631392 Jun 05 05:52:22 PM PDT 24 Jun 05 05:52:27 PM PDT 24 248139656 ps
T961 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2748717014 Jun 05 05:52:20 PM PDT 24 Jun 05 05:52:24 PM PDT 24 830723988 ps
T962 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2726943565 Jun 05 05:52:19 PM PDT 24 Jun 05 05:52:22 PM PDT 24 64271546 ps
T963 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1176480911 Jun 05 05:52:23 PM PDT 24 Jun 05 05:52:33 PM PDT 24 344521708 ps
T964 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1742053423 Jun 05 05:52:19 PM PDT 24 Jun 05 05:52:21 PM PDT 24 19657956 ps
T965 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.828282330 Jun 05 05:52:28 PM PDT 24 Jun 05 05:52:31 PM PDT 24 151250430 ps
T115 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2754253738 Jun 05 05:52:19 PM PDT 24 Jun 05 05:52:24 PM PDT 24 426760944 ps
T966 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1691685889 Jun 05 05:52:43 PM PDT 24 Jun 05 05:52:45 PM PDT 24 152906139 ps
T967 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.713987846 Jun 05 05:52:40 PM PDT 24 Jun 05 05:52:42 PM PDT 24 18973245 ps
T968 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1957160798 Jun 05 05:52:27 PM PDT 24 Jun 05 05:52:31 PM PDT 24 217245481 ps
T969 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.4175093077 Jun 05 05:52:29 PM PDT 24 Jun 05 05:52:32 PM PDT 24 67695286 ps
T170 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.993313381 Jun 05 05:52:18 PM PDT 24 Jun 05 05:52:20 PM PDT 24 125950293 ps
T970 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2935174318 Jun 05 05:52:22 PM PDT 24 Jun 05 05:52:25 PM PDT 24 442366425 ps
T971 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2888517568 Jun 05 05:52:31 PM PDT 24 Jun 05 05:52:33 PM PDT 24 66296147 ps
T972 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2812098971 Jun 05 05:52:24 PM PDT 24 Jun 05 05:52:27 PM PDT 24 1169291086 ps
T973 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.546200247 Jun 05 05:52:22 PM PDT 24 Jun 05 05:52:25 PM PDT 24 89995697 ps
T974 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.168102263 Jun 05 05:52:17 PM PDT 24 Jun 05 05:52:21 PM PDT 24 346925757 ps
T975 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3474570089 Jun 05 05:52:30 PM PDT 24 Jun 05 05:52:53 PM PDT 24 4497691468 ps
T976 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.769500436 Jun 05 05:52:15 PM PDT 24 Jun 05 05:52:17 PM PDT 24 21852867 ps
T171 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1097836511 Jun 05 05:52:44 PM PDT 24 Jun 05 05:52:46 PM PDT 24 134014896 ps
T977 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.335060341 Jun 05 05:52:17 PM PDT 24 Jun 05 05:52:20 PM PDT 24 274434042 ps
T978 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3223791762 Jun 05 05:52:28 PM PDT 24 Jun 05 05:52:30 PM PDT 24 26009774 ps
T979 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1303116794 Jun 05 05:52:22 PM PDT 24 Jun 05 05:52:24 PM PDT 24 66324427 ps
T129 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.638612829 Jun 05 05:52:25 PM PDT 24 Jun 05 05:52:30 PM PDT 24 648729620 ps
T980 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1605734805 Jun 05 05:52:36 PM PDT 24 Jun 05 05:52:37 PM PDT 24 43438437 ps
T981 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.722346293 Jun 05 05:52:29 PM PDT 24 Jun 05 05:52:32 PM PDT 24 342090737 ps
T982 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2632238068 Jun 05 05:52:30 PM PDT 24 Jun 05 05:52:32 PM PDT 24 19540917 ps
T983 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.4120792800 Jun 05 05:52:29 PM PDT 24 Jun 05 05:52:32 PM PDT 24 49677027 ps
T984 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4245861549 Jun 05 05:52:15 PM PDT 24 Jun 05 05:52:33 PM PDT 24 6066771999 ps
T985 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1659418955 Jun 05 05:52:23 PM PDT 24 Jun 05 05:52:28 PM PDT 24 576678853 ps
T986 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.673343598 Jun 05 05:52:37 PM PDT 24 Jun 05 05:52:39 PM PDT 24 36371395 ps
T987 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2172843634 Jun 05 05:52:16 PM PDT 24 Jun 05 05:52:34 PM PDT 24 9180292001 ps
T988 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1501722257 Jun 05 05:52:27 PM PDT 24 Jun 05 05:52:44 PM PDT 24 698044457 ps
T989 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2968667732 Jun 05 05:52:43 PM PDT 24 Jun 05 05:52:46 PM PDT 24 73640860 ps
T990 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2010925411 Jun 05 05:52:28 PM PDT 24 Jun 05 05:52:36 PM PDT 24 523530431 ps
T991 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.55664824 Jun 05 05:52:25 PM PDT 24 Jun 05 05:52:27 PM PDT 24 135157340 ps
T116 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1606181432 Jun 05 05:52:20 PM PDT 24 Jun 05 05:52:24 PM PDT 24 125979586 ps
T992 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1649988016 Jun 05 05:52:16 PM PDT 24 Jun 05 05:52:19 PM PDT 24 314214077 ps
T172 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.276717074 Jun 05 05:52:46 PM PDT 24 Jun 05 05:52:47 PM PDT 24 173693582 ps
T993 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.666050567 Jun 05 05:52:18 PM PDT 24 Jun 05 05:52:24 PM PDT 24 3281794320 ps
T994 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.840862875 Jun 05 05:52:20 PM PDT 24 Jun 05 05:52:23 PM PDT 24 206023330 ps
T995 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1020913117 Jun 05 05:52:33 PM PDT 24 Jun 05 05:52:35 PM PDT 24 27204275 ps
T996 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.287808699 Jun 05 05:52:17 PM PDT 24 Jun 05 05:52:21 PM PDT 24 246621806 ps
T131 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.850372623 Jun 05 05:52:41 PM PDT 24 Jun 05 05:52:45 PM PDT 24 85978229 ps
T997 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1858697176 Jun 05 05:52:29 PM PDT 24 Jun 05 05:52:32 PM PDT 24 117505169 ps

Test location /workspace/coverage/default/41.lc_ctrl_stress_all_with_rand_reset.1207382535
Short name T3
Test name
Test status
Simulation time 21804228013 ps
CPU time 461.15 seconds
Started Jun 05 05:22:15 PM PDT 24
Finished Jun 05 05:29:57 PM PDT 24
Peak memory 284024 kb
Host smart-a44ab68b-2546-482a-a1a2-5b74565fe9bc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1207382535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_stress_all_with_rand_reset.1207382535
Directory /workspace/41.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.3029482800
Short name T45
Test name
Test status
Simulation time 324095178 ps
CPU time 13.86 seconds
Started Jun 05 05:20:43 PM PDT 24
Finished Jun 05 05:20:57 PM PDT 24
Peak memory 224780 kb
Host smart-d6fa2388-ac01-4f27-aba9-fbd87005df3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029482800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.3029482800
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.4149269202
Short name T8
Test name
Test status
Simulation time 3320750541 ps
CPU time 24.94 seconds
Started Jun 05 05:21:01 PM PDT 24
Finished Jun 05 05:21:27 PM PDT 24
Peak memory 219296 kb
Host smart-d8d600f1-47df-4883-b59f-76a7da790f0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149269202 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.4149269202
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.2283982440
Short name T105
Test name
Test status
Simulation time 19281591 ps
CPU time 1.22 seconds
Started Jun 05 05:52:25 PM PDT 24
Finished Jun 05 05:52:27 PM PDT 24
Peak memory 219412 kb
Host smart-f4cb6c40-0f40-41be-8938-b5693091ccc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283982440 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.2283982440
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.812984561
Short name T30
Test name
Test status
Simulation time 37976450730 ps
CPU time 378.65 seconds
Started Jun 05 05:20:27 PM PDT 24
Finished Jun 05 05:26:47 PM PDT 24
Peak memory 283868 kb
Host smart-fd26317b-fb53-4ee4-9019-5833abbde7ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=812984561 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.812984561
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.2727141484
Short name T44
Test name
Test status
Simulation time 124025073 ps
CPU time 24.68 seconds
Started Jun 05 05:19:26 PM PDT 24
Finished Jun 05 05:19:51 PM PDT 24
Peak memory 281224 kb
Host smart-aa1d99cd-baa1-459c-8649-5e3330d23cd2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727141484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.2727141484
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.206828121
Short name T38
Test name
Test status
Simulation time 684986145 ps
CPU time 13.88 seconds
Started Jun 05 05:20:27 PM PDT 24
Finished Jun 05 05:20:41 PM PDT 24
Peak memory 217936 kb
Host smart-f82ec17b-f3f8-4211-86e6-0b2ed082006b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206828121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.206828121
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.3421414990
Short name T6
Test name
Test status
Simulation time 294806370 ps
CPU time 3.18 seconds
Started Jun 05 05:22:01 PM PDT 24
Finished Jun 05 05:22:05 PM PDT 24
Peak memory 209488 kb
Host smart-68399acd-020e-4b0f-8821-1f0267385680
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421414990 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.3421414990
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3852897636
Short name T109
Test name
Test status
Simulation time 119705048 ps
CPU time 2.87 seconds
Started Jun 05 05:52:43 PM PDT 24
Finished Jun 05 05:52:46 PM PDT 24
Peak memory 222488 kb
Host smart-91897e2d-ac17-4aea-a2a6-b5108f3af7a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852897636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.3852897636
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.145311664
Short name T28
Test name
Test status
Simulation time 75310367 ps
CPU time 1.14 seconds
Started Jun 05 05:20:35 PM PDT 24
Finished Jun 05 05:20:37 PM PDT 24
Peak memory 208904 kb
Host smart-09abe794-ecb1-4b63-b654-ce62e68fc195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145311664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.145311664
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.3514512098
Short name T112
Test name
Test status
Simulation time 1170813715 ps
CPU time 6.46 seconds
Started Jun 05 05:52:15 PM PDT 24
Finished Jun 05 05:52:22 PM PDT 24
Peak memory 209472 kb
Host smart-6fc480d7-6550-4774-b4b1-5a69f1b14ade
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514512098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.3514512098
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.993313381
Short name T170
Test name
Test status
Simulation time 125950293 ps
CPU time 0.98 seconds
Started Jun 05 05:52:18 PM PDT 24
Finished Jun 05 05:52:20 PM PDT 24
Peak memory 209868 kb
Host smart-17a79c84-c666-4be9-a8e5-048c2e7bf842
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993313381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasing
.993313381
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.1016545152
Short name T16
Test name
Test status
Simulation time 103906204950 ps
CPU time 441.15 seconds
Started Jun 05 05:19:27 PM PDT 24
Finished Jun 05 05:26:49 PM PDT 24
Peak memory 283828 kb
Host smart-11999aed-ba23-44fc-9f39-b49ef6a69ada
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1016545152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_stress_all_with_rand_reset.1016545152
Directory /workspace/0.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1132254693
Short name T104
Test name
Test status
Simulation time 116742926 ps
CPU time 4.66 seconds
Started Jun 05 05:52:27 PM PDT 24
Finished Jun 05 05:52:33 PM PDT 24
Peak memory 218192 kb
Host smart-3e184a0b-8788-442a-9f6b-66d566f49d2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132254693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1132254693
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.2754253738
Short name T115
Test name
Test status
Simulation time 426760944 ps
CPU time 3.91 seconds
Started Jun 05 05:52:19 PM PDT 24
Finished Jun 05 05:52:24 PM PDT 24
Peak memory 218152 kb
Host smart-3f747510-149b-4710-9384-13cdb82bf168
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754253738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.2754253738
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.738679920
Short name T121
Test name
Test status
Simulation time 992889904 ps
CPU time 2.7 seconds
Started Jun 05 05:52:30 PM PDT 24
Finished Jun 05 05:52:34 PM PDT 24
Peak memory 213856 kb
Host smart-0f3ce882-8d04-41d9-9a6b-e33e9ff79c05
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738679920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg_
err.738679920
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.4093776235
Short name T40
Test name
Test status
Simulation time 718422139 ps
CPU time 13.18 seconds
Started Jun 05 05:21:47 PM PDT 24
Finished Jun 05 05:22:01 PM PDT 24
Peak memory 224848 kb
Host smart-9cc7b1e0-74d2-4bff-8c95-07aaa8dd4728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093776235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.4093776235
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all.3461905380
Short name T50
Test name
Test status
Simulation time 17467387969 ps
CPU time 175.94 seconds
Started Jun 05 05:21:46 PM PDT 24
Finished Jun 05 05:24:43 PM PDT 24
Peak memory 250716 kb
Host smart-4604dbf1-351d-4eeb-ae39-1702d4c1e8ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461905380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
32.lc_ctrl_stress_all.3461905380
Directory /workspace/32.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.1447832452
Short name T17
Test name
Test status
Simulation time 2489004824 ps
CPU time 14.59 seconds
Started Jun 05 05:21:53 PM PDT 24
Finished Jun 05 05:22:09 PM PDT 24
Peak memory 219232 kb
Host smart-0d702ddc-25ee-4f3a-a049-90717f6c7208
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447832452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.1447832452
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2159728079
Short name T94
Test name
Test status
Simulation time 474069693 ps
CPU time 46.22 seconds
Started Jun 05 05:19:35 PM PDT 24
Finished Jun 05 05:20:22 PM PDT 24
Peak memory 282368 kb
Host smart-b624d638-1bae-4ffd-bb93-79bb6cfdd364
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159728079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2159728079
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.3674289095
Short name T123
Test name
Test status
Simulation time 79199832 ps
CPU time 3.45 seconds
Started Jun 05 05:52:28 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 218164 kb
Host smart-b9a2e351-9a92-4881-9484-347edc44ea35
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674289095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg
_err.3674289095
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.4120429514
Short name T176
Test name
Test status
Simulation time 17308183 ps
CPU time 1.03 seconds
Started Jun 05 05:52:18 PM PDT 24
Finished Jun 05 05:52:20 PM PDT 24
Peak memory 209996 kb
Host smart-b93b01ae-b8e3-4129-8d39-d1f49c4cc912
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120429514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.4120429514
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all_with_rand_reset.3864239140
Short name T83
Test name
Test status
Simulation time 40917178886 ps
CPU time 422.69 seconds
Started Jun 05 05:21:07 PM PDT 24
Finished Jun 05 05:28:10 PM PDT 24
Peak memory 283864 kb
Host smart-114ff10e-61b4-4781-9cd7-f2f2f0411f99
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3864239140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_stress_all_with_rand_reset.3864239140
Directory /workspace/21.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.3881329559
Short name T143
Test name
Test status
Simulation time 61147200 ps
CPU time 0.89 seconds
Started Jun 05 05:20:21 PM PDT 24
Finished Jun 05 05:20:23 PM PDT 24
Peak memory 211488 kb
Host smart-e56d0df7-bd85-4d7c-91da-b9cdaeed8399
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881329559 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.3881329559
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.917640279
Short name T122
Test name
Test status
Simulation time 307995713 ps
CPU time 3.38 seconds
Started Jun 05 05:52:23 PM PDT 24
Finished Jun 05 05:52:27 PM PDT 24
Peak memory 218364 kb
Host smart-49cf31b9-121f-4549-ac9f-8545825b2e9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917640279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg_
err.917640279
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.3197539031
Short name T119
Test name
Test status
Simulation time 58618868 ps
CPU time 2.56 seconds
Started Jun 05 05:52:48 PM PDT 24
Finished Jun 05 05:52:51 PM PDT 24
Peak memory 218160 kb
Host smart-5f4c5454-e7df-4240-841f-031b95df1332
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197539031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.3197539031
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.551424787
Short name T126
Test name
Test status
Simulation time 77548349 ps
CPU time 2.76 seconds
Started Jun 05 05:52:24 PM PDT 24
Finished Jun 05 05:52:28 PM PDT 24
Peak memory 223056 kb
Host smart-5a4e2541-577a-4783-b8a5-bec1b399b409
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551424787 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e
rr.551424787
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.45630314
Short name T187
Test name
Test status
Simulation time 36880855 ps
CPU time 0.87 seconds
Started Jun 05 05:19:28 PM PDT 24
Finished Jun 05 05:19:30 PM PDT 24
Peak memory 208688 kb
Host smart-cc83cb4c-bcdd-4289-9362-19498a2a79a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45630314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.45630314
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.693499067
Short name T188
Test name
Test status
Simulation time 74236891 ps
CPU time 0.93 seconds
Started Jun 05 05:19:27 PM PDT 24
Finished Jun 05 05:19:29 PM PDT 24
Peak memory 208720 kb
Host smart-c484ffe0-1121-4368-b68d-5837d02ff08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=693499067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.693499067
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1636603981
Short name T63
Test name
Test status
Simulation time 13599454 ps
CPU time 0.84 seconds
Started Jun 05 05:19:43 PM PDT 24
Finished Jun 05 05:19:44 PM PDT 24
Peak memory 208640 kb
Host smart-4f931f1a-4d17-416b-be85-63833c8bd1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636603981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1636603981
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1838672101
Short name T151
Test name
Test status
Simulation time 91253014 ps
CPU time 0.84 seconds
Started Jun 05 05:19:49 PM PDT 24
Finished Jun 05 05:19:50 PM PDT 24
Peak memory 208728 kb
Host smart-15a2c547-fa49-4cfb-abfe-5a14b5425da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838672101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1838672101
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.4143423754
Short name T185
Test name
Test status
Simulation time 10400297 ps
CPU time 0.96 seconds
Started Jun 05 05:20:14 PM PDT 24
Finished Jun 05 05:20:15 PM PDT 24
Peak memory 208672 kb
Host smart-a07d1b06-570a-44c0-b7e5-3d4f4fd37eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143423754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.4143423754
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1606181432
Short name T116
Test name
Test status
Simulation time 125979586 ps
CPU time 3.04 seconds
Started Jun 05 05:52:20 PM PDT 24
Finished Jun 05 05:52:24 PM PDT 24
Peak memory 223016 kb
Host smart-60630c77-569e-4d58-9a74-b79bcc7f6129
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606181432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.1606181432
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.850372623
Short name T131
Test name
Test status
Simulation time 85978229 ps
CPU time 2.43 seconds
Started Jun 05 05:52:41 PM PDT 24
Finished Jun 05 05:52:45 PM PDT 24
Peak memory 222684 kb
Host smart-7570cd29-0c41-4db6-a5fa-7200b6a40eaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850372623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_e
rr.850372623
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.1166145051
Short name T36
Test name
Test status
Simulation time 1662465568 ps
CPU time 12.63 seconds
Started Jun 05 05:21:45 PM PDT 24
Finished Jun 05 05:21:58 PM PDT 24
Peak memory 217936 kb
Host smart-f862557d-8f8a-429d-ba14-b4a2dc153b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166145051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.1166145051
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.221683260
Short name T144
Test name
Test status
Simulation time 6904444535 ps
CPU time 11.49 seconds
Started Jun 05 05:22:00 PM PDT 24
Finished Jun 05 05:22:12 PM PDT 24
Peak memory 226084 kb
Host smart-0a683a2d-50b9-49e1-b610-9e0c0fe2958b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221683260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_di
gest.221683260
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.1061522419
Short name T12
Test name
Test status
Simulation time 714047256 ps
CPU time 16.08 seconds
Started Jun 05 05:20:37 PM PDT 24
Finished Jun 05 05:20:54 PM PDT 24
Peak memory 217996 kb
Host smart-eee5459c-b88a-4f68-8f9a-06c90d49335b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061522419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.1061522419
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.798350516
Short name T54
Test name
Test status
Simulation time 2654291112 ps
CPU time 43.36 seconds
Started Jun 05 05:19:30 PM PDT 24
Finished Jun 05 05:20:14 PM PDT 24
Peak memory 242776 kb
Host smart-f2a77db0-c2fa-4548-a87c-68a8ef1aad82
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798350516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.798350516
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.47676597
Short name T168
Test name
Test status
Simulation time 372080900 ps
CPU time 1.25 seconds
Started Jun 05 05:52:24 PM PDT 24
Finished Jun 05 05:52:27 PM PDT 24
Peak memory 209864 kb
Host smart-2e853b9e-b5ca-4d06-9e83-4cbbb092060f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47676597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing.47676597
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.3241082833
Short name T928
Test name
Test status
Simulation time 37838345 ps
CPU time 1.78 seconds
Started Jun 05 05:52:45 PM PDT 24
Finished Jun 05 05:52:47 PM PDT 24
Peak memory 209140 kb
Host smart-3c061f1e-3b17-42eb-98f6-9b1e8ced1844
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241082833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.3241082833
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.564582869
Short name T938
Test name
Test status
Simulation time 16194802 ps
CPU time 1.21 seconds
Started Jun 05 05:52:23 PM PDT 24
Finished Jun 05 05:52:25 PM PDT 24
Peak memory 218636 kb
Host smart-49591a02-224b-430e-8f1a-72fa19b87e72
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564582869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_reset
.564582869
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3766238566
Short name T146
Test name
Test status
Simulation time 27617757 ps
CPU time 1.58 seconds
Started Jun 05 05:52:19 PM PDT 24
Finished Jun 05 05:52:22 PM PDT 24
Peak memory 218212 kb
Host smart-2c2b9f36-18b7-4152-a57c-afee00b1e12d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766238566 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.3766238566
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.2224327051
Short name T880
Test name
Test status
Simulation time 45649934 ps
CPU time 0.82 seconds
Started Jun 05 05:52:16 PM PDT 24
Finished Jun 05 05:52:18 PM PDT 24
Peak memory 209620 kb
Host smart-1da56377-075b-47fa-b95e-2851d98f69a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224327051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.2224327051
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.1649988016
Short name T992
Test name
Test status
Simulation time 314214077 ps
CPU time 1.27 seconds
Started Jun 05 05:52:16 PM PDT 24
Finished Jun 05 05:52:19 PM PDT 24
Peak memory 209724 kb
Host smart-a48e1ec3-4a73-4f28-b609-7dc72c23f104
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649988016 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.1649988016
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.103302468
Short name T919
Test name
Test status
Simulation time 2179328734 ps
CPU time 9.46 seconds
Started Jun 05 05:52:15 PM PDT 24
Finished Jun 05 05:52:25 PM PDT 24
Peak memory 217608 kb
Host smart-0ef21c11-d999-4157-baf0-dd4195ce266e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103302468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.103302468
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.4245861549
Short name T984
Test name
Test status
Simulation time 6066771999 ps
CPU time 16.87 seconds
Started Jun 05 05:52:15 PM PDT 24
Finished Jun 05 05:52:33 PM PDT 24
Peak memory 209752 kb
Host smart-fce9dba8-2785-41a8-8cd7-8a4e6abb927a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245861549 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.4245861549
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.1438609295
Short name T878
Test name
Test status
Simulation time 177428130 ps
CPU time 1.77 seconds
Started Jun 05 05:52:22 PM PDT 24
Finished Jun 05 05:52:24 PM PDT 24
Peak memory 211228 kb
Host smart-515d9a2a-86be-41a2-844b-f6fe18c631e9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438609295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.1438609295
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1105052654
Short name T931
Test name
Test status
Simulation time 58621560 ps
CPU time 1.44 seconds
Started Jun 05 05:52:17 PM PDT 24
Finished Jun 05 05:52:20 PM PDT 24
Peak memory 219280 kb
Host smart-e155d70a-dcef-4625-80d7-b62d42527d2b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110505
2654 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1105052654
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3199479325
Short name T908
Test name
Test status
Simulation time 261035311 ps
CPU time 1.38 seconds
Started Jun 05 05:52:19 PM PDT 24
Finished Jun 05 05:52:21 PM PDT 24
Peak memory 209800 kb
Host smart-4a07417b-e768-49e0-a0bf-6cb2d122edb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199479325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.3199479325
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3060154414
Short name T911
Test name
Test status
Simulation time 67319943 ps
CPU time 1.13 seconds
Started Jun 05 05:52:21 PM PDT 24
Finished Jun 05 05:52:23 PM PDT 24
Peak memory 209676 kb
Host smart-c815ac18-8ccf-4a50-9b61-7b5731f389a9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060154414 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.3060154414
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.2794299345
Short name T108
Test name
Test status
Simulation time 275837685 ps
CPU time 4.41 seconds
Started Jun 05 05:52:36 PM PDT 24
Finished Jun 05 05:52:41 PM PDT 24
Peak memory 218196 kb
Host smart-97addaee-0742-42c6-9296-b989136b5d8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794299345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.2794299345
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.1726326799
Short name T124
Test name
Test status
Simulation time 78972120 ps
CPU time 3.49 seconds
Started Jun 05 05:52:24 PM PDT 24
Finished Jun 05 05:52:29 PM PDT 24
Peak memory 218124 kb
Host smart-bc9c26d6-82db-47a9-8b0f-f675e6375601
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726326799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_
err.1726326799
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.2935174318
Short name T970
Test name
Test status
Simulation time 442366425 ps
CPU time 1.34 seconds
Started Jun 05 05:52:22 PM PDT 24
Finished Jun 05 05:52:25 PM PDT 24
Peak memory 217252 kb
Host smart-cb0e3df8-96df-4cb2-9096-9d9d09197513
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935174318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.2935174318
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2833729045
Short name T893
Test name
Test status
Simulation time 60280409 ps
CPU time 1.17 seconds
Started Jun 05 05:52:28 PM PDT 24
Finished Jun 05 05:52:30 PM PDT 24
Peak memory 218600 kb
Host smart-215949fd-37bf-44b7-ac79-0cab1c2c5876
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833729045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.2833729045
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.1157136022
Short name T899
Test name
Test status
Simulation time 19644718 ps
CPU time 1.31 seconds
Started Jun 05 05:52:16 PM PDT 24
Finished Jun 05 05:52:18 PM PDT 24
Peak memory 218180 kb
Host smart-798612d5-5c5a-469c-b5b7-b85c9b54bf5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157136022 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.1157136022
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1657525555
Short name T169
Test name
Test status
Simulation time 13633862 ps
CPU time 1.03 seconds
Started Jun 05 05:52:16 PM PDT 24
Finished Jun 05 05:52:18 PM PDT 24
Peak memory 209616 kb
Host smart-b0820715-6567-46c4-8ae5-0a57f6c370de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657525555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.1657525555
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.335060341
Short name T977
Test name
Test status
Simulation time 274434042 ps
CPU time 1.25 seconds
Started Jun 05 05:52:17 PM PDT 24
Finished Jun 05 05:52:20 PM PDT 24
Peak memory 209752 kb
Host smart-e325ac16-00d5-4d3c-8cfd-d709c1ef81a7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335060341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 1.lc_ctrl_jtag_alert_test.335060341
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3308563802
Short name T906
Test name
Test status
Simulation time 691058513 ps
CPU time 16.54 seconds
Started Jun 05 05:52:14 PM PDT 24
Finished Jun 05 05:52:31 PM PDT 24
Peak memory 209568 kb
Host smart-9491bac3-b0fe-44ae-8dea-415337b47097
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308563802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.3308563802
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.168102263
Short name T974
Test name
Test status
Simulation time 346925757 ps
CPU time 2.67 seconds
Started Jun 05 05:52:17 PM PDT 24
Finished Jun 05 05:52:21 PM PDT 24
Peak memory 211228 kb
Host smart-6b2fc923-c9b4-4492-a97d-6325ff461c1a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168102263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.168102263
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1061047577
Short name T909
Test name
Test status
Simulation time 272612209 ps
CPU time 1.7 seconds
Started Jun 05 05:52:34 PM PDT 24
Finished Jun 05 05:52:36 PM PDT 24
Peak memory 218192 kb
Host smart-52526432-72ed-4d03-b784-9aeb4723bc5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106104
7577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1061047577
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2812098971
Short name T972
Test name
Test status
Simulation time 1169291086 ps
CPU time 1.37 seconds
Started Jun 05 05:52:24 PM PDT 24
Finished Jun 05 05:52:27 PM PDT 24
Peak memory 217812 kb
Host smart-1c69b287-8c17-4aa2-8964-befe3092d9d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812098971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2812098971
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.1991992559
Short name T178
Test name
Test status
Simulation time 50708006 ps
CPU time 1.36 seconds
Started Jun 05 05:52:24 PM PDT 24
Finished Jun 05 05:52:27 PM PDT 24
Peak memory 218152 kb
Host smart-bdf1c421-3c4d-47ee-a374-259f8ffc5911
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991992559 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.1991992559
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3699563861
Short name T111
Test name
Test status
Simulation time 17927473 ps
CPU time 0.97 seconds
Started Jun 05 05:52:25 PM PDT 24
Finished Jun 05 05:52:27 PM PDT 24
Peak memory 210020 kb
Host smart-271f3ff7-e4ba-442f-979e-14f222f760dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699563861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl
_same_csr_outstanding.3699563861
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.4220314028
Short name T900
Test name
Test status
Simulation time 57155091 ps
CPU time 1.87 seconds
Started Jun 05 05:52:17 PM PDT 24
Finished Jun 05 05:52:20 PM PDT 24
Peak memory 218188 kb
Host smart-d2df6596-b30e-40e0-97b7-0f1d071f1d90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220314028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.4220314028
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1646762588
Short name T130
Test name
Test status
Simulation time 143205068 ps
CPU time 3.26 seconds
Started Jun 05 05:52:16 PM PDT 24
Finished Jun 05 05:52:20 PM PDT 24
Peak memory 222892 kb
Host smart-158f044d-22fe-454f-85b1-9b3245ed7a77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646762588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1646762588
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2197875434
Short name T902
Test name
Test status
Simulation time 85484101 ps
CPU time 1.6 seconds
Started Jun 05 05:52:22 PM PDT 24
Finished Jun 05 05:52:25 PM PDT 24
Peak memory 218140 kb
Host smart-01496eac-2432-4020-b6de-91df2baa8b49
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197875434 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2197875434
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.875125483
Short name T870
Test name
Test status
Simulation time 30620801 ps
CPU time 0.83 seconds
Started Jun 05 05:52:32 PM PDT 24
Finished Jun 05 05:52:34 PM PDT 24
Peak memory 209648 kb
Host smart-22314b5a-5d04-4894-9324-18f797c1c82b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875125483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.875125483
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.4120792800
Short name T983
Test name
Test status
Simulation time 49677027 ps
CPU time 1.44 seconds
Started Jun 05 05:52:29 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 211884 kb
Host smart-a5a097b5-7420-4551-aec3-d8d8cacddf6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120792800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr
l_same_csr_outstanding.4120792800
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2983510398
Short name T945
Test name
Test status
Simulation time 239055749 ps
CPU time 2.04 seconds
Started Jun 05 05:52:24 PM PDT 24
Finished Jun 05 05:52:28 PM PDT 24
Peak memory 218356 kb
Host smart-ea93be31-fdca-482b-a442-9eb0f15d14d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983510398 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2983510398
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1119014378
Short name T125
Test name
Test status
Simulation time 268762410 ps
CPU time 3.26 seconds
Started Jun 05 05:52:31 PM PDT 24
Finished Jun 05 05:52:45 PM PDT 24
Peak memory 222860 kb
Host smart-f03ff69f-96ea-4144-930f-5cca3b846609
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119014378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1119014378
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3841922535
Short name T939
Test name
Test status
Simulation time 49424927 ps
CPU time 0.89 seconds
Started Jun 05 05:52:22 PM PDT 24
Finished Jun 05 05:52:24 PM PDT 24
Peak memory 209840 kb
Host smart-fa924cc1-39a9-43c5-a76d-b2a6ec4e1e98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841922535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3841922535
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.650513936
Short name T177
Test name
Test status
Simulation time 21584592 ps
CPU time 1.22 seconds
Started Jun 05 05:52:23 PM PDT 24
Finished Jun 05 05:52:25 PM PDT 24
Peak memory 209956 kb
Host smart-79aa9775-db01-40ec-816e-0309ce68cc14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650513936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.650513936
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.288327391
Short name T120
Test name
Test status
Simulation time 99376124 ps
CPU time 2.44 seconds
Started Jun 05 05:52:41 PM PDT 24
Finished Jun 05 05:52:44 PM PDT 24
Peak memory 218196 kb
Host smart-52cc2da2-165b-4874-b2b0-170ce475a39a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288327391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.288327391
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.3190510179
Short name T117
Test name
Test status
Simulation time 28160596 ps
CPU time 1.63 seconds
Started Jun 05 05:52:22 PM PDT 24
Finished Jun 05 05:52:25 PM PDT 24
Peak memory 223608 kb
Host smart-335fe5bc-0aa2-48d9-99b9-b9931773abf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190510179 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.3190510179
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.2991287420
Short name T922
Test name
Test status
Simulation time 15979392 ps
CPU time 1.03 seconds
Started Jun 05 05:52:26 PM PDT 24
Finished Jun 05 05:52:28 PM PDT 24
Peak memory 209864 kb
Host smart-05b4e7ea-80ab-4395-944a-8633037fb46a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991287420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.2991287420
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.1691685889
Short name T966
Test name
Test status
Simulation time 152906139 ps
CPU time 1.81 seconds
Started Jun 05 05:52:43 PM PDT 24
Finished Jun 05 05:52:45 PM PDT 24
Peak memory 217932 kb
Host smart-6aeec157-a818-47b7-9c34-804fa11cfdcc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691685889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.1691685889
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2052471177
Short name T896
Test name
Test status
Simulation time 29405253 ps
CPU time 2.14 seconds
Started Jun 05 05:52:25 PM PDT 24
Finished Jun 05 05:52:28 PM PDT 24
Peak memory 218300 kb
Host smart-452dfd0c-48a2-42cc-98b2-c188ec1f559d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052471177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2052471177
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1147750248
Short name T118
Test name
Test status
Simulation time 85744894 ps
CPU time 1.68 seconds
Started Jun 05 05:52:51 PM PDT 24
Finished Jun 05 05:52:53 PM PDT 24
Peak memory 218268 kb
Host smart-836b8e56-d313-481d-83f9-4f5e6315364b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147750248 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1147750248
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.2401672249
Short name T871
Test name
Test status
Simulation time 39033513 ps
CPU time 0.96 seconds
Started Jun 05 05:52:28 PM PDT 24
Finished Jun 05 05:52:30 PM PDT 24
Peak memory 209864 kb
Host smart-e800341a-f9af-486c-80ac-0d35e95d7dfc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401672249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.2401672249
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.3425854634
Short name T113
Test name
Test status
Simulation time 181550838 ps
CPU time 1.79 seconds
Started Jun 05 05:52:33 PM PDT 24
Finished Jun 05 05:52:36 PM PDT 24
Peak memory 209948 kb
Host smart-57d05cd3-b9f6-47c0-8dcb-5b797de60e7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425854634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.3425854634
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1091814400
Short name T952
Test name
Test status
Simulation time 83768047 ps
CPU time 2.54 seconds
Started Jun 05 05:52:28 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 218192 kb
Host smart-170b3f71-0f39-4f2b-a3f3-6f3fdc37fb79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091814400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.1091814400
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2884834202
Short name T897
Test name
Test status
Simulation time 79706688 ps
CPU time 1.22 seconds
Started Jun 05 05:52:36 PM PDT 24
Finished Jun 05 05:52:38 PM PDT 24
Peak memory 219272 kb
Host smart-90923f01-003c-4d5b-8803-afebd271cbbf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884834202 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2884834202
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.3223791762
Short name T978
Test name
Test status
Simulation time 26009774 ps
CPU time 0.92 seconds
Started Jun 05 05:52:28 PM PDT 24
Finished Jun 05 05:52:30 PM PDT 24
Peak memory 209880 kb
Host smart-7070d855-16a4-4059-8265-8e01dd34d31e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223791762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.3223791762
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.527162312
Short name T905
Test name
Test status
Simulation time 18573842 ps
CPU time 1.01 seconds
Started Jun 05 05:52:43 PM PDT 24
Finished Jun 05 05:52:44 PM PDT 24
Peak memory 210016 kb
Host smart-d17c8332-0c74-46e2-b740-9c94d2cccc56
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527162312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_same_csr_outstanding.527162312
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.733577707
Short name T881
Test name
Test status
Simulation time 61459176 ps
CPU time 2.75 seconds
Started Jun 05 05:52:46 PM PDT 24
Finished Jun 05 05:52:49 PM PDT 24
Peak memory 218328 kb
Host smart-69fec6d5-d3f1-41d7-a03c-a2d87986fb81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733577707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.733577707
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.4221352716
Short name T132
Test name
Test status
Simulation time 122896865 ps
CPU time 2.98 seconds
Started Jun 05 05:52:33 PM PDT 24
Finished Jun 05 05:52:36 PM PDT 24
Peak memory 222780 kb
Host smart-740ee012-c883-4350-80d2-bc9e50e2a99b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221352716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg
_err.4221352716
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2439439597
Short name T147
Test name
Test status
Simulation time 29405546 ps
CPU time 1.35 seconds
Started Jun 05 05:52:37 PM PDT 24
Finished Jun 05 05:52:39 PM PDT 24
Peak memory 223120 kb
Host smart-aebfc7c4-37d8-47f7-a2e6-793aebd9061a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439439597 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2439439597
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.3670518359
Short name T166
Test name
Test status
Simulation time 17546595 ps
CPU time 0.8 seconds
Started Jun 05 05:52:43 PM PDT 24
Finished Jun 05 05:52:44 PM PDT 24
Peak memory 209708 kb
Host smart-f994399d-7a28-4c05-8d3c-cdc2f1657904
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670518359 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.3670518359
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.2970813822
Short name T174
Test name
Test status
Simulation time 48383224 ps
CPU time 1.36 seconds
Started Jun 05 05:52:24 PM PDT 24
Finished Jun 05 05:52:27 PM PDT 24
Peak memory 217736 kb
Host smart-cd338711-8501-4f44-8f59-d5fd50db29c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970813822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctr
l_same_csr_outstanding.2970813822
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1299418190
Short name T887
Test name
Test status
Simulation time 60777318 ps
CPU time 2.56 seconds
Started Jun 05 05:52:24 PM PDT 24
Finished Jun 05 05:52:28 PM PDT 24
Peak memory 218204 kb
Host smart-55421584-ccfe-42e0-8b32-430b178ab922
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299418190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.1299418190
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.1387813240
Short name T103
Test name
Test status
Simulation time 121526668 ps
CPU time 1.28 seconds
Started Jun 05 05:52:29 PM PDT 24
Finished Jun 05 05:52:31 PM PDT 24
Peak memory 220328 kb
Host smart-dfcf9cdd-fd5c-4cbe-91d6-ec92fe797ffc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387813240 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.1387813240
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1655253980
Short name T940
Test name
Test status
Simulation time 85092324 ps
CPU time 0.92 seconds
Started Jun 05 05:52:31 PM PDT 24
Finished Jun 05 05:52:33 PM PDT 24
Peak memory 209680 kb
Host smart-377d1895-981e-4c3b-86ec-da7584835450
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655253980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1655253980
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2903263209
Short name T179
Test name
Test status
Simulation time 38465780 ps
CPU time 1.29 seconds
Started Jun 05 05:52:20 PM PDT 24
Finished Jun 05 05:52:22 PM PDT 24
Peak memory 211964 kb
Host smart-5bbf481c-36c2-4fac-8fb3-67289aeb190e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903263209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.2903263209
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3639758837
Short name T921
Test name
Test status
Simulation time 111959161 ps
CPU time 3.16 seconds
Started Jun 05 05:52:43 PM PDT 24
Finished Jun 05 05:52:47 PM PDT 24
Peak memory 219204 kb
Host smart-5501ad8f-782d-44a7-a5c8-79cb81e1296e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639758837 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3639758837
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2748717014
Short name T961
Test name
Test status
Simulation time 830723988 ps
CPU time 2.57 seconds
Started Jun 05 05:52:20 PM PDT 24
Finished Jun 05 05:52:24 PM PDT 24
Peak memory 218096 kb
Host smart-ee0c5518-11b9-4a40-b40e-7c03491fa0c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748717014 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg
_err.2748717014
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.673343598
Short name T986
Test name
Test status
Simulation time 36371395 ps
CPU time 1.29 seconds
Started Jun 05 05:52:37 PM PDT 24
Finished Jun 05 05:52:39 PM PDT 24
Peak memory 219296 kb
Host smart-34dd549e-205d-4574-9bc2-0e780af9345a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673343598 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.673343598
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.3546086602
Short name T167
Test name
Test status
Simulation time 12565555 ps
CPU time 1.01 seconds
Started Jun 05 05:52:24 PM PDT 24
Finished Jun 05 05:52:27 PM PDT 24
Peak memory 210024 kb
Host smart-70e5ed30-1fa4-423e-962b-887f470c1bd5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546086602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.3546086602
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.660110935
Short name T948
Test name
Test status
Simulation time 20770556 ps
CPU time 1.27 seconds
Started Jun 05 05:52:24 PM PDT 24
Finished Jun 05 05:52:27 PM PDT 24
Peak memory 218268 kb
Host smart-44679e0c-97fc-42e2-a882-6dfa38e4b68a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660110935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_same_csr_outstanding.660110935
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.267916369
Short name T148
Test name
Test status
Simulation time 159956555 ps
CPU time 1.45 seconds
Started Jun 05 05:52:29 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 219200 kb
Host smart-fa7c3233-e5a0-4142-b27e-6369d342c9a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267916369 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.267916369
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.447942211
Short name T161
Test name
Test status
Simulation time 24411299 ps
CPU time 1.11 seconds
Started Jun 05 05:53:01 PM PDT 24
Finished Jun 05 05:53:03 PM PDT 24
Peak memory 209876 kb
Host smart-bb4ff1cb-ce7e-4d5b-a0a9-7250b9aadc48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447942211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.447942211
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3809089923
Short name T956
Test name
Test status
Simulation time 45822354 ps
CPU time 1.08 seconds
Started Jun 05 05:52:39 PM PDT 24
Finished Jun 05 05:52:41 PM PDT 24
Peak memory 209896 kb
Host smart-76deb483-852d-47cd-a400-e1088b764bf6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809089923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr
l_same_csr_outstanding.3809089923
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.238169914
Short name T953
Test name
Test status
Simulation time 92159008 ps
CPU time 2.29 seconds
Started Jun 05 05:52:28 PM PDT 24
Finished Jun 05 05:52:31 PM PDT 24
Peak memory 218176 kb
Host smart-84ebec56-b4b0-4fb2-8436-6f402b388be0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238169914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.238169914
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3182364277
Short name T107
Test name
Test status
Simulation time 54930145 ps
CPU time 2.01 seconds
Started Jun 05 05:52:32 PM PDT 24
Finished Jun 05 05:52:35 PM PDT 24
Peak memory 222220 kb
Host smart-27ae4e5f-4f6d-4227-a933-4c6cf8f1a8a2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182364277 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3182364277
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.2396006674
Short name T912
Test name
Test status
Simulation time 15564059 ps
CPU time 1.22 seconds
Started Jun 05 05:52:52 PM PDT 24
Finished Jun 05 05:52:54 PM PDT 24
Peak memory 218272 kb
Host smart-61a75bdd-40ba-4914-aee6-0bbc64033366
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396006674 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.2396006674
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.2709883145
Short name T872
Test name
Test status
Simulation time 18287033 ps
CPU time 1.18 seconds
Started Jun 05 05:53:01 PM PDT 24
Finished Jun 05 05:53:04 PM PDT 24
Peak memory 209872 kb
Host smart-012e9e62-7f10-4a89-b6af-b81dd079beaf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709883145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.2709883145
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.2090002965
Short name T932
Test name
Test status
Simulation time 15361323 ps
CPU time 1.2 seconds
Started Jun 05 05:52:34 PM PDT 24
Finished Jun 05 05:52:36 PM PDT 24
Peak memory 209948 kb
Host smart-30da217a-7444-4c9f-abea-833c31f29be7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090002965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.2090002965
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.2398630299
Short name T936
Test name
Test status
Simulation time 29368189 ps
CPU time 1.91 seconds
Started Jun 05 05:52:19 PM PDT 24
Finished Jun 05 05:52:22 PM PDT 24
Peak memory 218188 kb
Host smart-48d9be9c-43cd-41df-9d3d-3a20428b9cea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398630299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.2398630299
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.130581138
Short name T164
Test name
Test status
Simulation time 25405013 ps
CPU time 1 seconds
Started Jun 05 05:52:31 PM PDT 24
Finished Jun 05 05:52:33 PM PDT 24
Peak memory 209864 kb
Host smart-942677aa-fe5c-44f1-a862-a45794dfb2e8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130581138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasing
.130581138
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.456820518
Short name T894
Test name
Test status
Simulation time 273488414 ps
CPU time 2.43 seconds
Started Jun 05 05:52:19 PM PDT 24
Finished Jun 05 05:52:23 PM PDT 24
Peak memory 217244 kb
Host smart-a8806f57-ca5c-4d34-a585-15b8cd4520f6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456820518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash
.456820518
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.384481768
Short name T886
Test name
Test status
Simulation time 59290078 ps
CPU time 0.93 seconds
Started Jun 05 05:52:14 PM PDT 24
Finished Jun 05 05:52:15 PM PDT 24
Peak memory 211004 kb
Host smart-baa79625-3e34-4114-b54f-18ac9c168ac6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384481768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_reset
.384481768
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.959641636
Short name T879
Test name
Test status
Simulation time 24976735 ps
CPU time 1.17 seconds
Started Jun 05 05:52:29 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 218188 kb
Host smart-0db0f3c2-6947-406f-969a-280ef4852d7f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959641636 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.959641636
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.276717074
Short name T172
Test name
Test status
Simulation time 173693582 ps
CPU time 0.99 seconds
Started Jun 05 05:52:46 PM PDT 24
Finished Jun 05 05:52:47 PM PDT 24
Peak memory 209840 kb
Host smart-a3272c34-0016-4c12-93eb-af2909f568e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276717074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.276717074
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2153853724
Short name T955
Test name
Test status
Simulation time 680493974 ps
CPU time 2.18 seconds
Started Jun 05 05:52:31 PM PDT 24
Finished Jun 05 05:52:35 PM PDT 24
Peak memory 209708 kb
Host smart-ba13b7eb-7578-44e9-bc67-0827b0a24d59
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153853724 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2153853724
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1076452124
Short name T910
Test name
Test status
Simulation time 370102692 ps
CPU time 8.7 seconds
Started Jun 05 05:52:21 PM PDT 24
Finished Jun 05 05:52:31 PM PDT 24
Peak memory 217592 kb
Host smart-ddcaee6e-b153-4944-a1c6-e0684f8240f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076452124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.1076452124
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.919567674
Short name T877
Test name
Test status
Simulation time 17823973424 ps
CPU time 20.4 seconds
Started Jun 05 05:52:20 PM PDT 24
Finished Jun 05 05:52:41 PM PDT 24
Peak memory 209888 kb
Host smart-89246f0b-d1c8-4648-be24-50f828afaa00
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919567674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.919567674
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.641863429
Short name T891
Test name
Test status
Simulation time 607282362 ps
CPU time 1.99 seconds
Started Jun 05 05:52:18 PM PDT 24
Finished Jun 05 05:52:22 PM PDT 24
Peak memory 211404 kb
Host smart-0ca132a4-1bcb-4c10-9571-39a621add5c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641863429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.641863429
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2638944785
Short name T934
Test name
Test status
Simulation time 392533614 ps
CPU time 2 seconds
Started Jun 05 05:52:19 PM PDT 24
Finished Jun 05 05:52:22 PM PDT 24
Peak memory 222288 kb
Host smart-162dbac0-e104-4855-88fc-0858ec39318e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263894
4785 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2638944785
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1197774926
Short name T898
Test name
Test status
Simulation time 1418361941 ps
CPU time 4.36 seconds
Started Jun 05 05:52:18 PM PDT 24
Finished Jun 05 05:52:24 PM PDT 24
Peak memory 209784 kb
Host smart-f4d09515-5748-4ecd-af3a-dd2088d0c404
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197774926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.1197774926
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.828282330
Short name T965
Test name
Test status
Simulation time 151250430 ps
CPU time 1.42 seconds
Started Jun 05 05:52:28 PM PDT 24
Finished Jun 05 05:52:31 PM PDT 24
Peak memory 212080 kb
Host smart-4ea435d6-ae5c-4416-abcc-db659dccd82a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828282330 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.828282330
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.2273039851
Short name T173
Test name
Test status
Simulation time 66211026 ps
CPU time 1.27 seconds
Started Jun 05 05:52:16 PM PDT 24
Finished Jun 05 05:52:18 PM PDT 24
Peak memory 218216 kb
Host smart-3e0dbd83-8ecf-469a-ad8d-ed3a9973fa5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273039851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.2273039851
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.287808699
Short name T996
Test name
Test status
Simulation time 246621806 ps
CPU time 2.52 seconds
Started Jun 05 05:52:17 PM PDT 24
Finished Jun 05 05:52:21 PM PDT 24
Peak memory 218192 kb
Host smart-7b610e46-fa6a-47a3-b1ab-5cb1679992ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287808699 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.287808699
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.638612829
Short name T129
Test name
Test status
Simulation time 648729620 ps
CPU time 3.53 seconds
Started Jun 05 05:52:25 PM PDT 24
Finished Jun 05 05:52:30 PM PDT 24
Peak memory 218100 kb
Host smart-241c9833-ad4c-4189-8c7f-397e68d61944
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638612829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_e
rr.638612829
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.1097836511
Short name T171
Test name
Test status
Simulation time 134014896 ps
CPU time 1.22 seconds
Started Jun 05 05:52:44 PM PDT 24
Finished Jun 05 05:52:46 PM PDT 24
Peak memory 209152 kb
Host smart-a16f0970-c5f5-41a6-a1b6-60ed17d2e8b1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097836511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.1097836511
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.4280091872
Short name T883
Test name
Test status
Simulation time 93304601 ps
CPU time 1.64 seconds
Started Jun 05 05:52:34 PM PDT 24
Finished Jun 05 05:52:36 PM PDT 24
Peak memory 209336 kb
Host smart-9f84e3a7-2148-4bdd-b03f-83f36a74678a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280091872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.4280091872
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.3876490271
Short name T925
Test name
Test status
Simulation time 43602906 ps
CPU time 0.86 seconds
Started Jun 05 05:52:36 PM PDT 24
Finished Jun 05 05:52:37 PM PDT 24
Peak memory 210272 kb
Host smart-97150f00-16d3-46b9-b786-0bb22de5d4b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876490271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.3876490271
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1595699747
Short name T885
Test name
Test status
Simulation time 20347797 ps
CPU time 0.94 seconds
Started Jun 05 05:52:16 PM PDT 24
Finished Jun 05 05:52:18 PM PDT 24
Peak memory 218096 kb
Host smart-48d3bb63-e560-42c6-a814-1351ff3c61c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595699747 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.1595699747
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2915061001
Short name T163
Test name
Test status
Simulation time 53379000 ps
CPU time 0.91 seconds
Started Jun 05 05:53:00 PM PDT 24
Finished Jun 05 05:53:02 PM PDT 24
Peak memory 209860 kb
Host smart-bb9d8dd8-1975-4bd9-9940-9ede7121f447
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915061001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2915061001
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.769500436
Short name T976
Test name
Test status
Simulation time 21852867 ps
CPU time 1.28 seconds
Started Jun 05 05:52:15 PM PDT 24
Finished Jun 05 05:52:17 PM PDT 24
Peak memory 209788 kb
Host smart-2b06ade0-6fa8-4bed-8e16-49f9c989f66c
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769500436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 3.lc_ctrl_jtag_alert_test.769500436
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2172843634
Short name T987
Test name
Test status
Simulation time 9180292001 ps
CPU time 17.11 seconds
Started Jun 05 05:52:16 PM PDT 24
Finished Jun 05 05:52:34 PM PDT 24
Peak memory 209884 kb
Host smart-b534d5e3-e351-476c-a49a-8ee710ab270c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172843634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2172843634
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.445135148
Short name T895
Test name
Test status
Simulation time 17495457452 ps
CPU time 8.91 seconds
Started Jun 05 05:52:19 PM PDT 24
Finished Jun 05 05:52:30 PM PDT 24
Peak memory 209704 kb
Host smart-56e51f9e-f6ba-4b14-8b07-f3fbe2032310
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445135148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.445135148
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3549842200
Short name T873
Test name
Test status
Simulation time 263211201 ps
CPU time 1.98 seconds
Started Jun 05 05:52:17 PM PDT 24
Finished Jun 05 05:52:20 PM PDT 24
Peak memory 211356 kb
Host smart-643ef562-bf8d-49b0-9358-b09ca2db5f0b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549842200 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.3549842200
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1900892683
Short name T904
Test name
Test status
Simulation time 943649676 ps
CPU time 2.3 seconds
Started Jun 05 05:52:22 PM PDT 24
Finished Jun 05 05:52:25 PM PDT 24
Peak memory 218212 kb
Host smart-8f9798a5-c5f9-4676-b72d-04f656186645
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190089
2683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1900892683
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.55664824
Short name T991
Test name
Test status
Simulation time 135157340 ps
CPU time 1.03 seconds
Started Jun 05 05:52:25 PM PDT 24
Finished Jun 05 05:52:27 PM PDT 24
Peak memory 217824 kb
Host smart-1e77865a-d36d-46d7-ae90-3d8a573686da
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55664824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 3.lc_ctrl_jtag_csr_rw.55664824
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2888517568
Short name T971
Test name
Test status
Simulation time 66296147 ps
CPU time 1.22 seconds
Started Jun 05 05:52:31 PM PDT 24
Finished Jun 05 05:52:33 PM PDT 24
Peak memory 218136 kb
Host smart-28a1a133-c041-470c-9469-fa7b92694cef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888517568 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.2888517568
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1662350247
Short name T924
Test name
Test status
Simulation time 32799868 ps
CPU time 1.2 seconds
Started Jun 05 05:52:59 PM PDT 24
Finished Jun 05 05:53:01 PM PDT 24
Peak memory 209664 kb
Host smart-2517fa48-d346-446a-8e42-984ed24a6b6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662350247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1662350247
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.840862875
Short name T994
Test name
Test status
Simulation time 206023330 ps
CPU time 2.21 seconds
Started Jun 05 05:52:20 PM PDT 24
Finished Jun 05 05:52:23 PM PDT 24
Peak memory 218408 kb
Host smart-d522e946-ff3a-4533-8281-45200bcae70f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840862875 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.840862875
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.18691847
Short name T942
Test name
Test status
Simulation time 46205977 ps
CPU time 1.09 seconds
Started Jun 05 05:52:28 PM PDT 24
Finished Jun 05 05:52:30 PM PDT 24
Peak memory 209864 kb
Host smart-6f50642c-af47-45fb-9af1-5e4138ff57cb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18691847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasing.18691847
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3689013159
Short name T874
Test name
Test status
Simulation time 657683207 ps
CPU time 2 seconds
Started Jun 05 05:52:28 PM PDT 24
Finished Jun 05 05:52:31 PM PDT 24
Peak memory 209864 kb
Host smart-9c33f33f-3ea1-43ea-a1f6-342efb132e33
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689013159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas
h.3689013159
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.329946156
Short name T181
Test name
Test status
Simulation time 35088398 ps
CPU time 0.95 seconds
Started Jun 05 05:52:28 PM PDT 24
Finished Jun 05 05:52:30 PM PDT 24
Peak memory 210312 kb
Host smart-4eeadba3-a46b-4cb5-99d0-41a4f36dbd11
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329946156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_reset
.329946156
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.1019208222
Short name T890
Test name
Test status
Simulation time 20348044 ps
CPU time 1.36 seconds
Started Jun 05 05:52:27 PM PDT 24
Finished Jun 05 05:52:29 PM PDT 24
Peak memory 220428 kb
Host smart-307710a8-d2b2-40bd-b8d8-7e87103b71c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019208222 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.1019208222
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.1178841354
Short name T165
Test name
Test status
Simulation time 12543072 ps
CPU time 0.96 seconds
Started Jun 05 05:52:30 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 209332 kb
Host smart-2f678fe6-f6d1-4a67-b217-37b8c76f8ee1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178841354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.1178841354
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.4175093077
Short name T969
Test name
Test status
Simulation time 67695286 ps
CPU time 1.48 seconds
Started Jun 05 05:52:29 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 209728 kb
Host smart-a0ed78aa-d3df-41f0-a707-ee8a11cc5b97
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175093077 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.4175093077
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.666050567
Short name T993
Test name
Test status
Simulation time 3281794320 ps
CPU time 4.82 seconds
Started Jun 05 05:52:18 PM PDT 24
Finished Jun 05 05:52:24 PM PDT 24
Peak memory 217884 kb
Host smart-2495d51c-705d-4d44-92cc-ccc80ad7dea6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666050567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.666050567
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.3474570089
Short name T975
Test name
Test status
Simulation time 4497691468 ps
CPU time 21.95 seconds
Started Jun 05 05:52:30 PM PDT 24
Finished Jun 05 05:52:53 PM PDT 24
Peak memory 209800 kb
Host smart-d4970498-114e-4d5e-8a10-7e55642848d6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474570089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.3474570089
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.4137234192
Short name T888
Test name
Test status
Simulation time 324466840 ps
CPU time 2.73 seconds
Started Jun 05 05:52:17 PM PDT 24
Finished Jun 05 05:52:21 PM PDT 24
Peak memory 211720 kb
Host smart-1deb92c3-d6ae-4737-92f7-f5f05ab3dfd6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137234192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.4137234192
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2662356761
Short name T927
Test name
Test status
Simulation time 228243629 ps
CPU time 2.53 seconds
Started Jun 05 05:52:33 PM PDT 24
Finished Jun 05 05:52:46 PM PDT 24
Peak memory 219760 kb
Host smart-b923d06f-a5db-44a2-85c3-a472631ac3e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266235
6761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2662356761
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2977766178
Short name T882
Test name
Test status
Simulation time 133214091 ps
CPU time 1.45 seconds
Started Jun 05 05:52:24 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 209812 kb
Host smart-7abe5b33-2690-44fe-bb3d-d82b021fe446
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977766178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.2977766178
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.4152436649
Short name T930
Test name
Test status
Simulation time 183081035 ps
CPU time 1.9 seconds
Started Jun 05 05:52:22 PM PDT 24
Finished Jun 05 05:52:25 PM PDT 24
Peak memory 218076 kb
Host smart-c28f10e8-e34e-41fc-88d7-dd04e1a2acf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152436649 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.4152436649
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.1742053423
Short name T964
Test name
Test status
Simulation time 19657956 ps
CPU time 1.26 seconds
Started Jun 05 05:52:19 PM PDT 24
Finished Jun 05 05:52:21 PM PDT 24
Peak memory 209744 kb
Host smart-781a5a94-9ad5-4fad-bf01-99cf801d9eaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742053423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl
_same_csr_outstanding.1742053423
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1659418955
Short name T985
Test name
Test status
Simulation time 576678853 ps
CPU time 3.95 seconds
Started Jun 05 05:52:23 PM PDT 24
Finished Jun 05 05:52:28 PM PDT 24
Peak memory 218200 kb
Host smart-fa17552c-30d6-43e7-8878-ae91ccbc188c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659418955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1659418955
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.4139567716
Short name T933
Test name
Test status
Simulation time 183086843 ps
CPU time 2.18 seconds
Started Jun 05 05:52:23 PM PDT 24
Finished Jun 05 05:52:27 PM PDT 24
Peak memory 218132 kb
Host smart-df55364b-6b88-4aca-9932-7986144ca328
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139567716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_
err.4139567716
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.1303116794
Short name T979
Test name
Test status
Simulation time 66324427 ps
CPU time 1.27 seconds
Started Jun 05 05:52:22 PM PDT 24
Finished Jun 05 05:52:24 PM PDT 24
Peak memory 218308 kb
Host smart-0c1b62db-1ca1-41fb-abaf-3cd6eefc8c9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303116794 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.1303116794
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.2632238068
Short name T982
Test name
Test status
Simulation time 19540917 ps
CPU time 0.89 seconds
Started Jun 05 05:52:30 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 209464 kb
Host smart-b1d43219-eac6-477d-a105-7a1dcabca93f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632238068 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.2632238068
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.923541533
Short name T949
Test name
Test status
Simulation time 119012100 ps
CPU time 1.79 seconds
Started Jun 05 05:52:29 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 209764 kb
Host smart-fd9e1bc6-efd8-4c74-9099-eb8e7eb8b742
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923541533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 5.lc_ctrl_jtag_alert_test.923541533
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.2085023857
Short name T876
Test name
Test status
Simulation time 448279601 ps
CPU time 11.2 seconds
Started Jun 05 05:52:28 PM PDT 24
Finished Jun 05 05:52:41 PM PDT 24
Peak memory 209772 kb
Host smart-6a25f30b-9873-4c34-8165-e2308fd096e9
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085023857 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.2085023857
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1236465210
Short name T135
Test name
Test status
Simulation time 2286381342 ps
CPU time 13.95 seconds
Started Jun 05 05:52:19 PM PDT 24
Finished Jun 05 05:52:34 PM PDT 24
Peak memory 210020 kb
Host smart-e897aaad-bb66-4eac-8ccd-8fb70abb12f1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236465210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.1236465210
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1809812544
Short name T941
Test name
Test status
Simulation time 203412787 ps
CPU time 2.24 seconds
Started Jun 05 05:52:17 PM PDT 24
Finished Jun 05 05:52:21 PM PDT 24
Peak memory 211380 kb
Host smart-4f40eeda-73eb-4553-8901-8153f1375c53
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809812544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1809812544
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1230170284
Short name T903
Test name
Test status
Simulation time 101882476 ps
CPU time 3.7 seconds
Started Jun 05 05:52:18 PM PDT 24
Finished Jun 05 05:52:23 PM PDT 24
Peak memory 219928 kb
Host smart-734fd62e-6e79-4413-85fa-f2fd0cc43905
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123017
0284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1230170284
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1774224213
Short name T957
Test name
Test status
Simulation time 163946595 ps
CPU time 1.31 seconds
Started Jun 05 05:52:42 PM PDT 24
Finished Jun 05 05:52:44 PM PDT 24
Peak memory 209724 kb
Host smart-d348a5bf-88ca-410b-91fe-726949785a9f
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774224213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1774224213
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3753744848
Short name T136
Test name
Test status
Simulation time 36778340 ps
CPU time 1.26 seconds
Started Jun 05 05:52:23 PM PDT 24
Finished Jun 05 05:52:25 PM PDT 24
Peak memory 209940 kb
Host smart-fd8ce30b-61d1-4e89-a8af-cffc4f2c6ca1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753744848 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.3753744848
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.8765467
Short name T889
Test name
Test status
Simulation time 42416848 ps
CPU time 1.04 seconds
Started Jun 05 05:52:30 PM PDT 24
Finished Jun 05 05:52:33 PM PDT 24
Peak memory 209944 kb
Host smart-da028ee8-e592-43d4-9348-25d7e9a9dc04
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8765467 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ct
rl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sa
me_csr_outstanding.8765467
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.3241893762
Short name T944
Test name
Test status
Simulation time 211615623 ps
CPU time 2.9 seconds
Started Jun 05 05:52:30 PM PDT 24
Finished Jun 05 05:52:34 PM PDT 24
Peak memory 218264 kb
Host smart-02d16d7f-28f5-4c6a-b2fb-e2930d82b555
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241893762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.3241893762
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.1889064397
Short name T127
Test name
Test status
Simulation time 341292831 ps
CPU time 3.32 seconds
Started Jun 05 05:52:29 PM PDT 24
Finished Jun 05 05:52:34 PM PDT 24
Peak memory 223000 kb
Host smart-aa6fb821-b7a4-48a0-9df9-483dcde24f4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889064397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.1889064397
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3732575024
Short name T959
Test name
Test status
Simulation time 74960381 ps
CPU time 1.61 seconds
Started Jun 05 05:52:33 PM PDT 24
Finished Jun 05 05:52:36 PM PDT 24
Peak memory 219204 kb
Host smart-e1021c03-d4e1-4a72-acc7-3aecf635e70d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732575024 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3732575024
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.1605734805
Short name T980
Test name
Test status
Simulation time 43438437 ps
CPU time 0.97 seconds
Started Jun 05 05:52:36 PM PDT 24
Finished Jun 05 05:52:37 PM PDT 24
Peak memory 209868 kb
Host smart-7b6308bd-cb36-4a28-964e-882495287967
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605734805 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.1605734805
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.191479155
Short name T926
Test name
Test status
Simulation time 83869322 ps
CPU time 1.09 seconds
Started Jun 05 05:52:23 PM PDT 24
Finished Jun 05 05:52:25 PM PDT 24
Peak memory 209752 kb
Host smart-6914aca7-c96d-41ce-941a-4910c55b3299
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191479155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 6.lc_ctrl_jtag_alert_test.191479155
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.4058371432
Short name T133
Test name
Test status
Simulation time 4794218022 ps
CPU time 22.21 seconds
Started Jun 05 05:52:20 PM PDT 24
Finished Jun 05 05:52:44 PM PDT 24
Peak memory 218092 kb
Host smart-567bcb41-3f45-45ae-a226-74027412cdc7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058371432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.4058371432
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1501722257
Short name T988
Test name
Test status
Simulation time 698044457 ps
CPU time 16.48 seconds
Started Jun 05 05:52:27 PM PDT 24
Finished Jun 05 05:52:44 PM PDT 24
Peak memory 209580 kb
Host smart-c22b409f-fdb8-46a4-9863-104170bb89bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501722257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.1501722257
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.4069282320
Short name T917
Test name
Test status
Simulation time 138930284 ps
CPU time 3.13 seconds
Started Jun 05 05:52:37 PM PDT 24
Finished Jun 05 05:52:41 PM PDT 24
Peak memory 218028 kb
Host smart-9389380e-6827-411e-a315-156be5fc2fe0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069282320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.4069282320
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.726942243
Short name T892
Test name
Test status
Simulation time 120828948 ps
CPU time 2.16 seconds
Started Jun 05 05:52:21 PM PDT 24
Finished Jun 05 05:52:24 PM PDT 24
Peak memory 218256 kb
Host smart-7de6956e-b07a-4d8c-8ad9-39e67b3a7a66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726942
243 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.726942243
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.828480612
Short name T915
Test name
Test status
Simulation time 133135524 ps
CPU time 1.46 seconds
Started Jun 05 05:52:18 PM PDT 24
Finished Jun 05 05:52:21 PM PDT 24
Peak memory 210000 kb
Host smart-31823c43-450a-4feb-8c06-c3bb8fe4e255
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828480612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.828480612
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.546200247
Short name T973
Test name
Test status
Simulation time 89995697 ps
CPU time 1.88 seconds
Started Jun 05 05:52:22 PM PDT 24
Finished Jun 05 05:52:25 PM PDT 24
Peak memory 209944 kb
Host smart-753e2696-6855-4b90-8950-d53658c82c68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546200247 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.546200247
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.705197741
Short name T913
Test name
Test status
Simulation time 77906206 ps
CPU time 1.85 seconds
Started Jun 05 05:52:37 PM PDT 24
Finished Jun 05 05:52:39 PM PDT 24
Peak memory 218136 kb
Host smart-fa3a95e8-437f-43c7-959d-666031587f4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705197741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
same_csr_outstanding.705197741
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.722346293
Short name T981
Test name
Test status
Simulation time 342090737 ps
CPU time 2.22 seconds
Started Jun 05 05:52:29 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 218216 kb
Host smart-785b5ddd-ec8a-44f4-8a3b-81867207b9b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722346293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.722346293
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.1858697176
Short name T997
Test name
Test status
Simulation time 117505169 ps
CPU time 1.65 seconds
Started Jun 05 05:52:29 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 218692 kb
Host smart-fb3553d9-c9c2-492a-ba9f-212b43095ee9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858697176 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.1858697176
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4093996682
Short name T162
Test name
Test status
Simulation time 29000237 ps
CPU time 0.88 seconds
Started Jun 05 05:52:21 PM PDT 24
Finished Jun 05 05:52:23 PM PDT 24
Peak memory 209864 kb
Host smart-406b4edf-fe0c-47c3-b557-02f84280cce2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093996682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.4093996682
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.3059220859
Short name T920
Test name
Test status
Simulation time 83737943 ps
CPU time 1.52 seconds
Started Jun 05 05:52:28 PM PDT 24
Finished Jun 05 05:52:31 PM PDT 24
Peak memory 209196 kb
Host smart-09c68532-b828-4173-9871-a43a06ea5216
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059220859 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.3059220859
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.2010925411
Short name T990
Test name
Test status
Simulation time 523530431 ps
CPU time 6.69 seconds
Started Jun 05 05:52:28 PM PDT 24
Finished Jun 05 05:52:36 PM PDT 24
Peak memory 209572 kb
Host smart-2343b496-5fef-4be7-97e7-e38ae8540178
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010925411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.2010925411
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2375512540
Short name T901
Test name
Test status
Simulation time 2733560089 ps
CPU time 9.39 seconds
Started Jun 05 05:52:23 PM PDT 24
Finished Jun 05 05:52:34 PM PDT 24
Peak memory 209880 kb
Host smart-259722d8-8f11-4270-88a2-b37a0eda8928
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375512540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.2375512540
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.2968667732
Short name T989
Test name
Test status
Simulation time 73640860 ps
CPU time 2.04 seconds
Started Jun 05 05:52:43 PM PDT 24
Finished Jun 05 05:52:46 PM PDT 24
Peak memory 211184 kb
Host smart-f34ad3e8-9ab9-47d7-9041-7f54ecc0be55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968667732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.2968667732
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1176480911
Short name T963
Test name
Test status
Simulation time 344521708 ps
CPU time 2.79 seconds
Started Jun 05 05:52:23 PM PDT 24
Finished Jun 05 05:52:33 PM PDT 24
Peak memory 220972 kb
Host smart-15227b66-a888-4c9d-9c66-24d688641832
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117648
0911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1176480911
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.3630817060
Short name T947
Test name
Test status
Simulation time 1520158499 ps
CPU time 2.72 seconds
Started Jun 05 05:52:21 PM PDT 24
Finished Jun 05 05:52:25 PM PDT 24
Peak memory 217856 kb
Host smart-4666994c-97ea-4e34-bbab-7b28efc874ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630817060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.3630817060
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.690473645
Short name T175
Test name
Test status
Simulation time 112372970 ps
CPU time 1.41 seconds
Started Jun 05 05:52:30 PM PDT 24
Finished Jun 05 05:52:33 PM PDT 24
Peak memory 210020 kb
Host smart-fe1b9f2d-7151-48a0-afd7-479e7a6bfdae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690473645 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.690473645
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.1020913117
Short name T995
Test name
Test status
Simulation time 27204275 ps
CPU time 1.28 seconds
Started Jun 05 05:52:33 PM PDT 24
Finished Jun 05 05:52:35 PM PDT 24
Peak memory 209488 kb
Host smart-5d0ecbd9-42ec-42ca-aa1b-ca1c40127129
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020913117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.1020913117
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3335776918
Short name T114
Test name
Test status
Simulation time 55748511 ps
CPU time 3.23 seconds
Started Jun 05 05:52:28 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 218368 kb
Host smart-e921a09c-2495-4474-994f-12adaf57c631
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335776918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3335776918
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.3571203854
Short name T106
Test name
Test status
Simulation time 41681562 ps
CPU time 1.3 seconds
Started Jun 05 05:52:31 PM PDT 24
Finished Jun 05 05:52:33 PM PDT 24
Peak memory 218992 kb
Host smart-aa79d21c-a895-4b8e-a510-9f9a152683e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571203854 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.3571203854
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.899030263
Short name T958
Test name
Test status
Simulation time 55983778 ps
CPU time 0.85 seconds
Started Jun 05 05:52:21 PM PDT 24
Finished Jun 05 05:52:23 PM PDT 24
Peak memory 209700 kb
Host smart-9a896fdc-9f0d-45d7-8642-361febaf9772
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899030263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.899030263
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.488036330
Short name T875
Test name
Test status
Simulation time 819637644 ps
CPU time 1.22 seconds
Started Jun 05 05:52:16 PM PDT 24
Finished Jun 05 05:52:18 PM PDT 24
Peak memory 208996 kb
Host smart-502dec9b-7a91-48dd-8c95-76807e74b804
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488036330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 8.lc_ctrl_jtag_alert_test.488036330
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1586245212
Short name T134
Test name
Test status
Simulation time 1379418389 ps
CPU time 9.95 seconds
Started Jun 05 05:52:21 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 209460 kb
Host smart-8ea75f4b-8361-44c3-a363-07d88a1f8586
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586245212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.1586245212
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.4166889170
Short name T918
Test name
Test status
Simulation time 4303276651 ps
CPU time 10.08 seconds
Started Jun 05 05:52:21 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 209836 kb
Host smart-9406c0ac-0d42-49c1-b342-98159da3f5a4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166889170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.4166889170
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.711560207
Short name T946
Test name
Test status
Simulation time 514938117 ps
CPU time 1.64 seconds
Started Jun 05 05:52:20 PM PDT 24
Finished Jun 05 05:52:23 PM PDT 24
Peak memory 211212 kb
Host smart-a808bd43-3dea-40f2-ba2c-e037715bb6b0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711560207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.711560207
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2726943565
Short name T962
Test name
Test status
Simulation time 64271546 ps
CPU time 1.62 seconds
Started Jun 05 05:52:19 PM PDT 24
Finished Jun 05 05:52:22 PM PDT 24
Peak memory 218556 kb
Host smart-42cdd10d-6abe-466e-bc0d-3485f4a98e6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272694
3565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2726943565
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.721592676
Short name T937
Test name
Test status
Simulation time 191577040 ps
CPU time 1.09 seconds
Started Jun 05 05:52:26 PM PDT 24
Finished Jun 05 05:52:28 PM PDT 24
Peak memory 209752 kb
Host smart-d11a15fe-2d6e-4824-8840-79cb72bad790
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721592676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.lc_ctrl_jtag_csr_rw.721592676
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.972563222
Short name T914
Test name
Test status
Simulation time 51723349 ps
CPU time 1.07 seconds
Started Jun 05 05:52:49 PM PDT 24
Finished Jun 05 05:52:50 PM PDT 24
Peak memory 218040 kb
Host smart-4495c55e-7947-422a-9b77-fc4568dcf1e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972563222 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.972563222
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1875409317
Short name T950
Test name
Test status
Simulation time 37009494 ps
CPU time 1.45 seconds
Started Jun 05 05:52:21 PM PDT 24
Finished Jun 05 05:52:24 PM PDT 24
Peak memory 212084 kb
Host smart-d051903d-013f-4abb-9864-092adbde421f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875409317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.1875409317
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.2836639382
Short name T884
Test name
Test status
Simulation time 163035192 ps
CPU time 2.06 seconds
Started Jun 05 05:52:32 PM PDT 24
Finished Jun 05 05:52:35 PM PDT 24
Peak memory 218164 kb
Host smart-f1073cac-dce8-4b62-a099-e4f017276e43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836639382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.2836639382
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3221835874
Short name T110
Test name
Test status
Simulation time 123055588 ps
CPU time 2.54 seconds
Started Jun 05 05:52:25 PM PDT 24
Finished Jun 05 05:52:29 PM PDT 24
Peak memory 218160 kb
Host smart-b6abc674-0b4d-464f-b7f5-6d7b595608d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221835874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3221835874
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.3128302403
Short name T935
Test name
Test status
Simulation time 72211407 ps
CPU time 1.31 seconds
Started Jun 05 05:52:18 PM PDT 24
Finished Jun 05 05:52:21 PM PDT 24
Peak memory 218244 kb
Host smart-3ad01f5a-aa13-4ff1-a501-90bb751927c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128302403 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.3128302403
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.744318495
Short name T907
Test name
Test status
Simulation time 23888115 ps
CPU time 0.88 seconds
Started Jun 05 05:52:24 PM PDT 24
Finished Jun 05 05:52:27 PM PDT 24
Peak memory 209868 kb
Host smart-22f1aed4-a2c6-4601-a1db-61b5638c9f51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744318495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.744318495
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.457807963
Short name T929
Test name
Test status
Simulation time 41810192 ps
CPU time 0.89 seconds
Started Jun 05 05:52:27 PM PDT 24
Finished Jun 05 05:52:29 PM PDT 24
Peak memory 209704 kb
Host smart-8f626b24-3205-4d98-b53e-03be7a182618
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457807963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_
base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d
ev/null -cm_name 9.lc_ctrl_jtag_alert_test.457807963
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3097804996
Short name T923
Test name
Test status
Simulation time 822209402 ps
CPU time 10.23 seconds
Started Jun 05 05:52:20 PM PDT 24
Finished Jun 05 05:52:32 PM PDT 24
Peak memory 209468 kb
Host smart-6a3610b5-e1fe-4465-823a-f17029b48202
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097804996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.3097804996
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2417524800
Short name T916
Test name
Test status
Simulation time 970383605 ps
CPU time 9.18 seconds
Started Jun 05 05:52:25 PM PDT 24
Finished Jun 05 05:52:35 PM PDT 24
Peak memory 209492 kb
Host smart-6b35db93-1249-469b-bbed-e0642c2afbc5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417524800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2417524800
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3346283879
Short name T943
Test name
Test status
Simulation time 73954114 ps
CPU time 1.58 seconds
Started Jun 05 05:52:27 PM PDT 24
Finished Jun 05 05:52:29 PM PDT 24
Peak memory 211236 kb
Host smart-bb30742b-623f-45ec-ad41-694c60384447
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346283879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3346283879
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1957160798
Short name T968
Test name
Test status
Simulation time 217245481 ps
CPU time 2.2 seconds
Started Jun 05 05:52:27 PM PDT 24
Finished Jun 05 05:52:31 PM PDT 24
Peak memory 219456 kb
Host smart-b1d38b59-3347-4a61-89fe-bbaab17286d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195716
0798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1957160798
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.3397320601
Short name T954
Test name
Test status
Simulation time 35474109 ps
CPU time 1.5 seconds
Started Jun 05 05:52:21 PM PDT 24
Finished Jun 05 05:52:24 PM PDT 24
Peak memory 217884 kb
Host smart-479e6825-45e5-428a-8565-e3fc71e0368d
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397320601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.3397320601
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.713987846
Short name T967
Test name
Test status
Simulation time 18973245 ps
CPU time 1.3 seconds
Started Jun 05 05:52:40 PM PDT 24
Finished Jun 05 05:52:42 PM PDT 24
Peak memory 218084 kb
Host smart-e6b9dffc-bc5e-4053-813f-cd2cd8483ac1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713987846 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.713987846
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.3475407958
Short name T951
Test name
Test status
Simulation time 35878302 ps
CPU time 1.36 seconds
Started Jun 05 05:52:29 PM PDT 24
Finished Jun 05 05:52:36 PM PDT 24
Peak memory 209988 kb
Host smart-12d55643-dd5e-4a1c-b59f-fd0a70436281
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475407958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl
_same_csr_outstanding.3475407958
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.1692631392
Short name T960
Test name
Test status
Simulation time 248139656 ps
CPU time 3.3 seconds
Started Jun 05 05:52:22 PM PDT 24
Finished Jun 05 05:52:27 PM PDT 24
Peak memory 218188 kb
Host smart-60aba2e7-4c8b-4708-9510-af092703965b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692631392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.1692631392
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1618568727
Short name T128
Test name
Test status
Simulation time 214126871 ps
CPU time 1.8 seconds
Started Jun 05 05:52:33 PM PDT 24
Finished Jun 05 05:52:36 PM PDT 24
Peak memory 222264 kb
Host smart-d362d2c8-1de7-431f-8d1d-443aac88d73f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618568727 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.1618568727
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.3975852788
Short name T398
Test name
Test status
Simulation time 20739809 ps
CPU time 1.17 seconds
Started Jun 05 05:19:29 PM PDT 24
Finished Jun 05 05:19:31 PM PDT 24
Peak memory 208764 kb
Host smart-b0b0fde6-02fc-4440-a0d7-5e6ee98a7944
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975852788 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.3975852788
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3766616166
Short name T637
Test name
Test status
Simulation time 19080114 ps
CPU time 0.81 seconds
Started Jun 05 05:19:17 PM PDT 24
Finished Jun 05 05:19:19 PM PDT 24
Peak memory 208644 kb
Host smart-3ff11820-98a3-4d4c-9903-25ad3ddfd85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766616166 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3766616166
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.117323282
Short name T745
Test name
Test status
Simulation time 1333538804 ps
CPU time 10.3 seconds
Started Jun 05 05:19:17 PM PDT 24
Finished Jun 05 05:19:28 PM PDT 24
Peak memory 217976 kb
Host smart-d0d60122-1be9-4b7e-aac5-8ee5bfd910c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117323282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.117323282
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.2870807501
Short name T159
Test name
Test status
Simulation time 400309710 ps
CPU time 10.73 seconds
Started Jun 05 05:19:21 PM PDT 24
Finished Jun 05 05:19:33 PM PDT 24
Peak memory 209508 kb
Host smart-a28f6707-d2e9-4470-998f-9248ee63c556
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870807501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.2870807501
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.2127391092
Short name T391
Test name
Test status
Simulation time 1605950307 ps
CPU time 45.44 seconds
Started Jun 05 05:19:19 PM PDT 24
Finished Jun 05 05:20:06 PM PDT 24
Peak memory 218008 kb
Host smart-60f796db-9ee5-40cb-8f6b-1c50cae08ea7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127391092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_er
rors.2127391092
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.408765743
Short name T752
Test name
Test status
Simulation time 123276155 ps
CPU time 3.77 seconds
Started Jun 05 05:19:14 PM PDT 24
Finished Jun 05 05:19:18 PM PDT 24
Peak memory 217200 kb
Host smart-0012cff3-c7b6-476c-96ab-3f4e0f1e6861
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408765743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.408765743
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.220734084
Short name T753
Test name
Test status
Simulation time 273099023 ps
CPU time 8.58 seconds
Started Jun 05 05:19:21 PM PDT 24
Finished Jun 05 05:19:30 PM PDT 24
Peak memory 218000 kb
Host smart-6a4866b7-91c5-4b5b-aa79-567f65f307e8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220734084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_
prog_failure.220734084
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.1681323889
Short name T314
Test name
Test status
Simulation time 1238241375 ps
CPU time 38.23 seconds
Started Jun 05 05:19:18 PM PDT 24
Finished Jun 05 05:19:58 PM PDT 24
Peak memory 217632 kb
Host smart-809607a5-3ccb-4728-83ce-2d2a879eae38
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681323889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.1681323889
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.842535537
Short name T832
Test name
Test status
Simulation time 77826200 ps
CPU time 1.87 seconds
Started Jun 05 05:19:18 PM PDT 24
Finished Jun 05 05:19:21 PM PDT 24
Peak memory 217624 kb
Host smart-9545cbdb-7cfd-4710-b992-f59ccbb8fbe9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842535537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.842535537
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.3989499355
Short name T235
Test name
Test status
Simulation time 2267200050 ps
CPU time 43.56 seconds
Started Jun 05 05:19:20 PM PDT 24
Finished Jun 05 05:20:05 PM PDT 24
Peak memory 250876 kb
Host smart-2e0c2c50-6167-4b74-8959-3dc14761e30c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989499355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.3989499355
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.1511785596
Short name T465
Test name
Test status
Simulation time 2353584046 ps
CPU time 22.87 seconds
Started Jun 05 05:19:19 PM PDT 24
Finished Jun 05 05:19:43 PM PDT 24
Peak memory 250904 kb
Host smart-17ff7190-b57f-4872-8f34-b508904dd479
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511785596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_state_post_trans.1511785596
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.1528091114
Short name T236
Test name
Test status
Simulation time 85563567 ps
CPU time 4.01 seconds
Started Jun 05 05:19:18 PM PDT 24
Finished Jun 05 05:19:24 PM PDT 24
Peak memory 218004 kb
Host smart-419cf921-d70d-4625-926b-4ceff041ce30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528091114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.1528091114
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.3214915042
Short name T484
Test name
Test status
Simulation time 922103483 ps
CPU time 8.97 seconds
Started Jun 05 05:19:18 PM PDT 24
Finished Jun 05 05:19:29 PM PDT 24
Peak memory 214132 kb
Host smart-fa216fd5-abc1-4121-b5e9-aba20d94bf15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214915042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.3214915042
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.4102076721
Short name T856
Test name
Test status
Simulation time 2928139466 ps
CPU time 9.56 seconds
Started Jun 05 05:19:20 PM PDT 24
Finished Jun 05 05:19:31 PM PDT 24
Peak memory 218992 kb
Host smart-29ed75da-482e-4fa3-bd37-71018f14a9b7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102076721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.4102076721
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.3981982966
Short name T255
Test name
Test status
Simulation time 452364727 ps
CPU time 8.88 seconds
Started Jun 05 05:19:22 PM PDT 24
Finished Jun 05 05:19:31 PM PDT 24
Peak memory 226052 kb
Host smart-7f60ad57-b29a-4f5b-b3bd-2a655a10ef37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981982966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.3981982966
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.3977241423
Short name T388
Test name
Test status
Simulation time 1242593817 ps
CPU time 9.4 seconds
Started Jun 05 05:19:18 PM PDT 24
Finished Jun 05 05:19:29 PM PDT 24
Peak memory 218000 kb
Host smart-34434d66-b52e-4e26-8ac5-f07d708f16c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977241423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.3
977241423
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.655197389
Short name T758
Test name
Test status
Simulation time 4240392774 ps
CPU time 12.02 seconds
Started Jun 05 05:19:19 PM PDT 24
Finished Jun 05 05:19:32 PM PDT 24
Peak memory 225692 kb
Host smart-38437af6-1da8-4f9b-aa38-1e99f5b4839d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655197389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.655197389
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.2979653638
Short name T51
Test name
Test status
Simulation time 208032674 ps
CPU time 2.44 seconds
Started Jun 05 05:19:19 PM PDT 24
Finished Jun 05 05:19:23 PM PDT 24
Peak memory 214108 kb
Host smart-b8e4d7d0-7c4d-49de-8157-2033f281c719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979653638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.2979653638
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.1569827485
Short name T624
Test name
Test status
Simulation time 901086478 ps
CPU time 25.18 seconds
Started Jun 05 05:19:18 PM PDT 24
Finished Jun 05 05:19:45 PM PDT 24
Peak memory 250936 kb
Host smart-0beb7482-f903-4f87-bab9-24d81516114e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569827485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.1569827485
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.1835072999
Short name T563
Test name
Test status
Simulation time 184319421 ps
CPU time 6.8 seconds
Started Jun 05 05:19:18 PM PDT 24
Finished Jun 05 05:19:27 PM PDT 24
Peak memory 248464 kb
Host smart-8b68c061-378b-4412-9dc4-8a8e4b051b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835072999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.1835072999
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.3358705780
Short name T260
Test name
Test status
Simulation time 11659027310 ps
CPU time 129.08 seconds
Started Jun 05 05:19:29 PM PDT 24
Finished Jun 05 05:21:39 PM PDT 24
Peak memory 219720 kb
Host smart-3fdd14ce-9d9b-48fd-b7ad-d407a8e14cc7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358705780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.3358705780
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2012216479
Short name T420
Test name
Test status
Simulation time 13577305 ps
CPU time 1.05 seconds
Started Jun 05 05:19:19 PM PDT 24
Finished Jun 05 05:19:21 PM PDT 24
Peak memory 211568 kb
Host smart-6e3fb1b5-b322-4dc3-87e8-6b9670441ef1
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012216479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.2012216479
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.3802762703
Short name T861
Test name
Test status
Simulation time 43484443 ps
CPU time 1.07 seconds
Started Jun 05 05:19:29 PM PDT 24
Finished Jun 05 05:19:31 PM PDT 24
Peak memory 208688 kb
Host smart-8181b2f1-746a-4f8c-9051-872b806070e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802762703 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.3802762703
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.1189391556
Short name T479
Test name
Test status
Simulation time 247233149 ps
CPU time 10.98 seconds
Started Jun 05 05:19:26 PM PDT 24
Finished Jun 05 05:19:38 PM PDT 24
Peak memory 218020 kb
Host smart-3d0ef6ef-55ab-44a3-a695-02600991a735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189391556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.1189391556
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.1342868510
Short name T711
Test name
Test status
Simulation time 1019912223 ps
CPU time 5.57 seconds
Started Jun 05 05:19:27 PM PDT 24
Finished Jun 05 05:19:33 PM PDT 24
Peak memory 217104 kb
Host smart-a0f4b529-5f80-4101-a929-901c81798af3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342868510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.1342868510
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.603825571
Short name T416
Test name
Test status
Simulation time 7685162765 ps
CPU time 88.33 seconds
Started Jun 05 05:19:24 PM PDT 24
Finished Jun 05 05:20:53 PM PDT 24
Peak memory 218628 kb
Host smart-39a6d19f-bad1-458c-9380-fcee64ccb78c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603825571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_err
ors.603825571
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.201282886
Short name T245
Test name
Test status
Simulation time 209343871 ps
CPU time 3.11 seconds
Started Jun 05 05:19:25 PM PDT 24
Finished Jun 05 05:19:29 PM PDT 24
Peak memory 217380 kb
Host smart-299557e5-6a57-43d7-8f17-950b29863cba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201282886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.201282886
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.3152618289
Short name T403
Test name
Test status
Simulation time 111605795 ps
CPU time 4.16 seconds
Started Jun 05 05:19:29 PM PDT 24
Finished Jun 05 05:19:34 PM PDT 24
Peak memory 217880 kb
Host smart-cf98a3ac-6aa3-4c8d-a8b1-50bb07c30bdb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152618289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag
_prog_failure.3152618289
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.591260918
Short name T501
Test name
Test status
Simulation time 1339458602 ps
CPU time 20.04 seconds
Started Jun 05 05:19:27 PM PDT 24
Finished Jun 05 05:19:47 PM PDT 24
Peak memory 217640 kb
Host smart-4b9fc2c3-a599-4e11-889d-f2d39478c32c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591260918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_regwen_during_op.591260918
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.397394296
Short name T600
Test name
Test status
Simulation time 847482513 ps
CPU time 5.97 seconds
Started Jun 05 05:19:25 PM PDT 24
Finished Jun 05 05:19:32 PM PDT 24
Peak memory 217620 kb
Host smart-d5cd75ff-8d41-4594-9cef-66cbaec975de
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397394296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.397394296
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.4089522698
Short name T754
Test name
Test status
Simulation time 5407968811 ps
CPU time 48.43 seconds
Started Jun 05 05:19:26 PM PDT 24
Finished Jun 05 05:20:15 PM PDT 24
Peak memory 267292 kb
Host smart-b2dfc6dd-7e6b-4c36-987c-d4e256c2f64c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089522698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.4089522698
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.3571514584
Short name T766
Test name
Test status
Simulation time 1542234288 ps
CPU time 18.69 seconds
Started Jun 05 05:19:25 PM PDT 24
Finished Jun 05 05:19:45 PM PDT 24
Peak memory 250844 kb
Host smart-46737564-e6ba-4f46-8404-df03bad4c882
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571514584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_state_post_trans.3571514584
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.2114078384
Short name T204
Test name
Test status
Simulation time 60688610 ps
CPU time 2.6 seconds
Started Jun 05 05:19:25 PM PDT 24
Finished Jun 05 05:19:29 PM PDT 24
Peak memory 218012 kb
Host smart-48e8a4cd-d661-4698-bc97-141935b15ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114078384 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.2114078384
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.2229527368
Short name T554
Test name
Test status
Simulation time 1027034374 ps
CPU time 5.78 seconds
Started Jun 05 05:19:26 PM PDT 24
Finished Jun 05 05:19:32 PM PDT 24
Peak memory 217712 kb
Host smart-f7011696-4d3e-4f33-8372-c61a274fc2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229527368 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.2229527368
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2092553830
Short name T47
Test name
Test status
Simulation time 640472146 ps
CPU time 22.7 seconds
Started Jun 05 05:19:27 PM PDT 24
Finished Jun 05 05:19:51 PM PDT 24
Peak memory 284200 kb
Host smart-cd3ce0cb-5224-4ce6-9b92-b430a60c7c9f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092553830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2092553830
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3468845531
Short name T579
Test name
Test status
Simulation time 1008617062 ps
CPU time 12.4 seconds
Started Jun 05 05:19:25 PM PDT 24
Finished Jun 05 05:19:38 PM PDT 24
Peak memory 218948 kb
Host smart-bae79d80-007f-47ff-80d0-a7d157b52d20
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468845531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3468845531
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.727242906
Short name T446
Test name
Test status
Simulation time 1093533490 ps
CPU time 19.46 seconds
Started Jun 05 05:19:29 PM PDT 24
Finished Jun 05 05:19:49 PM PDT 24
Peak memory 226028 kb
Host smart-056a1bc9-c4ab-4730-9ba2-280f2b9fb126
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727242906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_dig
est.727242906
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.1900109446
Short name T352
Test name
Test status
Simulation time 301582694 ps
CPU time 11.13 seconds
Started Jun 05 05:19:29 PM PDT 24
Finished Jun 05 05:19:41 PM PDT 24
Peak memory 217952 kb
Host smart-ea2393ce-0c8a-4684-a10f-9fcd913837cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900109446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.1
900109446
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.3410988054
Short name T481
Test name
Test status
Simulation time 784503467 ps
CPU time 13.89 seconds
Started Jun 05 05:19:26 PM PDT 24
Finished Jun 05 05:19:41 PM PDT 24
Peak memory 225400 kb
Host smart-6bfe3f0b-8511-467f-95c1-20e9ce42e482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410988054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.3410988054
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.2429493295
Short name T652
Test name
Test status
Simulation time 53329882 ps
CPU time 2.53 seconds
Started Jun 05 05:19:26 PM PDT 24
Finished Jun 05 05:19:29 PM PDT 24
Peak memory 214176 kb
Host smart-93f55fb0-d2d1-4da8-b9be-3d5b45eaddd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429493295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.2429493295
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.277953056
Short name T526
Test name
Test status
Simulation time 763311872 ps
CPU time 32.35 seconds
Started Jun 05 05:19:25 PM PDT 24
Finished Jun 05 05:19:58 PM PDT 24
Peak memory 251000 kb
Host smart-0b8ed83e-02f8-4a7a-b7e1-2f945ee42d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277953056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.277953056
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.1285563032
Short name T825
Test name
Test status
Simulation time 49850877 ps
CPU time 6.72 seconds
Started Jun 05 05:19:26 PM PDT 24
Finished Jun 05 05:19:33 PM PDT 24
Peak memory 250420 kb
Host smart-4281280b-03d0-4294-896f-79b0912f3bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285563032 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.1285563032
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2446327944
Short name T483
Test name
Test status
Simulation time 33239188 ps
CPU time 0.92 seconds
Started Jun 05 05:19:26 PM PDT 24
Finished Jun 05 05:19:28 PM PDT 24
Peak memory 211440 kb
Host smart-5ccdfe90-0d5b-450b-973c-f4211d8f37d8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446327944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.2446327944
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.3708184430
Short name T523
Test name
Test status
Simulation time 60005813 ps
CPU time 1.1 seconds
Started Jun 05 05:20:17 PM PDT 24
Finished Jun 05 05:20:20 PM PDT 24
Peak memory 208736 kb
Host smart-9979948e-e1f0-478e-ad3e-7b949a9d60c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708184430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.3708184430
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.3530131187
Short name T227
Test name
Test status
Simulation time 276990955 ps
CPU time 9.38 seconds
Started Jun 05 05:20:19 PM PDT 24
Finished Jun 05 05:20:29 PM PDT 24
Peak memory 218152 kb
Host smart-ceeb6e93-95d4-4d74-b0d1-f04d6cd9c1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530131187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.3530131187
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.3167244541
Short name T287
Test name
Test status
Simulation time 6278502596 ps
CPU time 11.94 seconds
Started Jun 05 05:20:18 PM PDT 24
Finished Jun 05 05:20:31 PM PDT 24
Peak memory 209584 kb
Host smart-35039f63-a4c4-4936-813e-40e37d106555
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167244541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.3167244541
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.3850266101
Short name T32
Test name
Test status
Simulation time 5411505781 ps
CPU time 38.66 seconds
Started Jun 05 05:20:17 PM PDT 24
Finished Jun 05 05:20:56 PM PDT 24
Peak memory 218920 kb
Host smart-0430a96a-ccc0-459e-8be7-451be93d5319
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850266101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.3850266101
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.199852711
Short name T374
Test name
Test status
Simulation time 115413863 ps
CPU time 4.53 seconds
Started Jun 05 05:20:18 PM PDT 24
Finished Jun 05 05:20:24 PM PDT 24
Peak memory 217940 kb
Host smart-47978690-c716-4fad-9a9e-4ec01d0b7664
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199852711 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag
_prog_failure.199852711
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.4197134568
Short name T197
Test name
Test status
Simulation time 407573598 ps
CPU time 3.15 seconds
Started Jun 05 05:20:17 PM PDT 24
Finished Jun 05 05:20:22 PM PDT 24
Peak memory 217648 kb
Host smart-b0ca490e-40fc-49ac-9b3a-03b81507a06c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197134568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.4197134568
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.2059305642
Short name T848
Test name
Test status
Simulation time 7787553354 ps
CPU time 51.02 seconds
Started Jun 05 05:20:19 PM PDT 24
Finished Jun 05 05:21:11 PM PDT 24
Peak memory 267284 kb
Host smart-1eed9c3c-1f40-412a-a0b4-6ac5c3f55985
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059305642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.2059305642
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2453380041
Short name T576
Test name
Test status
Simulation time 3623923183 ps
CPU time 33.17 seconds
Started Jun 05 05:20:17 PM PDT 24
Finished Jun 05 05:20:52 PM PDT 24
Peak memory 250840 kb
Host smart-bbca453b-aa6d-4706-8191-e37384551fcc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453380041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2453380041
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2719813085
Short name T335
Test name
Test status
Simulation time 165075177 ps
CPU time 1.42 seconds
Started Jun 05 05:20:21 PM PDT 24
Finished Jun 05 05:20:24 PM PDT 24
Peak memory 218008 kb
Host smart-48e4ec0a-4791-45fd-8c7a-ec4bb1cd80e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719813085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2719813085
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.2225972808
Short name T510
Test name
Test status
Simulation time 5976157715 ps
CPU time 10.12 seconds
Started Jun 05 05:20:17 PM PDT 24
Finished Jun 05 05:20:29 PM PDT 24
Peak memory 220052 kb
Host smart-0565cb15-e909-476c-a52b-be9f3083d33d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225972808 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.2225972808
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.1710646372
Short name T259
Test name
Test status
Simulation time 243838066 ps
CPU time 9.17 seconds
Started Jun 05 05:20:19 PM PDT 24
Finished Jun 05 05:20:29 PM PDT 24
Peak memory 226044 kb
Host smart-34103575-9848-4542-99d0-7e87d70ed99b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710646372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.1710646372
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.2364922760
Short name T631
Test name
Test status
Simulation time 3781420472 ps
CPU time 9.28 seconds
Started Jun 05 05:20:18 PM PDT 24
Finished Jun 05 05:20:28 PM PDT 24
Peak memory 217992 kb
Host smart-63e176ff-4597-482a-bdf5-0e9aad93f2bf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364922760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
2364922760
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.82234268
Short name T672
Test name
Test status
Simulation time 1058461555 ps
CPU time 6.85 seconds
Started Jun 05 05:20:17 PM PDT 24
Finished Jun 05 05:20:24 PM PDT 24
Peak memory 224216 kb
Host smart-99ce3b3d-a7ca-423e-9ad3-8f7cb1564206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82234268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.82234268
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.937194392
Short name T568
Test name
Test status
Simulation time 71381585 ps
CPU time 2.06 seconds
Started Jun 05 05:20:17 PM PDT 24
Finished Jun 05 05:20:21 PM PDT 24
Peak memory 213720 kb
Host smart-d503fdda-b635-4d21-8051-70614c6bbdb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937194392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.937194392
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3452218048
Short name T452
Test name
Test status
Simulation time 185229392 ps
CPU time 20.41 seconds
Started Jun 05 05:20:17 PM PDT 24
Finished Jun 05 05:20:39 PM PDT 24
Peak memory 250892 kb
Host smart-4f406720-ff6e-4836-b92e-216ef5738589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452218048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3452218048
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.2284390913
Short name T200
Test name
Test status
Simulation time 70844592 ps
CPU time 7.53 seconds
Started Jun 05 05:20:18 PM PDT 24
Finished Jun 05 05:20:26 PM PDT 24
Peak memory 250848 kb
Host smart-a138b3ad-ad35-4de5-902a-935c1bfd7242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284390913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.2284390913
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.4201884958
Short name T286
Test name
Test status
Simulation time 787331596 ps
CPU time 14.43 seconds
Started Jun 05 05:20:17 PM PDT 24
Finished Jun 05 05:20:33 PM PDT 24
Peak memory 226280 kb
Host smart-462da889-d5e1-4462-8d99-89874cc83bf3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201884958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.4201884958
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all_with_rand_reset.2896222616
Short name T70
Test name
Test status
Simulation time 56883113231 ps
CPU time 671.36 seconds
Started Jun 05 05:20:17 PM PDT 24
Finished Jun 05 05:31:29 PM PDT 24
Peak memory 529588 kb
Host smart-1ea8322f-d463-40f6-b535-b3467cdc931a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2896222616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_stress_all_with_rand_reset.2896222616
Directory /workspace/10.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.2818230033
Short name T683
Test name
Test status
Simulation time 19886856 ps
CPU time 1.03 seconds
Started Jun 05 05:20:19 PM PDT 24
Finished Jun 05 05:20:21 PM PDT 24
Peak memory 212688 kb
Host smart-32e50e49-7835-4a4a-a9b8-9697e532fbbb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818230033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.2818230033
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.4017553058
Short name T743
Test name
Test status
Simulation time 17336770 ps
CPU time 1.09 seconds
Started Jun 05 05:20:26 PM PDT 24
Finished Jun 05 05:20:27 PM PDT 24
Peak memory 208740 kb
Host smart-8c7a055c-ffb2-408d-9954-fe3717922f96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017553058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.4017553058
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.1238001724
Short name T155
Test name
Test status
Simulation time 1539350253 ps
CPU time 13.22 seconds
Started Jun 05 05:20:18 PM PDT 24
Finished Jun 05 05:20:32 PM PDT 24
Peak memory 218072 kb
Host smart-93ec6bf0-093a-44af-affa-88c25c9de6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238001724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.1238001724
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.1555109447
Short name T437
Test name
Test status
Simulation time 383107843 ps
CPU time 9.87 seconds
Started Jun 05 05:20:27 PM PDT 24
Finished Jun 05 05:20:38 PM PDT 24
Peak memory 209524 kb
Host smart-3966972d-e626-47b4-8abe-202215196f8b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555109447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.1555109447
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.1033770362
Short name T20
Test name
Test status
Simulation time 4789611827 ps
CPU time 57.17 seconds
Started Jun 05 05:20:26 PM PDT 24
Finished Jun 05 05:21:24 PM PDT 24
Peak memory 219984 kb
Host smart-97a8697c-d818-4bd6-920b-5c7baa397f76
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033770362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_e
rrors.1033770362
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.306538367
Short name T246
Test name
Test status
Simulation time 223841178 ps
CPU time 2.74 seconds
Started Jun 05 05:20:17 PM PDT 24
Finished Jun 05 05:20:21 PM PDT 24
Peak memory 217988 kb
Host smart-b6423c8d-73cb-4877-9173-a0a48c104db4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306538367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag
_prog_failure.306538367
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.1625394067
Short name T454
Test name
Test status
Simulation time 542613223 ps
CPU time 3.33 seconds
Started Jun 05 05:20:17 PM PDT 24
Finished Jun 05 05:20:22 PM PDT 24
Peak memory 217732 kb
Host smart-7e33326f-3996-4765-b582-a8c071998cc6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625394067 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.1625394067
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.3932837207
Short name T198
Test name
Test status
Simulation time 1977292614 ps
CPU time 35.79 seconds
Started Jun 05 05:20:18 PM PDT 24
Finished Jun 05 05:20:56 PM PDT 24
Peak memory 250856 kb
Host smart-a5042ec6-2ddb-4082-ad7c-1dc1533f4cd8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932837207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.3932837207
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.4210081681
Short name T503
Test name
Test status
Simulation time 3008674439 ps
CPU time 17.07 seconds
Started Jun 05 05:20:18 PM PDT 24
Finished Jun 05 05:20:37 PM PDT 24
Peak memory 250540 kb
Host smart-fcfc4fc4-d86b-4777-873e-0a32f7cebbc3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210081681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.4210081681
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.716285793
Short name T820
Test name
Test status
Simulation time 43326295 ps
CPU time 1.9 seconds
Started Jun 05 05:20:17 PM PDT 24
Finished Jun 05 05:20:20 PM PDT 24
Peak memory 217976 kb
Host smart-8e7d6722-62bf-4cfd-849f-6fe423c283b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716285793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.716285793
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.150632247
Short name T773
Test name
Test status
Simulation time 1348543364 ps
CPU time 13.75 seconds
Started Jun 05 05:20:27 PM PDT 24
Finished Jun 05 05:20:41 PM PDT 24
Peak memory 218944 kb
Host smart-4ff2601a-baea-4241-92d6-d742ea8cb68e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150632247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.150632247
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1757171397
Short name T429
Test name
Test status
Simulation time 446820378 ps
CPU time 11.28 seconds
Started Jun 05 05:20:27 PM PDT 24
Finished Jun 05 05:20:39 PM PDT 24
Peak memory 226036 kb
Host smart-d8e82b5d-cbe4-45c4-aa2c-69c1e3aed5c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757171397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1757171397
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.4178416393
Short name T422
Test name
Test status
Simulation time 373347703 ps
CPU time 13.39 seconds
Started Jun 05 05:20:27 PM PDT 24
Finished Jun 05 05:20:42 PM PDT 24
Peak memory 217936 kb
Host smart-9e73a920-7a08-4d83-82e9-eb3dd212c207
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178416393 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
4178416393
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.2720373642
Short name T326
Test name
Test status
Simulation time 539825424 ps
CPU time 10.99 seconds
Started Jun 05 05:20:21 PM PDT 24
Finished Jun 05 05:20:33 PM PDT 24
Peak memory 218224 kb
Host smart-a6049659-6147-49f7-a663-235158b9d600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720373642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.2720373642
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.3139232099
Short name T74
Test name
Test status
Simulation time 22551207 ps
CPU time 1.28 seconds
Started Jun 05 05:20:16 PM PDT 24
Finished Jun 05 05:20:17 PM PDT 24
Peak memory 217716 kb
Host smart-6865cb92-0007-441c-9bca-081822599b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139232099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.3139232099
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.3748954922
Short name T421
Test name
Test status
Simulation time 394765888 ps
CPU time 21.43 seconds
Started Jun 05 05:20:19 PM PDT 24
Finished Jun 05 05:20:41 PM PDT 24
Peak memory 250920 kb
Host smart-f09be107-5839-4d1a-98a2-2d9877854ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748954922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.3748954922
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.1550025626
Short name T301
Test name
Test status
Simulation time 226926141 ps
CPU time 8.05 seconds
Started Jun 05 05:20:19 PM PDT 24
Finished Jun 05 05:20:28 PM PDT 24
Peak memory 246908 kb
Host smart-72819ccf-0def-435d-acc1-29cf99396b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550025626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.1550025626
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.3514454931
Short name T668
Test name
Test status
Simulation time 13925442489 ps
CPU time 236.58 seconds
Started Jun 05 05:20:29 PM PDT 24
Finished Jun 05 05:24:27 PM PDT 24
Peak memory 254672 kb
Host smart-4421bcdb-bc81-4501-a644-50eb3583a291
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514454931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.3514454931
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.91538585
Short name T598
Test name
Test status
Simulation time 17492213 ps
CPU time 1.14 seconds
Started Jun 05 05:20:27 PM PDT 24
Finished Jun 05 05:20:29 PM PDT 24
Peak memory 209664 kb
Host smart-128417c1-05ef-4ada-8e81-65bcfb08ab3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91538585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.91538585
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.2086209258
Short name T305
Test name
Test status
Simulation time 589921006 ps
CPU time 23.01 seconds
Started Jun 05 05:20:24 PM PDT 24
Finished Jun 05 05:20:48 PM PDT 24
Peak memory 218008 kb
Host smart-7a40b671-041b-475e-9f70-2d7e543ebfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086209258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.2086209258
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.2642309124
Short name T296
Test name
Test status
Simulation time 1939641275 ps
CPU time 12.84 seconds
Started Jun 05 05:20:27 PM PDT 24
Finished Jun 05 05:20:41 PM PDT 24
Peak memory 209496 kb
Host smart-d1793fc2-4eb3-4a14-9b7e-d58f0c136b84
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642309124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.2642309124
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.1350461142
Short name T308
Test name
Test status
Simulation time 6646803723 ps
CPU time 39.03 seconds
Started Jun 05 05:20:26 PM PDT 24
Finished Jun 05 05:21:05 PM PDT 24
Peak memory 218924 kb
Host smart-9210dcd5-8bec-4835-8712-1706dd7d3067
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350461142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.1350461142
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.1282684850
Short name T533
Test name
Test status
Simulation time 311361474 ps
CPU time 4.99 seconds
Started Jun 05 05:20:26 PM PDT 24
Finished Jun 05 05:20:31 PM PDT 24
Peak memory 218008 kb
Host smart-bf48fee3-e36d-47e8-90e9-95f96c548f25
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282684850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.1282684850
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2612985022
Short name T691
Test name
Test status
Simulation time 943996391 ps
CPU time 12.06 seconds
Started Jun 05 05:20:26 PM PDT 24
Finished Jun 05 05:20:39 PM PDT 24
Peak memory 217628 kb
Host smart-c0460732-ad98-43ab-8ad3-eebf26364da2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612985022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2612985022
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.1741432779
Short name T748
Test name
Test status
Simulation time 6513047354 ps
CPU time 40.02 seconds
Started Jun 05 05:20:28 PM PDT 24
Finished Jun 05 05:21:09 PM PDT 24
Peak memory 250900 kb
Host smart-577c5af1-5a6d-49c2-9cb8-67447449e9f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741432779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.1741432779
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.256303678
Short name T377
Test name
Test status
Simulation time 391705321 ps
CPU time 16.73 seconds
Started Jun 05 05:20:29 PM PDT 24
Finished Jun 05 05:20:47 PM PDT 24
Peak memory 250388 kb
Host smart-5d60d3b6-6f73-4244-bf2a-a068515699d8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256303678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_
jtag_state_post_trans.256303678
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.3258696971
Short name T233
Test name
Test status
Simulation time 342118835 ps
CPU time 4.32 seconds
Started Jun 05 05:20:30 PM PDT 24
Finished Jun 05 05:20:35 PM PDT 24
Peak memory 218056 kb
Host smart-524c378c-c64c-4e8a-811b-6d94f741e09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258696971 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.3258696971
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.3306775421
Short name T48
Test name
Test status
Simulation time 1460344291 ps
CPU time 13.35 seconds
Started Jun 05 05:20:27 PM PDT 24
Finished Jun 05 05:20:41 PM PDT 24
Peak memory 226024 kb
Host smart-9e0b73b0-7300-4568-ba05-96ed27affbe2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306775421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.3306775421
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.1557894814
Short name T318
Test name
Test status
Simulation time 331952530 ps
CPU time 8.13 seconds
Started Jun 05 05:20:28 PM PDT 24
Finished Jun 05 05:20:38 PM PDT 24
Peak memory 226024 kb
Host smart-8ed3eafc-04aa-49d0-8e18-52efbc83748e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557894814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_d
igest.1557894814
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.1067023350
Short name T546
Test name
Test status
Simulation time 1163966294 ps
CPU time 8.46 seconds
Started Jun 05 05:20:26 PM PDT 24
Finished Jun 05 05:20:35 PM PDT 24
Peak memory 224676 kb
Host smart-eb63e818-56c6-41db-ad1c-71e5aade8744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067023350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.1067023350
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1560314813
Short name T390
Test name
Test status
Simulation time 242898110 ps
CPU time 2.89 seconds
Started Jun 05 05:20:26 PM PDT 24
Finished Jun 05 05:20:30 PM PDT 24
Peak memory 217696 kb
Host smart-74ad2b93-500b-4e5a-889c-bf42c9c1785e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560314813 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1560314813
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.2252648987
Short name T385
Test name
Test status
Simulation time 214863449 ps
CPU time 27.66 seconds
Started Jun 05 05:20:25 PM PDT 24
Finished Jun 05 05:20:53 PM PDT 24
Peak memory 251000 kb
Host smart-f2ec1a9e-aac4-41e0-8281-57cbab6015c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252648987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.2252648987
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.2051722713
Short name T810
Test name
Test status
Simulation time 148115481 ps
CPU time 3.37 seconds
Started Jun 05 05:20:26 PM PDT 24
Finished Jun 05 05:20:30 PM PDT 24
Peak memory 222616 kb
Host smart-69a2560c-6cca-468d-ae34-3114252ef6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051722713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.2051722713
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.2979880966
Short name T65
Test name
Test status
Simulation time 33705208017 ps
CPU time 109.41 seconds
Started Jun 05 05:20:28 PM PDT 24
Finished Jun 05 05:22:18 PM PDT 24
Peak memory 226180 kb
Host smart-bba4612f-862c-4cc9-89cc-4d4260c587f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979880966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.2979880966
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.7914619
Short name T141
Test name
Test status
Simulation time 11330011284 ps
CPU time 107.59 seconds
Started Jun 05 05:20:26 PM PDT 24
Finished Jun 05 05:22:14 PM PDT 24
Peak memory 270184 kb
Host smart-2c9d2707-4201-4d46-a50a-82540ab169ed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=7914619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_stress_all_with_rand_reset.7914619
Directory /workspace/12.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.2685916499
Short name T357
Test name
Test status
Simulation time 40678178 ps
CPU time 0.9 seconds
Started Jun 05 05:20:28 PM PDT 24
Finished Jun 05 05:20:29 PM PDT 24
Peak memory 207928 kb
Host smart-d47bd61c-c013-44cd-9d36-7233faa02ffb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685916499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.2685916499
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.2692716205
Short name T496
Test name
Test status
Simulation time 13932735 ps
CPU time 1.02 seconds
Started Jun 05 05:20:37 PM PDT 24
Finished Jun 05 05:20:39 PM PDT 24
Peak memory 209576 kb
Host smart-ab849186-ae8a-4420-bcc6-2896615428ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692716205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.2692716205
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.2970395351
Short name T92
Test name
Test status
Simulation time 703295701 ps
CPU time 8.06 seconds
Started Jun 05 05:20:29 PM PDT 24
Finished Jun 05 05:20:38 PM PDT 24
Peak memory 218008 kb
Host smart-2e6180ac-3810-4e71-bf33-5c359497605b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970395351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.2970395351
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1105004473
Short name T279
Test name
Test status
Simulation time 1044931296 ps
CPU time 9.57 seconds
Started Jun 05 05:20:35 PM PDT 24
Finished Jun 05 05:20:46 PM PDT 24
Peak memory 209512 kb
Host smart-0c59961b-3f31-495d-a378-aea444cd30b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105004473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1105004473
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.715823401
Short name T654
Test name
Test status
Simulation time 7109519530 ps
CPU time 57.11 seconds
Started Jun 05 05:20:28 PM PDT 24
Finished Jun 05 05:21:27 PM PDT 24
Peak memory 218920 kb
Host smart-d3112f14-c21c-4aea-9cc1-beef73c6b01e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715823401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_er
rors.715823401
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.3916293122
Short name T770
Test name
Test status
Simulation time 418684694 ps
CPU time 5.91 seconds
Started Jun 05 05:20:28 PM PDT 24
Finished Jun 05 05:20:35 PM PDT 24
Peak memory 217948 kb
Host smart-be885dc8-1815-4232-b181-a62bee13a4f1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916293122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jta
g_prog_failure.3916293122
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.739560017
Short name T529
Test name
Test status
Simulation time 593289105 ps
CPU time 15.34 seconds
Started Jun 05 05:20:25 PM PDT 24
Finished Jun 05 05:20:41 PM PDT 24
Peak memory 217636 kb
Host smart-247554ae-46d8-483f-a326-52933492f85b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739560017 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke.
739560017
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3708326021
Short name T266
Test name
Test status
Simulation time 1569220929 ps
CPU time 52.12 seconds
Started Jun 05 05:20:28 PM PDT 24
Finished Jun 05 05:21:22 PM PDT 24
Peak memory 269060 kb
Host smart-385eced0-cc63-4f12-b1de-647d34512b6f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708326021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3708326021
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.267792999
Short name T232
Test name
Test status
Simulation time 320841141 ps
CPU time 11.13 seconds
Started Jun 05 05:20:29 PM PDT 24
Finished Jun 05 05:20:41 PM PDT 24
Peak memory 250284 kb
Host smart-6bfe8a7f-b4a9-4c91-8c39-f3436d79540d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267792999 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_
jtag_state_post_trans.267792999
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.717947128
Short name T84
Test name
Test status
Simulation time 26324930 ps
CPU time 1.74 seconds
Started Jun 05 05:20:29 PM PDT 24
Finished Jun 05 05:20:32 PM PDT 24
Peak memory 218012 kb
Host smart-7935d279-a502-47a0-8f89-dd68ea7ac5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717947128 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.717947128
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.3896903528
Short name T812
Test name
Test status
Simulation time 3274732752 ps
CPU time 18.21 seconds
Started Jun 05 05:20:36 PM PDT 24
Finished Jun 05 05:20:55 PM PDT 24
Peak memory 226148 kb
Host smart-cc885e05-4779-4e5a-918a-67189bafa18a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896903528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.3896903528
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.2668810997
Short name T643
Test name
Test status
Simulation time 282163706 ps
CPU time 10.62 seconds
Started Jun 05 05:20:34 PM PDT 24
Finished Jun 05 05:20:46 PM PDT 24
Peak memory 224972 kb
Host smart-835d9003-3d21-45a4-ac04-8590238477b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668810997 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_d
igest.2668810997
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2404239334
Short name T567
Test name
Test status
Simulation time 376732417 ps
CPU time 8.88 seconds
Started Jun 05 05:20:34 PM PDT 24
Finished Jun 05 05:20:43 PM PDT 24
Peak memory 217988 kb
Host smart-041a607d-a886-40f7-bd31-448af56ece41
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404239334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2404239334
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.4125519299
Short name T346
Test name
Test status
Simulation time 539152788 ps
CPU time 8.53 seconds
Started Jun 05 05:20:27 PM PDT 24
Finished Jun 05 05:20:36 PM PDT 24
Peak memory 225908 kb
Host smart-e3a3dd45-c8a7-46db-852a-306235be625a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125519299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.4125519299
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.2706771605
Short name T577
Test name
Test status
Simulation time 147683872 ps
CPU time 2.41 seconds
Started Jun 05 05:20:29 PM PDT 24
Finished Jun 05 05:20:33 PM PDT 24
Peak memory 214112 kb
Host smart-49f5741e-cd3d-49af-ba3b-8a8c568f0633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706771605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.2706771605
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.232147459
Short name T521
Test name
Test status
Simulation time 1314717408 ps
CPU time 22.27 seconds
Started Jun 05 05:20:26 PM PDT 24
Finished Jun 05 05:20:49 PM PDT 24
Peak memory 250912 kb
Host smart-8fe456fe-3c61-44e2-8abc-17b48091b8d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232147459 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.232147459
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1791030172
Short name T228
Test name
Test status
Simulation time 83756193 ps
CPU time 8.15 seconds
Started Jun 05 05:20:28 PM PDT 24
Finished Jun 05 05:20:37 PM PDT 24
Peak memory 250820 kb
Host smart-9f486f18-5552-4773-8836-b2a9d00cc63c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791030172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1791030172
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.2194945957
Short name T824
Test name
Test status
Simulation time 14930969069 ps
CPU time 69.58 seconds
Started Jun 05 05:20:36 PM PDT 24
Finished Jun 05 05:21:47 PM PDT 24
Peak memory 281164 kb
Host smart-c7923b29-310d-471c-91ae-632f07795c9d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194945957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.2194945957
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.772443887
Short name T231
Test name
Test status
Simulation time 36088877 ps
CPU time 0.94 seconds
Started Jun 05 05:20:28 PM PDT 24
Finished Jun 05 05:20:30 PM PDT 24
Peak memory 211492 kb
Host smart-e714b085-3db1-4b0c-9dcc-9816a6783635
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772443887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ct
rl_volatile_unlock_smoke.772443887
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.3330729199
Short name T674
Test name
Test status
Simulation time 3709976310 ps
CPU time 15.51 seconds
Started Jun 05 05:20:36 PM PDT 24
Finished Jun 05 05:20:53 PM PDT 24
Peak memory 218992 kb
Host smart-5cb5c77f-4d74-4649-be0b-f7f59699e1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330729199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.3330729199
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.808876258
Short name T458
Test name
Test status
Simulation time 1119085567 ps
CPU time 5.88 seconds
Started Jun 05 05:20:37 PM PDT 24
Finished Jun 05 05:20:44 PM PDT 24
Peak memory 209496 kb
Host smart-da220f18-4362-44c9-a416-8b8b600a6f70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808876258 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.808876258
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.2047178565
Short name T817
Test name
Test status
Simulation time 9774184236 ps
CPU time 41.84 seconds
Started Jun 05 05:20:36 PM PDT 24
Finished Jun 05 05:21:19 PM PDT 24
Peak memory 218948 kb
Host smart-b56f8d74-b957-44df-8139-b7fa4acf8f0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047178565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_e
rrors.2047178565
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.2205145350
Short name T272
Test name
Test status
Simulation time 380880776 ps
CPU time 10.49 seconds
Started Jun 05 05:20:39 PM PDT 24
Finished Jun 05 05:20:50 PM PDT 24
Peak memory 217868 kb
Host smart-e7743cc7-10ba-477a-af1c-014cdd9daccb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205145350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jta
g_prog_failure.2205145350
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.2450030325
Short name T72
Test name
Test status
Simulation time 341399319 ps
CPU time 3.36 seconds
Started Jun 05 05:20:38 PM PDT 24
Finished Jun 05 05:20:43 PM PDT 24
Peak memory 217636 kb
Host smart-9411716e-7a22-4684-a17d-1c032deb3832
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450030325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.2450030325
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.1668837491
Short name T82
Test name
Test status
Simulation time 3402450028 ps
CPU time 60.44 seconds
Started Jun 05 05:20:37 PM PDT 24
Finished Jun 05 05:21:39 PM PDT 24
Peak memory 269240 kb
Host smart-9e487096-a4bc-4ec9-94b9-981781ba0bdc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668837491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.1668837491
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.3816515269
Short name T282
Test name
Test status
Simulation time 1351091226 ps
CPU time 7.03 seconds
Started Jun 05 05:20:35 PM PDT 24
Finished Jun 05 05:20:43 PM PDT 24
Peak memory 222752 kb
Host smart-dbdcc601-a0d8-4070-bfa2-ca6dcd7c0c6b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816515269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.3816515269
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.3777077960
Short name T740
Test name
Test status
Simulation time 28957129 ps
CPU time 2.3 seconds
Started Jun 05 05:20:36 PM PDT 24
Finished Jun 05 05:20:39 PM PDT 24
Peak memory 218000 kb
Host smart-12bd08b2-e8a6-4e19-ba76-12cd24fcdead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777077960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.3777077960
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.3481049873
Short name T453
Test name
Test status
Simulation time 821766318 ps
CPU time 10.07 seconds
Started Jun 05 05:20:36 PM PDT 24
Finished Jun 05 05:20:47 PM PDT 24
Peak memory 218064 kb
Host smart-508ee6ae-c3cf-41fe-bdb6-23f0bc132acd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481049873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.3481049873
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.714362801
Short name T469
Test name
Test status
Simulation time 723073416 ps
CPU time 27.4 seconds
Started Jun 05 05:20:37 PM PDT 24
Finished Jun 05 05:21:06 PM PDT 24
Peak memory 226044 kb
Host smart-2227dd67-44e0-4590-ad39-a9419fbec13c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714362801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.714362801
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1598953822
Short name T90
Test name
Test status
Simulation time 945107467 ps
CPU time 7.12 seconds
Started Jun 05 05:20:35 PM PDT 24
Finished Jun 05 05:20:43 PM PDT 24
Peak memory 217948 kb
Host smart-b0701163-fa3b-40d2-b05d-36f4cde42aa0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598953822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1598953822
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2910987773
Short name T41
Test name
Test status
Simulation time 246343255 ps
CPU time 11.61 seconds
Started Jun 05 05:20:37 PM PDT 24
Finished Jun 05 05:20:50 PM PDT 24
Peak memory 218152 kb
Host smart-4e09015b-d9d8-4e9b-a2b9-f1f2e5c4f34f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910987773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2910987773
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.826453935
Short name T463
Test name
Test status
Simulation time 282772817 ps
CPU time 4.43 seconds
Started Jun 05 05:20:39 PM PDT 24
Finished Jun 05 05:20:44 PM PDT 24
Peak memory 217744 kb
Host smart-7c982cff-e505-460f-a305-9759f313aa53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826453935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.826453935
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.2797771253
Short name T666
Test name
Test status
Simulation time 444815822 ps
CPU time 26.55 seconds
Started Jun 05 05:20:34 PM PDT 24
Finished Jun 05 05:21:01 PM PDT 24
Peak memory 250720 kb
Host smart-02cbbf28-7520-47d0-aa69-a4ed95679bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797771253 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.2797771253
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.3877081602
Short name T440
Test name
Test status
Simulation time 362653591 ps
CPU time 9.96 seconds
Started Jun 05 05:20:33 PM PDT 24
Finished Jun 05 05:20:44 PM PDT 24
Peak memory 250920 kb
Host smart-2d2d142c-9cf2-4be9-802d-1d53f175d06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877081602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.3877081602
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.3384782478
Short name T49
Test name
Test status
Simulation time 6147707490 ps
CPU time 98.03 seconds
Started Jun 05 05:20:37 PM PDT 24
Finished Jun 05 05:22:17 PM PDT 24
Peak memory 252120 kb
Host smart-378416d6-c271-455a-935f-b4bba494936d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384782478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.3384782478
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.1600727218
Short name T402
Test name
Test status
Simulation time 39291874 ps
CPU time 0.74 seconds
Started Jun 05 05:20:35 PM PDT 24
Finished Jun 05 05:20:37 PM PDT 24
Peak memory 206780 kb
Host smart-103f3a02-8096-4b90-b9a1-6d37722ebbee
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600727218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_c
trl_volatile_unlock_smoke.1600727218
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.43941185
Short name T584
Test name
Test status
Simulation time 22341027 ps
CPU time 1.26 seconds
Started Jun 05 05:20:44 PM PDT 24
Finished Jun 05 05:20:46 PM PDT 24
Peak memory 208712 kb
Host smart-0aa52c85-a938-42ce-a596-4715766f55cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43941185 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.43941185
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.2637676777
Short name T366
Test name
Test status
Simulation time 124020346 ps
CPU time 2.1 seconds
Started Jun 05 05:20:44 PM PDT 24
Finished Jun 05 05:20:47 PM PDT 24
Peak memory 217780 kb
Host smart-360b6de3-4282-40d8-939a-7bc890f0135d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637676777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.2637676777
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.628439270
Short name T607
Test name
Test status
Simulation time 4935188634 ps
CPU time 70.21 seconds
Started Jun 05 05:20:43 PM PDT 24
Finished Jun 05 05:21:54 PM PDT 24
Peak memory 218952 kb
Host smart-04de9a6b-f308-40b6-a8d7-ac519a318aa3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628439270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_er
rors.628439270
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3923656018
Short name T525
Test name
Test status
Simulation time 460997394 ps
CPU time 13.89 seconds
Started Jun 05 05:20:42 PM PDT 24
Finished Jun 05 05:20:57 PM PDT 24
Peak memory 217884 kb
Host smart-aacea961-d6f3-41b9-97a5-03fb7990b51e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923656018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3923656018
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.3862216003
Short name T830
Test name
Test status
Simulation time 3536584039 ps
CPU time 13.39 seconds
Started Jun 05 05:20:42 PM PDT 24
Finished Jun 05 05:20:56 PM PDT 24
Peak memory 217688 kb
Host smart-6319b873-eb7a-45a4-b191-e6e8f0e280ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862216003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.3862216003
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.1798221523
Short name T212
Test name
Test status
Simulation time 9751442730 ps
CPU time 56.31 seconds
Started Jun 05 05:20:46 PM PDT 24
Finished Jun 05 05:21:43 PM PDT 24
Peak memory 267260 kb
Host smart-837e9dfb-cedb-4e9a-9175-0498a75e2e3c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798221523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jt
ag_state_failure.1798221523
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.1194320909
Short name T202
Test name
Test status
Simulation time 653036032 ps
CPU time 14.83 seconds
Started Jun 05 05:20:45 PM PDT 24
Finished Jun 05 05:21:01 PM PDT 24
Peak memory 250592 kb
Host smart-c43f7b89-dedc-4e0d-a48a-d061247524c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194320909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.1194320909
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.1689664877
Short name T596
Test name
Test status
Simulation time 279616254 ps
CPU time 3.29 seconds
Started Jun 05 05:20:37 PM PDT 24
Finished Jun 05 05:20:42 PM PDT 24
Peak memory 218056 kb
Host smart-cd6a3310-b386-4dfc-bc96-f8c3115ba053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689664877 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.1689664877
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.3333335210
Short name T293
Test name
Test status
Simulation time 279171896 ps
CPU time 12.21 seconds
Started Jun 05 05:20:42 PM PDT 24
Finished Jun 05 05:20:55 PM PDT 24
Peak memory 218184 kb
Host smart-1d8bc042-eaea-4975-8231-5fc571f4ba94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333335210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.3333335210
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.1725381306
Short name T142
Test name
Test status
Simulation time 2444599120 ps
CPU time 8.19 seconds
Started Jun 05 05:20:45 PM PDT 24
Finished Jun 05 05:20:54 PM PDT 24
Peak memory 225812 kb
Host smart-7ae979fa-f6d9-4711-b9c1-7aef2260013a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725381306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.1725381306
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.3591225522
Short name T443
Test name
Test status
Simulation time 3514433834 ps
CPU time 13.1 seconds
Started Jun 05 05:20:45 PM PDT 24
Finished Jun 05 05:20:59 PM PDT 24
Peak memory 217988 kb
Host smart-a3d0e7d7-9c4f-4874-ac8a-30e22c68d367
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591225522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
3591225522
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.3195756018
Short name T614
Test name
Test status
Simulation time 234409919 ps
CPU time 10.39 seconds
Started Jun 05 05:20:43 PM PDT 24
Finished Jun 05 05:20:54 PM PDT 24
Peak memory 218028 kb
Host smart-a5915947-fde6-460f-b521-f0b22ccc3a0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195756018 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.3195756018
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.3348869034
Short name T85
Test name
Test status
Simulation time 59983268 ps
CPU time 2.59 seconds
Started Jun 05 05:20:34 PM PDT 24
Finished Jun 05 05:20:37 PM PDT 24
Peak memory 214192 kb
Host smart-0fd56033-261a-46a5-a9e4-fd9256ff27a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348869034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.3348869034
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.1070235073
Short name T424
Test name
Test status
Simulation time 4722601363 ps
CPU time 29.04 seconds
Started Jun 05 05:20:37 PM PDT 24
Finished Jun 05 05:21:07 PM PDT 24
Peak memory 250948 kb
Host smart-323aae02-24d1-410e-8f04-1f4e97d3a49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070235073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.1070235073
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.1418729648
Short name T412
Test name
Test status
Simulation time 159997945 ps
CPU time 2.71 seconds
Started Jun 05 05:20:37 PM PDT 24
Finished Jun 05 05:20:41 PM PDT 24
Peak memory 222216 kb
Host smart-d4512844-fe99-4f31-8fbf-e8b858b5fb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418729648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.1418729648
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3685663696
Short name T157
Test name
Test status
Simulation time 41490490420 ps
CPU time 242.77 seconds
Started Jun 05 05:20:43 PM PDT 24
Finished Jun 05 05:24:46 PM PDT 24
Peak memory 267372 kb
Host smart-1c14c2a9-cce3-4bdc-846e-5e92fef7e559
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685663696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3685663696
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.2571767774
Short name T730
Test name
Test status
Simulation time 12765166 ps
CPU time 0.92 seconds
Started Jun 05 05:20:36 PM PDT 24
Finished Jun 05 05:20:38 PM PDT 24
Peak memory 211508 kb
Host smart-f473ac3f-7dd9-4a3d-a380-c76a33900bc9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571767774 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_c
trl_volatile_unlock_smoke.2571767774
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2225610803
Short name T62
Test name
Test status
Simulation time 12964262 ps
CPU time 0.84 seconds
Started Jun 05 05:20:52 PM PDT 24
Finished Jun 05 05:20:53 PM PDT 24
Peak memory 209572 kb
Host smart-0731aa57-ce46-4966-a71f-7846beca1176
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225610803 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2225610803
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.3078299003
Short name T425
Test name
Test status
Simulation time 2309945687 ps
CPU time 16.33 seconds
Started Jun 05 05:20:45 PM PDT 24
Finished Jun 05 05:21:03 PM PDT 24
Peak memory 218012 kb
Host smart-74ba2c0a-55e4-4739-a2c3-9895d9c129b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078299003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.3078299003
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.3507659887
Short name T5
Test name
Test status
Simulation time 206404271 ps
CPU time 3.68 seconds
Started Jun 05 05:20:44 PM PDT 24
Finished Jun 05 05:20:49 PM PDT 24
Peak memory 209516 kb
Host smart-b52318b5-2e9e-410e-b8d5-a32e115729e8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507659887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.3507659887
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.3932414962
Short name T750
Test name
Test status
Simulation time 3049776611 ps
CPU time 46.12 seconds
Started Jun 05 05:20:42 PM PDT 24
Finished Jun 05 05:21:29 PM PDT 24
Peak memory 219012 kb
Host smart-3976e453-3906-4bb7-9b20-09afbb03f498
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932414962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_e
rrors.3932414962
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.4291865833
Short name T530
Test name
Test status
Simulation time 5199512633 ps
CPU time 13.55 seconds
Started Jun 05 05:20:46 PM PDT 24
Finished Jun 05 05:21:00 PM PDT 24
Peak memory 217980 kb
Host smart-54d9bc4e-52ce-4b52-969d-2a71f13f3b24
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291865833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.4291865833
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2904111659
Short name T409
Test name
Test status
Simulation time 1205655450 ps
CPU time 9.43 seconds
Started Jun 05 05:20:45 PM PDT 24
Finished Jun 05 05:20:55 PM PDT 24
Peak memory 217680 kb
Host smart-1b5ea8d4-5426-4003-8812-044519feaeb3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904111659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2904111659
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2567874429
Short name T327
Test name
Test status
Simulation time 31551606863 ps
CPU time 52.44 seconds
Started Jun 05 05:20:47 PM PDT 24
Finished Jun 05 05:21:41 PM PDT 24
Peak memory 267320 kb
Host smart-97bdc89d-be26-4fce-b86d-6399d64f9706
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567874429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2567874429
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3140874341
Short name T457
Test name
Test status
Simulation time 289631232 ps
CPU time 10.57 seconds
Started Jun 05 05:20:45 PM PDT 24
Finished Jun 05 05:20:56 PM PDT 24
Peak memory 250704 kb
Host smart-e8246fca-298a-4a4e-8651-f8e39571d813
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140874341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3140874341
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.677234345
Short name T354
Test name
Test status
Simulation time 164246142 ps
CPU time 2.54 seconds
Started Jun 05 05:20:44 PM PDT 24
Finished Jun 05 05:20:47 PM PDT 24
Peak memory 218028 kb
Host smart-d087fd13-5d56-41ee-877c-1a27300ca50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677234345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.677234345
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.2700262076
Short name T804
Test name
Test status
Simulation time 428508445 ps
CPU time 16.28 seconds
Started Jun 05 05:20:42 PM PDT 24
Finished Jun 05 05:20:59 PM PDT 24
Peak memory 218192 kb
Host smart-4985d95f-e1d2-47bb-84a8-b7516a5ebc0f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700262076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2700262076
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1944578279
Short name T220
Test name
Test status
Simulation time 1356822549 ps
CPU time 12.8 seconds
Started Jun 05 05:20:42 PM PDT 24
Finished Jun 05 05:20:55 PM PDT 24
Peak memory 225972 kb
Host smart-e2d1815d-1ef0-42d9-aa5b-71c5ff42d278
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944578279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1944578279
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.268808845
Short name T257
Test name
Test status
Simulation time 419435559 ps
CPU time 14.33 seconds
Started Jun 05 05:20:45 PM PDT 24
Finished Jun 05 05:21:00 PM PDT 24
Peak memory 217940 kb
Host smart-23b086ea-bc9b-441a-9039-5c055496293b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268808845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.268808845
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.84188833
Short name T566
Test name
Test status
Simulation time 97373237 ps
CPU time 3.06 seconds
Started Jun 05 05:20:44 PM PDT 24
Finished Jun 05 05:20:47 PM PDT 24
Peak memory 214428 kb
Host smart-3f9ee633-21cc-4a2e-b290-5144ee4824ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84188833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.84188833
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.1724085643
Short name T866
Test name
Test status
Simulation time 4508903733 ps
CPU time 22.88 seconds
Started Jun 05 05:20:44 PM PDT 24
Finished Jun 05 05:21:08 PM PDT 24
Peak memory 250940 kb
Host smart-4a1f8d5a-e473-4311-a67d-858690107f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724085643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.1724085643
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.4262922209
Short name T622
Test name
Test status
Simulation time 714527953 ps
CPU time 3.1 seconds
Started Jun 05 05:20:45 PM PDT 24
Finished Jun 05 05:20:49 PM PDT 24
Peak memory 222244 kb
Host smart-df03779a-1a6f-451b-bac9-31242a7f4be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262922209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.4262922209
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.736215453
Short name T419
Test name
Test status
Simulation time 11531608214 ps
CPU time 206.63 seconds
Started Jun 05 05:20:45 PM PDT 24
Finished Jun 05 05:24:13 PM PDT 24
Peak memory 281676 kb
Host smart-ffb3e168-4e7f-44f3-b654-076509978c01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736215453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.736215453
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.2847061205
Short name T34
Test name
Test status
Simulation time 33029441526 ps
CPU time 274.27 seconds
Started Jun 05 05:20:54 PM PDT 24
Finished Jun 05 05:25:29 PM PDT 24
Peak memory 282532 kb
Host smart-fa158c8d-9c88-4f0f-8940-aa2f2b30335c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2847061205 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_stress_all_with_rand_reset.2847061205
Directory /workspace/16.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.1628856025
Short name T746
Test name
Test status
Simulation time 50428280 ps
CPU time 0.9 seconds
Started Jun 05 05:20:43 PM PDT 24
Finished Jun 05 05:20:45 PM PDT 24
Peak memory 211460 kb
Host smart-ca9f2ead-e7a4-426f-8210-dc06540d726e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628856025 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.1628856025
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.372649271
Short name T180
Test name
Test status
Simulation time 47381209 ps
CPU time 0.98 seconds
Started Jun 05 05:20:54 PM PDT 24
Finished Jun 05 05:20:56 PM PDT 24
Peak memory 208660 kb
Host smart-7b67286c-be30-4cfd-b59d-2d32ca324b2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372649271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.372649271
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3926881531
Short name T199
Test name
Test status
Simulation time 1620476503 ps
CPU time 16.03 seconds
Started Jun 05 05:20:56 PM PDT 24
Finished Jun 05 05:21:13 PM PDT 24
Peak memory 217936 kb
Host smart-3b2684ac-ed64-49c5-8f97-dd257567a24a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926881531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3926881531
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.1611805334
Short name T25
Test name
Test status
Simulation time 1914413605 ps
CPU time 7.52 seconds
Started Jun 05 05:20:56 PM PDT 24
Finished Jun 05 05:21:04 PM PDT 24
Peak memory 209512 kb
Host smart-e8eb612c-63d4-4a1c-aae4-00f6b352481d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611805334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.1611805334
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1438759151
Short name T486
Test name
Test status
Simulation time 10800426176 ps
CPU time 137.97 seconds
Started Jun 05 05:20:55 PM PDT 24
Finished Jun 05 05:23:14 PM PDT 24
Peak memory 219904 kb
Host smart-02c6a597-6f7a-4394-bedc-9c20068f11fa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438759151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1438759151
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.1756857207
Short name T321
Test name
Test status
Simulation time 289212139 ps
CPU time 9.71 seconds
Started Jun 05 05:20:53 PM PDT 24
Finished Jun 05 05:21:04 PM PDT 24
Peak memory 217928 kb
Host smart-6f343fc0-5ec8-419c-bc65-969d893598fc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756857207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.1756857207
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3347819996
Short name T508
Test name
Test status
Simulation time 261861058 ps
CPU time 8.11 seconds
Started Jun 05 05:20:54 PM PDT 24
Finished Jun 05 05:21:03 PM PDT 24
Peak memory 217624 kb
Host smart-2a7a448a-4d82-4688-8030-c55328da536f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347819996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3347819996
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.1157757651
Short name T230
Test name
Test status
Simulation time 1196061858 ps
CPU time 38.47 seconds
Started Jun 05 05:20:55 PM PDT 24
Finished Jun 05 05:21:34 PM PDT 24
Peak memory 267560 kb
Host smart-0047acee-1ce9-4c7a-8bd4-61c69f754015
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157757651 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.1157757651
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.321147112
Short name T456
Test name
Test status
Simulation time 359820807 ps
CPU time 16.84 seconds
Started Jun 05 05:20:55 PM PDT 24
Finished Jun 05 05:21:13 PM PDT 24
Peak memory 250916 kb
Host smart-0732fa34-df69-4d8a-8ec1-38978a86f8dd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321147112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_
jtag_state_post_trans.321147112
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.4154632379
Short name T811
Test name
Test status
Simulation time 316730320 ps
CPU time 2.9 seconds
Started Jun 05 05:20:56 PM PDT 24
Finished Jun 05 05:20:59 PM PDT 24
Peak memory 218008 kb
Host smart-b4323e9f-b97a-4d06-b9bf-f4d5737b1713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154632379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.4154632379
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.2222910311
Short name T1
Test name
Test status
Simulation time 1493514390 ps
CPU time 12.66 seconds
Started Jun 05 05:20:54 PM PDT 24
Finished Jun 05 05:21:07 PM PDT 24
Peak memory 218784 kb
Host smart-3b070ad7-80c8-4388-af42-66998198fb97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222910311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2222910311
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.2491806482
Short name T317
Test name
Test status
Simulation time 2548517004 ps
CPU time 17.46 seconds
Started Jun 05 05:20:55 PM PDT 24
Finished Jun 05 05:21:13 PM PDT 24
Peak memory 226056 kb
Host smart-db81fcdb-fdcf-41c5-a565-9022ea92bc5d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491806482 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.2491806482
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.4231427566
Short name T52
Test name
Test status
Simulation time 526209478 ps
CPU time 7.8 seconds
Started Jun 05 05:20:52 PM PDT 24
Finished Jun 05 05:21:00 PM PDT 24
Peak memory 217924 kb
Host smart-3da66f43-7cbd-43db-977b-ec09896ecec3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231427566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
4231427566
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.4105396009
Short name T712
Test name
Test status
Simulation time 483475172 ps
CPU time 12.65 seconds
Started Jun 05 05:20:55 PM PDT 24
Finished Jun 05 05:21:09 PM PDT 24
Peak memory 225440 kb
Host smart-a10575d3-badc-47bf-9c36-f2f029e31482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105396009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.4105396009
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.16746781
Short name T229
Test name
Test status
Simulation time 30003417 ps
CPU time 2.37 seconds
Started Jun 05 05:20:54 PM PDT 24
Finished Jun 05 05:20:57 PM PDT 24
Peak memory 214248 kb
Host smart-c7ed4b2d-0494-4850-a7b4-4f47c69e67a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16746781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.16746781
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1449991768
Short name T196
Test name
Test status
Simulation time 283114625 ps
CPU time 34.73 seconds
Started Jun 05 05:20:54 PM PDT 24
Finished Jun 05 05:21:30 PM PDT 24
Peak memory 250936 kb
Host smart-198cbb9c-c845-4b9e-b5ff-55cb94473f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449991768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1449991768
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.581666565
Short name T252
Test name
Test status
Simulation time 306264010 ps
CPU time 8.64 seconds
Started Jun 05 05:20:58 PM PDT 24
Finished Jun 05 05:21:08 PM PDT 24
Peak memory 245232 kb
Host smart-7e8b69c2-b673-4fd4-a12e-d37c86fec3c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581666565 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.581666565
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.1800047744
Short name T678
Test name
Test status
Simulation time 13278076052 ps
CPU time 140.84 seconds
Started Jun 05 05:20:57 PM PDT 24
Finished Jun 05 05:23:18 PM PDT 24
Peak memory 420808 kb
Host smart-e1f91164-d585-4a9b-b6f9-03a20c51fde6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800047744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.1800047744
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.4075059613
Short name T776
Test name
Test status
Simulation time 20136410 ps
CPU time 0.95 seconds
Started Jun 05 05:20:53 PM PDT 24
Finished Jun 05 05:20:55 PM PDT 24
Peak memory 211520 kb
Host smart-ba8137b4-0ab7-4a6a-acfe-d94e1f62208f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075059613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.4075059613
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2865127644
Short name T364
Test name
Test status
Simulation time 82748547 ps
CPU time 0.97 seconds
Started Jun 05 05:21:02 PM PDT 24
Finished Jun 05 05:21:04 PM PDT 24
Peak memory 209552 kb
Host smart-83e22b00-5518-4a2d-aff5-300ebf4bd6dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865127644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2865127644
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.3977302028
Short name T294
Test name
Test status
Simulation time 977782441 ps
CPU time 11.22 seconds
Started Jun 05 05:20:55 PM PDT 24
Finished Jun 05 05:21:07 PM PDT 24
Peak memory 217976 kb
Host smart-82dcf3cf-63be-4f7c-8390-b03c34ed405a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977302028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.3977302028
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.889889789
Short name T24
Test name
Test status
Simulation time 853758885 ps
CPU time 9.6 seconds
Started Jun 05 05:20:53 PM PDT 24
Finished Jun 05 05:21:04 PM PDT 24
Peak memory 209508 kb
Host smart-a0a3f946-0722-4686-a6c2-a69dc2ef1a53
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889889789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.889889789
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1687238125
Short name T690
Test name
Test status
Simulation time 11823641052 ps
CPU time 43.93 seconds
Started Jun 05 05:20:56 PM PDT 24
Finished Jun 05 05:21:40 PM PDT 24
Peak memory 218924 kb
Host smart-394a45e9-c813-42c1-912d-3aec2f4ec449
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687238125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1687238125
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.2089907385
Short name T18
Test name
Test status
Simulation time 1174761120 ps
CPU time 6.03 seconds
Started Jun 05 05:20:55 PM PDT 24
Finished Jun 05 05:21:02 PM PDT 24
Peak memory 218004 kb
Host smart-eb987d19-d9be-4452-8d96-6ed44ba5bd04
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089907385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jta
g_prog_failure.2089907385
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.3468693048
Short name T239
Test name
Test status
Simulation time 427204645 ps
CPU time 2.23 seconds
Started Jun 05 05:20:55 PM PDT 24
Finished Jun 05 05:20:58 PM PDT 24
Peak memory 217620 kb
Host smart-225883c8-f7d2-46ec-a6b2-091da5db529a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468693048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.3468693048
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.3500721630
Short name T203
Test name
Test status
Simulation time 2893326901 ps
CPU time 51.86 seconds
Started Jun 05 05:20:53 PM PDT 24
Finished Jun 05 05:21:46 PM PDT 24
Peak memory 267296 kb
Host smart-b12d4299-b83d-4c5c-9a67-514e44f3712b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500721630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.3500721630
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.265392189
Short name T251
Test name
Test status
Simulation time 1719023387 ps
CPU time 15.37 seconds
Started Jun 05 05:20:55 PM PDT 24
Finished Jun 05 05:21:11 PM PDT 24
Peak memory 245236 kb
Host smart-c49f9384-5fce-4f32-b2b3-ecdd89ea6924
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265392189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_
jtag_state_post_trans.265392189
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.3770038220
Short name T244
Test name
Test status
Simulation time 82035972 ps
CPU time 3.46 seconds
Started Jun 05 05:20:55 PM PDT 24
Finished Jun 05 05:20:59 PM PDT 24
Peak memory 218052 kb
Host smart-36bfb093-905c-4c82-a3ca-b638523e9290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770038220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.3770038220
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.3546381733
Short name T527
Test name
Test status
Simulation time 299229807 ps
CPU time 14.21 seconds
Started Jun 05 05:20:58 PM PDT 24
Finished Jun 05 05:21:13 PM PDT 24
Peak memory 218136 kb
Host smart-bb3c3a38-3389-4017-8a43-1165b2b030fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546381733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.3546381733
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.4113684336
Short name T194
Test name
Test status
Simulation time 1546859804 ps
CPU time 10.49 seconds
Started Jun 05 05:20:59 PM PDT 24
Finished Jun 05 05:21:11 PM PDT 24
Peak memory 224592 kb
Host smart-dd735022-6e17-4d76-b3e8-efd9c09c6408
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113684336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.4113684336
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3426146562
Short name T611
Test name
Test status
Simulation time 238325868 ps
CPU time 6.9 seconds
Started Jun 05 05:21:00 PM PDT 24
Finished Jun 05 05:21:08 PM PDT 24
Peak memory 217936 kb
Host smart-58d4dc83-5dc0-4e0c-9e37-9f996302f088
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426146562 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3426146562
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.2262995336
Short name T613
Test name
Test status
Simulation time 260247664 ps
CPU time 9.83 seconds
Started Jun 05 05:20:54 PM PDT 24
Finished Jun 05 05:21:04 PM PDT 24
Peak memory 218060 kb
Host smart-706c6aaa-9fed-40a2-a1d0-fddb64a5f8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262995336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.2262995336
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.1956497010
Short name T61
Test name
Test status
Simulation time 141710734 ps
CPU time 4.22 seconds
Started Jun 05 05:20:55 PM PDT 24
Finished Jun 05 05:21:01 PM PDT 24
Peak memory 217716 kb
Host smart-d8b8be78-3268-45a6-aec3-5b9f09a50015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956497010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.1956497010
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.1435749733
Short name T298
Test name
Test status
Simulation time 677868171 ps
CPU time 31.73 seconds
Started Jun 05 05:20:55 PM PDT 24
Finished Jun 05 05:21:28 PM PDT 24
Peak memory 250924 kb
Host smart-15a8cfa6-020a-487e-8368-bcb7e6108be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435749733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.1435749733
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.493239520
Short name T478
Test name
Test status
Simulation time 215154899 ps
CPU time 7.43 seconds
Started Jun 05 05:20:58 PM PDT 24
Finished Jun 05 05:21:06 PM PDT 24
Peak memory 250924 kb
Host smart-a082fe21-5aff-4e62-851e-f9c1b2589b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493239520 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.493239520
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.108658260
Short name T55
Test name
Test status
Simulation time 5870669260 ps
CPU time 44.42 seconds
Started Jun 05 05:20:58 PM PDT 24
Finished Jun 05 05:21:44 PM PDT 24
Peak memory 226132 kb
Host smart-1b9f4a6a-6c75-4ea7-906e-6f5c5b6a03ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108658260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.108658260
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1439506809
Short name T762
Test name
Test status
Simulation time 22714884 ps
CPU time 1.09 seconds
Started Jun 05 05:20:54 PM PDT 24
Finished Jun 05 05:20:56 PM PDT 24
Peak memory 212700 kb
Host smart-a612958e-e631-403b-8cad-19e6af734eda
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439506809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.1439506809
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.1090097598
Short name T60
Test name
Test status
Simulation time 64651873 ps
CPU time 1.11 seconds
Started Jun 05 05:21:00 PM PDT 24
Finished Jun 05 05:21:03 PM PDT 24
Peak memory 208740 kb
Host smart-01169dde-a9c3-41be-8ca1-2b0115134ef8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090097598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.1090097598
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.1041463095
Short name T664
Test name
Test status
Simulation time 498307263 ps
CPU time 16.09 seconds
Started Jun 05 05:20:59 PM PDT 24
Finished Jun 05 05:21:16 PM PDT 24
Peak memory 218004 kb
Host smart-0a76ec70-395b-44c3-86a7-6687f86ee1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041463095 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.1041463095
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.3410824539
Short name T26
Test name
Test status
Simulation time 379161777 ps
CPU time 5.56 seconds
Started Jun 05 05:21:04 PM PDT 24
Finished Jun 05 05:21:10 PM PDT 24
Peak memory 216892 kb
Host smart-0ede51eb-5189-42d1-848e-083a19aed963
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410824539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.3410824539
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.3868803094
Short name T548
Test name
Test status
Simulation time 7069188678 ps
CPU time 31.16 seconds
Started Jun 05 05:21:01 PM PDT 24
Finished Jun 05 05:21:33 PM PDT 24
Peak memory 218412 kb
Host smart-18794e24-cb71-4212-b94c-dbf58938d75d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868803094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.3868803094
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.687614830
Short name T765
Test name
Test status
Simulation time 115821453 ps
CPU time 2.64 seconds
Started Jun 05 05:21:00 PM PDT 24
Finished Jun 05 05:21:04 PM PDT 24
Peak memory 217936 kb
Host smart-a594dc9d-5e85-496a-9e66-05f2cef3162c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687614830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag
_prog_failure.687614830
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.615678947
Short name T717
Test name
Test status
Simulation time 916378688 ps
CPU time 3.19 seconds
Started Jun 05 05:21:03 PM PDT 24
Finished Jun 05 05:21:07 PM PDT 24
Peak memory 217636 kb
Host smart-b8b4ce1e-0df7-46e3-b9ba-2da85940e989
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615678947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke.
615678947
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.1469947889
Short name T219
Test name
Test status
Simulation time 7381459566 ps
CPU time 61.96 seconds
Started Jun 05 05:21:04 PM PDT 24
Finished Jun 05 05:22:06 PM PDT 24
Peak memory 276000 kb
Host smart-99bd7f51-7a2c-40df-b906-bc1058db3abd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469947889 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.1469947889
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.993990304
Short name T663
Test name
Test status
Simulation time 2642904678 ps
CPU time 16.59 seconds
Started Jun 05 05:21:02 PM PDT 24
Finished Jun 05 05:21:19 PM PDT 24
Peak memory 250904 kb
Host smart-812f5bad-b015-4b9b-8a2a-9731d860e55a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993990304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_
jtag_state_post_trans.993990304
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.10305179
Short name T433
Test name
Test status
Simulation time 75618734 ps
CPU time 3.31 seconds
Started Jun 05 05:21:00 PM PDT 24
Finished Jun 05 05:21:04 PM PDT 24
Peak memory 217780 kb
Host smart-07948058-3054-48a6-9814-03e03f730caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10305179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.10305179
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.232727879
Short name T650
Test name
Test status
Simulation time 413295550 ps
CPU time 14.92 seconds
Started Jun 05 05:20:59 PM PDT 24
Finished Jun 05 05:21:15 PM PDT 24
Peak memory 226044 kb
Host smart-f2e4aa1b-27a5-402f-acab-4886ffab62a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232727879 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_di
gest.232727879
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.1197903490
Short name T671
Test name
Test status
Simulation time 721527575 ps
CPU time 13.82 seconds
Started Jun 05 05:21:00 PM PDT 24
Finished Jun 05 05:21:15 PM PDT 24
Peak memory 218004 kb
Host smart-fb46b1e4-e2d9-437f-9e41-9b493f40d9f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197903490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
1197903490
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2074388181
Short name T604
Test name
Test status
Simulation time 432482653 ps
CPU time 10.38 seconds
Started Jun 05 05:21:02 PM PDT 24
Finished Jun 05 05:21:13 PM PDT 24
Peak memory 226092 kb
Host smart-fcaf175a-7bd6-42a5-bfd4-3d0b6dc9f7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074388181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2074388181
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.354774540
Short name T688
Test name
Test status
Simulation time 54694264 ps
CPU time 2.63 seconds
Started Jun 05 05:21:01 PM PDT 24
Finished Jun 05 05:21:05 PM PDT 24
Peak memory 214392 kb
Host smart-8ae8f9e4-b956-4904-bc0b-951baaa9c39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354774540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.354774540
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1676816843
Short name T685
Test name
Test status
Simulation time 1206616708 ps
CPU time 24.83 seconds
Started Jun 05 05:20:58 PM PDT 24
Finished Jun 05 05:21:23 PM PDT 24
Peak memory 250880 kb
Host smart-6370501a-8f2e-419d-9a91-50920c136dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676816843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1676816843
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.4112966831
Short name T88
Test name
Test status
Simulation time 229435626 ps
CPU time 3.09 seconds
Started Jun 05 05:20:59 PM PDT 24
Finished Jun 05 05:21:03 PM PDT 24
Peak memory 222396 kb
Host smart-3e49fc4c-c077-4e04-9d2a-56e7280252db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112966831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.4112966831
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.30685206
Short name T499
Test name
Test status
Simulation time 13234943589 ps
CPU time 202.59 seconds
Started Jun 05 05:21:02 PM PDT 24
Finished Jun 05 05:24:25 PM PDT 24
Peak memory 276636 kb
Host smart-992a3386-57a4-4d41-9d82-4b1f0e6ec737
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30685206 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.lc_ctrl_stress_all.30685206
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2144412423
Short name T803
Test name
Test status
Simulation time 12610194 ps
CPU time 1.02 seconds
Started Jun 05 05:21:00 PM PDT 24
Finished Jun 05 05:21:01 PM PDT 24
Peak memory 211460 kb
Host smart-9ff21282-083b-4fb5-890a-774d79156eb8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144412423 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2144412423
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.1035619715
Short name T722
Test name
Test status
Simulation time 19272302 ps
CPU time 1 seconds
Started Jun 05 05:19:36 PM PDT 24
Finished Jun 05 05:19:37 PM PDT 24
Peak memory 209556 kb
Host smart-4428a9f0-8370-4040-a2e5-250841cae454
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035619715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.1035619715
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.3965183132
Short name T559
Test name
Test status
Simulation time 602270484 ps
CPU time 11.13 seconds
Started Jun 05 05:19:30 PM PDT 24
Finished Jun 05 05:19:42 PM PDT 24
Peak memory 218012 kb
Host smart-6df7aed5-e511-495a-bfd0-0c5b1121ae67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965183132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.3965183132
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1690251249
Short name T723
Test name
Test status
Simulation time 312892732 ps
CPU time 4.1 seconds
Started Jun 05 05:19:30 PM PDT 24
Finished Jun 05 05:19:35 PM PDT 24
Peak memory 209596 kb
Host smart-c922125c-0919-43fa-8da7-4ecec5451c21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690251249 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1690251249
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.261643041
Short name T570
Test name
Test status
Simulation time 7424545129 ps
CPU time 28.56 seconds
Started Jun 05 05:19:26 PM PDT 24
Finished Jun 05 05:19:55 PM PDT 24
Peak memory 218548 kb
Host smart-e927555a-0ee6-47c5-9287-4db91fdfd97f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261643041 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_err
ors.261643041
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.2846252498
Short name T329
Test name
Test status
Simulation time 181329741 ps
CPU time 5.43 seconds
Started Jun 05 05:19:33 PM PDT 24
Finished Jun 05 05:19:39 PM PDT 24
Peak memory 217036 kb
Host smart-dca0ea58-c3b2-470b-8c30-a82e1df27fbe
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846252498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.2
846252498
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.4179118985
Short name T247
Test name
Test status
Simulation time 1587246622 ps
CPU time 11.95 seconds
Started Jun 05 05:19:29 PM PDT 24
Finished Jun 05 05:19:42 PM PDT 24
Peak memory 218000 kb
Host smart-5d5ff979-896b-4ea6-b6c6-6bf46a467319
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179118985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.4179118985
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.340449327
Short name T744
Test name
Test status
Simulation time 5555106365 ps
CPU time 19.83 seconds
Started Jun 05 05:19:37 PM PDT 24
Finished Jun 05 05:19:58 PM PDT 24
Peak memory 217696 kb
Host smart-b778077d-0338-48c2-af78-3eaf954b753f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340449327 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.340449327
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.2377657784
Short name T705
Test name
Test status
Simulation time 556348107 ps
CPU time 8.64 seconds
Started Jun 05 05:19:29 PM PDT 24
Finished Jun 05 05:19:38 PM PDT 24
Peak memory 217636 kb
Host smart-c5fe7edd-75ec-4039-81b3-c01b72388369
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377657784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.
2377657784
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.290664709
Short name T360
Test name
Test status
Simulation time 1446332603 ps
CPU time 64.51 seconds
Started Jun 05 05:19:27 PM PDT 24
Finished Jun 05 05:20:32 PM PDT 24
Peak memory 275580 kb
Host smart-28b39858-b742-435f-b398-218c8b4f9a13
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290664709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_state_failure.290664709
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.3962349682
Short name T795
Test name
Test status
Simulation time 1332844015 ps
CPU time 5.82 seconds
Started Jun 05 05:19:26 PM PDT 24
Finished Jun 05 05:19:33 PM PDT 24
Peak memory 221496 kb
Host smart-eedd3814-c169-444b-a571-f458ddf10d5a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962349682 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.3962349682
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.2599211594
Short name T790
Test name
Test status
Simulation time 200691125 ps
CPU time 3.05 seconds
Started Jun 05 05:19:27 PM PDT 24
Finished Jun 05 05:19:31 PM PDT 24
Peak memory 218016 kb
Host smart-0288407a-61fd-4d1e-8a27-8beef22f88a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599211594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.2599211594
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.294451409
Short name T353
Test name
Test status
Simulation time 1634629975 ps
CPU time 14.49 seconds
Started Jun 05 05:19:28 PM PDT 24
Finished Jun 05 05:19:44 PM PDT 24
Peak memory 217720 kb
Host smart-1a8fc160-be72-4d8d-ba24-b66ba4c84510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294451409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.294451409
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.2345475601
Short name T517
Test name
Test status
Simulation time 392209929 ps
CPU time 12.25 seconds
Started Jun 05 05:19:34 PM PDT 24
Finished Jun 05 05:19:47 PM PDT 24
Peak memory 218136 kb
Host smart-59e3d84d-d9c7-4367-835a-bbc335769eaa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345475601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.2345475601
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.93163861
Short name T11
Test name
Test status
Simulation time 3435338974 ps
CPU time 22.96 seconds
Started Jun 05 05:19:35 PM PDT 24
Finished Jun 05 05:19:58 PM PDT 24
Peak memory 226044 kb
Host smart-1506db29-9473-4902-aa3b-451e2fa18ad9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93163861 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_dige
st.93163861
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.3950324938
Short name T475
Test name
Test status
Simulation time 351500891 ps
CPU time 8.72 seconds
Started Jun 05 05:19:32 PM PDT 24
Finished Jun 05 05:19:42 PM PDT 24
Peak memory 218016 kb
Host smart-0d558764-2f91-49b3-8bf0-bb499d7b864d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950324938 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.3
950324938
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.895608012
Short name T15
Test name
Test status
Simulation time 666234646 ps
CPU time 15.65 seconds
Started Jun 05 05:19:27 PM PDT 24
Finished Jun 05 05:19:43 PM PDT 24
Peak memory 225608 kb
Host smart-8701295a-7050-4431-8904-bf10739a54c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895608012 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.895608012
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.245956134
Short name T263
Test name
Test status
Simulation time 121495235 ps
CPU time 2.04 seconds
Started Jun 05 05:19:25 PM PDT 24
Finished Jun 05 05:19:28 PM PDT 24
Peak memory 214092 kb
Host smart-5eed9593-5c0f-4d88-a3c8-98df2f8b98bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245956134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.245956134
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1909578189
Short name T640
Test name
Test status
Simulation time 221905809 ps
CPU time 31.05 seconds
Started Jun 05 05:19:25 PM PDT 24
Finished Jun 05 05:19:57 PM PDT 24
Peak memory 250924 kb
Host smart-c549d30b-0c12-4784-95d8-ce7a282bfe1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909578189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1909578189
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.4261237092
Short name T772
Test name
Test status
Simulation time 95389812 ps
CPU time 7.05 seconds
Started Jun 05 05:19:25 PM PDT 24
Finished Jun 05 05:19:32 PM PDT 24
Peak memory 250728 kb
Host smart-90b5dda5-f323-4295-9209-a536768ff126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4261237092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.4261237092
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.1554715346
Short name T796
Test name
Test status
Simulation time 9785421821 ps
CPU time 323.44 seconds
Started Jun 05 05:19:35 PM PDT 24
Finished Jun 05 05:24:59 PM PDT 24
Peak memory 311640 kb
Host smart-7b785128-a9aa-40cf-ab84-2e42add5cac3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554715346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.1554715346
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.3261936326
Short name T543
Test name
Test status
Simulation time 13407088 ps
CPU time 0.86 seconds
Started Jun 05 05:19:25 PM PDT 24
Finished Jun 05 05:19:26 PM PDT 24
Peak memory 211488 kb
Host smart-a373b9d7-e50d-4bab-bfda-710b46eecc8d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261936326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.3261936326
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.2807105830
Short name T713
Test name
Test status
Simulation time 129161000 ps
CPU time 1.41 seconds
Started Jun 05 05:21:05 PM PDT 24
Finished Jun 05 05:21:07 PM PDT 24
Peak memory 208680 kb
Host smart-413b836a-1b6c-4d1d-974b-21c8e7510a0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807105830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.2807105830
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3411700619
Short name T361
Test name
Test status
Simulation time 3192650083 ps
CPU time 19.83 seconds
Started Jun 05 05:21:00 PM PDT 24
Finished Jun 05 05:21:21 PM PDT 24
Peak memory 219000 kb
Host smart-ec4ec7ec-73f4-4e4f-a5bf-2dfddf00ea8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411700619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3411700619
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.4222389688
Short name T814
Test name
Test status
Simulation time 1967532718 ps
CPU time 23.52 seconds
Started Jun 05 05:21:06 PM PDT 24
Finished Jun 05 05:21:31 PM PDT 24
Peak memory 209520 kb
Host smart-539890e7-8391-4830-87a1-8b2c3faefa21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222389688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.4222389688
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.2552849663
Short name T97
Test name
Test status
Simulation time 33666851 ps
CPU time 1.61 seconds
Started Jun 05 05:21:00 PM PDT 24
Finished Jun 05 05:21:03 PM PDT 24
Peak memory 218008 kb
Host smart-b73b0f7c-cd22-482f-a373-ed45108d6543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552849663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.2552849663
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.2081656263
Short name T662
Test name
Test status
Simulation time 1108396464 ps
CPU time 12.49 seconds
Started Jun 05 05:21:08 PM PDT 24
Finished Jun 05 05:21:21 PM PDT 24
Peak memory 218944 kb
Host smart-028e1cd8-71bf-4b60-8a96-04c0312f2690
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081656263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.2081656263
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.4138378492
Short name T714
Test name
Test status
Simulation time 711742289 ps
CPU time 13.59 seconds
Started Jun 05 05:21:08 PM PDT 24
Finished Jun 05 05:21:22 PM PDT 24
Peak memory 226028 kb
Host smart-db6701a3-4fcc-408c-8cb2-75d558054f42
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138378492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_d
igest.4138378492
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2019679462
Short name T724
Test name
Test status
Simulation time 649925422 ps
CPU time 8.89 seconds
Started Jun 05 05:21:06 PM PDT 24
Finished Jun 05 05:21:16 PM PDT 24
Peak memory 218036 kb
Host smart-706c6817-8abd-4b30-9402-cb535982ed4e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019679462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2019679462
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.3949442124
Short name T823
Test name
Test status
Simulation time 748564096 ps
CPU time 9.48 seconds
Started Jun 05 05:20:59 PM PDT 24
Finished Jun 05 05:21:09 PM PDT 24
Peak memory 225896 kb
Host smart-5bbf5306-dd32-48f5-a1fc-36cd39213277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949442124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.3949442124
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.1125203464
Short name T761
Test name
Test status
Simulation time 386881000 ps
CPU time 2.62 seconds
Started Jun 05 05:21:00 PM PDT 24
Finished Jun 05 05:21:04 PM PDT 24
Peak memory 217688 kb
Host smart-e410587d-bb6d-4ed7-b6b4-2d1b4ab8b4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125203464 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.1125203464
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3160707052
Short name T612
Test name
Test status
Simulation time 2087120917 ps
CPU time 20.69 seconds
Started Jun 05 05:21:01 PM PDT 24
Finished Jun 05 05:21:23 PM PDT 24
Peak memory 250900 kb
Host smart-e9c163bd-ab7b-45c8-a71d-2ab9c3054fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160707052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3160707052
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.2653385592
Short name T464
Test name
Test status
Simulation time 53963690 ps
CPU time 6.77 seconds
Started Jun 05 05:21:02 PM PDT 24
Finished Jun 05 05:21:09 PM PDT 24
Peak memory 250352 kb
Host smart-63ec9250-8c75-46f0-bd03-3f592a5100a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653385592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.2653385592
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3027908495
Short name T99
Test name
Test status
Simulation time 87473499425 ps
CPU time 206.31 seconds
Started Jun 05 05:21:05 PM PDT 24
Finished Jun 05 05:24:31 PM PDT 24
Peak memory 267352 kb
Host smart-a363103b-55b0-4659-83a7-0b25af4bb6f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027908495 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3027908495
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1211440088
Short name T184
Test name
Test status
Simulation time 14699658 ps
CPU time 0.93 seconds
Started Jun 05 05:20:59 PM PDT 24
Finished Jun 05 05:21:01 PM PDT 24
Peak memory 211516 kb
Host smart-a9461cf3-17ed-4cd3-b46e-59c5eb05530a
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211440088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_c
trl_volatile_unlock_smoke.1211440088
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.2580556964
Short name T222
Test name
Test status
Simulation time 59646109 ps
CPU time 1.08 seconds
Started Jun 05 05:21:06 PM PDT 24
Finished Jun 05 05:21:08 PM PDT 24
Peak memory 209688 kb
Host smart-6c2a4f26-1b88-49d3-ac55-64d957de819d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580556964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.2580556964
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.3253911934
Short name T450
Test name
Test status
Simulation time 295141234 ps
CPU time 11.74 seconds
Started Jun 05 05:21:07 PM PDT 24
Finished Jun 05 05:21:20 PM PDT 24
Peak memory 217908 kb
Host smart-6b3a1e21-ba19-425e-9604-e8af94dafd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253911934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.3253911934
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.2110074390
Short name T284
Test name
Test status
Simulation time 544618388 ps
CPU time 5.37 seconds
Started Jun 05 05:21:06 PM PDT 24
Finished Jun 05 05:21:12 PM PDT 24
Peak memory 209480 kb
Host smart-7ebedd62-e6c6-43e8-a817-497b2b7fd60f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110074390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.2110074390
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.47671781
Short name T221
Test name
Test status
Simulation time 47713196 ps
CPU time 2.86 seconds
Started Jun 05 05:21:08 PM PDT 24
Finished Jun 05 05:21:12 PM PDT 24
Peak memory 218004 kb
Host smart-386cca93-6f37-4c48-8340-5dc670a3a3da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47671781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.47671781
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.2229110033
Short name T315
Test name
Test status
Simulation time 2225598141 ps
CPU time 14.08 seconds
Started Jun 05 05:21:05 PM PDT 24
Finished Jun 05 05:21:20 PM PDT 24
Peak memory 218196 kb
Host smart-c16bd23f-6210-4df6-b36f-0b0b2c5e1e98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229110033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.2229110033
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1809525510
Short name T835
Test name
Test status
Simulation time 1457254052 ps
CPU time 11.45 seconds
Started Jun 05 05:21:04 PM PDT 24
Finished Jun 05 05:21:16 PM PDT 24
Peak memory 226024 kb
Host smart-5d8fc3dc-1f96-447d-91ee-3984306f24ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809525510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1809525510
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.4093049555
Short name T594
Test name
Test status
Simulation time 2779714938 ps
CPU time 15.25 seconds
Started Jun 05 05:21:04 PM PDT 24
Finished Jun 05 05:21:20 PM PDT 24
Peak memory 218060 kb
Host smart-91e65566-b56b-4746-84df-e624f046668c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093049555 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
4093049555
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.3065910754
Short name T741
Test name
Test status
Simulation time 3949648697 ps
CPU time 11.14 seconds
Started Jun 05 05:21:05 PM PDT 24
Finished Jun 05 05:21:17 PM PDT 24
Peak memory 218180 kb
Host smart-22553888-abbe-4764-8190-cb4b5a1b8f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065910754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.3065910754
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.3651409286
Short name T348
Test name
Test status
Simulation time 212414136 ps
CPU time 4.57 seconds
Started Jun 05 05:21:09 PM PDT 24
Finished Jun 05 05:21:14 PM PDT 24
Peak memory 217712 kb
Host smart-81e414e5-72a9-4e44-afd3-6912fe452981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651409286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.3651409286
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.1252699427
Short name T261
Test name
Test status
Simulation time 700564397 ps
CPU time 31.38 seconds
Started Jun 05 05:21:06 PM PDT 24
Finished Jun 05 05:21:38 PM PDT 24
Peak memory 250920 kb
Host smart-cc66eb44-ad1b-496c-9137-9ad9d23d6699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252699427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.1252699427
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.2974392148
Short name T780
Test name
Test status
Simulation time 341043348 ps
CPU time 8.78 seconds
Started Jun 05 05:21:07 PM PDT 24
Finished Jun 05 05:21:16 PM PDT 24
Peak memory 250876 kb
Host smart-311d3eff-83ee-4125-ad4a-8c00c5f7258c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974392148 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.2974392148
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2003444303
Short name T241
Test name
Test status
Simulation time 21006344824 ps
CPU time 129.88 seconds
Started Jun 05 05:21:07 PM PDT 24
Finished Jun 05 05:23:18 PM PDT 24
Peak memory 250960 kb
Host smart-d4177681-727b-457a-ae51-ee0889ffb52d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003444303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2003444303
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1236688034
Short name T588
Test name
Test status
Simulation time 20638825 ps
CPU time 0.82 seconds
Started Jun 05 05:21:05 PM PDT 24
Finished Jun 05 05:21:07 PM PDT 24
Peak memory 211496 kb
Host smart-af5c37f2-b9e2-473e-b66d-ff1e4c0d41f6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236688034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1236688034
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.1474624639
Short name T80
Test name
Test status
Simulation time 43004523 ps
CPU time 0.97 seconds
Started Jun 05 05:21:14 PM PDT 24
Finished Jun 05 05:21:16 PM PDT 24
Peak memory 209568 kb
Host smart-3381fbac-631c-459e-a094-ef428e3bb5a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474624639 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.1474624639
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.1192083235
Short name T555
Test name
Test status
Simulation time 4002459910 ps
CPU time 14.67 seconds
Started Jun 05 05:21:08 PM PDT 24
Finished Jun 05 05:21:23 PM PDT 24
Peak memory 218132 kb
Host smart-cdca5e9e-2fa6-4439-95e3-ae6d7d029885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192083235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.1192083235
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.767198056
Short name T434
Test name
Test status
Simulation time 3380888851 ps
CPU time 8.88 seconds
Started Jun 05 05:21:15 PM PDT 24
Finished Jun 05 05:21:25 PM PDT 24
Peak memory 217816 kb
Host smart-b081f2d8-e76a-409c-af27-4fc564538d1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767198056 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.767198056
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.1670978468
Short name T608
Test name
Test status
Simulation time 166956717 ps
CPU time 2.79 seconds
Started Jun 05 05:21:04 PM PDT 24
Finished Jun 05 05:21:07 PM PDT 24
Peak memory 218016 kb
Host smart-d098966c-4761-4a02-966a-9edaea5c11d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670978468 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.1670978468
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.1362814647
Short name T681
Test name
Test status
Simulation time 553842868 ps
CPU time 20.28 seconds
Started Jun 05 05:21:16 PM PDT 24
Finished Jun 05 05:21:38 PM PDT 24
Peak memory 218956 kb
Host smart-9f72f3a8-bb32-46d6-afe2-6a07e5dbc1da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362814647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.1362814647
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1018236176
Short name T565
Test name
Test status
Simulation time 1774827087 ps
CPU time 11.52 seconds
Started Jun 05 05:21:14 PM PDT 24
Finished Jun 05 05:21:27 PM PDT 24
Peak memory 226028 kb
Host smart-a844b2a2-af32-4366-92b8-1b770663dc9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018236176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1018236176
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.3339740084
Short name T719
Test name
Test status
Simulation time 278008357 ps
CPU time 11.32 seconds
Started Jun 05 05:21:13 PM PDT 24
Finished Jun 05 05:21:26 PM PDT 24
Peak memory 218144 kb
Host smart-77d10f80-644f-4d68-a46e-dfaf468dee09
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339740084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
3339740084
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3748059690
Short name T829
Test name
Test status
Simulation time 2399676329 ps
CPU time 13.13 seconds
Started Jun 05 05:21:09 PM PDT 24
Finished Jun 05 05:21:22 PM PDT 24
Peak memory 225660 kb
Host smart-2e0c09d6-1a4f-4184-b0f8-061944a475f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748059690 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3748059690
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.1923588104
Short name T426
Test name
Test status
Simulation time 143674413 ps
CPU time 2.73 seconds
Started Jun 05 05:21:07 PM PDT 24
Finished Jun 05 05:21:10 PM PDT 24
Peak memory 214224 kb
Host smart-c1f82286-0920-497e-ba0d-88a5d25e1637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923588104 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.1923588104
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.3312823232
Short name T655
Test name
Test status
Simulation time 838157578 ps
CPU time 21.34 seconds
Started Jun 05 05:21:08 PM PDT 24
Finished Jun 05 05:21:30 PM PDT 24
Peak memory 250860 kb
Host smart-218b5df3-7b55-48d6-af36-1e664bee849c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312823232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.3312823232
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.2091115589
Short name T395
Test name
Test status
Simulation time 159339571 ps
CPU time 4.57 seconds
Started Jun 05 05:21:08 PM PDT 24
Finished Jun 05 05:21:14 PM PDT 24
Peak memory 222832 kb
Host smart-fa89f1e0-d448-4fd7-bc99-1220109d2a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091115589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.2091115589
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.1293871313
Short name T684
Test name
Test status
Simulation time 9810831189 ps
CPU time 307.68 seconds
Started Jun 05 05:21:16 PM PDT 24
Finished Jun 05 05:26:25 PM PDT 24
Peak memory 250960 kb
Host smart-6e75feed-c797-4b38-a726-63abc9e085f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293871313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.1293871313
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all_with_rand_reset.2388517218
Short name T495
Test name
Test status
Simulation time 26092087625 ps
CPU time 930.75 seconds
Started Jun 05 05:21:14 PM PDT 24
Finished Jun 05 05:36:46 PM PDT 24
Peak memory 422108 kb
Host smart-0022f17d-a23d-474c-b615-923406991217
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2388517218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_stress_all_with_rand_reset.2388517218
Directory /workspace/22.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.2841675083
Short name T627
Test name
Test status
Simulation time 14619966 ps
CPU time 0.94 seconds
Started Jun 05 05:21:09 PM PDT 24
Finished Jun 05 05:21:11 PM PDT 24
Peak memory 212544 kb
Host smart-d7fb419e-d334-400c-84e2-c1b8735a263f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841675083 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_c
trl_volatile_unlock_smoke.2841675083
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.2579827479
Short name T544
Test name
Test status
Simulation time 13322194 ps
CPU time 1.01 seconds
Started Jun 05 05:21:12 PM PDT 24
Finished Jun 05 05:21:14 PM PDT 24
Peak memory 208740 kb
Host smart-20556a64-e5f7-483f-828a-ee2ec2fa8aa1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579827479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.2579827479
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.1175126633
Short name T35
Test name
Test status
Simulation time 429027640 ps
CPU time 8.19 seconds
Started Jun 05 05:21:16 PM PDT 24
Finished Jun 05 05:21:25 PM PDT 24
Peak memory 217840 kb
Host smart-03dcebc8-37ee-44be-8db9-9f72e6d91c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175126633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.1175126633
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.2020291297
Short name T721
Test name
Test status
Simulation time 460988398 ps
CPU time 3.43 seconds
Started Jun 05 05:21:14 PM PDT 24
Finished Jun 05 05:21:19 PM PDT 24
Peak memory 209512 kb
Host smart-f793b16f-1fe7-4ecd-b543-592887dbb8de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020291297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.2020291297
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.412075852
Short name T242
Test name
Test status
Simulation time 321726850 ps
CPU time 4.29 seconds
Started Jun 05 05:21:14 PM PDT 24
Finished Jun 05 05:21:19 PM PDT 24
Peak memory 218060 kb
Host smart-a2a36906-6b61-4d42-9273-73e93fabda90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412075852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.412075852
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.1141994581
Short name T838
Test name
Test status
Simulation time 502705357 ps
CPU time 22.87 seconds
Started Jun 05 05:21:16 PM PDT 24
Finished Jun 05 05:21:40 PM PDT 24
Peak memory 218932 kb
Host smart-7a993436-1f55-445c-ab55-22f48714bb9f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141994581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.1141994581
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.3103315334
Short name T549
Test name
Test status
Simulation time 306972890 ps
CPU time 9.1 seconds
Started Jun 05 05:21:16 PM PDT 24
Finished Jun 05 05:21:26 PM PDT 24
Peak memory 226044 kb
Host smart-f5d5e300-7332-462c-980c-eb4d17e6b8a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103315334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_d
igest.3103315334
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.3858903156
Short name T862
Test name
Test status
Simulation time 936188736 ps
CPU time 9.18 seconds
Started Jun 05 05:21:16 PM PDT 24
Finished Jun 05 05:21:26 PM PDT 24
Peak memory 217944 kb
Host smart-917856a6-07ef-46c9-ba4d-a96f3e7d230c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858903156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
3858903156
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2534841694
Short name T505
Test name
Test status
Simulation time 319657089 ps
CPU time 11.68 seconds
Started Jun 05 05:21:16 PM PDT 24
Finished Jun 05 05:21:28 PM PDT 24
Peak memory 225760 kb
Host smart-16b6e502-e668-49fa-b7ce-f1bf3b744c16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534841694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2534841694
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1457209411
Short name T89
Test name
Test status
Simulation time 130541546 ps
CPU time 1.86 seconds
Started Jun 05 05:21:16 PM PDT 24
Finished Jun 05 05:21:20 PM PDT 24
Peak memory 217708 kb
Host smart-7a618d4a-6520-4518-a41f-81daa1cf8408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457209411 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1457209411
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.763942285
Short name T805
Test name
Test status
Simulation time 208285985 ps
CPU time 19.9 seconds
Started Jun 05 05:21:14 PM PDT 24
Finished Jun 05 05:21:35 PM PDT 24
Peak memory 250956 kb
Host smart-ae152c9f-b68e-4368-94da-ffb8e01ff944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763942285 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.763942285
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.1277675975
Short name T749
Test name
Test status
Simulation time 217500611 ps
CPU time 3.76 seconds
Started Jun 05 05:21:14 PM PDT 24
Finished Jun 05 05:21:19 PM PDT 24
Peak memory 226280 kb
Host smart-2a9db52c-fd77-4b4d-8b9a-615201be062b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277675975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.1277675975
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3797136415
Short name T280
Test name
Test status
Simulation time 10596409605 ps
CPU time 346.33 seconds
Started Jun 05 05:21:16 PM PDT 24
Finished Jun 05 05:27:04 PM PDT 24
Peak memory 267340 kb
Host smart-614bd136-6a53-4ac3-9ec0-a147a1458586
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797136415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3797136415
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all_with_rand_reset.2323698299
Short name T592
Test name
Test status
Simulation time 29506239903 ps
CPU time 496.89 seconds
Started Jun 05 05:21:13 PM PDT 24
Finished Jun 05 05:29:31 PM PDT 24
Peak memory 447716 kb
Host smart-41730ee2-b5d1-4dab-bc8f-cec5246e602c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2323698299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_stress_all_with_rand_reset.2323698299
Directory /workspace/23.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.2678067792
Short name T444
Test name
Test status
Simulation time 32048292 ps
CPU time 0.9 seconds
Started Jun 05 05:21:15 PM PDT 24
Finished Jun 05 05:21:17 PM PDT 24
Peak memory 211392 kb
Host smart-69bb7917-c527-445f-9f0c-e84a176888b6
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678067792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_c
trl_volatile_unlock_smoke.2678067792
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.690249986
Short name T491
Test name
Test status
Simulation time 22883719 ps
CPU time 0.93 seconds
Started Jun 05 05:21:22 PM PDT 24
Finished Jun 05 05:21:23 PM PDT 24
Peak memory 208740 kb
Host smart-abfabcca-0117-4554-bb60-d23d55713b81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690249986 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.690249986
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.1932638697
Short name T547
Test name
Test status
Simulation time 626290382 ps
CPU time 13.68 seconds
Started Jun 05 05:21:23 PM PDT 24
Finished Jun 05 05:21:38 PM PDT 24
Peak memory 218076 kb
Host smart-c202c0d7-aba1-4ff6-989c-e8596f20b689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932638697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.1932638697
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2570471579
Short name T414
Test name
Test status
Simulation time 4617731326 ps
CPU time 9.86 seconds
Started Jun 05 05:21:22 PM PDT 24
Finished Jun 05 05:21:32 PM PDT 24
Peak memory 217540 kb
Host smart-dd219fd3-7e59-4adc-a078-fa9bb7437d98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570471579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2570471579
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.2130050537
Short name T635
Test name
Test status
Simulation time 234925778 ps
CPU time 2.68 seconds
Started Jun 05 05:21:16 PM PDT 24
Finished Jun 05 05:21:20 PM PDT 24
Peak memory 218080 kb
Host smart-48a3d1e4-f74d-40bb-9299-732167868dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130050537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.2130050537
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.1819008843
Short name T603
Test name
Test status
Simulation time 753762510 ps
CPU time 10.87 seconds
Started Jun 05 05:21:22 PM PDT 24
Finished Jun 05 05:21:33 PM PDT 24
Peak memory 217992 kb
Host smart-4232b769-9d61-470b-a859-60d863376243
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819008843 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.1819008843
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.1895155829
Short name T715
Test name
Test status
Simulation time 1246807489 ps
CPU time 10.38 seconds
Started Jun 05 05:21:24 PM PDT 24
Finished Jun 05 05:21:35 PM PDT 24
Peak memory 225820 kb
Host smart-b570814e-8a09-41ab-a9dd-3ef2beeb1070
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895155829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_d
igest.1895155829
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.395845114
Short name T783
Test name
Test status
Simulation time 2311815856 ps
CPU time 10.37 seconds
Started Jun 05 05:21:25 PM PDT 24
Finished Jun 05 05:21:36 PM PDT 24
Peak memory 218060 kb
Host smart-f88f1d81-7999-4701-b25f-d64a4b7fcab4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395845114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.395845114
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3113430070
Short name T590
Test name
Test status
Simulation time 265387795 ps
CPU time 10.84 seconds
Started Jun 05 05:21:13 PM PDT 24
Finished Jun 05 05:21:25 PM PDT 24
Peak memory 218052 kb
Host smart-e32dd3e9-f976-4d5c-9b9a-7da4dfa5f8a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113430070 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3113430070
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.3611727717
Short name T71
Test name
Test status
Simulation time 824704541 ps
CPU time 7.28 seconds
Started Jun 05 05:21:14 PM PDT 24
Finished Jun 05 05:21:22 PM PDT 24
Peak memory 217692 kb
Host smart-239173d7-488b-46ac-8ff9-c764daf6a5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611727717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.3611727717
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.853731320
Short name T734
Test name
Test status
Simulation time 375204166 ps
CPU time 40.84 seconds
Started Jun 05 05:21:14 PM PDT 24
Finished Jun 05 05:21:56 PM PDT 24
Peak memory 250940 kb
Host smart-6f57ab56-93fb-4bc4-a775-160cd6467afb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853731320 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.853731320
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.4163286664
Short name T669
Test name
Test status
Simulation time 395497436 ps
CPU time 9.43 seconds
Started Jun 05 05:21:13 PM PDT 24
Finished Jun 05 05:21:23 PM PDT 24
Peak memory 250880 kb
Host smart-e78c5fac-2f03-49fd-b0a9-d45fc559847b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163286664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.4163286664
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.364427522
Short name T58
Test name
Test status
Simulation time 24035280479 ps
CPU time 110.95 seconds
Started Jun 05 05:21:23 PM PDT 24
Finished Jun 05 05:23:15 PM PDT 24
Peak memory 250988 kb
Host smart-f638cba1-7df2-4dff-bee4-63608c2c9fe7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364427522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.364427522
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all_with_rand_reset.1010187534
Short name T182
Test name
Test status
Simulation time 64288896242 ps
CPU time 1638.32 seconds
Started Jun 05 05:21:23 PM PDT 24
Finished Jun 05 05:48:42 PM PDT 24
Peak memory 643948 kb
Host smart-c0a9afa3-7069-41f6-a3f9-2237e17af2f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1010187534 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_stress_all_with_rand_reset.1010187534
Directory /workspace/24.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.2147269338
Short name T216
Test name
Test status
Simulation time 30222011 ps
CPU time 0.73 seconds
Started Jun 05 05:21:14 PM PDT 24
Finished Jun 05 05:21:16 PM PDT 24
Peak memory 206760 kb
Host smart-ee93b872-2a23-4102-8a1e-00592ec5d4af
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147269338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.2147269338
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1353708702
Short name T787
Test name
Test status
Simulation time 22075676 ps
CPU time 1.26 seconds
Started Jun 05 05:21:22 PM PDT 24
Finished Jun 05 05:21:24 PM PDT 24
Peak memory 208764 kb
Host smart-1df0ba32-5330-4b62-abaf-b438212daffc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353708702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1353708702
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.3468224709
Short name T338
Test name
Test status
Simulation time 1522967720 ps
CPU time 11.14 seconds
Started Jun 05 05:21:24 PM PDT 24
Finished Jun 05 05:21:36 PM PDT 24
Peak memory 217972 kb
Host smart-bb22a0f2-a3ec-486a-92c1-19c2016431bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3468224709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.3468224709
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.1544287888
Short name T152
Test name
Test status
Simulation time 1273838198 ps
CPU time 4.61 seconds
Started Jun 05 05:21:22 PM PDT 24
Finished Jun 05 05:21:27 PM PDT 24
Peak memory 209516 kb
Host smart-c434a767-4a99-47b0-9aa5-039b2b7cc3d9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544287888 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.1544287888
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.2009150422
Short name T786
Test name
Test status
Simulation time 134525511 ps
CPU time 3.28 seconds
Started Jun 05 05:21:22 PM PDT 24
Finished Jun 05 05:21:26 PM PDT 24
Peak memory 218032 kb
Host smart-20983ba9-cac1-4d32-b19e-5c1d063f2a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009150422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.2009150422
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.4195142366
Short name T509
Test name
Test status
Simulation time 373168586 ps
CPU time 10.6 seconds
Started Jun 05 05:21:24 PM PDT 24
Finished Jun 05 05:21:35 PM PDT 24
Peak memory 218512 kb
Host smart-6fe4d6d4-3b7a-4bca-ac8f-f022463c4b0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195142366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.4195142366
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.1798449421
Short name T506
Test name
Test status
Simulation time 282730017 ps
CPU time 11.35 seconds
Started Jun 05 05:21:23 PM PDT 24
Finished Jun 05 05:21:36 PM PDT 24
Peak memory 226032 kb
Host smart-c57f6daf-7061-4176-b44a-2918b7226427
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798449421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.1798449421
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.3835559263
Short name T626
Test name
Test status
Simulation time 4244459878 ps
CPU time 15.71 seconds
Started Jun 05 05:21:23 PM PDT 24
Finished Jun 05 05:21:40 PM PDT 24
Peak memory 217996 kb
Host smart-748f7192-0e55-453b-934f-632359270088
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835559263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.
3835559263
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.1644332977
Short name T156
Test name
Test status
Simulation time 612782384 ps
CPU time 8.39 seconds
Started Jun 05 05:21:22 PM PDT 24
Finished Jun 05 05:21:30 PM PDT 24
Peak memory 225108 kb
Host smart-04f377f9-0676-41ec-8d87-fbb7797dcc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644332977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.1644332977
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.2879287696
Short name T865
Test name
Test status
Simulation time 54632325 ps
CPU time 3.39 seconds
Started Jun 05 05:21:22 PM PDT 24
Finished Jun 05 05:21:26 PM PDT 24
Peak memory 217720 kb
Host smart-3eae878a-7f8c-4e02-a12d-9ecba395a0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879287696 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.2879287696
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.507518616
Short name T319
Test name
Test status
Simulation time 271417758 ps
CPU time 25.96 seconds
Started Jun 05 05:21:25 PM PDT 24
Finished Jun 05 05:21:51 PM PDT 24
Peak memory 250908 kb
Host smart-7f9dedae-35ae-4564-bf8b-6f6b9cc52b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507518616 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.507518616
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.2332050291
Short name T365
Test name
Test status
Simulation time 924645457 ps
CPU time 9.31 seconds
Started Jun 05 05:21:22 PM PDT 24
Finished Jun 05 05:21:32 PM PDT 24
Peak memory 251064 kb
Host smart-fa0e254c-79cb-4f58-97cb-e0bb435c292f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332050291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.2332050291
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.1356158432
Short name T859
Test name
Test status
Simulation time 20840561443 ps
CPU time 352.86 seconds
Started Jun 05 05:21:23 PM PDT 24
Finished Jun 05 05:27:17 PM PDT 24
Peak memory 283736 kb
Host smart-e4ae5f3f-bb4a-4087-a4bb-5864519f8f21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356158432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.1356158432
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2117977777
Short name T258
Test name
Test status
Simulation time 11542841 ps
CPU time 1.07 seconds
Started Jun 05 05:21:24 PM PDT 24
Finished Jun 05 05:21:25 PM PDT 24
Peak memory 211452 kb
Host smart-1b528b7f-14bf-4d4b-8dbe-47422af21998
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117977777 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.2117977777
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.87249387
Short name T243
Test name
Test status
Simulation time 23405008 ps
CPU time 1.26 seconds
Started Jun 05 05:21:22 PM PDT 24
Finished Jun 05 05:21:24 PM PDT 24
Peak memory 208808 kb
Host smart-ac281a83-bdaf-4589-8121-41c0c0763292
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87249387 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.87249387
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.3590530178
Short name T500
Test name
Test status
Simulation time 1687926456 ps
CPU time 16.46 seconds
Started Jun 05 05:21:24 PM PDT 24
Finished Jun 05 05:21:41 PM PDT 24
Peak memory 218020 kb
Host smart-6df4e43f-e73a-498a-9257-e2431c71aa70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590530178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.3590530178
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.3490953994
Short name T580
Test name
Test status
Simulation time 867134828 ps
CPU time 12.9 seconds
Started Jun 05 05:21:27 PM PDT 24
Finished Jun 05 05:21:40 PM PDT 24
Peak memory 209500 kb
Host smart-bd2406b1-ef85-432a-a710-6d40770d9659
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490953994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.3490953994
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.717773531
Short name T349
Test name
Test status
Simulation time 186743728 ps
CPU time 2.19 seconds
Started Jun 05 05:21:24 PM PDT 24
Finished Jun 05 05:21:27 PM PDT 24
Peak memory 218088 kb
Host smart-dcd443c9-fcd5-4e91-8f15-b5c870305a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717773531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.717773531
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.376278937
Short name T411
Test name
Test status
Simulation time 2794935525 ps
CPU time 19.7 seconds
Started Jun 05 05:21:25 PM PDT 24
Finished Jun 05 05:21:46 PM PDT 24
Peak memory 218180 kb
Host smart-2d6eb068-a908-4cb5-8a7f-d3ac385ce5bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376278937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.376278937
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2390352414
Short name T620
Test name
Test status
Simulation time 941163659 ps
CPU time 13.74 seconds
Started Jun 05 05:21:23 PM PDT 24
Finished Jun 05 05:21:38 PM PDT 24
Peak memory 226016 kb
Host smart-61fa41c1-bfb8-48fb-9566-c3dc2530a785
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390352414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2390352414
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1455217792
Short name T322
Test name
Test status
Simulation time 2582592598 ps
CPU time 15.05 seconds
Started Jun 05 05:21:22 PM PDT 24
Finished Jun 05 05:21:38 PM PDT 24
Peak memory 217960 kb
Host smart-5e4975ed-3246-4fa6-84b0-a2cfb77c53ee
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455217792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1455217792
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.4128565833
Short name T708
Test name
Test status
Simulation time 1994450191 ps
CPU time 8.26 seconds
Started Jun 05 05:21:22 PM PDT 24
Finished Jun 05 05:21:31 PM PDT 24
Peak memory 224680 kb
Host smart-aaf43c33-3a85-4c65-9284-8e4956f53871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128565833 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.4128565833
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.3855879985
Short name T387
Test name
Test status
Simulation time 18477356 ps
CPU time 1.19 seconds
Started Jun 05 05:21:24 PM PDT 24
Finished Jun 05 05:21:26 PM PDT 24
Peak memory 213248 kb
Host smart-df516861-02a9-4414-ac5e-50e6f8e85358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855879985 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.3855879985
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.1806137170
Short name T350
Test name
Test status
Simulation time 997776171 ps
CPU time 24.73 seconds
Started Jun 05 05:21:23 PM PDT 24
Finished Jun 05 05:21:49 PM PDT 24
Peak memory 250988 kb
Host smart-d50a0fd1-9920-48d5-b193-36f08d42ff62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806137170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.1806137170
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.4044288168
Short name T341
Test name
Test status
Simulation time 87441604 ps
CPU time 6.04 seconds
Started Jun 05 05:21:21 PM PDT 24
Finished Jun 05 05:21:28 PM PDT 24
Peak memory 250516 kb
Host smart-2e04426e-186d-4506-a6c1-c8f5227b4d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044288168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.4044288168
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.3996649227
Short name T725
Test name
Test status
Simulation time 6294491765 ps
CPU time 143.21 seconds
Started Jun 05 05:21:24 PM PDT 24
Finished Jun 05 05:23:49 PM PDT 24
Peak memory 247980 kb
Host smart-a1caa2a2-636a-4476-b77a-3446bd629942
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996649227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.3996649227
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.1506664036
Short name T682
Test name
Test status
Simulation time 37351466 ps
CPU time 0.88 seconds
Started Jun 05 05:21:23 PM PDT 24
Finished Jun 05 05:21:25 PM PDT 24
Peak memory 211596 kb
Host smart-0dc19378-4755-4baa-abdc-32f4167f7149
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506664036 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.1506664036
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.1752302257
Short name T64
Test name
Test status
Simulation time 26015207 ps
CPU time 1.3 seconds
Started Jun 05 05:21:31 PM PDT 24
Finished Jun 05 05:21:33 PM PDT 24
Peak memory 208704 kb
Host smart-739c85b8-c82c-4fa5-9a8e-999520c9facc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752302257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.1752302257
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.2311408219
Short name T249
Test name
Test status
Simulation time 532333597 ps
CPU time 22.32 seconds
Started Jun 05 05:21:30 PM PDT 24
Finished Jun 05 05:21:53 PM PDT 24
Peak memory 218008 kb
Host smart-159bea60-7f8a-4227-8cea-959c900d0446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311408219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.2311408219
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.1266105615
Short name T675
Test name
Test status
Simulation time 2758622908 ps
CPU time 8.07 seconds
Started Jun 05 05:21:28 PM PDT 24
Finished Jun 05 05:21:37 PM PDT 24
Peak memory 217652 kb
Host smart-11948f12-49b7-4c23-ba7a-2fe0ddecfd48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266105615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.1266105615
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.381584160
Short name T676
Test name
Test status
Simulation time 85872353 ps
CPU time 3.54 seconds
Started Jun 05 05:21:31 PM PDT 24
Finished Jun 05 05:21:35 PM PDT 24
Peak memory 217976 kb
Host smart-9b64c79f-872a-418c-9024-00db89a72b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381584160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.381584160
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.3409688952
Short name T211
Test name
Test status
Simulation time 364274379 ps
CPU time 16.49 seconds
Started Jun 05 05:21:30 PM PDT 24
Finished Jun 05 05:21:47 PM PDT 24
Peak memory 218904 kb
Host smart-22ba64c6-bccb-44ab-8193-60edbbd7cb68
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409688952 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.3409688952
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.3101201256
Short name T855
Test name
Test status
Simulation time 200602136 ps
CPU time 9.24 seconds
Started Jun 05 05:21:27 PM PDT 24
Finished Jun 05 05:21:37 PM PDT 24
Peak memory 226028 kb
Host smart-ff6cf076-379e-4f94-bee0-f724135071dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101201256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_d
igest.3101201256
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.2614101412
Short name T686
Test name
Test status
Simulation time 4636474527 ps
CPU time 9 seconds
Started Jun 05 05:21:28 PM PDT 24
Finished Jun 05 05:21:38 PM PDT 24
Peak memory 217976 kb
Host smart-509478b2-54b9-405e-bf24-29cc01e66934
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614101412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
2614101412
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.1367660980
Short name T572
Test name
Test status
Simulation time 320278285 ps
CPU time 10.08 seconds
Started Jun 05 05:21:30 PM PDT 24
Finished Jun 05 05:21:41 PM PDT 24
Peak memory 224832 kb
Host smart-7d15f3ab-597c-4990-b52d-81a5ed8d5f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367660980 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.1367660980
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.4081352054
Short name T313
Test name
Test status
Simulation time 711562712 ps
CPU time 4.36 seconds
Started Jun 05 05:21:31 PM PDT 24
Finished Jun 05 05:21:36 PM PDT 24
Peak memory 217712 kb
Host smart-502d8313-a9a6-408a-8756-58a15d043d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081352054 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.4081352054
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.1003376102
Short name T813
Test name
Test status
Simulation time 559703931 ps
CPU time 32.83 seconds
Started Jun 05 05:21:32 PM PDT 24
Finished Jun 05 05:22:05 PM PDT 24
Peak memory 250884 kb
Host smart-418275e1-389c-4128-b0c7-8073252f49c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003376102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.1003376102
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.2420673133
Short name T277
Test name
Test status
Simulation time 208853037 ps
CPU time 8.11 seconds
Started Jun 05 05:21:31 PM PDT 24
Finished Jun 05 05:21:40 PM PDT 24
Peak memory 251048 kb
Host smart-8989bd3d-1d40-4e1d-be5f-750f13eeabeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420673133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.2420673133
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.1077272263
Short name T427
Test name
Test status
Simulation time 17663800452 ps
CPU time 177.62 seconds
Started Jun 05 05:21:32 PM PDT 24
Finished Jun 05 05:24:30 PM PDT 24
Peak memory 316472 kb
Host smart-546987c5-e71b-4ed5-bbc3-0f3f5504f55d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077272263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.1077272263
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.2669344989
Short name T435
Test name
Test status
Simulation time 13858046 ps
CPU time 1.02 seconds
Started Jun 05 05:21:32 PM PDT 24
Finished Jun 05 05:21:33 PM PDT 24
Peak memory 211428 kb
Host smart-f86d1b03-0679-4c75-b394-46310c2c2d9b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669344989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.2669344989
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.2565860201
Short name T597
Test name
Test status
Simulation time 58009208 ps
CPU time 0.91 seconds
Started Jun 05 05:21:38 PM PDT 24
Finished Jun 05 05:21:40 PM PDT 24
Peak memory 208492 kb
Host smart-2d92fea0-463c-4a05-a689-cb9c968fe77f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565860201 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.2565860201
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.883305763
Short name T645
Test name
Test status
Simulation time 268444840 ps
CPU time 8.24 seconds
Started Jun 05 05:21:30 PM PDT 24
Finished Jun 05 05:21:38 PM PDT 24
Peak memory 218012 kb
Host smart-e09b56d3-5809-4b6d-bcc9-90e561382bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883305763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.883305763
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.25180573
Short name T858
Test name
Test status
Simulation time 434712780 ps
CPU time 5.85 seconds
Started Jun 05 05:21:30 PM PDT 24
Finished Jun 05 05:21:36 PM PDT 24
Peak memory 209516 kb
Host smart-cddef97e-f9fb-430f-b6a9-65a0f7bc374b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25180573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.25180573
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.2213728868
Short name T299
Test name
Test status
Simulation time 575417807 ps
CPU time 2.27 seconds
Started Jun 05 05:21:29 PM PDT 24
Finished Jun 05 05:21:32 PM PDT 24
Peak memory 218080 kb
Host smart-a47f505a-e567-48ef-9515-50ae9082e955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213728868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.2213728868
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.3187748287
Short name T702
Test name
Test status
Simulation time 1259533712 ps
CPU time 10.37 seconds
Started Jun 05 05:21:29 PM PDT 24
Finished Jun 05 05:21:40 PM PDT 24
Peak memory 218936 kb
Host smart-53f51c02-05bf-4a12-a9c4-8a8f3a5f43a2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187748287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.3187748287
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.4063346310
Short name T601
Test name
Test status
Simulation time 400832490 ps
CPU time 10.28 seconds
Started Jun 05 05:21:38 PM PDT 24
Finished Jun 05 05:21:50 PM PDT 24
Peak memory 225872 kb
Host smart-47275cce-f2a0-400c-b123-1627f17b7379
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063346310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.4063346310
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.2866016907
Short name T616
Test name
Test status
Simulation time 616722224 ps
CPU time 10.54 seconds
Started Jun 05 05:21:29 PM PDT 24
Finished Jun 05 05:21:40 PM PDT 24
Peak memory 217932 kb
Host smart-bc5a519e-47e1-4621-ae2e-a6a5b4ba25eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866016907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
2866016907
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.2695669517
Short name T536
Test name
Test status
Simulation time 2947028904 ps
CPU time 9.8 seconds
Started Jun 05 05:21:32 PM PDT 24
Finished Jun 05 05:21:42 PM PDT 24
Peak memory 218228 kb
Host smart-84eaf393-8e02-4622-9509-06814ca51105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695669517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.2695669517
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.1670386835
Short name T739
Test name
Test status
Simulation time 142338086 ps
CPU time 1.28 seconds
Started Jun 05 05:21:28 PM PDT 24
Finished Jun 05 05:21:30 PM PDT 24
Peak memory 217720 kb
Host smart-86ebf2db-9a3b-417d-8372-f547f7d8edbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670386835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.1670386835
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.2932474766
Short name T539
Test name
Test status
Simulation time 517820164 ps
CPU time 25.57 seconds
Started Jun 05 05:21:32 PM PDT 24
Finished Jun 05 05:21:58 PM PDT 24
Peak memory 245592 kb
Host smart-bb55e6d7-4716-4414-8c8f-4282d1bef3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932474766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.2932474766
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.2675889637
Short name T102
Test name
Test status
Simulation time 253038132 ps
CPU time 7.39 seconds
Started Jun 05 05:21:29 PM PDT 24
Finished Jun 05 05:21:37 PM PDT 24
Peak memory 250900 kb
Host smart-86a1ee3a-d1e3-4c79-b370-74afa1bad2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675889637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.2675889637
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2901386259
Short name T733
Test name
Test status
Simulation time 27708515266 ps
CPU time 125.28 seconds
Started Jun 05 05:21:35 PM PDT 24
Finished Jun 05 05:23:41 PM PDT 24
Peak memory 268780 kb
Host smart-7b392894-ebfd-4583-836e-6a33157f6929
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901386259 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2901386259
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3675391588
Short name T646
Test name
Test status
Simulation time 15897061 ps
CPU time 1.14 seconds
Started Jun 05 05:21:30 PM PDT 24
Finished Jun 05 05:21:32 PM PDT 24
Peak memory 211540 kb
Host smart-f74bb3ce-9b3e-4f1c-a890-91d32fb13b87
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675391588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.3675391588
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.423019631
Short name T485
Test name
Test status
Simulation time 25915078 ps
CPU time 1.3 seconds
Started Jun 05 05:21:37 PM PDT 24
Finished Jun 05 05:21:40 PM PDT 24
Peak memory 209580 kb
Host smart-302e2439-d41d-4fb5-a329-70eb4e4c7d46
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423019631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.423019631
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.2921667366
Short name T192
Test name
Test status
Simulation time 1714620119 ps
CPU time 10.43 seconds
Started Jun 05 05:21:38 PM PDT 24
Finished Jun 05 05:21:49 PM PDT 24
Peak memory 217996 kb
Host smart-8269bb46-82f6-4329-b039-188d05fd2048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921667366 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.2921667366
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2549241770
Short name T21
Test name
Test status
Simulation time 2674555341 ps
CPU time 12.92 seconds
Started Jun 05 05:21:40 PM PDT 24
Finished Jun 05 05:21:53 PM PDT 24
Peak memory 209556 kb
Host smart-1cc0f91f-5c14-418f-8b54-91c0eac75fde
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549241770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2549241770
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.311460663
Short name T7
Test name
Test status
Simulation time 62421948 ps
CPU time 1.44 seconds
Started Jun 05 05:21:38 PM PDT 24
Finished Jun 05 05:21:41 PM PDT 24
Peak memory 218004 kb
Host smart-dce09c0c-d2e1-4145-b73f-62d812e276d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311460663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.311460663
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.100348106
Short name T528
Test name
Test status
Simulation time 347900834 ps
CPU time 17.34 seconds
Started Jun 05 05:21:38 PM PDT 24
Finished Jun 05 05:21:56 PM PDT 24
Peak memory 218944 kb
Host smart-96ee9dad-7899-44a6-bdcc-787840bc44b3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100348106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.100348106
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.3306140898
Short name T234
Test name
Test status
Simulation time 1363332668 ps
CPU time 12.48 seconds
Started Jun 05 05:21:39 PM PDT 24
Finished Jun 05 05:21:52 PM PDT 24
Peak memory 225744 kb
Host smart-83ec3f16-f1c1-439f-abaa-0ed5e040b775
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306140898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.3306140898
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.1890485220
Short name T840
Test name
Test status
Simulation time 2054869293 ps
CPU time 7.72 seconds
Started Jun 05 05:21:38 PM PDT 24
Finished Jun 05 05:21:47 PM PDT 24
Peak memory 217888 kb
Host smart-18ca679a-bbd5-4994-bf4e-7ec645743703
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890485220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
1890485220
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.3273150266
Short name T575
Test name
Test status
Simulation time 1399565579 ps
CPU time 12.79 seconds
Started Jun 05 05:21:37 PM PDT 24
Finished Jun 05 05:21:51 PM PDT 24
Peak memory 218092 kb
Host smart-027ae697-eadb-40f7-a884-e1992d9d7478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273150266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.3273150266
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.2591727752
Short name T256
Test name
Test status
Simulation time 62897045 ps
CPU time 2.4 seconds
Started Jun 05 05:21:39 PM PDT 24
Finished Jun 05 05:21:43 PM PDT 24
Peak memory 214148 kb
Host smart-d771e3a2-b7e6-463e-8659-2593852861ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591727752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.2591727752
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.1025876768
Short name T408
Test name
Test status
Simulation time 247562939 ps
CPU time 18.63 seconds
Started Jun 05 05:21:37 PM PDT 24
Finished Jun 05 05:21:56 PM PDT 24
Peak memory 250912 kb
Host smart-9a0ada9f-127c-462c-8f13-82c4a8449434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025876768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.1025876768
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.2038576613
Short name T67
Test name
Test status
Simulation time 539817178 ps
CPU time 7.16 seconds
Started Jun 05 05:21:37 PM PDT 24
Finished Jun 05 05:21:45 PM PDT 24
Peak memory 246764 kb
Host smart-9c5d2810-fd6a-4ec9-b981-ca4abbcb7ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038576613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.2038576613
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1078179401
Short name T358
Test name
Test status
Simulation time 32725083911 ps
CPU time 127.02 seconds
Started Jun 05 05:21:37 PM PDT 24
Finished Jun 05 05:23:45 PM PDT 24
Peak memory 271668 kb
Host smart-51a9f0a2-1b6a-4068-a0df-fce1dfc12b1e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078179401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1078179401
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.540442848
Short name T860
Test name
Test status
Simulation time 12273461 ps
CPU time 1.03 seconds
Started Jun 05 05:21:38 PM PDT 24
Finished Jun 05 05:21:40 PM PDT 24
Peak memory 211468 kb
Host smart-7aef7a0a-50aa-4de6-8c0d-046743a9f255
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540442848 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ct
rl_volatile_unlock_smoke.540442848
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.2782289236
Short name T727
Test name
Test status
Simulation time 22804656 ps
CPU time 1.12 seconds
Started Jun 05 05:19:32 PM PDT 24
Finished Jun 05 05:19:35 PM PDT 24
Peak memory 209564 kb
Host smart-182dd417-2d2e-4b3b-bf5c-04ae2db1372b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782289236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.2782289236
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.1218502724
Short name T186
Test name
Test status
Simulation time 13282418 ps
CPU time 0.88 seconds
Started Jun 05 05:19:39 PM PDT 24
Finished Jun 05 05:19:41 PM PDT 24
Peak memory 208508 kb
Host smart-b35ef670-2b36-4a6a-8825-82213f51d22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218502724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.1218502724
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.988743331
Short name T710
Test name
Test status
Simulation time 1219381066 ps
CPU time 19.08 seconds
Started Jun 05 05:19:33 PM PDT 24
Finished Jun 05 05:19:53 PM PDT 24
Peak memory 217964 kb
Host smart-3566b78c-3868-479e-9ed9-5691aa2ea657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988743331 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.988743331
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.1779537432
Short name T320
Test name
Test status
Simulation time 469440577 ps
CPU time 2.14 seconds
Started Jun 05 05:19:33 PM PDT 24
Finished Jun 05 05:19:36 PM PDT 24
Peak memory 209620 kb
Host smart-5997cc38-967c-4713-803b-4b335e53f8ca
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779537432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.1779537432
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.1814342077
Short name T679
Test name
Test status
Simulation time 3293549402 ps
CPU time 93.53 seconds
Started Jun 05 05:19:32 PM PDT 24
Finished Jun 05 05:21:06 PM PDT 24
Peak memory 218932 kb
Host smart-ec93542d-0a7f-4360-bfc2-001b1df55aeb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814342077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_er
rors.1814342077
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.1714933498
Short name T553
Test name
Test status
Simulation time 170697911 ps
CPU time 2.48 seconds
Started Jun 05 05:19:33 PM PDT 24
Finished Jun 05 05:19:36 PM PDT 24
Peak memory 217152 kb
Host smart-e78ccc26-0f52-4af1-8388-50681a15f84d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714933498 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.1
714933498
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.4104955216
Short name T659
Test name
Test status
Simulation time 1646236386 ps
CPU time 6.91 seconds
Started Jun 05 05:19:33 PM PDT 24
Finished Jun 05 05:19:41 PM PDT 24
Peak memory 217964 kb
Host smart-995d8e4c-f3b2-4093-a697-09e1cede11c8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104955216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.4104955216
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1249201855
Short name T498
Test name
Test status
Simulation time 753588824 ps
CPU time 10.28 seconds
Started Jun 05 05:19:37 PM PDT 24
Finished Jun 05 05:19:48 PM PDT 24
Peak memory 217672 kb
Host smart-ef35ff90-f6b9-4b0a-8ad1-cfed9c87ce18
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249201855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1249201855
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.3653162693
Short name T602
Test name
Test status
Simulation time 1671157961 ps
CPU time 6.41 seconds
Started Jun 05 05:19:35 PM PDT 24
Finished Jun 05 05:19:42 PM PDT 24
Peak memory 217636 kb
Host smart-1eb1ce4f-8db7-4c60-862e-8ed19afabf70
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653162693 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
3653162693
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.25677172
Short name T303
Test name
Test status
Simulation time 1081402311 ps
CPU time 40.4 seconds
Started Jun 05 05:19:34 PM PDT 24
Finished Jun 05 05:20:15 PM PDT 24
Peak memory 250912 kb
Host smart-ac1b302b-146d-47c4-adde-6997f129aae3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25677172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_
state_failure.25677172
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.4025170721
Short name T798
Test name
Test status
Simulation time 5957610749 ps
CPU time 11.81 seconds
Started Jun 05 05:19:39 PM PDT 24
Finished Jun 05 05:19:51 PM PDT 24
Peak memory 247248 kb
Host smart-97a8e635-43ab-4a71-9068-4b1553eeb52e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025170721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_state_post_trans.4025170721
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.1608268544
Short name T237
Test name
Test status
Simulation time 128335004 ps
CPU time 2.15 seconds
Started Jun 05 05:19:32 PM PDT 24
Finished Jun 05 05:19:35 PM PDT 24
Peak memory 218008 kb
Host smart-e0794697-348b-47de-9652-a6ba148509f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608268544 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.1608268544
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.1886312602
Short name T68
Test name
Test status
Simulation time 2089992283 ps
CPU time 13.14 seconds
Started Jun 05 05:19:37 PM PDT 24
Finished Jun 05 05:19:51 PM PDT 24
Peak memory 214336 kb
Host smart-2ce9e0bd-0d3b-4f14-bee3-d7266e25d75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886312602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.1886312602
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.328027506
Short name T43
Test name
Test status
Simulation time 124894070 ps
CPU time 22.21 seconds
Started Jun 05 05:19:38 PM PDT 24
Finished Jun 05 05:20:00 PM PDT 24
Peak memory 267648 kb
Host smart-223c7a4a-bd87-484d-b8b1-766c6aef1c70
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328027506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.328027506
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.1066426629
Short name T818
Test name
Test status
Simulation time 283114128 ps
CPU time 12.91 seconds
Started Jun 05 05:19:34 PM PDT 24
Finished Jun 05 05:19:48 PM PDT 24
Peak memory 217996 kb
Host smart-cd40a445-a48d-4eba-9789-9f0d9bcc7c48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066426629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.1066426629
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.2683489900
Short name T2
Test name
Test status
Simulation time 1270379988 ps
CPU time 12.75 seconds
Started Jun 05 05:19:34 PM PDT 24
Finished Jun 05 05:19:47 PM PDT 24
Peak memory 226040 kb
Host smart-c335847e-7293-4d2b-b1ed-5ead535d1ce4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683489900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.2683489900
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3668912872
Short name T504
Test name
Test status
Simulation time 997981575 ps
CPU time 8.6 seconds
Started Jun 05 05:19:33 PM PDT 24
Finished Jun 05 05:19:42 PM PDT 24
Peak memory 218000 kb
Host smart-9001e670-9aff-43bc-8289-4c06be0d90fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668912872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3
668912872
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.3594789491
Short name T39
Test name
Test status
Simulation time 1536484334 ps
CPU time 13.37 seconds
Started Jun 05 05:19:32 PM PDT 24
Finished Jun 05 05:19:46 PM PDT 24
Peak memory 218060 kb
Host smart-b49dcea7-7aaf-42d1-a574-b378a220ce2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594789491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.3594789491
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.2155027491
Short name T57
Test name
Test status
Simulation time 60793428 ps
CPU time 1.14 seconds
Started Jun 05 05:19:33 PM PDT 24
Finished Jun 05 05:19:35 PM PDT 24
Peak memory 217720 kb
Host smart-07a884a8-4aa2-4186-8a82-367315c01e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155027491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.2155027491
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.2161669823
Short name T98
Test name
Test status
Simulation time 715316318 ps
CPU time 31.79 seconds
Started Jun 05 05:19:39 PM PDT 24
Finished Jun 05 05:20:11 PM PDT 24
Peak memory 250928 kb
Host smart-c5679527-5875-4554-8f38-9c2132bb6210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161669823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.2161669823
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1730966455
Short name T632
Test name
Test status
Simulation time 145133031 ps
CPU time 8.04 seconds
Started Jun 05 05:19:33 PM PDT 24
Finished Jun 05 05:19:42 PM PDT 24
Peak memory 250916 kb
Host smart-ac7d4ef8-c727-4b6f-95e9-a5b5ed610280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730966455 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1730966455
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.2191577493
Short name T847
Test name
Test status
Simulation time 9402597418 ps
CPU time 199.13 seconds
Started Jun 05 05:19:34 PM PDT 24
Finished Jun 05 05:22:53 PM PDT 24
Peak memory 275540 kb
Host smart-4ea78435-52d8-4ab1-b440-11e633fd04b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191577493 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.2191577493
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3459228402
Short name T100
Test name
Test status
Simulation time 143261477127 ps
CPU time 1179.87 seconds
Started Jun 05 05:19:34 PM PDT 24
Finished Jun 05 05:39:14 PM PDT 24
Peak memory 414924 kb
Host smart-8cae79c9-ddac-432e-a43c-4dcdb6a820e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3459228402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_stress_all_with_rand_reset.3459228402
Directory /workspace/3.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.4278527953
Short name T737
Test name
Test status
Simulation time 35602554 ps
CPU time 0.95 seconds
Started Jun 05 05:19:32 PM PDT 24
Finished Jun 05 05:19:34 PM PDT 24
Peak memory 211508 kb
Host smart-8debcff0-5706-4546-a711-4e2aad2a67d2
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278527953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.4278527953
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.1530387927
Short name T191
Test name
Test status
Simulation time 20903742 ps
CPU time 1.27 seconds
Started Jun 05 05:21:46 PM PDT 24
Finished Jun 05 05:21:48 PM PDT 24
Peak memory 208692 kb
Host smart-418ec649-bb9b-4192-95d2-fcec25de8295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530387927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.1530387927
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.3126754958
Short name T269
Test name
Test status
Simulation time 227352106 ps
CPU time 9.09 seconds
Started Jun 05 05:21:39 PM PDT 24
Finished Jun 05 05:21:49 PM PDT 24
Peak memory 217960 kb
Host smart-8b2c9530-af02-460c-8432-7a25771c6f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126754958 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.3126754958
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.35463753
Short name T852
Test name
Test status
Simulation time 958148090 ps
CPU time 4.78 seconds
Started Jun 05 05:21:38 PM PDT 24
Finished Jun 05 05:21:43 PM PDT 24
Peak memory 216964 kb
Host smart-1da1ed47-de6a-4551-b3ef-b0e6ab4c3b6c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35463753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.35463753
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2607632644
Short name T442
Test name
Test status
Simulation time 242842464 ps
CPU time 2.69 seconds
Started Jun 05 05:21:36 PM PDT 24
Finished Jun 05 05:21:39 PM PDT 24
Peak memory 218016 kb
Host smart-97d7aef7-79b6-4f1e-9bfd-9361078ec0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607632644 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2607632644
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.2567289479
Short name T407
Test name
Test status
Simulation time 1577991898 ps
CPU time 16.39 seconds
Started Jun 05 05:21:37 PM PDT 24
Finished Jun 05 05:21:55 PM PDT 24
Peak memory 218944 kb
Host smart-e31d3ef0-dbcc-47d7-9e2f-5d1251bf0381
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567289479 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.2567289479
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1302822974
Short name T656
Test name
Test status
Simulation time 698522896 ps
CPU time 12.8 seconds
Started Jun 05 05:21:37 PM PDT 24
Finished Jun 05 05:21:51 PM PDT 24
Peak memory 225976 kb
Host smart-11ddfb8f-922c-4543-a2e2-2978a44806eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302822974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1302822974
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.1132240314
Short name T868
Test name
Test status
Simulation time 5145171106 ps
CPU time 11.23 seconds
Started Jun 05 05:21:40 PM PDT 24
Finished Jun 05 05:21:52 PM PDT 24
Peak memory 217944 kb
Host smart-ec1b4405-3fcc-4839-870d-e41607a27395
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132240314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
1132240314
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.456991914
Short name T642
Test name
Test status
Simulation time 1668726310 ps
CPU time 14.31 seconds
Started Jun 05 05:21:36 PM PDT 24
Finished Jun 05 05:21:51 PM PDT 24
Peak memory 226092 kb
Host smart-b190c34a-098c-4357-8979-1c0df5ee6320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456991914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.456991914
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.1243326413
Short name T644
Test name
Test status
Simulation time 107408230 ps
CPU time 2.82 seconds
Started Jun 05 05:21:37 PM PDT 24
Finished Jun 05 05:21:40 PM PDT 24
Peak memory 214500 kb
Host smart-aa122eec-f11e-479c-ad7d-63922e6d9c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243326413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.1243326413
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.976582991
Short name T582
Test name
Test status
Simulation time 204157563 ps
CPU time 26.89 seconds
Started Jun 05 05:21:36 PM PDT 24
Finished Jun 05 05:22:03 PM PDT 24
Peak memory 250916 kb
Host smart-217fe9c0-0f17-4f28-8227-19cfb2573cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976582991 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.976582991
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.3975959034
Short name T477
Test name
Test status
Simulation time 91167479 ps
CPU time 8.97 seconds
Started Jun 05 05:21:39 PM PDT 24
Finished Jun 05 05:21:49 PM PDT 24
Peak memory 250884 kb
Host smart-8674af49-df84-4213-94ce-493e434bbf9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975959034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.3975959034
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.3514739721
Short name T731
Test name
Test status
Simulation time 27150373275 ps
CPU time 235 seconds
Started Jun 05 05:21:44 PM PDT 24
Finished Jun 05 05:25:39 PM PDT 24
Peak memory 308572 kb
Host smart-d66fd5dc-b2cf-41c7-a84a-11c1c1d8f203
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514739721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.3514739721
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.3567129705
Short name T801
Test name
Test status
Simulation time 14511151 ps
CPU time 0.8 seconds
Started Jun 05 05:21:38 PM PDT 24
Finished Jun 05 05:21:39 PM PDT 24
Peak memory 207936 kb
Host smart-7a3cc848-1632-4b95-a280-aac0101db13f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567129705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_c
trl_volatile_unlock_smoke.3567129705
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.2345652753
Short name T267
Test name
Test status
Simulation time 74642251 ps
CPU time 0.95 seconds
Started Jun 05 05:21:43 PM PDT 24
Finished Jun 05 05:21:44 PM PDT 24
Peak memory 208652 kb
Host smart-a39e0a1b-e1df-4253-a1be-970f15a097e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345652753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.2345652753
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.2465222906
Short name T732
Test name
Test status
Simulation time 1082587620 ps
CPU time 15.53 seconds
Started Jun 05 05:21:43 PM PDT 24
Finished Jun 05 05:21:59 PM PDT 24
Peak memory 218064 kb
Host smart-723be5a4-9e37-4ff3-845f-ae0b86b9a4b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465222906 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.2465222906
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.2094793435
Short name T585
Test name
Test status
Simulation time 705838745 ps
CPU time 5.29 seconds
Started Jun 05 05:21:46 PM PDT 24
Finished Jun 05 05:21:52 PM PDT 24
Peak memory 209520 kb
Host smart-6ba1aac8-3b0b-4e31-8f08-fe99ee27fd7e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094793435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.2094793435
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3262516490
Short name T636
Test name
Test status
Simulation time 72105055 ps
CPU time 3.04 seconds
Started Jun 05 05:21:44 PM PDT 24
Finished Jun 05 05:21:48 PM PDT 24
Peak memory 218068 kb
Host smart-bcfaa6b5-957b-443a-bb35-ec20ae176e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262516490 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3262516490
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.425265212
Short name T432
Test name
Test status
Simulation time 778424979 ps
CPU time 8.62 seconds
Started Jun 05 05:21:44 PM PDT 24
Finished Jun 05 05:21:53 PM PDT 24
Peak memory 218116 kb
Host smart-3b46e39c-b990-48de-b03c-4c058b636a92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425265212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.425265212
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.19010337
Short name T253
Test name
Test status
Simulation time 551992982 ps
CPU time 12.94 seconds
Started Jun 05 05:21:45 PM PDT 24
Finished Jun 05 05:21:59 PM PDT 24
Peak memory 226028 kb
Host smart-c4f31ac7-5111-4331-ade0-74fe67b13cb8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19010337 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_dig
est.19010337
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.3525899160
Short name T657
Test name
Test status
Simulation time 1816841152 ps
CPU time 9.53 seconds
Started Jun 05 05:21:45 PM PDT 24
Finished Jun 05 05:21:56 PM PDT 24
Peak memory 217904 kb
Host smart-40bc5c0f-8427-4852-9192-9b090211b389
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525899160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.
3525899160
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.2109274013
Short name T634
Test name
Test status
Simulation time 1137555312 ps
CPU time 12.59 seconds
Started Jun 05 05:21:45 PM PDT 24
Finished Jun 05 05:21:58 PM PDT 24
Peak memory 225484 kb
Host smart-5afbf85e-5b33-4b16-8f99-6107c7c74f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109274013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.2109274013
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.758666973
Short name T265
Test name
Test status
Simulation time 112243226 ps
CPU time 2.02 seconds
Started Jun 05 05:21:43 PM PDT 24
Finished Jun 05 05:21:45 PM PDT 24
Peak memory 217696 kb
Host smart-08d6d9e8-68e6-4498-817b-0c362c709b0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758666973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.758666973
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.2702995586
Short name T846
Test name
Test status
Simulation time 959365654 ps
CPU time 31.62 seconds
Started Jun 05 05:21:46 PM PDT 24
Finished Jun 05 05:22:18 PM PDT 24
Peak memory 250928 kb
Host smart-c7db143c-5f6d-4a04-a5ff-21c4593c6656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702995586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.2702995586
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.4153391599
Short name T379
Test name
Test status
Simulation time 277104412 ps
CPU time 7.56 seconds
Started Jun 05 05:21:44 PM PDT 24
Finished Jun 05 05:21:52 PM PDT 24
Peak memory 250892 kb
Host smart-5830a624-7043-4fb0-8855-ad5810479dbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153391599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.4153391599
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.1853861763
Short name T264
Test name
Test status
Simulation time 35102220762 ps
CPU time 93.62 seconds
Started Jun 05 05:21:43 PM PDT 24
Finished Jun 05 05:23:17 PM PDT 24
Peak memory 252300 kb
Host smart-a3d23955-8735-4e67-99ae-e627a46d9b98
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853861763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.1853861763
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2722794900
Short name T638
Test name
Test status
Simulation time 34238680 ps
CPU time 1.01 seconds
Started Jun 05 05:21:47 PM PDT 24
Finished Jun 05 05:21:49 PM PDT 24
Peak memory 211520 kb
Host smart-d7f139d0-1b78-45fc-8bad-3d3449648859
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722794900 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2722794900
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.4008777234
Short name T223
Test name
Test status
Simulation time 31620457 ps
CPU time 1.08 seconds
Started Jun 05 05:21:44 PM PDT 24
Finished Jun 05 05:21:46 PM PDT 24
Peak memory 209564 kb
Host smart-456da0d7-28d2-4fcf-8226-228615c0e045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008777234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.4008777234
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.2115307052
Short name T591
Test name
Test status
Simulation time 744136235 ps
CPU time 9.95 seconds
Started Jun 05 05:21:44 PM PDT 24
Finished Jun 05 05:21:54 PM PDT 24
Peak memory 209516 kb
Host smart-59ad3bd0-4b65-40d0-b610-fa41eaf7a270
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115307052 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.2115307052
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.1751762204
Short name T367
Test name
Test status
Simulation time 100195908 ps
CPU time 2.04 seconds
Started Jun 05 05:21:45 PM PDT 24
Finished Jun 05 05:21:48 PM PDT 24
Peak memory 218008 kb
Host smart-e85c218a-9c9a-46c0-83b3-1921ee9e78b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751762204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.1751762204
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.3965270437
Short name T33
Test name
Test status
Simulation time 1705666935 ps
CPU time 17.86 seconds
Started Jun 05 05:21:44 PM PDT 24
Finished Jun 05 05:22:02 PM PDT 24
Peak memory 218944 kb
Host smart-568cccc1-b7e4-461d-8af5-9e4b1714641d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965270437 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.3965270437
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.4069920623
Short name T268
Test name
Test status
Simulation time 497071457 ps
CPU time 20.25 seconds
Started Jun 05 05:21:44 PM PDT 24
Finished Jun 05 05:22:05 PM PDT 24
Peak memory 226040 kb
Host smart-e12ca965-eef2-4555-a58b-f2fe3c5fc4d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069920623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.4069920623
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.564713120
Short name T542
Test name
Test status
Simulation time 361904982 ps
CPU time 9.44 seconds
Started Jun 05 05:21:44 PM PDT 24
Finished Jun 05 05:21:54 PM PDT 24
Peak memory 217932 kb
Host smart-c61d4281-7eee-4f55-8b12-c185715b1df6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564713120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.564713120
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.3264659607
Short name T609
Test name
Test status
Simulation time 181755720 ps
CPU time 2.37 seconds
Started Jun 05 05:21:45 PM PDT 24
Finished Jun 05 05:21:48 PM PDT 24
Peak memory 214152 kb
Host smart-5ed9c213-cd3f-4135-a3dc-330335b9089a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264659607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.3264659607
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.3302035532
Short name T397
Test name
Test status
Simulation time 535681635 ps
CPU time 29.95 seconds
Started Jun 05 05:21:46 PM PDT 24
Finished Jun 05 05:22:16 PM PDT 24
Peak memory 250920 kb
Host smart-d7dbdaa0-d09d-4b32-b88b-66888d9fb39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302035532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.3302035532
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.762414948
Short name T323
Test name
Test status
Simulation time 411522416 ps
CPU time 3 seconds
Started Jun 05 05:21:44 PM PDT 24
Finished Jun 05 05:21:48 PM PDT 24
Peak memory 217976 kb
Host smart-73a50cd2-96e2-4163-8fa3-b80d6763d85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762414948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.762414948
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.745675907
Short name T138
Test name
Test status
Simulation time 8782319763 ps
CPU time 73.56 seconds
Started Jun 05 05:21:46 PM PDT 24
Finished Jun 05 05:23:01 PM PDT 24
Peak memory 254424 kb
Host smart-6b33490e-41a8-41b0-a6d2-50b393265fe6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=745675907 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.745675907
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.2906364324
Short name T759
Test name
Test status
Simulation time 11011327 ps
CPU time 0.89 seconds
Started Jun 05 05:21:45 PM PDT 24
Finished Jun 05 05:21:47 PM PDT 24
Peak memory 211548 kb
Host smart-89abe477-132e-428e-aef5-cc2bed7d0c21
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906364324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_c
trl_volatile_unlock_smoke.2906364324
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.379678440
Short name T383
Test name
Test status
Simulation time 18683978 ps
CPU time 0.92 seconds
Started Jun 05 05:21:54 PM PDT 24
Finished Jun 05 05:21:55 PM PDT 24
Peak memory 209568 kb
Host smart-0995425a-bc53-401c-9c40-7c9b0d876fa7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379678440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.379678440
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.4196417675
Short name T436
Test name
Test status
Simulation time 926929892 ps
CPU time 12.81 seconds
Started Jun 05 05:21:54 PM PDT 24
Finished Jun 05 05:22:07 PM PDT 24
Peak memory 218008 kb
Host smart-6cede263-d027-47fa-85ac-e8e49b4d231c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196417675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.4196417675
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.440759960
Short name T310
Test name
Test status
Simulation time 9903483999 ps
CPU time 7.79 seconds
Started Jun 05 05:21:53 PM PDT 24
Finished Jun 05 05:22:02 PM PDT 24
Peak memory 209564 kb
Host smart-395d9e41-b078-4e80-bc6f-9fc043d16e59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440759960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.440759960
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.643496974
Short name T271
Test name
Test status
Simulation time 240417643 ps
CPU time 2.45 seconds
Started Jun 05 05:21:54 PM PDT 24
Finished Jun 05 05:21:57 PM PDT 24
Peak memory 218012 kb
Host smart-c155f089-3289-442b-a0d5-ced5f7a577e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643496974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.643496974
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2952833140
Short name T777
Test name
Test status
Simulation time 793844487 ps
CPU time 16.75 seconds
Started Jun 05 05:21:52 PM PDT 24
Finished Jun 05 05:22:09 PM PDT 24
Peak memory 226028 kb
Host smart-afdb4a70-075d-4a61-8ebb-59bc6bc7f3c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952833140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2952833140
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.3389312987
Short name T834
Test name
Test status
Simulation time 1186007834 ps
CPU time 11.68 seconds
Started Jun 05 05:21:51 PM PDT 24
Finished Jun 05 05:22:03 PM PDT 24
Peak memory 217920 kb
Host smart-be8b72ec-25db-4cab-8216-649fabf1f511
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389312987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
3389312987
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.1669756940
Short name T687
Test name
Test status
Simulation time 1094211542 ps
CPU time 7.68 seconds
Started Jun 05 05:21:51 PM PDT 24
Finished Jun 05 05:21:59 PM PDT 24
Peak memory 218092 kb
Host smart-34163884-f950-4894-930d-71dd025564fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669756940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.1669756940
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.3345791491
Short name T76
Test name
Test status
Simulation time 54052569 ps
CPU time 2.14 seconds
Started Jun 05 05:21:45 PM PDT 24
Finished Jun 05 05:21:48 PM PDT 24
Peak memory 213980 kb
Host smart-e8ff0549-ac39-479a-8bf6-4dbd671b345e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345791491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.3345791491
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.4167031524
Short name T78
Test name
Test status
Simulation time 385498450 ps
CPU time 27.04 seconds
Started Jun 05 05:21:52 PM PDT 24
Finished Jun 05 05:22:20 PM PDT 24
Peak memory 251000 kb
Host smart-1e96f1ad-fc07-40a5-a82d-af7486a7b1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167031524 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.4167031524
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.1085090022
Short name T618
Test name
Test status
Simulation time 323351754 ps
CPU time 8.32 seconds
Started Jun 05 05:21:53 PM PDT 24
Finished Jun 05 05:22:02 PM PDT 24
Peak memory 250920 kb
Host smart-4a0902d1-1782-4159-ba88-68cfe9199d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085090022 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.1085090022
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1292076399
Short name T792
Test name
Test status
Simulation time 74218864733 ps
CPU time 330.38 seconds
Started Jun 05 05:21:55 PM PDT 24
Finished Jun 05 05:27:26 PM PDT 24
Peak memory 267804 kb
Host smart-a15ae78a-c0be-4a68-b4db-bd58a4baca0d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292076399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1292076399
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.2385992171
Short name T700
Test name
Test status
Simulation time 27115321 ps
CPU time 0.98 seconds
Started Jun 05 05:21:48 PM PDT 24
Finished Jun 05 05:21:49 PM PDT 24
Peak memory 212692 kb
Host smart-aae4a638-d3d5-436b-b2c5-642d0c24bcef
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385992171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.2385992171
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.314970408
Short name T560
Test name
Test status
Simulation time 34183554 ps
CPU time 1.1 seconds
Started Jun 05 05:21:55 PM PDT 24
Finished Jun 05 05:21:56 PM PDT 24
Peak memory 209564 kb
Host smart-4801cb8a-3e09-4cae-88fd-e7cd5e5eab4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314970408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.314970408
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.361298811
Short name T406
Test name
Test status
Simulation time 776611626 ps
CPU time 10.71 seconds
Started Jun 05 05:21:54 PM PDT 24
Finished Jun 05 05:22:05 PM PDT 24
Peak memory 217992 kb
Host smart-4881cc26-0539-4b59-97a2-f56cb4454de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361298811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.361298811
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.4139480515
Short name T522
Test name
Test status
Simulation time 3191485679 ps
CPU time 6.62 seconds
Started Jun 05 05:21:54 PM PDT 24
Finished Jun 05 05:22:01 PM PDT 24
Peak memory 209580 kb
Host smart-c489beda-c586-40f3-8161-05714fdf0256
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139480515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.4139480515
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.1862032260
Short name T599
Test name
Test status
Simulation time 35638001 ps
CPU time 2.42 seconds
Started Jun 05 05:21:56 PM PDT 24
Finished Jun 05 05:21:59 PM PDT 24
Peak memory 218056 kb
Host smart-e5b8a065-ef75-4d36-9421-22b18b248c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862032260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.1862032260
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.2391703426
Short name T384
Test name
Test status
Simulation time 815615357 ps
CPU time 8.2 seconds
Started Jun 05 05:21:53 PM PDT 24
Finished Jun 05 05:22:02 PM PDT 24
Peak memory 218132 kb
Host smart-54fa413c-2e3c-4f11-9635-bd2f93ef35f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391703426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.2391703426
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.2120289745
Short name T850
Test name
Test status
Simulation time 4705662198 ps
CPU time 17.54 seconds
Started Jun 05 05:21:54 PM PDT 24
Finished Jun 05 05:22:12 PM PDT 24
Peak memory 226092 kb
Host smart-afc4a6a8-854b-4d1e-a884-3d939b3e80dd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120289745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_d
igest.2120289745
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.958399310
Short name T561
Test name
Test status
Simulation time 928668561 ps
CPU time 10.45 seconds
Started Jun 05 05:21:53 PM PDT 24
Finished Jun 05 05:22:04 PM PDT 24
Peak memory 217936 kb
Host smart-c3dc9a3b-e1d3-40e2-a003-045708ca9ed5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958399310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.958399310
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.2279236314
Short name T550
Test name
Test status
Simulation time 1192647993 ps
CPU time 7.83 seconds
Started Jun 05 05:21:53 PM PDT 24
Finished Jun 05 05:22:02 PM PDT 24
Peak memory 218028 kb
Host smart-b5c62ce8-fcdb-4530-8b3e-5f0872ffd846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279236314 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.2279236314
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.2834652511
Short name T869
Test name
Test status
Simulation time 85823905 ps
CPU time 5.14 seconds
Started Jun 05 05:21:53 PM PDT 24
Finished Jun 05 05:21:59 PM PDT 24
Peak memory 217664 kb
Host smart-bc9382ca-26c6-4e02-a86d-aa667daa863e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834652511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.2834652511
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2892292178
Short name T472
Test name
Test status
Simulation time 3767970333 ps
CPU time 25.08 seconds
Started Jun 05 05:21:53 PM PDT 24
Finished Jun 05 05:22:18 PM PDT 24
Peak memory 250944 kb
Host smart-8f067892-cd89-4702-a0fa-c9a3616dcdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892292178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2892292178
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.3858638804
Short name T843
Test name
Test status
Simulation time 355191206 ps
CPU time 6.23 seconds
Started Jun 05 05:21:53 PM PDT 24
Finished Jun 05 05:22:00 PM PDT 24
Peak memory 246244 kb
Host smart-5286222e-8cae-46f8-a8a6-7370c0c85bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858638804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.3858638804
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.1978125409
Short name T583
Test name
Test status
Simulation time 2837015541 ps
CPU time 129.59 seconds
Started Jun 05 05:21:55 PM PDT 24
Finished Jun 05 05:24:05 PM PDT 24
Peak memory 274156 kb
Host smart-7c65147c-9ca8-4baa-bfed-e25459c75cc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978125409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.1978125409
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.422025360
Short name T569
Test name
Test status
Simulation time 86980320 ps
CPU time 1.21 seconds
Started Jun 05 05:21:54 PM PDT 24
Finished Jun 05 05:21:56 PM PDT 24
Peak memory 212992 kb
Host smart-f374a98a-3a59-4db8-9ca7-40429c941528
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422025360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ct
rl_volatile_unlock_smoke.422025360
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.857203941
Short name T775
Test name
Test status
Simulation time 95849164 ps
CPU time 1.1 seconds
Started Jun 05 05:22:00 PM PDT 24
Finished Jun 05 05:22:01 PM PDT 24
Peak memory 208716 kb
Host smart-2595fe28-b5ce-4a1f-929c-cddd628e0ccb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857203941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.857203941
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.2741249758
Short name T441
Test name
Test status
Simulation time 3253232656 ps
CPU time 15.26 seconds
Started Jun 05 05:21:52 PM PDT 24
Finished Jun 05 05:22:08 PM PDT 24
Peak memory 217980 kb
Host smart-0cf313a3-a727-4f77-8427-b2aaddef1af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741249758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.2741249758
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.803051744
Short name T22
Test name
Test status
Simulation time 615016730 ps
CPU time 14.68 seconds
Started Jun 05 05:22:01 PM PDT 24
Finished Jun 05 05:22:17 PM PDT 24
Peak memory 217116 kb
Host smart-6d82d568-749c-4279-bd15-7a117a40e66f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803051744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.803051744
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.92147226
Short name T742
Test name
Test status
Simulation time 29082108 ps
CPU time 1.66 seconds
Started Jun 05 05:21:51 PM PDT 24
Finished Jun 05 05:21:53 PM PDT 24
Peak memory 218012 kb
Host smart-42af081d-42bc-4b4b-8b56-537a9f66bdc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92147226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.92147226
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.558171126
Short name T226
Test name
Test status
Simulation time 370965623 ps
CPU time 16.22 seconds
Started Jun 05 05:22:02 PM PDT 24
Finished Jun 05 05:22:19 PM PDT 24
Peak memory 218952 kb
Host smart-cfe32145-7bde-4143-8839-0beb28e54878
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558171126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.558171126
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.2449292940
Short name T206
Test name
Test status
Simulation time 700532022 ps
CPU time 9.9 seconds
Started Jun 05 05:22:01 PM PDT 24
Finished Jun 05 05:22:12 PM PDT 24
Peak memory 226028 kb
Host smart-d192169f-dcc9-496b-94b6-bf0a5f92b5f9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449292940 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.2449292940
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.1374099417
Short name T342
Test name
Test status
Simulation time 797107725 ps
CPU time 8.17 seconds
Started Jun 05 05:22:02 PM PDT 24
Finished Jun 05 05:22:11 PM PDT 24
Peak memory 217932 kb
Host smart-77cf3292-97c9-4120-a021-cdd5bf067ecd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374099417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
1374099417
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.1535108776
Short name T333
Test name
Test status
Simulation time 1244200877 ps
CPU time 12.45 seconds
Started Jun 05 05:22:00 PM PDT 24
Finished Jun 05 05:22:13 PM PDT 24
Peak memory 226076 kb
Host smart-069c6398-bc7f-409f-9e9b-d566e77f95b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535108776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.1535108776
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.764392912
Short name T665
Test name
Test status
Simulation time 23316959 ps
CPU time 1.59 seconds
Started Jun 05 05:21:54 PM PDT 24
Finished Jun 05 05:21:56 PM PDT 24
Peak memory 217712 kb
Host smart-e7a18df8-13fd-483b-823d-af999b00bffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764392912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.764392912
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.2924942329
Short name T703
Test name
Test status
Simulation time 1112114639 ps
CPU time 25.19 seconds
Started Jun 05 05:21:52 PM PDT 24
Finished Jun 05 05:22:18 PM PDT 24
Peak memory 250940 kb
Host smart-660dbba4-49a8-4361-a3b1-60a2ef8a1939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924942329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.2924942329
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.2836408345
Short name T842
Test name
Test status
Simulation time 203158905 ps
CPU time 7.24 seconds
Started Jun 05 05:21:53 PM PDT 24
Finished Jun 05 05:22:01 PM PDT 24
Peak memory 246852 kb
Host smart-79c054a4-ac79-4af9-9761-81d1de27b9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836408345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2836408345
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3128536430
Short name T418
Test name
Test status
Simulation time 7559116740 ps
CPU time 61.68 seconds
Started Jun 05 05:22:01 PM PDT 24
Finished Jun 05 05:23:04 PM PDT 24
Peak memory 276828 kb
Host smart-0eef6bf9-69f9-41b2-a943-3f844d603032
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128536430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3128536430
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3898649043
Short name T410
Test name
Test status
Simulation time 31775749 ps
CPU time 0.92 seconds
Started Jun 05 05:21:53 PM PDT 24
Finished Jun 05 05:21:54 PM PDT 24
Peak memory 211540 kb
Host smart-ada95901-4cdd-4764-87d2-a6b149306632
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898649043 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3898649043
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.3435595108
Short name T489
Test name
Test status
Simulation time 66705933 ps
CPU time 1.09 seconds
Started Jun 05 05:22:00 PM PDT 24
Finished Jun 05 05:22:02 PM PDT 24
Peak memory 209568 kb
Host smart-88277377-ce62-439c-abaa-df8b071dfeed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435595108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.3435595108
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.2592780735
Short name T677
Test name
Test status
Simulation time 275945697 ps
CPU time 13.39 seconds
Started Jun 05 05:22:03 PM PDT 24
Finished Jun 05 05:22:17 PM PDT 24
Peak memory 218076 kb
Host smart-9e945bc5-11e6-4323-b0bb-e4906d40e7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592780735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.2592780735
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.2878729365
Short name T193
Test name
Test status
Simulation time 219071750 ps
CPU time 3.22 seconds
Started Jun 05 05:22:00 PM PDT 24
Finished Jun 05 05:22:04 PM PDT 24
Peak memory 217984 kb
Host smart-8168a2da-7d4a-41aa-872f-8d4d14552698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878729365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.2878729365
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.1027973038
Short name T493
Test name
Test status
Simulation time 371789817 ps
CPU time 16.08 seconds
Started Jun 05 05:22:02 PM PDT 24
Finished Jun 05 05:22:19 PM PDT 24
Peak memory 218964 kb
Host smart-01adae70-4039-46c0-bcf3-fe5f89cb0747
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027973038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.1027973038
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2989429089
Short name T373
Test name
Test status
Simulation time 306208741 ps
CPU time 8.67 seconds
Started Jun 05 05:22:01 PM PDT 24
Finished Jun 05 05:22:11 PM PDT 24
Peak memory 217936 kb
Host smart-d9f7a563-225b-4235-afb4-6c5a997c2213
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989429089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2989429089
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.4037386261
Short name T831
Test name
Test status
Simulation time 1613185922 ps
CPU time 15.04 seconds
Started Jun 05 05:22:01 PM PDT 24
Finished Jun 05 05:22:17 PM PDT 24
Peak memory 218076 kb
Host smart-d4c1a04d-d190-4fe8-bdde-caa4193bcbbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037386261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.4037386261
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1127693461
Short name T497
Test name
Test status
Simulation time 97698747 ps
CPU time 3.03 seconds
Started Jun 05 05:22:00 PM PDT 24
Finished Jun 05 05:22:03 PM PDT 24
Peak memory 222632 kb
Host smart-2ef5b7e5-cd2e-4ec6-93c6-219f8c2d35d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127693461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1127693461
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.3821247850
Short name T378
Test name
Test status
Simulation time 176379172 ps
CPU time 19.65 seconds
Started Jun 05 05:22:00 PM PDT 24
Finished Jun 05 05:22:20 PM PDT 24
Peak memory 250940 kb
Host smart-b9047ce0-4273-4580-ae9f-54d0f32a413d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821247850 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.3821247850
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.3864499292
Short name T351
Test name
Test status
Simulation time 298662314 ps
CPU time 7.34 seconds
Started Jun 05 05:22:01 PM PDT 24
Finished Jun 05 05:22:09 PM PDT 24
Peak memory 250984 kb
Host smart-cbbec8aa-7c8f-40e9-ab93-5d1322bc6510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864499292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.3864499292
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.428395458
Short name T633
Test name
Test status
Simulation time 11418188200 ps
CPU time 85.54 seconds
Started Jun 05 05:22:03 PM PDT 24
Finished Jun 05 05:23:29 PM PDT 24
Peak memory 250952 kb
Host smart-bf7b50aa-a131-4c4c-b5a9-11d98b71115e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428395458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
36.lc_ctrl_stress_all.428395458
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.1609911316
Short name T578
Test name
Test status
Simulation time 13813264 ps
CPU time 1.03 seconds
Started Jun 05 05:22:00 PM PDT 24
Finished Jun 05 05:22:02 PM PDT 24
Peak memory 211448 kb
Host smart-965d327c-d8f2-41ef-b1c5-0553b0898360
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609911316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_c
trl_volatile_unlock_smoke.1609911316
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.3101800680
Short name T586
Test name
Test status
Simulation time 32203810 ps
CPU time 1.1 seconds
Started Jun 05 05:22:08 PM PDT 24
Finished Jun 05 05:22:10 PM PDT 24
Peak memory 208760 kb
Host smart-da8c2c3a-2a29-463d-b8f5-84557be0b751
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101800680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.3101800680
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.795431401
Short name T827
Test name
Test status
Simulation time 1483231354 ps
CPU time 14.82 seconds
Started Jun 05 05:22:01 PM PDT 24
Finished Jun 05 05:22:17 PM PDT 24
Peak memory 218068 kb
Host smart-53d9a17e-1959-4b28-87f7-1f86262838c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795431401 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.795431401
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.3156392676
Short name T405
Test name
Test status
Simulation time 1932230763 ps
CPU time 17.89 seconds
Started Jun 05 05:22:02 PM PDT 24
Finished Jun 05 05:22:21 PM PDT 24
Peak memory 209468 kb
Host smart-90285dc6-6152-43da-9fd0-944cabf97aa3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156392676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.3156392676
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.3472135967
Short name T362
Test name
Test status
Simulation time 38826187 ps
CPU time 1.88 seconds
Started Jun 05 05:22:05 PM PDT 24
Finished Jun 05 05:22:08 PM PDT 24
Peak memory 218072 kb
Host smart-fa4c33a5-affe-4942-b85b-b075a5853750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472135967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.3472135967
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.4207911058
Short name T680
Test name
Test status
Simulation time 1050856161 ps
CPU time 11.73 seconds
Started Jun 05 05:22:03 PM PDT 24
Finished Jun 05 05:22:15 PM PDT 24
Peak memory 218020 kb
Host smart-3545bb42-595d-460e-a94d-b90a3992dfb4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207911058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.4207911058
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.2371030385
Short name T764
Test name
Test status
Simulation time 759222082 ps
CPU time 9.44 seconds
Started Jun 05 05:22:06 PM PDT 24
Finished Jun 05 05:22:15 PM PDT 24
Peak memory 225576 kb
Host smart-b2a5623c-4b20-43a2-97bb-f839ca148641
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371030385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_d
igest.2371030385
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.2860183193
Short name T53
Test name
Test status
Simulation time 343826445 ps
CPU time 9.78 seconds
Started Jun 05 05:21:59 PM PDT 24
Finished Jun 05 05:22:10 PM PDT 24
Peak memory 217936 kb
Host smart-388e4767-280c-4d6c-8723-89e37e0b2253
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860183193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
2860183193
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.1797431730
Short name T490
Test name
Test status
Simulation time 718187301 ps
CPU time 8.58 seconds
Started Jun 05 05:22:01 PM PDT 24
Finished Jun 05 05:22:11 PM PDT 24
Peak memory 224572 kb
Host smart-6ac1f3ea-f917-4818-80b9-0c357cb214cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797431730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.1797431730
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.964563213
Short name T9
Test name
Test status
Simulation time 267533749 ps
CPU time 2.89 seconds
Started Jun 05 05:22:06 PM PDT 24
Finished Jun 05 05:22:09 PM PDT 24
Peak memory 214692 kb
Host smart-909071b8-1557-43ee-b108-229dfe5cc06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964563213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.964563213
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.3597345642
Short name T214
Test name
Test status
Simulation time 232641047 ps
CPU time 28.64 seconds
Started Jun 05 05:22:01 PM PDT 24
Finished Jun 05 05:22:30 PM PDT 24
Peak memory 250920 kb
Host smart-9df3073a-0f15-42af-a60a-b13b77ba641a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597345642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.3597345642
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.406702499
Short name T520
Test name
Test status
Simulation time 361969561 ps
CPU time 8.02 seconds
Started Jun 05 05:22:01 PM PDT 24
Finished Jun 05 05:22:10 PM PDT 24
Peak memory 243480 kb
Host smart-0b0f9399-b6bb-4cd8-8825-6a2f729bfbd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=406702499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.406702499
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.436573351
Short name T629
Test name
Test status
Simulation time 4194386779 ps
CPU time 121.19 seconds
Started Jun 05 05:22:08 PM PDT 24
Finished Jun 05 05:24:10 PM PDT 24
Peak memory 267552 kb
Host smart-684ca46f-9ec0-4568-b289-e1ac2ea50d7c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436573351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.436573351
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.723537767
Short name T692
Test name
Test status
Simulation time 11016287 ps
CPU time 1.06 seconds
Started Jun 05 05:22:00 PM PDT 24
Finished Jun 05 05:22:02 PM PDT 24
Peak memory 211560 kb
Host smart-b036a90b-a58e-4c2a-899e-c265ede26d41
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723537767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ct
rl_volatile_unlock_smoke.723537767
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.1488204136
Short name T396
Test name
Test status
Simulation time 38818360 ps
CPU time 1.01 seconds
Started Jun 05 05:22:12 PM PDT 24
Finished Jun 05 05:22:13 PM PDT 24
Peak memory 208748 kb
Host smart-12feb6c0-5ca1-4e85-a731-1919a598b5df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488204136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.1488204136
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.2583510552
Short name T826
Test name
Test status
Simulation time 3303183519 ps
CPU time 13.05 seconds
Started Jun 05 05:22:08 PM PDT 24
Finished Jun 05 05:22:22 PM PDT 24
Peak memory 218996 kb
Host smart-90356b34-0ded-4ac1-bbc1-f0238d70f2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583510552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.2583510552
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.4200173198
Short name T514
Test name
Test status
Simulation time 1470571714 ps
CPU time 6.16 seconds
Started Jun 05 05:22:05 PM PDT 24
Finished Jun 05 05:22:12 PM PDT 24
Peak memory 217252 kb
Host smart-96def179-5c43-4998-8c5d-b7355374222f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200173198 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.4200173198
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.1464118998
Short name T466
Test name
Test status
Simulation time 33470676 ps
CPU time 2.01 seconds
Started Jun 05 05:22:07 PM PDT 24
Finished Jun 05 05:22:10 PM PDT 24
Peak memory 218024 kb
Host smart-646c57b0-45ed-4d57-9138-d1b3efb72e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464118998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.1464118998
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.3215127892
Short name T467
Test name
Test status
Simulation time 200708719 ps
CPU time 11.08 seconds
Started Jun 05 05:22:13 PM PDT 24
Finished Jun 05 05:22:24 PM PDT 24
Peak memory 217992 kb
Host smart-21e94d96-9dfd-402a-a6b0-32ac383ac081
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215127892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.3215127892
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.1643158590
Short name T794
Test name
Test status
Simulation time 2516009724 ps
CPU time 14.33 seconds
Started Jun 05 05:22:08 PM PDT 24
Finished Jun 05 05:22:23 PM PDT 24
Peak memory 226028 kb
Host smart-368b797a-7346-4458-8b4b-3125ae2097eb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643158590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.1643158590
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.876944755
Short name T628
Test name
Test status
Simulation time 354263399 ps
CPU time 6.59 seconds
Started Jun 05 05:22:09 PM PDT 24
Finished Jun 05 05:22:16 PM PDT 24
Peak memory 217944 kb
Host smart-5edfdc79-934e-4b85-9b4c-b8106ad57bce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876944755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.876944755
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.821206072
Short name T647
Test name
Test status
Simulation time 497536847 ps
CPU time 11.25 seconds
Started Jun 05 05:22:08 PM PDT 24
Finished Jun 05 05:22:19 PM PDT 24
Peak memory 225316 kb
Host smart-bca4696c-d075-4700-8fec-996c4a996eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821206072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.821206072
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.3498504752
Short name T56
Test name
Test status
Simulation time 36565629 ps
CPU time 2.52 seconds
Started Jun 05 05:22:07 PM PDT 24
Finished Jun 05 05:22:10 PM PDT 24
Peak memory 214528 kb
Host smart-f23e8752-fe00-4796-99c3-25ffaa8d3396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498504752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.3498504752
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.2982415599
Short name T96
Test name
Test status
Simulation time 301982896 ps
CPU time 22.12 seconds
Started Jun 05 05:22:07 PM PDT 24
Finished Jun 05 05:22:29 PM PDT 24
Peak memory 250924 kb
Host smart-ce68bff6-be9d-4a12-8b7c-6d2a576018e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982415599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.2982415599
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.3162662434
Short name T79
Test name
Test status
Simulation time 95977433 ps
CPU time 6.71 seconds
Started Jun 05 05:22:06 PM PDT 24
Finished Jun 05 05:22:13 PM PDT 24
Peak memory 246696 kb
Host smart-08720259-26d7-43ff-a5f2-35391c3a33c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162662434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.3162662434
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.2689679293
Short name T800
Test name
Test status
Simulation time 8404984347 ps
CPU time 93.71 seconds
Started Jun 05 05:22:08 PM PDT 24
Finished Jun 05 05:23:42 PM PDT 24
Peak memory 267352 kb
Host smart-c67aedee-f771-4346-ac78-7694b1769702
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689679293 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.2689679293
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.1997692419
Short name T302
Test name
Test status
Simulation time 26272719 ps
CPU time 1.16 seconds
Started Jun 05 05:22:08 PM PDT 24
Finished Jun 05 05:22:10 PM PDT 24
Peak memory 212828 kb
Host smart-af68caf9-1ada-4a7d-9e2c-3ab5a9e5ba57
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997692419 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.1997692419
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.3469795994
Short name T782
Test name
Test status
Simulation time 65675753 ps
CPU time 0.86 seconds
Started Jun 05 05:22:15 PM PDT 24
Finished Jun 05 05:22:16 PM PDT 24
Peak memory 208664 kb
Host smart-c4904296-e960-49d9-9c34-6217bbe435f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469795994 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.3469795994
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.4093730587
Short name T295
Test name
Test status
Simulation time 1789761699 ps
CPU time 16.43 seconds
Started Jun 05 05:22:08 PM PDT 24
Finished Jun 05 05:22:25 PM PDT 24
Peak memory 218004 kb
Host smart-66e2be64-8d8a-4da0-97f2-5f8702035493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093730587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.4093730587
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3419123155
Short name T306
Test name
Test status
Simulation time 1959272515 ps
CPU time 6.2 seconds
Started Jun 05 05:22:08 PM PDT 24
Finished Jun 05 05:22:15 PM PDT 24
Peak memory 217088 kb
Host smart-3757f48f-729c-4d1e-b9a4-87ce1b7c5466
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419123155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3419123155
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1514829702
Short name T793
Test name
Test status
Simulation time 60786859 ps
CPU time 2.04 seconds
Started Jun 05 05:22:08 PM PDT 24
Finished Jun 05 05:22:11 PM PDT 24
Peak memory 218032 kb
Host smart-74230720-3166-406f-af75-6001ec37212f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514829702 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1514829702
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.2667161554
Short name T474
Test name
Test status
Simulation time 3832210804 ps
CPU time 23.08 seconds
Started Jun 05 05:22:06 PM PDT 24
Finished Jun 05 05:22:30 PM PDT 24
Peak memory 220028 kb
Host smart-ece14601-6ff2-41de-9f5d-32d18489318c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667161554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.2667161554
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.434153617
Short name T808
Test name
Test status
Simulation time 271748142 ps
CPU time 9.1 seconds
Started Jun 05 05:22:09 PM PDT 24
Finished Jun 05 05:22:18 PM PDT 24
Peak memory 226016 kb
Host smart-f0d79bfe-69a5-4e5f-acd7-4c64f7ae0eed
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434153617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_di
gest.434153617
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.3907487615
Short name T605
Test name
Test status
Simulation time 3780755295 ps
CPU time 12.96 seconds
Started Jun 05 05:22:08 PM PDT 24
Finished Jun 05 05:22:22 PM PDT 24
Peak memory 218040 kb
Host smart-7729a612-465b-48c2-8748-f026165a0d11
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907487615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.
3907487615
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3140039058
Short name T778
Test name
Test status
Simulation time 362526050 ps
CPU time 8.57 seconds
Started Jun 05 05:22:08 PM PDT 24
Finished Jun 05 05:22:17 PM PDT 24
Peak memory 218060 kb
Host smart-285b7bee-ce2f-4dc6-9d99-5d3039ee2872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140039058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3140039058
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.1881816796
Short name T693
Test name
Test status
Simulation time 59542511 ps
CPU time 3.75 seconds
Started Jun 05 05:22:08 PM PDT 24
Finished Jun 05 05:22:13 PM PDT 24
Peak memory 214940 kb
Host smart-a2860667-0e81-412e-8b3c-0b7c10386ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881816796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.1881816796
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.3306049755
Short name T328
Test name
Test status
Simulation time 1850440831 ps
CPU time 21.09 seconds
Started Jun 05 05:22:07 PM PDT 24
Finished Jun 05 05:22:29 PM PDT 24
Peak memory 250908 kb
Host smart-0fc253e1-8ec7-41f7-8a6c-267e463a2557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306049755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.3306049755
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.672744042
Short name T447
Test name
Test status
Simulation time 163682924 ps
CPU time 7.53 seconds
Started Jun 05 05:22:07 PM PDT 24
Finished Jun 05 05:22:15 PM PDT 24
Peak memory 250896 kb
Host smart-d0317572-353b-4ee4-8334-209a6cb84e00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672744042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.672744042
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.272608827
Short name T815
Test name
Test status
Simulation time 39556183958 ps
CPU time 107.35 seconds
Started Jun 05 05:22:08 PM PDT 24
Finished Jun 05 05:23:56 PM PDT 24
Peak memory 250968 kb
Host smart-553eda86-4486-4554-a6ed-df899698024b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272608827 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.272608827
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1525141272
Short name T371
Test name
Test status
Simulation time 42203042 ps
CPU time 0.74 seconds
Started Jun 05 05:22:06 PM PDT 24
Finished Jun 05 05:22:07 PM PDT 24
Peak memory 206772 kb
Host smart-198b2cbb-237e-49b7-b3e1-56df7b00a8df
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525141272 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1525141272
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.3419407957
Short name T468
Test name
Test status
Simulation time 58594351 ps
CPU time 0.91 seconds
Started Jun 05 05:19:43 PM PDT 24
Finished Jun 05 05:19:45 PM PDT 24
Peak memory 208736 kb
Host smart-f67366a4-976a-450e-8e65-8829287298b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419407957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.3419407957
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.731524074
Short name T689
Test name
Test status
Simulation time 594498433 ps
CPU time 15.37 seconds
Started Jun 05 05:19:49 PM PDT 24
Finished Jun 05 05:20:05 PM PDT 24
Peak memory 217992 kb
Host smart-718af923-c9d4-48aa-bb8f-909f29156f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731524074 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.731524074
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.3496396334
Short name T515
Test name
Test status
Simulation time 1169866465 ps
CPU time 9.48 seconds
Started Jun 05 05:19:42 PM PDT 24
Finished Jun 05 05:19:52 PM PDT 24
Peak memory 217208 kb
Host smart-ca4284e6-6e4c-4b32-ad7c-759d47b21698
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496396334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.3496396334
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.4079444109
Short name T370
Test name
Test status
Simulation time 1302259906 ps
CPU time 27.23 seconds
Started Jun 05 05:19:43 PM PDT 24
Finished Jun 05 05:20:11 PM PDT 24
Peak memory 218000 kb
Host smart-0592ea55-d105-4837-9558-186ebbf00c0c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079444109 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_er
rors.4079444109
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.1266457819
Short name T307
Test name
Test status
Simulation time 772249677 ps
CPU time 3.82 seconds
Started Jun 05 05:19:41 PM PDT 24
Finished Jun 05 05:19:46 PM PDT 24
Peak memory 217180 kb
Host smart-ad74d7b1-5118-43bc-8caa-699d1cdce013
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266457819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.1
266457819
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.3067594121
Short name T423
Test name
Test status
Simulation time 706987243 ps
CPU time 11.16 seconds
Started Jun 05 05:19:42 PM PDT 24
Finished Jun 05 05:19:53 PM PDT 24
Peak memory 217916 kb
Host smart-b779125c-85a0-4283-a877-5d4ef4bb4585
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067594121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.3067594121
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3553222307
Short name T462
Test name
Test status
Simulation time 2563003526 ps
CPU time 19.36 seconds
Started Jun 05 05:19:42 PM PDT 24
Finished Jun 05 05:20:02 PM PDT 24
Peak memory 217692 kb
Host smart-ad886098-a26b-4bdc-a8e1-7c7b6df0aa51
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553222307 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_regwen_during_op.3553222307
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3387643301
Short name T69
Test name
Test status
Simulation time 573356272 ps
CPU time 3.96 seconds
Started Jun 05 05:19:44 PM PDT 24
Finished Jun 05 05:19:48 PM PDT 24
Peak memory 217644 kb
Host smart-f7c41b8b-b726-47a7-ac69-1540f448befd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387643301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3387643301
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.2206948093
Short name T336
Test name
Test status
Simulation time 1353527252 ps
CPU time 48.53 seconds
Started Jun 05 05:19:48 PM PDT 24
Finished Jun 05 05:20:37 PM PDT 24
Peak memory 267228 kb
Host smart-537c6689-cd3c-4225-a957-e2f66b44d16c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206948093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.2206948093
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.1110059801
Short name T557
Test name
Test status
Simulation time 1387118137 ps
CPU time 10.26 seconds
Started Jun 05 05:19:43 PM PDT 24
Finished Jun 05 05:19:54 PM PDT 24
Peak memory 245688 kb
Host smart-d2d2c566-d603-469b-beab-385eda995898
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110059801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
jtag_state_post_trans.1110059801
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.2899005845
Short name T297
Test name
Test status
Simulation time 284096470 ps
CPU time 3.58 seconds
Started Jun 05 05:19:41 PM PDT 24
Finished Jun 05 05:19:45 PM PDT 24
Peak memory 218088 kb
Host smart-afa57a75-01e6-478e-a14e-a2f5754064f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899005845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.2899005845
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.2513908801
Short name T332
Test name
Test status
Simulation time 254597658 ps
CPU time 5.93 seconds
Started Jun 05 05:19:43 PM PDT 24
Finished Jun 05 05:19:50 PM PDT 24
Peak memory 217716 kb
Host smart-a90255c6-d454-44aa-82a5-f85aee0261d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513908801 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.2513908801
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.1066172474
Short name T93
Test name
Test status
Simulation time 486581708 ps
CPU time 24.83 seconds
Started Jun 05 05:19:42 PM PDT 24
Finished Jun 05 05:20:08 PM PDT 24
Peak memory 269300 kb
Host smart-0342f98c-606d-4ff3-8b54-a669a252b7ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066172474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.1066172474
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.1359620554
Short name T376
Test name
Test status
Simulation time 1340964037 ps
CPU time 17.16 seconds
Started Jun 05 05:19:42 PM PDT 24
Finished Jun 05 05:20:00 PM PDT 24
Peak memory 218944 kb
Host smart-98f8f586-ee7b-45d7-b70e-9fc8137f060e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359620554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.1359620554
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1042514579
Short name T381
Test name
Test status
Simulation time 1831819734 ps
CPU time 11.73 seconds
Started Jun 05 05:19:48 PM PDT 24
Finished Jun 05 05:20:00 PM PDT 24
Peak memory 226020 kb
Host smart-ad67a1ed-d0d0-4224-a4e3-87ab41770298
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042514579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1042514579
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.11192120
Short name T392
Test name
Test status
Simulation time 4186761773 ps
CPU time 10.25 seconds
Started Jun 05 05:19:41 PM PDT 24
Finished Jun 05 05:19:51 PM PDT 24
Peak memory 218052 kb
Host smart-685bea56-45d0-474e-9747-4cb838175440
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11192120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.11192120
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.3188166312
Short name T430
Test name
Test status
Simulation time 578425362 ps
CPU time 11.05 seconds
Started Jun 05 05:19:42 PM PDT 24
Finished Jun 05 05:19:54 PM PDT 24
Peak memory 224860 kb
Host smart-f51aece5-6181-48df-9ade-39c2a84ceef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188166312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.3188166312
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.979478461
Short name T340
Test name
Test status
Simulation time 47068346 ps
CPU time 2.11 seconds
Started Jun 05 05:19:33 PM PDT 24
Finished Jun 05 05:19:36 PM PDT 24
Peak memory 217712 kb
Host smart-63284af6-d13a-442c-995d-a76ce1a3d633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979478461 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.979478461
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.348171705
Short name T512
Test name
Test status
Simulation time 474044409 ps
CPU time 14.96 seconds
Started Jun 05 05:19:36 PM PDT 24
Finished Jun 05 05:19:51 PM PDT 24
Peak memory 250912 kb
Host smart-d9aa1dad-02e0-4d97-8580-a33d3bdfd60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348171705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.348171705
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1335836453
Short name T791
Test name
Test status
Simulation time 269154676 ps
CPU time 6.82 seconds
Started Jun 05 05:19:35 PM PDT 24
Finished Jun 05 05:19:42 PM PDT 24
Peak memory 246244 kb
Host smart-7921cd1d-3684-423b-a1b3-350babc0167a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335836453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1335836453
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.658464582
Short name T158
Test name
Test status
Simulation time 2203342043 ps
CPU time 64.72 seconds
Started Jun 05 05:19:43 PM PDT 24
Finished Jun 05 05:20:49 PM PDT 24
Peak memory 250972 kb
Host smart-f087b578-0fdf-4426-97f9-f8e237368602
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658464582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.658464582
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3648116859
Short name T524
Test name
Test status
Simulation time 12247769 ps
CPU time 0.89 seconds
Started Jun 05 05:19:34 PM PDT 24
Finished Jun 05 05:19:35 PM PDT 24
Peak memory 211532 kb
Host smart-084d5438-739a-480d-9015-d1ad9565fb4d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648116859 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.3648116859
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.3874692438
Short name T291
Test name
Test status
Simulation time 118690749 ps
CPU time 0.9 seconds
Started Jun 05 05:22:18 PM PDT 24
Finished Jun 05 05:22:19 PM PDT 24
Peak memory 208696 kb
Host smart-edfdf78d-73de-4de3-b4ae-ab7249080c6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874692438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.3874692438
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.2441957306
Short name T400
Test name
Test status
Simulation time 660213596 ps
CPU time 10.98 seconds
Started Jun 05 05:22:16 PM PDT 24
Finished Jun 05 05:22:28 PM PDT 24
Peak memory 218044 kb
Host smart-85861db9-76b5-4299-993e-83740b19de72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441957306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.2441957306
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.3975045834
Short name T449
Test name
Test status
Simulation time 1494064048 ps
CPU time 3.75 seconds
Started Jun 05 05:22:16 PM PDT 24
Finished Jun 05 05:22:20 PM PDT 24
Peak memory 209480 kb
Host smart-a3b7ac02-d85b-47b0-9edf-1438945b8e76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975045834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.3975045834
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.1515932816
Short name T595
Test name
Test status
Simulation time 60153331 ps
CPU time 3.42 seconds
Started Jun 05 05:22:17 PM PDT 24
Finished Jun 05 05:22:21 PM PDT 24
Peak memory 218080 kb
Host smart-fceee5c0-0b27-4c18-9874-5fc162b028a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515932816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.1515932816
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.1999184680
Short name T250
Test name
Test status
Simulation time 431719373 ps
CPU time 18.35 seconds
Started Jun 05 05:22:16 PM PDT 24
Finished Jun 05 05:22:34 PM PDT 24
Peak memory 218948 kb
Host smart-9ccf5ecc-6cc4-456b-978d-4a428fbccac7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999184680 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.1999184680
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.1962445764
Short name T728
Test name
Test status
Simulation time 561675078 ps
CPU time 8.45 seconds
Started Jun 05 05:22:15 PM PDT 24
Finished Jun 05 05:22:24 PM PDT 24
Peak memory 225984 kb
Host smart-1f685b34-e2f6-47cc-b1b4-2556ceeabbbd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962445764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.1962445764
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2939273450
Short name T698
Test name
Test status
Simulation time 1216117059 ps
CPU time 11.69 seconds
Started Jun 05 05:22:18 PM PDT 24
Finished Jun 05 05:22:30 PM PDT 24
Peak memory 217932 kb
Host smart-20b1902c-07aa-4717-ad50-74d0182ecf21
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939273450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
2939273450
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3162043614
Short name T190
Test name
Test status
Simulation time 179707491 ps
CPU time 8.01 seconds
Started Jun 05 05:22:15 PM PDT 24
Finished Jun 05 05:22:24 PM PDT 24
Peak memory 224668 kb
Host smart-d63c9042-59bf-4058-9439-9966b692fd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162043614 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3162043614
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.2515010231
Short name T836
Test name
Test status
Simulation time 22129472 ps
CPU time 1.57 seconds
Started Jun 05 05:22:16 PM PDT 24
Finished Jun 05 05:22:18 PM PDT 24
Peak memory 217736 kb
Host smart-94e7c917-2a90-4f4c-abe0-9ed10bab756d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515010231 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.2515010231
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.280753551
Short name T304
Test name
Test status
Simulation time 211194495 ps
CPU time 26.22 seconds
Started Jun 05 05:22:16 PM PDT 24
Finished Jun 05 05:22:43 PM PDT 24
Peak memory 250980 kb
Host smart-308e5a10-eb07-4ffc-8245-a6b90ef6705b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280753551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.280753551
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.1477134456
Short name T278
Test name
Test status
Simulation time 113857796 ps
CPU time 6.96 seconds
Started Jun 05 05:22:16 PM PDT 24
Finished Jun 05 05:22:24 PM PDT 24
Peak memory 250476 kb
Host smart-f108a3b7-3ce3-416b-82e4-0bd3c8310567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477134456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.1477134456
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.1140031783
Short name T851
Test name
Test status
Simulation time 20329098425 ps
CPU time 336.04 seconds
Started Jun 05 05:22:17 PM PDT 24
Finished Jun 05 05:27:53 PM PDT 24
Peak memory 272284 kb
Host smart-fed38001-ad10-4755-b586-9191a969e4fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140031783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.1140031783
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.87744847
Short name T658
Test name
Test status
Simulation time 25602876779 ps
CPU time 311.25 seconds
Started Jun 05 05:22:15 PM PDT 24
Finished Jun 05 05:27:27 PM PDT 24
Peak memory 496780 kb
Host smart-44d5ec64-7614-492a-8183-54c15652480b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=87744847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.87744847
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.68762684
Short name T389
Test name
Test status
Simulation time 34634178 ps
CPU time 0.94 seconds
Started Jun 05 05:22:15 PM PDT 24
Finished Jun 05 05:22:16 PM PDT 24
Peak memory 211584 kb
Host smart-be15363b-59ea-4def-9891-0c11646c0940
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68762684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctr
l_volatile_unlock_smoke.68762684
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.2024946290
Short name T343
Test name
Test status
Simulation time 97384914 ps
CPU time 0.93 seconds
Started Jun 05 05:22:28 PM PDT 24
Finished Jun 05 05:22:29 PM PDT 24
Peak memory 208712 kb
Host smart-02499baf-9420-4c7a-be4f-e83b179ecd3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024946290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.2024946290
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.3803269556
Short name T648
Test name
Test status
Simulation time 582541338 ps
CPU time 15.32 seconds
Started Jun 05 05:22:15 PM PDT 24
Finished Jun 05 05:22:31 PM PDT 24
Peak memory 217996 kb
Host smart-47485e00-dd22-4c1a-9057-5d49b43bf074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803269556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.3803269556
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1430932939
Short name T160
Test name
Test status
Simulation time 5220554796 ps
CPU time 7.78 seconds
Started Jun 05 05:22:16 PM PDT 24
Finished Jun 05 05:22:25 PM PDT 24
Peak memory 217716 kb
Host smart-31987d1c-b314-4646-b2d7-257e0ad74dc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430932939 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1430932939
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.4066434903
Short name T621
Test name
Test status
Simulation time 149410527 ps
CPU time 1.87 seconds
Started Jun 05 05:22:17 PM PDT 24
Finished Jun 05 05:22:20 PM PDT 24
Peak memory 218076 kb
Host smart-c7aa55fe-befc-4aa2-9e2a-2f98a2164b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066434903 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.4066434903
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.1410696280
Short name T476
Test name
Test status
Simulation time 1866311842 ps
CPU time 28.87 seconds
Started Jun 05 05:22:18 PM PDT 24
Finished Jun 05 05:22:48 PM PDT 24
Peak memory 218956 kb
Host smart-11bac8d9-6ee9-4856-848f-003ddab6b4e7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410696280 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.1410696280
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.1483590051
Short name T345
Test name
Test status
Simulation time 288644324 ps
CPU time 12.29 seconds
Started Jun 05 05:22:16 PM PDT 24
Finished Jun 05 05:22:28 PM PDT 24
Peak memory 226044 kb
Host smart-6c5edb1d-6b6b-47bb-8ae9-51118053a7cc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483590051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.1483590051
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.4165521587
Short name T673
Test name
Test status
Simulation time 1493231610 ps
CPU time 9.96 seconds
Started Jun 05 05:22:16 PM PDT 24
Finished Jun 05 05:22:27 PM PDT 24
Peak memory 217984 kb
Host smart-4cabb60e-ed6e-4d68-9da2-f65e48497596
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165521587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.
4165521587
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.846326780
Short name T670
Test name
Test status
Simulation time 373667098 ps
CPU time 11.37 seconds
Started Jun 05 05:22:17 PM PDT 24
Finished Jun 05 05:22:29 PM PDT 24
Peak memory 224928 kb
Host smart-e35432b7-011d-4ef5-9f9a-4c9e8a36c87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846326780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.846326780
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2338831908
Short name T532
Test name
Test status
Simulation time 25982776 ps
CPU time 1.85 seconds
Started Jun 05 05:22:18 PM PDT 24
Finished Jun 05 05:22:21 PM PDT 24
Peak memory 217704 kb
Host smart-11dd21f8-03f8-48b5-a274-6ab76d297240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338831908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2338831908
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.819136589
Short name T195
Test name
Test status
Simulation time 230735238 ps
CPU time 20.2 seconds
Started Jun 05 05:22:14 PM PDT 24
Finished Jun 05 05:22:35 PM PDT 24
Peak memory 250936 kb
Host smart-43f30591-b0c5-4213-a32f-0a80a318bf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819136589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.819136589
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3075256669
Short name T853
Test name
Test status
Simulation time 99130488 ps
CPU time 8.36 seconds
Started Jun 05 05:22:18 PM PDT 24
Finished Jun 05 05:22:27 PM PDT 24
Peak memory 247288 kb
Host smart-b982d839-8c86-4ef9-98ab-b5b7bf62e919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075256669 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3075256669
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.1441176088
Short name T729
Test name
Test status
Simulation time 35916585037 ps
CPU time 149.9 seconds
Started Jun 05 05:22:18 PM PDT 24
Finished Jun 05 05:24:49 PM PDT 24
Peak memory 283672 kb
Host smart-ff5384b7-e8c5-443a-8ac6-5bd3be1b5c1b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441176088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.1441176088
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.1655376376
Short name T617
Test name
Test status
Simulation time 84785026 ps
CPU time 0.88 seconds
Started Jun 05 05:22:15 PM PDT 24
Finished Jun 05 05:22:17 PM PDT 24
Peak memory 212656 kb
Host smart-2d250b38-e798-4f3a-ab14-4916eef02401
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655376376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.1655376376
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.2075460573
Short name T210
Test name
Test status
Simulation time 19413187 ps
CPU time 1.17 seconds
Started Jun 05 05:22:29 PM PDT 24
Finished Jun 05 05:22:31 PM PDT 24
Peak memory 209564 kb
Host smart-03b0c9f8-66cf-41db-8288-00849bf6c88d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075460573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.2075460573
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.2015252211
Short name T375
Test name
Test status
Simulation time 1921323701 ps
CPU time 11.99 seconds
Started Jun 05 05:22:26 PM PDT 24
Finished Jun 05 05:22:39 PM PDT 24
Peak memory 217988 kb
Host smart-c3bfc214-0fc0-44af-ac50-e9f76530b8e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015252211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.2015252211
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.2345703852
Short name T460
Test name
Test status
Simulation time 794095084 ps
CPU time 5.55 seconds
Started Jun 05 05:22:26 PM PDT 24
Finished Jun 05 05:22:32 PM PDT 24
Peak memory 209512 kb
Host smart-fe28adc0-fee4-40ef-bcc4-1cdfead82a6f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345703852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.2345703852
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.774213406
Short name T623
Test name
Test status
Simulation time 77993777 ps
CPU time 1.87 seconds
Started Jun 05 05:22:27 PM PDT 24
Finished Jun 05 05:22:30 PM PDT 24
Peak memory 217964 kb
Host smart-4309b428-b87d-4bfe-89c7-c3b8c7afd96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774213406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.774213406
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.2853021066
Short name T394
Test name
Test status
Simulation time 661918312 ps
CPU time 13.16 seconds
Started Jun 05 05:22:25 PM PDT 24
Finished Jun 05 05:22:39 PM PDT 24
Peak memory 219092 kb
Host smart-6404ef46-7fb4-4cd9-bc05-62c3f96bb5b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853021066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.2853021066
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.2874872681
Short name T841
Test name
Test status
Simulation time 450117116 ps
CPU time 17.6 seconds
Started Jun 05 05:22:26 PM PDT 24
Finished Jun 05 05:22:44 PM PDT 24
Peak memory 226032 kb
Host smart-b17f5654-44ec-4b90-bc9e-7484d279ba45
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874872681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.2874872681
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2102391745
Short name T593
Test name
Test status
Simulation time 514068047 ps
CPU time 7.3 seconds
Started Jun 05 05:22:26 PM PDT 24
Finished Jun 05 05:22:34 PM PDT 24
Peak memory 217924 kb
Host smart-55cfeeab-3476-424f-87c6-ce7e5fea41a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102391745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2102391745
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.3825682960
Short name T324
Test name
Test status
Simulation time 348879971 ps
CPU time 8.97 seconds
Started Jun 05 05:22:27 PM PDT 24
Finished Jun 05 05:22:37 PM PDT 24
Peak memory 224620 kb
Host smart-b2062d2e-fe51-438c-824d-0b20a8ffe0bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825682960 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.3825682960
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.615718987
Short name T316
Test name
Test status
Simulation time 26923318 ps
CPU time 1.37 seconds
Started Jun 05 05:22:28 PM PDT 24
Finished Jun 05 05:22:30 PM PDT 24
Peak memory 217704 kb
Host smart-a46949a6-02fd-4124-9c9b-fe9b91e69cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615718987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.615718987
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.3637579346
Short name T709
Test name
Test status
Simulation time 1735406989 ps
CPU time 32.46 seconds
Started Jun 05 05:22:27 PM PDT 24
Finished Jun 05 05:23:00 PM PDT 24
Peak memory 250896 kb
Host smart-17d18c02-f395-4f1b-ac48-0f4cf933fe97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637579346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.3637579346
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.3327872120
Short name T10
Test name
Test status
Simulation time 66146617 ps
CPU time 7.67 seconds
Started Jun 05 05:22:29 PM PDT 24
Finished Jun 05 05:22:38 PM PDT 24
Peak memory 250888 kb
Host smart-fd6982d7-1195-4bff-ae8f-f3a875000f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327872120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.3327872120
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.2366787325
Short name T779
Test name
Test status
Simulation time 6597868368 ps
CPU time 227.14 seconds
Started Jun 05 05:22:28 PM PDT 24
Finished Jun 05 05:26:16 PM PDT 24
Peak memory 251312 kb
Host smart-7141dcb1-af19-4581-9c6d-4bbb1f09955e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366787325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.2366787325
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.1417088141
Short name T587
Test name
Test status
Simulation time 16773652 ps
CPU time 0.89 seconds
Started Jun 05 05:22:27 PM PDT 24
Finished Jun 05 05:22:29 PM PDT 24
Peak memory 211568 kb
Host smart-4e4fc4f3-1ec9-4630-a5e4-e2623fb263f5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417088141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.1417088141
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.2843165663
Short name T538
Test name
Test status
Simulation time 18366865 ps
CPU time 1.11 seconds
Started Jun 05 05:22:28 PM PDT 24
Finished Jun 05 05:22:30 PM PDT 24
Peak memory 208656 kb
Host smart-3d3937e7-8f8c-4aa9-ac20-496b821a15c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843165663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.2843165663
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.567082894
Short name T502
Test name
Test status
Simulation time 1181149255 ps
CPU time 11.4 seconds
Started Jun 05 05:22:27 PM PDT 24
Finished Jun 05 05:22:39 PM PDT 24
Peak memory 218056 kb
Host smart-0c1767df-69f2-4c81-a809-402226a31150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567082894 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.567082894
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.3314774143
Short name T564
Test name
Test status
Simulation time 83457552 ps
CPU time 1.75 seconds
Started Jun 05 05:22:28 PM PDT 24
Finished Jun 05 05:22:31 PM PDT 24
Peak memory 209504 kb
Host smart-111ad67f-31d7-4e21-b977-9c0a6db428db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314774143 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.3314774143
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.1854393058
Short name T839
Test name
Test status
Simulation time 58063248 ps
CPU time 3.34 seconds
Started Jun 05 05:22:28 PM PDT 24
Finished Jun 05 05:22:32 PM PDT 24
Peak memory 218080 kb
Host smart-b8b43e6f-7e69-499e-b9cc-1b58886d05e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854393058 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.1854393058
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2328999051
Short name T270
Test name
Test status
Simulation time 919877413 ps
CPU time 19.61 seconds
Started Jun 05 05:22:27 PM PDT 24
Finished Jun 05 05:22:48 PM PDT 24
Peak memory 218960 kb
Host smart-d9d71589-a12c-4987-92e8-da7af2f8476e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328999051 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2328999051
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.3189238783
Short name T273
Test name
Test status
Simulation time 272412075 ps
CPU time 10.73 seconds
Started Jun 05 05:22:26 PM PDT 24
Finished Jun 05 05:22:38 PM PDT 24
Peak memory 226044 kb
Host smart-09569f5b-dec7-46bc-85a7-7a3a82989d1a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189238783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_d
igest.3189238783
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.1317973472
Short name T254
Test name
Test status
Simulation time 268883018 ps
CPU time 8.78 seconds
Started Jun 05 05:22:27 PM PDT 24
Finished Jun 05 05:22:37 PM PDT 24
Peak memory 218020 kb
Host smart-b87f7420-b9f0-4c0c-8a29-ade221449efb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317973472 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.
1317973472
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.2409103558
Short name T382
Test name
Test status
Simulation time 984248252 ps
CPU time 6.7 seconds
Started Jun 05 05:22:28 PM PDT 24
Finished Jun 05 05:22:36 PM PDT 24
Peak memory 224120 kb
Host smart-3c26e5a2-d2d0-416a-8244-67e61dfed601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409103558 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.2409103558
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1614855556
Short name T816
Test name
Test status
Simulation time 131449850 ps
CPU time 2.42 seconds
Started Jun 05 05:22:28 PM PDT 24
Finished Jun 05 05:22:32 PM PDT 24
Peak memory 217628 kb
Host smart-354f6637-f363-4602-96be-92b0f7afc0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614855556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1614855556
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3737138537
Short name T334
Test name
Test status
Simulation time 220480160 ps
CPU time 22.17 seconds
Started Jun 05 05:22:28 PM PDT 24
Finished Jun 05 05:22:51 PM PDT 24
Peak memory 250848 kb
Host smart-4d17d534-3969-4a8c-a23e-bf0548b8c268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737138537 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3737138537
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.2643872121
Short name T819
Test name
Test status
Simulation time 91033767 ps
CPU time 9.19 seconds
Started Jun 05 05:22:25 PM PDT 24
Finished Jun 05 05:22:35 PM PDT 24
Peak memory 250916 kb
Host smart-1af04120-99ca-41ab-ac15-20bc844adae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643872121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.2643872121
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.199597550
Short name T77
Test name
Test status
Simulation time 47245523238 ps
CPU time 183.23 seconds
Started Jun 05 05:22:28 PM PDT 24
Finished Jun 05 05:25:32 PM PDT 24
Peak memory 279148 kb
Host smart-aaa8d985-afa6-4419-9148-bd7c8c464d31
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199597550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.199597550
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all_with_rand_reset.4015721228
Short name T573
Test name
Test status
Simulation time 80690187779 ps
CPU time 2251.21 seconds
Started Jun 05 05:22:26 PM PDT 24
Finished Jun 05 05:59:59 PM PDT 24
Peak memory 922872 kb
Host smart-9c21a0b9-a48a-4e2e-882f-7358631bb76b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4015721228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_stress_all_with_rand_reset.4015721228
Directory /workspace/43.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.3550927886
Short name T864
Test name
Test status
Simulation time 38865647 ps
CPU time 0.74 seconds
Started Jun 05 05:22:27 PM PDT 24
Finished Jun 05 05:22:29 PM PDT 24
Peak memory 206728 kb
Host smart-998b568a-aa69-452a-ae73-8dedb2c72ecd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550927886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.3550927886
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3813738229
Short name T347
Test name
Test status
Simulation time 72641339 ps
CPU time 1.04 seconds
Started Jun 05 05:22:44 PM PDT 24
Finished Jun 05 05:22:46 PM PDT 24
Peak memory 208668 kb
Host smart-6c7e655e-0062-4d74-b1a9-ad362fbc01cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813738229 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3813738229
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.2999103429
Short name T767
Test name
Test status
Simulation time 651271956 ps
CPU time 11.96 seconds
Started Jun 05 05:22:28 PM PDT 24
Finished Jun 05 05:22:40 PM PDT 24
Peak memory 218144 kb
Host smart-09fdbe57-4567-4a89-bf08-edc9c7e71d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999103429 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.2999103429
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.4090191836
Short name T581
Test name
Test status
Simulation time 1385964133 ps
CPU time 3.87 seconds
Started Jun 05 05:22:39 PM PDT 24
Finished Jun 05 05:22:44 PM PDT 24
Peak memory 216836 kb
Host smart-375e1078-e086-4dc5-a3a0-4c6eec8297fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090191836 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.4090191836
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.409388352
Short name T701
Test name
Test status
Simulation time 144776873 ps
CPU time 3.78 seconds
Started Jun 05 05:22:28 PM PDT 24
Finished Jun 05 05:22:33 PM PDT 24
Peak memory 218008 kb
Host smart-7587f848-2f51-4fb9-a989-da29931ffe5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409388352 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.409388352
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.602103810
Short name T14
Test name
Test status
Simulation time 938053868 ps
CPU time 18.3 seconds
Started Jun 05 05:22:41 PM PDT 24
Finished Jun 05 05:23:00 PM PDT 24
Peak memory 218948 kb
Host smart-e76610c9-0cc5-40b8-917c-7a80456dedad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602103810 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.602103810
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.1985719957
Short name T837
Test name
Test status
Simulation time 1354750478 ps
CPU time 13.3 seconds
Started Jun 05 05:22:44 PM PDT 24
Finished Jun 05 05:22:58 PM PDT 24
Peak memory 226012 kb
Host smart-74133e6e-5faf-45be-aa2f-aa531b439b67
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985719957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_d
igest.1985719957
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.2009808946
Short name T413
Test name
Test status
Simulation time 822021228 ps
CPU time 14.11 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:22:58 PM PDT 24
Peak memory 218004 kb
Host smart-135137e2-9b7b-4a13-9d94-88915ca699be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009808946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.
2009808946
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.4184796151
Short name T189
Test name
Test status
Simulation time 2214410810 ps
CPU time 14.22 seconds
Started Jun 05 05:22:28 PM PDT 24
Finished Jun 05 05:22:43 PM PDT 24
Peak memory 225620 kb
Host smart-756e031d-db6d-4634-8fa2-bd277665a1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184796151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.4184796151
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.947815226
Short name T738
Test name
Test status
Simulation time 78199734 ps
CPU time 2.59 seconds
Started Jun 05 05:22:28 PM PDT 24
Finished Jun 05 05:22:32 PM PDT 24
Peak memory 217648 kb
Host smart-5cb5351e-6573-4cac-8120-fd82eebfdca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947815226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.947815226
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.548959601
Short name T562
Test name
Test status
Simulation time 1208697762 ps
CPU time 26.76 seconds
Started Jun 05 05:22:30 PM PDT 24
Finished Jun 05 05:22:57 PM PDT 24
Peak memory 250904 kb
Host smart-c30bff72-ff1f-4028-9c9f-aab4c5314a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548959601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.548959601
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.1217018069
Short name T309
Test name
Test status
Simulation time 107269308 ps
CPU time 8.31 seconds
Started Jun 05 05:22:28 PM PDT 24
Finished Jun 05 05:22:38 PM PDT 24
Peak memory 250908 kb
Host smart-2459fb0e-9cdf-4e53-aa68-637510d23708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217018069 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.1217018069
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.4046351681
Short name T540
Test name
Test status
Simulation time 11940219346 ps
CPU time 92.52 seconds
Started Jun 05 05:22:41 PM PDT 24
Finished Jun 05 05:24:15 PM PDT 24
Peak memory 267552 kb
Host smart-113b5b20-adbe-4e6f-b7c6-d57ca9b45f63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046351681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.4046351681
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all_with_rand_reset.1250199552
Short name T137
Test name
Test status
Simulation time 385479589122 ps
CPU time 8374.18 seconds
Started Jun 05 05:22:41 PM PDT 24
Finished Jun 05 07:42:16 PM PDT 24
Peak memory 726232 kb
Host smart-da72fae6-04e1-4374-bbe9-26d6d7833db7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1250199552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_stress_all_with_rand_reset.1250199552
Directory /workspace/44.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2900121029
Short name T849
Test name
Test status
Simulation time 11679734 ps
CPU time 1.03 seconds
Started Jun 05 05:22:27 PM PDT 24
Finished Jun 05 05:22:29 PM PDT 24
Peak memory 211460 kb
Host smart-bfc41b91-cbf9-42fe-93b6-21162a68c609
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900121029 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_c
trl_volatile_unlock_smoke.2900121029
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.2047827053
Short name T649
Test name
Test status
Simulation time 22836679 ps
CPU time 1.3 seconds
Started Jun 05 05:22:42 PM PDT 24
Finished Jun 05 05:22:45 PM PDT 24
Peak memory 208716 kb
Host smart-134c1da1-8993-4128-b473-b9ad863240ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047827053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.2047827053
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1109149688
Short name T615
Test name
Test status
Simulation time 1179137641 ps
CPU time 17.62 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:23:02 PM PDT 24
Peak memory 217984 kb
Host smart-dbe22a6b-b0c9-4c0d-a12b-0a1b07a7b40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109149688 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1109149688
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1493565152
Short name T492
Test name
Test status
Simulation time 1029737530 ps
CPU time 3.34 seconds
Started Jun 05 05:22:42 PM PDT 24
Finished Jun 05 05:22:47 PM PDT 24
Peak memory 217716 kb
Host smart-b0c669ba-920b-47e0-906e-75be7ec75337
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493565152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1493565152
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2937337658
Short name T531
Test name
Test status
Simulation time 1821932851 ps
CPU time 4.36 seconds
Started Jun 05 05:22:44 PM PDT 24
Finished Jun 05 05:22:49 PM PDT 24
Peak memory 218080 kb
Host smart-b9793164-3f75-4530-b21e-32925a84d01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937337658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2937337658
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.3156677814
Short name T386
Test name
Test status
Simulation time 628688955 ps
CPU time 13.87 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:22:58 PM PDT 24
Peak memory 218944 kb
Host smart-8226f5ad-f3cd-45c6-9fd2-6cb73aca3249
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156677814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.3156677814
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.2272287501
Short name T207
Test name
Test status
Simulation time 3181853454 ps
CPU time 11.79 seconds
Started Jun 05 05:22:40 PM PDT 24
Finished Jun 05 05:22:53 PM PDT 24
Peak memory 225864 kb
Host smart-867ee165-b185-405a-b326-9a11b0d2c7a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272287501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.2272287501
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.4251175376
Short name T863
Test name
Test status
Simulation time 413070262 ps
CPU time 11.51 seconds
Started Jun 05 05:22:41 PM PDT 24
Finished Jun 05 05:22:53 PM PDT 24
Peak memory 217932 kb
Host smart-072e0e39-4feb-4144-9f7b-363ee57c7b91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251175376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.
4251175376
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.1435051170
Short name T769
Test name
Test status
Simulation time 185547792 ps
CPU time 7.86 seconds
Started Jun 05 05:22:45 PM PDT 24
Finished Jun 05 05:22:54 PM PDT 24
Peak memory 224748 kb
Host smart-445b6a03-53a2-43f1-b657-0d1db8bea0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435051170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.1435051170
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.595401317
Short name T571
Test name
Test status
Simulation time 19734984 ps
CPU time 1.46 seconds
Started Jun 05 05:22:41 PM PDT 24
Finished Jun 05 05:22:44 PM PDT 24
Peak memory 213524 kb
Host smart-f2ed8811-bc82-451d-89b3-6204a018cecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595401317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.595401317
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.2173935670
Short name T854
Test name
Test status
Simulation time 662896368 ps
CPU time 19.29 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:23:04 PM PDT 24
Peak memory 250796 kb
Host smart-f13700de-adc9-4cde-92c6-89df25e3051d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173935670 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.2173935670
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.4178017704
Short name T149
Test name
Test status
Simulation time 99524732 ps
CPU time 3.79 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:22:48 PM PDT 24
Peak memory 217968 kb
Host smart-ffb00806-030a-4965-983b-57173c7ae3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178017704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.4178017704
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.3251800750
Short name T488
Test name
Test status
Simulation time 7285410157 ps
CPU time 243.82 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:26:48 PM PDT 24
Peak memory 283668 kb
Host smart-b1f4d461-c4c3-4278-9165-67e00495c954
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251800750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.3251800750
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.1734628288
Short name T697
Test name
Test status
Simulation time 10432729 ps
CPU time 1 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:22:46 PM PDT 24
Peak memory 211460 kb
Host smart-fbc9d22b-041a-4adc-b9e7-485ec5229db7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734628288 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_c
trl_volatile_unlock_smoke.1734628288
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1761623329
Short name T81
Test name
Test status
Simulation time 22537744 ps
CPU time 1.06 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:22:46 PM PDT 24
Peak memory 209564 kb
Host smart-2af8d64d-9533-4d49-b620-5a70188f095c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761623329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1761623329
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2356279213
Short name T610
Test name
Test status
Simulation time 383268812 ps
CPU time 10.66 seconds
Started Jun 05 05:22:41 PM PDT 24
Finished Jun 05 05:22:53 PM PDT 24
Peak memory 217992 kb
Host smart-9684ae5d-b5e3-4fd4-b5ea-37cd8fa0d9e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356279213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2356279213
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.2906134170
Short name T707
Test name
Test status
Simulation time 405956085 ps
CPU time 11.62 seconds
Started Jun 05 05:22:41 PM PDT 24
Finished Jun 05 05:22:53 PM PDT 24
Peak memory 209592 kb
Host smart-96df58a5-071c-4209-9ba2-2d894bf52989
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906134170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.2906134170
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.2892561704
Short name T372
Test name
Test status
Simulation time 347458092 ps
CPU time 4.1 seconds
Started Jun 05 05:22:41 PM PDT 24
Finished Jun 05 05:22:45 PM PDT 24
Peak memory 218024 kb
Host smart-727736ae-4b3f-4771-b929-cd9807119e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892561704 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.2892561704
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.2123373511
Short name T439
Test name
Test status
Simulation time 1174354975 ps
CPU time 12.48 seconds
Started Jun 05 05:22:41 PM PDT 24
Finished Jun 05 05:22:54 PM PDT 24
Peak memory 218956 kb
Host smart-8b3233e8-e01a-400e-a895-086dc03eb796
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123373511 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.2123373511
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.1429038573
Short name T806
Test name
Test status
Simulation time 406634057 ps
CPU time 15.8 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:22:59 PM PDT 24
Peak memory 225984 kb
Host smart-f17bc34c-13bf-442d-a55d-c6cdfe102f3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429038573 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_d
igest.1429038573
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3769338842
Short name T363
Test name
Test status
Simulation time 216977786 ps
CPU time 8.52 seconds
Started Jun 05 05:22:42 PM PDT 24
Finished Jun 05 05:22:51 PM PDT 24
Peak memory 217932 kb
Host smart-e75c5c2b-b69f-4128-9f7b-bfed37e61a02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769338842 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3769338842
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.1071245586
Short name T785
Test name
Test status
Simulation time 1765112352 ps
CPU time 9.5 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:22:54 PM PDT 24
Peak memory 226048 kb
Host smart-7dc4db9a-204d-4ffd-9da9-64eb9df11845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071245586 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.1071245586
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.1836675093
Short name T283
Test name
Test status
Simulation time 39534222 ps
CPU time 2.59 seconds
Started Jun 05 05:22:41 PM PDT 24
Finished Jun 05 05:22:44 PM PDT 24
Peak memory 214276 kb
Host smart-3d770f89-245f-437d-82d7-497b47b39c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836675093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.1836675093
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.1108706754
Short name T667
Test name
Test status
Simulation time 823646418 ps
CPU time 19.57 seconds
Started Jun 05 05:22:44 PM PDT 24
Finished Jun 05 05:23:05 PM PDT 24
Peak memory 243508 kb
Host smart-29adf146-461e-4782-a0ae-7ef704083ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108706754 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.1108706754
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.2500097613
Short name T344
Test name
Test status
Simulation time 200950097 ps
CPU time 6.93 seconds
Started Jun 05 05:22:44 PM PDT 24
Finished Jun 05 05:22:52 PM PDT 24
Peak memory 246724 kb
Host smart-7d29f9c0-5326-4b43-bf64-35615cedf10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500097613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.2500097613
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.241482194
Short name T696
Test name
Test status
Simulation time 15133456888 ps
CPU time 124.27 seconds
Started Jun 05 05:22:41 PM PDT 24
Finished Jun 05 05:24:46 PM PDT 24
Peak memory 283688 kb
Host smart-96ba2034-a526-4aef-a053-bb99aa94b3ff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241482194 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
46.lc_ctrl_stress_all.241482194
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.4127473828
Short name T589
Test name
Test status
Simulation time 83705929 ps
CPU time 0.92 seconds
Started Jun 05 05:22:42 PM PDT 24
Finished Jun 05 05:22:44 PM PDT 24
Peak memory 211544 kb
Host smart-8b73ba70-223e-475a-be10-63904c756251
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127473828 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.4127473828
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1962943372
Short name T537
Test name
Test status
Simulation time 22100998 ps
CPU time 0.98 seconds
Started Jun 05 05:22:44 PM PDT 24
Finished Jun 05 05:22:46 PM PDT 24
Peak memory 209548 kb
Host smart-977cf484-7678-4541-a326-40de47ca31cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962943372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1962943372
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.317306457
Short name T694
Test name
Test status
Simulation time 2622557674 ps
CPU time 14.09 seconds
Started Jun 05 05:22:42 PM PDT 24
Finished Jun 05 05:22:58 PM PDT 24
Peak memory 218984 kb
Host smart-086e6c8e-320d-4aee-95f6-bf1a7c88178c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317306457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.317306457
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.2519752521
Short name T27
Test name
Test status
Simulation time 395005078 ps
CPU time 5.2 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:22:49 PM PDT 24
Peak memory 216964 kb
Host smart-0bfc4adc-8135-4e77-bb4e-92fc31be5f90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519752521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.2519752521
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.1274666113
Short name T262
Test name
Test status
Simulation time 87950091 ps
CPU time 3.73 seconds
Started Jun 05 05:22:42 PM PDT 24
Finished Jun 05 05:22:47 PM PDT 24
Peak memory 218000 kb
Host smart-041d3ff9-d414-4c19-9493-e942732a9761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274666113 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.1274666113
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3204804378
Short name T300
Test name
Test status
Simulation time 1323145206 ps
CPU time 10.56 seconds
Started Jun 05 05:22:41 PM PDT 24
Finished Jun 05 05:22:52 PM PDT 24
Peak memory 218928 kb
Host smart-c5669b7e-d268-468a-8e82-5ab013565be9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204804378 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3204804378
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.892367061
Short name T789
Test name
Test status
Simulation time 1354090864 ps
CPU time 14.05 seconds
Started Jun 05 05:22:41 PM PDT 24
Finished Jun 05 05:22:56 PM PDT 24
Peak memory 226004 kb
Host smart-9c8e56da-74a1-49ae-a290-c9010752ba02
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892367061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_di
gest.892367061
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.149502626
Short name T797
Test name
Test status
Simulation time 324893656 ps
CPU time 11.75 seconds
Started Jun 05 05:22:42 PM PDT 24
Finished Jun 05 05:22:54 PM PDT 24
Peak memory 218004 kb
Host smart-f02bd600-1e46-476e-bc70-de10e61a8550
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149502626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.149502626
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.1082003209
Short name T355
Test name
Test status
Simulation time 788102782 ps
CPU time 9 seconds
Started Jun 05 05:22:42 PM PDT 24
Finished Jun 05 05:22:52 PM PDT 24
Peak memory 224256 kb
Host smart-89e48313-6c37-4442-87af-93a29943c074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082003209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.1082003209
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.628192681
Short name T75
Test name
Test status
Simulation time 190997337 ps
CPU time 2.4 seconds
Started Jun 05 05:22:41 PM PDT 24
Finished Jun 05 05:22:44 PM PDT 24
Peak memory 217708 kb
Host smart-f4aff06d-6b6f-448b-a9ad-e340e9403f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628192681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.628192681
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.3031935310
Short name T651
Test name
Test status
Simulation time 547578853 ps
CPU time 21.65 seconds
Started Jun 05 05:22:42 PM PDT 24
Finished Jun 05 05:23:05 PM PDT 24
Peak memory 250916 kb
Host smart-87a58dbe-180c-40dd-9f17-967b39114de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031935310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.3031935310
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.3149181000
Short name T735
Test name
Test status
Simulation time 104261325 ps
CPU time 7.01 seconds
Started Jun 05 05:22:44 PM PDT 24
Finished Jun 05 05:22:53 PM PDT 24
Peak memory 246604 kb
Host smart-40a682a5-0db7-4232-92ad-a5c6d044fe07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149181000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.3149181000
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.463632538
Short name T438
Test name
Test status
Simulation time 33861697405 ps
CPU time 61.39 seconds
Started Jun 05 05:22:46 PM PDT 24
Finished Jun 05 05:23:48 PM PDT 24
Peak memory 282704 kb
Host smart-fe658126-13e7-40e9-8d02-f95632e9a1f2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463632538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.463632538
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.1535744154
Short name T87
Test name
Test status
Simulation time 35291950 ps
CPU time 1 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:22:46 PM PDT 24
Peak memory 211460 kb
Host smart-6aba7f2a-5948-419e-8893-b1aa5d6ed3e5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535744154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.1535744154
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1538735420
Short name T399
Test name
Test status
Simulation time 90624826 ps
CPU time 1.11 seconds
Started Jun 05 05:22:55 PM PDT 24
Finished Jun 05 05:22:57 PM PDT 24
Peak memory 208736 kb
Host smart-e3a59e8e-653f-4617-b5b1-8a793fafd924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538735420 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1538735420
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.1909833251
Short name T845
Test name
Test status
Simulation time 291729157 ps
CPU time 12.23 seconds
Started Jun 05 05:22:42 PM PDT 24
Finished Jun 05 05:22:55 PM PDT 24
Peak memory 218076 kb
Host smart-303be0da-53a5-4ef2-891f-a96c693027ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909833251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.1909833251
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.3077909763
Short name T606
Test name
Test status
Simulation time 227464128 ps
CPU time 3.98 seconds
Started Jun 05 05:22:42 PM PDT 24
Finished Jun 05 05:22:47 PM PDT 24
Peak memory 216880 kb
Host smart-36250ca6-b8c2-40ca-82c9-d9cf5c9038a0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077909763 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.3077909763
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3680668809
Short name T448
Test name
Test status
Simulation time 17751942 ps
CPU time 1.45 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:22:46 PM PDT 24
Peak memory 218008 kb
Host smart-ce3b68ea-bdf4-42b6-8cbf-fb313a724f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680668809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3680668809
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.4167966324
Short name T330
Test name
Test status
Simulation time 526296856 ps
CPU time 10.19 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:22:55 PM PDT 24
Peak memory 225048 kb
Host smart-3fa79efa-9111-427c-bdeb-a8eb8f53f8a1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167966324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.4167966324
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.376103862
Short name T471
Test name
Test status
Simulation time 1624598771 ps
CPU time 14.82 seconds
Started Jun 05 05:22:44 PM PDT 24
Finished Jun 05 05:23:00 PM PDT 24
Peak memory 226036 kb
Host smart-b60efc25-f26d-4756-b549-32edf9b3b2ec
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376103862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.376103862
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1508452273
Short name T401
Test name
Test status
Simulation time 1736561567 ps
CPU time 15.16 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:23:00 PM PDT 24
Peak memory 217936 kb
Host smart-97994441-0d1d-4745-856c-6185a61a7c78
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508452273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1508452273
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.2875123772
Short name T393
Test name
Test status
Simulation time 802984114 ps
CPU time 10.91 seconds
Started Jun 05 05:22:44 PM PDT 24
Finished Jun 05 05:22:56 PM PDT 24
Peak memory 226072 kb
Host smart-1dd03655-edd1-4a3a-b893-4914433cd63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875123772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.2875123772
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.3711108260
Short name T660
Test name
Test status
Simulation time 74266187 ps
CPU time 2.86 seconds
Started Jun 05 05:22:41 PM PDT 24
Finished Jun 05 05:22:45 PM PDT 24
Peak memory 214568 kb
Host smart-3b4066b9-6ed7-4202-a3c7-6ab8c4f830a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711108260 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.3711108260
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.2575405532
Short name T519
Test name
Test status
Simulation time 1006250334 ps
CPU time 30.83 seconds
Started Jun 05 05:22:45 PM PDT 24
Finished Jun 05 05:23:17 PM PDT 24
Peak memory 251052 kb
Host smart-31011ec6-df6d-4ed7-a4d5-bbefe175eb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575405532 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.2575405532
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.2188005082
Short name T507
Test name
Test status
Simulation time 168596406 ps
CPU time 7.41 seconds
Started Jun 05 05:22:56 PM PDT 24
Finished Jun 05 05:23:04 PM PDT 24
Peak memory 250928 kb
Host smart-c36a1b9c-2c35-4bc7-a082-ae72a2b99984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188005082 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.2188005082
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3545694335
Short name T511
Test name
Test status
Simulation time 7014118810 ps
CPU time 224.97 seconds
Started Jun 05 05:23:00 PM PDT 24
Finished Jun 05 05:26:47 PM PDT 24
Peak memory 276384 kb
Host smart-3a2e96a9-aed8-4c37-88b8-7d2c437ba115
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545694335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3545694335
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.3505155963
Short name T31
Test name
Test status
Simulation time 116269886309 ps
CPU time 6317.08 seconds
Started Jun 05 05:22:45 PM PDT 24
Finished Jun 05 07:08:04 PM PDT 24
Peak memory 1150552 kb
Host smart-27ad88b9-b1fd-42ab-be9a-89f23eed1835
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3505155963 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.3505155963
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.738471334
Short name T415
Test name
Test status
Simulation time 49350657 ps
CPU time 0.84 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:22:44 PM PDT 24
Peak memory 211500 kb
Host smart-fdf40aec-1a38-412f-b7d1-d494a3535dbf
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738471334 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ct
rl_volatile_unlock_smoke.738471334
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.1679548215
Short name T755
Test name
Test status
Simulation time 32970463 ps
CPU time 0.93 seconds
Started Jun 05 05:22:45 PM PDT 24
Finished Jun 05 05:22:47 PM PDT 24
Peak memory 208816 kb
Host smart-8b694d71-deff-4cdc-a034-78a2adc5b42f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679548215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.1679548215
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.19298341
Short name T331
Test name
Test status
Simulation time 2370744555 ps
CPU time 15.69 seconds
Started Jun 05 05:22:46 PM PDT 24
Finished Jun 05 05:23:03 PM PDT 24
Peak memory 218996 kb
Host smart-10b9d5de-b1b0-4fc9-833b-cc0340388173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19298341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.19298341
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.3390367778
Short name T275
Test name
Test status
Simulation time 1173126686 ps
CPU time 6.28 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:22:50 PM PDT 24
Peak memory 209492 kb
Host smart-2a023e78-f7e6-446c-b6ff-0f63c4b2c29c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390367778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.3390367778
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2945117525
Short name T325
Test name
Test status
Simulation time 28361802 ps
CPU time 1.88 seconds
Started Jun 05 05:22:42 PM PDT 24
Finished Jun 05 05:22:45 PM PDT 24
Peak memory 218008 kb
Host smart-383989af-0ed5-49d2-8d27-c565158e9f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945117525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2945117525
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.754170504
Short name T788
Test name
Test status
Simulation time 5367409970 ps
CPU time 18.62 seconds
Started Jun 05 05:22:47 PM PDT 24
Finished Jun 05 05:23:07 PM PDT 24
Peak memory 218432 kb
Host smart-a7d285d2-b0c2-4977-8c2a-2293c53d5a74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754170504 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.754170504
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.1215137034
Short name T639
Test name
Test status
Simulation time 4806553577 ps
CPU time 29.36 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:23:14 PM PDT 24
Peak memory 226068 kb
Host smart-5b1440a3-43a5-4e36-80bc-a292d84c6478
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215137034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.1215137034
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.1504781771
Short name T535
Test name
Test status
Simulation time 242154494 ps
CPU time 9.72 seconds
Started Jun 05 05:22:56 PM PDT 24
Finished Jun 05 05:23:06 PM PDT 24
Peak memory 218004 kb
Host smart-bb838c2b-68c0-493d-8796-3627ad40ad23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504781771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
1504781771
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.1742208454
Short name T46
Test name
Test status
Simulation time 383675050 ps
CPU time 11.39 seconds
Started Jun 05 05:22:47 PM PDT 24
Finished Jun 05 05:22:59 PM PDT 24
Peak memory 225656 kb
Host smart-89124a7c-488a-4800-9fe8-f210da3241ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742208454 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.1742208454
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1533685519
Short name T857
Test name
Test status
Simulation time 151390861 ps
CPU time 1.23 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:22:46 PM PDT 24
Peak memory 217720 kb
Host smart-27bb46af-34a2-49aa-85a0-8ca43d4655c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533685519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1533685519
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.3206533385
Short name T482
Test name
Test status
Simulation time 176094772 ps
CPU time 20.17 seconds
Started Jun 05 05:22:43 PM PDT 24
Finished Jun 05 05:23:04 PM PDT 24
Peak memory 250904 kb
Host smart-ef68eb57-d0d8-44c8-b57f-9c7148e84b4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206533385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.3206533385
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.501443164
Short name T551
Test name
Test status
Simulation time 411337395 ps
CPU time 6.68 seconds
Started Jun 05 05:22:42 PM PDT 24
Finished Jun 05 05:22:50 PM PDT 24
Peak memory 247592 kb
Host smart-99336bf3-7fdc-4299-ab02-ef1751359b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501443164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.501443164
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.2669073679
Short name T552
Test name
Test status
Simulation time 8551975060 ps
CPU time 42.74 seconds
Started Jun 05 05:22:48 PM PDT 24
Finished Jun 05 05:23:31 PM PDT 24
Peak memory 250968 kb
Host smart-365ca3c4-3530-440b-82df-202ecf48247c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669073679 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.2669073679
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.1387622501
Short name T763
Test name
Test status
Simulation time 11668469 ps
CPU time 1.01 seconds
Started Jun 05 05:22:46 PM PDT 24
Finished Jun 05 05:22:48 PM PDT 24
Peak memory 211584 kb
Host smart-7863654a-dc98-49fe-8521-318611aa6adb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387622501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.1387622501
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.1016879953
Short name T630
Test name
Test status
Simulation time 42896674 ps
CPU time 0.96 seconds
Started Jun 05 05:19:49 PM PDT 24
Finished Jun 05 05:19:50 PM PDT 24
Peak memory 208668 kb
Host smart-e6cdd6b0-3acb-43b0-8791-056be8a74466
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016879953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.1016879953
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.67805924
Short name T225
Test name
Test status
Simulation time 365226086 ps
CPU time 16.68 seconds
Started Jun 05 05:19:44 PM PDT 24
Finished Jun 05 05:20:01 PM PDT 24
Peak memory 218000 kb
Host smart-b9192c6d-b0e9-4c04-840d-b6ace292cb62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67805924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.67805924
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.3761259132
Short name T23
Test name
Test status
Simulation time 639277560 ps
CPU time 7.66 seconds
Started Jun 05 05:19:50 PM PDT 24
Finished Jun 05 05:19:59 PM PDT 24
Peak memory 209504 kb
Host smart-13e21bd8-d980-41db-89e3-fdfb39f9befd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761259132 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.3761259132
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.2524987432
Short name T290
Test name
Test status
Simulation time 6302205943 ps
CPU time 32.66 seconds
Started Jun 05 05:19:52 PM PDT 24
Finished Jun 05 05:20:25 PM PDT 24
Peak memory 219252 kb
Host smart-0e0d6163-b82e-4160-a240-827b0d418110
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524987432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.2524987432
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.851430802
Short name T518
Test name
Test status
Simulation time 158099388 ps
CPU time 1.71 seconds
Started Jun 05 05:19:49 PM PDT 24
Finished Jun 05 05:19:51 PM PDT 24
Peak memory 217124 kb
Host smart-4b4a4bc8-abf9-4ad6-be70-00aad4390965
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851430802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.851430802
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.2756577747
Short name T695
Test name
Test status
Simulation time 148661524 ps
CPU time 2.65 seconds
Started Jun 05 05:19:49 PM PDT 24
Finished Jun 05 05:19:53 PM PDT 24
Peak memory 217900 kb
Host smart-560e3b29-9161-4c1e-9573-7402077505ef
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756577747 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.2756577747
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.3602201377
Short name T844
Test name
Test status
Simulation time 1454141972 ps
CPU time 41.37 seconds
Started Jun 05 05:19:50 PM PDT 24
Finished Jun 05 05:20:32 PM PDT 24
Peak memory 217652 kb
Host smart-9cbf2cfd-6857-48f3-b196-3b52a71151e1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602201377 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.3602201377
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.1353308613
Short name T455
Test name
Test status
Simulation time 2293984232 ps
CPU time 8.67 seconds
Started Jun 05 05:19:50 PM PDT 24
Finished Jun 05 05:19:59 PM PDT 24
Peak memory 217680 kb
Host smart-0acbac31-24ef-4e41-a15c-fb314a47f0dc
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353308613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
1353308613
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.4055964542
Short name T574
Test name
Test status
Simulation time 7850340467 ps
CPU time 68.8 seconds
Started Jun 05 05:19:49 PM PDT 24
Finished Jun 05 05:20:58 PM PDT 24
Peak memory 267628 kb
Host smart-0319db35-8fee-4f35-b356-b4db17646296
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055964542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.4055964542
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.2224340027
Short name T238
Test name
Test status
Simulation time 307585737 ps
CPU time 11.11 seconds
Started Jun 05 05:19:49 PM PDT 24
Finished Jun 05 05:20:01 PM PDT 24
Peak memory 222936 kb
Host smart-d2098d8b-3815-4db5-9b8f-f098621b222f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224340027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.2224340027
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.2662802977
Short name T487
Test name
Test status
Simulation time 213955513 ps
CPU time 2.55 seconds
Started Jun 05 05:19:41 PM PDT 24
Finished Jun 05 05:19:44 PM PDT 24
Peak memory 218012 kb
Host smart-44403735-3db9-47e3-a7b8-239fa84b2dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662802977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.2662802977
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.2244417453
Short name T404
Test name
Test status
Simulation time 1812825364 ps
CPU time 9.54 seconds
Started Jun 05 05:19:50 PM PDT 24
Finished Jun 05 05:20:00 PM PDT 24
Peak memory 214444 kb
Host smart-80efe9ac-b534-4e1b-8a0d-267d3a1ca01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244417453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.2244417453
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.866240625
Short name T704
Test name
Test status
Simulation time 1464423155 ps
CPU time 17.21 seconds
Started Jun 05 05:19:50 PM PDT 24
Finished Jun 05 05:20:08 PM PDT 24
Peak memory 218932 kb
Host smart-6284b61d-0668-4fcb-adfe-ec8a29c50879
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866240625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.866240625
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.3570721339
Short name T799
Test name
Test status
Simulation time 621003815 ps
CPU time 13.54 seconds
Started Jun 05 05:19:50 PM PDT 24
Finished Jun 05 05:20:04 PM PDT 24
Peak memory 226008 kb
Host smart-1e33d42d-5320-4d90-8311-be26cdede05b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570721339 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.3570721339
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3827291506
Short name T545
Test name
Test status
Simulation time 519281192 ps
CPU time 10.22 seconds
Started Jun 05 05:19:49 PM PDT 24
Finished Jun 05 05:19:59 PM PDT 24
Peak memory 217932 kb
Host smart-4973656b-b497-4342-8ca8-400457a9eda0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827291506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
827291506
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1931744089
Short name T461
Test name
Test status
Simulation time 709979314 ps
CPU time 6.82 seconds
Started Jun 05 05:19:42 PM PDT 24
Finished Jun 05 05:19:50 PM PDT 24
Peak memory 224792 kb
Host smart-6a7326c2-34fe-4247-b2a1-03f46d6ba9f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931744089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1931744089
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.4068887414
Short name T747
Test name
Test status
Simulation time 49685395 ps
CPU time 2.42 seconds
Started Jun 05 05:19:49 PM PDT 24
Finished Jun 05 05:19:52 PM PDT 24
Peak memory 214140 kb
Host smart-8abbff81-135c-433c-ab33-44307ce5e307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068887414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.4068887414
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.2897875222
Short name T760
Test name
Test status
Simulation time 481468345 ps
CPU time 19.87 seconds
Started Jun 05 05:19:43 PM PDT 24
Finished Jun 05 05:20:04 PM PDT 24
Peak memory 250908 kb
Host smart-5581b47c-c8d5-44ca-9731-d48ce6df83ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897875222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.2897875222
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.4096517784
Short name T208
Test name
Test status
Simulation time 126746354 ps
CPU time 9.67 seconds
Started Jun 05 05:19:40 PM PDT 24
Finished Jun 05 05:19:50 PM PDT 24
Peak memory 250928 kb
Host smart-f3b1f26a-e381-4c6b-a28d-52559bfb8f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096517784 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.4096517784
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.1864087718
Short name T821
Test name
Test status
Simulation time 12884016269 ps
CPU time 365.95 seconds
Started Jun 05 05:19:50 PM PDT 24
Finished Jun 05 05:25:57 PM PDT 24
Peak memory 264276 kb
Host smart-e31b5acb-c97f-426e-b94f-51216fe03d4f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864087718 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.1864087718
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2309060458
Short name T369
Test name
Test status
Simulation time 15828082 ps
CPU time 1.06 seconds
Started Jun 05 05:19:48 PM PDT 24
Finished Jun 05 05:19:49 PM PDT 24
Peak memory 212632 kb
Host smart-b5bcdcdd-e6b1-4ccf-a95b-fe1ac46a19e3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309060458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.2309060458
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.823411414
Short name T209
Test name
Test status
Simulation time 94392095 ps
CPU time 1.27 seconds
Started Jun 05 05:19:57 PM PDT 24
Finished Jun 05 05:19:59 PM PDT 24
Peak memory 208752 kb
Host smart-67232376-c6ac-4171-a625-c072f8a0dc1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823411414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.823411414
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.230461033
Short name T802
Test name
Test status
Simulation time 19698020 ps
CPU time 0.95 seconds
Started Jun 05 05:19:55 PM PDT 24
Finished Jun 05 05:19:56 PM PDT 24
Peak memory 208692 kb
Host smart-04c7a4d6-4280-4547-9f70-f070df582efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230461033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.230461033
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.885051753
Short name T37
Test name
Test status
Simulation time 740463832 ps
CPU time 11.51 seconds
Started Jun 05 05:19:56 PM PDT 24
Finished Jun 05 05:20:09 PM PDT 24
Peak memory 217972 kb
Host smart-8d6314e2-c840-4d53-b1d4-9b009c324cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885051753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.885051753
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.1298031488
Short name T4
Test name
Test status
Simulation time 896591658 ps
CPU time 12.76 seconds
Started Jun 05 05:19:58 PM PDT 24
Finished Jun 05 05:20:11 PM PDT 24
Peak memory 209512 kb
Host smart-bcc2d3a5-1d1b-4de3-8392-dbe1ae9f78c5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298031488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.1298031488
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.3706520657
Short name T13
Test name
Test status
Simulation time 2031699344 ps
CPU time 60.14 seconds
Started Jun 05 05:20:00 PM PDT 24
Finished Jun 05 05:21:01 PM PDT 24
Peak memory 217972 kb
Host smart-ded9c7c0-9492-4628-9e7b-5a314cbb47d6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706520657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_er
rors.3706520657
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.833316929
Short name T828
Test name
Test status
Simulation time 4246320029 ps
CPU time 11.6 seconds
Started Jun 05 05:19:57 PM PDT 24
Finished Jun 05 05:20:09 PM PDT 24
Peak memory 217816 kb
Host smart-bbb4162b-bcb3-44fc-876e-6c2cc548331b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833316929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.833316929
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.2615051598
Short name T451
Test name
Test status
Simulation time 1554470742 ps
CPU time 6.7 seconds
Started Jun 05 05:19:58 PM PDT 24
Finished Jun 05 05:20:06 PM PDT 24
Peak memory 217928 kb
Host smart-c5d52360-444c-455b-99d8-edd250e6ead7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615051598 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.2615051598
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.4072008221
Short name T473
Test name
Test status
Simulation time 3580652156 ps
CPU time 10.81 seconds
Started Jun 05 05:20:01 PM PDT 24
Finished Jun 05 05:20:12 PM PDT 24
Peak memory 217688 kb
Host smart-b23b2d6e-f08a-4198-a229-e8a7c863f9a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072008221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_regwen_during_op.4072008221
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.4258745557
Short name T19
Test name
Test status
Simulation time 1017100631 ps
CPU time 8.69 seconds
Started Jun 05 05:19:59 PM PDT 24
Finished Jun 05 05:20:09 PM PDT 24
Peak memory 217636 kb
Host smart-ad1280eb-e80a-4300-99d1-d29092f16cdd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258745557 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
4258745557
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.2785382734
Short name T153
Test name
Test status
Simulation time 4204167818 ps
CPU time 30.54 seconds
Started Jun 05 05:19:59 PM PDT 24
Finished Jun 05 05:20:31 PM PDT 24
Peak memory 267284 kb
Host smart-d1b6201d-9aae-4733-9aa0-49630a3516ab
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785382734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.2785382734
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.1195726099
Short name T459
Test name
Test status
Simulation time 1345967947 ps
CPU time 7.1 seconds
Started Jun 05 05:19:56 PM PDT 24
Finished Jun 05 05:20:04 PM PDT 24
Peak memory 223020 kb
Host smart-04cf4166-9c34-42c4-8bf0-c7731463e52d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195726099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_
jtag_state_post_trans.1195726099
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.1235858211
Short name T867
Test name
Test status
Simulation time 64234206 ps
CPU time 3.18 seconds
Started Jun 05 05:19:51 PM PDT 24
Finished Jun 05 05:19:55 PM PDT 24
Peak memory 218012 kb
Host smart-3e64812f-8a4b-4944-bf85-f2088d9291f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235858211 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.1235858211
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1688994792
Short name T822
Test name
Test status
Simulation time 488677756 ps
CPU time 16.47 seconds
Started Jun 05 05:19:57 PM PDT 24
Finished Jun 05 05:20:14 PM PDT 24
Peak memory 213824 kb
Host smart-c1ea392a-8438-431e-8410-37c6e1574672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688994792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1688994792
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.3748787021
Short name T726
Test name
Test status
Simulation time 1762025198 ps
CPU time 14.14 seconds
Started Jun 05 05:19:56 PM PDT 24
Finished Jun 05 05:20:10 PM PDT 24
Peak memory 218764 kb
Host smart-3fee68a1-035a-43d7-95e9-115bb89308d0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748787021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.3748787021
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.3761796474
Short name T751
Test name
Test status
Simulation time 770974726 ps
CPU time 15.07 seconds
Started Jun 05 05:19:59 PM PDT 24
Finished Jun 05 05:20:16 PM PDT 24
Peak memory 226032 kb
Host smart-2c4fc719-9d0b-4711-ba45-e9cf41df7d91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761796474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.3761796474
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.1624161911
Short name T248
Test name
Test status
Simulation time 624363969 ps
CPU time 11.43 seconds
Started Jun 05 05:19:56 PM PDT 24
Finished Jun 05 05:20:08 PM PDT 24
Peak memory 217892 kb
Host smart-685b4093-31e5-4975-b912-f43a192f12b2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624161911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.1
624161911
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.190224802
Short name T534
Test name
Test status
Simulation time 229150270 ps
CPU time 8.99 seconds
Started Jun 05 05:19:55 PM PDT 24
Finished Jun 05 05:20:05 PM PDT 24
Peak memory 224780 kb
Host smart-a2b140cb-1ab7-4107-a913-b11cbc1ef074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190224802 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.190224802
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1414190529
Short name T240
Test name
Test status
Simulation time 117376435 ps
CPU time 2.33 seconds
Started Jun 05 05:19:49 PM PDT 24
Finished Jun 05 05:19:52 PM PDT 24
Peak memory 214064 kb
Host smart-ad78de55-bb37-4a34-86c6-cfe51f63ce7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414190529 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1414190529
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3318889743
Short name T312
Test name
Test status
Simulation time 438221421 ps
CPU time 20.95 seconds
Started Jun 05 05:19:50 PM PDT 24
Finished Jun 05 05:20:12 PM PDT 24
Peak memory 250836 kb
Host smart-6e1e7d79-d86d-431e-b84d-157f54f1eb7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318889743 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3318889743
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.3879419898
Short name T217
Test name
Test status
Simulation time 80970309 ps
CPU time 6.65 seconds
Started Jun 05 05:19:49 PM PDT 24
Finished Jun 05 05:19:56 PM PDT 24
Peak memory 250364 kb
Host smart-94bbad4d-05d7-471b-92b2-3bfb06f7f573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879419898 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.3879419898
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.1600492816
Short name T339
Test name
Test status
Simulation time 6533046524 ps
CPU time 57.54 seconds
Started Jun 05 05:19:55 PM PDT 24
Finished Jun 05 05:20:53 PM PDT 24
Peak memory 250944 kb
Host smart-0e3c6aa3-f91f-4a73-8f99-6cad91675d34
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600492816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.1600492816
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3790434924
Short name T150
Test name
Test status
Simulation time 14320652 ps
CPU time 0.95 seconds
Started Jun 05 05:19:50 PM PDT 24
Finished Jun 05 05:19:51 PM PDT 24
Peak memory 211592 kb
Host smart-fb9684cd-80be-4d09-8253-23ec2b3b6e7d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790434924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3790434924
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.233146937
Short name T784
Test name
Test status
Simulation time 33277540 ps
CPU time 0.84 seconds
Started Jun 05 05:19:56 PM PDT 24
Finished Jun 05 05:19:58 PM PDT 24
Peak memory 209568 kb
Host smart-6d8693df-a839-45fd-bac7-2901caabd077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233146937 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.233146937
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.3104608237
Short name T807
Test name
Test status
Simulation time 37732560 ps
CPU time 0.99 seconds
Started Jun 05 05:19:58 PM PDT 24
Finished Jun 05 05:20:01 PM PDT 24
Peak memory 208696 kb
Host smart-609cd030-be21-4745-a09d-44e5f1506ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104608237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.3104608237
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.4103357587
Short name T720
Test name
Test status
Simulation time 253658235 ps
CPU time 13.15 seconds
Started Jun 05 05:19:59 PM PDT 24
Finished Jun 05 05:20:13 PM PDT 24
Peak memory 218012 kb
Host smart-540594b1-7bcd-46d7-9146-d116464da977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103357587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.4103357587
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.4152647375
Short name T809
Test name
Test status
Simulation time 1723574793 ps
CPU time 12.4 seconds
Started Jun 05 05:19:58 PM PDT 24
Finished Jun 05 05:20:11 PM PDT 24
Peak memory 209508 kb
Host smart-f367de4f-108f-4162-a51f-790532e956bd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152647375 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.4152647375
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.475392923
Short name T276
Test name
Test status
Simulation time 5586658669 ps
CPU time 24.33 seconds
Started Jun 05 05:19:57 PM PDT 24
Finished Jun 05 05:20:22 PM PDT 24
Peak memory 218572 kb
Host smart-03d249cc-da4b-4ddc-9c28-5d036b3f491c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475392923 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_err
ors.475392923
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.3302643646
Short name T625
Test name
Test status
Simulation time 205327064 ps
CPU time 5.18 seconds
Started Jun 05 05:19:55 PM PDT 24
Finished Jun 05 05:20:01 PM PDT 24
Peak memory 217244 kb
Host smart-70a76c6d-edde-4dba-8a4e-28588e280f4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302643646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.3
302643646
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.4124841416
Short name T368
Test name
Test status
Simulation time 1403996740 ps
CPU time 4.09 seconds
Started Jun 05 05:19:57 PM PDT 24
Finished Jun 05 05:20:02 PM PDT 24
Peak memory 217932 kb
Host smart-be544698-928f-4081-b134-d745dc0ef90f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124841416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.4124841416
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2077081794
Short name T494
Test name
Test status
Simulation time 1125720019 ps
CPU time 30.91 seconds
Started Jun 05 05:19:57 PM PDT 24
Finished Jun 05 05:20:29 PM PDT 24
Peak memory 217616 kb
Host smart-43b88211-dacd-4fb6-9974-d460f6806ff5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077081794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.2077081794
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.4079046088
Short name T66
Test name
Test status
Simulation time 822789165 ps
CPU time 10.26 seconds
Started Jun 05 05:19:58 PM PDT 24
Finished Jun 05 05:20:09 PM PDT 24
Peak memory 217624 kb
Host smart-d6f5f368-f0ac-4006-9ae4-a3c421a1a77a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079046088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
4079046088
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.2777505414
Short name T706
Test name
Test status
Simulation time 1394581945 ps
CPU time 51.4 seconds
Started Jun 05 05:19:58 PM PDT 24
Finished Jun 05 05:20:50 PM PDT 24
Peak memory 267256 kb
Host smart-fa7cd976-36aa-4ef5-9adf-3f07bfb24d95
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777505414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jta
g_state_failure.2777505414
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.71928698
Short name T757
Test name
Test status
Simulation time 1484400268 ps
CPU time 13.9 seconds
Started Jun 05 05:20:00 PM PDT 24
Finished Jun 05 05:20:15 PM PDT 24
Peak memory 250844 kb
Host smart-0e023ef9-b9fc-46dd-ac4c-c5d1149830eb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71928698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jt
ag_state_post_trans.71928698
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.3775007835
Short name T145
Test name
Test status
Simulation time 46908096 ps
CPU time 2.64 seconds
Started Jun 05 05:19:59 PM PDT 24
Finished Jun 05 05:20:03 PM PDT 24
Peak memory 218068 kb
Host smart-092441bd-fca6-4fcf-823f-036f912cff9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775007835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.3775007835
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3831380418
Short name T431
Test name
Test status
Simulation time 1512922353 ps
CPU time 25.8 seconds
Started Jun 05 05:19:58 PM PDT 24
Finished Jun 05 05:20:25 PM PDT 24
Peak memory 214048 kb
Host smart-a05357e0-ec7a-4e32-8866-d803bbb100d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831380418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3831380418
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.2563179793
Short name T558
Test name
Test status
Simulation time 1052734833 ps
CPU time 12.94 seconds
Started Jun 05 05:19:58 PM PDT 24
Finished Jun 05 05:20:12 PM PDT 24
Peak memory 218248 kb
Host smart-2af89224-f5bf-4929-a7d4-320a709a14f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563179793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.2563179793
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.1611052989
Short name T768
Test name
Test status
Simulation time 861350027 ps
CPU time 14.12 seconds
Started Jun 05 05:20:00 PM PDT 24
Finished Jun 05 05:20:15 PM PDT 24
Peak memory 226028 kb
Host smart-c0514c50-99d7-4729-8063-017ee9b3a722
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611052989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.1611052989
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1372370776
Short name T417
Test name
Test status
Simulation time 562860600 ps
CPU time 7.65 seconds
Started Jun 05 05:19:58 PM PDT 24
Finished Jun 05 05:20:07 PM PDT 24
Peak memory 217904 kb
Host smart-cc2fba1c-d218-44b6-9269-6cdfb6fdecbf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372370776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
372370776
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.4155935234
Short name T428
Test name
Test status
Simulation time 597318283 ps
CPU time 12.52 seconds
Started Jun 05 05:19:56 PM PDT 24
Finished Jun 05 05:20:10 PM PDT 24
Peak memory 218044 kb
Host smart-da0945f6-00b4-4e44-b10e-a07a528cc838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155935234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.4155935234
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.3598409073
Short name T736
Test name
Test status
Simulation time 754078837 ps
CPU time 2.53 seconds
Started Jun 05 05:19:57 PM PDT 24
Finished Jun 05 05:20:00 PM PDT 24
Peak memory 217684 kb
Host smart-13205555-a78f-4688-9fbb-027a625ac8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598409073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.3598409073
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.2863768571
Short name T337
Test name
Test status
Simulation time 580677493 ps
CPU time 27 seconds
Started Jun 05 05:19:58 PM PDT 24
Finished Jun 05 05:20:27 PM PDT 24
Peak memory 250928 kb
Host smart-241d142c-91bb-471a-938e-cb82427761f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863768571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.2863768571
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.2779898094
Short name T356
Test name
Test status
Simulation time 64492477 ps
CPU time 3.56 seconds
Started Jun 05 05:19:57 PM PDT 24
Finished Jun 05 05:20:01 PM PDT 24
Peak memory 222360 kb
Host smart-b5e2042f-4582-4952-aaa5-0fbed14fec72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779898094 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.2779898094
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.3284913829
Short name T139
Test name
Test status
Simulation time 6696458592 ps
CPU time 167.45 seconds
Started Jun 05 05:19:58 PM PDT 24
Finished Jun 05 05:22:47 PM PDT 24
Peak memory 404828 kb
Host smart-90a6bd45-ba94-4f4d-afa5-1f0d1c8a68e0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3284913829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_stress_all_with_rand_reset.3284913829
Directory /workspace/7.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.1322882547
Short name T224
Test name
Test status
Simulation time 55103452 ps
CPU time 1.03 seconds
Started Jun 05 05:19:58 PM PDT 24
Finished Jun 05 05:20:00 PM PDT 24
Peak memory 211484 kb
Host smart-e5fbcf6e-a6ed-4dd9-8fce-e56eee4003d5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1322882547 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ct
rl_volatile_unlock_smoke.1322882547
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.1502475073
Short name T833
Test name
Test status
Simulation time 23522838 ps
CPU time 0.97 seconds
Started Jun 05 05:20:13 PM PDT 24
Finished Jun 05 05:20:14 PM PDT 24
Peak memory 208684 kb
Host smart-776b097a-674d-4f19-be9f-33ba3b3184b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502475073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.1502475073
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.1160706245
Short name T29
Test name
Test status
Simulation time 31495334 ps
CPU time 0.8 seconds
Started Jun 05 05:20:07 PM PDT 24
Finished Jun 05 05:20:08 PM PDT 24
Peak memory 208660 kb
Host smart-b1a20ca2-ea76-4187-91a2-6b179ecf41d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160706245 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.1160706245
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1388916599
Short name T653
Test name
Test status
Simulation time 416234369 ps
CPU time 8.9 seconds
Started Jun 05 05:20:07 PM PDT 24
Finished Jun 05 05:20:17 PM PDT 24
Peak memory 217976 kb
Host smart-f8608b73-c9d0-45f7-826c-b4bb050bc60d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388916599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1388916599
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.1724991822
Short name T288
Test name
Test status
Simulation time 1027175403 ps
CPU time 7.16 seconds
Started Jun 05 05:20:06 PM PDT 24
Finished Jun 05 05:20:14 PM PDT 24
Peak memory 209508 kb
Host smart-12858969-65b2-4f27-a503-3263a8074270
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724991822 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.1724991822
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2003704522
Short name T641
Test name
Test status
Simulation time 3638908615 ps
CPU time 53.41 seconds
Started Jun 05 05:20:06 PM PDT 24
Finished Jun 05 05:21:00 PM PDT 24
Peak memory 218936 kb
Host smart-5817e4a2-92b7-40e2-89ea-b37818e634e5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003704522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2003704522
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2421348734
Short name T470
Test name
Test status
Simulation time 475728994 ps
CPU time 6.89 seconds
Started Jun 05 05:20:05 PM PDT 24
Finished Jun 05 05:20:13 PM PDT 24
Peak memory 217300 kb
Host smart-7b40f30c-a016-45c6-9329-7be3f8f1a7f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421348734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
421348734
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.2472894027
Short name T359
Test name
Test status
Simulation time 2544242841 ps
CPU time 6.21 seconds
Started Jun 05 05:20:05 PM PDT 24
Finished Jun 05 05:20:12 PM PDT 24
Peak memory 218056 kb
Host smart-ad1679ed-cbfe-4d0b-8de6-78f698d06af8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472894027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.2472894027
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.4021385357
Short name T541
Test name
Test status
Simulation time 829945239 ps
CPU time 24.83 seconds
Started Jun 05 05:20:07 PM PDT 24
Finished Jun 05 05:20:32 PM PDT 24
Peak memory 217648 kb
Host smart-a3313423-db93-4c0a-8b44-d1d923f23bf8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021385357 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.4021385357
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.1048952271
Short name T59
Test name
Test status
Simulation time 731660546 ps
CPU time 10.95 seconds
Started Jun 05 05:20:06 PM PDT 24
Finished Jun 05 05:20:17 PM PDT 24
Peak memory 217636 kb
Host smart-73d385f8-34f0-4a00-9a26-739ba19b6395
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048952271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
1048952271
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.4162882766
Short name T274
Test name
Test status
Simulation time 5356507622 ps
CPU time 77.27 seconds
Started Jun 05 05:20:14 PM PDT 24
Finished Jun 05 05:21:32 PM PDT 24
Peak memory 271700 kb
Host smart-81dfde77-2c77-4bc6-81e0-6ee74f4ce7c3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162882766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.4162882766
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.2387053416
Short name T289
Test name
Test status
Simulation time 598821393 ps
CPU time 10.16 seconds
Started Jun 05 05:20:05 PM PDT 24
Finished Jun 05 05:20:16 PM PDT 24
Peak memory 247216 kb
Host smart-f2462545-d297-4479-bdf2-cf1bd4288e57
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387053416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_state_post_trans.2387053416
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.912711023
Short name T480
Test name
Test status
Simulation time 98377326 ps
CPU time 4.5 seconds
Started Jun 05 05:20:07 PM PDT 24
Finished Jun 05 05:20:12 PM PDT 24
Peak memory 217984 kb
Host smart-adff68e6-a3b9-456b-9b50-0142ea755e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912711023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.912711023
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.4104308716
Short name T756
Test name
Test status
Simulation time 648116686 ps
CPU time 21.85 seconds
Started Jun 05 05:20:13 PM PDT 24
Finished Jun 05 05:20:36 PM PDT 24
Peak memory 214440 kb
Host smart-1f431c41-f83f-4055-a4e3-96604898952f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104308716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.4104308716
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.3964423723
Short name T91
Test name
Test status
Simulation time 185506003 ps
CPU time 9.68 seconds
Started Jun 05 05:20:06 PM PDT 24
Finished Jun 05 05:20:16 PM PDT 24
Peak memory 218152 kb
Host smart-ec0daef2-8068-461e-baf6-d3112c9f6ac4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964423723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.3964423723
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.3805980473
Short name T771
Test name
Test status
Simulation time 2060806447 ps
CPU time 21.14 seconds
Started Jun 05 05:20:05 PM PDT 24
Finished Jun 05 05:20:27 PM PDT 24
Peak memory 226032 kb
Host smart-645981ba-6cdd-4f41-883c-15f71ee8151d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805980473 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_di
gest.3805980473
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.1183515567
Short name T292
Test name
Test status
Simulation time 2071759426 ps
CPU time 9.01 seconds
Started Jun 05 05:20:13 PM PDT 24
Finished Jun 05 05:20:23 PM PDT 24
Peak memory 217916 kb
Host smart-2c287bf5-7cef-46fe-8645-b6344de730e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183515567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.1
183515567
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.4026649695
Short name T781
Test name
Test status
Simulation time 890739812 ps
CPU time 9.72 seconds
Started Jun 05 05:20:04 PM PDT 24
Finished Jun 05 05:20:14 PM PDT 24
Peak memory 226080 kb
Host smart-f04499ca-5021-4a48-be8e-090c74f3c510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026649695 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.4026649695
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.2360662144
Short name T73
Test name
Test status
Simulation time 448255299 ps
CPU time 7.81 seconds
Started Jun 05 05:19:58 PM PDT 24
Finished Jun 05 05:20:07 PM PDT 24
Peak memory 217708 kb
Host smart-26fb68f7-b1a2-4949-95aa-cd1085734bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360662144 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.2360662144
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.2537385156
Short name T718
Test name
Test status
Simulation time 291190145 ps
CPU time 22.17 seconds
Started Jun 05 05:19:57 PM PDT 24
Finished Jun 05 05:20:20 PM PDT 24
Peak memory 251004 kb
Host smart-52b46974-f88a-4815-89c8-eebaafb07510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537385156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.2537385156
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.689496811
Short name T774
Test name
Test status
Simulation time 358892683 ps
CPU time 7.27 seconds
Started Jun 05 05:19:58 PM PDT 24
Finished Jun 05 05:20:06 PM PDT 24
Peak memory 250332 kb
Host smart-6bb17916-71ce-49cc-baa8-36c0af7eb7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689496811 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.689496811
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.3559832957
Short name T101
Test name
Test status
Simulation time 4666445298 ps
CPU time 102.06 seconds
Started Jun 05 05:20:05 PM PDT 24
Finished Jun 05 05:21:49 PM PDT 24
Peak memory 276928 kb
Host smart-82a258ec-5b5a-449d-9dc5-80394c26941f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559832957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
8.lc_ctrl_stress_all.3559832957
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3615123049
Short name T716
Test name
Test status
Simulation time 31820105 ps
CPU time 0.92 seconds
Started Jun 05 05:19:58 PM PDT 24
Finished Jun 05 05:20:00 PM PDT 24
Peak memory 211436 kb
Host smart-01357e2a-029a-487c-860a-a722f3be3850
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615123049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.3615123049
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.228191019
Short name T205
Test name
Test status
Simulation time 58551480 ps
CPU time 0.9 seconds
Started Jun 05 05:20:18 PM PDT 24
Finished Jun 05 05:20:20 PM PDT 24
Peak memory 209412 kb
Host smart-8aa8a865-2b64-4a78-b5a2-f420d0e77835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228191019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.228191019
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1036806516
Short name T281
Test name
Test status
Simulation time 2210783693 ps
CPU time 16.12 seconds
Started Jun 05 05:20:06 PM PDT 24
Finished Jun 05 05:20:23 PM PDT 24
Peak memory 218112 kb
Host smart-03de1e35-8924-422e-b135-1939dde111ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036806516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1036806516
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.2356942567
Short name T699
Test name
Test status
Simulation time 676843668 ps
CPU time 4.89 seconds
Started Jun 05 05:20:06 PM PDT 24
Finished Jun 05 05:20:12 PM PDT 24
Peak memory 209528 kb
Host smart-77d5a6bb-9f15-4e7d-9804-2874cd2bcd01
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356942567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.2356942567
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.2726245560
Short name T285
Test name
Test status
Simulation time 5402255130 ps
CPU time 28.35 seconds
Started Jun 05 05:20:04 PM PDT 24
Finished Jun 05 05:20:33 PM PDT 24
Peak memory 218928 kb
Host smart-f752ead3-10f1-4370-ab12-0fd1cf6daf33
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726245560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.2726245560
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.2749372771
Short name T445
Test name
Test status
Simulation time 1573227312 ps
CPU time 4.12 seconds
Started Jun 05 05:20:18 PM PDT 24
Finished Jun 05 05:20:23 PM PDT 24
Peak memory 217876 kb
Host smart-e007f4cd-7e5c-4a90-8edf-9c164185ea30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749372771 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.2
749372771
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.1098019053
Short name T661
Test name
Test status
Simulation time 3711228852 ps
CPU time 11.91 seconds
Started Jun 05 05:20:04 PM PDT 24
Finished Jun 05 05:20:17 PM PDT 24
Peak memory 218000 kb
Host smart-ac2becbe-01b5-4ee4-ad2e-cc67ed60680b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098019053 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.1098019053
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.445755046
Short name T95
Test name
Test status
Simulation time 3576839385 ps
CPU time 19.94 seconds
Started Jun 05 05:20:17 PM PDT 24
Finished Jun 05 05:20:38 PM PDT 24
Peak memory 217668 kb
Host smart-9f66b245-b390-4a81-a558-ca8f8216064a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445755046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_j
tag_regwen_during_op.445755046
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.1748985336
Short name T201
Test name
Test status
Simulation time 1047809960 ps
CPU time 4 seconds
Started Jun 05 05:20:05 PM PDT 24
Finished Jun 05 05:20:10 PM PDT 24
Peak memory 217592 kb
Host smart-9a1d68ea-2b40-4c6a-940c-c6e4eae3a063
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748985336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
1748985336
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3258026250
Short name T513
Test name
Test status
Simulation time 19625721288 ps
CPU time 151.48 seconds
Started Jun 05 05:20:05 PM PDT 24
Finished Jun 05 05:22:37 PM PDT 24
Peak memory 283656 kb
Host smart-47e8cad8-ee3a-4a01-9b8e-4487a6f08bac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258026250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3258026250
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.4193566941
Short name T619
Test name
Test status
Simulation time 1731636233 ps
CPU time 19.25 seconds
Started Jun 05 05:20:05 PM PDT 24
Finished Jun 05 05:20:26 PM PDT 24
Peak memory 250932 kb
Host smart-3d633444-3d0f-4f15-82c0-5693cad326a4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193566941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.4193566941
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.4135024254
Short name T516
Test name
Test status
Simulation time 253434324 ps
CPU time 2.9 seconds
Started Jun 05 05:20:05 PM PDT 24
Finished Jun 05 05:20:09 PM PDT 24
Peak memory 217992 kb
Host smart-9fbca396-52b4-497a-8130-b3769dbac644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135024254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.4135024254
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1191749484
Short name T556
Test name
Test status
Simulation time 1713423606 ps
CPU time 7.85 seconds
Started Jun 05 05:20:05 PM PDT 24
Finished Jun 05 05:20:14 PM PDT 24
Peak memory 218184 kb
Host smart-53bda602-46de-4719-b212-494e58ab26e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191749484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1191749484
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.3682633973
Short name T311
Test name
Test status
Simulation time 1809522942 ps
CPU time 17.91 seconds
Started Jun 05 05:20:20 PM PDT 24
Finished Jun 05 05:20:38 PM PDT 24
Peak memory 218952 kb
Host smart-715fbcdf-171e-4deb-a351-4a92b421e4ad
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682633973 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3682633973
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.3734575316
Short name T154
Test name
Test status
Simulation time 1306327354 ps
CPU time 13.88 seconds
Started Jun 05 05:20:17 PM PDT 24
Finished Jun 05 05:20:33 PM PDT 24
Peak memory 226044 kb
Host smart-b7d91a97-064a-45b5-86c4-744d58524ea1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734575316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.3734575316
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.3173691625
Short name T86
Test name
Test status
Simulation time 376706985 ps
CPU time 10.48 seconds
Started Jun 05 05:20:18 PM PDT 24
Finished Jun 05 05:20:30 PM PDT 24
Peak memory 218008 kb
Host smart-bea4af9b-2c65-4c15-8acf-b8f71c06e172
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173691625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.3
173691625
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1158220179
Short name T42
Test name
Test status
Simulation time 1529504106 ps
CPU time 9.9 seconds
Started Jun 05 05:20:06 PM PDT 24
Finished Jun 05 05:20:17 PM PDT 24
Peak memory 225204 kb
Host smart-ca9f741b-115b-4af7-8a78-b45bacbfc41e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158220179 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1158220179
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.3192430550
Short name T215
Test name
Test status
Simulation time 838279347 ps
CPU time 3.44 seconds
Started Jun 05 05:20:05 PM PDT 24
Finished Jun 05 05:20:09 PM PDT 24
Peak memory 217704 kb
Host smart-caf4513e-510c-436f-a9fe-853e0347de95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192430550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.3192430550
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.393308216
Short name T218
Test name
Test status
Simulation time 390909920 ps
CPU time 20.59 seconds
Started Jun 05 05:20:05 PM PDT 24
Finished Jun 05 05:20:27 PM PDT 24
Peak memory 250764 kb
Host smart-ea12bf00-07a0-46a4-8fe2-7e092954b498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393308216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.393308216
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.3991096092
Short name T213
Test name
Test status
Simulation time 182530733 ps
CPU time 7.35 seconds
Started Jun 05 05:20:04 PM PDT 24
Finished Jun 05 05:20:12 PM PDT 24
Peak memory 245400 kb
Host smart-370990a8-7a95-4461-adea-6822f35a7584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991096092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.3991096092
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.2616231712
Short name T380
Test name
Test status
Simulation time 51734662178 ps
CPU time 52.91 seconds
Started Jun 05 05:20:18 PM PDT 24
Finished Jun 05 05:21:12 PM PDT 24
Peak memory 226136 kb
Host smart-bab8e31d-0087-4b0d-9489-c631713f8547
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616231712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.2616231712
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.1421952212
Short name T140
Test name
Test status
Simulation time 13286913805 ps
CPU time 247.26 seconds
Started Jun 05 05:20:21 PM PDT 24
Finished Jun 05 05:24:29 PM PDT 24
Peak memory 251104 kb
Host smart-3b01dd9f-ba4e-403d-8d86-eac280478fe6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1421952212 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.1421952212
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3139108240
Short name T183
Test name
Test status
Simulation time 13332108 ps
CPU time 0.91 seconds
Started Jun 05 05:20:05 PM PDT 24
Finished Jun 05 05:20:07 PM PDT 24
Peak memory 211472 kb
Host smart-c1fa4b49-14db-4899-82c1-6dd833381cd9
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139108240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ct
rl_volatile_unlock_smoke.3139108240
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%