Summary for Variable clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47420 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
83 |
auto[1] |
1547 |
1 |
|
|
T15 |
9 |
|
T16 |
28 |
|
T17 |
9 |
Summary for Variable clk_byp_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for clk_byp_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48186 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
83 |
auto[1] |
781 |
1 |
|
|
T14 |
18 |
|
T22 |
17 |
|
T24 |
18 |
Summary for Variable count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47263 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
77 |
auto[1] |
1704 |
1 |
|
|
T4 |
6 |
|
T6 |
7 |
|
T55 |
1 |
Summary for Variable count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47269 |
1 |
|
|
T1 |
9 |
|
T2 |
86 |
|
T4 |
72 |
auto[1] |
1698 |
1 |
|
|
T1 |
2 |
|
T4 |
11 |
|
T6 |
8 |
Summary for Variable count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for count_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47318 |
1 |
|
|
T1 |
10 |
|
T2 |
86 |
|
T4 |
75 |
auto[1] |
1649 |
1 |
|
|
T1 |
1 |
|
T4 |
8 |
|
T6 |
4 |
Summary for Variable err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
2 |
0 |
2 |
100.00 |
User Defined Bins for err_inj_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
err_inj |
44685 |
1 |
|
|
T1 |
5 |
|
T2 |
86 |
|
T4 |
83 |
no_err_inj |
4282 |
1 |
|
|
T1 |
6 |
|
T27 |
9 |
|
T55 |
5 |
Summary for Variable flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_error_rsp_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47372 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
83 |
auto[1] |
1595 |
1 |
|
|
T15 |
9 |
|
T16 |
33 |
|
T17 |
9 |
Summary for Variable flash_rma_rsp_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for flash_rma_rsp_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48264 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
83 |
auto[1] |
703 |
1 |
|
|
T14 |
21 |
|
T22 |
16 |
|
T24 |
16 |
Summary for Variable jtag_csr_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for jtag_csr_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
35917 |
1 |
|
|
T2 |
86 |
|
T4 |
83 |
|
T13 |
91 |
auto[1] |
13050 |
1 |
|
|
T1 |
11 |
|
T5 |
6 |
|
T6 |
55 |
Summary for Variable kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47234 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
78 |
auto[1] |
1733 |
1 |
|
|
T4 |
5 |
|
T6 |
1 |
|
T55 |
2 |
Summary for Variable lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for lc_fsm_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47328 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
67 |
auto[1] |
1639 |
1 |
|
|
T4 |
16 |
|
T6 |
6 |
|
T27 |
2 |
Summary for Variable otp_lc_data_i_valid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_lc_data_i_valid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47273 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
69 |
auto[1] |
1694 |
1 |
|
|
T4 |
14 |
|
T6 |
7 |
|
T27 |
1 |
Summary for Variable otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_partition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47433 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
83 |
auto[1] |
1534 |
1 |
|
|
T15 |
11 |
|
T16 |
28 |
|
T17 |
9 |
Summary for Variable otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_prog_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47028 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
83 |
auto[1] |
1939 |
1 |
|
|
T5 |
6 |
|
T15 |
16 |
|
T63 |
17 |
Summary for Variable otp_rma_token_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_rma_token_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48199 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
83 |
auto[1] |
768 |
1 |
|
|
T14 |
19 |
|
T22 |
15 |
|
T24 |
15 |
Summary for Variable otp_secrets_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_secrets_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48203 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
83 |
auto[1] |
764 |
1 |
|
|
T14 |
23 |
|
T22 |
18 |
|
T24 |
24 |
Summary for Variable otp_test_tokens_valid_mubi_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for otp_test_tokens_valid_mubi_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48213 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
83 |
auto[1] |
754 |
1 |
|
|
T14 |
17 |
|
T22 |
9 |
|
T24 |
21 |
Summary for Variable post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for post_trans_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
46693 |
1 |
|
|
T2 |
86 |
|
T4 |
83 |
|
T13 |
91 |
auto[1] |
2274 |
1 |
|
|
T1 |
11 |
|
T27 |
15 |
|
T55 |
11 |
Summary for Variable security_escalation_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for security_escalation_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
45340 |
1 |
|
|
T1 |
11 |
|
T4 |
83 |
|
T5 |
6 |
auto[1] |
3627 |
1 |
|
|
T2 |
86 |
|
T13 |
91 |
|
T26 |
87 |
Summary for Variable state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_backdoor_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47239 |
1 |
|
|
T1 |
10 |
|
T2 |
86 |
|
T4 |
81 |
auto[1] |
1728 |
1 |
|
|
T1 |
1 |
|
T4 |
2 |
|
T6 |
9 |
Summary for Variable state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47213 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
70 |
auto[1] |
1754 |
1 |
|
|
T4 |
13 |
|
T6 |
5 |
|
T27 |
1 |
Summary for Variable state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for state_illegal_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47265 |
1 |
|
|
T1 |
10 |
|
T2 |
86 |
|
T4 |
75 |
auto[1] |
1702 |
1 |
|
|
T1 |
1 |
|
T4 |
8 |
|
T6 |
8 |
Summary for Variable token_invalid_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_invalid_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47467 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
83 |
auto[1] |
1500 |
1 |
|
|
T15 |
7 |
|
T16 |
27 |
|
T17 |
8 |
Summary for Variable token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mismatch_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
43325 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
83 |
auto[1] |
5642 |
1 |
|
|
T21 |
73 |
|
T15 |
5 |
|
T16 |
29 |
Summary for Variable token_mux_ctrl_redun_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_mux_ctrl_redun_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
45416 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
83 |
auto[1] |
3551 |
1 |
|
|
T18 |
56 |
|
T23 |
96 |
|
T56 |
65 |
Summary for Variable token_mux_digest_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
1 |
1 |
50.00 |
Automatically Generated Bins for token_mux_digest_err_cp
Uncovered bins
NAME | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
0 |
1 |
1 |
|
Covered bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
48967 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
83 |
Summary for Variable token_response_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for token_response_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47363 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
83 |
auto[1] |
1604 |
1 |
|
|
T15 |
9 |
|
T16 |
26 |
|
T17 |
6 |
Summary for Variable transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_count_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47409 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
83 |
auto[1] |
1558 |
1 |
|
|
T15 |
6 |
|
T16 |
30 |
|
T17 |
4 |
Summary for Variable transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for transition_err_cp
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
47450 |
1 |
|
|
T1 |
11 |
|
T2 |
86 |
|
T4 |
83 |
auto[1] |
1517 |
1 |
|
|
T15 |
6 |
|
T16 |
38 |
|
T17 |
10 |
Summary for Cross post_trans_err_inj_xp
Samples crossed: post_trans_err_cp err_inj_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_err_inj_xp
Bins
post_trans_err_cp | err_inj_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
err_inj |
43564 |
1 |
|
|
T2 |
86 |
|
T4 |
83 |
|
T13 |
91 |
auto[0] |
no_err_inj |
3129 |
1 |
|
|
T15 |
24 |
|
T19 |
20 |
|
T16 |
6 |
auto[1] |
err_inj |
1121 |
1 |
|
|
T1 |
5 |
|
T27 |
6 |
|
T55 |
6 |
auto[1] |
no_err_inj |
1153 |
1 |
|
|
T1 |
6 |
|
T27 |
9 |
|
T55 |
5 |
Summary for Cross post_trans_state_err_xp
Samples crossed: post_trans_err_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_err_xp
Bins
post_trans_err_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45063 |
1 |
|
|
T2 |
86 |
|
T4 |
70 |
|
T13 |
91 |
auto[0] |
auto[1] |
1630 |
1 |
|
|
T4 |
13 |
|
T6 |
5 |
|
T15 |
10 |
auto[1] |
auto[0] |
2150 |
1 |
|
|
T1 |
11 |
|
T27 |
14 |
|
T55 |
9 |
auto[1] |
auto[1] |
124 |
1 |
|
|
T27 |
1 |
|
T55 |
2 |
|
T16 |
2 |
Summary for Cross post_trans_lc_fsm_backdoor_err_xp
Samples crossed: post_trans_err_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_lc_fsm_backdoor_err_xp
Bins
post_trans_err_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45182 |
1 |
|
|
T2 |
86 |
|
T4 |
67 |
|
T13 |
91 |
auto[0] |
auto[1] |
1511 |
1 |
|
|
T4 |
16 |
|
T6 |
6 |
|
T15 |
7 |
auto[1] |
auto[0] |
2146 |
1 |
|
|
T1 |
11 |
|
T27 |
13 |
|
T55 |
11 |
auto[1] |
auto[1] |
128 |
1 |
|
|
T27 |
2 |
|
T16 |
1 |
|
T206 |
1 |
Summary for Cross post_trans_state_illegal_err_xp
Samples crossed: post_trans_err_cp state_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_state_illegal_err_xp
Bins
post_trans_err_cp | state_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45100 |
1 |
|
|
T2 |
86 |
|
T4 |
75 |
|
T13 |
91 |
auto[0] |
auto[1] |
1593 |
1 |
|
|
T4 |
8 |
|
T6 |
8 |
|
T15 |
4 |
auto[1] |
auto[0] |
2165 |
1 |
|
|
T1 |
10 |
|
T27 |
15 |
|
T55 |
11 |
auto[1] |
auto[1] |
109 |
1 |
|
|
T1 |
1 |
|
T16 |
4 |
|
T70 |
3 |
Summary for Cross post_trans_count_err_xp
Samples crossed: post_trans_err_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_err_xp
Bins
post_trans_err_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45136 |
1 |
|
|
T2 |
86 |
|
T4 |
72 |
|
T13 |
91 |
auto[0] |
auto[1] |
1557 |
1 |
|
|
T4 |
11 |
|
T6 |
8 |
|
T15 |
6 |
auto[1] |
auto[0] |
2133 |
1 |
|
|
T1 |
9 |
|
T27 |
14 |
|
T55 |
11 |
auto[1] |
auto[1] |
141 |
1 |
|
|
T1 |
2 |
|
T27 |
1 |
|
T16 |
2 |
Summary for Cross post_trans_count_illegal_err_xp
Samples crossed: post_trans_err_cp count_illegal_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_illegal_err_xp
Bins
post_trans_err_cp | count_illegal_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45142 |
1 |
|
|
T2 |
86 |
|
T4 |
75 |
|
T13 |
91 |
auto[0] |
auto[1] |
1551 |
1 |
|
|
T4 |
8 |
|
T6 |
4 |
|
T15 |
8 |
auto[1] |
auto[0] |
2176 |
1 |
|
|
T1 |
10 |
|
T27 |
15 |
|
T55 |
11 |
auto[1] |
auto[1] |
98 |
1 |
|
|
T1 |
1 |
|
T70 |
1 |
|
T174 |
1 |
Summary for Cross post_trans_count_backdoor_err_xp
Samples crossed: post_trans_err_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for post_trans_count_backdoor_err_xp
Bins
post_trans_err_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
45116 |
1 |
|
|
T2 |
86 |
|
T4 |
77 |
|
T13 |
91 |
auto[0] |
auto[1] |
1577 |
1 |
|
|
T4 |
6 |
|
T6 |
7 |
|
T15 |
7 |
auto[1] |
auto[0] |
2147 |
1 |
|
|
T1 |
11 |
|
T27 |
15 |
|
T55 |
10 |
auto[1] |
auto[1] |
127 |
1 |
|
|
T55 |
1 |
|
T16 |
4 |
|
T70 |
2 |
Summary for Cross jtag_clk_byp_error_rsp_xp
Samples crossed: jtag_csr_cp clk_byp_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_clk_byp_error_rsp_xp
Bins
jtag_csr_cp | clk_byp_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34903 |
1 |
|
|
T2 |
86 |
|
T4 |
83 |
|
T13 |
91 |
auto[0] |
auto[1] |
1014 |
1 |
|
|
T15 |
9 |
|
T16 |
21 |
|
T17 |
9 |
auto[1] |
auto[0] |
12517 |
1 |
|
|
T1 |
11 |
|
T5 |
6 |
|
T6 |
55 |
auto[1] |
auto[1] |
533 |
1 |
|
|
T16 |
7 |
|
T89 |
10 |
|
T49 |
25 |
Summary for Cross jtag_flash_rma_error_rsp_xp
Samples crossed: jtag_csr_cp flash_rma_error_rsp_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_flash_rma_error_rsp_xp
Bins
jtag_csr_cp | flash_rma_error_rsp_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34877 |
1 |
|
|
T2 |
86 |
|
T4 |
83 |
|
T13 |
91 |
auto[0] |
auto[1] |
1040 |
1 |
|
|
T15 |
9 |
|
T16 |
26 |
|
T17 |
9 |
auto[1] |
auto[0] |
12495 |
1 |
|
|
T1 |
11 |
|
T5 |
6 |
|
T6 |
55 |
auto[1] |
auto[1] |
555 |
1 |
|
|
T16 |
7 |
|
T89 |
14 |
|
T49 |
25 |
Summary for Cross jtag_otp_prog_err_xp
Samples crossed: jtag_csr_cp otp_prog_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_prog_err_xp
Bins
jtag_csr_cp | otp_prog_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34761 |
1 |
|
|
T2 |
86 |
|
T4 |
83 |
|
T13 |
91 |
auto[0] |
auto[1] |
1156 |
1 |
|
|
T63 |
17 |
|
T64 |
15 |
|
T65 |
9 |
auto[1] |
auto[0] |
12267 |
1 |
|
|
T1 |
11 |
|
T6 |
55 |
|
T27 |
15 |
auto[1] |
auto[1] |
783 |
1 |
|
|
T5 |
6 |
|
T15 |
16 |
|
T16 |
19 |
Summary for Cross jtag_otp_partition_err_xp
Samples crossed: jtag_csr_cp otp_partition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_otp_partition_err_xp
Bins
jtag_csr_cp | otp_partition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34951 |
1 |
|
|
T2 |
86 |
|
T4 |
83 |
|
T13 |
91 |
auto[0] |
auto[1] |
966 |
1 |
|
|
T15 |
11 |
|
T16 |
21 |
|
T17 |
9 |
auto[1] |
auto[0] |
12482 |
1 |
|
|
T1 |
11 |
|
T5 |
6 |
|
T6 |
55 |
auto[1] |
auto[1] |
568 |
1 |
|
|
T16 |
7 |
|
T89 |
8 |
|
T49 |
23 |
Summary for Cross jtag_token_mismatch_err_xp
Samples crossed: jtag_csr_cp token_mismatch_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_token_mismatch_err_xp
Bins
jtag_csr_cp | token_mismatch_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
30854 |
1 |
|
|
T2 |
86 |
|
T4 |
83 |
|
T13 |
91 |
auto[0] |
auto[1] |
5063 |
1 |
|
|
T21 |
73 |
|
T15 |
5 |
|
T16 |
22 |
auto[1] |
auto[0] |
12471 |
1 |
|
|
T1 |
11 |
|
T5 |
6 |
|
T6 |
55 |
auto[1] |
auto[1] |
579 |
1 |
|
|
T16 |
7 |
|
T89 |
17 |
|
T49 |
25 |
Summary for Cross jtag_state_err_xp
Samples crossed: jtag_csr_cp state_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_err_xp
Bins
jtag_csr_cp | state_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34867 |
1 |
|
|
T2 |
86 |
|
T4 |
70 |
|
T13 |
91 |
auto[0] |
auto[1] |
1050 |
1 |
|
|
T4 |
13 |
|
T55 |
2 |
|
T15 |
10 |
auto[1] |
auto[0] |
12346 |
1 |
|
|
T1 |
11 |
|
T5 |
6 |
|
T6 |
50 |
auto[1] |
auto[1] |
704 |
1 |
|
|
T6 |
5 |
|
T27 |
1 |
|
T16 |
13 |
Summary for Cross jtag_state_backdoor_err_xp
Samples crossed: jtag_csr_cp state_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_state_backdoor_err_xp
Bins
jtag_csr_cp | state_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34854 |
1 |
|
|
T2 |
86 |
|
T4 |
81 |
|
T13 |
91 |
auto[0] |
auto[1] |
1063 |
1 |
|
|
T4 |
2 |
|
T15 |
8 |
|
T16 |
31 |
auto[1] |
auto[0] |
12385 |
1 |
|
|
T1 |
10 |
|
T5 |
6 |
|
T6 |
46 |
auto[1] |
auto[1] |
665 |
1 |
|
|
T1 |
1 |
|
T6 |
9 |
|
T27 |
1 |
Summary for Cross jtag_lc_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp lc_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_lc_fsm_backdoor_err_xp
Bins
jtag_csr_cp | lc_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34925 |
1 |
|
|
T2 |
86 |
|
T4 |
67 |
|
T13 |
91 |
auto[0] |
auto[1] |
992 |
1 |
|
|
T4 |
16 |
|
T15 |
7 |
|
T16 |
14 |
auto[1] |
auto[0] |
12403 |
1 |
|
|
T1 |
11 |
|
T5 |
6 |
|
T6 |
49 |
auto[1] |
auto[1] |
647 |
1 |
|
|
T6 |
6 |
|
T27 |
2 |
|
T16 |
12 |
Summary for Cross jtag_kmac_fsm_backdoor_err_xp
Samples crossed: jtag_csr_cp kmac_fsm_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_kmac_fsm_backdoor_err_xp
Bins
jtag_csr_cp | kmac_fsm_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34879 |
1 |
|
|
T2 |
86 |
|
T4 |
78 |
|
T13 |
91 |
auto[0] |
auto[1] |
1038 |
1 |
|
|
T4 |
5 |
|
T55 |
2 |
|
T15 |
4 |
auto[1] |
auto[0] |
12355 |
1 |
|
|
T1 |
11 |
|
T5 |
6 |
|
T6 |
54 |
auto[1] |
auto[1] |
695 |
1 |
|
|
T6 |
1 |
|
T16 |
5 |
|
T28 |
10 |
Summary for Cross jtag_count_err_xp
Samples crossed: jtag_csr_cp count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_err_xp
Bins
jtag_csr_cp | count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34862 |
1 |
|
|
T2 |
86 |
|
T4 |
72 |
|
T13 |
91 |
auto[0] |
auto[1] |
1055 |
1 |
|
|
T4 |
11 |
|
T15 |
6 |
|
T16 |
16 |
auto[1] |
auto[0] |
12407 |
1 |
|
|
T1 |
9 |
|
T5 |
6 |
|
T6 |
47 |
auto[1] |
auto[1] |
643 |
1 |
|
|
T1 |
2 |
|
T6 |
8 |
|
T27 |
1 |
Summary for Cross jtag_count_backdoor_err_xp
Samples crossed: jtag_csr_cp count_backdoor_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_count_backdoor_err_xp
Bins
jtag_csr_cp | count_backdoor_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34889 |
1 |
|
|
T2 |
86 |
|
T4 |
77 |
|
T13 |
91 |
auto[0] |
auto[1] |
1028 |
1 |
|
|
T4 |
6 |
|
T55 |
1 |
|
T15 |
7 |
auto[1] |
auto[0] |
12374 |
1 |
|
|
T1 |
11 |
|
T5 |
6 |
|
T6 |
48 |
auto[1] |
auto[1] |
676 |
1 |
|
|
T6 |
7 |
|
T16 |
6 |
|
T28 |
10 |
Summary for Cross jtag_transition_err_xp
Samples crossed: jtag_csr_cp transition_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_err_xp
Bins
jtag_csr_cp | transition_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34926 |
1 |
|
|
T2 |
86 |
|
T4 |
83 |
|
T13 |
91 |
auto[0] |
auto[1] |
991 |
1 |
|
|
T15 |
6 |
|
T16 |
27 |
|
T17 |
10 |
auto[1] |
auto[0] |
12524 |
1 |
|
|
T1 |
11 |
|
T5 |
6 |
|
T6 |
55 |
auto[1] |
auto[1] |
526 |
1 |
|
|
T16 |
11 |
|
T89 |
6 |
|
T49 |
23 |
Summary for Cross jtag_transition_count_err_xp
Samples crossed: jtag_csr_cp transition_count_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_transition_count_err_xp
Bins
jtag_csr_cp | transition_count_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34911 |
1 |
|
|
T2 |
86 |
|
T4 |
83 |
|
T13 |
91 |
auto[0] |
auto[1] |
1006 |
1 |
|
|
T15 |
6 |
|
T16 |
24 |
|
T17 |
4 |
auto[1] |
auto[0] |
12498 |
1 |
|
|
T1 |
11 |
|
T5 |
6 |
|
T6 |
55 |
auto[1] |
auto[1] |
552 |
1 |
|
|
T16 |
6 |
|
T89 |
11 |
|
T49 |
26 |
Summary for Cross jtag_post_trans_err_xp
Samples crossed: jtag_csr_cp post_trans_err_cp
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for jtag_post_trans_err_xp
Bins
jtag_csr_cp | post_trans_err_cp | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
34604 |
1 |
|
|
T2 |
86 |
|
T4 |
83 |
|
T13 |
91 |
auto[0] |
auto[1] |
1313 |
1 |
|
|
T55 |
11 |
|
T16 |
13 |
|
T70 |
12 |
auto[1] |
auto[0] |
12089 |
1 |
|
|
T5 |
6 |
|
T6 |
55 |
|
T15 |
24 |
auto[1] |
auto[1] |
961 |
1 |
|
|
T1 |
11 |
|
T27 |
15 |
|
T16 |
15 |