Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

89410533

1

T1

85007

T2

16114

T3

1033

auto[1]

1291602

1

T1

196

T2

9121

T4

3465

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

89441298

1

T1

85007

T2

15593

T3

1033

auto[1]

1260837

1

T1

196

T2

9642

T4

2574

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	6643618	1			T1	1014		T2	7643		T3	116
auto[IdleSt]	18931148	1			T1	23143		T2	2181		T3	917
auto[ClkMuxSt]	32549	1			T1	6		T2	77		T12	1
auto[CntIncrSt]	32278	1			T1	6		T2	75		T12	1
auto[CntProgSt]	1245075	1			T1	12		T2	706		T12	203
auto[TransCheckSt]	25363	1			T1	6		T2	37		T12	1
auto[TokenHashSt]	36374530	1			T1	1970		T2	328		T12	12
auto[FlashRmaSt]	26171	1			T1	13		T2	61		T13	88
auto[TokenCheck0St]	11479	1			T1	6		T2	25		T13	36
auto[TokenCheck1St]	8507	1			T1	6		T2	25		T13	36
auto[TransProgSt]	327565	1			T1	12		T2	71		T13	78
auto[PostTransSt]	10370692	1			T1	29174		T2	3		T12	853
auto[ScrapSt]	126115	1			T2	6		T13	6		T26	3
auto[EscalateSt]	6016405	1			T1	14651		T2	13997		T4	8909
auto[InvalidSt]	10528940	1			T1	15184		T4	11362		T14	3303

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1700	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	10528940	1			T1	15184		T4	11362		T14	3303
EscalateSt	6016405	1			T1	14651		T2	13997		T4	8909
ScrapSt	126115	1			T2	6		T13	6		T26	3
PostTransSt	10370692	1			T1	29174		T2	3		T12	853
TransProgSt	327565	1			T1	12		T2	71		T13	78
TokenCheck1St	8507	1			T1	6		T2	25		T13	36
TokenCheck0St	11479	1			T1	6		T2	25		T13	36
FlashRmaSt	26171	1			T1	13		T2	61		T13	88
TokenHashSt	36374530	1			T1	1970		T2	328		T12	12
TransCheckSt	25363	1			T1	6		T2	37		T12	1
CntProgSt	1245075	1			T1	12		T2	706		T12	203
CntIncrSt	32278	1			T1	6		T2	75		T12	1
ClkMuxSt	32549	1			T1	6		T2	77		T12	1
IdleSt	18931148	1			T1	23143		T2	2181		T3	917
ResetSt	6643618	1			T1	1014		T2	7643		T3	116
arcs[ResetSt=>IdleSt]	49228	1			T1	12		T2	80		T3	1
arcs[IdleSt=>ScrapSt]	277	1			T2	2		T13	2		T26	1
arcs[IdleSt=>ClkMuxSt]	32362	1			T1	6		T2	77		T12	1
arcs[ClkMuxSt=>CntIncrSt]	32278	1			T1	6		T2	75		T12	1
arcs[CntIncrSt=>PostTransSt]	1558	1			T15	6		T16	30		T17	4
arcs[CntIncrSt=>CntProgSt]	30658	1			T1	6		T2	73		T12	1
arcs[CntProgSt=>PostTransSt]	4231	1			T5	6		T14	18		T22	17
arcs[CntProgSt=>TransCheckSt]	25363	1			T1	6		T2	37		T12	1
arcs[TransCheckSt=>PostTransSt]	3260	1			T18	34		T23	44		T15	6
arcs[TransCheckSt=>TokenHashSt]	21979	1			T1	6		T2	35		T12	1
arcs[TokenHashSt=>PostTransSt]	9730	1			T12	1		T14	11		T18	6
arcs[TokenHashSt=>FlashRmaSt]	11567	1			T1	6		T2	29		T13	37
arcs[FlashRmaSt=>TokenCheck0St]	11479	1			T1	6		T2	25		T13	36
arcs[TokenCheck0St=>PostTransSt]	2946	1			T14	19		T18	8		T22	13
arcs[TokenCheck0St=>TokenCheck1St]	8507	1			T1	6		T2	25		T13	36
arcs[TokenCheck1St=>PostTransSt]	633	1			T14	1		T18	8		T23	9
arcs[TransProgSt=>PostTransSt]	7046	1			T1	6		T2	1		T13	1
arcs[IdleSt=>EscalateSt]	150	1			T13	4		T57	3		T42	5
arcs[ClkMuxSt=>EscalateSt]	84	1			T2	2		T13	2		T26	1
arcs[CntIncrSt=>EscalateSt]	62	1			T2	2		T13	1		T26	1
arcs[CntProgSt=>EscalateSt]	1064	1			T2	36		T13	27		T26	19
arcs[TransCheckSt=>EscalateSt]	124	1			T2	2		T13	1		T26	4
arcs[TokenHashSt=>EscalateSt]	682	1			T2	6		T13	13		T26	24
arcs[FlashRmaSt=>EscalateSt]	88	1			T2	4		T13	1		T26	1
arcs[TokenCheck0St=>EscalateSt]	26	1			T57	1		T42	1		T60	1
arcs[TokenCheck1St=>EscalateSt]	152	1			T2	5		T13	8		T26	6
arcs[TransProgSt=>EscalateSt]	676	1			T2	19		T13	27		T26	17
arcs[PostTransSt=>EscalateSt]	4468	1			T2	1		T13	1		T5	6
arcs[InvalidSt=>EscalateSt]	12682	1			T1	4		T4	61		T14	23

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6643434	1			T1	1014		T2	7640		T3	116
auto[0]	auto[IdleSt]	18931059	1			T1	23143		T2	2181		T3	917
auto[0]	auto[ClkMuxSt]	32496	1			T1	6		T2	76		T12	1
auto[0]	auto[CntIncrSt]	32237	1			T1	6		T2	73		T12	1
auto[0]	auto[CntProgSt]	1244369	1			T1	12		T2	680		T12	203
auto[0]	auto[TransCheckSt]	25283	1			T1	6		T2	35		T12	1
auto[0]	auto[TokenHashSt]	36374051	1			T1	1970		T2	324		T12	12
auto[0]	auto[FlashRmaSt]	26111	1			T1	13		T2	59		T13	87
auto[0]	auto[TokenCheck0St]	11458	1			T1	6		T2	25		T13	36
auto[0]	auto[TokenCheck1St]	8409	1			T1	6		T2	22		T13	34
auto[0]	auto[TransProgSt]	327124	1			T1	12		T2	60		T13	62
auto[0]	auto[PostTransSt]	10368413	1			T1	29174		T2	2		T12	853
auto[0]	auto[ScrapSt]	126068	1			T2	4		T13	4		T26	2
auto[0]	auto[EscalateSt]	4735808	1			T1	14457		T2	4933		T4	5479
auto[0]	auto[InvalidSt]	10522513	1			T1	15182		T4	11327		T14	3290
auto[1]	auto[ResetSt]	184	1			T2	3		T13	3		T26	6
auto[1]	auto[IdleSt]	89	1			T13	1		T57	2		T42	4
auto[1]	auto[ClkMuxSt]	53	1			T2	1		T26	1		T203	2
auto[1]	auto[CntIncrSt]	41	1			T2	2		T13	1		T57	1
auto[1]	auto[CntProgSt]	706	1			T2	26		T13	18		T26	10
auto[1]	auto[TransCheckSt]	80	1			T2	2		T26	3		T42	5
auto[1]	auto[TokenHashSt]	479	1			T2	4		T13	11		T26	17
auto[1]	auto[FlashRmaSt]	60	1			T2	2		T13	1		T26	1
auto[1]	auto[TokenCheck0St]	21	1			T42	1		T204	1		T205	2
auto[1]	auto[TokenCheck1St]	98	1			T2	3		T13	2		T26	4
auto[1]	auto[TransProgSt]	441	1			T2	11		T13	16		T26	13
auto[1]	auto[PostTransSt]	2279	1			T2	1		T5	3		T14	8
auto[1]	auto[ScrapSt]	47	1			T2	2		T13	2		T26	1
auto[1]	auto[EscalateSt]	1280597	1			T1	194		T2	9064		T4	3430
auto[1]	auto[InvalidSt]	6427	1			T1	2		T4	35		T14	13

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	6643453	1			T1	1014		T2	7637		T3	116
auto[0]	auto[IdleSt]	18931047	1			T1	23143		T2	2181		T3	917
auto[0]	auto[ClkMuxSt]	32493	1			T1	6		T2	75		T12	1
auto[0]	auto[CntIncrSt]	32239	1			T1	6		T2	74		T12	1
auto[0]	auto[CntProgSt]	1244381	1			T1	12		T2	684		T12	203
auto[0]	auto[TransCheckSt]	25280	1			T1	6		T2	36		T12	1
auto[0]	auto[TokenHashSt]	36374107	1			T1	1970		T2	325		T12	12
auto[0]	auto[FlashRmaSt]	26119	1			T1	13		T2	57		T13	88
auto[0]	auto[TokenCheck0St]	11464	1			T1	6		T2	25		T13	36
auto[0]	auto[TokenCheck1St]	8407	1			T1	6		T2	20		T13	29
auto[0]	auto[TransProgSt]	327111	1			T1	12		T2	59		T13	58
auto[0]	auto[PostTransSt]	10368428	1			T1	29174		T2	2		T12	853
auto[0]	auto[ScrapSt]	126076	1			T2	6		T13	4		T26	3
auto[0]	auto[EscalateSt]	4766308	1			T1	14457		T2	4412		T4	6361
auto[0]	auto[InvalidSt]	10522685	1			T1	15182		T4	11336		T14	3293
auto[1]	auto[ResetSt]	165	1			T2	6		T13	1		T26	4
auto[1]	auto[IdleSt]	101	1			T13	4		T57	1		T42	4
auto[1]	auto[ClkMuxSt]	56	1			T2	2		T13	2		T57	1
auto[1]	auto[CntIncrSt]	39	1			T2	1		T13	1		T26	1
auto[1]	auto[CntProgSt]	694	1			T2	22		T13	19		T26	14
auto[1]	auto[TransCheckSt]	83	1			T2	1		T13	1		T26	2
auto[1]	auto[TokenHashSt]	423	1			T2	3		T13	8		T26	17
auto[1]	auto[FlashRmaSt]	52	1			T2	4		T42	1		T112	1
auto[1]	auto[TokenCheck0St]	15	1			T57	1		T42	1		T60	1
auto[1]	auto[TokenCheck1St]	100	1			T2	5		T13	7		T26	3
auto[1]	auto[TransProgSt]	454	1			T2	12		T13	20		T26	6
auto[1]	auto[PostTransSt]	2264	1			T2	1		T13	1		T5	3
auto[1]	auto[ScrapSt]	39	1			T13	2		T57	2		T112	1
auto[1]	auto[EscalateSt]	1250097	1			T1	194		T2	9585		T4	2548
auto[1]	auto[InvalidSt]	6255	1			T1	2		T4	26		T14	10