Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.83 97.82 95.84 93.34 97.62 98.52 98.76 95.94


Total test records in report: 994
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html
T807 /workspace/coverage/default/37.lc_ctrl_alert_test.587557772 Jun 07 08:36:05 PM PDT 24 Jun 07 08:36:09 PM PDT 24 45979031 ps
T808 /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1559028039 Jun 07 08:34:53 PM PDT 24 Jun 07 08:35:02 PM PDT 24 441672388 ps
T809 /workspace/coverage/default/32.lc_ctrl_sec_token_mux.3243163187 Jun 07 08:35:46 PM PDT 24 Jun 07 08:36:01 PM PDT 24 251123862 ps
T810 /workspace/coverage/default/49.lc_ctrl_sec_token_digest.3921094416 Jun 07 08:36:19 PM PDT 24 Jun 07 08:36:35 PM PDT 24 283562547 ps
T811 /workspace/coverage/default/42.lc_ctrl_stress_all.1518331965 Jun 07 08:36:13 PM PDT 24 Jun 07 08:39:13 PM PDT 24 10786910283 ps
T812 /workspace/coverage/default/24.lc_ctrl_sec_token_digest.466873653 Jun 07 08:35:29 PM PDT 24 Jun 07 08:35:55 PM PDT 24 1155045822 ps
T813 /workspace/coverage/default/23.lc_ctrl_security_escalation.2787291136 Jun 07 08:35:19 PM PDT 24 Jun 07 08:35:41 PM PDT 24 236455180 ps
T814 /workspace/coverage/default/23.lc_ctrl_stress_all.3243170829 Jun 07 08:35:49 PM PDT 24 Jun 07 08:36:52 PM PDT 24 2299689841 ps
T815 /workspace/coverage/default/9.lc_ctrl_security_escalation.1391118807 Jun 07 08:35:01 PM PDT 24 Jun 07 08:35:16 PM PDT 24 1930197047 ps
T156 /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.2821620494 Jun 07 08:35:45 PM PDT 24 Jun 07 09:15:09 PM PDT 24 33807841045 ps
T816 /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1005300236 Jun 07 08:34:47 PM PDT 24 Jun 07 08:34:58 PM PDT 24 2159315771 ps
T817 /workspace/coverage/default/9.lc_ctrl_jtag_access.303575621 Jun 07 08:34:55 PM PDT 24 Jun 07 08:35:06 PM PDT 24 571253697 ps
T818 /workspace/coverage/default/19.lc_ctrl_jtag_access.1738037523 Jun 07 08:35:15 PM PDT 24 Jun 07 08:35:35 PM PDT 24 1570497783 ps
T819 /workspace/coverage/default/35.lc_ctrl_prog_failure.810686126 Jun 07 08:35:58 PM PDT 24 Jun 07 08:36:06 PM PDT 24 313939509 ps
T820 /workspace/coverage/default/39.lc_ctrl_alert_test.67343055 Jun 07 08:36:08 PM PDT 24 Jun 07 08:36:12 PM PDT 24 14104663 ps
T821 /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.26636383 Jun 07 08:35:11 PM PDT 24 Jun 07 08:35:27 PM PDT 24 52019174 ps
T822 /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.80306216 Jun 07 08:35:11 PM PDT 24 Jun 07 08:35:35 PM PDT 24 373203127 ps
T823 /workspace/coverage/default/20.lc_ctrl_prog_failure.3927278998 Jun 07 08:35:11 PM PDT 24 Jun 07 08:35:28 PM PDT 24 56155891 ps
T824 /workspace/coverage/default/27.lc_ctrl_state_post_trans.597727340 Jun 07 08:35:36 PM PDT 24 Jun 07 08:35:49 PM PDT 24 49352982 ps
T825 /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2487597287 Jun 07 08:35:19 PM PDT 24 Jun 07 08:35:36 PM PDT 24 49337185 ps
T826 /workspace/coverage/default/41.lc_ctrl_security_escalation.659077905 Jun 07 08:36:09 PM PDT 24 Jun 07 08:36:20 PM PDT 24 617748193 ps
T827 /workspace/coverage/default/5.lc_ctrl_jtag_access.2425927974 Jun 07 08:34:53 PM PDT 24 Jun 07 08:35:02 PM PDT 24 1733889441 ps
T828 /workspace/coverage/default/32.lc_ctrl_smoke.1461262746 Jun 07 08:35:48 PM PDT 24 Jun 07 08:35:58 PM PDT 24 172212524 ps
T829 /workspace/coverage/default/11.lc_ctrl_state_post_trans.434318497 Jun 07 08:35:05 PM PDT 24 Jun 07 08:35:22 PM PDT 24 62548187 ps
T830 /workspace/coverage/default/48.lc_ctrl_alert_test.1123825912 Jun 07 08:36:17 PM PDT 24 Jun 07 08:36:25 PM PDT 24 16770178 ps
T831 /workspace/coverage/default/20.lc_ctrl_errors.3008897975 Jun 07 08:35:16 PM PDT 24 Jun 07 08:35:43 PM PDT 24 4385043588 ps
T832 /workspace/coverage/default/23.lc_ctrl_alert_test.788356499 Jun 07 08:35:29 PM PDT 24 Jun 07 08:35:39 PM PDT 24 91637560 ps
T88 /workspace/coverage/default/0.lc_ctrl_stress_all.4214566001 Jun 07 08:34:19 PM PDT 24 Jun 07 08:37:07 PM PDT 24 26817629508 ps
T833 /workspace/coverage/default/27.lc_ctrl_security_escalation.4264743360 Jun 07 08:35:34 PM PDT 24 Jun 07 08:35:53 PM PDT 24 305556613 ps
T834 /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2629337924 Jun 07 08:36:12 PM PDT 24 Jun 07 08:36:35 PM PDT 24 435767870 ps
T835 /workspace/coverage/default/32.lc_ctrl_prog_failure.3295709186 Jun 07 08:35:48 PM PDT 24 Jun 07 08:35:58 PM PDT 24 302604315 ps
T836 /workspace/coverage/default/39.lc_ctrl_errors.2265987895 Jun 07 08:36:06 PM PDT 24 Jun 07 08:36:24 PM PDT 24 518224535 ps
T837 /workspace/coverage/default/45.lc_ctrl_state_post_trans.2870284978 Jun 07 08:36:11 PM PDT 24 Jun 07 08:36:24 PM PDT 24 83306314 ps
T838 /workspace/coverage/default/5.lc_ctrl_state_post_trans.253021485 Jun 07 08:34:47 PM PDT 24 Jun 07 08:34:58 PM PDT 24 60254805 ps
T839 /workspace/coverage/default/10.lc_ctrl_stress_all.1205845581 Jun 07 08:35:07 PM PDT 24 Jun 07 08:36:14 PM PDT 24 2048258149 ps
T840 /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3142388620 Jun 07 08:35:10 PM PDT 24 Jun 07 08:35:35 PM PDT 24 534823964 ps
T841 /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1440297220 Jun 07 08:35:14 PM PDT 24 Jun 07 08:35:41 PM PDT 24 466683624 ps
T842 /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.924919746 Jun 07 08:34:51 PM PDT 24 Jun 07 08:35:08 PM PDT 24 3809096009 ps
T843 /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2653076820 Jun 07 08:35:01 PM PDT 24 Jun 07 08:35:12 PM PDT 24 974119482 ps
T844 /workspace/coverage/default/4.lc_ctrl_sec_mubi.2563818079 Jun 07 08:34:34 PM PDT 24 Jun 07 08:34:59 PM PDT 24 2727210629 ps
T845 /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1949456118 Jun 07 08:36:01 PM PDT 24 Jun 07 08:36:06 PM PDT 24 13689833 ps
T846 /workspace/coverage/default/23.lc_ctrl_jtag_access.251537525 Jun 07 08:35:15 PM PDT 24 Jun 07 08:35:37 PM PDT 24 264140269 ps
T847 /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3299360497 Jun 07 08:34:58 PM PDT 24 Jun 07 08:35:16 PM PDT 24 1846280822 ps
T848 /workspace/coverage/default/48.lc_ctrl_prog_failure.3607806063 Jun 07 08:36:18 PM PDT 24 Jun 07 08:36:25 PM PDT 24 26288496 ps
T849 /workspace/coverage/default/3.lc_ctrl_jtag_priority.3625529440 Jun 07 08:34:54 PM PDT 24 Jun 07 08:35:03 PM PDT 24 643845614 ps
T850 /workspace/coverage/default/6.lc_ctrl_prog_failure.3983108791 Jun 07 08:34:51 PM PDT 24 Jun 07 08:34:57 PM PDT 24 65907871 ps
T851 /workspace/coverage/default/22.lc_ctrl_stress_all.3951597742 Jun 07 08:35:33 PM PDT 24 Jun 07 08:36:36 PM PDT 24 4098128883 ps
T852 /workspace/coverage/default/8.lc_ctrl_jtag_priority.2004389103 Jun 07 08:35:08 PM PDT 24 Jun 07 08:35:27 PM PDT 24 819983599 ps
T853 /workspace/coverage/default/8.lc_ctrl_smoke.1594801065 Jun 07 08:35:06 PM PDT 24 Jun 07 08:35:18 PM PDT 24 35034711 ps
T854 /workspace/coverage/default/26.lc_ctrl_sec_mubi.463470470 Jun 07 08:35:40 PM PDT 24 Jun 07 08:35:56 PM PDT 24 308928225 ps
T855 /workspace/coverage/default/26.lc_ctrl_errors.4094854453 Jun 07 08:35:33 PM PDT 24 Jun 07 08:35:52 PM PDT 24 376127002 ps
T856 /workspace/coverage/default/47.lc_ctrl_errors.2390904629 Jun 07 08:36:17 PM PDT 24 Jun 07 08:36:43 PM PDT 24 414426840 ps
T857 /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2920678575 Jun 07 08:35:07 PM PDT 24 Jun 07 08:35:29 PM PDT 24 355944240 ps
T858 /workspace/coverage/default/45.lc_ctrl_jtag_access.1586753239 Jun 07 08:36:11 PM PDT 24 Jun 07 08:36:31 PM PDT 24 1794598258 ps
T859 /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.846262683 Jun 07 08:35:16 PM PDT 24 Jun 07 08:35:32 PM PDT 24 26404407 ps
T860 /workspace/coverage/default/8.lc_ctrl_sec_mubi.789406620 Jun 07 08:35:05 PM PDT 24 Jun 07 08:35:32 PM PDT 24 560662359 ps
T861 /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.184176031 Jun 07 08:34:22 PM PDT 24 Jun 07 08:34:42 PM PDT 24 4877584140 ps
T862 /workspace/coverage/default/18.lc_ctrl_jtag_errors.1435257717 Jun 07 08:35:35 PM PDT 24 Jun 07 08:36:11 PM PDT 24 6507756837 ps
T863 /workspace/coverage/default/11.lc_ctrl_jtag_errors.171507512 Jun 07 08:35:08 PM PDT 24 Jun 07 08:36:05 PM PDT 24 5605687912 ps
T128 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1156040465 Jun 07 08:25:15 PM PDT 24 Jun 07 08:25:19 PM PDT 24 63316528 ps
T125 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.870084890 Jun 07 08:25:57 PM PDT 24 Jun 07 08:26:07 PM PDT 24 223463060 ps
T118 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3994276531 Jun 07 08:25:18 PM PDT 24 Jun 07 08:25:25 PM PDT 24 59730354 ps
T151 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4026277878 Jun 07 08:25:13 PM PDT 24 Jun 07 08:25:22 PM PDT 24 1183856448 ps
T150 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2148556798 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:31 PM PDT 24 1457976618 ps
T148 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2248989146 Jun 07 08:25:15 PM PDT 24 Jun 07 08:25:18 PM PDT 24 45384336 ps
T121 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1817923686 Jun 07 08:25:59 PM PDT 24 Jun 07 08:26:11 PM PDT 24 52565633 ps
T157 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1450203530 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:27 PM PDT 24 34233908 ps
T119 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3776683057 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:30 PM PDT 24 203943956 ps
T120 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1192591636 Jun 07 08:26:00 PM PDT 24 Jun 07 08:26:15 PM PDT 24 251194827 ps
T149 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1276651522 Jun 07 08:25:17 PM PDT 24 Jun 07 08:25:23 PM PDT 24 2703433841 ps
T122 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.139585039 Jun 07 08:25:59 PM PDT 24 Jun 07 08:26:14 PM PDT 24 79428044 ps
T126 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4001256154 Jun 07 08:25:58 PM PDT 24 Jun 07 08:26:08 PM PDT 24 111049816 ps
T123 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2371410257 Jun 07 08:25:57 PM PDT 24 Jun 07 08:26:08 PM PDT 24 1148140082 ps
T163 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1996631686 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:29 PM PDT 24 90925855 ps
T864 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1674493038 Jun 07 08:26:02 PM PDT 24 Jun 07 08:26:17 PM PDT 24 30922031 ps
T865 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3318517872 Jun 07 08:25:19 PM PDT 24 Jun 07 08:25:39 PM PDT 24 7783620763 ps
T124 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.583691955 Jun 07 08:25:57 PM PDT 24 Jun 07 08:26:09 PM PDT 24 590029046 ps
T140 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1727159589 Jun 07 08:25:58 PM PDT 24 Jun 07 08:26:12 PM PDT 24 208718264 ps
T190 /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.184302226 Jun 07 08:25:16 PM PDT 24 Jun 07 08:25:19 PM PDT 24 45163233 ps
T131 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1640773895 Jun 07 08:25:19 PM PDT 24 Jun 07 08:25:26 PM PDT 24 96290593 ps
T866 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2929928916 Jun 07 08:25:19 PM PDT 24 Jun 07 08:25:36 PM PDT 24 1181971920 ps
T867 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3546214638 Jun 07 08:25:13 PM PDT 24 Jun 07 08:25:16 PM PDT 24 21424822 ps
T191 /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3165748716 Jun 07 08:25:56 PM PDT 24 Jun 07 08:26:04 PM PDT 24 18433555 ps
T133 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1925751628 Jun 07 08:25:18 PM PDT 24 Jun 07 08:25:24 PM PDT 24 96872461 ps
T192 /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2719244772 Jun 07 08:26:10 PM PDT 24 Jun 07 08:26:30 PM PDT 24 139667551 ps
T193 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3957066536 Jun 07 08:25:55 PM PDT 24 Jun 07 08:26:01 PM PDT 24 82365473 ps
T194 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4294682156 Jun 07 08:26:06 PM PDT 24 Jun 07 08:26:24 PM PDT 24 22612461 ps
T868 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3273860970 Jun 07 08:25:18 PM PDT 24 Jun 07 08:25:23 PM PDT 24 291881588 ps
T138 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.988948353 Jun 07 08:25:17 PM PDT 24 Jun 07 08:25:24 PM PDT 24 212472407 ps
T136 /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1202818136 Jun 07 08:26:02 PM PDT 24 Jun 07 08:26:19 PM PDT 24 184165838 ps
T195 /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2713404643 Jun 07 08:25:58 PM PDT 24 Jun 07 08:26:09 PM PDT 24 157290123 ps
T869 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1777849180 Jun 07 08:25:56 PM PDT 24 Jun 07 08:26:05 PM PDT 24 52851471 ps
T870 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3809705942 Jun 07 08:26:01 PM PDT 24 Jun 07 08:26:16 PM PDT 24 28877162 ps
T181 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1060941684 Jun 07 08:25:20 PM PDT 24 Jun 07 08:25:26 PM PDT 24 41701720 ps
T871 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1182101989 Jun 07 08:25:19 PM PDT 24 Jun 07 08:25:24 PM PDT 24 43825944 ps
T872 /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3258673974 Jun 07 08:25:58 PM PDT 24 Jun 07 08:26:12 PM PDT 24 258851605 ps
T873 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2168913550 Jun 07 08:26:04 PM PDT 24 Jun 07 08:26:32 PM PDT 24 183749602 ps
T182 /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.687326160 Jun 07 08:26:02 PM PDT 24 Jun 07 08:26:17 PM PDT 24 14086512 ps
T874 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2628893485 Jun 07 08:25:17 PM PDT 24 Jun 07 08:25:23 PM PDT 24 73826715 ps
T875 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3578352790 Jun 07 08:25:23 PM PDT 24 Jun 07 08:25:28 PM PDT 24 109279515 ps
T876 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.50323093 Jun 07 08:25:15 PM PDT 24 Jun 07 08:25:19 PM PDT 24 171696635 ps
T877 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1366146845 Jun 07 08:25:19 PM PDT 24 Jun 07 08:25:25 PM PDT 24 152967871 ps
T135 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2719477797 Jun 07 08:26:08 PM PDT 24 Jun 07 08:26:28 PM PDT 24 23634299 ps
T878 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3570594646 Jun 07 08:25:17 PM PDT 24 Jun 07 08:25:22 PM PDT 24 170321510 ps
T879 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.800984953 Jun 07 08:25:59 PM PDT 24 Jun 07 08:26:12 PM PDT 24 95925069 ps
T880 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1976695512 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:26 PM PDT 24 43308345 ps
T881 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.371379173 Jun 07 08:25:58 PM PDT 24 Jun 07 08:26:10 PM PDT 24 36958847 ps
T882 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.295070367 Jun 07 08:25:16 PM PDT 24 Jun 07 08:25:20 PM PDT 24 238570317 ps
T883 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3169594535 Jun 07 08:25:18 PM PDT 24 Jun 07 08:25:24 PM PDT 24 46868247 ps
T884 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2542074476 Jun 07 08:25:14 PM PDT 24 Jun 07 08:25:17 PM PDT 24 74911078 ps
T885 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3941550313 Jun 07 08:25:18 PM PDT 24 Jun 07 08:25:24 PM PDT 24 18897418 ps
T886 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3697162141 Jun 07 08:25:19 PM PDT 24 Jun 07 08:25:25 PM PDT 24 36413103 ps
T887 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.4247056267 Jun 07 08:25:15 PM PDT 24 Jun 07 08:25:18 PM PDT 24 18414050 ps
T129 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2310631780 Jun 07 08:25:17 PM PDT 24 Jun 07 08:25:24 PM PDT 24 271106968 ps
T888 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2150896531 Jun 07 08:25:14 PM PDT 24 Jun 07 08:25:19 PM PDT 24 83683160 ps
T889 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.663586713 Jun 07 08:26:04 PM PDT 24 Jun 07 08:26:20 PM PDT 24 67083190 ps
T890 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2057372510 Jun 07 08:25:19 PM PDT 24 Jun 07 08:25:30 PM PDT 24 1067718436 ps
T891 /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1612043171 Jun 07 08:25:17 PM PDT 24 Jun 07 08:25:22 PM PDT 24 120480965 ps
T892 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1420237235 Jun 07 08:25:57 PM PDT 24 Jun 07 08:26:08 PM PDT 24 1093550965 ps
T893 /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1217425890 Jun 07 08:25:13 PM PDT 24 Jun 07 08:25:15 PM PDT 24 18966487 ps
T894 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2209741541 Jun 07 08:25:20 PM PDT 24 Jun 07 08:25:27 PM PDT 24 184435926 ps
T895 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2350335344 Jun 07 08:25:57 PM PDT 24 Jun 07 08:26:07 PM PDT 24 25810586 ps
T896 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.650738563 Jun 07 08:26:00 PM PDT 24 Jun 07 08:26:19 PM PDT 24 2921049504 ps
T897 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3195862451 Jun 07 08:25:58 PM PDT 24 Jun 07 08:26:08 PM PDT 24 31206225 ps
T898 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.484704613 Jun 07 08:25:17 PM PDT 24 Jun 07 08:25:22 PM PDT 24 140896780 ps
T899 /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.186346694 Jun 07 08:25:57 PM PDT 24 Jun 07 08:26:06 PM PDT 24 209038013 ps
T196 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.568645817 Jun 07 08:25:19 PM PDT 24 Jun 07 08:25:25 PM PDT 24 352463254 ps
T900 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3412041892 Jun 07 08:25:14 PM PDT 24 Jun 07 08:25:30 PM PDT 24 1787057339 ps
T901 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4243345730 Jun 07 08:26:04 PM PDT 24 Jun 07 08:26:27 PM PDT 24 884865008 ps
T902 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.61615494 Jun 07 08:25:17 PM PDT 24 Jun 07 08:25:23 PM PDT 24 201653459 ps
T143 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1404251218 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:28 PM PDT 24 44850878 ps
T903 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.528016736 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:27 PM PDT 24 197353128 ps
T904 /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1662550088 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:29 PM PDT 24 270839411 ps
T905 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.4049588237 Jun 07 08:25:18 PM PDT 24 Jun 07 08:25:25 PM PDT 24 88590641 ps
T906 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.864844885 Jun 07 08:25:18 PM PDT 24 Jun 07 08:25:23 PM PDT 24 87928147 ps
T197 /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3219456266 Jun 07 08:26:00 PM PDT 24 Jun 07 08:26:14 PM PDT 24 21804167 ps
T907 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.754620812 Jun 07 08:26:00 PM PDT 24 Jun 07 08:26:14 PM PDT 24 20238223 ps
T908 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2735535868 Jun 07 08:25:17 PM PDT 24 Jun 07 08:25:26 PM PDT 24 1038024957 ps
T198 /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.693212792 Jun 07 08:25:58 PM PDT 24 Jun 07 08:26:09 PM PDT 24 103977749 ps
T909 /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2405663568 Jun 07 08:25:59 PM PDT 24 Jun 07 08:26:11 PM PDT 24 24863573 ps
T910 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.4106801225 Jun 07 08:25:20 PM PDT 24 Jun 07 08:25:31 PM PDT 24 2234974920 ps
T911 /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2357215706 Jun 07 08:26:01 PM PDT 24 Jun 07 08:26:15 PM PDT 24 25947450 ps
T912 /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2971526796 Jun 07 08:25:59 PM PDT 24 Jun 07 08:26:11 PM PDT 24 52869202 ps
T913 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.996928814 Jun 07 08:25:58 PM PDT 24 Jun 07 08:26:08 PM PDT 24 23575664 ps
T183 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2852546250 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:26 PM PDT 24 14641243 ps
T914 /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1240053742 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:26 PM PDT 24 122009604 ps
T915 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1918579521 Jun 07 08:25:19 PM PDT 24 Jun 07 08:25:27 PM PDT 24 106432667 ps
T916 /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2312620689 Jun 07 08:26:02 PM PDT 24 Jun 07 08:26:18 PM PDT 24 47370628 ps
T917 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.4111932845 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:26 PM PDT 24 37042783 ps
T918 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2644875046 Jun 07 08:25:17 PM PDT 24 Jun 07 08:25:23 PM PDT 24 112764218 ps
T919 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1807800050 Jun 07 08:26:05 PM PDT 24 Jun 07 08:26:23 PM PDT 24 20698246 ps
T920 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2139745049 Jun 07 08:25:18 PM PDT 24 Jun 07 08:25:33 PM PDT 24 1118764302 ps
T921 /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1448086600 Jun 07 08:25:19 PM PDT 24 Jun 07 08:25:25 PM PDT 24 36873153 ps
T922 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3637025130 Jun 07 08:25:16 PM PDT 24 Jun 07 08:25:20 PM PDT 24 28528681 ps
T923 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.399439596 Jun 07 08:25:24 PM PDT 24 Jun 07 08:25:28 PM PDT 24 62260738 ps
T924 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1982210770 Jun 07 08:25:18 PM PDT 24 Jun 07 08:25:23 PM PDT 24 25961080 ps
T184 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3713928086 Jun 07 08:25:20 PM PDT 24 Jun 07 08:25:25 PM PDT 24 62498070 ps
T925 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2644277761 Jun 07 08:25:54 PM PDT 24 Jun 07 08:26:00 PM PDT 24 71213585 ps
T926 /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4291470328 Jun 07 08:25:57 PM PDT 24 Jun 07 08:26:08 PM PDT 24 26182863 ps
T927 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2807656647 Jun 07 08:25:20 PM PDT 24 Jun 07 08:25:25 PM PDT 24 483814466 ps
T928 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4151779623 Jun 07 08:25:19 PM PDT 24 Jun 07 08:25:24 PM PDT 24 57781291 ps
T929 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.401062724 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:51 PM PDT 24 2191789101 ps
T930 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1383618210 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:36 PM PDT 24 3969383159 ps
T931 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1559547708 Jun 07 08:26:00 PM PDT 24 Jun 07 08:26:13 PM PDT 24 24527686 ps
T932 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2314994741 Jun 07 08:25:57 PM PDT 24 Jun 07 08:26:07 PM PDT 24 29426217 ps
T933 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3063105526 Jun 07 08:25:14 PM PDT 24 Jun 07 08:25:18 PM PDT 24 562426980 ps
T934 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.167727846 Jun 07 08:25:58 PM PDT 24 Jun 07 08:26:09 PM PDT 24 225025397 ps
T935 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1622479726 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:27 PM PDT 24 35281965 ps
T936 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.607324089 Jun 07 08:25:14 PM PDT 24 Jun 07 08:25:18 PM PDT 24 65849497 ps
T937 /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1017884514 Jun 07 08:25:17 PM PDT 24 Jun 07 08:25:23 PM PDT 24 94007293 ps
T185 /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2136310347 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:26 PM PDT 24 14234514 ps
T938 /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2418313548 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:27 PM PDT 24 126712979 ps
T939 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1260431733 Jun 07 08:25:15 PM PDT 24 Jun 07 08:25:20 PM PDT 24 156861103 ps
T940 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1800843661 Jun 07 08:25:17 PM PDT 24 Jun 07 08:25:21 PM PDT 24 104874440 ps
T941 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2609076737 Jun 07 08:25:22 PM PDT 24 Jun 07 08:25:37 PM PDT 24 438441632 ps
T942 /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2877819934 Jun 07 08:26:02 PM PDT 24 Jun 07 08:26:18 PM PDT 24 73989158 ps
T943 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2657101078 Jun 07 08:25:15 PM PDT 24 Jun 07 08:25:18 PM PDT 24 34483526 ps
T944 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.425246878 Jun 07 08:25:19 PM PDT 24 Jun 07 08:25:35 PM PDT 24 4195549250 ps
T139 /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3555717829 Jun 07 08:25:14 PM PDT 24 Jun 07 08:25:18 PM PDT 24 51160200 ps
T945 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.563355311 Jun 07 08:25:20 PM PDT 24 Jun 07 08:25:26 PM PDT 24 45394896 ps
T132 /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.553360444 Jun 07 08:25:59 PM PDT 24 Jun 07 08:26:14 PM PDT 24 106658760 ps
T946 /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1362172242 Jun 07 08:25:14 PM PDT 24 Jun 07 08:25:17 PM PDT 24 29382150 ps
T947 /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.561999140 Jun 07 08:26:03 PM PDT 24 Jun 07 08:26:19 PM PDT 24 97527568 ps
T145 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3259785204 Jun 07 08:25:20 PM PDT 24 Jun 07 08:25:27 PM PDT 24 450063657 ps
T127 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3683746408 Jun 07 08:26:05 PM PDT 24 Jun 07 08:26:26 PM PDT 24 107177305 ps
T186 /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3258779403 Jun 07 08:26:02 PM PDT 24 Jun 07 08:26:17 PM PDT 24 31669408 ps
T948 /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.131665506 Jun 07 08:26:05 PM PDT 24 Jun 07 08:26:23 PM PDT 24 54219907 ps
T949 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.641067913 Jun 07 08:25:17 PM PDT 24 Jun 07 08:25:23 PM PDT 24 76628795 ps
T142 /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1867924675 Jun 07 08:26:01 PM PDT 24 Jun 07 08:26:17 PM PDT 24 483572421 ps
T950 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1450043236 Jun 07 08:25:16 PM PDT 24 Jun 07 08:25:20 PM PDT 24 258926836 ps
T134 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3055253918 Jun 07 08:26:03 PM PDT 24 Jun 07 08:26:22 PM PDT 24 1450268672 ps
T951 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.401602162 Jun 07 08:25:20 PM PDT 24 Jun 07 08:25:27 PM PDT 24 203527086 ps
T952 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.64737929 Jun 07 08:25:54 PM PDT 24 Jun 07 08:26:00 PM PDT 24 105528080 ps
T187 /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.614156322 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:27 PM PDT 24 51110723 ps
T953 /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1441773590 Jun 07 08:25:16 PM PDT 24 Jun 07 08:25:22 PM PDT 24 133554252 ps
T954 /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.892870530 Jun 07 08:26:02 PM PDT 24 Jun 07 08:26:17 PM PDT 24 24028531 ps
T955 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3247591008 Jun 07 08:26:06 PM PDT 24 Jun 07 08:26:26 PM PDT 24 228080390 ps
T956 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2211353508 Jun 07 08:25:57 PM PDT 24 Jun 07 08:26:18 PM PDT 24 1040988569 ps
T957 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3116086815 Jun 07 08:25:20 PM PDT 24 Jun 07 08:25:28 PM PDT 24 1341403963 ps
T958 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1087771874 Jun 07 08:25:18 PM PDT 24 Jun 07 08:25:27 PM PDT 24 922137802 ps
T137 /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.133621719 Jun 07 08:26:07 PM PDT 24 Jun 07 08:26:27 PM PDT 24 623450775 ps
T959 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3980027626 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:30 PM PDT 24 698812803 ps
T960 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1120866864 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:31 PM PDT 24 1161526566 ps
T961 /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2480111213 Jun 07 08:26:07 PM PDT 24 Jun 07 08:26:27 PM PDT 24 21696133 ps
T962 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2277747230 Jun 07 08:25:17 PM PDT 24 Jun 07 08:25:23 PM PDT 24 255417041 ps
T963 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2850316005 Jun 07 08:25:57 PM PDT 24 Jun 07 08:26:09 PM PDT 24 165639681 ps
T964 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3549961075 Jun 07 08:25:13 PM PDT 24 Jun 07 08:25:15 PM PDT 24 144679492 ps
T965 /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1851639587 Jun 07 08:26:04 PM PDT 24 Jun 07 08:26:20 PM PDT 24 118472386 ps
T966 /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2727384752 Jun 07 08:26:02 PM PDT 24 Jun 07 08:26:21 PM PDT 24 117941176 ps
T146 /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.657474317 Jun 07 08:25:17 PM PDT 24 Jun 07 08:25:23 PM PDT 24 243962335 ps
T967 /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3448205815 Jun 07 08:26:09 PM PDT 24 Jun 07 08:26:29 PM PDT 24 87092139 ps
T968 /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2073495483 Jun 07 08:26:03 PM PDT 24 Jun 07 08:26:21 PM PDT 24 182677697 ps
T147 /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3475191310 Jun 07 08:25:20 PM PDT 24 Jun 07 08:25:26 PM PDT 24 153646959 ps
T188 /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4029561892 Jun 07 08:26:12 PM PDT 24 Jun 07 08:26:32 PM PDT 24 43990020 ps
T189 /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2553073587 Jun 07 08:25:14 PM PDT 24 Jun 07 08:25:17 PM PDT 24 34935815 ps
T969 /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2377489909 Jun 07 08:25:16 PM PDT 24 Jun 07 08:25:20 PM PDT 24 62908725 ps
T970 /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1403831725 Jun 07 08:25:17 PM PDT 24 Jun 07 08:25:21 PM PDT 24 47295363 ps
T971 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3646824410 Jun 07 08:25:20 PM PDT 24 Jun 07 08:25:30 PM PDT 24 3492389715 ps
T972 /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2241931010 Jun 07 08:26:00 PM PDT 24 Jun 07 08:26:25 PM PDT 24 557040312 ps
T973 /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3461009506 Jun 07 08:25:20 PM PDT 24 Jun 07 08:25:27 PM PDT 24 80776128 ps
T974 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3198092021 Jun 07 08:25:21 PM PDT 24 Jun 07 08:25:27 PM PDT 24 70252896 ps
T975 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.738176742 Jun 07 08:26:04 PM PDT 24 Jun 07 08:26:22 PM PDT 24 50394504 ps
T976 /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1765741260 Jun 07 08:25:23 PM PDT 24 Jun 07 08:25:29 PM PDT 24 531403502 ps
T977 /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.399014761 Jun 07 08:25:55 PM PDT 24 Jun 07 08:26:02 PM PDT 24 46883475 ps
T978 /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2900991323 Jun 07 08:25:20 PM PDT 24 Jun 07 08:25:26 PM PDT 24 37596402 ps
T130 /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3280489583 Jun 07 08:25:58 PM PDT 24 Jun 07 08:26:10 PM PDT 24 112069693 ps
T979 /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4193420471 Jun 07 08:25:20 PM PDT 24 Jun 07 08:25:25 PM PDT 24 34246555 ps
T980 /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.650433149 Jun 07 08:25:19 PM PDT 24 Jun 07 08:25:23 PM PDT 24 44949992 ps
T981 /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.848253831 Jun 07 08:25:58 PM PDT 24 Jun 07 08:26:18 PM PDT 24 1163328274 ps
T144 /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3259909640 Jun 07 08:25:59 PM PDT 24 Jun 07 08:26:13 PM PDT 24 429798231 ps
T982 /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3722648620 Jun 07 08:25:22 PM PDT 24 Jun 07 08:25:27 PM PDT 24 108943568 ps
T983 /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.375346395 Jun 07 08:25:57 PM PDT 24 Jun 07 08:26:09 PM PDT 24 77928764 ps
T984 /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2435324800 Jun 07 08:26:07 PM PDT 24 Jun 07 08:26:27 PM PDT 24 31413672 ps
T985 /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.619628556 Jun 07 08:25:17 PM PDT 24 Jun 07 08:25:22 PM PDT 24 73911414 ps
T986 /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4140854582 Jun 07 08:26:02 PM PDT 24 Jun 07 08:26:17 PM PDT 24 18729753 ps
T987 /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.762285678 Jun 07 08:26:05 PM PDT 24 Jun 07 08:26:24 PM PDT 24 74451325 ps
T988 /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3764128185 Jun 07 08:25:20 PM PDT 24 Jun 07 08:25:25 PM PDT 24 150113740 ps
T989 /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2013882252 Jun 07 08:26:00 PM PDT 24 Jun 07 08:26:14 PM PDT 24 232510850 ps
T141 /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3255974415 Jun 07 08:25:18 PM PDT 24 Jun 07 08:25:24 PM PDT 24 156111695 ps
T990 /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3810933344 Jun 07 08:25:19 PM PDT 24 Jun 07 08:25:26 PM PDT 24 171077194 ps
T991 /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1304289362 Jun 07 08:25:20 PM PDT 24 Jun 07 08:25:26 PM PDT 24 80479624 ps
T992 /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4017930538 Jun 07 08:25:19 PM PDT 24 Jun 07 08:25:26 PM PDT 24 20646550 ps
T993 /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3965333384 Jun 07 08:25:57 PM PDT 24 Jun 07 08:26:08 PM PDT 24 28588643 ps
T994 /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.387526846 Jun 07 08:25:18 PM PDT 24 Jun 07 08:25:23 PM PDT 24 34551533 ps

Test location /workspace/coverage/default/7.lc_ctrl_security_escalation.2744307318
Short name T13
Test name
Test status
Simulation time 1943966545 ps
CPU time 11.64 seconds
Started Jun 07 08:34:50 PM PDT 24
Finished Jun 07 08:35:04 PM PDT 24
Peak memory 226088 kb
Host smart-72d08da8-406e-46e2-820d-4f5944a31706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744307318 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_security_escalation.2744307318
Directory /workspace/7.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all.2016507066
Short name T15
Test name
Test status
Simulation time 87878644017 ps
CPU time 97.52 seconds
Started Jun 07 08:35:44 PM PDT 24
Finished Jun 07 08:37:28 PM PDT 24
Peak memory 252000 kb
Host smart-7790b772-6c41-4347-a570-071b73f4b615
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016507066 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
28.lc_ctrl_stress_all.2016507066
Directory /workspace/28.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_mubi.190430145
Short name T24
Test name
Test status
Simulation time 1160814271 ps
CPU time 18.58 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:35 PM PDT 24
Peak memory 220000 kb
Host smart-1d834754-540c-472c-aff4-aeff4d16b737
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190430145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_mubi.190430145
Directory /workspace/42.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.1725718432
Short name T49
Test name
Test status
Simulation time 149778073741 ps
CPU time 2948.65 seconds
Started Jun 07 08:35:04 PM PDT 24
Finished Jun 07 09:24:22 PM PDT 24
Peak memory 758404 kb
Host smart-2391ceb4-13e3-4da4-924a-34c0e71a26b6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1725718432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_stress_all_with_rand_reset.1725718432
Directory /workspace/8.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3776683057
Short name T119
Test name
Test status
Simulation time 203943956 ps
CPU time 4.09 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:30 PM PDT 24
Peak memory 219316 kb
Host smart-51704816-c452-452f-8a2c-ee0ce1a69ff6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377668
3057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3776683057
Directory /workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_mux.3011166421
Short name T18
Test name
Test status
Simulation time 845285305 ps
CPU time 6.06 seconds
Started Jun 07 08:34:52 PM PDT 24
Finished Jun 07 08:35:02 PM PDT 24
Peak memory 218288 kb
Host smart-94e5db1a-a442-4296-b33e-d49cdeb975d7
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011166421 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_mux.3
011166421
Directory /workspace/3.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_cm.3324333794
Short name T59
Test name
Test status
Simulation time 1734114096 ps
CPU time 25.34 seconds
Started Jun 07 08:34:25 PM PDT 24
Finished Jun 07 08:35:05 PM PDT 24
Peak memory 280968 kb
Host smart-c99a7b0b-651e-4b86-b886-b726fdb14672
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324333794 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_cm.3324333794
Directory /workspace/0.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/21.lc_ctrl_stress_all.2405470133
Short name T16
Test name
Test status
Simulation time 10426374958 ps
CPU time 266.6 seconds
Started Jun 07 08:35:44 PM PDT 24
Finished Jun 07 08:40:17 PM PDT 24
Peak memory 332760 kb
Host smart-ffba41dc-aea9-4470-b114-c95e42356bf9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405470133 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
21.lc_ctrl_stress_all.2405470133
Directory /workspace/21.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_security_escalation.3809146071
Short name T42
Test name
Test status
Simulation time 404882003 ps
CPU time 8.19 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:27 PM PDT 24
Peak memory 225436 kb
Host smart-4fce9115-bd62-4210-9ead-ad700af2d924
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809146071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_security_escalation.3809146071
Directory /workspace/44.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.2371410257
Short name T123
Test name
Test status
Simulation time 1148140082 ps
CPU time 2.74 seconds
Started Jun 07 08:25:57 PM PDT 24
Finished Jun 07 08:26:08 PM PDT 24
Peak memory 222984 kb
Host smart-3cbaa169-22e4-4ef2-a7da-24faa3ddc216
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371410257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg
_err.2371410257
Directory /workspace/15.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/5.lc_ctrl_alert_test.679347476
Short name T11
Test name
Test status
Simulation time 16068685 ps
CPU time 0.9 seconds
Started Jun 07 08:35:05 PM PDT 24
Finished Jun 07 08:35:15 PM PDT 24
Peak memory 208980 kb
Host smart-5a4d6d88-1250-49ee-8431-2141f42b409d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679347476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_alert_test.679347476
Directory /workspace/5.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_jtag_access.2162646347
Short name T9
Test name
Test status
Simulation time 1162258953 ps
CPU time 27.25 seconds
Started Jun 07 08:35:25 PM PDT 24
Finished Jun 07 08:36:03 PM PDT 24
Peak memory 217492 kb
Host smart-6a95db4f-1ce1-4994-a99d-1eb43126db83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162646347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_jtag_access.2162646347
Directory /workspace/24.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.687326160
Short name T182
Test name
Test status
Simulation time 14086512 ps
CPU time 0.88 seconds
Started Jun 07 08:26:02 PM PDT 24
Finished Jun 07 08:26:17 PM PDT 24
Peak memory 209920 kb
Host smart-b40fa121-5078-486a-9cb9-87e6671470dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687326160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.687326160
Directory /workspace/19.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.613398338
Short name T48
Test name
Test status
Simulation time 148998033349 ps
CPU time 600.24 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:45:22 PM PDT 24
Peak memory 308580 kb
Host smart-5f66cd9b-57ba-4754-b4cd-73de621b897e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=613398338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_stress_all_with_rand_reset.613398338
Directory /workspace/9.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2310631780
Short name T129
Test name
Test status
Simulation time 271106968 ps
CPU time 3.57 seconds
Started Jun 07 08:25:17 PM PDT 24
Finished Jun 07 08:25:24 PM PDT 24
Peak memory 222936 kb
Host smart-cd24f7f2-5a5a-4dc7-9023-d503dd152c7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310631780 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_
err.2310631780
Directory /workspace/5.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.lc_ctrl_security_escalation.2729364462
Short name T2
Test name
Test status
Simulation time 1802610571 ps
CPU time 11.03 seconds
Started Jun 07 08:35:10 PM PDT 24
Finished Jun 07 08:35:36 PM PDT 24
Peak memory 226088 kb
Host smart-fba88844-9e3c-455d-9983-5b8efd2e5e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729364462 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_security_escalation.2729364462
Directory /workspace/14.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1867924675
Short name T142
Test name
Test status
Simulation time 483572421 ps
CPU time 2.96 seconds
Started Jun 07 08:26:01 PM PDT 24
Finished Jun 07 08:26:17 PM PDT 24
Peak memory 222924 kb
Host smart-871c6b91-0064-4fc7-b624-7bf9effb14e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867924675 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg
_err.1867924675
Directory /workspace/11.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.3031403389
Short name T115
Test name
Test status
Simulation time 15326440107 ps
CPU time 256.92 seconds
Started Jun 07 08:35:44 PM PDT 24
Finished Jun 07 08:40:08 PM PDT 24
Peak memory 283088 kb
Host smart-1dcac81a-c1fd-4f99-aa66-3be1335d76ce
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3031403389 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_stress_all_with_rand_reset.3031403389
Directory /workspace/28.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_mubi.3348203628
Short name T14
Test name
Test status
Simulation time 1555738213 ps
CPU time 15.03 seconds
Started Jun 07 08:34:24 PM PDT 24
Finished Jun 07 08:34:49 PM PDT 24
Peak memory 218376 kb
Host smart-f2ec8f8e-b507-42ae-8c43-9ef04d491ba1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348203628 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_mubi.3348203628
Directory /workspace/1.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.3683746408
Short name T127
Test name
Test status
Simulation time 107177305 ps
CPU time 3.98 seconds
Started Jun 07 08:26:05 PM PDT 24
Finished Jun 07 08:26:26 PM PDT 24
Peak memory 218216 kb
Host smart-da0f3a9a-9634-4a8c-baf7-364150bc0324
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683746408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg
_err.3683746408
Directory /workspace/13.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.371379173
Short name T881
Test name
Test status
Simulation time 36958847 ps
CPU time 2.3 seconds
Started Jun 07 08:25:58 PM PDT 24
Finished Jun 07 08:26:10 PM PDT 24
Peak memory 218180 kb
Host smart-89462740-82b5-407a-98f6-3165c6d951f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371379173 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.371379173
Directory /workspace/18.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3255974415
Short name T141
Test name
Test status
Simulation time 156111695 ps
CPU time 2.5 seconds
Started Jun 07 08:25:18 PM PDT 24
Finished Jun 07 08:25:24 PM PDT 24
Peak memory 222844 kb
Host smart-15bd1575-a633-46c0-b9ef-cf96f64e93ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255974415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_
err.3255974415
Directory /workspace/3.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all_with_rand_reset.1416279576
Short name T95
Test name
Test status
Simulation time 233887697305 ps
CPU time 610.99 seconds
Started Jun 07 08:35:14 PM PDT 24
Finished Jun 07 08:45:40 PM PDT 24
Peak memory 299528 kb
Host smart-2d23170e-404a-4f90-b5e9-66eefabd4c93
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1416279576 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_stress_all_with_rand_reset.1416279576
Directory /workspace/20.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.lc_ctrl_claim_transition_if.450684567
Short name T3
Test name
Test status
Simulation time 54436640 ps
CPU time 0.94 seconds
Started Jun 07 08:34:31 PM PDT 24
Finished Jun 07 08:34:44 PM PDT 24
Peak memory 209056 kb
Host smart-6d0b724b-828e-411d-ba51-7fa9829bbc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450684567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_claim_transition_if.450684567
Directory /workspace/1.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.133621719
Short name T137
Test name
Test status
Simulation time 623450775 ps
CPU time 2.13 seconds
Started Jun 07 08:26:07 PM PDT 24
Finished Jun 07 08:26:27 PM PDT 24
Peak memory 222028 kb
Host smart-ae54307d-a33d-48a1-adbf-64818a5d7520
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133621719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg_
err.133621719
Directory /workspace/14.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.553360444
Short name T132
Test name
Test status
Simulation time 106658760 ps
CPU time 2.79 seconds
Started Jun 07 08:25:59 PM PDT 24
Finished Jun 07 08:26:14 PM PDT 24
Peak memory 222888 kb
Host smart-ac833631-4c59-45ea-bf14-f793114d5a8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553360444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_
err.553360444
Directory /workspace/17.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/11.lc_ctrl_volatile_unlock_smoke.1204247102
Short name T233
Test name
Test status
Simulation time 13024578 ps
CPU time 0.88 seconds
Started Jun 07 08:35:09 PM PDT 24
Finished Jun 07 08:35:23 PM PDT 24
Peak memory 211944 kb
Host smart-08ad11b4-ab0d-4486-acdf-a98e27248a76
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204247102 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_c
trl_volatile_unlock_smoke.1204247102
Directory /workspace/11.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_claim_transition_if.1980833251
Short name T200
Test name
Test status
Simulation time 112845321 ps
CPU time 0.86 seconds
Started Jun 07 08:34:47 PM PDT 24
Finished Jun 07 08:34:51 PM PDT 24
Peak memory 208908 kb
Host smart-0f5d394f-4156-4ec6-8e55-d809bb9ff1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980833251 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_claim_transition_if.1980833251
Directory /workspace/5.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.657474317
Short name T146
Test name
Test status
Simulation time 243962335 ps
CPU time 2.02 seconds
Started Jun 07 08:25:17 PM PDT 24
Finished Jun 07 08:25:23 PM PDT 24
Peak memory 222500 kb
Host smart-f76a7ecd-a118-49b3-b58a-4b265e0e8670
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657474317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_e
rr.657474317
Directory /workspace/0.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3055253918
Short name T134
Test name
Test status
Simulation time 1450268672 ps
CPU time 4.37 seconds
Started Jun 07 08:26:03 PM PDT 24
Finished Jun 07 08:26:22 PM PDT 24
Peak memory 218136 kb
Host smart-54d5d6fa-c671-472f-981b-64da2fc7db77
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055253918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg
_err.3055253918
Directory /workspace/12.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.988948353
Short name T138
Test name
Test status
Simulation time 212472407 ps
CPU time 4.03 seconds
Started Jun 07 08:25:17 PM PDT 24
Finished Jun 07 08:25:24 PM PDT 24
Peak memory 218272 kb
Host smart-101ef5b5-aaf8-4e3b-984a-ffff33cf1954
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988948353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e
rr.988948353
Directory /workspace/4.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.3475191310
Short name T147
Test name
Test status
Simulation time 153646959 ps
CPU time 1.8 seconds
Started Jun 07 08:25:20 PM PDT 24
Finished Jun 07 08:25:26 PM PDT 24
Peak memory 222708 kb
Host smart-ee9a0e4f-ea8c-4128-b9b6-927ea9b17901
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475191310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_
err.3475191310
Directory /workspace/6.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/14.lc_ctrl_stress_all.2595450949
Short name T52
Test name
Test status
Simulation time 82676121930 ps
CPU time 498.21 seconds
Started Jun 07 08:35:13 PM PDT 24
Finished Jun 07 08:43:46 PM PDT 24
Peak memory 283728 kb
Host smart-9bd5a888-0ba1-4f2c-a2cb-bb15fc8b4692
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595450949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
14.lc_ctrl_stress_all.2595450949
Directory /workspace/14.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_failure.780094418
Short name T6
Test name
Test status
Simulation time 8712478328 ps
CPU time 34.37 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:36:00 PM PDT 24
Peak memory 251048 kb
Host smart-6d68cf0c-a8b9-4114-a521-45dc224d21f2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780094418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_state_failure.780094418
Directory /workspace/15.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_mux.1731713457
Short name T56
Test name
Test status
Simulation time 291513439 ps
CPU time 7.01 seconds
Started Jun 07 08:35:33 PM PDT 24
Finished Jun 07 08:35:48 PM PDT 24
Peak memory 218188 kb
Host smart-b2387334-c401-42c9-8b2b-ca67045938b1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731713457 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_mux.
1731713457
Directory /workspace/23.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.864844885
Short name T906
Test name
Test status
Simulation time 87928147 ps
CPU time 1.21 seconds
Started Jun 07 08:25:18 PM PDT 24
Finished Jun 07 08:25:23 PM PDT 24
Peak memory 209936 kb
Host smart-da30931e-4c72-4127-ab8f-a8278d6dc338
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864844885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasing
.864844885
Directory /workspace/0.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2209741541
Short name T894
Test name
Test status
Simulation time 184435926 ps
CPU time 1.87 seconds
Started Jun 07 08:25:20 PM PDT 24
Finished Jun 07 08:25:27 PM PDT 24
Peak memory 209940 kb
Host smart-ac0b21ef-a364-4d5e-8378-a0d26564de8b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209741541 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas
h.2209741541
Directory /workspace/0.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3941550313
Short name T885
Test name
Test status
Simulation time 18897418 ps
CPU time 1.04 seconds
Started Jun 07 08:25:18 PM PDT 24
Finished Jun 07 08:25:24 PM PDT 24
Peak memory 218684 kb
Host smart-4a7fe514-6629-4e97-9205-ec199fce84ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941550313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese
t.3941550313
Directory /workspace/0.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1976695512
Short name T880
Test name
Test status
Simulation time 43308345 ps
CPU time 1.06 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:26 PM PDT 24
Peak memory 218180 kb
Host smart-d78d6d4d-1fef-4a94-b198-33123f1f0051
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976695512 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1976695512
Directory /workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.614156322
Short name T187
Test name
Test status
Simulation time 51110723 ps
CPU time 0.94 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:27 PM PDT 24
Peak memory 209980 kb
Host smart-b439531a-18c5-4e6c-8c47-d13ca9c661fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614156322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.614156322
Directory /workspace/0.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3764128185
Short name T988
Test name
Test status
Simulation time 150113740 ps
CPU time 1.06 seconds
Started Jun 07 08:25:20 PM PDT 24
Finished Jun 07 08:25:25 PM PDT 24
Peak memory 209312 kb
Host smart-9f5d3ef1-dc15-457e-9529-d02a0d50d528
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764128185 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 0.lc_ctrl_jtag_alert_test.3764128185
Directory /workspace/0.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1276651522
Short name T149
Test name
Test status
Simulation time 2703433841 ps
CPU time 2.89 seconds
Started Jun 07 08:25:17 PM PDT 24
Finished Jun 07 08:25:23 PM PDT 24
Peak memory 209964 kb
Host smart-8cace50b-7594-4303-bdd1-4f88d263803a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276651522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.1276651522
Directory /workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2139745049
Short name T920
Test name
Test status
Simulation time 1118764302 ps
CPU time 11.14 seconds
Started Jun 07 08:25:18 PM PDT 24
Finished Jun 07 08:25:33 PM PDT 24
Peak memory 217572 kb
Host smart-c855afad-3295-49a8-b4b5-8e52a73e754d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139745049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2139745049
Directory /workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.3570594646
Short name T878
Test name
Test status
Simulation time 170321510 ps
CPU time 2.27 seconds
Started Jun 07 08:25:17 PM PDT 24
Finished Jun 07 08:25:22 PM PDT 24
Peak memory 211556 kb
Host smart-5e7d3d02-8a28-48e7-ba73-ee5fb19e0cb3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570594646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.3570594646
Directory /workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2277747230
Short name T962
Test name
Test status
Simulation time 255417041 ps
CPU time 2.58 seconds
Started Jun 07 08:25:17 PM PDT 24
Finished Jun 07 08:25:23 PM PDT 24
Peak memory 218216 kb
Host smart-88a3fedc-04bf-40a4-9298-34f7248466e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227774
7230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2277747230
Directory /workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.641067913
Short name T949
Test name
Test status
Simulation time 76628795 ps
CPU time 2.42 seconds
Started Jun 07 08:25:17 PM PDT 24
Finished Jun 07 08:25:23 PM PDT 24
Peak memory 209892 kb
Host smart-e2871be6-116b-4a2b-9db9-a3b7545d7670
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641067913 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.lc_ctrl_jtag_csr_rw.641067913
Directory /workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.563355311
Short name T945
Test name
Test status
Simulation time 45394896 ps
CPU time 1.01 seconds
Started Jun 07 08:25:20 PM PDT 24
Finished Jun 07 08:25:26 PM PDT 24
Peak memory 209972 kb
Host smart-5c2c3d2b-0970-4371-991c-5636541cebf3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563355311 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.563355311
Directory /workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1240053742
Short name T914
Test name
Test status
Simulation time 122009604 ps
CPU time 1.04 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:26 PM PDT 24
Peak memory 209972 kb
Host smart-36122898-a322-40ce-ab7f-48eca2e12f73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240053742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl
_same_csr_outstanding.1240053742
Directory /workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3169594535
Short name T883
Test name
Test status
Simulation time 46868247 ps
CPU time 1.89 seconds
Started Jun 07 08:25:18 PM PDT 24
Finished Jun 07 08:25:24 PM PDT 24
Peak memory 218780 kb
Host smart-38d052dc-2995-485f-a915-e40bb5702597
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169594535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3169594535
Directory /workspace/0.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.1060941684
Short name T181
Test name
Test status
Simulation time 41701720 ps
CPU time 1.1 seconds
Started Jun 07 08:25:20 PM PDT 24
Finished Jun 07 08:25:26 PM PDT 24
Peak memory 210012 kb
Host smart-9e7a58b9-c4eb-402d-93fb-e63190a277ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060941684 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin
g.1060941684
Directory /workspace/1.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.3273860970
Short name T868
Test name
Test status
Simulation time 291881588 ps
CPU time 1.34 seconds
Started Jun 07 08:25:18 PM PDT 24
Finished Jun 07 08:25:23 PM PDT 24
Peak memory 209916 kb
Host smart-792cd9f2-8810-40a9-b09e-a07ec6e8b052
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273860970 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas
h.3273860970
Directory /workspace/1.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.1450203530
Short name T157
Test name
Test status
Simulation time 34233908 ps
CPU time 0.92 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:27 PM PDT 24
Peak memory 210088 kb
Host smart-d8939485-6e41-4238-a6e2-66e43f0aa72a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450203530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese
t.1450203530
Directory /workspace/1.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.2377489909
Short name T969
Test name
Test status
Simulation time 62908725 ps
CPU time 1.42 seconds
Started Jun 07 08:25:16 PM PDT 24
Finished Jun 07 08:25:20 PM PDT 24
Peak memory 219876 kb
Host smart-7cadde1a-2a05-41b0-b64c-cef7ca32dd03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377489909 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.2377489909
Directory /workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2852546250
Short name T183
Test name
Test status
Simulation time 14641243 ps
CPU time 1.01 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:26 PM PDT 24
Peak memory 209968 kb
Host smart-c9a3b9ad-c49b-4d60-8083-8b014f8d1907
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852546250 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2852546250
Directory /workspace/1.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.3198092021
Short name T974
Test name
Test status
Simulation time 70252896 ps
CPU time 2.26 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:27 PM PDT 24
Peak memory 209900 kb
Host smart-46830450-3040-4846-89e9-fad41dd9ca1d
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198092021 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 1.lc_ctrl_jtag_alert_test.3198092021
Directory /workspace/1.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2148556798
Short name T150
Test name
Test status
Simulation time 1457976618 ps
CPU time 5.17 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:31 PM PDT 24
Peak memory 209616 kb
Host smart-201822f0-5a1b-47f2-8acd-19c7b15906cc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148556798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2148556798
Directory /workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.425246878
Short name T944
Test name
Test status
Simulation time 4195549250 ps
CPU time 10.57 seconds
Started Jun 07 08:25:19 PM PDT 24
Finished Jun 07 08:25:35 PM PDT 24
Peak memory 210028 kb
Host smart-a97b4d1d-d328-4324-8d90-ab6517ec6182
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425246878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.425246878
Directory /workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1304289362
Short name T991
Test name
Test status
Simulation time 80479624 ps
CPU time 1.68 seconds
Started Jun 07 08:25:20 PM PDT 24
Finished Jun 07 08:25:26 PM PDT 24
Peak memory 211612 kb
Host smart-d110712c-f933-412b-8f76-a31ef72a5369
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304289362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.1304289362
Directory /workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1996631686
Short name T163
Test name
Test status
Simulation time 90925855 ps
CPU time 3.24 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:29 PM PDT 24
Peak memory 218864 kb
Host smart-7eb14c13-a8fd-45fd-81ab-44ba488f8f65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199663
1686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1996631686
Directory /workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2807656647
Short name T927
Test name
Test status
Simulation time 483814466 ps
CPU time 1.34 seconds
Started Jun 07 08:25:20 PM PDT 24
Finished Jun 07 08:25:25 PM PDT 24
Peak memory 209888 kb
Host smart-56627f93-5ed4-49cb-966c-b6940d9e5699
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807656647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.lc_ctrl_jtag_csr_rw.2807656647
Directory /workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.4111932845
Short name T917
Test name
Test status
Simulation time 37042783 ps
CPU time 1.28 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:26 PM PDT 24
Peak memory 218144 kb
Host smart-9164ba8c-780e-4cf5-adc3-1fdc46f830be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111932845 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.4111932845
Directory /workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.619628556
Short name T985
Test name
Test status
Simulation time 73911414 ps
CPU time 1.25 seconds
Started Jun 07 08:25:17 PM PDT 24
Finished Jun 07 08:25:22 PM PDT 24
Peak memory 209956 kb
Host smart-9431a72c-9ea7-4b80-801c-6a66df3e0685
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619628556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
same_csr_outstanding.619628556
Directory /workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1662550088
Short name T904
Test name
Test status
Simulation time 270839411 ps
CPU time 2.61 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:29 PM PDT 24
Peak memory 218176 kb
Host smart-8e028467-f967-4cb6-aab3-cbce73d6dc1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662550088 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1662550088
Directory /workspace/1.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1404251218
Short name T143
Test name
Test status
Simulation time 44850878 ps
CPU time 1.93 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:28 PM PDT 24
Peak memory 222672 kb
Host smart-f635b3ae-780d-4ed7-8cbb-bf0e3e5ed7d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404251218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_
err.1404251218
Directory /workspace/1.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.4140854582
Short name T986
Test name
Test status
Simulation time 18729753 ps
CPU time 1.24 seconds
Started Jun 07 08:26:02 PM PDT 24
Finished Jun 07 08:26:17 PM PDT 24
Peak memory 218232 kb
Host smart-72fcc750-5850-407c-9452-d436f8fd546c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140854582 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.4140854582
Directory /workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.738176742
Short name T975
Test name
Test status
Simulation time 50394504 ps
CPU time 1.06 seconds
Started Jun 07 08:26:04 PM PDT 24
Finished Jun 07 08:26:22 PM PDT 24
Peak memory 209668 kb
Host smart-c7f25028-1f5e-433f-9607-fb75f5e8ed2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738176742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.738176742
Directory /workspace/10.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.561999140
Short name T947
Test name
Test status
Simulation time 97527568 ps
CPU time 1.45 seconds
Started Jun 07 08:26:03 PM PDT 24
Finished Jun 07 08:26:19 PM PDT 24
Peak memory 210036 kb
Host smart-d408afcd-13a3-4886-8a1f-6a1ae77f68ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561999140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_same_csr_outstanding.561999140
Directory /workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.2727384752
Short name T966
Test name
Test status
Simulation time 117941176 ps
CPU time 4.44 seconds
Started Jun 07 08:26:02 PM PDT 24
Finished Jun 07 08:26:21 PM PDT 24
Peak memory 218092 kb
Host smart-9ca8ef9c-3d6b-4d9e-a7bd-5b56e05c5f13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727384752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.2727384752
Directory /workspace/10.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.1192591636
Short name T120
Test name
Test status
Simulation time 251194827 ps
CPU time 2.6 seconds
Started Jun 07 08:26:00 PM PDT 24
Finished Jun 07 08:26:15 PM PDT 24
Peak memory 218172 kb
Host smart-30d1b897-8145-400b-8cb4-31b6a5900f2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192591636 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg
_err.1192591636
Directory /workspace/10.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.3448205815
Short name T967
Test name
Test status
Simulation time 87092139 ps
CPU time 1.08 seconds
Started Jun 07 08:26:09 PM PDT 24
Finished Jun 07 08:26:29 PM PDT 24
Peak memory 218236 kb
Host smart-9ce3b3ac-ec38-47fe-ac1a-b8e1107296b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448205815 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.3448205815
Directory /workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.1674493038
Short name T864
Test name
Test status
Simulation time 30922031 ps
CPU time 0.96 seconds
Started Jun 07 08:26:02 PM PDT 24
Finished Jun 07 08:26:17 PM PDT 24
Peak memory 209940 kb
Host smart-18278298-a80d-4425-a0f5-4752cf44e0e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674493038 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.1674493038
Directory /workspace/11.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.762285678
Short name T987
Test name
Test status
Simulation time 74451325 ps
CPU time 1.75 seconds
Started Jun 07 08:26:05 PM PDT 24
Finished Jun 07 08:26:24 PM PDT 24
Peak memory 209932 kb
Host smart-2f28af98-2a52-4932-bc04-6d6b889d22c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762285678 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_same_csr_outstanding.762285678
Directory /workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.139585039
Short name T122
Test name
Test status
Simulation time 79428044 ps
CPU time 2.55 seconds
Started Jun 07 08:25:59 PM PDT 24
Finished Jun 07 08:26:14 PM PDT 24
Peak memory 218216 kb
Host smart-84dd7b87-1313-40f0-ac92-55e1ecd823a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139585039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.139585039
Directory /workspace/11.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.1807800050
Short name T919
Test name
Test status
Simulation time 20698246 ps
CPU time 1.4 seconds
Started Jun 07 08:26:05 PM PDT 24
Finished Jun 07 08:26:23 PM PDT 24
Peak memory 219900 kb
Host smart-95f0d02f-0fd0-4a1d-a507-fc9beb7d55ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807800050 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.1807800050
Directory /workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3258779403
Short name T186
Test name
Test status
Simulation time 31669408 ps
CPU time 1.14 seconds
Started Jun 07 08:26:02 PM PDT 24
Finished Jun 07 08:26:17 PM PDT 24
Peak memory 217980 kb
Host smart-326118fd-5542-421a-8b6f-df505d4647c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258779403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3258779403
Directory /workspace/12.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.2480111213
Short name T961
Test name
Test status
Simulation time 21696133 ps
CPU time 1.53 seconds
Started Jun 07 08:26:07 PM PDT 24
Finished Jun 07 08:26:27 PM PDT 24
Peak memory 212112 kb
Host smart-cd9fe9ae-6e2e-4f3c-b9c4-5956e083c0eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480111213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr
l_same_csr_outstanding.2480111213
Directory /workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2073495483
Short name T968
Test name
Test status
Simulation time 182677697 ps
CPU time 3.58 seconds
Started Jun 07 08:26:03 PM PDT 24
Finished Jun 07 08:26:21 PM PDT 24
Peak memory 218124 kb
Host smart-f9d03f24-1be5-4cd4-a993-f074cc41d872
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073495483 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.2073495483
Directory /workspace/12.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.3247591008
Short name T955
Test name
Test status
Simulation time 228080390 ps
CPU time 1.85 seconds
Started Jun 07 08:26:06 PM PDT 24
Finished Jun 07 08:26:26 PM PDT 24
Peak memory 219528 kb
Host smart-0dd8436c-7a15-4576-b9d0-6e3a19e8c7cf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247591008 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.3247591008
Directory /workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.4029561892
Short name T188
Test name
Test status
Simulation time 43990020 ps
CPU time 0.86 seconds
Started Jun 07 08:26:12 PM PDT 24
Finished Jun 07 08:26:32 PM PDT 24
Peak memory 209832 kb
Host smart-ef84540d-c3ba-4bc2-a769-feccf9c82fac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029561892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.4029561892
Directory /workspace/13.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2719244772
Short name T192
Test name
Test status
Simulation time 139667551 ps
CPU time 1.82 seconds
Started Jun 07 08:26:10 PM PDT 24
Finished Jun 07 08:26:30 PM PDT 24
Peak memory 212044 kb
Host smart-033d317f-cf9d-4454-92d5-2d30dc4d9fab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719244772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr
l_same_csr_outstanding.2719244772
Directory /workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2435324800
Short name T984
Test name
Test status
Simulation time 31413672 ps
CPU time 2.02 seconds
Started Jun 07 08:26:07 PM PDT 24
Finished Jun 07 08:26:27 PM PDT 24
Peak memory 218452 kb
Host smart-ccc867f2-9c6f-409e-885a-2b6cb536f692
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435324800 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.2435324800
Directory /workspace/13.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2405663568
Short name T909
Test name
Test status
Simulation time 24863573 ps
CPU time 1.17 seconds
Started Jun 07 08:25:59 PM PDT 24
Finished Jun 07 08:26:11 PM PDT 24
Peak memory 218244 kb
Host smart-6894ae40-7f7f-4b99-8cad-91131edd6fb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405663568 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2405663568
Directory /workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.4294682156
Short name T194
Test name
Test status
Simulation time 22612461 ps
CPU time 0.9 seconds
Started Jun 07 08:26:06 PM PDT 24
Finished Jun 07 08:26:24 PM PDT 24
Peak memory 209996 kb
Host smart-825d046d-2469-46cb-9162-1472875f4e4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294682156 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.4294682156
Directory /workspace/14.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2713404643
Short name T195
Test name
Test status
Simulation time 157290123 ps
CPU time 1.37 seconds
Started Jun 07 08:25:58 PM PDT 24
Finished Jun 07 08:26:09 PM PDT 24
Peak memory 209940 kb
Host smart-52a96286-ba27-4849-be87-d33d98a3a58e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713404643 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr
l_same_csr_outstanding.2713404643
Directory /workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.2719477797
Short name T135
Test name
Test status
Simulation time 23634299 ps
CPU time 1.74 seconds
Started Jun 07 08:26:08 PM PDT 24
Finished Jun 07 08:26:28 PM PDT 24
Peak memory 219264 kb
Host smart-a745e222-ed13-4d78-873a-d53b318d9d2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719477797 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.2719477797
Directory /workspace/14.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.2350335344
Short name T895
Test name
Test status
Simulation time 25810586 ps
CPU time 1.28 seconds
Started Jun 07 08:25:57 PM PDT 24
Finished Jun 07 08:26:07 PM PDT 24
Peak memory 222004 kb
Host smart-e860952d-4cb1-416e-8af3-1e16e3972fc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350335344 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.2350335344
Directory /workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.399014761
Short name T977
Test name
Test status
Simulation time 46883475 ps
CPU time 0.89 seconds
Started Jun 07 08:25:55 PM PDT 24
Finished Jun 07 08:26:02 PM PDT 24
Peak memory 209980 kb
Host smart-bdfa7c1f-5942-410f-9378-1266aeb111b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399014761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.399014761
Directory /workspace/15.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.693212792
Short name T198
Test name
Test status
Simulation time 103977749 ps
CPU time 1.12 seconds
Started Jun 07 08:25:58 PM PDT 24
Finished Jun 07 08:26:09 PM PDT 24
Peak memory 218240 kb
Host smart-4eb3e337-32dc-4691-bf78-5e3950fa4e78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693212792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_same_csr_outstanding.693212792
Directory /workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.375346395
Short name T983
Test name
Test status
Simulation time 77928764 ps
CPU time 2.91 seconds
Started Jun 07 08:25:57 PM PDT 24
Finished Jun 07 08:26:09 PM PDT 24
Peak memory 218568 kb
Host smart-88f96c3f-a7f3-470c-b860-ef53f7880af8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375346395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.375346395
Directory /workspace/15.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.4291470328
Short name T926
Test name
Test status
Simulation time 26182863 ps
CPU time 1.74 seconds
Started Jun 07 08:25:57 PM PDT 24
Finished Jun 07 08:26:08 PM PDT 24
Peak memory 218452 kb
Host smart-5d4ea447-e099-4d47-bace-28968b8a5216
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291470328 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.4291470328
Directory /workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.3195862451
Short name T897
Test name
Test status
Simulation time 31206225 ps
CPU time 0.96 seconds
Started Jun 07 08:25:58 PM PDT 24
Finished Jun 07 08:26:08 PM PDT 24
Peak memory 209988 kb
Host smart-47fc9b3c-84be-4d1d-9ae2-6c02918e0649
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195862451 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.3195862451
Directory /workspace/16.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.3165748716
Short name T191
Test name
Test status
Simulation time 18433555 ps
CPU time 1.16 seconds
Started Jun 07 08:25:56 PM PDT 24
Finished Jun 07 08:26:04 PM PDT 24
Peak memory 218100 kb
Host smart-912505e2-254e-4f53-8fcc-7e497f96b06d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165748716 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr
l_same_csr_outstanding.3165748716
Directory /workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.3258673974
Short name T872
Test name
Test status
Simulation time 258851605 ps
CPU time 4.83 seconds
Started Jun 07 08:25:58 PM PDT 24
Finished Jun 07 08:26:12 PM PDT 24
Peak memory 218188 kb
Host smart-0e4ff54e-2376-44ef-a1c7-576db13d1d96
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258673974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.3258673974
Directory /workspace/16.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.583691955
Short name T124
Test name
Test status
Simulation time 590029046 ps
CPU time 4.73 seconds
Started Jun 07 08:25:57 PM PDT 24
Finished Jun 07 08:26:09 PM PDT 24
Peak memory 218248 kb
Host smart-06da7c7b-ded0-4e9d-92cd-e4f24fe811f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583691955 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_
err.583691955
Directory /workspace/16.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.3965333384
Short name T993
Test name
Test status
Simulation time 28588643 ps
CPU time 1.61 seconds
Started Jun 07 08:25:57 PM PDT 24
Finished Jun 07 08:26:08 PM PDT 24
Peak memory 218272 kb
Host smart-d91fe0e9-79e5-4bb1-be7d-555c56397a9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965333384 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.3965333384
Directory /workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.996928814
Short name T913
Test name
Test status
Simulation time 23575664 ps
CPU time 0.84 seconds
Started Jun 07 08:25:58 PM PDT 24
Finished Jun 07 08:26:08 PM PDT 24
Peak memory 209192 kb
Host smart-27a89642-62c5-48fe-a171-9858a795bcee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996928814 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.996928814
Directory /workspace/17.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.2971526796
Short name T912
Test name
Test status
Simulation time 52869202 ps
CPU time 0.98 seconds
Started Jun 07 08:25:59 PM PDT 24
Finished Jun 07 08:26:11 PM PDT 24
Peak memory 209968 kb
Host smart-705f58c9-99cd-4d4a-832b-421019fc5fb3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971526796 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctr
l_same_csr_outstanding.2971526796
Directory /workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.4001256154
Short name T126
Test name
Test status
Simulation time 111049816 ps
CPU time 1.67 seconds
Started Jun 07 08:25:58 PM PDT 24
Finished Jun 07 08:26:08 PM PDT 24
Peak memory 218172 kb
Host smart-d47d0098-2cdb-4a70-b1a4-a17064e81886
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001256154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.4001256154
Directory /workspace/17.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.2357215706
Short name T911
Test name
Test status
Simulation time 25947450 ps
CPU time 1.13 seconds
Started Jun 07 08:26:01 PM PDT 24
Finished Jun 07 08:26:15 PM PDT 24
Peak memory 218276 kb
Host smart-6748e18b-d4d5-45cb-be23-4d8f2ea43588
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357215706 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.2357215706
Directory /workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.663586713
Short name T889
Test name
Test status
Simulation time 67083190 ps
CPU time 0.89 seconds
Started Jun 07 08:26:04 PM PDT 24
Finished Jun 07 08:26:20 PM PDT 24
Peak memory 209800 kb
Host smart-73c4a7f8-2374-4bee-8b87-398bfdb3887c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663586713 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.663586713
Directory /workspace/18.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.892870530
Short name T954
Test name
Test status
Simulation time 24028531 ps
CPU time 1.04 seconds
Started Jun 07 08:26:02 PM PDT 24
Finished Jun 07 08:26:17 PM PDT 24
Peak memory 210124 kb
Host smart-577f04de-a29e-41bd-a9d5-fde687509f91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892870530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_same_csr_outstanding.892870530
Directory /workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.3280489583
Short name T130
Test name
Test status
Simulation time 112069693 ps
CPU time 2.51 seconds
Started Jun 07 08:25:58 PM PDT 24
Finished Jun 07 08:26:10 PM PDT 24
Peak memory 218184 kb
Host smart-b19a4543-f7e4-4193-bfbc-fe834b63e691
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280489583 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg
_err.3280489583
Directory /workspace/18.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.1817923686
Short name T121
Test name
Test status
Simulation time 52565633 ps
CPU time 1.1 seconds
Started Jun 07 08:25:59 PM PDT 24
Finished Jun 07 08:26:11 PM PDT 24
Peak memory 220100 kb
Host smart-8269f329-bf6c-4511-abab-3163c83b07b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817923686 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.1817923686
Directory /workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.1851639587
Short name T965
Test name
Test status
Simulation time 118472386 ps
CPU time 1.34 seconds
Started Jun 07 08:26:04 PM PDT 24
Finished Jun 07 08:26:20 PM PDT 24
Peak memory 209952 kb
Host smart-5ac1f5b7-9e18-452c-a203-868c5d73ae0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851639587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctr
l_same_csr_outstanding.1851639587
Directory /workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1202818136
Short name T136
Test name
Test status
Simulation time 184165838 ps
CPU time 3.08 seconds
Started Jun 07 08:26:02 PM PDT 24
Finished Jun 07 08:26:19 PM PDT 24
Peak memory 218144 kb
Host smart-97bc78a0-f864-4ea1-95d2-ae6e8465eb71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202818136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.1202818136
Directory /workspace/19.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1727159589
Short name T140
Test name
Test status
Simulation time 208718264 ps
CPU time 3.26 seconds
Started Jun 07 08:25:58 PM PDT 24
Finished Jun 07 08:26:12 PM PDT 24
Peak memory 218180 kb
Host smart-2923f07a-da80-4bdd-be42-08a03789f810
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727159589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg
_err.1727159589
Directory /workspace/19.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.3546214638
Short name T867
Test name
Test status
Simulation time 21424822 ps
CPU time 1.23 seconds
Started Jun 07 08:25:13 PM PDT 24
Finished Jun 07 08:25:16 PM PDT 24
Peak memory 210012 kb
Host smart-bba2a89d-07e9-441e-a81f-85b447a1de67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546214638 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin
g.3546214638
Directory /workspace/2.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.50323093
Short name T876
Test name
Test status
Simulation time 171696635 ps
CPU time 1.9 seconds
Started Jun 07 08:25:15 PM PDT 24
Finished Jun 07 08:25:19 PM PDT 24
Peak memory 209884 kb
Host smart-58a29516-0ec0-498e-8fb2-f42a7b2f1e66
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50323093 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bash.50323093
Directory /workspace/2.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.1156040465
Short name T128
Test name
Test status
Simulation time 63316528 ps
CPU time 1.02 seconds
Started Jun 07 08:25:15 PM PDT 24
Finished Jun 07 08:25:19 PM PDT 24
Peak memory 210216 kb
Host smart-5ead078b-e62e-4094-bea9-1a34c1ab4d6f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156040465 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese
t.1156040465
Directory /workspace/2.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.1925751628
Short name T133
Test name
Test status
Simulation time 96872461 ps
CPU time 1.94 seconds
Started Jun 07 08:25:18 PM PDT 24
Finished Jun 07 08:25:24 PM PDT 24
Peak memory 218424 kb
Host smart-6a618b9a-eb57-4de6-814d-4d89d2f6b685
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925751628 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.1925751628
Directory /workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1217425890
Short name T893
Test name
Test status
Simulation time 18966487 ps
CPU time 0.88 seconds
Started Jun 07 08:25:13 PM PDT 24
Finished Jun 07 08:25:15 PM PDT 24
Peak memory 209980 kb
Host smart-7f98faf4-ec5a-472d-8c74-4805fc1b473f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217425890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.1217425890
Directory /workspace/2.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.2628893485
Short name T874
Test name
Test status
Simulation time 73826715 ps
CPU time 2.27 seconds
Started Jun 07 08:25:17 PM PDT 24
Finished Jun 07 08:25:23 PM PDT 24
Peak memory 209980 kb
Host smart-8d6649ec-5368-46e8-af17-724ec3bfa969
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628893485 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 2.lc_ctrl_jtag_alert_test.2628893485
Directory /workspace/2.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2609076737
Short name T941
Test name
Test status
Simulation time 438441632 ps
CPU time 10.4 seconds
Started Jun 07 08:25:22 PM PDT 24
Finished Jun 07 08:25:37 PM PDT 24
Peak memory 209604 kb
Host smart-63ace7a2-0a64-4507-95ed-4e095743d2f7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609076737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2609076737
Directory /workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.3980027626
Short name T959
Test name
Test status
Simulation time 698812803 ps
CPU time 4.38 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:30 PM PDT 24
Peak memory 209912 kb
Host smart-b44feafc-706e-4658-b8ab-38bec5d122e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980027626 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.3980027626
Directory /workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3116086815
Short name T957
Test name
Test status
Simulation time 1341403963 ps
CPU time 4.05 seconds
Started Jun 07 08:25:20 PM PDT 24
Finished Jun 07 08:25:28 PM PDT 24
Peak memory 218188 kb
Host smart-f3189b02-225a-416d-bb68-645e623c723f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116086815 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.3116086815
Directory /workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.401602162
Short name T951
Test name
Test status
Simulation time 203527086 ps
CPU time 2.67 seconds
Started Jun 07 08:25:20 PM PDT 24
Finished Jun 07 08:25:27 PM PDT 24
Peak memory 222704 kb
Host smart-11bf341c-73cc-47ae-a8b7-25a0582dff4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401602
162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.401602162
Directory /workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2900991323
Short name T978
Test name
Test status
Simulation time 37596402 ps
CPU time 1.6 seconds
Started Jun 07 08:25:20 PM PDT 24
Finished Jun 07 08:25:26 PM PDT 24
Peak memory 209876 kb
Host smart-8d49b7ea-dd2a-455c-a098-5f587f9c08fb
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900991323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.lc_ctrl_jtag_csr_rw.2900991323
Directory /workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.4151779623
Short name T928
Test name
Test status
Simulation time 57781291 ps
CPU time 1.2 seconds
Started Jun 07 08:25:19 PM PDT 24
Finished Jun 07 08:25:24 PM PDT 24
Peak memory 218164 kb
Host smart-1485a209-d33d-48c5-94b2-ab09d99efcab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151779623 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.4151779623
Directory /workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.1362172242
Short name T946
Test name
Test status
Simulation time 29382150 ps
CPU time 1.11 seconds
Started Jun 07 08:25:14 PM PDT 24
Finished Jun 07 08:25:17 PM PDT 24
Peak memory 218160 kb
Host smart-170bdd2d-1984-4e26-9d59-6a57744eca8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362172242 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl
_same_csr_outstanding.1362172242
Directory /workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.1260431733
Short name T939
Test name
Test status
Simulation time 156861103 ps
CPU time 2.42 seconds
Started Jun 07 08:25:15 PM PDT 24
Finished Jun 07 08:25:20 PM PDT 24
Peak memory 218344 kb
Host smart-ee3cf8f3-7a3c-48aa-8ffa-b22edb276e1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260431733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.1260431733
Directory /workspace/2.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3555717829
Short name T139
Test name
Test status
Simulation time 51160200 ps
CPU time 2.39 seconds
Started Jun 07 08:25:14 PM PDT 24
Finished Jun 07 08:25:18 PM PDT 24
Peak memory 218164 kb
Host smart-9932824f-feee-4e86-bea0-b0b501af6d45
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555717829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_
err.3555717829
Directory /workspace/2.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.3713928086
Short name T184
Test name
Test status
Simulation time 62498070 ps
CPU time 1.17 seconds
Started Jun 07 08:25:20 PM PDT 24
Finished Jun 07 08:25:25 PM PDT 24
Peak memory 209944 kb
Host smart-88c56119-64cf-4114-a6aa-f90bb42faeab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713928086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin
g.3713928086
Directory /workspace/3.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.3549961075
Short name T964
Test name
Test status
Simulation time 144679492 ps
CPU time 1.74 seconds
Started Jun 07 08:25:13 PM PDT 24
Finished Jun 07 08:25:15 PM PDT 24
Peak memory 209768 kb
Host smart-51abd09d-3e83-4ca2-9eae-530ecd5a0684
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549961075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas
h.3549961075
Directory /workspace/3.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.4247056267
Short name T887
Test name
Test status
Simulation time 18414050 ps
CPU time 1 seconds
Started Jun 07 08:25:15 PM PDT 24
Finished Jun 07 08:25:18 PM PDT 24
Peak memory 210456 kb
Host smart-434b0a45-7ab8-47ff-b309-4e918ea9b0b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247056267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_rese
t.4247056267
Directory /workspace/3.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2657101078
Short name T943
Test name
Test status
Simulation time 34483526 ps
CPU time 1.03 seconds
Started Jun 07 08:25:15 PM PDT 24
Finished Jun 07 08:25:18 PM PDT 24
Peak memory 219256 kb
Host smart-a321b435-6ee7-44e6-8ff7-e3f7512a823e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657101078 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2657101078
Directory /workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.2553073587
Short name T189
Test name
Test status
Simulation time 34935815 ps
CPU time 0.8 seconds
Started Jun 07 08:25:14 PM PDT 24
Finished Jun 07 08:25:17 PM PDT 24
Peak memory 209000 kb
Host smart-1890b5f8-733b-4015-9d03-8ee9e74aa74a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553073587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.2553073587
Directory /workspace/3.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.1765741260
Short name T976
Test name
Test status
Simulation time 531403502 ps
CPU time 1.78 seconds
Started Jun 07 08:25:23 PM PDT 24
Finished Jun 07 08:25:29 PM PDT 24
Peak memory 209888 kb
Host smart-0907c239-80b2-4da0-9af4-006af02f16be
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765741260 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 3.lc_ctrl_jtag_alert_test.1765741260
Directory /workspace/3.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.2057372510
Short name T890
Test name
Test status
Simulation time 1067718436 ps
CPU time 6.69 seconds
Started Jun 07 08:25:19 PM PDT 24
Finished Jun 07 08:25:30 PM PDT 24
Peak memory 209836 kb
Host smart-127c414e-e296-44a9-9fb1-c62e066029ed
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057372510 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.2057372510
Directory /workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3412041892
Short name T900
Test name
Test status
Simulation time 1787057339 ps
CPU time 15.31 seconds
Started Jun 07 08:25:14 PM PDT 24
Finished Jun 07 08:25:30 PM PDT 24
Peak memory 209408 kb
Host smart-8d017626-cd52-4121-a096-14990a2f85bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412041892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.3412041892
Directory /workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.61615494
Short name T902
Test name
Test status
Simulation time 201653459 ps
CPU time 2.86 seconds
Started Jun 07 08:25:17 PM PDT 24
Finished Jun 07 08:25:23 PM PDT 24
Peak memory 211628 kb
Host smart-67efd383-d808-4b4f-b1fc-3dfb55c2db2d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61615494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_bas
e_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/
null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.61615494
Directory /workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1918579521
Short name T915
Test name
Test status
Simulation time 106432667 ps
CPU time 3.42 seconds
Started Jun 07 08:25:19 PM PDT 24
Finished Jun 07 08:25:27 PM PDT 24
Peak memory 218260 kb
Host smart-5166e8a0-e337-4cf7-bb2f-521afd5c6945
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191857
9521 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1918579521
Directory /workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.607324089
Short name T936
Test name
Test status
Simulation time 65849497 ps
CPU time 2.16 seconds
Started Jun 07 08:25:14 PM PDT 24
Finished Jun 07 08:25:18 PM PDT 24
Peak memory 217960 kb
Host smart-c3846741-86a2-4da8-ae7e-8171ec0858b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607324089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.lc_ctrl_jtag_csr_rw.607324089
Directory /workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.1800843661
Short name T940
Test name
Test status
Simulation time 104874440 ps
CPU time 1.39 seconds
Started Jun 07 08:25:17 PM PDT 24
Finished Jun 07 08:25:21 PM PDT 24
Peak memory 209976 kb
Host smart-cdad4745-b622-4099-a5c7-74910c48b351
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800843661 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.1800843661
Directory /workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1017884514
Short name T937
Test name
Test status
Simulation time 94007293 ps
CPU time 2.01 seconds
Started Jun 07 08:25:17 PM PDT 24
Finished Jun 07 08:25:23 PM PDT 24
Peak memory 209980 kb
Host smart-36578df2-f600-4a5c-aa1b-6d4e0e44476f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017884514 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl
_same_csr_outstanding.1017884514
Directory /workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2150896531
Short name T888
Test name
Test status
Simulation time 83683160 ps
CPU time 3.47 seconds
Started Jun 07 08:25:14 PM PDT 24
Finished Jun 07 08:25:19 PM PDT 24
Peak memory 218156 kb
Host smart-1412734a-cb74-4810-bf21-db120c538f4e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150896531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.2150896531
Directory /workspace/3.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.2418313548
Short name T938
Test name
Test status
Simulation time 126712979 ps
CPU time 1.25 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:27 PM PDT 24
Peak memory 210036 kb
Host smart-de6971fe-fc41-4c23-be94-e33e9dd61951
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418313548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin
g.2418313548
Directory /workspace/4.lc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.484704613
Short name T898
Test name
Test status
Simulation time 140896780 ps
CPU time 1.26 seconds
Started Jun 07 08:25:17 PM PDT 24
Finished Jun 07 08:25:22 PM PDT 24
Peak memory 209976 kb
Host smart-39d3502f-9be5-4934-9d36-01b98c3d939e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484704613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bash
.484704613
Directory /workspace/4.lc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2542074476
Short name T884
Test name
Test status
Simulation time 74911078 ps
CPU time 0.98 seconds
Started Jun 07 08:25:14 PM PDT 24
Finished Jun 07 08:25:17 PM PDT 24
Peak memory 218712 kb
Host smart-6627cf03-b786-4321-938f-661cb7b11d09
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542074476 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese
t.2542074476
Directory /workspace/4.lc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3637025130
Short name T922
Test name
Test status
Simulation time 28528681 ps
CPU time 1.89 seconds
Started Jun 07 08:25:16 PM PDT 24
Finished Jun 07 08:25:20 PM PDT 24
Peak memory 218352 kb
Host smart-2532a747-903c-49e1-a8d0-785171fde8a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637025130 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3637025130
Directory /workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2248989146
Short name T148
Test name
Test status
Simulation time 45384336 ps
CPU time 0.93 seconds
Started Jun 07 08:25:15 PM PDT 24
Finished Jun 07 08:25:18 PM PDT 24
Peak memory 209964 kb
Host smart-eab05f87-ce48-4ce2-8c59-fbd7fbf8de72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248989146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2248989146
Directory /workspace/4.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3063105526
Short name T933
Test name
Test status
Simulation time 562426980 ps
CPU time 2.67 seconds
Started Jun 07 08:25:14 PM PDT 24
Finished Jun 07 08:25:18 PM PDT 24
Peak memory 209884 kb
Host smart-41661bea-2e91-4d07-bad7-54438d4f24b7
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063105526 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 4.lc_ctrl_jtag_alert_test.3063105526
Directory /workspace/4.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.2735535868
Short name T908
Test name
Test status
Simulation time 1038024957 ps
CPU time 5.82 seconds
Started Jun 07 08:25:17 PM PDT 24
Finished Jun 07 08:25:26 PM PDT 24
Peak memory 209716 kb
Host smart-69bdc1b4-89b9-4380-a3fa-7915559cd6fa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735535868 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.2735535868
Directory /workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.4026277878
Short name T151
Test name
Test status
Simulation time 1183856448 ps
CPU time 6.84 seconds
Started Jun 07 08:25:13 PM PDT 24
Finished Jun 07 08:25:22 PM PDT 24
Peak memory 209872 kb
Host smart-f0834db7-09ee-4f09-b958-7d931605a5d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026277878 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.4026277878
Directory /workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.4049588237
Short name T905
Test name
Test status
Simulation time 88590641 ps
CPU time 2.66 seconds
Started Jun 07 08:25:18 PM PDT 24
Finished Jun 07 08:25:25 PM PDT 24
Peak memory 211304 kb
Host smart-63b627ae-930c-4f99-a929-59ab662286ab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049588237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.4049588237
Directory /workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.1450043236
Short name T950
Test name
Test status
Simulation time 258926836 ps
CPU time 2.18 seconds
Started Jun 07 08:25:16 PM PDT 24
Finished Jun 07 08:25:20 PM PDT 24
Peak memory 209832 kb
Host smart-4d8568c1-d962-4825-b288-33a30e604c63
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450043236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.lc_ctrl_jtag_csr_rw.1450043236
Directory /workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.387526846
Short name T994
Test name
Test status
Simulation time 34551533 ps
CPU time 1.15 seconds
Started Jun 07 08:25:18 PM PDT 24
Finished Jun 07 08:25:23 PM PDT 24
Peak memory 218332 kb
Host smart-780c3569-f3dc-4819-9c53-bc85aa135b73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387526846 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.387526846
Directory /workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.184302226
Short name T190
Test name
Test status
Simulation time 45163233 ps
CPU time 1.38 seconds
Started Jun 07 08:25:16 PM PDT 24
Finished Jun 07 08:25:19 PM PDT 24
Peak memory 218188 kb
Host smart-72453f7e-4782-4564-b0af-41c28fbf7a33
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184302226 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_
same_csr_outstanding.184302226
Directory /workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.1441773590
Short name T953
Test name
Test status
Simulation time 133554252 ps
CPU time 2.6 seconds
Started Jun 07 08:25:16 PM PDT 24
Finished Jun 07 08:25:22 PM PDT 24
Peak memory 218172 kb
Host smart-a5ab6678-ec19-46c9-8e4f-e4fb6322a205
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441773590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.1441773590
Directory /workspace/4.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.399439596
Short name T923
Test name
Test status
Simulation time 62260738 ps
CPU time 1.21 seconds
Started Jun 07 08:25:24 PM PDT 24
Finished Jun 07 08:25:28 PM PDT 24
Peak memory 218328 kb
Host smart-6d79e66d-b37f-45c2-98d4-0266c1c0b73a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399439596 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.399439596
Directory /workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.650433149
Short name T980
Test name
Test status
Simulation time 44949992 ps
CPU time 0.84 seconds
Started Jun 07 08:25:19 PM PDT 24
Finished Jun 07 08:25:23 PM PDT 24
Peak memory 209872 kb
Host smart-b5b4db93-4a57-4d80-bf6c-21c23bf6c708
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650433149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.650433149
Directory /workspace/5.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1366146845
Short name T877
Test name
Test status
Simulation time 152967871 ps
CPU time 1.44 seconds
Started Jun 07 08:25:19 PM PDT 24
Finished Jun 07 08:25:25 PM PDT 24
Peak memory 209308 kb
Host smart-bb0b80c6-329d-41d6-acbc-4253b0630c53
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366146845 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1366146845
Directory /workspace/5.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1120866864
Short name T960
Test name
Test status
Simulation time 1161526566 ps
CPU time 4.71 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:31 PM PDT 24
Peak memory 209836 kb
Host smart-be4221fd-228c-4a62-8fac-10c120e7e4ae
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120866864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.1120866864
Directory /workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2929928916
Short name T866
Test name
Test status
Simulation time 1181971920 ps
CPU time 12.54 seconds
Started Jun 07 08:25:19 PM PDT 24
Finished Jun 07 08:25:36 PM PDT 24
Peak memory 209816 kb
Host smart-dcff2734-5991-47cc-bb02-da30f833784e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929928916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2929928916
Directory /workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2644875046
Short name T918
Test name
Test status
Simulation time 112764218 ps
CPU time 2.04 seconds
Started Jun 07 08:25:17 PM PDT 24
Finished Jun 07 08:25:23 PM PDT 24
Peak memory 211352 kb
Host smart-ffbb7a07-e59f-4025-abe6-4b8ae67b0273
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644875046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.2644875046
Directory /workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3994276531
Short name T118
Test name
Test status
Simulation time 59730354 ps
CPU time 2.01 seconds
Started Jun 07 08:25:18 PM PDT 24
Finished Jun 07 08:25:25 PM PDT 24
Peak memory 219468 kb
Host smart-b0de142d-3f29-49b0-b8c2-3313b0f85b6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399427
6531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3994276531
Directory /workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1403831725
Short name T970
Test name
Test status
Simulation time 47295363 ps
CPU time 1.74 seconds
Started Jun 07 08:25:17 PM PDT 24
Finished Jun 07 08:25:21 PM PDT 24
Peak memory 209848 kb
Host smart-23b35b78-ec5e-4ea5-972e-8a6ef3015051
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403831725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.lc_ctrl_jtag_csr_rw.1403831725
Directory /workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.568645817
Short name T196
Test name
Test status
Simulation time 352463254 ps
CPU time 1.35 seconds
Started Jun 07 08:25:19 PM PDT 24
Finished Jun 07 08:25:25 PM PDT 24
Peak memory 212156 kb
Host smart-8cbb7291-469a-4d15-8af0-2a909325663d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568645817 -assert nopostproc +UVM_TESTNAM
E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.568645817
Directory /workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.1448086600
Short name T921
Test name
Test status
Simulation time 36873153 ps
CPU time 1.73 seconds
Started Jun 07 08:25:19 PM PDT 24
Finished Jun 07 08:25:25 PM PDT 24
Peak memory 212076 kb
Host smart-15a8bddd-2624-4a77-a160-74e6bcb530ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448086600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl
_same_csr_outstanding.1448086600
Directory /workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.1612043171
Short name T891
Test name
Test status
Simulation time 120480965 ps
CPU time 2.2 seconds
Started Jun 07 08:25:17 PM PDT 24
Finished Jun 07 08:25:22 PM PDT 24
Peak memory 219164 kb
Host smart-2e17836b-26a0-480f-80fa-962a48d7ef98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612043171 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.1612043171
Directory /workspace/5.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.295070367
Short name T882
Test name
Test status
Simulation time 238570317 ps
CPU time 1.37 seconds
Started Jun 07 08:25:16 PM PDT 24
Finished Jun 07 08:25:20 PM PDT 24
Peak memory 218244 kb
Host smart-6e812e9c-ba67-467d-97c7-d66c17483588
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295070367 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.295070367
Directory /workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.2136310347
Short name T185
Test name
Test status
Simulation time 14234514 ps
CPU time 0.84 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:26 PM PDT 24
Peak memory 209964 kb
Host smart-8a550edf-b797-4134-97e7-5c3c7c72b045
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136310347 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.2136310347
Directory /workspace/6.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.3697162141
Short name T886
Test name
Test status
Simulation time 36413103 ps
CPU time 0.92 seconds
Started Jun 07 08:25:19 PM PDT 24
Finished Jun 07 08:25:25 PM PDT 24
Peak memory 209252 kb
Host smart-e9cf966e-4e44-41c3-af70-0e1bc4c52027
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697162141 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 6.lc_ctrl_jtag_alert_test.3697162141
Directory /workspace/6.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1383618210
Short name T930
Test name
Test status
Simulation time 3969383159 ps
CPU time 9.77 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:36 PM PDT 24
Peak memory 209912 kb
Host smart-1328eabe-8984-4a52-ab1e-b6590d5cc6c2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383618210 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_aliasing.1383618210
Directory /workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.4106801225
Short name T910
Test name
Test status
Simulation time 2234974920 ps
CPU time 6.87 seconds
Started Jun 07 08:25:20 PM PDT 24
Finished Jun 07 08:25:31 PM PDT 24
Peak memory 210032 kb
Host smart-fe992267-fc82-489b-bd9b-01fab613d689
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106801225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.4106801225
Directory /workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3810933344
Short name T990
Test name
Test status
Simulation time 171077194 ps
CPU time 2.53 seconds
Started Jun 07 08:25:19 PM PDT 24
Finished Jun 07 08:25:26 PM PDT 24
Peak memory 211524 kb
Host smart-960b2512-ad5f-4f82-967b-5baac4f4c549
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810933344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.3810933344
Directory /workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3646824410
Short name T971
Test name
Test status
Simulation time 3492389715 ps
CPU time 5.59 seconds
Started Jun 07 08:25:20 PM PDT 24
Finished Jun 07 08:25:30 PM PDT 24
Peak memory 219248 kb
Host smart-6d3342d6-40eb-4e3c-8990-c39b2e15ffbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364682
4410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3646824410
Directory /workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1622479726
Short name T935
Test name
Test status
Simulation time 35281965 ps
CPU time 1.56 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:27 PM PDT 24
Peak memory 209964 kb
Host smart-08189001-ce02-4dd8-949d-a803a2b35528
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622479726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te
st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.lc_ctrl_jtag_csr_rw.1622479726
Directory /workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.1982210770
Short name T924
Test name
Test status
Simulation time 25961080 ps
CPU time 1.26 seconds
Started Jun 07 08:25:18 PM PDT 24
Finished Jun 07 08:25:23 PM PDT 24
Peak memory 209924 kb
Host smart-add6ab0b-f865-410c-a2f3-762fe1e3e01e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982210770 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.1982210770
Directory /workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3722648620
Short name T982
Test name
Test status
Simulation time 108943568 ps
CPU time 1.09 seconds
Started Jun 07 08:25:22 PM PDT 24
Finished Jun 07 08:25:27 PM PDT 24
Peak memory 210028 kb
Host smart-02f10e58-0c9a-4c8d-9bb2-c00502389af0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722648620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl
_same_csr_outstanding.3722648620
Directory /workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1640773895
Short name T131
Test name
Test status
Simulation time 96290593 ps
CPU time 2.96 seconds
Started Jun 07 08:25:19 PM PDT 24
Finished Jun 07 08:25:26 PM PDT 24
Peak memory 218152 kb
Host smart-cf9acbe0-2685-4528-ae09-285607196b7c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640773895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1640773895
Directory /workspace/6.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.2314994741
Short name T932
Test name
Test status
Simulation time 29426217 ps
CPU time 1.27 seconds
Started Jun 07 08:25:57 PM PDT 24
Finished Jun 07 08:26:07 PM PDT 24
Peak memory 218468 kb
Host smart-5e03614d-18a2-489d-96c3-172ce9a7e222
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314994741 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.2314994741
Directory /workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.4193420471
Short name T979
Test name
Test status
Simulation time 34246555 ps
CPU time 0.91 seconds
Started Jun 07 08:25:20 PM PDT 24
Finished Jun 07 08:25:25 PM PDT 24
Peak memory 209524 kb
Host smart-240c3c53-7250-4a16-87d0-c7293fec0e09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193420471 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.4193420471
Directory /workspace/7.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1182101989
Short name T871
Test name
Test status
Simulation time 43825944 ps
CPU time 1.12 seconds
Started Jun 07 08:25:19 PM PDT 24
Finished Jun 07 08:25:24 PM PDT 24
Peak memory 209876 kb
Host smart-f9a19a83-2d55-4df5-b898-ef564fb0c6a1
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182101989 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 7.lc_ctrl_jtag_alert_test.1182101989
Directory /workspace/7.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.401062724
Short name T929
Test name
Test status
Simulation time 2191789101 ps
CPU time 26.06 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:51 PM PDT 24
Peak memory 217896 kb
Host smart-7b6e56ef-cf95-4c41-a8d2-77724f42b81e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401062724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 7.lc_ctrl_jtag_csr_aliasing.401062724
Directory /workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3318517872
Short name T865
Test name
Test status
Simulation time 7783620763 ps
CPU time 15.43 seconds
Started Jun 07 08:25:19 PM PDT 24
Finished Jun 07 08:25:39 PM PDT 24
Peak memory 218028 kb
Host smart-c2f2f722-9c17-47d3-b676-9bcf18b25fa5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318517872 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.3318517872
Directory /workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3578352790
Short name T875
Test name
Test status
Simulation time 109279515 ps
CPU time 1.7 seconds
Started Jun 07 08:25:23 PM PDT 24
Finished Jun 07 08:25:28 PM PDT 24
Peak memory 211288 kb
Host smart-96b8ed46-2d11-46b3-acb2-b9a03de12dd7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578352790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3578352790
Directory /workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1087771874
Short name T958
Test name
Test status
Simulation time 922137802 ps
CPU time 4.98 seconds
Started Jun 07 08:25:18 PM PDT 24
Finished Jun 07 08:25:27 PM PDT 24
Peak memory 218216 kb
Host smart-e9e9d2be-e989-4b89-b085-a3ae9f8c129d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108777
1874 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1087771874
Directory /workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.528016736
Short name T903
Test name
Test status
Simulation time 197353128 ps
CPU time 1.16 seconds
Started Jun 07 08:25:21 PM PDT 24
Finished Jun 07 08:25:27 PM PDT 24
Peak memory 209924 kb
Host smart-eb780f85-14e9-4b22-9680-e3011d1b3bd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528016736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.lc_ctrl_jtag_csr_rw.528016736
Directory /workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.4017930538
Short name T992
Test name
Test status
Simulation time 20646550 ps
CPU time 1.47 seconds
Started Jun 07 08:25:19 PM PDT 24
Finished Jun 07 08:25:26 PM PDT 24
Peak memory 212116 kb
Host smart-1731be95-821f-4b7c-85cd-809780038eb8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017930538 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.4017930538
Directory /workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3219456266
Short name T197
Test name
Test status
Simulation time 21804167 ps
CPU time 1.49 seconds
Started Jun 07 08:26:00 PM PDT 24
Finished Jun 07 08:26:14 PM PDT 24
Peak memory 209980 kb
Host smart-9ba6e93a-105a-465e-ba20-79a8240d3bcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219456266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl
_same_csr_outstanding.3219456266
Directory /workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3461009506
Short name T973
Test name
Test status
Simulation time 80776128 ps
CPU time 2.49 seconds
Started Jun 07 08:25:20 PM PDT 24
Finished Jun 07 08:25:27 PM PDT 24
Peak memory 219200 kb
Host smart-94dc4d23-16cb-4c55-b934-e87b16f14697
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461009506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3461009506
Directory /workspace/7.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.3259785204
Short name T145
Test name
Test status
Simulation time 450063657 ps
CPU time 2.71 seconds
Started Jun 07 08:25:20 PM PDT 24
Finished Jun 07 08:25:27 PM PDT 24
Peak memory 222664 kb
Host smart-62ff7177-46eb-4da6-a662-823052a83bff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259785204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_
err.3259785204
Directory /workspace/7.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.800984953
Short name T879
Test name
Test status
Simulation time 95925069 ps
CPU time 1.47 seconds
Started Jun 07 08:25:59 PM PDT 24
Finished Jun 07 08:26:12 PM PDT 24
Peak memory 218280 kb
Host smart-f6b2f965-af3f-44df-b587-183ce9ce6c83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800984953 -assert nopostproc +UVM_TESTNAME=
lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c
m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.800984953
Directory /workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.186346694
Short name T899
Test name
Test status
Simulation time 209038013 ps
CPU time 1.08 seconds
Started Jun 07 08:25:57 PM PDT 24
Finished Jun 07 08:26:06 PM PDT 24
Peak memory 210076 kb
Host smart-f58d66b3-82a8-471d-a154-f14706d0fc56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186346694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.186346694
Directory /workspace/8.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2644277761
Short name T925
Test name
Test status
Simulation time 71213585 ps
CPU time 2.43 seconds
Started Jun 07 08:25:54 PM PDT 24
Finished Jun 07 08:26:00 PM PDT 24
Peak memory 209888 kb
Host smart-0f628d4e-b5cb-4274-8a75-5bdf6e370430
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644277761 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 8.lc_ctrl_jtag_alert_test.2644277761
Directory /workspace/8.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.848253831
Short name T981
Test name
Test status
Simulation time 1163328274 ps
CPU time 9.18 seconds
Started Jun 07 08:25:58 PM PDT 24
Finished Jun 07 08:26:18 PM PDT 24
Peak memory 209520 kb
Host smart-0379d440-c1c7-42d6-9b6f-37682e24b80f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848253831 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.848253831
Directory /workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.2211353508
Short name T956
Test name
Test status
Simulation time 1040988569 ps
CPU time 12.57 seconds
Started Jun 07 08:25:57 PM PDT 24
Finished Jun 07 08:26:18 PM PDT 24
Peak memory 209672 kb
Host smart-5faeebe9-0c2d-4849-be03-98adba418882
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211353508 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.2211353508
Directory /workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.1777849180
Short name T869
Test name
Test status
Simulation time 52851471 ps
CPU time 1.99 seconds
Started Jun 07 08:25:56 PM PDT 24
Finished Jun 07 08:26:05 PM PDT 24
Peak memory 211384 kb
Host smart-0522818b-2b75-4d99-8d5a-f6ddf75e2f44
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777849180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.1777849180
Directory /workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2850316005
Short name T963
Test name
Test status
Simulation time 165639681 ps
CPU time 3.05 seconds
Started Jun 07 08:25:57 PM PDT 24
Finished Jun 07 08:26:09 PM PDT 24
Peak memory 218584 kb
Host smart-53bc9c42-0155-4114-974f-4c20d3dd180f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285031
6005 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2850316005
Directory /workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.64737929
Short name T952
Test name
Test status
Simulation time 105528080 ps
CPU time 1.09 seconds
Started Jun 07 08:25:54 PM PDT 24
Finished Jun 07 08:26:00 PM PDT 24
Peak memory 209880 kb
Host smart-dd90651a-9461-4557-8e18-2364d2c7c78b
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64737929 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test
+UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 8.lc_ctrl_jtag_csr_rw.64737929
Directory /workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3957066536
Short name T193
Test name
Test status
Simulation time 82365473 ps
CPU time 1.05 seconds
Started Jun 07 08:25:55 PM PDT 24
Finished Jun 07 08:26:01 PM PDT 24
Peak memory 218124 kb
Host smart-256e7599-2c9f-4c05-8c00-cc4708dcb7bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957066536 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3957066536
Directory /workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.2013882252
Short name T989
Test name
Test status
Simulation time 232510850 ps
CPU time 1.15 seconds
Started Jun 07 08:26:00 PM PDT 24
Finished Jun 07 08:26:14 PM PDT 24
Peak memory 209932 kb
Host smart-608a6226-9a8a-489a-b056-fad4d7dd650d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013882252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc
_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl
_same_csr_outstanding.2013882252
Directory /workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.167727846
Short name T934
Test name
Test status
Simulation time 225025397 ps
CPU time 2.91 seconds
Started Jun 07 08:25:58 PM PDT 24
Finished Jun 07 08:26:09 PM PDT 24
Peak memory 218252 kb
Host smart-1dbe92a1-68e1-47d5-bdfb-a34ebc29ae5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167727846 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.167727846
Directory /workspace/8.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.3259909640
Short name T144
Test name
Test status
Simulation time 429798231 ps
CPU time 3.85 seconds
Started Jun 07 08:25:59 PM PDT 24
Finished Jun 07 08:26:13 PM PDT 24
Peak memory 218240 kb
Host smart-9f9f5bf5-38f4-4c8b-8644-209fbc4baae3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259909640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_
err.3259909640
Directory /workspace/8.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.2877819934
Short name T942
Test name
Test status
Simulation time 73989158 ps
CPU time 1.39 seconds
Started Jun 07 08:26:02 PM PDT 24
Finished Jun 07 08:26:18 PM PDT 24
Peak memory 219268 kb
Host smart-e1330839-87f1-4df6-855f-1cc4963c077b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877819934 -assert nopostproc +UVM_TESTNAME
=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.2877819934
Directory /workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.754620812
Short name T907
Test name
Test status
Simulation time 20238223 ps
CPU time 0.98 seconds
Started Jun 07 08:26:00 PM PDT 24
Finished Jun 07 08:26:14 PM PDT 24
Peak memory 209936 kb
Host smart-1bbaee43-cc56-472a-8122-582c19b96d3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754620812 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.754620812
Directory /workspace/9.lc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.3809705942
Short name T870
Test name
Test status
Simulation time 28877162 ps
CPU time 1 seconds
Started Jun 07 08:26:01 PM PDT 24
Finished Jun 07 08:26:16 PM PDT 24
Peak memory 209292 kb
Host smart-985ea323-00e2-48ed-9b0f-26f1b7648d02
User root
Command /workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB
OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809705942 -assert nopostproc +UVM_TESTNAME=lc_ctrl
_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /
dev/null -cm_name 9.lc_ctrl_jtag_alert_test.3809705942
Directory /workspace/9.lc_ctrl_jtag_alert_test/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.650738563
Short name T896
Test name
Test status
Simulation time 2921049504 ps
CPU time 8.07 seconds
Started Jun 07 08:26:00 PM PDT 24
Finished Jun 07 08:26:19 PM PDT 24
Peak memory 210036 kb
Host smart-2d304d4f-124a-45ac-935a-f3ab608bcd20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650738563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba
se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev
/null -cm_name 9.lc_ctrl_jtag_csr_aliasing.650738563
Directory /workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.2241931010
Short name T972
Test name
Test status
Simulation time 557040312 ps
CPU time 13.44 seconds
Started Jun 07 08:26:00 PM PDT 24
Finished Jun 07 08:26:25 PM PDT 24
Peak memory 209668 kb
Host smart-e4ce7631-6335-4bdc-b7dc-d956387da1da
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241931010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.2241931010
Directory /workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.1420237235
Short name T892
Test name
Test status
Simulation time 1093550965 ps
CPU time 3.67 seconds
Started Jun 07 08:25:57 PM PDT 24
Finished Jun 07 08:26:08 PM PDT 24
Peak memory 218060 kb
Host smart-6614c47c-f7e6-4b50-803d-8517026d004e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420237235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b
ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de
v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.1420237235
Directory /workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4243345730
Short name T901
Test name
Test status
Simulation time 884865008 ps
CPU time 5.91 seconds
Started Jun 07 08:26:04 PM PDT 24
Finished Jun 07 08:26:27 PM PDT 24
Peak memory 218264 kb
Host smart-4916d1ab-04f2-486d-951a-d7fad3c5be3e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424334
5730 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.4243345730
Directory /workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.870084890
Short name T125
Test name
Test status
Simulation time 223463060 ps
CPU time 1.26 seconds
Started Jun 07 08:25:57 PM PDT 24
Finished Jun 07 08:26:07 PM PDT 24
Peak memory 217832 kb
Host smart-3c66408c-68d5-4dbd-9e75-460c7e333d10
User root
Command /workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870084890 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes
t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.lc_ctrl_jtag_csr_rw.870084890
Directory /workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.1559547708
Short name T931
Test name
Test status
Simulation time 24527686 ps
CPU time 1.03 seconds
Started Jun 07 08:26:00 PM PDT 24
Finished Jun 07 08:26:13 PM PDT 24
Peak memory 209980 kb
Host smart-e30825bd-c6c0-4b26-a9a2-9177968cf93a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559547708 -assert nopostproc +UVM_TESTNA
ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.1559547708
Directory /workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.131665506
Short name T948
Test name
Test status
Simulation time 54219907 ps
CPU time 1.13 seconds
Started Jun 07 08:26:05 PM PDT 24
Finished Jun 07 08:26:23 PM PDT 24
Peak memory 218164 kb
Host smart-0f731d77-604c-4ba7-bfb8-621ceb12b0bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131665506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
same_csr_outstanding.131665506
Directory /workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2168913550
Short name T873
Test name
Test status
Simulation time 183749602 ps
CPU time 3.44 seconds
Started Jun 07 08:26:04 PM PDT 24
Finished Jun 07 08:26:32 PM PDT 24
Peak memory 218092 kb
Host smart-72d8c21a-2b72-4099-ae48-84a0248f3753
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168913550 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.2168913550
Directory /workspace/9.lc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2312620689
Short name T916
Test name
Test status
Simulation time 47370628 ps
CPU time 1.76 seconds
Started Jun 07 08:26:02 PM PDT 24
Finished Jun 07 08:26:18 PM PDT 24
Peak memory 222756 kb
Host smart-6e5d32cb-a267-4a7d-a581-65404a29ec63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312620689 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_
err.2312620689
Directory /workspace/9.lc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.lc_ctrl_alert_test.800049139
Short name T110
Test name
Test status
Simulation time 28263945 ps
CPU time 0.99 seconds
Started Jun 07 08:34:26 PM PDT 24
Finished Jun 07 08:34:37 PM PDT 24
Peak memory 209068 kb
Host smart-15752d9c-0d71-4961-bb77-c130e5a94921
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800049139 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_alert_test.800049139
Directory /workspace/0.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.lc_ctrl_claim_transition_if.3357896460
Short name T709
Test name
Test status
Simulation time 22878362 ps
CPU time 0.8 seconds
Started Jun 07 08:34:29 PM PDT 24
Finished Jun 07 08:34:40 PM PDT 24
Peak memory 208904 kb
Host smart-ae7ecbc5-2db0-4aa0-9f9c-f9dcd4f99d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357896460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_claim_transition_if.3357896460
Directory /workspace/0.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/0.lc_ctrl_errors.3014395916
Short name T802
Test name
Test status
Simulation time 710506043 ps
CPU time 16.5 seconds
Started Jun 07 08:34:28 PM PDT 24
Finished Jun 07 08:34:54 PM PDT 24
Peak memory 218076 kb
Host smart-df677e66-3460-4cef-bbc9-6e962d32cc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014395916 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_errors.3014395916
Directory /workspace/0.lc_ctrl_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_access.4117478807
Short name T34
Test name
Test status
Simulation time 831628630 ps
CPU time 9.83 seconds
Started Jun 07 08:34:33 PM PDT 24
Finished Jun 07 08:34:51 PM PDT 24
Peak memory 217580 kb
Host smart-66db3be2-37f1-4e75-9ff7-53cc0d24df56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117478807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_access.4117478807
Directory /workspace/0.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_errors.987389071
Short name T600
Test name
Test status
Simulation time 11969332436 ps
CPU time 84.37 seconds
Started Jun 07 08:34:23 PM PDT 24
Finished Jun 07 08:35:58 PM PDT 24
Peak memory 218740 kb
Host smart-db3c9112-64eb-4238-9d67-919b058bdcdb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987389071 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_err
ors.987389071
Directory /workspace/0.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_priority.781337926
Short name T574
Test name
Test status
Simulation time 146233606 ps
CPU time 4.68 seconds
Started Jun 07 08:34:22 PM PDT 24
Finished Jun 07 08:34:37 PM PDT 24
Peak memory 217536 kb
Host smart-145a1000-0dc8-46f5-b382-3c78f6ae6ad4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781337926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_priority.781337926
Directory /workspace/0.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_prog_failure.2527244637
Short name T595
Test name
Test status
Simulation time 426421917 ps
CPU time 4.74 seconds
Started Jun 07 08:34:19 PM PDT 24
Finished Jun 07 08:34:34 PM PDT 24
Peak memory 223144 kb
Host smart-efd7e7f6-7b25-4844-bcad-ad130cfce0c6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527244637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag
_prog_failure.2527244637
Directory /workspace/0.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_regwen_during_op.3346599174
Short name T41
Test name
Test status
Simulation time 2645639027 ps
CPU time 37.81 seconds
Started Jun 07 08:34:20 PM PDT 24
Finished Jun 07 08:35:14 PM PDT 24
Peak memory 217728 kb
Host smart-eb785f52-a996-4a83-9ed7-4cbb8b71bb0a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346599174 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_
jtag_regwen_during_op.3346599174
Directory /workspace/0.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_smoke.1559028039
Short name T808
Test name
Test status
Simulation time 441672388 ps
CPU time 4.56 seconds
Started Jun 07 08:34:53 PM PDT 24
Finished Jun 07 08:35:02 PM PDT 24
Peak memory 217708 kb
Host smart-4efc2c2b-7c38-4714-ac5b-2fe2085fe419
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559028039 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_smoke.
1559028039
Directory /workspace/0.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_failure.1475782733
Short name T28
Test name
Test status
Simulation time 1344586009 ps
CPU time 42.51 seconds
Started Jun 07 08:34:25 PM PDT 24
Finished Jun 07 08:35:18 PM PDT 24
Peak memory 267252 kb
Host smart-893af75f-2680-414b-a428-1067e6f35635
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475782733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jta
g_state_failure.1475782733
Directory /workspace/0.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_jtag_state_post_trans.253082517
Short name T266
Test name
Test status
Simulation time 651718685 ps
CPU time 18.22 seconds
Started Jun 07 08:34:53 PM PDT 24
Finished Jun 07 08:35:16 PM PDT 24
Peak memory 224352 kb
Host smart-7b0951f3-5824-4d11-973a-a3f1dd1baa85
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253082517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_j
tag_state_post_trans.253082517
Directory /workspace/0.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_prog_failure.3654578781
Short name T253
Test name
Test status
Simulation time 67704561 ps
CPU time 3.33 seconds
Started Jun 07 08:34:19 PM PDT 24
Finished Jun 07 08:34:32 PM PDT 24
Peak memory 222708 kb
Host smart-1e1d7a9c-a289-4312-8f30-5e79d02640dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3654578781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_prog_failure.3654578781
Directory /workspace/0.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_regwen_during_op.1618757489
Short name T177
Test name
Test status
Simulation time 525367582 ps
CPU time 6.72 seconds
Started Jun 07 08:34:27 PM PDT 24
Finished Jun 07 08:34:44 PM PDT 24
Peak memory 214552 kb
Host smart-f33fef97-ab9b-4d9e-b763-e766690aecad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618757489 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_regwen_during_op.1618757489
Directory /workspace/0.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_mubi.1466747335
Short name T689
Test name
Test status
Simulation time 719374092 ps
CPU time 16.96 seconds
Started Jun 07 08:34:31 PM PDT 24
Finished Jun 07 08:34:58 PM PDT 24
Peak memory 226048 kb
Host smart-b971d827-2a89-4749-bd41-609c16d0e7b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466747335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_mubi.1466747335
Directory /workspace/0.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_digest.1469524108
Short name T398
Test name
Test status
Simulation time 771708156 ps
CPU time 14.82 seconds
Started Jun 07 08:34:35 PM PDT 24
Finished Jun 07 08:34:58 PM PDT 24
Peak memory 218276 kb
Host smart-3c3b7639-f1fc-4dd0-a991-fdf8952fb14d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469524108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_di
gest.1469524108
Directory /workspace/0.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/0.lc_ctrl_sec_token_mux.1085336945
Short name T165
Test name
Test status
Simulation time 532288777 ps
CPU time 6.45 seconds
Started Jun 07 08:34:27 PM PDT 24
Finished Jun 07 08:34:43 PM PDT 24
Peak memory 218252 kb
Host smart-862cfc9d-adfa-48b8-add8-e69ce16662a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085336945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_sec_token_mux.1
085336945
Directory /workspace/0.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/0.lc_ctrl_security_escalation.3118167732
Short name T204
Test name
Test status
Simulation time 1832985007 ps
CPU time 7.12 seconds
Started Jun 07 08:34:18 PM PDT 24
Finished Jun 07 08:34:35 PM PDT 24
Peak memory 224804 kb
Host smart-54067593-56ec-4c67-a4d3-aab948a60526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118167732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_security_escalation.3118167732
Directory /workspace/0.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/0.lc_ctrl_smoke.4256486882
Short name T710
Test name
Test status
Simulation time 191406446 ps
CPU time 5.63 seconds
Started Jun 07 08:34:19 PM PDT 24
Finished Jun 07 08:34:34 PM PDT 24
Peak memory 217780 kb
Host smart-5868e888-99a7-4510-a3cb-90b8b7395eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256486882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_smoke.4256486882
Directory /workspace/0.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_failure.901636790
Short name T411
Test name
Test status
Simulation time 193883997 ps
CPU time 20.98 seconds
Started Jun 07 08:34:28 PM PDT 24
Finished Jun 07 08:34:59 PM PDT 24
Peak memory 250936 kb
Host smart-c513fe12-b826-4cfc-9d12-1398b274dd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=901636790 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_failure.901636790
Directory /workspace/0.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/0.lc_ctrl_state_post_trans.3857627487
Short name T222
Test name
Test status
Simulation time 479504293 ps
CPU time 5.8 seconds
Started Jun 07 08:34:42 PM PDT 24
Finished Jun 07 08:34:52 PM PDT 24
Peak memory 218232 kb
Host smart-fc346d9b-ed51-49ac-afd4-af55049d8aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857627487 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_state_post_trans.3857627487
Directory /workspace/0.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/0.lc_ctrl_stress_all.4214566001
Short name T88
Test name
Test status
Simulation time 26817629508 ps
CPU time 159.18 seconds
Started Jun 07 08:34:19 PM PDT 24
Finished Jun 07 08:37:07 PM PDT 24
Peak memory 283760 kb
Host smart-7edd719a-0289-4240-9102-6f88343401a4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214566001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.lc_ctrl_stress_all.4214566001
Directory /workspace/0.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3580847760
Short name T558
Test name
Test status
Simulation time 20238527 ps
CPU time 0.98 seconds
Started Jun 07 08:34:19 PM PDT 24
Finished Jun 07 08:34:30 PM PDT 24
Peak memory 211972 kb
Host smart-36c06b9a-3584-4a27-b4bd-e64a68e257f5
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580847760 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.lc_ct
rl_volatile_unlock_smoke.3580847760
Directory /workspace/0.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_alert_test.859906552
Short name T599
Test name
Test status
Simulation time 78270656 ps
CPU time 1.1 seconds
Started Jun 07 08:34:54 PM PDT 24
Finished Jun 07 08:34:59 PM PDT 24
Peak memory 209000 kb
Host smart-7af5309b-4239-4fe1-bf16-a1b77fad1906
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859906552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_alert_test.859906552
Directory /workspace/1.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.lc_ctrl_errors.3091041410
Short name T210
Test name
Test status
Simulation time 874321944 ps
CPU time 16.3 seconds
Started Jun 07 08:34:38 PM PDT 24
Finished Jun 07 08:35:01 PM PDT 24
Peak memory 218332 kb
Host smart-47063530-3d4c-49df-bf67-c00738c593d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091041410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_errors.3091041410
Directory /workspace/1.lc_ctrl_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_access.2689406060
Short name T178
Test name
Test status
Simulation time 483110937 ps
CPU time 6.46 seconds
Started Jun 07 08:34:36 PM PDT 24
Finished Jun 07 08:34:49 PM PDT 24
Peak memory 217312 kb
Host smart-04d6aa09-bba5-4fa9-ab34-18aad0beb28a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689406060 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_access.2689406060
Directory /workspace/1.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_errors.1029527516
Short name T784
Test name
Test status
Simulation time 1709398214 ps
CPU time 30.8 seconds
Started Jun 07 08:34:27 PM PDT 24
Finished Jun 07 08:35:08 PM PDT 24
Peak memory 218216 kb
Host smart-1248c39f-b045-4e3d-ac22-daf68f48c2a5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029527516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_er
rors.1029527516
Directory /workspace/1.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_priority.640636006
Short name T792
Test name
Test status
Simulation time 3626645351 ps
CPU time 16.88 seconds
Started Jun 07 08:34:36 PM PDT 24
Finished Jun 07 08:35:00 PM PDT 24
Peak memory 217896 kb
Host smart-4b9cc7cd-1e55-4a87-adb2-b849f386aa90
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640636006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_priority.640636006
Directory /workspace/1.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_prog_failure.907533364
Short name T622
Test name
Test status
Simulation time 343537090 ps
CPU time 10.07 seconds
Started Jun 07 08:34:22 PM PDT 24
Finished Jun 07 08:34:43 PM PDT 24
Peak memory 223096 kb
Host smart-c0384274-c1bf-4cc1-a467-bf71ecf47ebb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907533364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_
prog_failure.907533364
Directory /workspace/1.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_regwen_during_op.1275278899
Short name T252
Test name
Test status
Simulation time 925557437 ps
CPU time 15.54 seconds
Started Jun 07 08:34:36 PM PDT 24
Finished Jun 07 08:34:58 PM PDT 24
Peak memory 217728 kb
Host smart-509e4c7f-011d-46b2-983b-6464dc80e486
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275278899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_
jtag_regwen_during_op.1275278899
Directory /workspace/1.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_smoke.4126000567
Short name T283
Test name
Test status
Simulation time 264109786 ps
CPU time 4.68 seconds
Started Jun 07 08:34:37 PM PDT 24
Finished Jun 07 08:34:48 PM PDT 24
Peak memory 217684 kb
Host smart-037574fa-6877-409f-8216-45ffce2cfec2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126000567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_smoke.
4126000567
Directory /workspace/1.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_failure.2468054571
Short name T776
Test name
Test status
Simulation time 12119654071 ps
CPU time 67.32 seconds
Started Jun 07 08:34:21 PM PDT 24
Finished Jun 07 08:35:39 PM PDT 24
Peak memory 283572 kb
Host smart-5b097977-eb10-4c4b-9f57-84cb3cd1779a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468054571 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jta
g_state_failure.2468054571
Directory /workspace/1.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_jtag_state_post_trans.864032665
Short name T528
Test name
Test status
Simulation time 2985787372 ps
CPU time 20.68 seconds
Started Jun 07 08:34:22 PM PDT 24
Finished Jun 07 08:34:53 PM PDT 24
Peak memory 250404 kb
Host smart-7e1c7532-b2fb-457a-a6c0-b41b225b3f86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864032665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_j
tag_state_post_trans.864032665
Directory /workspace/1.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_prog_failure.1325980931
Short name T573
Test name
Test status
Simulation time 201392832 ps
CPU time 2.67 seconds
Started Jun 07 08:34:30 PM PDT 24
Finished Jun 07 08:34:42 PM PDT 24
Peak memory 218244 kb
Host smart-9724cbc9-aa01-41ec-aa1b-e9375e5378c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325980931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_prog_failure.1325980931
Directory /workspace/1.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_regwen_during_op.1097254208
Short name T179
Test name
Test status
Simulation time 2778501624 ps
CPU time 17.34 seconds
Started Jun 07 08:34:33 PM PDT 24
Finished Jun 07 08:34:59 PM PDT 24
Peak memory 217844 kb
Host smart-7a8256ae-0a73-4457-bc52-d441f9bdafc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097254208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_regwen_during_op.1097254208
Directory /workspace/1.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_cm.2042097341
Short name T92
Test name
Test status
Simulation time 1103710741 ps
CPU time 40.9 seconds
Started Jun 07 08:34:27 PM PDT 24
Finished Jun 07 08:35:18 PM PDT 24
Peak memory 284184 kb
Host smart-047a80c5-0707-44d6-97b4-8bf54ef69fd1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042097341 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_cm.2042097341
Directory /workspace/1.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_digest.2400041653
Short name T230
Test name
Test status
Simulation time 1067498251 ps
CPU time 11.53 seconds
Started Jun 07 08:34:24 PM PDT 24
Finished Jun 07 08:34:47 PM PDT 24
Peak memory 226056 kb
Host smart-3648deff-1780-4e90-bd67-77d902d6fa94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400041653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_di
gest.2400041653
Directory /workspace/1.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/1.lc_ctrl_sec_token_mux.111966306
Short name T225
Test name
Test status
Simulation time 205293432 ps
CPU time 7.65 seconds
Started Jun 07 08:34:25 PM PDT 24
Finished Jun 07 08:34:43 PM PDT 24
Peak memory 218168 kb
Host smart-46a11690-3f99-47ec-b667-9cd2a199590f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111966306 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_sec_token_mux.111966306
Directory /workspace/1.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/1.lc_ctrl_security_escalation.44903844
Short name T57
Test name
Test status
Simulation time 249804444 ps
CPU time 7.22 seconds
Started Jun 07 08:34:36 PM PDT 24
Finished Jun 07 08:34:50 PM PDT 24
Peak memory 225096 kb
Host smart-e5ee7762-8301-4486-902c-67b5ba71dac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44903844 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_security_escalation.44903844
Directory /workspace/1.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/1.lc_ctrl_smoke.401490255
Short name T567
Test name
Test status
Simulation time 241842350 ps
CPU time 2.21 seconds
Started Jun 07 08:34:23 PM PDT 24
Finished Jun 07 08:34:36 PM PDT 24
Peak memory 214476 kb
Host smart-62075367-d984-4153-b377-963ffb963b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401490255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_smoke.401490255
Directory /workspace/1.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_failure.2057425659
Short name T530
Test name
Test status
Simulation time 488604352 ps
CPU time 31.59 seconds
Started Jun 07 08:34:20 PM PDT 24
Finished Jun 07 08:35:02 PM PDT 24
Peak memory 250952 kb
Host smart-0aceb12e-137c-4e41-9362-2cc999fd7474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057425659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_failure.2057425659
Directory /workspace/1.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/1.lc_ctrl_state_post_trans.3143620506
Short name T389
Test name
Test status
Simulation time 55939643 ps
CPU time 9.05 seconds
Started Jun 07 08:34:34 PM PDT 24
Finished Jun 07 08:34:51 PM PDT 24
Peak memory 250920 kb
Host smart-86636c2d-c2db-4b04-9ad7-1760018a397a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143620506 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_state_post_trans.3143620506
Directory /workspace/1.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/1.lc_ctrl_stress_all.3640946372
Short name T608
Test name
Test status
Simulation time 35318121717 ps
CPU time 167.17 seconds
Started Jun 07 08:34:32 PM PDT 24
Finished Jun 07 08:37:28 PM PDT 24
Peak memory 270944 kb
Host smart-3b4c8327-b38a-4a1b-bd42-4fb5f5518b4d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640946372 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.lc_ctrl_stress_all.3640946372
Directory /workspace/1.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1624443778
Short name T287
Test name
Test status
Simulation time 18536817 ps
CPU time 0.85 seconds
Started Jun 07 08:34:27 PM PDT 24
Finished Jun 07 08:34:38 PM PDT 24
Peak memory 211948 kb
Host smart-f8220278-ab55-4a47-b90c-7f1d95532a62
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624443778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.lc_ct
rl_volatile_unlock_smoke.1624443778
Directory /workspace/1.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_alert_test.2351334283
Short name T457
Test name
Test status
Simulation time 17581543 ps
CPU time 1.07 seconds
Started Jun 07 08:35:05 PM PDT 24
Finished Jun 07 08:35:17 PM PDT 24
Peak memory 209024 kb
Host smart-6a35c3a8-89dc-4c8c-9689-f48f58cb15b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351334283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_alert_test.2351334283
Directory /workspace/10.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.lc_ctrl_errors.121616551
Short name T537
Test name
Test status
Simulation time 439658746 ps
CPU time 12.77 seconds
Started Jun 07 08:35:06 PM PDT 24
Finished Jun 07 08:35:30 PM PDT 24
Peak memory 218284 kb
Host smart-ae26b03e-e0ea-4bd6-8569-ac87f90f9adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121616551 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_errors.121616551
Directory /workspace/10.lc_ctrl_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_access.1988546751
Short name T176
Test name
Test status
Simulation time 1418768374 ps
CPU time 4.78 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:35:32 PM PDT 24
Peak memory 217500 kb
Host smart-ada6789b-a2d3-4f80-afa0-38e17973f89f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988546751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_access.1988546751
Directory /workspace/10.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_errors.4217884615
Short name T604
Test name
Test status
Simulation time 3269488117 ps
CPU time 45.83 seconds
Started Jun 07 08:35:00 PM PDT 24
Finished Jun 07 08:35:52 PM PDT 24
Peak memory 225984 kb
Host smart-397c179f-9c84-4dc8-9bfd-2faca7fd4aaf
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217884615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_e
rrors.4217884615
Directory /workspace/10.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_prog_failure.2593615962
Short name T805
Test name
Test status
Simulation time 2832213647 ps
CPU time 12.81 seconds
Started Jun 07 08:35:03 PM PDT 24
Finished Jun 07 08:35:25 PM PDT 24
Peak memory 224676 kb
Host smart-fcace934-d056-44f9-b45d-6f037be9d740
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593615962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jta
g_prog_failure.2593615962
Directory /workspace/10.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_smoke.1142274883
Short name T273
Test name
Test status
Simulation time 94166011 ps
CPU time 1.82 seconds
Started Jun 07 08:35:02 PM PDT 24
Finished Jun 07 08:35:11 PM PDT 24
Peak memory 217752 kb
Host smart-6efe962f-d15c-4db6-a2d1-ba22a175662e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142274883 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jtag_smoke
.1142274883
Directory /workspace/10.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_failure.3688594657
Short name T160
Test name
Test status
Simulation time 3083279026 ps
CPU time 69.76 seconds
Started Jun 07 08:35:03 PM PDT 24
Finished Jun 07 08:36:21 PM PDT 24
Peak memory 275464 kb
Host smart-066e8dbb-b8da-4497-8be2-398643333867
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688594657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_jt
ag_state_failure.3688594657
Directory /workspace/10.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_jtag_state_post_trans.2217164117
Short name T285
Test name
Test status
Simulation time 298285905 ps
CPU time 12.79 seconds
Started Jun 07 08:34:51 PM PDT 24
Finished Jun 07 08:35:08 PM PDT 24
Peak memory 250824 kb
Host smart-6ae195c8-5f48-4d2e-987c-3c6a51a3095f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217164117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl
_jtag_state_post_trans.2217164117
Directory /workspace/10.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_prog_failure.2855556515
Short name T296
Test name
Test status
Simulation time 215911378 ps
CPU time 3.43 seconds
Started Jun 07 08:34:59 PM PDT 24
Finished Jun 07 08:35:09 PM PDT 24
Peak memory 218240 kb
Host smart-45760ed3-4a97-489f-a94a-ed9e62d7e48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855556515 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_prog_failure.2855556515
Directory /workspace/10.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_mubi.3081602661
Short name T743
Test name
Test status
Simulation time 645614555 ps
CPU time 13.29 seconds
Started Jun 07 08:35:05 PM PDT 24
Finished Jun 07 08:35:29 PM PDT 24
Peak memory 226096 kb
Host smart-cd4bd3e9-65db-4fed-967c-63fbee67002d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081602661 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_mubi.3081602661
Directory /workspace/10.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_digest.3894071028
Short name T310
Test name
Test status
Simulation time 1183502111 ps
CPU time 9.79 seconds
Started Jun 07 08:35:04 PM PDT 24
Finished Jun 07 08:35:24 PM PDT 24
Peak memory 225988 kb
Host smart-4e17f433-74c1-4ba8-a7f5-3b732190c803
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894071028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_d
igest.3894071028
Directory /workspace/10.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/10.lc_ctrl_sec_token_mux.1041239672
Short name T302
Test name
Test status
Simulation time 6318451817 ps
CPU time 9.14 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:28 PM PDT 24
Peak memory 226036 kb
Host smart-88e297c3-84eb-49c1-8d04-e094d024473f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041239672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_sec_token_mux.
1041239672
Directory /workspace/10.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/10.lc_ctrl_security_escalation.985369222
Short name T793
Test name
Test status
Simulation time 1011386390 ps
CPU time 6.87 seconds
Started Jun 07 08:35:06 PM PDT 24
Finished Jun 07 08:35:25 PM PDT 24
Peak memory 225076 kb
Host smart-1be921d6-2fbb-4961-91fc-6b43c03ffed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985369222 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_security_escalation.985369222
Directory /workspace/10.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/10.lc_ctrl_smoke.3961509726
Short name T497
Test name
Test status
Simulation time 214440852 ps
CPU time 1.57 seconds
Started Jun 07 08:35:03 PM PDT 24
Finished Jun 07 08:35:13 PM PDT 24
Peak memory 217744 kb
Host smart-cb2a2b7c-fc7b-4e51-9a92-d03493eb5ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961509726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_smoke.3961509726
Directory /workspace/10.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_failure.3853216538
Short name T582
Test name
Test status
Simulation time 277402013 ps
CPU time 33.23 seconds
Started Jun 07 08:34:54 PM PDT 24
Finished Jun 07 08:35:31 PM PDT 24
Peak memory 250892 kb
Host smart-cdca1204-22b8-4f6d-8486-ff87b37b37c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853216538 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_failure.3853216538
Directory /workspace/10.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/10.lc_ctrl_state_post_trans.1691606310
Short name T766
Test name
Test status
Simulation time 129546892 ps
CPU time 7.7 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:35:30 PM PDT 24
Peak memory 250984 kb
Host smart-a256cd43-cfb1-4c92-8bfb-49b98180a8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691606310 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_state_post_trans.1691606310
Directory /workspace/10.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/10.lc_ctrl_stress_all.1205845581
Short name T839
Test name
Test status
Simulation time 2048258149 ps
CPU time 54.23 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:36:14 PM PDT 24
Peak memory 226104 kb
Host smart-b6e42f51-eaad-401d-b956-3788891adef2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205845581 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
10.lc_ctrl_stress_all.1205845581
Directory /workspace/10.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.lc_ctrl_volatile_unlock_smoke.3152999720
Short name T598
Test name
Test status
Simulation time 24969349 ps
CPU time 0.91 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:19 PM PDT 24
Peak memory 211796 kb
Host smart-6ade49ce-9ba6-4f3d-9a5e-5fb889c9a909
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152999720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.lc_c
trl_volatile_unlock_smoke.3152999720
Directory /workspace/10.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_alert_test.2629092486
Short name T453
Test name
Test status
Simulation time 26844842 ps
CPU time 1 seconds
Started Jun 07 08:35:06 PM PDT 24
Finished Jun 07 08:35:18 PM PDT 24
Peak memory 209044 kb
Host smart-c697fc0f-8eaf-4706-967c-2d090caab81a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629092486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_alert_test.2629092486
Directory /workspace/11.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.lc_ctrl_errors.4272781595
Short name T172
Test name
Test status
Simulation time 194740065 ps
CPU time 7.28 seconds
Started Jun 07 08:35:05 PM PDT 24
Finished Jun 07 08:35:22 PM PDT 24
Peak memory 218224 kb
Host smart-a36f3a1d-0cb7-4b96-840c-6c3e202be8e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272781595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_errors.4272781595
Directory /workspace/11.lc_ctrl_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_access.164784935
Short name T328
Test name
Test status
Simulation time 526362492 ps
CPU time 1.47 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:27 PM PDT 24
Peak memory 217080 kb
Host smart-e9e5a314-79ef-4093-a051-8503000c9be0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=164784935 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_access.164784935
Directory /workspace/11.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_errors.171507512
Short name T863
Test name
Test status
Simulation time 5605687912 ps
CPU time 43.18 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:36:05 PM PDT 24
Peak memory 219144 kb
Host smart-37a14df3-daea-4697-b07e-03fdab623674
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171507512 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_er
rors.171507512
Directory /workspace/11.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_prog_failure.3087390542
Short name T220
Test name
Test status
Simulation time 248674491 ps
CPU time 5.19 seconds
Started Jun 07 08:35:13 PM PDT 24
Finished Jun 07 08:35:33 PM PDT 24
Peak memory 223148 kb
Host smart-b14d6d5f-4af9-42c9-8ff0-70f0995d8250
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087390542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jta
g_prog_failure.3087390542
Directory /workspace/11.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_smoke.1747375247
Short name T680
Test name
Test status
Simulation time 1207657940 ps
CPU time 7.78 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:35:35 PM PDT 24
Peak memory 217688 kb
Host smart-a8ea1fed-0623-46aa-96d5-c7545a42b139
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747375247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jtag_smoke
.1747375247
Directory /workspace/11.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_failure.2672980118
Short name T775
Test name
Test status
Simulation time 6824336626 ps
CPU time 49.86 seconds
Started Jun 07 08:35:09 PM PDT 24
Finished Jun 07 08:36:12 PM PDT 24
Peak memory 275464 kb
Host smart-93c05876-aef7-449d-99e4-9bdfbb143071
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672980118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_jt
ag_state_failure.2672980118
Directory /workspace/11.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_jtag_state_post_trans.3465771405
Short name T325
Test name
Test status
Simulation time 495389598 ps
CPU time 19.85 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:42 PM PDT 24
Peak memory 250360 kb
Host smart-3ef57539-b921-443f-be98-97ef9157dddd
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465771405 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl
_jtag_state_post_trans.3465771405
Directory /workspace/11.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_prog_failure.1674196530
Short name T751
Test name
Test status
Simulation time 15767354 ps
CPU time 1.63 seconds
Started Jun 07 08:35:10 PM PDT 24
Finished Jun 07 08:35:26 PM PDT 24
Peak memory 221600 kb
Host smart-b30a5ea7-aa16-48f6-a1e6-7ad40e54d59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674196530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_prog_failure.1674196530
Directory /workspace/11.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_mubi.1598585077
Short name T414
Test name
Test status
Simulation time 612907385 ps
CPU time 16.16 seconds
Started Jun 07 08:35:04 PM PDT 24
Finished Jun 07 08:35:32 PM PDT 24
Peak memory 226076 kb
Host smart-251e51a1-bd70-413c-8941-b2ff5d48ac23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598585077 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_mubi.1598585077
Directory /workspace/11.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_digest.1083435751
Short name T661
Test name
Test status
Simulation time 4065549786 ps
CPU time 12.1 seconds
Started Jun 07 08:35:06 PM PDT 24
Finished Jun 07 08:35:29 PM PDT 24
Peak memory 226168 kb
Host smart-59a23e96-ab9a-4136-be34-bac78c0cb558
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083435751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_d
igest.1083435751
Directory /workspace/11.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/11.lc_ctrl_sec_token_mux.1653658752
Short name T259
Test name
Test status
Simulation time 277488268 ps
CPU time 9.77 seconds
Started Jun 07 08:35:06 PM PDT 24
Finished Jun 07 08:35:27 PM PDT 24
Peak memory 226104 kb
Host smart-8c789d38-091e-4ffb-a014-cde45a2c304b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653658752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_sec_token_mux.
1653658752
Directory /workspace/11.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/11.lc_ctrl_security_escalation.718715946
Short name T639
Test name
Test status
Simulation time 889541774 ps
CPU time 7.82 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:35:35 PM PDT 24
Peak memory 224788 kb
Host smart-7661ad9d-79c7-4965-87ca-2406fa797980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718715946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_security_escalation.718715946
Directory /workspace/11.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/11.lc_ctrl_smoke.2061180830
Short name T765
Test name
Test status
Simulation time 142865965 ps
CPU time 3.3 seconds
Started Jun 07 08:35:04 PM PDT 24
Finished Jun 07 08:35:16 PM PDT 24
Peak memory 217812 kb
Host smart-9ad62db7-dc3d-4b8f-9b9f-8b3ba0d1d705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061180830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_smoke.2061180830
Directory /workspace/11.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_failure.4152463926
Short name T69
Test name
Test status
Simulation time 409662103 ps
CPU time 20.39 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:35:42 PM PDT 24
Peak memory 250932 kb
Host smart-63a73af2-b882-4757-b627-108f2c3df5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152463926 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_failure.4152463926
Directory /workspace/11.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/11.lc_ctrl_state_post_trans.434318497
Short name T829
Test name
Test status
Simulation time 62548187 ps
CPU time 7.04 seconds
Started Jun 07 08:35:05 PM PDT 24
Finished Jun 07 08:35:22 PM PDT 24
Peak memory 250916 kb
Host smart-10db7023-cc98-4e30-a7ea-92674901715f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434318497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_state_post_trans.434318497
Directory /workspace/11.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all.4166536115
Short name T332
Test name
Test status
Simulation time 3554143167 ps
CPU time 67.1 seconds
Started Jun 07 08:35:05 PM PDT 24
Finished Jun 07 08:36:22 PM PDT 24
Peak memory 275780 kb
Host smart-00dfca40-9db0-4d44-8834-7b364d927606
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166536115 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.lc_ctrl_stress_all.4166536115
Directory /workspace/11.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.281945601
Short name T153
Test name
Test status
Simulation time 70134380394 ps
CPU time 350.81 seconds
Started Jun 07 08:35:10 PM PDT 24
Finished Jun 07 08:41:14 PM PDT 24
Peak memory 333004 kb
Host smart-4abb9305-edb3-40df-9208-cf3c50c4be76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=281945601 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_stress_all_with_rand_reset.281945601
Directory /workspace/11.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.lc_ctrl_alert_test.136544435
Short name T79
Test name
Test status
Simulation time 29468793 ps
CPU time 0.89 seconds
Started Jun 07 08:35:13 PM PDT 24
Finished Jun 07 08:35:29 PM PDT 24
Peak memory 208972 kb
Host smart-4dc42144-dbbf-49d2-92db-8854b2bc7f69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136544435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_alert_test.136544435
Directory /workspace/12.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.lc_ctrl_errors.3923956610
Short name T621
Test name
Test status
Simulation time 295483995 ps
CPU time 9.85 seconds
Started Jun 07 08:35:13 PM PDT 24
Finished Jun 07 08:35:39 PM PDT 24
Peak memory 218172 kb
Host smart-9227a5b0-00ba-4a63-bc28-43ec1b3d67de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923956610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_errors.3923956610
Directory /workspace/12.lc_ctrl_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_access.1347275672
Short name T36
Test name
Test status
Simulation time 1661494491 ps
CPU time 5.66 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:25 PM PDT 24
Peak memory 217460 kb
Host smart-f686663b-499f-4fcb-8289-892981694337
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347275672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_access.1347275672
Directory /workspace/12.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_errors.3685509962
Short name T351
Test name
Test status
Simulation time 3367211887 ps
CPU time 27.04 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:47 PM PDT 24
Peak memory 226116 kb
Host smart-0ff2fc36-7bf0-4ff0-9edc-f25c95411f61
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685509962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_e
rrors.3685509962
Directory /workspace/12.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_prog_failure.4073041781
Short name T691
Test name
Test status
Simulation time 860534177 ps
CPU time 12.05 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:37 PM PDT 24
Peak memory 223996 kb
Host smart-1490bc3e-25c2-4ed9-9eba-73cb1519d36f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073041781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jta
g_prog_failure.4073041781
Directory /workspace/12.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_smoke.2016662579
Short name T494
Test name
Test status
Simulation time 781694692 ps
CPU time 10.39 seconds
Started Jun 07 08:35:05 PM PDT 24
Finished Jun 07 08:35:24 PM PDT 24
Peak memory 217680 kb
Host smart-e7f4884e-b6d7-4719-be18-9334d4d36181
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016662579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jtag_smoke
.2016662579
Directory /workspace/12.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_failure.2486944315
Short name T732
Test name
Test status
Simulation time 2153340447 ps
CPU time 39.12 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:36:05 PM PDT 24
Peak memory 250884 kb
Host smart-114a3341-45bb-4a42-a582-6bfe793a2f5c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486944315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_jt
ag_state_failure.2486944315
Directory /workspace/12.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_jtag_state_post_trans.3919842316
Short name T668
Test name
Test status
Simulation time 327765030 ps
CPU time 15.36 seconds
Started Jun 07 08:35:06 PM PDT 24
Finished Jun 07 08:35:32 PM PDT 24
Peak memory 250824 kb
Host smart-d529a461-ef90-4126-b2cf-1de8dea195ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919842316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl
_jtag_state_post_trans.3919842316
Directory /workspace/12.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_prog_failure.1517054705
Short name T436
Test name
Test status
Simulation time 173939367 ps
CPU time 3.91 seconds
Started Jun 07 08:35:10 PM PDT 24
Finished Jun 07 08:35:29 PM PDT 24
Peak memory 222476 kb
Host smart-ae99759e-7f9a-49f0-acd3-e567a164a4cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517054705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_prog_failure.1517054705
Directory /workspace/12.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_mubi.897070295
Short name T353
Test name
Test status
Simulation time 1420138725 ps
CPU time 15.9 seconds
Started Jun 07 08:35:05 PM PDT 24
Finished Jun 07 08:35:32 PM PDT 24
Peak memory 218924 kb
Host smart-1f2080ae-d249-438c-bb39-3864085374ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897070295 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_mubi.897070295
Directory /workspace/12.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_digest.508172204
Short name T526
Test name
Test status
Simulation time 623914162 ps
CPU time 9.86 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:28 PM PDT 24
Peak memory 218288 kb
Host smart-f72d1659-5382-4cdd-92ea-9d3933bf2431
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508172204 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_di
gest.508172204
Directory /workspace/12.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/12.lc_ctrl_sec_token_mux.2032469852
Short name T722
Test name
Test status
Simulation time 1097800371 ps
CPU time 7.62 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:32 PM PDT 24
Peak memory 218316 kb
Host smart-42a21eea-002d-4297-b68c-5cf235df3c37
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032469852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_sec_token_mux.
2032469852
Directory /workspace/12.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/12.lc_ctrl_security_escalation.2041868086
Short name T348
Test name
Test status
Simulation time 248209749 ps
CPU time 10.21 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:35:31 PM PDT 24
Peak memory 226100 kb
Host smart-915bc36d-d503-46d1-97cd-4a233d763f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041868086 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_security_escalation.2041868086
Directory /workspace/12.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/12.lc_ctrl_smoke.1717423158
Short name T712
Test name
Test status
Simulation time 125806480 ps
CPU time 2.28 seconds
Started Jun 07 08:35:09 PM PDT 24
Finished Jun 07 08:35:24 PM PDT 24
Peak memory 214588 kb
Host smart-5c1933d9-e659-406c-aede-7dc9eb0d0469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717423158 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_smoke.1717423158
Directory /workspace/12.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_failure.3382004291
Short name T572
Test name
Test status
Simulation time 951384636 ps
CPU time 26.19 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:35:48 PM PDT 24
Peak memory 250920 kb
Host smart-7e943b4e-14eb-46fd-a35d-cec54d7cc3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382004291 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_failure.3382004291
Directory /workspace/12.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/12.lc_ctrl_state_post_trans.1613998752
Short name T727
Test name
Test status
Simulation time 785200656 ps
CPU time 8.57 seconds
Started Jun 07 08:35:09 PM PDT 24
Finished Jun 07 08:35:31 PM PDT 24
Peak memory 250892 kb
Host smart-6f9f307c-0995-4b37-ba28-3fb1f76e49f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613998752 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_state_post_trans.1613998752
Directory /workspace/12.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/12.lc_ctrl_stress_all.3747583981
Short name T175
Test name
Test status
Simulation time 15087433365 ps
CPU time 132.39 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:37:38 PM PDT 24
Peak memory 283712 kb
Host smart-1096122c-aa40-472d-8126-9f4c8f04f469
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747583981 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
12.lc_ctrl_stress_all.3747583981
Directory /workspace/12.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.lc_ctrl_volatile_unlock_smoke.4171603325
Short name T472
Test name
Test status
Simulation time 16217365 ps
CPU time 0.92 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:26 PM PDT 24
Peak memory 212952 kb
Host smart-1a984392-b0fd-45e5-9e7d-8d4de219b2f7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171603325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.lc_c
trl_volatile_unlock_smoke.4171603325
Directory /workspace/12.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_alert_test.4175988358
Short name T98
Test name
Test status
Simulation time 19690067 ps
CPU time 0.94 seconds
Started Jun 07 08:35:10 PM PDT 24
Finished Jun 07 08:35:25 PM PDT 24
Peak memory 209004 kb
Host smart-a0477922-b551-4b28-bba7-db8eb2e9b71f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175988358 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_alert_test.4175988358
Directory /workspace/13.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.lc_ctrl_errors.3827580920
Short name T547
Test name
Test status
Simulation time 1141931632 ps
CPU time 13.94 seconds
Started Jun 07 08:35:02 PM PDT 24
Finished Jun 07 08:35:23 PM PDT 24
Peak memory 226088 kb
Host smart-5895e33d-538f-400b-bfff-8c4ca9acfba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827580920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_errors.3827580920
Directory /workspace/13.lc_ctrl_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_access.1961567008
Short name T455
Test name
Test status
Simulation time 606093269 ps
CPU time 14.66 seconds
Started Jun 07 08:35:03 PM PDT 24
Finished Jun 07 08:35:26 PM PDT 24
Peak memory 217432 kb
Host smart-6e90a20d-2c0d-4390-8a49-c4a3b6807013
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961567008 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_access.1961567008
Directory /workspace/13.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_errors.3788568440
Short name T690
Test name
Test status
Simulation time 4030702818 ps
CPU time 31.82 seconds
Started Jun 07 08:35:15 PM PDT 24
Finished Jun 07 08:36:01 PM PDT 24
Peak memory 226052 kb
Host smart-fda85425-2e4b-456b-8dd4-9d626b437fd5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788568440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_e
rrors.3788568440
Directory /workspace/13.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_prog_failure.311264435
Short name T218
Test name
Test status
Simulation time 3109900661 ps
CPU time 3.88 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:30 PM PDT 24
Peak memory 223316 kb
Host smart-f6b500b9-1a05-467d-9b1c-59147ea9cc54
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311264435 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag
_prog_failure.311264435
Directory /workspace/13.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_smoke.3240693657
Short name T493
Test name
Test status
Simulation time 131991819 ps
CPU time 4.01 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:30 PM PDT 24
Peak memory 217768 kb
Host smart-0611e473-7da8-4758-9e0e-37b85fbe1c86
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240693657 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jtag_smoke
.3240693657
Directory /workspace/13.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_failure.3028111428
Short name T777
Test name
Test status
Simulation time 1496558269 ps
CPU time 64.67 seconds
Started Jun 07 08:35:09 PM PDT 24
Finished Jun 07 08:36:27 PM PDT 24
Peak memory 267236 kb
Host smart-41fd2caf-b13b-4a8c-b9e1-3a3b010f086b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028111428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_jt
ag_state_failure.3028111428
Directory /workspace/13.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_jtag_state_post_trans.3407343392
Short name T442
Test name
Test status
Simulation time 2042987438 ps
CPU time 12.41 seconds
Started Jun 07 08:35:21 PM PDT 24
Finished Jun 07 08:35:46 PM PDT 24
Peak memory 222864 kb
Host smart-c99da0c2-f757-4948-a3f4-69a101c3ac25
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407343392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl
_jtag_state_post_trans.3407343392
Directory /workspace/13.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_prog_failure.3237327042
Short name T214
Test name
Test status
Simulation time 91891701 ps
CPU time 4.28 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:35:30 PM PDT 24
Peak memory 218276 kb
Host smart-ab644d44-6a0c-4038-97bd-e9750388cbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237327042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_prog_failure.3237327042
Directory /workspace/13.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_mubi.1465905783
Short name T166
Test name
Test status
Simulation time 885791835 ps
CPU time 18.63 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:35:45 PM PDT 24
Peak memory 218988 kb
Host smart-3dd21a94-54a7-4f66-b069-838463490ec3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465905783 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_mubi.1465905783
Directory /workspace/13.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_digest.561430579
Short name T362
Test name
Test status
Simulation time 595319536 ps
CPU time 9.29 seconds
Started Jun 07 08:35:13 PM PDT 24
Finished Jun 07 08:35:37 PM PDT 24
Peak memory 218360 kb
Host smart-a0540ed3-819d-43d9-a09d-63c990359cc3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561430579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_di
gest.561430579
Directory /workspace/13.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/13.lc_ctrl_sec_token_mux.2249775934
Short name T399
Test name
Test status
Simulation time 1520992824 ps
CPU time 7.3 seconds
Started Jun 07 08:35:06 PM PDT 24
Finished Jun 07 08:35:25 PM PDT 24
Peak memory 226108 kb
Host smart-0c36b7b0-7e52-4398-97c8-ac980b64310c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249775934 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_sec_token_mux.
2249775934
Directory /workspace/13.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/13.lc_ctrl_security_escalation.858276335
Short name T438
Test name
Test status
Simulation time 617882780 ps
CPU time 11.37 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:31 PM PDT 24
Peak memory 225408 kb
Host smart-7434c444-b16a-4f09-9e77-bc215741398a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858276335 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_security_escalation.858276335
Directory /workspace/13.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/13.lc_ctrl_smoke.3517642545
Short name T688
Test name
Test status
Simulation time 85402688 ps
CPU time 4.83 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:25 PM PDT 24
Peak memory 217876 kb
Host smart-1c23c40d-6ee5-42d8-8e91-3091af44ce12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517642545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_smoke.3517642545
Directory /workspace/13.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_failure.2433153804
Short name T495
Test name
Test status
Simulation time 1301004178 ps
CPU time 34.37 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:35:55 PM PDT 24
Peak memory 250916 kb
Host smart-a9aad829-8ce9-4605-a979-1dfdc2a21ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433153804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_failure.2433153804
Directory /workspace/13.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/13.lc_ctrl_state_post_trans.1202005892
Short name T468
Test name
Test status
Simulation time 212656101 ps
CPU time 8.4 seconds
Started Jun 07 08:35:06 PM PDT 24
Finished Jun 07 08:35:25 PM PDT 24
Peak memory 250936 kb
Host smart-fb33bc1b-ca03-4272-910a-6e4b90a4a9ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202005892 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_state_post_trans.1202005892
Directory /workspace/13.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/13.lc_ctrl_stress_all.1679351686
Short name T374
Test name
Test status
Simulation time 5177278236 ps
CPU time 122.84 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:37:24 PM PDT 24
Peak memory 267336 kb
Host smart-7850b5b6-8510-4482-b433-09af723d16d2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679351686 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
13.lc_ctrl_stress_all.1679351686
Directory /workspace/13.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.lc_ctrl_volatile_unlock_smoke.3691580197
Short name T653
Test name
Test status
Simulation time 20321057 ps
CPU time 0.93 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:19 PM PDT 24
Peak memory 211832 kb
Host smart-c8a949ca-e358-48ce-9773-b3d014cf6ce8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691580197 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.lc_c
trl_volatile_unlock_smoke.3691580197
Directory /workspace/13.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_alert_test.814352824
Short name T74
Test name
Test status
Simulation time 71058127 ps
CPU time 0.94 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:22 PM PDT 24
Peak memory 208980 kb
Host smart-a69fe075-c2e8-4e27-ada7-ad83efc708cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814352824 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_alert_test.814352824
Directory /workspace/14.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.lc_ctrl_errors.1704876594
Short name T159
Test name
Test status
Simulation time 281241443 ps
CPU time 13.61 seconds
Started Jun 07 08:35:10 PM PDT 24
Finished Jun 07 08:35:37 PM PDT 24
Peak memory 218248 kb
Host smart-238121dd-037c-43d1-a631-2dbcf662ea96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704876594 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_errors.1704876594
Directory /workspace/14.lc_ctrl_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_access.3336571397
Short name T35
Test name
Test status
Simulation time 828688467 ps
CPU time 11.7 seconds
Started Jun 07 08:35:06 PM PDT 24
Finished Jun 07 08:35:28 PM PDT 24
Peak memory 217280 kb
Host smart-432bc072-f785-4c48-bdd0-4167e51dfa5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336571397 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_access.3336571397
Directory /workspace/14.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_errors.616536150
Short name T540
Test name
Test status
Simulation time 21041432487 ps
CPU time 85.36 seconds
Started Jun 07 08:35:10 PM PDT 24
Finished Jun 07 08:36:50 PM PDT 24
Peak memory 219792 kb
Host smart-8701a48d-dd1f-46b8-add6-4510e2553784
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616536150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_er
rors.616536150
Directory /workspace/14.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_prog_failure.955220908
Short name T215
Test name
Test status
Simulation time 378624987 ps
CPU time 4.32 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:35:37 PM PDT 24
Peak memory 221760 kb
Host smart-2062dfdb-baa6-4c7a-a06f-0f8e2e0965a2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955220908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag
_prog_failure.955220908
Directory /workspace/14.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_smoke.3818115721
Short name T521
Test name
Test status
Simulation time 69780235 ps
CPU time 1.79 seconds
Started Jun 07 08:35:09 PM PDT 24
Finished Jun 07 08:35:24 PM PDT 24
Peak memory 217472 kb
Host smart-074dcc91-2ad6-4777-a47f-76ddc99c48f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818115721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jtag_smoke
.3818115721
Directory /workspace/14.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_failure.3001791207
Short name T300
Test name
Test status
Simulation time 19719429402 ps
CPU time 58.62 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:36:33 PM PDT 24
Peak memory 277012 kb
Host smart-4eb14e5d-da8b-461c-90cf-18e244fdb7ea
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001791207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_jt
ag_state_failure.3001791207
Directory /workspace/14.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_jtag_state_post_trans.1303592585
Short name T433
Test name
Test status
Simulation time 715349943 ps
CPU time 12.29 seconds
Started Jun 07 08:35:10 PM PDT 24
Finished Jun 07 08:35:37 PM PDT 24
Peak memory 250860 kb
Host smart-57f788a9-4284-424e-87e8-8863070de17d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303592585 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl
_jtag_state_post_trans.1303592585
Directory /workspace/14.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_prog_failure.2106436578
Short name T373
Test name
Test status
Simulation time 65208979 ps
CPU time 2.23 seconds
Started Jun 07 08:35:35 PM PDT 24
Finished Jun 07 08:35:45 PM PDT 24
Peak memory 218220 kb
Host smart-4219f3cb-4d43-449b-8911-d3326b7465ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106436578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_prog_failure.2106436578
Directory /workspace/14.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_mubi.2763251364
Short name T630
Test name
Test status
Simulation time 1091405848 ps
CPU time 10.67 seconds
Started Jun 07 08:35:10 PM PDT 24
Finished Jun 07 08:35:35 PM PDT 24
Peak memory 226092 kb
Host smart-629297a5-4701-428e-9cd8-4c3e4d1f65d5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763251364 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_mubi.2763251364
Directory /workspace/14.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_digest.794204773
Short name T445
Test name
Test status
Simulation time 1746718769 ps
CPU time 14.39 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:39 PM PDT 24
Peak memory 226108 kb
Host smart-47e8c1c8-05d2-472b-a250-7675ccf4ce7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794204773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_di
gest.794204773
Directory /workspace/14.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/14.lc_ctrl_sec_token_mux.1980158316
Short name T272
Test name
Test status
Simulation time 155481640 ps
CPU time 6.28 seconds
Started Jun 07 08:35:09 PM PDT 24
Finished Jun 07 08:35:29 PM PDT 24
Peak memory 218360 kb
Host smart-7c914dbb-b201-40d2-a6fc-94a582b9fa85
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980158316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_sec_token_mux.
1980158316
Directory /workspace/14.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/14.lc_ctrl_smoke.3335206135
Short name T83
Test name
Test status
Simulation time 26435350 ps
CPU time 2.17 seconds
Started Jun 07 08:35:05 PM PDT 24
Finished Jun 07 08:35:18 PM PDT 24
Peak memory 214548 kb
Host smart-b9d2ea13-eefd-4e01-872a-257726c698d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335206135 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_smoke.3335206135
Directory /workspace/14.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_failure.462512373
Short name T439
Test name
Test status
Simulation time 165532900 ps
CPU time 18.06 seconds
Started Jun 07 08:35:10 PM PDT 24
Finished Jun 07 08:35:43 PM PDT 24
Peak memory 250920 kb
Host smart-93669c32-edfc-41cd-8009-4038d62d4ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462512373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_failure.462512373
Directory /workspace/14.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/14.lc_ctrl_state_post_trans.2398884220
Short name T587
Test name
Test status
Simulation time 80227644 ps
CPU time 3.93 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:30 PM PDT 24
Peak memory 226180 kb
Host smart-0109c624-29c1-4041-84b8-7ac8a912dbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398884220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_state_post_trans.2398884220
Directory /workspace/14.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/14.lc_ctrl_volatile_unlock_smoke.337135165
Short name T161
Test name
Test status
Simulation time 195672351 ps
CPU time 0.98 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:35:23 PM PDT 24
Peak memory 213008 kb
Host smart-db869353-a701-45ca-8222-bee80ef85579
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337135165 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.lc_ct
rl_volatile_unlock_smoke.337135165
Directory /workspace/14.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_alert_test.1437617737
Short name T788
Test name
Test status
Simulation time 57370420 ps
CPU time 1.06 seconds
Started Jun 07 08:35:10 PM PDT 24
Finished Jun 07 08:35:26 PM PDT 24
Peak memory 208972 kb
Host smart-d3f068be-3f73-4e18-adfd-f711f0776afc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437617737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_alert_test.1437617737
Directory /workspace/15.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.lc_ctrl_errors.204526485
Short name T561
Test name
Test status
Simulation time 3594122703 ps
CPU time 8.79 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:34 PM PDT 24
Peak memory 219360 kb
Host smart-2bfb7b53-d240-48f4-8534-95084b2aeaf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204526485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_errors.204526485
Directory /workspace/15.lc_ctrl_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_access.102717252
Short name T402
Test name
Test status
Simulation time 228500877 ps
CPU time 1.95 seconds
Started Jun 07 08:35:09 PM PDT 24
Finished Jun 07 08:35:25 PM PDT 24
Peak memory 217204 kb
Host smart-b1c843d6-15f1-435d-b23d-1d4fc19e7d96
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102717252 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_access.102717252
Directory /workspace/15.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_errors.1286169178
Short name T655
Test name
Test status
Simulation time 2446456036 ps
CPU time 70.13 seconds
Started Jun 07 08:35:23 PM PDT 24
Finished Jun 07 08:36:45 PM PDT 24
Peak memory 219536 kb
Host smart-4d60cba7-689b-4640-ab95-b096b8f5a765
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286169178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_e
rrors.1286169178
Directory /workspace/15.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_prog_failure.3523384399
Short name T30
Test name
Test status
Simulation time 198339743 ps
CPU time 2.06 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:22 PM PDT 24
Peak memory 221568 kb
Host smart-1b745cfb-6419-4aef-974f-8b52b05fa6c0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523384399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jta
g_prog_failure.3523384399
Directory /workspace/15.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_smoke.1628322390
Short name T84
Test name
Test status
Simulation time 684851112 ps
CPU time 9.74 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:35:36 PM PDT 24
Peak memory 217712 kb
Host smart-f5bfb6ca-744f-4c12-973d-939b7b1b8ab1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628322390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_jtag_smoke
.1628322390
Directory /workspace/15.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_jtag_state_post_trans.3032736155
Short name T1
Test name
Test status
Simulation time 3704506219 ps
CPU time 16.27 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:35:38 PM PDT 24
Peak memory 245992 kb
Host smart-da4de366-c8ff-48f2-9483-9cfaf9733c8f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032736155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl
_jtag_state_post_trans.3032736155
Directory /workspace/15.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_prog_failure.2984636969
Short name T660
Test name
Test status
Simulation time 180486966 ps
CPU time 2.49 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:22 PM PDT 24
Peak memory 218208 kb
Host smart-8cb48ecf-a9ab-4b11-a50e-f72fa1a6f01b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984636969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_prog_failure.2984636969
Directory /workspace/15.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_mubi.2195274964
Short name T460
Test name
Test status
Simulation time 910913403 ps
CPU time 9.77 seconds
Started Jun 07 08:35:06 PM PDT 24
Finished Jun 07 08:35:27 PM PDT 24
Peak memory 218344 kb
Host smart-e46eb6e0-f049-48eb-b7a2-614afd6aad74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195274964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_mubi.2195274964
Directory /workspace/15.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_digest.3142388620
Short name T840
Test name
Test status
Simulation time 534823964 ps
CPU time 10.28 seconds
Started Jun 07 08:35:10 PM PDT 24
Finished Jun 07 08:35:35 PM PDT 24
Peak memory 226084 kb
Host smart-f17afd1b-2cb7-4c33-8668-9b88ee518c3c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142388620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_d
igest.3142388620
Directory /workspace/15.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/15.lc_ctrl_sec_token_mux.1316039597
Short name T276
Test name
Test status
Simulation time 525944180 ps
CPU time 7.04 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:32 PM PDT 24
Peak memory 218032 kb
Host smart-97f7d150-a5e7-4307-b6ff-3b10b91e1347
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316039597 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_sec_token_mux.
1316039597
Directory /workspace/15.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/15.lc_ctrl_security_escalation.453806312
Short name T256
Test name
Test status
Simulation time 331645494 ps
CPU time 8.11 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:35:35 PM PDT 24
Peak memory 225512 kb
Host smart-e55ee256-f03d-426b-b60d-8af164dd0e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453806312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_security_escalation.453806312
Directory /workspace/15.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/15.lc_ctrl_smoke.864854164
Short name T397
Test name
Test status
Simulation time 113046385 ps
CPU time 2.47 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:28 PM PDT 24
Peak memory 214388 kb
Host smart-7c8a4b82-537e-4a56-a601-22ba3daf2a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864854164 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_smoke.864854164
Directory /workspace/15.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_failure.548230065
Short name T463
Test name
Test status
Simulation time 2418547150 ps
CPU time 24.45 seconds
Started Jun 07 08:35:10 PM PDT 24
Finished Jun 07 08:35:49 PM PDT 24
Peak memory 250880 kb
Host smart-d236ca2f-0faa-4478-ba37-1699d99adbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548230065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_failure.548230065
Directory /workspace/15.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/15.lc_ctrl_state_post_trans.2857269255
Short name T45
Test name
Test status
Simulation time 125270305 ps
CPU time 7.57 seconds
Started Jun 07 08:35:09 PM PDT 24
Finished Jun 07 08:35:30 PM PDT 24
Peak memory 250900 kb
Host smart-e5a28fc2-dbb7-40a0-96ba-540ef57ed987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857269255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_state_post_trans.2857269255
Directory /workspace/15.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/15.lc_ctrl_stress_all.3678543584
Short name T505
Test name
Test status
Simulation time 8501816086 ps
CPU time 64.3 seconds
Started Jun 07 08:35:06 PM PDT 24
Finished Jun 07 08:36:21 PM PDT 24
Peak memory 275040 kb
Host smart-a3b86f98-7bf5-4651-a5a2-14ce0add5c75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678543584 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
15.lc_ctrl_stress_all.3678543584
Directory /workspace/15.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.lc_ctrl_volatile_unlock_smoke.951002612
Short name T774
Test name
Test status
Simulation time 65073904 ps
CPU time 0.81 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:35:30 PM PDT 24
Peak memory 211880 kb
Host smart-cde573a4-daba-454f-b224-ca9d6badb414
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951002612 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.lc_ct
rl_volatile_unlock_smoke.951002612
Directory /workspace/15.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_alert_test.2544764373
Short name T327
Test name
Test status
Simulation time 42152801 ps
CPU time 0.88 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:20 PM PDT 24
Peak memory 208944 kb
Host smart-f34760b7-f331-4016-80bd-33c3da6f3582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544764373 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_alert_test.2544764373
Directory /workspace/16.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.lc_ctrl_errors.808033484
Short name T232
Test name
Test status
Simulation time 1778373947 ps
CPU time 11.13 seconds
Started Jun 07 08:35:09 PM PDT 24
Finished Jun 07 08:35:33 PM PDT 24
Peak memory 218136 kb
Host smart-d04026a3-82e4-47b0-be34-12a1e29cf13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808033484 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_errors.808033484
Directory /workspace/16.lc_ctrl_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_access.889896649
Short name T500
Test name
Test status
Simulation time 423246221 ps
CPU time 4.9 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:35:27 PM PDT 24
Peak memory 217228 kb
Host smart-5c684c39-3a6d-4e6f-9cde-864076d512c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889896649 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_access.889896649
Directory /workspace/16.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_errors.245231323
Short name T409
Test name
Test status
Simulation time 33823529675 ps
CPU time 33.9 seconds
Started Jun 07 08:35:09 PM PDT 24
Finished Jun 07 08:35:57 PM PDT 24
Peak memory 218264 kb
Host smart-86449b11-834e-4809-8c47-58ae2ab059d3
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245231323 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_er
rors.245231323
Directory /workspace/16.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_prog_failure.4168890957
Short name T424
Test name
Test status
Simulation time 623761734 ps
CPU time 5.09 seconds
Started Jun 07 08:35:09 PM PDT 24
Finished Jun 07 08:35:28 PM PDT 24
Peak memory 221732 kb
Host smart-ef8f2533-3438-4345-af8f-bb9d1f769561
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168890957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jta
g_prog_failure.4168890957
Directory /workspace/16.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_smoke.2791336764
Short name T703
Test name
Test status
Simulation time 244743545 ps
CPU time 3.72 seconds
Started Jun 07 08:35:13 PM PDT 24
Finished Jun 07 08:35:33 PM PDT 24
Peak memory 217748 kb
Host smart-bc5f291b-f5f8-4537-88a4-7e3f70c02fa1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791336764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jtag_smoke
.2791336764
Directory /workspace/16.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_failure.2661853016
Short name T317
Test name
Test status
Simulation time 14432611697 ps
CPU time 62.24 seconds
Started Jun 07 08:35:06 PM PDT 24
Finished Jun 07 08:36:19 PM PDT 24
Peak memory 283612 kb
Host smart-f74cc962-f787-46bc-9bbf-851cf5d81547
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661853016 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_jt
ag_state_failure.2661853016
Directory /workspace/16.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_jtag_state_post_trans.3029387641
Short name T506
Test name
Test status
Simulation time 710388089 ps
CPU time 11.11 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:35:38 PM PDT 24
Peak memory 250408 kb
Host smart-b134c126-6161-46fb-90b7-eb83621f21b4
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029387641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl
_jtag_state_post_trans.3029387641
Directory /workspace/16.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_prog_failure.3202065470
Short name T510
Test name
Test status
Simulation time 257997891 ps
CPU time 2.68 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:35:24 PM PDT 24
Peak memory 218188 kb
Host smart-63b0e0c5-3f41-4aa8-a148-8bec47f81524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202065470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_prog_failure.3202065470
Directory /workspace/16.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_mubi.2888466085
Short name T682
Test name
Test status
Simulation time 357415214 ps
CPU time 9.88 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:35 PM PDT 24
Peak memory 218364 kb
Host smart-12d68e4b-fdd9-49ff-8e3a-838771167fd4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888466085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_mubi.2888466085
Directory /workspace/16.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_digest.1763787395
Short name T467
Test name
Test status
Simulation time 2122604114 ps
CPU time 9.44 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:34 PM PDT 24
Peak memory 218068 kb
Host smart-6de8772e-7c91-4dda-9a3e-c398938f3e83
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763787395 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_d
igest.1763787395
Directory /workspace/16.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/16.lc_ctrl_sec_token_mux.1949236412
Short name T365
Test name
Test status
Simulation time 1193557753 ps
CPU time 6.49 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:32 PM PDT 24
Peak memory 225248 kb
Host smart-22a3ecc6-3820-4bb8-bffc-82c4643b1af3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949236412 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_sec_token_mux.
1949236412
Directory /workspace/16.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/16.lc_ctrl_security_escalation.1671622224
Short name T314
Test name
Test status
Simulation time 1700833586 ps
CPU time 15.89 seconds
Started Jun 07 08:35:05 PM PDT 24
Finished Jun 07 08:35:32 PM PDT 24
Peak memory 225600 kb
Host smart-05c6db22-cd39-4f69-80fd-130eff86db65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671622224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_security_escalation.1671622224
Directory /workspace/16.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/16.lc_ctrl_smoke.427183945
Short name T797
Test name
Test status
Simulation time 318234723 ps
CPU time 5.45 seconds
Started Jun 07 08:35:10 PM PDT 24
Finished Jun 07 08:35:30 PM PDT 24
Peak memory 217896 kb
Host smart-b72093c1-2351-40d6-9561-066b118435b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427183945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_smoke.427183945
Directory /workspace/16.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_failure.2798851556
Short name T236
Test name
Test status
Simulation time 1007373258 ps
CPU time 25.12 seconds
Started Jun 07 08:35:10 PM PDT 24
Finished Jun 07 08:35:50 PM PDT 24
Peak memory 250892 kb
Host smart-6a02225b-2eaf-4f95-a56c-0eb6004b81f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798851556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_failure.2798851556
Directory /workspace/16.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/16.lc_ctrl_state_post_trans.3444345351
Short name T705
Test name
Test status
Simulation time 366251918 ps
CPU time 7.91 seconds
Started Jun 07 08:35:14 PM PDT 24
Finished Jun 07 08:35:37 PM PDT 24
Peak memory 250836 kb
Host smart-3f9fc095-1f23-4fcb-b799-fba5036cd748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444345351 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_state_post_trans.3444345351
Directory /workspace/16.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/16.lc_ctrl_stress_all.567334646
Short name T66
Test name
Test status
Simulation time 13566709792 ps
CPU time 299.46 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:40:31 PM PDT 24
Peak memory 267420 kb
Host smart-97dbbc23-6f53-404f-86d5-2f0adc6eb057
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567334646 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
16.lc_ctrl_stress_all.567334646
Directory /workspace/16.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3486242755
Short name T171
Test name
Test status
Simulation time 13470768 ps
CPU time 1.04 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:21 PM PDT 24
Peak memory 211836 kb
Host smart-ba7b2f6e-892c-4b11-9571-3ad7eef11345
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486242755 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.lc_c
trl_volatile_unlock_smoke.3486242755
Directory /workspace/16.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_alert_test.865684922
Short name T111
Test name
Test status
Simulation time 24553952 ps
CPU time 1.29 seconds
Started Jun 07 08:35:32 PM PDT 24
Finished Jun 07 08:35:42 PM PDT 24
Peak memory 209044 kb
Host smart-7c34083b-97d5-4e27-9bbf-e1c644c81d95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865684922 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_alert_test.865684922
Directory /workspace/17.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.lc_ctrl_errors.3622176494
Short name T687
Test name
Test status
Simulation time 769795547 ps
CPU time 13.42 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:35:40 PM PDT 24
Peak memory 218196 kb
Host smart-1503a0a4-8bf9-4dab-8521-4cdc98190a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622176494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_errors.3622176494
Directory /workspace/17.lc_ctrl_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_access.3127247221
Short name T499
Test name
Test status
Simulation time 488354561 ps
CPU time 12.75 seconds
Started Jun 07 08:35:10 PM PDT 24
Finished Jun 07 08:35:41 PM PDT 24
Peak memory 217572 kb
Host smart-b06900ed-c310-43ad-a545-9b701d9c8d58
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127247221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_access.3127247221
Directory /workspace/17.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_errors.1627024592
Short name T649
Test name
Test status
Simulation time 21659788677 ps
CPU time 40.74 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:36:07 PM PDT 24
Peak memory 218760 kb
Host smart-a4501d47-148f-4beb-9da5-953576cfbb80
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627024592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_e
rrors.1627024592
Directory /workspace/17.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_prog_failure.3332811590
Short name T536
Test name
Test status
Simulation time 431179504 ps
CPU time 3.6 seconds
Started Jun 07 08:35:14 PM PDT 24
Finished Jun 07 08:35:32 PM PDT 24
Peak memory 222692 kb
Host smart-0b73b8c0-7116-46a9-846e-d449b749d5aa
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332811590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jta
g_prog_failure.3332811590
Directory /workspace/17.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_smoke.3858716865
Short name T602
Test name
Test status
Simulation time 875134409 ps
CPU time 8.71 seconds
Started Jun 07 08:35:33 PM PDT 24
Finished Jun 07 08:35:49 PM PDT 24
Peak memory 217640 kb
Host smart-9ed83ce9-18ab-4da2-8703-815a1a558789
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858716865 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jtag_smoke
.3858716865
Directory /workspace/17.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_failure.3105556885
Short name T375
Test name
Test status
Simulation time 1371626940 ps
CPU time 38.92 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:36:01 PM PDT 24
Peak memory 267220 kb
Host smart-2966aa47-42aa-4346-a188-ed40836e3276
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105556885 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_jt
ag_state_failure.3105556885
Directory /workspace/17.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_jtag_state_post_trans.1482732265
Short name T475
Test name
Test status
Simulation time 1760681420 ps
CPU time 14.02 seconds
Started Jun 07 08:35:13 PM PDT 24
Finished Jun 07 08:35:42 PM PDT 24
Peak memory 250848 kb
Host smart-13e36ee1-7e8e-487c-a8dd-cefa1c29ebf0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482732265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl
_jtag_state_post_trans.1482732265
Directory /workspace/17.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_prog_failure.3248131758
Short name T279
Test name
Test status
Simulation time 286744960 ps
CPU time 2.68 seconds
Started Jun 07 08:35:22 PM PDT 24
Finished Jun 07 08:35:37 PM PDT 24
Peak memory 222484 kb
Host smart-2af754fa-bad6-4ed3-8ee7-041aacb2221d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248131758 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_prog_failure.3248131758
Directory /workspace/17.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_mubi.2905292452
Short name T25
Test name
Test status
Simulation time 4006719561 ps
CPU time 12.06 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:38 PM PDT 24
Peak memory 219296 kb
Host smart-6bed7ecc-facf-43b7-9672-df5167d5cf48
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905292452 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_mubi.2905292452
Directory /workspace/17.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_digest.1688109286
Short name T737
Test name
Test status
Simulation time 364889174 ps
CPU time 8.34 seconds
Started Jun 07 08:35:32 PM PDT 24
Finished Jun 07 08:35:49 PM PDT 24
Peak memory 225660 kb
Host smart-9d182518-5523-49bc-8958-d446adb8c5b0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688109286 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_d
igest.1688109286
Directory /workspace/17.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/17.lc_ctrl_sec_token_mux.3086782540
Short name T631
Test name
Test status
Simulation time 441926521 ps
CPU time 7.47 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:33 PM PDT 24
Peak memory 218180 kb
Host smart-00aaa357-ee75-4d77-b05a-02bc01dd90c0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086782540 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_sec_token_mux.
3086782540
Directory /workspace/17.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/17.lc_ctrl_security_escalation.4211259954
Short name T103
Test name
Test status
Simulation time 348833105 ps
CPU time 13.04 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:35:42 PM PDT 24
Peak memory 225068 kb
Host smart-d1cd3aeb-9ed4-45ea-a22b-a120639df911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211259954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_security_escalation.4211259954
Directory /workspace/17.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/17.lc_ctrl_smoke.1862750781
Short name T87
Test name
Test status
Simulation time 125793442 ps
CPU time 3.89 seconds
Started Jun 07 08:35:42 PM PDT 24
Finished Jun 07 08:35:52 PM PDT 24
Peak memory 217736 kb
Host smart-416740a0-eec0-4fb9-a5c2-877c9327974a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862750781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_smoke.1862750781
Directory /workspace/17.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_failure.1430523137
Short name T575
Test name
Test status
Simulation time 835143227 ps
CPU time 27.95 seconds
Started Jun 07 08:35:22 PM PDT 24
Finished Jun 07 08:36:02 PM PDT 24
Peak memory 250860 kb
Host smart-346211e3-a548-46cc-98cb-c1e6c6b3227e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430523137 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_failure.1430523137
Directory /workspace/17.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/17.lc_ctrl_state_post_trans.4257505183
Short name T778
Test name
Test status
Simulation time 104507084 ps
CPU time 7.3 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:27 PM PDT 24
Peak memory 250884 kb
Host smart-6abd4e93-95d0-48cc-8c96-154558ac94fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257505183 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_state_post_trans.4257505183
Directory /workspace/17.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all.3142183428
Short name T648
Test name
Test status
Simulation time 142466860134 ps
CPU time 366.23 seconds
Started Jun 07 08:35:28 PM PDT 24
Finished Jun 07 08:41:44 PM PDT 24
Peak memory 282332 kb
Host smart-2c0355af-74b6-472e-bf9c-86d610ccdab0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142183428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
17.lc_ctrl_stress_all.3142183428
Directory /workspace/17.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.477102404
Short name T155
Test name
Test status
Simulation time 37338628834 ps
CPU time 170.97 seconds
Started Jun 07 08:35:16 PM PDT 24
Finished Jun 07 08:38:22 PM PDT 24
Peak memory 283820 kb
Host smart-d86c2ca2-7b40-4b9a-96ea-04d3b139e01d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=477102404 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_stress_all_with_rand_reset.477102404
Directory /workspace/17.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3699480129
Short name T229
Test name
Test status
Simulation time 12673124 ps
CPU time 1.01 seconds
Started Jun 07 08:35:39 PM PDT 24
Finished Jun 07 08:35:46 PM PDT 24
Peak memory 211920 kb
Host smart-4627f33a-5239-477b-ad2a-456b8f40ffe7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699480129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.lc_c
trl_volatile_unlock_smoke.3699480129
Directory /workspace/17.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_alert_test.2471391283
Short name T304
Test name
Test status
Simulation time 86609058 ps
CPU time 0.93 seconds
Started Jun 07 08:35:22 PM PDT 24
Finished Jun 07 08:35:36 PM PDT 24
Peak memory 208844 kb
Host smart-cafe0e60-e2a8-483d-9ee6-3fb5fdee9bd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471391283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_alert_test.2471391283
Directory /workspace/18.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.lc_ctrl_errors.2566061209
Short name T513
Test name
Test status
Simulation time 644158690 ps
CPU time 11.38 seconds
Started Jun 07 08:35:13 PM PDT 24
Finished Jun 07 08:35:39 PM PDT 24
Peak memory 218280 kb
Host smart-2d401946-c9a3-4bd4-bd30-4c689ba7a1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566061209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_errors.2566061209
Directory /workspace/18.lc_ctrl_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_access.3021461527
Short name T764
Test name
Test status
Simulation time 439816138 ps
CPU time 9.7 seconds
Started Jun 07 08:35:09 PM PDT 24
Finished Jun 07 08:35:33 PM PDT 24
Peak memory 217204 kb
Host smart-3ffa57fc-df12-42b7-9fba-a4c62ff3667a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021461527 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_access.3021461527
Directory /workspace/18.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_errors.1435257717
Short name T862
Test name
Test status
Simulation time 6507756837 ps
CPU time 28.55 seconds
Started Jun 07 08:35:35 PM PDT 24
Finished Jun 07 08:36:11 PM PDT 24
Peak memory 226068 kb
Host smart-54879608-d63a-4519-964d-f3552ca6962f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435257717 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_e
rrors.1435257717
Directory /workspace/18.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_prog_failure.80306216
Short name T822
Test name
Test status
Simulation time 373203127 ps
CPU time 8.89 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:35 PM PDT 24
Peak memory 222080 kb
Host smart-e049c1a5-9a88-41e4-bbb3-ddc64892a603
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80306216 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_p
rog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_
prog_failure.80306216
Directory /workspace/18.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_smoke.2681202399
Short name T708
Test name
Test status
Simulation time 646884465 ps
CPU time 3.06 seconds
Started Jun 07 08:35:09 PM PDT 24
Finished Jun 07 08:35:26 PM PDT 24
Peak memory 217744 kb
Host smart-91eca8ac-ec9c-460f-aae9-260f38fe6cf5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681202399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jtag_smoke
.2681202399
Directory /workspace/18.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_failure.4047086915
Short name T745
Test name
Test status
Simulation time 19093314221 ps
CPU time 156.77 seconds
Started Jun 07 08:35:13 PM PDT 24
Finished Jun 07 08:38:06 PM PDT 24
Peak memory 311024 kb
Host smart-a04b6a49-cf50-4aa6-9b13-e1035197a204
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047086915 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_jt
ag_state_failure.4047086915
Directory /workspace/18.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_jtag_state_post_trans.2077254269
Short name T313
Test name
Test status
Simulation time 1121462859 ps
CPU time 9.94 seconds
Started Jun 07 08:35:10 PM PDT 24
Finished Jun 07 08:35:35 PM PDT 24
Peak memory 249280 kb
Host smart-0e375445-713d-4db7-bce8-d8f01155b02a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077254269 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl
_jtag_state_post_trans.2077254269
Directory /workspace/18.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_prog_failure.1511988430
Short name T361
Test name
Test status
Simulation time 23033415 ps
CPU time 1.68 seconds
Started Jun 07 08:35:09 PM PDT 24
Finished Jun 07 08:35:28 PM PDT 24
Peak memory 218012 kb
Host smart-44839837-718d-4416-b9ee-e541d8a95c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511988430 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_prog_failure.1511988430
Directory /workspace/18.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_mubi.60304580
Short name T335
Test name
Test status
Simulation time 578606057 ps
CPU time 13.3 seconds
Started Jun 07 08:35:09 PM PDT 24
Finished Jun 07 08:35:37 PM PDT 24
Peak memory 218932 kb
Host smart-6bb132f3-54f2-4e85-9e9a-561c0f0df866
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60304580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_mubi.60304580
Directory /workspace/18.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_digest.1440297220
Short name T841
Test name
Test status
Simulation time 466683624 ps
CPU time 12.15 seconds
Started Jun 07 08:35:14 PM PDT 24
Finished Jun 07 08:35:41 PM PDT 24
Peak memory 218300 kb
Host smart-ff0b32d4-1553-45ba-81be-f93d94367ca2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440297220 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_d
igest.1440297220
Directory /workspace/18.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/18.lc_ctrl_sec_token_mux.3353969159
Short name T509
Test name
Test status
Simulation time 333919991 ps
CPU time 11.31 seconds
Started Jun 07 08:35:22 PM PDT 24
Finished Jun 07 08:35:46 PM PDT 24
Peak memory 218212 kb
Host smart-04dfeb2d-45a9-4d40-b81f-7442368ea36c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353969159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_sec_token_mux.
3353969159
Directory /workspace/18.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/18.lc_ctrl_security_escalation.813092845
Short name T205
Test name
Test status
Simulation time 425426191 ps
CPU time 9.83 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:35:37 PM PDT 24
Peak memory 226084 kb
Host smart-5c0e204d-e97f-4601-aee1-1a7027dded11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813092845 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_security_escalation.813092845
Directory /workspace/18.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/18.lc_ctrl_smoke.224629823
Short name T620
Test name
Test status
Simulation time 28596759 ps
CPU time 1.74 seconds
Started Jun 07 08:35:14 PM PDT 24
Finished Jun 07 08:35:31 PM PDT 24
Peak memory 214036 kb
Host smart-4fada060-54e7-4df8-bd46-9478b6e1f061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224629823 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_smoke.224629823
Directory /workspace/18.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_failure.4287990876
Short name T481
Test name
Test status
Simulation time 249390301 ps
CPU time 21.06 seconds
Started Jun 07 08:35:15 PM PDT 24
Finished Jun 07 08:35:51 PM PDT 24
Peak memory 250896 kb
Host smart-b6eb76f0-e66a-4a7b-b61b-f77a8c62f387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287990876 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_failure.4287990876
Directory /workspace/18.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/18.lc_ctrl_state_post_trans.19968615
Short name T251
Test name
Test status
Simulation time 63582729 ps
CPU time 2.67 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:23 PM PDT 24
Peak memory 224028 kb
Host smart-c452bed4-ca85-4ce7-8d42-a26d333c7ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19968615 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_state_post_trans.19968615
Directory /workspace/18.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/18.lc_ctrl_stress_all.2381823009
Short name T322
Test name
Test status
Simulation time 2416179621 ps
CPU time 62.98 seconds
Started Jun 07 08:35:21 PM PDT 24
Finished Jun 07 08:36:37 PM PDT 24
Peak memory 282080 kb
Host smart-148df949-0823-4258-949a-1c74642cb933
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381823009 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
18.lc_ctrl_stress_all.2381823009
Directory /workspace/18.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.lc_ctrl_volatile_unlock_smoke.2663013140
Short name T12
Test name
Test status
Simulation time 51975966 ps
CPU time 1.08 seconds
Started Jun 07 08:35:35 PM PDT 24
Finished Jun 07 08:35:44 PM PDT 24
Peak memory 213040 kb
Host smart-d3940923-5e55-44bd-9614-c8c30e8b5f64
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663013140 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.lc_c
trl_volatile_unlock_smoke.2663013140
Directory /workspace/18.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_alert_test.3408779619
Short name T529
Test name
Test status
Simulation time 58992122 ps
CPU time 0.97 seconds
Started Jun 07 08:35:13 PM PDT 24
Finished Jun 07 08:35:29 PM PDT 24
Peak memory 208952 kb
Host smart-1b723c01-57ab-4956-b3a9-cb1d3c75c3ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408779619 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_alert_test.3408779619
Directory /workspace/19.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.lc_ctrl_errors.2634179881
Short name T570
Test name
Test status
Simulation time 516178544 ps
CPU time 14.62 seconds
Started Jun 07 08:35:16 PM PDT 24
Finished Jun 07 08:35:45 PM PDT 24
Peak memory 218300 kb
Host smart-013bec94-5ba6-4f88-a9dd-2ddea3779acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634179881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_errors.2634179881
Directory /workspace/19.lc_ctrl_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_access.1738037523
Short name T818
Test name
Test status
Simulation time 1570497783 ps
CPU time 5.17 seconds
Started Jun 07 08:35:15 PM PDT 24
Finished Jun 07 08:35:35 PM PDT 24
Peak memory 217104 kb
Host smart-9652e95a-4462-451f-81ac-7596c07b19be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738037523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_access.1738037523
Directory /workspace/19.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_errors.2103657154
Short name T278
Test name
Test status
Simulation time 3518360683 ps
CPU time 53.39 seconds
Started Jun 07 08:35:06 PM PDT 24
Finished Jun 07 08:36:10 PM PDT 24
Peak memory 226084 kb
Host smart-cdb9e722-0a55-4e9d-b8f9-aefabbda8f9e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103657154 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_e
rrors.2103657154
Directory /workspace/19.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_prog_failure.4128522184
Short name T592
Test name
Test status
Simulation time 821496903 ps
CPU time 3.4 seconds
Started Jun 07 08:35:10 PM PDT 24
Finished Jun 07 08:35:27 PM PDT 24
Peak memory 223024 kb
Host smart-218919b9-2214-42aa-853b-ad3ce013341e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128522184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jta
g_prog_failure.4128522184
Directory /workspace/19.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_smoke.1654693838
Short name T29
Test name
Test status
Simulation time 752095015 ps
CPU time 5.46 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:35:32 PM PDT 24
Peak memory 217732 kb
Host smart-7e9a7f4d-cde7-4c91-8f4d-f8558a487db0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654693838 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jtag_smoke
.1654693838
Directory /workspace/19.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_failure.2699334762
Short name T678
Test name
Test status
Simulation time 2201904620 ps
CPU time 80.77 seconds
Started Jun 07 08:35:13 PM PDT 24
Finished Jun 07 08:36:49 PM PDT 24
Peak memory 279892 kb
Host smart-78318289-83f4-4daa-9bbd-656076a8cb58
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699334762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_jt
ag_state_failure.2699334762
Directory /workspace/19.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_jtag_state_post_trans.1616869011
Short name T740
Test name
Test status
Simulation time 2226509812 ps
CPU time 24.81 seconds
Started Jun 07 08:35:15 PM PDT 24
Finished Jun 07 08:35:54 PM PDT 24
Peak memory 250772 kb
Host smart-dd2c63eb-77e9-47a9-81e4-ebd9f6d850a6
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616869011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl
_jtag_state_post_trans.1616869011
Directory /workspace/19.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_prog_failure.1408658920
Short name T421
Test name
Test status
Simulation time 167481685 ps
CPU time 3.71 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:35:25 PM PDT 24
Peak memory 222724 kb
Host smart-65331867-5897-4db7-b194-c8d0f598e783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408658920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_prog_failure.1408658920
Directory /workspace/19.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_mubi.4172206021
Short name T569
Test name
Test status
Simulation time 257747031 ps
CPU time 10.13 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:35:37 PM PDT 24
Peak memory 218920 kb
Host smart-c4b60ba7-80c1-4bdc-9fe0-ae477aefac0c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172206021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_mubi.4172206021
Directory /workspace/19.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_digest.44869460
Short name T508
Test name
Test status
Simulation time 2170924339 ps
CPU time 19.38 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:45 PM PDT 24
Peak memory 218348 kb
Host smart-40c7f179-62aa-499c-850d-a697f018453d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44869460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_dig
est.44869460
Directory /workspace/19.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/19.lc_ctrl_sec_token_mux.2314276488
Short name T577
Test name
Test status
Simulation time 250605607 ps
CPU time 9.04 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:35:30 PM PDT 24
Peak memory 226092 kb
Host smart-c2b60664-94a5-47cb-bf34-b65e1e66a236
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314276488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_sec_token_mux.
2314276488
Directory /workspace/19.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/19.lc_ctrl_security_escalation.2322098151
Short name T576
Test name
Test status
Simulation time 270274450 ps
CPU time 8.36 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:35:35 PM PDT 24
Peak memory 225400 kb
Host smart-73fda16c-d045-4d58-9bbe-7c39da9287f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322098151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_security_escalation.2322098151
Directory /workspace/19.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/19.lc_ctrl_smoke.3918573676
Short name T677
Test name
Test status
Simulation time 257081120 ps
CPU time 3.51 seconds
Started Jun 07 08:35:43 PM PDT 24
Finished Jun 07 08:35:52 PM PDT 24
Peak memory 217712 kb
Host smart-d894e45f-3f5f-4d41-b2df-aaa316a13d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918573676 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_smoke.3918573676
Directory /workspace/19.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_failure.1771909444
Short name T676
Test name
Test status
Simulation time 273824261 ps
CPU time 32.83 seconds
Started Jun 07 08:35:13 PM PDT 24
Finished Jun 07 08:36:01 PM PDT 24
Peak memory 250924 kb
Host smart-4cfa5874-d67c-4c2e-b52c-eac01be113da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771909444 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_failure.1771909444
Directory /workspace/19.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/19.lc_ctrl_state_post_trans.3757995795
Short name T545
Test name
Test status
Simulation time 294474815 ps
CPU time 9.89 seconds
Started Jun 07 08:35:15 PM PDT 24
Finished Jun 07 08:35:40 PM PDT 24
Peak memory 250956 kb
Host smart-2b9a9c55-f2bd-4688-a92d-ee5c499b5d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757995795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_state_post_trans.3757995795
Directory /workspace/19.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/19.lc_ctrl_stress_all.3103360191
Short name T656
Test name
Test status
Simulation time 8178172120 ps
CPU time 196.32 seconds
Started Jun 07 08:35:13 PM PDT 24
Finished Jun 07 08:38:44 PM PDT 24
Peak memory 249224 kb
Host smart-b65bba3c-91ea-45b7-9112-26908764b3e9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103360191 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.lc_ctrl_stress_all.3103360191
Directory /workspace/19.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.lc_ctrl_volatile_unlock_smoke.2487597287
Short name T825
Test name
Test status
Simulation time 49337185 ps
CPU time 0.92 seconds
Started Jun 07 08:35:19 PM PDT 24
Finished Jun 07 08:35:36 PM PDT 24
Peak memory 213080 kb
Host smart-6370322b-df31-45b4-ac98-522d2bfddfde
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487597287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.lc_c
trl_volatile_unlock_smoke.2487597287
Directory /workspace/19.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_alert_test.3000332111
Short name T382
Test name
Test status
Simulation time 130729490 ps
CPU time 0.92 seconds
Started Jun 07 08:34:51 PM PDT 24
Finished Jun 07 08:34:55 PM PDT 24
Peak memory 208980 kb
Host smart-9653ad01-6056-417d-a2d4-6f9221e0f4f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000332111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_alert_test.3000332111
Directory /workspace/2.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.lc_ctrl_claim_transition_if.3895321349
Short name T281
Test name
Test status
Simulation time 31839494 ps
CPU time 0.79 seconds
Started Jun 07 08:34:23 PM PDT 24
Finished Jun 07 08:34:34 PM PDT 24
Peak memory 209032 kb
Host smart-15efc17d-1ff5-4b93-9317-72768c9141a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895321349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_claim_transition_if.3895321349
Directory /workspace/2.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/2.lc_ctrl_errors.2363288946
Short name T46
Test name
Test status
Simulation time 1101828203 ps
CPU time 9.43 seconds
Started Jun 07 08:34:29 PM PDT 24
Finished Jun 07 08:34:48 PM PDT 24
Peak memory 226148 kb
Host smart-b9c60ef1-5313-4a1d-aac4-25fb60b43244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363288946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_errors.2363288946
Directory /workspace/2.lc_ctrl_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_access.1979360278
Short name T674
Test name
Test status
Simulation time 5770996805 ps
CPU time 20.54 seconds
Started Jun 07 08:34:32 PM PDT 24
Finished Jun 07 08:35:02 PM PDT 24
Peak memory 217768 kb
Host smart-e60b6264-f36c-4000-876d-bce91a3c004a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979360278 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_access.1979360278
Directory /workspace/2.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_errors.1502966343
Short name T106
Test name
Test status
Simulation time 7227826838 ps
CPU time 23.71 seconds
Started Jun 07 08:34:39 PM PDT 24
Finished Jun 07 08:35:08 PM PDT 24
Peak memory 218232 kb
Host smart-de7a5977-effb-441c-b55f-ac45fd7ef5c1
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502966343 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_er
rors.1502966343
Directory /workspace/2.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_priority.1050766637
Short name T432
Test name
Test status
Simulation time 321183370 ps
CPU time 8.36 seconds
Started Jun 07 08:34:29 PM PDT 24
Finished Jun 07 08:34:47 PM PDT 24
Peak memory 217896 kb
Host smart-cab907a7-41b0-45ac-8328-8670ac74baeb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050766637 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_priority.1
050766637
Directory /workspace/2.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_prog_failure.1798368294
Short name T697
Test name
Test status
Simulation time 7122793304 ps
CPU time 7.25 seconds
Started Jun 07 08:34:26 PM PDT 24
Finished Jun 07 08:34:44 PM PDT 24
Peak memory 223800 kb
Host smart-f121cf11-a373-41b6-bb7a-f17facc42f7a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798368294 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag
_prog_failure.1798368294
Directory /workspace/2.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_regwen_during_op.347900117
Short name T806
Test name
Test status
Simulation time 1518866715 ps
CPU time 27.34 seconds
Started Jun 07 08:34:26 PM PDT 24
Finished Jun 07 08:35:08 PM PDT 24
Peak memory 217704 kb
Host smart-50cad0c7-df21-442e-8910-5377bc03246d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347900117 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_j
tag_regwen_during_op.347900117
Directory /workspace/2.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_smoke.607030928
Short name T169
Test name
Test status
Simulation time 181902916 ps
CPU time 3.73 seconds
Started Jun 07 08:34:36 PM PDT 24
Finished Jun 07 08:34:47 PM PDT 24
Peak memory 217720 kb
Host smart-04db679c-5c4a-45e5-9dd1-2e9d48650417
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607030928 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_smoke.607030928
Directory /workspace/2.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_failure.53987385
Short name T219
Test name
Test status
Simulation time 6324141187 ps
CPU time 47.99 seconds
Started Jun 07 08:34:42 PM PDT 24
Finished Jun 07 08:35:34 PM PDT 24
Peak memory 250896 kb
Host smart-ed7becfd-a98c-4af3-8d7d-5c610001b8b2
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53987385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_s
tate_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_
state_failure.53987385
Directory /workspace/2.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_jtag_state_post_trans.1827468299
Short name T408
Test name
Test status
Simulation time 839529620 ps
CPU time 14.01 seconds
Started Jun 07 08:34:29 PM PDT 24
Finished Jun 07 08:34:53 PM PDT 24
Peak memory 226232 kb
Host smart-24b070d2-928d-4a26-991e-ea16f3f064ac
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827468299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_
jtag_state_post_trans.1827468299
Directory /workspace/2.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_prog_failure.3548892947
Short name T63
Test name
Test status
Simulation time 256249688 ps
CPU time 2.85 seconds
Started Jun 07 08:34:34 PM PDT 24
Finished Jun 07 08:34:44 PM PDT 24
Peak memory 222632 kb
Host smart-400ff4f2-8dac-45e1-b252-374131d1896f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548892947 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_prog_failure.3548892947
Directory /workspace/2.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_regwen_during_op.1836556391
Short name T199
Test name
Test status
Simulation time 545295145 ps
CPU time 9.97 seconds
Started Jun 07 08:35:00 PM PDT 24
Finished Jun 07 08:35:16 PM PDT 24
Peak memory 217784 kb
Host smart-a0ab8f0b-e0df-4ed8-857f-cca9cccfd78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836556391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_regwen_during_op.1836556391
Directory /workspace/2.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_cm.2461112159
Short name T58
Test name
Test status
Simulation time 127795420 ps
CPU time 25 seconds
Started Jun 07 08:34:39 PM PDT 24
Finished Jun 07 08:35:10 PM PDT 24
Peak memory 269052 kb
Host smart-3dc0f45d-ae12-46be-849c-1c2734a9a889
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461112159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_cm.2461112159
Directory /workspace/2.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_mubi.628945931
Short name T208
Test name
Test status
Simulation time 454654517 ps
CPU time 14.28 seconds
Started Jun 07 08:34:22 PM PDT 24
Finished Jun 07 08:34:47 PM PDT 24
Peak memory 218536 kb
Host smart-1d3da7a7-3901-4987-bbfe-910edb32a2f1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628945931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_mubi.628945931
Directory /workspace/2.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_digest.4128452941
Short name T270
Test name
Test status
Simulation time 680479748 ps
CPU time 12.79 seconds
Started Jun 07 08:34:21 PM PDT 24
Finished Jun 07 08:34:45 PM PDT 24
Peak memory 218364 kb
Host smart-cc49bea7-33a0-4df6-a4e5-285d492393db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128452941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_di
gest.4128452941
Directory /workspace/2.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/2.lc_ctrl_sec_token_mux.1568467187
Short name T504
Test name
Test status
Simulation time 456256606 ps
CPU time 10.37 seconds
Started Jun 07 08:34:28 PM PDT 24
Finished Jun 07 08:34:49 PM PDT 24
Peak memory 218364 kb
Host smart-30a08854-8853-4818-a623-28571b24900f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568467187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_sec_token_mux.1
568467187
Directory /workspace/2.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/2.lc_ctrl_security_escalation.3834239268
Short name T290
Test name
Test status
Simulation time 2147271527 ps
CPU time 7.8 seconds
Started Jun 07 08:34:27 PM PDT 24
Finished Jun 07 08:34:45 PM PDT 24
Peak memory 225092 kb
Host smart-a2dadd00-be76-4a7c-a04c-918bada3a68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834239268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_security_escalation.3834239268
Directory /workspace/2.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/2.lc_ctrl_smoke.376796776
Short name T739
Test name
Test status
Simulation time 66083179 ps
CPU time 2.35 seconds
Started Jun 07 08:34:41 PM PDT 24
Finished Jun 07 08:34:48 PM PDT 24
Peak memory 217788 kb
Host smart-8dd95e3e-3b56-40a0-bfec-979266031aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376796776 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_smoke.376796776
Directory /workspace/2.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_failure.1754217000
Short name T476
Test name
Test status
Simulation time 183577327 ps
CPU time 22.97 seconds
Started Jun 07 08:34:24 PM PDT 24
Finished Jun 07 08:34:57 PM PDT 24
Peak memory 250932 kb
Host smart-f639234d-e625-4062-bad5-c897b93c4c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754217000 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_failure.1754217000
Directory /workspace/2.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/2.lc_ctrl_state_post_trans.3049819691
Short name T794
Test name
Test status
Simulation time 314276588 ps
CPU time 6.34 seconds
Started Jun 07 08:34:34 PM PDT 24
Finished Jun 07 08:34:49 PM PDT 24
Peak memory 246176 kb
Host smart-42c4778b-a57f-475e-83eb-222bfcb8aa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049819691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_state_post_trans.3049819691
Directory /workspace/2.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all.656612523
Short name T113
Test name
Test status
Simulation time 57898866081 ps
CPU time 289.79 seconds
Started Jun 07 08:34:30 PM PDT 24
Finished Jun 07 08:39:30 PM PDT 24
Peak memory 250980 kb
Host smart-c245bcb0-9751-4605-8c2d-f7e83319f73a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656612523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.lc_ctrl_stress_all.656612523
Directory /workspace/2.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2957103870
Short name T154
Test name
Test status
Simulation time 79032716055 ps
CPU time 497.3 seconds
Started Jun 07 08:34:52 PM PDT 24
Finished Jun 07 08:43:14 PM PDT 24
Peak memory 496772 kb
Host smart-611e8772-e4e3-459d-8d9d-68234c540f57
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2957103870 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_stress_all_with_rand_reset.2957103870
Directory /workspace/2.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.lc_ctrl_volatile_unlock_smoke.4144432303
Short name T247
Test name
Test status
Simulation time 14880780 ps
CPU time 0.84 seconds
Started Jun 07 08:34:47 PM PDT 24
Finished Jun 07 08:34:51 PM PDT 24
Peak memory 211900 kb
Host smart-a7678bc0-3c24-4904-aa58-bf4d90ae59cb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144432303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.lc_ct
rl_volatile_unlock_smoke.4144432303
Directory /workspace/2.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_alert_test.1681242731
Short name T759
Test name
Test status
Simulation time 49322244 ps
CPU time 0.88 seconds
Started Jun 07 08:35:14 PM PDT 24
Finished Jun 07 08:35:30 PM PDT 24
Peak memory 208832 kb
Host smart-4eeb6150-42bd-4295-a4df-db2d610027f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681242731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_alert_test.1681242731
Directory /workspace/20.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.lc_ctrl_errors.3008897975
Short name T831
Test name
Test status
Simulation time 4385043588 ps
CPU time 11.67 seconds
Started Jun 07 08:35:16 PM PDT 24
Finished Jun 07 08:35:43 PM PDT 24
Peak memory 218532 kb
Host smart-54dc6d70-1a09-4b78-886a-9cb44eeb6f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008897975 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_errors.3008897975
Directory /workspace/20.lc_ctrl_errors/latest

Test location /workspace/coverage/default/20.lc_ctrl_jtag_access.3204953167
Short name T507
Test name
Test status
Simulation time 508368431 ps
CPU time 5.34 seconds
Started Jun 07 08:35:20 PM PDT 24
Finished Jun 07 08:35:38 PM PDT 24
Peak memory 217404 kb
Host smart-3f9128cf-edc3-4842-8da6-37663d3a1a59
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204953167 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_jtag_access.3204953167
Directory /workspace/20.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/20.lc_ctrl_prog_failure.3927278998
Short name T823
Test name
Test status
Simulation time 56155891 ps
CPU time 1.97 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:28 PM PDT 24
Peak memory 222048 kb
Host smart-38c28194-4d20-41e0-be0e-019fb3345fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927278998 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_prog_failure.3927278998
Directory /workspace/20.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_mubi.3408945882
Short name T38
Test name
Test status
Simulation time 255150361 ps
CPU time 12.94 seconds
Started Jun 07 08:35:44 PM PDT 24
Finished Jun 07 08:36:03 PM PDT 24
Peak memory 226092 kb
Host smart-079e485a-8d78-4729-8ae3-e85fa1f7a23f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408945882 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_mubi.3408945882
Directory /workspace/20.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_digest.843366261
Short name T696
Test name
Test status
Simulation time 1610589014 ps
CPU time 14.41 seconds
Started Jun 07 08:35:27 PM PDT 24
Finished Jun 07 08:35:52 PM PDT 24
Peak memory 218260 kb
Host smart-550a86e7-7648-4959-b5ae-aa665f73108e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843366261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_di
gest.843366261
Directory /workspace/20.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/20.lc_ctrl_sec_token_mux.2936006896
Short name T413
Test name
Test status
Simulation time 969729000 ps
CPU time 6.38 seconds
Started Jun 07 08:35:40 PM PDT 24
Finished Jun 07 08:35:52 PM PDT 24
Peak memory 218272 kb
Host smart-183ef7b2-d8d1-4091-bf46-10f7b444d426
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936006896 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_sec_token_mux.
2936006896
Directory /workspace/20.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/20.lc_ctrl_security_escalation.1851097386
Short name T647
Test name
Test status
Simulation time 264606965 ps
CPU time 8.22 seconds
Started Jun 07 08:35:40 PM PDT 24
Finished Jun 07 08:35:55 PM PDT 24
Peak memory 226088 kb
Host smart-4570db36-6fae-4e27-ab40-11e0b25725ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851097386 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_security_escalation.1851097386
Directory /workspace/20.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/20.lc_ctrl_smoke.2803249448
Short name T715
Test name
Test status
Simulation time 210474245 ps
CPU time 6.32 seconds
Started Jun 07 08:35:23 PM PDT 24
Finished Jun 07 08:35:41 PM PDT 24
Peak memory 217856 kb
Host smart-e3342e58-740d-4b33-9dc2-7f44b897718a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803249448 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_smoke.2803249448
Directory /workspace/20.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_failure.3071136880
Short name T741
Test name
Test status
Simulation time 379784939 ps
CPU time 26.6 seconds
Started Jun 07 08:35:13 PM PDT 24
Finished Jun 07 08:35:54 PM PDT 24
Peak memory 250940 kb
Host smart-e2e9ad7f-d63e-4730-a8fa-ef53635917d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071136880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_failure.3071136880
Directory /workspace/20.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/20.lc_ctrl_state_post_trans.470780155
Short name T206
Test name
Test status
Simulation time 66924774 ps
CPU time 8.3 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:35:29 PM PDT 24
Peak memory 250924 kb
Host smart-1ba0e2d8-829b-4e2e-bdd9-3769b3979fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470780155 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctrl_state_post_trans.470780155
Directory /workspace/20.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/20.lc_ctrl_stress_all.3224478658
Short name T735
Test name
Test status
Simulation time 1987993344 ps
CPU time 39.7 seconds
Started Jun 07 08:35:35 PM PDT 24
Finished Jun 07 08:36:22 PM PDT 24
Peak memory 250900 kb
Host smart-8e27074d-4df0-4757-ba40-e101800eb1bb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224478658 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
20.lc_ctrl_stress_all.3224478658
Directory /workspace/20.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.lc_ctrl_volatile_unlock_smoke.26636383
Short name T821
Test name
Test status
Simulation time 52019174 ps
CPU time 0.93 seconds
Started Jun 07 08:35:11 PM PDT 24
Finished Jun 07 08:35:27 PM PDT 24
Peak memory 211844 kb
Host smart-8b2179e4-d4ea-48d9-b7a5-75b22ca21bbb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26636383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vol
atile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.lc_ctr
l_volatile_unlock_smoke.26636383
Directory /workspace/20.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_alert_test.4274792120
Short name T337
Test name
Test status
Simulation time 44793310 ps
CPU time 0.91 seconds
Started Jun 07 08:35:32 PM PDT 24
Finished Jun 07 08:35:41 PM PDT 24
Peak memory 209032 kb
Host smart-20e44be5-fd4c-46b7-8c57-c022b1df85bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274792120 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_alert_test.4274792120
Directory /workspace/21.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.lc_ctrl_errors.770551611
Short name T167
Test name
Test status
Simulation time 1444596609 ps
CPU time 13.96 seconds
Started Jun 07 08:35:33 PM PDT 24
Finished Jun 07 08:35:55 PM PDT 24
Peak memory 218332 kb
Host smart-e6d4eb44-812e-42a6-a8dd-5c0b31549c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770551611 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_errors.770551611
Directory /workspace/21.lc_ctrl_errors/latest

Test location /workspace/coverage/default/21.lc_ctrl_jtag_access.590260698
Short name T636
Test name
Test status
Simulation time 1427012768 ps
CPU time 4 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:35:31 PM PDT 24
Peak memory 217124 kb
Host smart-8b2d102a-9aa4-466c-99aa-a824ac22552b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590260698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_jtag_access.590260698
Directory /workspace/21.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/21.lc_ctrl_prog_failure.2505157247
Short name T770
Test name
Test status
Simulation time 74486218 ps
CPU time 3.81 seconds
Started Jun 07 08:35:30 PM PDT 24
Finished Jun 07 08:35:43 PM PDT 24
Peak memory 222576 kb
Host smart-a8fe98eb-6bd5-4848-bd8b-ca3ca5797cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505157247 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_prog_failure.2505157247
Directory /workspace/21.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_mubi.4228564607
Short name T212
Test name
Test status
Simulation time 996876581 ps
CPU time 15.95 seconds
Started Jun 07 08:35:14 PM PDT 24
Finished Jun 07 08:35:45 PM PDT 24
Peak memory 218356 kb
Host smart-421a8151-5f2c-468d-82d5-1fcc4e68100e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228564607 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_mubi.4228564607
Directory /workspace/21.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_digest.1315962195
Short name T502
Test name
Test status
Simulation time 457075505 ps
CPU time 8.26 seconds
Started Jun 07 08:35:46 PM PDT 24
Finished Jun 07 08:36:01 PM PDT 24
Peak memory 218336 kb
Host smart-850f9231-b939-415b-b6e7-522ce86fd9d3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315962195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_d
igest.1315962195
Directory /workspace/21.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/21.lc_ctrl_sec_token_mux.4140123374
Short name T211
Test name
Test status
Simulation time 998506404 ps
CPU time 10.8 seconds
Started Jun 07 08:35:34 PM PDT 24
Finished Jun 07 08:35:52 PM PDT 24
Peak memory 226088 kb
Host smart-8c078131-ac12-4a72-b0dc-1aa8599b7810
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140123374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_sec_token_mux.
4140123374
Directory /workspace/21.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/21.lc_ctrl_security_escalation.735452371
Short name T491
Test name
Test status
Simulation time 1297091448 ps
CPU time 9.06 seconds
Started Jun 07 08:35:16 PM PDT 24
Finished Jun 07 08:35:40 PM PDT 24
Peak memory 218304 kb
Host smart-a8a31d4d-90d7-426c-8ee9-86fb36ebbc93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735452371 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_security_escalation.735452371
Directory /workspace/21.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/21.lc_ctrl_smoke.1049156141
Short name T390
Test name
Test status
Simulation time 59847991 ps
CPU time 2.33 seconds
Started Jun 07 08:35:13 PM PDT 24
Finished Jun 07 08:35:30 PM PDT 24
Peak memory 214348 kb
Host smart-80870bb7-e949-4bfc-bad6-814bcab0722d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049156141 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_smoke.1049156141
Directory /workspace/21.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_failure.3101755309
Short name T173
Test name
Test status
Simulation time 368116048 ps
CPU time 19.77 seconds
Started Jun 07 08:35:14 PM PDT 24
Finished Jun 07 08:35:49 PM PDT 24
Peak memory 250916 kb
Host smart-3a10a97e-d2e3-4187-b670-4f00495dbf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101755309 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_failure.3101755309
Directory /workspace/21.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/21.lc_ctrl_state_post_trans.1862800240
Short name T416
Test name
Test status
Simulation time 180508808 ps
CPU time 3.77 seconds
Started Jun 07 08:35:27 PM PDT 24
Finished Jun 07 08:35:41 PM PDT 24
Peak memory 222848 kb
Host smart-b154525a-58c9-408d-ba2a-238c205f6066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862800240 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_ctrl_state_post_trans.1862800240
Directory /workspace/21.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1617266123
Short name T43
Test name
Test status
Simulation time 49008467 ps
CPU time 0.81 seconds
Started Jun 07 08:35:14 PM PDT 24
Finished Jun 07 08:35:30 PM PDT 24
Peak memory 211892 kb
Host smart-a23cf643-b5cd-45f7-a557-764e1c80e57e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617266123 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.lc_c
trl_volatile_unlock_smoke.1617266123
Directory /workspace/21.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_alert_test.933701098
Short name T326
Test name
Test status
Simulation time 33985316 ps
CPU time 1.11 seconds
Started Jun 07 08:35:43 PM PDT 24
Finished Jun 07 08:35:51 PM PDT 24
Peak memory 208988 kb
Host smart-666607d6-5dd9-432a-ba9e-7ee885fc4c93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933701098 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_alert_test.933701098
Directory /workspace/22.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.lc_ctrl_errors.3310217946
Short name T359
Test name
Test status
Simulation time 811312506 ps
CPU time 8.41 seconds
Started Jun 07 08:35:41 PM PDT 24
Finished Jun 07 08:35:56 PM PDT 24
Peak memory 218156 kb
Host smart-170c17c2-c6b4-424c-93c9-cbb479cdcf74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310217946 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_errors.3310217946
Directory /workspace/22.lc_ctrl_errors/latest

Test location /workspace/coverage/default/22.lc_ctrl_jtag_access.107363263
Short name T420
Test name
Test status
Simulation time 418408364 ps
CPU time 4.39 seconds
Started Jun 07 08:35:15 PM PDT 24
Finished Jun 07 08:35:34 PM PDT 24
Peak memory 217180 kb
Host smart-693bf643-6a01-4acb-a3b6-e3d79d58c4db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107363263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_jtag_access.107363263
Directory /workspace/22.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/22.lc_ctrl_prog_failure.2201205779
Short name T224
Test name
Test status
Simulation time 386806704 ps
CPU time 4 seconds
Started Jun 07 08:35:16 PM PDT 24
Finished Jun 07 08:35:35 PM PDT 24
Peak memory 218212 kb
Host smart-151e707b-70aa-4b12-968c-147762c627c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201205779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_prog_failure.2201205779
Directory /workspace/22.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_mubi.2822340525
Short name T385
Test name
Test status
Simulation time 357853136 ps
CPU time 12.78 seconds
Started Jun 07 08:35:28 PM PDT 24
Finished Jun 07 08:35:51 PM PDT 24
Peak memory 218976 kb
Host smart-b6756b57-732d-4b8b-977f-114a321acad1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822340525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_mubi.2822340525
Directory /workspace/22.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_digest.1258147127
Short name T673
Test name
Test status
Simulation time 459207245 ps
CPU time 18.01 seconds
Started Jun 07 08:35:34 PM PDT 24
Finished Jun 07 08:36:00 PM PDT 24
Peak memory 218400 kb
Host smart-1add9f3c-5562-4dbb-8a66-0c240fd0418b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258147127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_d
igest.1258147127
Directory /workspace/22.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/22.lc_ctrl_sec_token_mux.1888760647
Short name T800
Test name
Test status
Simulation time 1255399435 ps
CPU time 11.8 seconds
Started Jun 07 08:35:14 PM PDT 24
Finished Jun 07 08:35:40 PM PDT 24
Peak memory 218268 kb
Host smart-b4841fae-3ea5-4c62-8d4f-31f8e02ea1aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888760647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_sec_token_mux.
1888760647
Directory /workspace/22.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/22.lc_ctrl_security_escalation.3462319044
Short name T617
Test name
Test status
Simulation time 1214680555 ps
CPU time 10.42 seconds
Started Jun 07 08:35:34 PM PDT 24
Finished Jun 07 08:35:52 PM PDT 24
Peak memory 218300 kb
Host smart-cffcdbbb-6027-42f5-a0ee-231553339062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462319044 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_security_escalation.3462319044
Directory /workspace/22.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/22.lc_ctrl_smoke.4158304112
Short name T400
Test name
Test status
Simulation time 112447929 ps
CPU time 2.63 seconds
Started Jun 07 08:35:16 PM PDT 24
Finished Jun 07 08:35:34 PM PDT 24
Peak memory 215048 kb
Host smart-0edea5dc-3942-4fcf-b3db-2370e67594be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158304112 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_smoke.4158304112
Directory /workspace/22.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_failure.2371330399
Short name T164
Test name
Test status
Simulation time 321884333 ps
CPU time 40.11 seconds
Started Jun 07 08:35:21 PM PDT 24
Finished Jun 07 08:36:13 PM PDT 24
Peak memory 250968 kb
Host smart-66c1797e-723a-48c9-826c-eb5de0a8b6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371330399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_failure.2371330399
Directory /workspace/22.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/22.lc_ctrl_state_post_trans.27822602
Short name T346
Test name
Test status
Simulation time 316470226 ps
CPU time 9 seconds
Started Jun 07 08:35:29 PM PDT 24
Finished Jun 07 08:35:48 PM PDT 24
Peak memory 250912 kb
Host smart-37f502cb-010a-4e6a-ae2a-f695971c41aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27822602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ctrl_state_post_trans.27822602
Directory /workspace/22.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/22.lc_ctrl_stress_all.3951597742
Short name T851
Test name
Test status
Simulation time 4098128883 ps
CPU time 54.86 seconds
Started Jun 07 08:35:33 PM PDT 24
Finished Jun 07 08:36:36 PM PDT 24
Peak memory 266360 kb
Host smart-6ecad414-bcc7-4168-95db-1739856f0c17
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951597742 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
22.lc_ctrl_stress_all.3951597742
Directory /workspace/22.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.lc_ctrl_volatile_unlock_smoke.846262683
Short name T859
Test name
Test status
Simulation time 26404407 ps
CPU time 0.91 seconds
Started Jun 07 08:35:16 PM PDT 24
Finished Jun 07 08:35:32 PM PDT 24
Peak memory 211960 kb
Host smart-9a0e1c40-7420-40fb-b1f1-3a782209bf4b
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846262683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.lc_ct
rl_volatile_unlock_smoke.846262683
Directory /workspace/22.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_alert_test.788356499
Short name T832
Test name
Test status
Simulation time 91637560 ps
CPU time 1.01 seconds
Started Jun 07 08:35:29 PM PDT 24
Finished Jun 07 08:35:39 PM PDT 24
Peak memory 208988 kb
Host smart-a1eaee4f-eb82-45c1-9f44-defa22e68272
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788356499 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_alert_test.788356499
Directory /workspace/23.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.lc_ctrl_errors.3146388969
Short name T412
Test name
Test status
Simulation time 1740049048 ps
CPU time 18.06 seconds
Started Jun 07 08:35:15 PM PDT 24
Finished Jun 07 08:35:48 PM PDT 24
Peak memory 218248 kb
Host smart-074cfb33-e72c-4a7f-b109-19201860f208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146388969 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_errors.3146388969
Directory /workspace/23.lc_ctrl_errors/latest

Test location /workspace/coverage/default/23.lc_ctrl_jtag_access.251537525
Short name T846
Test name
Test status
Simulation time 264140269 ps
CPU time 7.55 seconds
Started Jun 07 08:35:15 PM PDT 24
Finished Jun 07 08:35:37 PM PDT 24
Peak memory 217256 kb
Host smart-580d5150-c623-4451-95f3-a57278cb685e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251537525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_jtag_access.251537525
Directory /workspace/23.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/23.lc_ctrl_prog_failure.2718334282
Short name T458
Test name
Test status
Simulation time 246705095 ps
CPU time 2.76 seconds
Started Jun 07 08:35:13 PM PDT 24
Finished Jun 07 08:35:31 PM PDT 24
Peak memory 218232 kb
Host smart-c6c295ad-283a-4b8f-891c-f78d8fa9e832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718334282 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_prog_failure.2718334282
Directory /workspace/23.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_mubi.3505378108
Short name T403
Test name
Test status
Simulation time 477373405 ps
CPU time 8.97 seconds
Started Jun 07 08:35:42 PM PDT 24
Finished Jun 07 08:35:57 PM PDT 24
Peak memory 218288 kb
Host smart-58e8fc0b-5178-4a43-88e0-08545eb02637
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505378108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_mubi.3505378108
Directory /workspace/23.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/23.lc_ctrl_sec_token_digest.967340080
Short name T452
Test name
Test status
Simulation time 373863743 ps
CPU time 11.51 seconds
Started Jun 07 08:35:39 PM PDT 24
Finished Jun 07 08:35:57 PM PDT 24
Peak memory 218292 kb
Host smart-6efada9a-12f5-4b7a-8532-594eb078dd05
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967340080 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_sec_token_di
gest.967340080
Directory /workspace/23.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/23.lc_ctrl_security_escalation.2787291136
Short name T813
Test name
Test status
Simulation time 236455180 ps
CPU time 9.01 seconds
Started Jun 07 08:35:19 PM PDT 24
Finished Jun 07 08:35:41 PM PDT 24
Peak memory 224944 kb
Host smart-d479216a-8949-4a53-a9dc-df3d5a07a1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787291136 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_security_escalation.2787291136
Directory /workspace/23.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/23.lc_ctrl_smoke.1078872996
Short name T544
Test name
Test status
Simulation time 45728690 ps
CPU time 1.75 seconds
Started Jun 07 08:35:40 PM PDT 24
Finished Jun 07 08:35:48 PM PDT 24
Peak memory 214208 kb
Host smart-94ce21f6-4876-4294-a42f-ab721532d84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078872996 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_smoke.1078872996
Directory /workspace/23.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_failure.1184045779
Short name T675
Test name
Test status
Simulation time 1510839583 ps
CPU time 31.86 seconds
Started Jun 07 08:35:16 PM PDT 24
Finished Jun 07 08:36:03 PM PDT 24
Peak memory 250876 kb
Host smart-4f7c0fcb-b608-40cf-a2f0-2b71ef656681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184045779 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_failure.1184045779
Directory /workspace/23.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/23.lc_ctrl_state_post_trans.3777708010
Short name T519
Test name
Test status
Simulation time 432222120 ps
CPU time 4.66 seconds
Started Jun 07 08:35:36 PM PDT 24
Finished Jun 07 08:35:47 PM PDT 24
Peak memory 222396 kb
Host smart-946c4dd7-e03d-46b4-baa3-b4f88ceea141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777708010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ctrl_state_post_trans.3777708010
Directory /workspace/23.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/23.lc_ctrl_stress_all.3243170829
Short name T814
Test name
Test status
Simulation time 2299689841 ps
CPU time 57.16 seconds
Started Jun 07 08:35:49 PM PDT 24
Finished Jun 07 08:36:52 PM PDT 24
Peak memory 249704 kb
Host smart-eb2b3e7e-c670-48e6-8d53-08949d2b2b60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243170829 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
23.lc_ctrl_stress_all.3243170829
Directory /workspace/23.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.lc_ctrl_volatile_unlock_smoke.611538488
Short name T102
Test name
Test status
Simulation time 11844595 ps
CPU time 1.01 seconds
Started Jun 07 08:35:40 PM PDT 24
Finished Jun 07 08:35:47 PM PDT 24
Peak memory 211952 kb
Host smart-891061f6-012b-48b1-be76-6b1a35f8721d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611538488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.lc_ct
rl_volatile_unlock_smoke.611538488
Directory /workspace/23.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_alert_test.3061924799
Short name T654
Test name
Test status
Simulation time 61713778 ps
CPU time 0.79 seconds
Started Jun 07 08:35:41 PM PDT 24
Finished Jun 07 08:35:48 PM PDT 24
Peak memory 209036 kb
Host smart-b75a3742-2109-42fc-bba2-8449c1a1e7c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061924799 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_alert_test.3061924799
Directory /workspace/24.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.lc_ctrl_errors.3161642830
Short name T363
Test name
Test status
Simulation time 277839198 ps
CPU time 10.73 seconds
Started Jun 07 08:35:42 PM PDT 24
Finished Jun 07 08:35:59 PM PDT 24
Peak memory 218256 kb
Host smart-1433d058-02a8-46a6-a00e-7243fe990d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161642830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_errors.3161642830
Directory /workspace/24.lc_ctrl_errors/latest

Test location /workspace/coverage/default/24.lc_ctrl_prog_failure.1975134492
Short name T344
Test name
Test status
Simulation time 43318127 ps
CPU time 1.47 seconds
Started Jun 07 08:35:42 PM PDT 24
Finished Jun 07 08:35:49 PM PDT 24
Peak memory 221568 kb
Host smart-c8dfc3e8-5e5d-40c8-ba51-681db115ea4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975134492 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_prog_failure.1975134492
Directory /workspace/24.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_mubi.3216595642
Short name T338
Test name
Test status
Simulation time 202222973 ps
CPU time 10.5 seconds
Started Jun 07 08:35:28 PM PDT 24
Finished Jun 07 08:35:48 PM PDT 24
Peak memory 226092 kb
Host smart-47ea168c-f7e2-4646-8f8c-2b8d58fe83fc
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216595642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_mubi.3216595642
Directory /workspace/24.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_digest.466873653
Short name T812
Test name
Test status
Simulation time 1155045822 ps
CPU time 16.63 seconds
Started Jun 07 08:35:29 PM PDT 24
Finished Jun 07 08:35:55 PM PDT 24
Peak memory 218288 kb
Host smart-81844b01-4011-4106-8b2a-226cb44ed049
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466873653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_di
gest.466873653
Directory /workspace/24.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/24.lc_ctrl_sec_token_mux.2278290605
Short name T638
Test name
Test status
Simulation time 344103491 ps
CPU time 9.01 seconds
Started Jun 07 08:35:40 PM PDT 24
Finished Jun 07 08:35:55 PM PDT 24
Peak memory 226132 kb
Host smart-0a30deb3-79cb-4e63-b5ab-c1cb971bc73b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278290605 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_sec_token_mux.
2278290605
Directory /workspace/24.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/24.lc_ctrl_security_escalation.3893011655
Short name T664
Test name
Test status
Simulation time 1154062634 ps
CPU time 11.47 seconds
Started Jun 07 08:35:40 PM PDT 24
Finished Jun 07 08:35:57 PM PDT 24
Peak memory 225412 kb
Host smart-f32d93bb-3156-470c-8cd7-24504dae2587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893011655 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_security_escalation.3893011655
Directory /workspace/24.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/24.lc_ctrl_smoke.798877219
Short name T490
Test name
Test status
Simulation time 228152982 ps
CPU time 2.54 seconds
Started Jun 07 08:35:24 PM PDT 24
Finished Jun 07 08:35:38 PM PDT 24
Peak memory 214516 kb
Host smart-70fe7bb7-95d4-404c-99c4-08851f038a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798877219 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_smoke.798877219
Directory /workspace/24.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_failure.2021390918
Short name T258
Test name
Test status
Simulation time 452949770 ps
CPU time 18.88 seconds
Started Jun 07 08:35:35 PM PDT 24
Finished Jun 07 08:36:01 PM PDT 24
Peak memory 250832 kb
Host smart-f6ae82f2-55f1-4d7b-a50f-875f42379a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021390918 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_failure.2021390918
Directory /workspace/24.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/24.lc_ctrl_state_post_trans.3087917227
Short name T552
Test name
Test status
Simulation time 95330449 ps
CPU time 3.39 seconds
Started Jun 07 08:35:17 PM PDT 24
Finished Jun 07 08:35:35 PM PDT 24
Peak memory 222160 kb
Host smart-21c70ca0-71a7-46f3-97a6-c243083e8c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087917227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_ctrl_state_post_trans.3087917227
Directory /workspace/24.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/24.lc_ctrl_stress_all.278235408
Short name T62
Test name
Test status
Simulation time 16208625385 ps
CPU time 86.01 seconds
Started Jun 07 08:35:47 PM PDT 24
Finished Jun 07 08:37:19 PM PDT 24
Peak memory 250980 kb
Host smart-004429b2-7537-41a9-8bff-3e65cedde37f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278235408 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
24.lc_ctrl_stress_all.278235408
Directory /workspace/24.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.lc_ctrl_volatile_unlock_smoke.3421952072
Short name T515
Test name
Test status
Simulation time 19329337 ps
CPU time 0.84 seconds
Started Jun 07 08:35:15 PM PDT 24
Finished Jun 07 08:35:30 PM PDT 24
Peak memory 211892 kb
Host smart-fbb9dea5-4d71-4053-9b9d-3f5234bdcf98
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421952072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.lc_c
trl_volatile_unlock_smoke.3421952072
Directory /workspace/24.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_alert_test.1667615350
Short name T618
Test name
Test status
Simulation time 30949015 ps
CPU time 0.9 seconds
Started Jun 07 08:35:39 PM PDT 24
Finished Jun 07 08:35:46 PM PDT 24
Peak memory 208976 kb
Host smart-11b91d81-7e03-4e8d-8939-b29e80cedc94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667615350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_alert_test.1667615350
Directory /workspace/25.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.lc_ctrl_errors.2173884580
Short name T670
Test name
Test status
Simulation time 3530686019 ps
CPU time 14.31 seconds
Started Jun 07 08:35:44 PM PDT 24
Finished Jun 07 08:36:05 PM PDT 24
Peak memory 218376 kb
Host smart-629ba094-ae42-41e3-9a5c-ddbc6c3e5948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173884580 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_errors.2173884580
Directory /workspace/25.lc_ctrl_errors/latest

Test location /workspace/coverage/default/25.lc_ctrl_jtag_access.2317261589
Short name T607
Test name
Test status
Simulation time 2885569236 ps
CPU time 4.33 seconds
Started Jun 07 08:35:36 PM PDT 24
Finished Jun 07 08:35:47 PM PDT 24
Peak memory 217664 kb
Host smart-c14f0bb2-ebba-4b02-9a18-9dab3bd7c9c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317261589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_jtag_access.2317261589
Directory /workspace/25.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/25.lc_ctrl_prog_failure.1990035773
Short name T750
Test name
Test status
Simulation time 80881314 ps
CPU time 1.57 seconds
Started Jun 07 08:35:42 PM PDT 24
Finished Jun 07 08:35:49 PM PDT 24
Peak memory 222028 kb
Host smart-78c13510-a0e3-42a4-b621-b2ff7bcf1ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990035773 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_prog_failure.1990035773
Directory /workspace/25.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_mubi.4197452750
Short name T336
Test name
Test status
Simulation time 249684769 ps
CPU time 8.19 seconds
Started Jun 07 08:35:41 PM PDT 24
Finished Jun 07 08:35:55 PM PDT 24
Peak memory 218960 kb
Host smart-de7b4071-8f14-4720-9545-854e40f11da8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197452750 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_mubi.4197452750
Directory /workspace/25.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_digest.3943922413
Short name T213
Test name
Test status
Simulation time 389839463 ps
CPU time 7.48 seconds
Started Jun 07 08:35:40 PM PDT 24
Finished Jun 07 08:35:53 PM PDT 24
Peak memory 226092 kb
Host smart-fbbd5a78-ae95-45e5-b1db-d6012d4e11e4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943922413 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_d
igest.3943922413
Directory /workspace/25.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/25.lc_ctrl_sec_token_mux.952410577
Short name T642
Test name
Test status
Simulation time 1338366743 ps
CPU time 12.19 seconds
Started Jun 07 08:35:33 PM PDT 24
Finished Jun 07 08:35:53 PM PDT 24
Peak memory 226064 kb
Host smart-6284fc84-97bb-47bf-a7e4-8302fdacfa23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952410577 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_sec_token_mux.952410577
Directory /workspace/25.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/25.lc_ctrl_security_escalation.809490084
Short name T384
Test name
Test status
Simulation time 1110887714 ps
CPU time 7.6 seconds
Started Jun 07 08:35:46 PM PDT 24
Finished Jun 07 08:36:00 PM PDT 24
Peak memory 225476 kb
Host smart-c2a9438a-a287-4842-96e1-502addc0160b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809490084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_security_escalation.809490084
Directory /workspace/25.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/25.lc_ctrl_smoke.3035495124
Short name T341
Test name
Test status
Simulation time 85199598 ps
CPU time 1.29 seconds
Started Jun 07 08:35:46 PM PDT 24
Finished Jun 07 08:35:53 PM PDT 24
Peak memory 213772 kb
Host smart-b08499bd-76eb-4ade-8bcc-92d41f6e582e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035495124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_smoke.3035495124
Directory /workspace/25.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_failure.3353625786
Short name T597
Test name
Test status
Simulation time 1150470794 ps
CPU time 19.33 seconds
Started Jun 07 08:35:40 PM PDT 24
Finished Jun 07 08:36:06 PM PDT 24
Peak memory 250996 kb
Host smart-82fd7550-94af-4fc4-b2e3-a89a5ed13292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353625786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_failure.3353625786
Directory /workspace/25.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/25.lc_ctrl_state_post_trans.4141463176
Short name T305
Test name
Test status
Simulation time 610885613 ps
CPU time 7.54 seconds
Started Jun 07 08:35:40 PM PDT 24
Finished Jun 07 08:35:54 PM PDT 24
Peak memory 250484 kb
Host smart-c3d46457-7ddd-403e-9887-1b9d47c9a45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141463176 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_ctrl_state_post_trans.4141463176
Directory /workspace/25.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/25.lc_ctrl_stress_all.2158278178
Short name T731
Test name
Test status
Simulation time 7029774940 ps
CPU time 218.09 seconds
Started Jun 07 08:35:38 PM PDT 24
Finished Jun 07 08:39:22 PM PDT 24
Peak memory 274488 kb
Host smart-02db2685-e437-4308-a680-cd2ead71a854
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158278178 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
25.lc_ctrl_stress_all.2158278178
Directory /workspace/25.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.lc_ctrl_volatile_unlock_smoke.4064329407
Short name T68
Test name
Test status
Simulation time 11409112 ps
CPU time 1 seconds
Started Jun 07 08:35:21 PM PDT 24
Finished Jun 07 08:35:35 PM PDT 24
Peak memory 211872 kb
Host smart-7e0573ca-005e-4a28-88eb-ed5c524b3cb8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064329407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.lc_c
trl_volatile_unlock_smoke.4064329407
Directory /workspace/25.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_alert_test.2306609568
Short name T39
Test name
Test status
Simulation time 53136119 ps
CPU time 0.91 seconds
Started Jun 07 08:35:43 PM PDT 24
Finished Jun 07 08:35:50 PM PDT 24
Peak memory 208984 kb
Host smart-1887c40a-4347-4eba-95a4-9b47b54c1174
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306609568 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_alert_test.2306609568
Directory /workspace/26.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.lc_ctrl_errors.4094854453
Short name T855
Test name
Test status
Simulation time 376127002 ps
CPU time 10.67 seconds
Started Jun 07 08:35:33 PM PDT 24
Finished Jun 07 08:35:52 PM PDT 24
Peak memory 218236 kb
Host smart-9c253075-153f-4dab-9bc9-3397daa1bf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094854453 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_errors.4094854453
Directory /workspace/26.lc_ctrl_errors/latest

Test location /workspace/coverage/default/26.lc_ctrl_jtag_access.2339031530
Short name T756
Test name
Test status
Simulation time 203516463 ps
CPU time 3.73 seconds
Started Jun 07 08:35:39 PM PDT 24
Finished Jun 07 08:35:49 PM PDT 24
Peak memory 217084 kb
Host smart-43ada761-0dee-4e79-940d-294841ac3ed1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339031530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_jtag_access.2339031530
Directory /workspace/26.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/26.lc_ctrl_prog_failure.3299216015
Short name T387
Test name
Test status
Simulation time 25020898 ps
CPU time 1.99 seconds
Started Jun 07 08:35:43 PM PDT 24
Finished Jun 07 08:35:51 PM PDT 24
Peak memory 222044 kb
Host smart-10bd0ea6-c782-463b-a2fa-8791f31c23fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299216015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_prog_failure.3299216015
Directory /workspace/26.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_mubi.463470470
Short name T854
Test name
Test status
Simulation time 308928225 ps
CPU time 10.45 seconds
Started Jun 07 08:35:40 PM PDT 24
Finished Jun 07 08:35:56 PM PDT 24
Peak memory 218300 kb
Host smart-50add487-1575-4b41-8d22-3928bfd210aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463470470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_mubi.463470470
Directory /workspace/26.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_digest.2459098672
Short name T716
Test name
Test status
Simulation time 1874872767 ps
CPU time 18.36 seconds
Started Jun 07 08:35:44 PM PDT 24
Finished Jun 07 08:36:09 PM PDT 24
Peak memory 226084 kb
Host smart-e894b9b2-4592-4455-ab02-656557cfd086
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459098672 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_d
igest.2459098672
Directory /workspace/26.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/26.lc_ctrl_sec_token_mux.1271765486
Short name T318
Test name
Test status
Simulation time 214714662 ps
CPU time 8.24 seconds
Started Jun 07 08:35:40 PM PDT 24
Finished Jun 07 08:35:55 PM PDT 24
Peak memory 218312 kb
Host smart-4b25c8ae-22c7-4813-8cf8-fcd9e7b7ed92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271765486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_sec_token_mux.
1271765486
Directory /workspace/26.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/26.lc_ctrl_security_escalation.2146303554
Short name T684
Test name
Test status
Simulation time 1625314153 ps
CPU time 9.79 seconds
Started Jun 07 08:35:36 PM PDT 24
Finished Jun 07 08:35:52 PM PDT 24
Peak memory 225432 kb
Host smart-66a9b063-1949-4a4c-8290-e389830fb784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146303554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_security_escalation.2146303554
Directory /workspace/26.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/26.lc_ctrl_smoke.647672362
Short name T692
Test name
Test status
Simulation time 65742501 ps
CPU time 3.91 seconds
Started Jun 07 08:35:43 PM PDT 24
Finished Jun 07 08:35:53 PM PDT 24
Peak memory 217780 kb
Host smart-371bfc12-4deb-444a-a58c-461f1663d2f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=647672362 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_smoke.647672362
Directory /workspace/26.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_failure.2150176296
Short name T746
Test name
Test status
Simulation time 1242323000 ps
CPU time 28.46 seconds
Started Jun 07 08:35:38 PM PDT 24
Finished Jun 07 08:36:13 PM PDT 24
Peak memory 250764 kb
Host smart-1fdf45ba-52b9-4c6c-824f-509c1805713b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150176296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_failure.2150176296
Directory /workspace/26.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/26.lc_ctrl_state_post_trans.225019852
Short name T517
Test name
Test status
Simulation time 185977440 ps
CPU time 7.64 seconds
Started Jun 07 08:35:29 PM PDT 24
Finished Jun 07 08:35:46 PM PDT 24
Peak memory 250836 kb
Host smart-d70da8dc-fbb1-45e8-837b-17ce8c4566d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225019852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_ctrl_state_post_trans.225019852
Directory /workspace/26.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/26.lc_ctrl_stress_all.2344063590
Short name T81
Test name
Test status
Simulation time 3277871764 ps
CPU time 92.4 seconds
Started Jun 07 08:35:41 PM PDT 24
Finished Jun 07 08:37:20 PM PDT 24
Peak memory 250968 kb
Host smart-f9fd0997-32ca-4bf2-b670-2a786e8d3693
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344063590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
26.lc_ctrl_stress_all.2344063590
Directory /workspace/26.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2606147488
Short name T480
Test name
Test status
Simulation time 13296926 ps
CPU time 1.06 seconds
Started Jun 07 08:35:43 PM PDT 24
Finished Jun 07 08:35:51 PM PDT 24
Peak memory 211928 kb
Host smart-130af8af-e238-41d0-9b16-91f25f37a22d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606147488 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.lc_c
trl_volatile_unlock_smoke.2606147488
Directory /workspace/26.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_alert_test.2676466150
Short name T769
Test name
Test status
Simulation time 33143952 ps
CPU time 0.87 seconds
Started Jun 07 08:35:39 PM PDT 24
Finished Jun 07 08:35:45 PM PDT 24
Peak memory 209016 kb
Host smart-21788ed0-260f-42a6-94bf-281bf56da9df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676466150 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_alert_test.2676466150
Directory /workspace/27.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.lc_ctrl_errors.1783353107
Short name T54
Test name
Test status
Simulation time 327911718 ps
CPU time 13.7 seconds
Started Jun 07 08:35:42 PM PDT 24
Finished Jun 07 08:36:02 PM PDT 24
Peak memory 218268 kb
Host smart-4f22a623-ddb9-46f5-a2b6-539eefa3e535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783353107 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_errors.1783353107
Directory /workspace/27.lc_ctrl_errors/latest

Test location /workspace/coverage/default/27.lc_ctrl_jtag_access.415242602
Short name T489
Test name
Test status
Simulation time 794108405 ps
CPU time 10.3 seconds
Started Jun 07 08:35:45 PM PDT 24
Finished Jun 07 08:36:02 PM PDT 24
Peak memory 217432 kb
Host smart-17fa1a41-e6f8-4c15-b99f-5cf023e740cb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415242602 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_jtag_access.415242602
Directory /workspace/27.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/27.lc_ctrl_prog_failure.4040193328
Short name T522
Test name
Test status
Simulation time 423647432 ps
CPU time 1.73 seconds
Started Jun 07 08:35:40 PM PDT 24
Finished Jun 07 08:35:48 PM PDT 24
Peak memory 218220 kb
Host smart-8e7f302d-3b11-4450-9dfc-23917da37e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040193328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_prog_failure.4040193328
Directory /workspace/27.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_mubi.645660129
Short name T312
Test name
Test status
Simulation time 871926198 ps
CPU time 11.72 seconds
Started Jun 07 08:35:45 PM PDT 24
Finished Jun 07 08:36:03 PM PDT 24
Peak memory 226092 kb
Host smart-054a203e-604e-4b51-9c9e-12f6a46fa789
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645660129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_mubi.645660129
Directory /workspace/27.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_digest.168821674
Short name T749
Test name
Test status
Simulation time 1154868349 ps
CPU time 14.04 seconds
Started Jun 07 08:35:33 PM PDT 24
Finished Jun 07 08:35:55 PM PDT 24
Peak memory 226108 kb
Host smart-11459e9c-39b6-4e7a-8451-0d3a9081c4d4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=168821674 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_di
gest.168821674
Directory /workspace/27.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/27.lc_ctrl_sec_token_mux.3524278110
Short name T584
Test name
Test status
Simulation time 737165997 ps
CPU time 7.59 seconds
Started Jun 07 08:35:40 PM PDT 24
Finished Jun 07 08:35:54 PM PDT 24
Peak memory 218284 kb
Host smart-86f3447a-1464-4136-b1b9-cdc104814372
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524278110 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_sec_token_mux.
3524278110
Directory /workspace/27.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/27.lc_ctrl_security_escalation.4264743360
Short name T833
Test name
Test status
Simulation time 305556613 ps
CPU time 11.58 seconds
Started Jun 07 08:35:34 PM PDT 24
Finished Jun 07 08:35:53 PM PDT 24
Peak memory 226080 kb
Host smart-22f0c24a-78b1-4069-8c62-3e3032e259fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264743360 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_security_escalation.4264743360
Directory /workspace/27.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/27.lc_ctrl_smoke.1980393753
Short name T67
Test name
Test status
Simulation time 28581042 ps
CPU time 2.2 seconds
Started Jun 07 08:35:45 PM PDT 24
Finished Jun 07 08:35:54 PM PDT 24
Peak memory 214532 kb
Host smart-b0cfe9a8-3b2a-4c96-b922-70134b46c6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980393753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_smoke.1980393753
Directory /workspace/27.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_failure.354360856
Short name T446
Test name
Test status
Simulation time 156789925 ps
CPU time 17.34 seconds
Started Jun 07 08:35:45 PM PDT 24
Finished Jun 07 08:36:09 PM PDT 24
Peak memory 250908 kb
Host smart-a8224a0c-d7ad-4c57-9e59-70fb6e49647e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354360856 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_failure.354360856
Directory /workspace/27.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/27.lc_ctrl_state_post_trans.597727340
Short name T824
Test name
Test status
Simulation time 49352982 ps
CPU time 6.55 seconds
Started Jun 07 08:35:36 PM PDT 24
Finished Jun 07 08:35:49 PM PDT 24
Peak memory 246840 kb
Host smart-246f3d6b-c7a7-4377-aac3-d29dddea50a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597727340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_ctrl_state_post_trans.597727340
Directory /workspace/27.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/27.lc_ctrl_stress_all.2457831015
Short name T790
Test name
Test status
Simulation time 6692111917 ps
CPU time 59.96 seconds
Started Jun 07 08:35:44 PM PDT 24
Finished Jun 07 08:36:50 PM PDT 24
Peak memory 250844 kb
Host smart-9eeda524-2511-47f6-80e1-6f7140e90860
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457831015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
27.lc_ctrl_stress_all.2457831015
Directory /workspace/27.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.lc_ctrl_volatile_unlock_smoke.3547780221
Short name T701
Test name
Test status
Simulation time 25069720 ps
CPU time 0.9 seconds
Started Jun 07 08:35:40 PM PDT 24
Finished Jun 07 08:35:47 PM PDT 24
Peak memory 211864 kb
Host smart-01d9522f-6d7b-4c04-a1ae-afda7785a24e
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547780221 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.lc_c
trl_volatile_unlock_smoke.3547780221
Directory /workspace/27.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_alert_test.1390835596
Short name T613
Test name
Test status
Simulation time 48380902 ps
CPU time 0.86 seconds
Started Jun 07 08:35:49 PM PDT 24
Finished Jun 07 08:35:56 PM PDT 24
Peak memory 208828 kb
Host smart-930a61bb-1327-4760-9d60-f9889b7695e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390835596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_alert_test.1390835596
Directory /workspace/28.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.lc_ctrl_errors.2496789767
Short name T293
Test name
Test status
Simulation time 973045728 ps
CPU time 9.85 seconds
Started Jun 07 08:35:43 PM PDT 24
Finished Jun 07 08:35:59 PM PDT 24
Peak memory 218080 kb
Host smart-493d0cc1-17e3-4e17-9b7c-f17e025364d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496789767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_errors.2496789767
Directory /workspace/28.lc_ctrl_errors/latest

Test location /workspace/coverage/default/28.lc_ctrl_jtag_access.3029332563
Short name T31
Test name
Test status
Simulation time 6055102281 ps
CPU time 3.37 seconds
Started Jun 07 08:35:38 PM PDT 24
Finished Jun 07 08:35:48 PM PDT 24
Peak memory 217624 kb
Host smart-93d73ae1-9181-4731-b592-4ce1ba7606b5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029332563 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_jtag_access.3029332563
Directory /workspace/28.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/28.lc_ctrl_prog_failure.1353063579
Short name T650
Test name
Test status
Simulation time 75055486 ps
CPU time 2.96 seconds
Started Jun 07 08:35:42 PM PDT 24
Finished Jun 07 08:35:51 PM PDT 24
Peak memory 218236 kb
Host smart-b61f1c81-ca0d-4d26-b494-5a8c34392235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353063579 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_prog_failure.1353063579
Directory /workspace/28.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_mubi.1030374949
Short name T474
Test name
Test status
Simulation time 378721586 ps
CPU time 14.15 seconds
Started Jun 07 08:35:43 PM PDT 24
Finished Jun 07 08:36:03 PM PDT 24
Peak memory 218920 kb
Host smart-ac9b7b1e-cb38-4e20-a177-6cd4d9d8c680
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030374949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_mubi.1030374949
Directory /workspace/28.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_digest.3003866441
Short name T358
Test name
Test status
Simulation time 797703762 ps
CPU time 10.4 seconds
Started Jun 07 08:35:48 PM PDT 24
Finished Jun 07 08:36:05 PM PDT 24
Peak memory 218208 kb
Host smart-874dab2d-9a33-4e49-9deb-904efd6c3ae1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003866441 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_d
igest.3003866441
Directory /workspace/28.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/28.lc_ctrl_sec_token_mux.1441329328
Short name T667
Test name
Test status
Simulation time 1097237800 ps
CPU time 9.54 seconds
Started Jun 07 08:35:40 PM PDT 24
Finished Jun 07 08:35:56 PM PDT 24
Peak memory 218260 kb
Host smart-302e3d22-3067-41f9-8840-0e74685e6d74
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441329328 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_sec_token_mux.
1441329328
Directory /workspace/28.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/28.lc_ctrl_security_escalation.689342987
Short name T396
Test name
Test status
Simulation time 332287492 ps
CPU time 12.27 seconds
Started Jun 07 08:35:48 PM PDT 24
Finished Jun 07 08:36:07 PM PDT 24
Peak memory 226108 kb
Host smart-a0d56b8f-0273-44cc-a3f1-9567e216c98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689342987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_security_escalation.689342987
Directory /workspace/28.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/28.lc_ctrl_smoke.4098913116
Short name T288
Test name
Test status
Simulation time 153756488 ps
CPU time 2.9 seconds
Started Jun 07 08:35:44 PM PDT 24
Finished Jun 07 08:35:53 PM PDT 24
Peak memory 214528 kb
Host smart-5bafb4ae-f896-4c7e-af46-544c373d42e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098913116 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_smoke.4098913116
Directory /workspace/28.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_failure.418065432
Short name T486
Test name
Test status
Simulation time 906146950 ps
CPU time 24.06 seconds
Started Jun 07 08:35:36 PM PDT 24
Finished Jun 07 08:36:07 PM PDT 24
Peak memory 250832 kb
Host smart-72281d19-ad45-45ff-9513-e613e87175ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418065432 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_failure.418065432
Directory /workspace/28.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/28.lc_ctrl_state_post_trans.3267837392
Short name T307
Test name
Test status
Simulation time 80470606 ps
CPU time 8.53 seconds
Started Jun 07 08:35:46 PM PDT 24
Finished Jun 07 08:36:01 PM PDT 24
Peak memory 250896 kb
Host smart-631abe1a-8de8-48cb-9894-466853864225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267837392 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_ctrl_state_post_trans.3267837392
Directory /workspace/28.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/28.lc_ctrl_volatile_unlock_smoke.1870660967
Short name T658
Test name
Test status
Simulation time 75923143 ps
CPU time 0.82 seconds
Started Jun 07 08:35:37 PM PDT 24
Finished Jun 07 08:35:45 PM PDT 24
Peak memory 211852 kb
Host smart-dcb97e13-7240-4607-a6d4-e487f580f5a7
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870660967 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.lc_c
trl_volatile_unlock_smoke.1870660967
Directory /workspace/28.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_alert_test.1528939147
Short name T580
Test name
Test status
Simulation time 30243766 ps
CPU time 1.17 seconds
Started Jun 07 08:35:46 PM PDT 24
Finished Jun 07 08:35:54 PM PDT 24
Peak memory 208928 kb
Host smart-482025f0-60ba-42ff-ae08-80c7f6e68f06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528939147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_alert_test.1528939147
Directory /workspace/29.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.lc_ctrl_errors.4146056414
Short name T284
Test name
Test status
Simulation time 3041073846 ps
CPU time 18.03 seconds
Started Jun 07 08:35:51 PM PDT 24
Finished Jun 07 08:36:15 PM PDT 24
Peak memory 218988 kb
Host smart-84f241a9-d825-4806-98a6-97ca257dee82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146056414 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_errors.4146056414
Directory /workspace/29.lc_ctrl_errors/latest

Test location /workspace/coverage/default/29.lc_ctrl_jtag_access.2387557988
Short name T704
Test name
Test status
Simulation time 1427524408 ps
CPU time 3.91 seconds
Started Jun 07 08:35:52 PM PDT 24
Finished Jun 07 08:36:02 PM PDT 24
Peak memory 217088 kb
Host smart-aa8bf7ab-634f-42aa-9a77-8c393e9e401b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387557988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_jtag_access.2387557988
Directory /workspace/29.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/29.lc_ctrl_prog_failure.1324072590
Short name T662
Test name
Test status
Simulation time 149310161 ps
CPU time 5.04 seconds
Started Jun 07 08:35:48 PM PDT 24
Finished Jun 07 08:36:00 PM PDT 24
Peak memory 218216 kb
Host smart-22fc4265-ef85-45e7-a6bd-10e08993ba63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324072590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_prog_failure.1324072590
Directory /workspace/29.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_mubi.246568982
Short name T459
Test name
Test status
Simulation time 1956735261 ps
CPU time 14.72 seconds
Started Jun 07 08:35:48 PM PDT 24
Finished Jun 07 08:36:10 PM PDT 24
Peak memory 226100 kb
Host smart-71dc2849-9971-4253-9622-aab30f58bd97
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246568982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_mubi.246568982
Directory /workspace/29.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_digest.1511609582
Short name T61
Test name
Test status
Simulation time 398025922 ps
CPU time 15.22 seconds
Started Jun 07 08:35:53 PM PDT 24
Finished Jun 07 08:36:13 PM PDT 24
Peak memory 218264 kb
Host smart-67d6b360-a53c-4581-a3ab-243db9779b63
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511609582 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_d
igest.1511609582
Directory /workspace/29.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/29.lc_ctrl_sec_token_mux.3280558741
Short name T768
Test name
Test status
Simulation time 1110034771 ps
CPU time 8.39 seconds
Started Jun 07 08:35:47 PM PDT 24
Finished Jun 07 08:36:02 PM PDT 24
Peak memory 218256 kb
Host smart-69d4cbdf-ba03-4319-8de4-c4945febb723
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280558741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_sec_token_mux.
3280558741
Directory /workspace/29.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/29.lc_ctrl_security_escalation.2035459835
Short name T485
Test name
Test status
Simulation time 943309454 ps
CPU time 12.22 seconds
Started Jun 07 08:35:45 PM PDT 24
Finished Jun 07 08:36:04 PM PDT 24
Peak memory 226056 kb
Host smart-9b55a7d0-97f8-4820-bb74-212abb4f291c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035459835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_security_escalation.2035459835
Directory /workspace/29.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/29.lc_ctrl_smoke.187515745
Short name T320
Test name
Test status
Simulation time 204778264 ps
CPU time 3.33 seconds
Started Jun 07 08:35:49 PM PDT 24
Finished Jun 07 08:35:59 PM PDT 24
Peak memory 217760 kb
Host smart-33ec68ea-c05d-4ef6-b44d-992cb35f7c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187515745 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_smoke.187515745
Directory /workspace/29.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_failure.4148868119
Short name T340
Test name
Test status
Simulation time 191293856 ps
CPU time 16.98 seconds
Started Jun 07 08:35:49 PM PDT 24
Finished Jun 07 08:36:13 PM PDT 24
Peak memory 250920 kb
Host smart-a8f780a2-3ce6-4777-b789-987662e66de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148868119 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_failure.4148868119
Directory /workspace/29.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/29.lc_ctrl_state_post_trans.86356941
Short name T629
Test name
Test status
Simulation time 143224576 ps
CPU time 7.55 seconds
Started Jun 07 08:35:52 PM PDT 24
Finished Jun 07 08:36:06 PM PDT 24
Peak memory 250916 kb
Host smart-dfdaeb98-b5fb-440c-97d3-bf7be7cd2408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86356941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_state_post_trans.86356941
Directory /workspace/29.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all.1480371600
Short name T440
Test name
Test status
Simulation time 142376295710 ps
CPU time 570.24 seconds
Started Jun 07 08:35:50 PM PDT 24
Finished Jun 07 08:45:27 PM PDT 24
Peak memory 250988 kb
Host smart-0843b572-7952-446f-aaf7-57608af1d272
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1480371600 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
29.lc_ctrl_stress_all.1480371600
Directory /workspace/29.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.lc_ctrl_stress_all_with_rand_reset.2821620494
Short name T156
Test name
Test status
Simulation time 33807841045 ps
CPU time 2355.8 seconds
Started Jun 07 08:35:45 PM PDT 24
Finished Jun 07 09:15:09 PM PDT 24
Peak memory 905764 kb
Host smart-08443dd0-f7b4-4e98-b1d6-449a2ef99803
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=2821620494 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_ctrl_stress_all_with_rand_reset.2821620494
Directory /workspace/29.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.lc_ctrl_volatile_unlock_smoke.3342078659
Short name T672
Test name
Test status
Simulation time 36264377 ps
CPU time 0.95 seconds
Started Jun 07 08:35:52 PM PDT 24
Finished Jun 07 08:35:59 PM PDT 24
Peak memory 211888 kb
Host smart-b19c116f-fda8-4985-ab0d-92964f17e381
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342078659 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.lc_c
trl_volatile_unlock_smoke.3342078659
Directory /workspace/29.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_alert_test.3223465613
Short name T430
Test name
Test status
Simulation time 34860375 ps
CPU time 1.03 seconds
Started Jun 07 08:34:48 PM PDT 24
Finished Jun 07 08:34:52 PM PDT 24
Peak memory 208968 kb
Host smart-a0eee995-a8bd-44d0-a79d-c12c5133f9d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223465613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_alert_test.3223465613
Directory /workspace/3.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.lc_ctrl_claim_transition_if.3229858215
Short name T783
Test name
Test status
Simulation time 12526257 ps
CPU time 0.98 seconds
Started Jun 07 08:34:40 PM PDT 24
Finished Jun 07 08:34:46 PM PDT 24
Peak memory 209012 kb
Host smart-11942882-d7a9-4a4e-a614-bc666c5bb40d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229858215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_claim_transition_if.3229858215
Directory /workspace/3.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/3.lc_ctrl_errors.1858249620
Short name T334
Test name
Test status
Simulation time 8929487334 ps
CPU time 15.21 seconds
Started Jun 07 08:34:47 PM PDT 24
Finished Jun 07 08:35:05 PM PDT 24
Peak memory 218524 kb
Host smart-b4f791bb-fb9e-4b04-8273-838b192c4783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858249620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_errors.1858249620
Directory /workspace/3.lc_ctrl_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_access.3339371944
Short name T488
Test name
Test status
Simulation time 1985149729 ps
CPU time 13.79 seconds
Started Jun 07 08:34:39 PM PDT 24
Finished Jun 07 08:34:58 PM PDT 24
Peak memory 217304 kb
Host smart-ae43e36c-8cbe-457e-ad31-abee2c1c804a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339371944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_access.3339371944
Directory /workspace/3.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_errors.129320631
Short name T107
Test name
Test status
Simulation time 8715556199 ps
CPU time 53.87 seconds
Started Jun 07 08:34:46 PM PDT 24
Finished Jun 07 08:35:43 PM PDT 24
Peak memory 218196 kb
Host smart-f96b743f-bd37-4050-bee1-eebfc8a2066e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129320631 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_err
ors.129320631
Directory /workspace/3.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_priority.3625529440
Short name T849
Test name
Test status
Simulation time 643845614 ps
CPU time 4.68 seconds
Started Jun 07 08:34:54 PM PDT 24
Finished Jun 07 08:35:03 PM PDT 24
Peak memory 217912 kb
Host smart-3bedae67-f9e1-4942-b462-cd67a27c990d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625529440 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_priority.3
625529440
Directory /workspace/3.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_prog_failure.4172301073
Short name T760
Test name
Test status
Simulation time 641386855 ps
CPU time 3.36 seconds
Started Jun 07 08:34:51 PM PDT 24
Finished Jun 07 08:34:58 PM PDT 24
Peak memory 221644 kb
Host smart-7f1dcb05-b10e-4c7b-a651-cb58fa3bc82b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172301073 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_prog_failure.4172301073
Directory /workspace/3.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_regwen_during_op.1787593653
Short name T606
Test name
Test status
Simulation time 1517430935 ps
CPU time 22.64 seconds
Started Jun 07 08:34:51 PM PDT 24
Finished Jun 07 08:35:17 PM PDT 24
Peak memory 217592 kb
Host smart-1c2f02cb-f73d-4d99-8eac-30135447cf7e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787593653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_
jtag_regwen_during_op.1787593653
Directory /workspace/3.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_smoke.4170402633
Short name T717
Test name
Test status
Simulation time 475844788 ps
CPU time 5.03 seconds
Started Jun 07 08:34:52 PM PDT 24
Finished Jun 07 08:35:02 PM PDT 24
Peak memory 217716 kb
Host smart-0d216459-e9f9-4115-a27a-4c90bab65f4a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170402633 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_smoke.
4170402633
Directory /workspace/3.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_failure.534998433
Short name T773
Test name
Test status
Simulation time 4912151505 ps
CPU time 37.21 seconds
Started Jun 07 08:34:28 PM PDT 24
Finished Jun 07 08:35:15 PM PDT 24
Peak memory 250716 kb
Host smart-ac207aa0-4ae4-4060-be8a-894e78d3bb3f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534998433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag
_state_failure.534998433
Directory /workspace/3.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_jtag_state_post_trans.330913819
Short name T407
Test name
Test status
Simulation time 269405306 ps
CPU time 13.61 seconds
Started Jun 07 08:34:59 PM PDT 24
Finished Jun 07 08:35:18 PM PDT 24
Peak memory 250836 kb
Host smart-9f345126-ee6b-4dbd-ae79-172716fce2be
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330913819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_j
tag_state_post_trans.330913819
Directory /workspace/3.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_prog_failure.808729149
Short name T269
Test name
Test status
Simulation time 430124231 ps
CPU time 2.2 seconds
Started Jun 07 08:34:37 PM PDT 24
Finished Jun 07 08:34:46 PM PDT 24
Peak memory 218296 kb
Host smart-b3a811a7-be30-40a1-9d22-ca91ceb62c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808729149 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_prog_failure.808729149
Directory /workspace/3.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_regwen_during_op.2409913268
Short name T73
Test name
Test status
Simulation time 619538100 ps
CPU time 11.15 seconds
Started Jun 07 08:34:57 PM PDT 24
Finished Jun 07 08:35:13 PM PDT 24
Peak memory 223112 kb
Host smart-fb1222f3-129a-4283-a888-38d5ee1032dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409913268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_regwen_during_op.2409913268
Directory /workspace/3.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_cm.1085691313
Short name T91
Test name
Test status
Simulation time 444001412 ps
CPU time 24.37 seconds
Started Jun 07 08:34:55 PM PDT 24
Finished Jun 07 08:35:24 PM PDT 24
Peak memory 282108 kb
Host smart-89f60b3b-4603-4bef-9e40-3cbe5d82c04a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085691313 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_cm.1085691313
Directory /workspace/3.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_mubi.4282749409
Short name T394
Test name
Test status
Simulation time 232742215 ps
CPU time 11.62 seconds
Started Jun 07 08:34:56 PM PDT 24
Finished Jun 07 08:35:13 PM PDT 24
Peak memory 218856 kb
Host smart-908fc8e3-098b-4b54-b3c8-5ee2f74f4cc1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282749409 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_mubi.4282749409
Directory /workspace/3.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/3.lc_ctrl_sec_token_digest.1174972728
Short name T611
Test name
Test status
Simulation time 7612937529 ps
CPU time 10.78 seconds
Started Jun 07 08:34:29 PM PDT 24
Finished Jun 07 08:34:50 PM PDT 24
Peak memory 226128 kb
Host smart-77e6ff98-7944-446b-92b5-cc6fecdc814c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174972728 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_sec_token_di
gest.1174972728
Directory /workspace/3.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/3.lc_ctrl_security_escalation.2244087542
Short name T624
Test name
Test status
Simulation time 842724144 ps
CPU time 9.22 seconds
Started Jun 07 08:34:42 PM PDT 24
Finished Jun 07 08:34:55 PM PDT 24
Peak memory 218368 kb
Host smart-28e6c3fb-cd7c-4baf-889d-3b77bbb1df7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244087542 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_security_escalation.2244087542
Directory /workspace/3.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/3.lc_ctrl_smoke.3336892948
Short name T501
Test name
Test status
Simulation time 151995412 ps
CPU time 2 seconds
Started Jun 07 08:34:22 PM PDT 24
Finished Jun 07 08:34:34 PM PDT 24
Peak memory 214296 kb
Host smart-df20787c-6a5c-462f-b0c8-89214391225e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336892948 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_smoke.3336892948
Directory /workspace/3.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_failure.3493140720
Short name T640
Test name
Test status
Simulation time 1076845256 ps
CPU time 36.89 seconds
Started Jun 07 08:34:53 PM PDT 24
Finished Jun 07 08:35:35 PM PDT 24
Peak memory 250908 kb
Host smart-4454b922-4930-4b5a-ac69-d448f456b570
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493140720 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_failure.3493140720
Directory /workspace/3.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/3.lc_ctrl_state_post_trans.1704153076
Short name T406
Test name
Test status
Simulation time 294214922 ps
CPU time 6.93 seconds
Started Jun 07 08:34:24 PM PDT 24
Finished Jun 07 08:34:41 PM PDT 24
Peak memory 246812 kb
Host smart-7e0cef4d-1929-4315-bcc5-359db9551333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704153076 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_state_post_trans.1704153076
Directory /workspace/3.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/3.lc_ctrl_stress_all.3324602350
Short name T292
Test name
Test status
Simulation time 20722318342 ps
CPU time 248.2 seconds
Started Jun 07 08:34:45 PM PDT 24
Finished Jun 07 08:38:56 PM PDT 24
Peak memory 250952 kb
Host smart-e122ff23-a105-4204-8cac-0e2a5169e8f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324602350 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.lc_ctrl_stress_all.3324602350
Directory /workspace/3.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.lc_ctrl_volatile_unlock_smoke.2670002539
Short name T531
Test name
Test status
Simulation time 13387025 ps
CPU time 0.88 seconds
Started Jun 07 08:34:40 PM PDT 24
Finished Jun 07 08:34:46 PM PDT 24
Peak memory 211976 kb
Host smart-0c15494c-7d8a-451f-bc04-b687ffcb736c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670002539 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.lc_ct
rl_volatile_unlock_smoke.2670002539
Directory /workspace/3.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_alert_test.2349324936
Short name T386
Test name
Test status
Simulation time 19440330 ps
CPU time 1.17 seconds
Started Jun 07 08:35:45 PM PDT 24
Finished Jun 07 08:35:53 PM PDT 24
Peak memory 208880 kb
Host smart-765c04d0-a695-417a-bf02-16ef6ea48bf0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349324936 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_alert_test.2349324936
Directory /workspace/30.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.lc_ctrl_errors.2741950523
Short name T262
Test name
Test status
Simulation time 1343789419 ps
CPU time 14.71 seconds
Started Jun 07 08:35:47 PM PDT 24
Finished Jun 07 08:36:08 PM PDT 24
Peak memory 218200 kb
Host smart-c8566812-6a99-4e7c-b915-6a2033232496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741950523 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_errors.2741950523
Directory /workspace/30.lc_ctrl_errors/latest

Test location /workspace/coverage/default/30.lc_ctrl_jtag_access.970024363
Short name T33
Test name
Test status
Simulation time 1702958881 ps
CPU time 7.96 seconds
Started Jun 07 08:35:51 PM PDT 24
Finished Jun 07 08:36:05 PM PDT 24
Peak memory 217136 kb
Host smart-43364a30-2b2f-4937-85e0-6daeff9cfc33
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970024363 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_jtag_access.970024363
Directory /workspace/30.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/30.lc_ctrl_prog_failure.2087537647
Short name T339
Test name
Test status
Simulation time 63811726 ps
CPU time 3.49 seconds
Started Jun 07 08:35:48 PM PDT 24
Finished Jun 07 08:35:58 PM PDT 24
Peak memory 222484 kb
Host smart-e2a1a7bc-5fa2-4ba9-a3d3-8c8f7253dc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087537647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_prog_failure.2087537647
Directory /workspace/30.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_mubi.207988040
Short name T280
Test name
Test status
Simulation time 1143293147 ps
CPU time 9.81 seconds
Started Jun 07 08:35:50 PM PDT 24
Finished Jun 07 08:36:06 PM PDT 24
Peak memory 218944 kb
Host smart-abdc847d-5370-4e50-944c-91650995313d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207988040 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_mubi.207988040
Directory /workspace/30.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_digest.1161556235
Short name T694
Test name
Test status
Simulation time 459123324 ps
CPU time 17.89 seconds
Started Jun 07 08:35:45 PM PDT 24
Finished Jun 07 08:36:10 PM PDT 24
Peak memory 218248 kb
Host smart-56a7a0d0-1223-4b55-8b54-2cad9ee6098e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161556235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_d
igest.1161556235
Directory /workspace/30.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/30.lc_ctrl_sec_token_mux.3830601575
Short name T785
Test name
Test status
Simulation time 361785432 ps
CPU time 13.21 seconds
Started Jun 07 08:35:43 PM PDT 24
Finished Jun 07 08:36:03 PM PDT 24
Peak memory 218284 kb
Host smart-be1c5307-46b2-4a30-a06f-a24dbba40dd9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830601575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_sec_token_mux.
3830601575
Directory /workspace/30.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/30.lc_ctrl_security_escalation.432246738
Short name T393
Test name
Test status
Simulation time 224334934 ps
CPU time 9.6 seconds
Started Jun 07 08:35:45 PM PDT 24
Finished Jun 07 08:36:02 PM PDT 24
Peak memory 226088 kb
Host smart-21bb182e-d693-4a78-8898-faa625094d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432246738 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_security_escalation.432246738
Directory /workspace/30.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/30.lc_ctrl_smoke.2617622566
Short name T391
Test name
Test status
Simulation time 28719019 ps
CPU time 2.21 seconds
Started Jun 07 08:35:47 PM PDT 24
Finished Jun 07 08:35:56 PM PDT 24
Peak memory 214384 kb
Host smart-0e8bc3b3-b3d3-48c7-bbcf-68b7d1612368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617622566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_smoke.2617622566
Directory /workspace/30.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_failure.3818234957
Short name T207
Test name
Test status
Simulation time 188700316 ps
CPU time 24.01 seconds
Started Jun 07 08:35:47 PM PDT 24
Finished Jun 07 08:36:18 PM PDT 24
Peak memory 250868 kb
Host smart-35913a2c-ccf9-4e13-98a8-59147a4e1c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818234957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_failure.3818234957
Directory /workspace/30.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/30.lc_ctrl_state_post_trans.1166637578
Short name T725
Test name
Test status
Simulation time 158870792 ps
CPU time 10.18 seconds
Started Jun 07 08:35:41 PM PDT 24
Finished Jun 07 08:35:57 PM PDT 24
Peak memory 250908 kb
Host smart-443b2e0d-33bb-44e6-9633-bb78844282eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166637578 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ctrl_state_post_trans.1166637578
Directory /workspace/30.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/30.lc_ctrl_stress_all.2332321989
Short name T605
Test name
Test status
Simulation time 4431409158 ps
CPU time 44.58 seconds
Started Jun 07 08:35:50 PM PDT 24
Finished Jun 07 08:36:41 PM PDT 24
Peak memory 251072 kb
Host smart-6db8f908-4b48-435a-bbbf-0496619b5643
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332321989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
30.lc_ctrl_stress_all.2332321989
Directory /workspace/30.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.lc_ctrl_volatile_unlock_smoke.198287697
Short name T311
Test name
Test status
Simulation time 34832208 ps
CPU time 0.94 seconds
Started Jun 07 08:35:47 PM PDT 24
Finished Jun 07 08:35:55 PM PDT 24
Peak memory 211876 kb
Host smart-810134d8-d713-407c-9231-471036ab18b3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198287697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.lc_ct
rl_volatile_unlock_smoke.198287697
Directory /workspace/30.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_alert_test.1430275652
Short name T539
Test name
Test status
Simulation time 31127681 ps
CPU time 0.85 seconds
Started Jun 07 08:35:48 PM PDT 24
Finished Jun 07 08:35:56 PM PDT 24
Peak memory 208976 kb
Host smart-bfc89279-4367-4df2-b1bb-ac453c69b5f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430275652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_alert_test.1430275652
Directory /workspace/31.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.lc_ctrl_errors.4092463893
Short name T796
Test name
Test status
Simulation time 265711080 ps
CPU time 11.83 seconds
Started Jun 07 08:35:48 PM PDT 24
Finished Jun 07 08:36:07 PM PDT 24
Peak memory 218168 kb
Host smart-37f3c4e4-c6c8-48de-9c78-c5b6c527c4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092463893 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_errors.4092463893
Directory /workspace/31.lc_ctrl_errors/latest

Test location /workspace/coverage/default/31.lc_ctrl_jtag_access.1351987353
Short name T329
Test name
Test status
Simulation time 422052788 ps
CPU time 3.23 seconds
Started Jun 07 08:35:49 PM PDT 24
Finished Jun 07 08:35:58 PM PDT 24
Peak memory 217108 kb
Host smart-9d465fbf-4a9a-46d7-b596-f38ce6974f4b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351987353 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_jtag_access.1351987353
Directory /workspace/31.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/31.lc_ctrl_prog_failure.3478960698
Short name T498
Test name
Test status
Simulation time 71067732 ps
CPU time 2.46 seconds
Started Jun 07 08:35:52 PM PDT 24
Finished Jun 07 08:36:00 PM PDT 24
Peak memory 222396 kb
Host smart-16244cd4-8bc1-4013-acb0-85264c6cc657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478960698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_prog_failure.3478960698
Directory /workspace/31.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_mubi.3152977385
Short name T22
Test name
Test status
Simulation time 308620805 ps
CPU time 11.1 seconds
Started Jun 07 08:35:50 PM PDT 24
Finished Jun 07 08:36:07 PM PDT 24
Peak memory 218968 kb
Host smart-f8f7e2a9-6139-4eb8-ab7c-d685419c07cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152977385 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_mubi.3152977385
Directory /workspace/31.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_digest.1427269433
Short name T651
Test name
Test status
Simulation time 378897428 ps
CPU time 12.76 seconds
Started Jun 07 08:35:49 PM PDT 24
Finished Jun 07 08:36:08 PM PDT 24
Peak memory 226088 kb
Host smart-4cb14354-c536-4279-88c6-ec814a8f3a07
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427269433 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_d
igest.1427269433
Directory /workspace/31.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/31.lc_ctrl_sec_token_mux.513404671
Short name T791
Test name
Test status
Simulation time 1325823035 ps
CPU time 9.01 seconds
Started Jun 07 08:36:01 PM PDT 24
Finished Jun 07 08:36:14 PM PDT 24
Peak memory 218252 kb
Host smart-cc987523-c43a-4b39-8a9f-f24ed0c342fa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513404671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_sec_token_mux.513404671
Directory /workspace/31.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/31.lc_ctrl_security_escalation.1760195552
Short name T610
Test name
Test status
Simulation time 1151997534 ps
CPU time 8.55 seconds
Started Jun 07 08:35:55 PM PDT 24
Finished Jun 07 08:36:09 PM PDT 24
Peak memory 226080 kb
Host smart-7f85b39c-204e-4ca5-9372-6e1059737f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760195552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_security_escalation.1760195552
Directory /workspace/31.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/31.lc_ctrl_smoke.1197402379
Short name T431
Test name
Test status
Simulation time 253403923 ps
CPU time 4.29 seconds
Started Jun 07 08:35:47 PM PDT 24
Finished Jun 07 08:35:58 PM PDT 24
Peak memory 217788 kb
Host smart-8bf889cc-31f1-432e-9f9b-2e136372caea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197402379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_smoke.1197402379
Directory /workspace/31.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_failure.374174234
Short name T527
Test name
Test status
Simulation time 280113643 ps
CPU time 26.85 seconds
Started Jun 07 08:35:52 PM PDT 24
Finished Jun 07 08:36:25 PM PDT 24
Peak memory 250932 kb
Host smart-20c8e0a4-8f20-47c7-b91d-9af8bfb9e95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374174234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_failure.374174234
Directory /workspace/31.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/31.lc_ctrl_state_post_trans.3664147610
Short name T170
Test name
Test status
Simulation time 66649432 ps
CPU time 8 seconds
Started Jun 07 08:35:57 PM PDT 24
Finished Jun 07 08:36:10 PM PDT 24
Peak memory 250936 kb
Host smart-23d5841c-4d36-4663-a11f-d44d256772ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664147610 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_ctrl_state_post_trans.3664147610
Directory /workspace/31.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/31.lc_ctrl_stress_all.2319973169
Short name T64
Test name
Test status
Simulation time 46008501009 ps
CPU time 192.9 seconds
Started Jun 07 08:35:49 PM PDT 24
Finished Jun 07 08:39:09 PM PDT 24
Peak memory 259136 kb
Host smart-622c8f72-25de-4cc8-aa93-91d0562d95f8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319973169 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
31.lc_ctrl_stress_all.2319973169
Directory /workspace/31.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2024460308
Short name T301
Test name
Test status
Simulation time 20940401 ps
CPU time 0.87 seconds
Started Jun 07 08:35:47 PM PDT 24
Finished Jun 07 08:35:55 PM PDT 24
Peak memory 212024 kb
Host smart-5ec04775-c700-47d4-b080-413c8162970c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024460308 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.lc_c
trl_volatile_unlock_smoke.2024460308
Directory /workspace/31.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_alert_test.1924882513
Short name T381
Test name
Test status
Simulation time 38046024 ps
CPU time 0.83 seconds
Started Jun 07 08:35:48 PM PDT 24
Finished Jun 07 08:35:56 PM PDT 24
Peak memory 208824 kb
Host smart-3819654d-ad12-413b-a2ec-ece38a74a00b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924882513 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_alert_test.1924882513
Directory /workspace/32.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.lc_ctrl_errors.904968751
Short name T356
Test name
Test status
Simulation time 808284625 ps
CPU time 12.47 seconds
Started Jun 07 08:36:00 PM PDT 24
Finished Jun 07 08:36:16 PM PDT 24
Peak memory 218252 kb
Host smart-9cf0c982-36ea-4ecd-9161-5eec10c1db19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904968751 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_errors.904968751
Directory /workspace/32.lc_ctrl_errors/latest

Test location /workspace/coverage/default/32.lc_ctrl_jtag_access.3915526302
Short name T434
Test name
Test status
Simulation time 271769716 ps
CPU time 3.73 seconds
Started Jun 07 08:35:55 PM PDT 24
Finished Jun 07 08:36:04 PM PDT 24
Peak memory 217248 kb
Host smart-5c1c0618-f479-40d1-b65f-b2bd80880157
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915526302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_jtag_access.3915526302
Directory /workspace/32.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/32.lc_ctrl_prog_failure.3295709186
Short name T835
Test name
Test status
Simulation time 302604315 ps
CPU time 2.74 seconds
Started Jun 07 08:35:48 PM PDT 24
Finished Jun 07 08:35:58 PM PDT 24
Peak memory 222588 kb
Host smart-cdfc99fa-7cd0-4440-a37b-ca295ea9ba88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295709186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_prog_failure.3295709186
Directory /workspace/32.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_mubi.1363453311
Short name T268
Test name
Test status
Simulation time 644795532 ps
CPU time 15.62 seconds
Started Jun 07 08:35:50 PM PDT 24
Finished Jun 07 08:36:12 PM PDT 24
Peak memory 218280 kb
Host smart-af6b6208-c722-47c7-a6e1-4df10e04965b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363453311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_mubi.1363453311
Directory /workspace/32.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_digest.1402960190
Short name T470
Test name
Test status
Simulation time 868484248 ps
CPU time 8.78 seconds
Started Jun 07 08:35:49 PM PDT 24
Finished Jun 07 08:36:05 PM PDT 24
Peak memory 218288 kb
Host smart-b4d111ee-9da0-46ab-8081-64d08684d1a5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402960190 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_d
igest.1402960190
Directory /workspace/32.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/32.lc_ctrl_sec_token_mux.3243163187
Short name T809
Test name
Test status
Simulation time 251123862 ps
CPU time 8.46 seconds
Started Jun 07 08:35:46 PM PDT 24
Finished Jun 07 08:36:01 PM PDT 24
Peak memory 226156 kb
Host smart-f888c176-91c2-43e8-b432-4425891064b9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243163187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_sec_token_mux.
3243163187
Directory /workspace/32.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/32.lc_ctrl_security_escalation.1343953662
Short name T26
Test name
Test status
Simulation time 521392265 ps
CPU time 11.38 seconds
Started Jun 07 08:35:55 PM PDT 24
Finished Jun 07 08:36:11 PM PDT 24
Peak memory 218380 kb
Host smart-75767501-00e0-48b6-90fa-ef3a20b5de18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343953662 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_security_escalation.1343953662
Directory /workspace/32.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/32.lc_ctrl_smoke.1461262746
Short name T828
Test name
Test status
Simulation time 172212524 ps
CPU time 3.31 seconds
Started Jun 07 08:35:48 PM PDT 24
Finished Jun 07 08:35:58 PM PDT 24
Peak memory 222424 kb
Host smart-c3f0116d-5555-45d7-bcca-99280027a919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461262746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_smoke.1461262746
Directory /workspace/32.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_failure.4046196436
Short name T590
Test name
Test status
Simulation time 275339709 ps
CPU time 22.93 seconds
Started Jun 07 08:35:47 PM PDT 24
Finished Jun 07 08:36:17 PM PDT 24
Peak memory 250988 kb
Host smart-de7d49a4-384f-4af7-96d6-6457f8a38dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046196436 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_failure.4046196436
Directory /workspace/32.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/32.lc_ctrl_state_post_trans.944923707
Short name T226
Test name
Test status
Simulation time 80979132 ps
CPU time 7.8 seconds
Started Jun 07 08:35:49 PM PDT 24
Finished Jun 07 08:36:03 PM PDT 24
Peak memory 250924 kb
Host smart-1048a2ef-840a-42e1-a56f-07db9942f8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944923707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_state_post_trans.944923707
Directory /workspace/32.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.3560990237
Short name T89
Test name
Test status
Simulation time 35567029594 ps
CPU time 571.58 seconds
Started Jun 07 08:35:46 PM PDT 24
Finished Jun 07 08:45:25 PM PDT 24
Peak memory 267080 kb
Host smart-66a0b7e1-66f9-45db-a647-5ad59341537d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3560990237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ctrl_stress_all_with_rand_reset.3560990237
Directory /workspace/32.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.lc_ctrl_volatile_unlock_smoke.423934049
Short name T20
Test name
Test status
Simulation time 132482996 ps
CPU time 1.17 seconds
Started Jun 07 08:35:46 PM PDT 24
Finished Jun 07 08:35:54 PM PDT 24
Peak memory 217776 kb
Host smart-4fce7f7b-0c71-430b-a1f2-7c3e6c4e87ad
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423934049 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.lc_ct
rl_volatile_unlock_smoke.423934049
Directory /workspace/32.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_alert_test.1974146246
Short name T10
Test name
Test status
Simulation time 38275233 ps
CPU time 1.53 seconds
Started Jun 07 08:36:03 PM PDT 24
Finished Jun 07 08:36:08 PM PDT 24
Peak memory 208944 kb
Host smart-27be4c99-3335-42f7-b4b6-9595ad9e7eb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974146246 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_alert_test.1974146246
Directory /workspace/33.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.lc_ctrl_errors.3353679301
Short name T405
Test name
Test status
Simulation time 1243546533 ps
CPU time 12.26 seconds
Started Jun 07 08:35:51 PM PDT 24
Finished Jun 07 08:36:09 PM PDT 24
Peak memory 218244 kb
Host smart-f914680a-933a-495c-b06f-cee92c6ea1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353679301 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_errors.3353679301
Directory /workspace/33.lc_ctrl_errors/latest

Test location /workspace/coverage/default/33.lc_ctrl_jtag_access.3120419400
Short name T798
Test name
Test status
Simulation time 1377708212 ps
CPU time 4.88 seconds
Started Jun 07 08:36:02 PM PDT 24
Finished Jun 07 08:36:11 PM PDT 24
Peak memory 217264 kb
Host smart-87fad4ca-156a-4926-9f2c-70c3d8cec006
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120419400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_jtag_access.3120419400
Directory /workspace/33.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/33.lc_ctrl_prog_failure.2360483264
Short name T377
Test name
Test status
Simulation time 125717348 ps
CPU time 3.33 seconds
Started Jun 07 08:35:57 PM PDT 24
Finished Jun 07 08:36:05 PM PDT 24
Peak memory 218240 kb
Host smart-7e5623ba-ae95-402a-9bd4-3e1278a0540c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360483264 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_prog_failure.2360483264
Directory /workspace/33.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_mubi.773855761
Short name T609
Test name
Test status
Simulation time 363179070 ps
CPU time 9.28 seconds
Started Jun 07 08:35:46 PM PDT 24
Finished Jun 07 08:36:02 PM PDT 24
Peak memory 226192 kb
Host smart-f8bf2a4d-48b1-456f-928e-2be5342c121b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773855761 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_mubi.773855761
Directory /workspace/33.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_digest.2017608470
Short name T426
Test name
Test status
Simulation time 900570337 ps
CPU time 9.15 seconds
Started Jun 07 08:35:57 PM PDT 24
Finished Jun 07 08:36:11 PM PDT 24
Peak memory 218284 kb
Host smart-86d5cbed-ea07-4b9c-8f68-b04222763268
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017608470 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_d
igest.2017608470
Directory /workspace/33.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/33.lc_ctrl_sec_token_mux.1135427957
Short name T265
Test name
Test status
Simulation time 1132295424 ps
CPU time 12.34 seconds
Started Jun 07 08:35:54 PM PDT 24
Finished Jun 07 08:36:12 PM PDT 24
Peak memory 218344 kb
Host smart-96a5c75d-515d-434a-8399-82051b47de3d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135427957 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_sec_token_mux.
1135427957
Directory /workspace/33.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/33.lc_ctrl_security_escalation.3642940106
Short name T781
Test name
Test status
Simulation time 7621713438 ps
CPU time 16.35 seconds
Started Jun 07 08:36:00 PM PDT 24
Finished Jun 07 08:36:20 PM PDT 24
Peak memory 226184 kb
Host smart-4609f770-1020-4369-af06-8335a009afb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642940106 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_security_escalation.3642940106
Directory /workspace/33.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/33.lc_ctrl_smoke.1711074725
Short name T371
Test name
Test status
Simulation time 14485837 ps
CPU time 1.44 seconds
Started Jun 07 08:35:47 PM PDT 24
Finished Jun 07 08:35:56 PM PDT 24
Peak memory 213800 kb
Host smart-4cea2e3c-4286-4c02-b3cc-82a9cdebd02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711074725 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_smoke.1711074725
Directory /workspace/33.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_failure.3780676767
Short name T4
Test name
Test status
Simulation time 308518262 ps
CPU time 23.16 seconds
Started Jun 07 08:35:45 PM PDT 24
Finished Jun 07 08:36:15 PM PDT 24
Peak memory 250904 kb
Host smart-bd6efb9e-3188-4256-b375-aa6e3380122d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780676767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_failure.3780676767
Directory /workspace/33.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/33.lc_ctrl_state_post_trans.895095152
Short name T718
Test name
Test status
Simulation time 82114618 ps
CPU time 3.4 seconds
Started Jun 07 08:35:56 PM PDT 24
Finished Jun 07 08:36:04 PM PDT 24
Peak memory 222312 kb
Host smart-e1fff508-a6dc-4db4-b21e-9f084126cf5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895095152 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_ctrl_state_post_trans.895095152
Directory /workspace/33.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/33.lc_ctrl_stress_all.1400368590
Short name T419
Test name
Test status
Simulation time 3058046109 ps
CPU time 86.55 seconds
Started Jun 07 08:35:54 PM PDT 24
Finished Jun 07 08:37:26 PM PDT 24
Peak memory 250948 kb
Host smart-2f233fc8-12ca-4355-a3be-4266ec1348de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400368590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
33.lc_ctrl_stress_all.1400368590
Directory /workspace/33.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.lc_ctrl_volatile_unlock_smoke.4198379391
Short name T217
Test name
Test status
Simulation time 20418745 ps
CPU time 0.92 seconds
Started Jun 07 08:35:51 PM PDT 24
Finished Jun 07 08:35:58 PM PDT 24
Peak memory 211840 kb
Host smart-d0223f6d-7908-4425-bb4b-63fa29398255
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198379391 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.lc_c
trl_volatile_unlock_smoke.4198379391
Directory /workspace/33.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_alert_test.3054701770
Short name T370
Test name
Test status
Simulation time 42270915 ps
CPU time 0.93 seconds
Started Jun 07 08:36:03 PM PDT 24
Finished Jun 07 08:36:20 PM PDT 24
Peak memory 208956 kb
Host smart-ea0a55a1-244e-4d2d-a0bc-be626bb81ece
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054701770 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_alert_test.3054701770
Directory /workspace/34.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.lc_ctrl_errors.1276273759
Short name T635
Test name
Test status
Simulation time 384978766 ps
CPU time 11.95 seconds
Started Jun 07 08:36:00 PM PDT 24
Finished Jun 07 08:36:15 PM PDT 24
Peak memory 218304 kb
Host smart-6b9eb719-8f6c-46d4-a017-d8e03fe98194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276273759 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_errors.1276273759
Directory /workspace/34.lc_ctrl_errors/latest

Test location /workspace/coverage/default/34.lc_ctrl_jtag_access.2458764325
Short name T566
Test name
Test status
Simulation time 3922627232 ps
CPU time 22.99 seconds
Started Jun 07 08:35:56 PM PDT 24
Finished Jun 07 08:36:24 PM PDT 24
Peak memory 217796 kb
Host smart-b565380b-21b7-4149-859b-3ae014ca3688
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458764325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_jtag_access.2458764325
Directory /workspace/34.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/34.lc_ctrl_prog_failure.2223884422
Short name T780
Test name
Test status
Simulation time 170731821 ps
CPU time 2.26 seconds
Started Jun 07 08:35:58 PM PDT 24
Finished Jun 07 08:36:05 PM PDT 24
Peak memory 218244 kb
Host smart-22468dde-dbb0-4cdb-9a32-8f9fe085c6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223884422 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_prog_failure.2223884422
Directory /workspace/34.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_mubi.3529907671
Short name T331
Test name
Test status
Simulation time 750784112 ps
CPU time 11.08 seconds
Started Jun 07 08:35:54 PM PDT 24
Finished Jun 07 08:36:11 PM PDT 24
Peak memory 218392 kb
Host smart-3e7acfea-4640-47c0-8443-6bd18b0bbeac
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529907671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_mubi.3529907671
Directory /workspace/34.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_digest.650714369
Short name T443
Test name
Test status
Simulation time 388845348 ps
CPU time 11.12 seconds
Started Jun 07 08:36:00 PM PDT 24
Finished Jun 07 08:36:15 PM PDT 24
Peak memory 218380 kb
Host smart-8bc5fc3b-09b9-43c1-aa03-c4d4ba6ff23b
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650714369 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_di
gest.650714369
Directory /workspace/34.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/34.lc_ctrl_sec_token_mux.285315806
Short name T333
Test name
Test status
Simulation time 1437460165 ps
CPU time 7.98 seconds
Started Jun 07 08:35:56 PM PDT 24
Finished Jun 07 08:36:08 PM PDT 24
Peak memory 218276 kb
Host smart-1c157c62-2c95-4676-a58a-7ccfbfe3db56
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285315806 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_sec_token_mux.285315806
Directory /workspace/34.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/34.lc_ctrl_security_escalation.1049312899
Short name T360
Test name
Test status
Simulation time 523671960 ps
CPU time 8.52 seconds
Started Jun 07 08:35:58 PM PDT 24
Finished Jun 07 08:36:11 PM PDT 24
Peak memory 218324 kb
Host smart-d82b6c62-9bea-4cb6-98a4-76ba896ae48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049312899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_security_escalation.1049312899
Directory /workspace/34.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/34.lc_ctrl_smoke.1628553265
Short name T738
Test name
Test status
Simulation time 43347409 ps
CPU time 1.62 seconds
Started Jun 07 08:35:58 PM PDT 24
Finished Jun 07 08:36:04 PM PDT 24
Peak memory 214032 kb
Host smart-8667987c-b65a-4671-9098-b3a6ed3eeba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628553265 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_smoke.1628553265
Directory /workspace/34.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_failure.2441989316
Short name T583
Test name
Test status
Simulation time 3129174518 ps
CPU time 25.74 seconds
Started Jun 07 08:36:03 PM PDT 24
Finished Jun 07 08:36:33 PM PDT 24
Peak memory 251024 kb
Host smart-5bd2cb40-0506-4d5f-b6bf-475ffb1f1a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441989316 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_failure.2441989316
Directory /workspace/34.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/34.lc_ctrl_state_post_trans.989896262
Short name T55
Test name
Test status
Simulation time 66957516 ps
CPU time 7.02 seconds
Started Jun 07 08:36:00 PM PDT 24
Finished Jun 07 08:36:10 PM PDT 24
Peak memory 250216 kb
Host smart-b915c5b7-c4ca-4eef-9f0f-c7042c57a368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989896262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_state_post_trans.989896262
Directory /workspace/34.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all.3882276159
Short name T557
Test name
Test status
Simulation time 34125496571 ps
CPU time 305.38 seconds
Started Jun 07 08:36:05 PM PDT 24
Finished Jun 07 08:41:14 PM PDT 24
Peak memory 294280 kb
Host smart-3298205b-8035-4aad-a558-1fef70820edf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882276159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
34.lc_ctrl_stress_all.3882276159
Directory /workspace/34.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.lc_ctrl_stress_all_with_rand_reset.3367374001
Short name T114
Test name
Test status
Simulation time 49980848644 ps
CPU time 804.82 seconds
Started Jun 07 08:35:51 PM PDT 24
Finished Jun 07 08:49:22 PM PDT 24
Peak memory 316540 kb
Host smart-7a83edef-145b-4aa5-8c39-8667c2e4d7e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3367374001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_ctrl_stress_all_with_rand_reset.3367374001
Directory /workspace/34.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.lc_ctrl_volatile_unlock_smoke.2770883048
Short name T633
Test name
Test status
Simulation time 27004499 ps
CPU time 0.96 seconds
Started Jun 07 08:36:02 PM PDT 24
Finished Jun 07 08:36:07 PM PDT 24
Peak memory 211924 kb
Host smart-b7d2e974-9d63-47f7-982d-1d141c253513
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770883048 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.lc_c
trl_volatile_unlock_smoke.2770883048
Directory /workspace/34.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_alert_test.3617701736
Short name T713
Test name
Test status
Simulation time 108219164 ps
CPU time 1.26 seconds
Started Jun 07 08:35:59 PM PDT 24
Finished Jun 07 08:36:05 PM PDT 24
Peak memory 209160 kb
Host smart-09aaf931-c108-4d74-95bd-b731b81db50d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617701736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_alert_test.3617701736
Directory /workspace/35.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.lc_ctrl_errors.4060283345
Short name T657
Test name
Test status
Simulation time 1480263195 ps
CPU time 16.34 seconds
Started Jun 07 08:35:58 PM PDT 24
Finished Jun 07 08:36:18 PM PDT 24
Peak memory 218112 kb
Host smart-f9f4e5a6-0b92-4637-beb3-49ebb98210b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060283345 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_errors.4060283345
Directory /workspace/35.lc_ctrl_errors/latest

Test location /workspace/coverage/default/35.lc_ctrl_jtag_access.3898396344
Short name T37
Test name
Test status
Simulation time 1438986760 ps
CPU time 9.89 seconds
Started Jun 07 08:35:57 PM PDT 24
Finished Jun 07 08:36:11 PM PDT 24
Peak memory 217556 kb
Host smart-04fcb146-9809-41c7-aaf5-ad89e790ec70
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898396344 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_jtag_access.3898396344
Directory /workspace/35.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/35.lc_ctrl_prog_failure.810686126
Short name T819
Test name
Test status
Simulation time 313939509 ps
CPU time 3.68 seconds
Started Jun 07 08:35:58 PM PDT 24
Finished Jun 07 08:36:06 PM PDT 24
Peak memory 218240 kb
Host smart-8adacc76-a11a-4e3e-a99e-c7d4fd8760f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810686126 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_prog_failure.810686126
Directory /workspace/35.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_mubi.2867037388
Short name T418
Test name
Test status
Simulation time 324111960 ps
CPU time 15.93 seconds
Started Jun 07 08:35:59 PM PDT 24
Finished Jun 07 08:36:19 PM PDT 24
Peak memory 219032 kb
Host smart-bd9b873b-f6b2-483d-a270-f40b971bfcab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867037388 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_mubi.2867037388
Directory /workspace/35.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_digest.1919052518
Short name T221
Test name
Test status
Simulation time 970676264 ps
CPU time 11.72 seconds
Started Jun 07 08:35:57 PM PDT 24
Finished Jun 07 08:36:13 PM PDT 24
Peak memory 218264 kb
Host smart-87fafadd-5d85-4a7f-a46d-2b0424359e40
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919052518 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_d
igest.1919052518
Directory /workspace/35.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/35.lc_ctrl_sec_token_mux.2986942687
Short name T354
Test name
Test status
Simulation time 1312082228 ps
CPU time 9.97 seconds
Started Jun 07 08:35:54 PM PDT 24
Finished Jun 07 08:36:10 PM PDT 24
Peak memory 218276 kb
Host smart-81d3d13a-db3c-4573-9896-d74c4553f422
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986942687 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_sec_token_mux.
2986942687
Directory /workspace/35.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/35.lc_ctrl_security_escalation.2197076737
Short name T244
Test name
Test status
Simulation time 279666459 ps
CPU time 7.2 seconds
Started Jun 07 08:36:01 PM PDT 24
Finished Jun 07 08:36:12 PM PDT 24
Peak memory 224912 kb
Host smart-27e0af48-3a1c-4aa0-8430-3aea2e106e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197076737 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_security_escalation.2197076737
Directory /workspace/35.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/35.lc_ctrl_smoke.2832896427
Short name T492
Test name
Test status
Simulation time 40608115 ps
CPU time 3.01 seconds
Started Jun 07 08:35:54 PM PDT 24
Finished Jun 07 08:36:03 PM PDT 24
Peak memory 214720 kb
Host smart-137c90be-11ba-4889-9a34-3062c014504f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832896427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_smoke.2832896427
Directory /workspace/35.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_failure.802620793
Short name T94
Test name
Test status
Simulation time 276126359 ps
CPU time 29.84 seconds
Started Jun 07 08:35:56 PM PDT 24
Finished Jun 07 08:36:31 PM PDT 24
Peak memory 250892 kb
Host smart-a8499646-678b-4fa8-ab47-9df9aab89215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802620793 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_failure.802620793
Directory /workspace/35.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/35.lc_ctrl_state_post_trans.2316235641
Short name T319
Test name
Test status
Simulation time 56689626 ps
CPU time 6.51 seconds
Started Jun 07 08:36:02 PM PDT 24
Finished Jun 07 08:36:13 PM PDT 24
Peak memory 250932 kb
Host smart-da0bebcd-cef8-4ece-b155-248fde4e5bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316235641 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_ctrl_state_post_trans.2316235641
Directory /workspace/35.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/35.lc_ctrl_stress_all.3873275941
Short name T257
Test name
Test status
Simulation time 3499322753 ps
CPU time 127.28 seconds
Started Jun 07 08:36:04 PM PDT 24
Finished Jun 07 08:38:21 PM PDT 24
Peak memory 251900 kb
Host smart-76d2510c-b9ca-471b-afcb-64883be28925
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873275941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
35.lc_ctrl_stress_all.3873275941
Directory /workspace/35.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.lc_ctrl_volatile_unlock_smoke.3235205196
Short name T162
Test name
Test status
Simulation time 41077011 ps
CPU time 0.83 seconds
Started Jun 07 08:35:55 PM PDT 24
Finished Jun 07 08:36:01 PM PDT 24
Peak memory 211880 kb
Host smart-c132325b-db06-4cac-980c-b5326c88342f
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235205196 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.lc_c
trl_volatile_unlock_smoke.3235205196
Directory /workspace/35.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_alert_test.551898817
Short name T44
Test name
Test status
Simulation time 52944059 ps
CPU time 1.04 seconds
Started Jun 07 08:36:01 PM PDT 24
Finished Jun 07 08:36:06 PM PDT 24
Peak memory 208976 kb
Host smart-fd8a223e-a56b-4c60-9c6a-c16877f7e6b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551898817 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_alert_test.551898817
Directory /workspace/36.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.lc_ctrl_errors.1362949486
Short name T479
Test name
Test status
Simulation time 681110112 ps
CPU time 9.37 seconds
Started Jun 07 08:36:01 PM PDT 24
Finished Jun 07 08:36:14 PM PDT 24
Peak memory 218328 kb
Host smart-ce580bb9-1e8c-4dd2-8e3e-eeb8c46dc989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362949486 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_errors.1362949486
Directory /workspace/36.lc_ctrl_errors/latest

Test location /workspace/coverage/default/36.lc_ctrl_jtag_access.2073708692
Short name T32
Test name
Test status
Simulation time 565367612 ps
CPU time 14.38 seconds
Started Jun 07 08:36:05 PM PDT 24
Finished Jun 07 08:36:22 PM PDT 24
Peak memory 217428 kb
Host smart-fb9178c6-9f75-4ff9-a093-449d1653198f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073708692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_jtag_access.2073708692
Directory /workspace/36.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/36.lc_ctrl_prog_failure.3282376735
Short name T441
Test name
Test status
Simulation time 115759648 ps
CPU time 2.45 seconds
Started Jun 07 08:35:54 PM PDT 24
Finished Jun 07 08:36:02 PM PDT 24
Peak memory 218312 kb
Host smart-45b8ab5d-2c62-4206-bcd2-520661441ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282376735 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_prog_failure.3282376735
Directory /workspace/36.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_mubi.3914089322
Short name T462
Test name
Test status
Simulation time 1300955470 ps
CPU time 16.81 seconds
Started Jun 07 08:35:54 PM PDT 24
Finished Jun 07 08:36:16 PM PDT 24
Peak memory 218968 kb
Host smart-6186fbbe-d84b-4a2e-958e-c6a2040d1983
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914089322 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_mubi.3914089322
Directory /workspace/36.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_digest.1861650099
Short name T669
Test name
Test status
Simulation time 3450004821 ps
CPU time 14.41 seconds
Started Jun 07 08:35:53 PM PDT 24
Finished Jun 07 08:36:13 PM PDT 24
Peak memory 218328 kb
Host smart-cbd7b5c4-faaf-40a2-8ced-98b8f5cda4de
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861650099 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_d
igest.1861650099
Directory /workspace/36.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/36.lc_ctrl_sec_token_mux.2474937599
Short name T771
Test name
Test status
Simulation time 1568001143 ps
CPU time 8.14 seconds
Started Jun 07 08:35:59 PM PDT 24
Finished Jun 07 08:36:11 PM PDT 24
Peak memory 218296 kb
Host smart-54b7bace-01a1-4908-b517-960b4d81703d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474937599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_sec_token_mux.
2474937599
Directory /workspace/36.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/36.lc_ctrl_security_escalation.2786288311
Short name T227
Test name
Test status
Simulation time 2386170744 ps
CPU time 8.35 seconds
Started Jun 07 08:36:00 PM PDT 24
Finished Jun 07 08:36:13 PM PDT 24
Peak memory 218336 kb
Host smart-1b70b527-5870-4017-b805-f17feaf4db39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786288311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_security_escalation.2786288311
Directory /workspace/36.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/36.lc_ctrl_smoke.1355900792
Short name T72
Test name
Test status
Simulation time 234095450 ps
CPU time 2.45 seconds
Started Jun 07 08:36:00 PM PDT 24
Finished Jun 07 08:36:06 PM PDT 24
Peak memory 214480 kb
Host smart-0816b3b3-4dc7-4c83-a182-b2d5210df328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355900792 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_smoke.1355900792
Directory /workspace/36.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_failure.2643207151
Short name T589
Test name
Test status
Simulation time 833298721 ps
CPU time 21.98 seconds
Started Jun 07 08:36:02 PM PDT 24
Finished Jun 07 08:36:28 PM PDT 24
Peak memory 251012 kb
Host smart-ecca3a76-d224-4173-ba75-d390b662e16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643207151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_failure.2643207151
Directory /workspace/36.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/36.lc_ctrl_state_post_trans.838097445
Short name T70
Test name
Test status
Simulation time 193257449 ps
CPU time 7.63 seconds
Started Jun 07 08:36:00 PM PDT 24
Finished Jun 07 08:36:12 PM PDT 24
Peak memory 250944 kb
Host smart-583e37ee-6b33-4843-b656-33a70249ed36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838097445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ctrl_state_post_trans.838097445
Directory /workspace/36.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/36.lc_ctrl_stress_all.73317653
Short name T753
Test name
Test status
Simulation time 6852524392 ps
CPU time 225.76 seconds
Started Jun 07 08:36:00 PM PDT 24
Finished Jun 07 08:39:50 PM PDT 24
Peak memory 267400 kb
Host smart-502f599c-f719-45e3-9f53-92de358298a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73317653 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3
6.lc_ctrl_stress_all.73317653
Directory /workspace/36.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.lc_ctrl_volatile_unlock_smoke.435151953
Short name T565
Test name
Test status
Simulation time 22257844 ps
CPU time 0.93 seconds
Started Jun 07 08:35:54 PM PDT 24
Finished Jun 07 08:36:01 PM PDT 24
Peak memory 211852 kb
Host smart-bc40bd88-41fc-45bf-9c4b-e4e4981677c8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435151953 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.lc_ct
rl_volatile_unlock_smoke.435151953
Directory /workspace/36.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_alert_test.587557772
Short name T807
Test name
Test status
Simulation time 45979031 ps
CPU time 0.89 seconds
Started Jun 07 08:36:05 PM PDT 24
Finished Jun 07 08:36:09 PM PDT 24
Peak memory 208816 kb
Host smart-9d2fe3af-23b7-4673-aa68-e108a7a33fbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587557772 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_alert_test.587557772
Directory /workspace/37.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.lc_ctrl_errors.2809775629
Short name T17
Test name
Test status
Simulation time 422668556 ps
CPU time 11.3 seconds
Started Jun 07 08:35:56 PM PDT 24
Finished Jun 07 08:36:12 PM PDT 24
Peak memory 218256 kb
Host smart-19dc6eb6-fc16-4427-936b-4ec852360a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809775629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_errors.2809775629
Directory /workspace/37.lc_ctrl_errors/latest

Test location /workspace/coverage/default/37.lc_ctrl_jtag_access.1327377795
Short name T637
Test name
Test status
Simulation time 370318604 ps
CPU time 3.92 seconds
Started Jun 07 08:35:56 PM PDT 24
Finished Jun 07 08:36:04 PM PDT 24
Peak memory 217320 kb
Host smart-84ff4617-6e8d-45f9-ae52-ff0529c1ac5e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327377795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_jtag_access.1327377795
Directory /workspace/37.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/37.lc_ctrl_prog_failure.595173741
Short name T216
Test name
Test status
Simulation time 481626233 ps
CPU time 4.85 seconds
Started Jun 07 08:35:58 PM PDT 24
Finished Jun 07 08:36:07 PM PDT 24
Peak memory 218248 kb
Host smart-74d88456-7868-4723-a75b-50869e66ed9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595173741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_prog_failure.595173741
Directory /workspace/37.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_mubi.393465712
Short name T652
Test name
Test status
Simulation time 1106649713 ps
CPU time 13.73 seconds
Started Jun 07 08:36:00 PM PDT 24
Finished Jun 07 08:36:17 PM PDT 24
Peak memory 218304 kb
Host smart-ac7c688f-fb9f-4f57-9e23-954a52f15ed3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393465712 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_mubi.393465712
Directory /workspace/37.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_digest.425896390
Short name T380
Test name
Test status
Simulation time 897572092 ps
CPU time 15.98 seconds
Started Jun 07 08:36:01 PM PDT 24
Finished Jun 07 08:36:22 PM PDT 24
Peak memory 218304 kb
Host smart-7ce24b55-74d2-423f-a76d-931e554025ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425896390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_di
gest.425896390
Directory /workspace/37.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/37.lc_ctrl_sec_token_mux.1379578724
Short name T763
Test name
Test status
Simulation time 400060198 ps
CPU time 9.16 seconds
Started Jun 07 08:36:05 PM PDT 24
Finished Jun 07 08:36:18 PM PDT 24
Peak memory 218280 kb
Host smart-1aa3bb63-d315-4b83-aefb-5fb044bb90c2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379578724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_sec_token_mux.
1379578724
Directory /workspace/37.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/37.lc_ctrl_security_escalation.544778037
Short name T395
Test name
Test status
Simulation time 249268245 ps
CPU time 10.06 seconds
Started Jun 07 08:36:00 PM PDT 24
Finished Jun 07 08:36:15 PM PDT 24
Peak memory 218288 kb
Host smart-77f994eb-98f4-49db-9539-54c9dbb4776e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544778037 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_security_escalation.544778037
Directory /workspace/37.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/37.lc_ctrl_smoke.1814258428
Short name T299
Test name
Test status
Simulation time 59353513 ps
CPU time 3.71 seconds
Started Jun 07 08:35:59 PM PDT 24
Finished Jun 07 08:36:07 PM PDT 24
Peak memory 217796 kb
Host smart-6c0f8dfd-f339-4784-b1cf-0c8951355cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814258428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_smoke.1814258428
Directory /workspace/37.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_failure.415324064
Short name T516
Test name
Test status
Simulation time 835565541 ps
CPU time 22.43 seconds
Started Jun 07 08:36:01 PM PDT 24
Finished Jun 07 08:36:27 PM PDT 24
Peak memory 250916 kb
Host smart-8a2bce03-0a61-4449-84ec-9f834029c62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415324064 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_failure.415324064
Directory /workspace/37.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/37.lc_ctrl_state_post_trans.2078708187
Short name T263
Test name
Test status
Simulation time 267515605 ps
CPU time 7.34 seconds
Started Jun 07 08:36:00 PM PDT 24
Finished Jun 07 08:36:11 PM PDT 24
Peak memory 246820 kb
Host smart-779a244d-e312-49a3-9bec-88a599811754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078708187 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_ctrl_state_post_trans.2078708187
Directory /workspace/37.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/37.lc_ctrl_stress_all.435481418
Short name T588
Test name
Test status
Simulation time 1841626631 ps
CPU time 82.5 seconds
Started Jun 07 08:36:02 PM PDT 24
Finished Jun 07 08:37:29 PM PDT 24
Peak memory 283736 kb
Host smart-48873905-368d-46b5-89fa-b0455ccec929
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435481418 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
37.lc_ctrl_stress_all.435481418
Directory /workspace/37.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.lc_ctrl_volatile_unlock_smoke.1949456118
Short name T845
Test name
Test status
Simulation time 13689833 ps
CPU time 0.91 seconds
Started Jun 07 08:36:01 PM PDT 24
Finished Jun 07 08:36:06 PM PDT 24
Peak memory 211936 kb
Host smart-c9cc9f15-9857-4361-80bb-32f8e3e905e8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949456118 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.lc_c
trl_volatile_unlock_smoke.1949456118
Directory /workspace/37.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_alert_test.2881204011
Short name T75
Test name
Test status
Simulation time 42053420 ps
CPU time 1.21 seconds
Started Jun 07 08:36:03 PM PDT 24
Finished Jun 07 08:36:08 PM PDT 24
Peak memory 209112 kb
Host smart-393b4ca8-8326-46b4-83ef-c9c5c806ce5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881204011 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_alert_test.2881204011
Directory /workspace/38.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.lc_ctrl_errors.1930871968
Short name T482
Test name
Test status
Simulation time 361772494 ps
CPU time 14.26 seconds
Started Jun 07 08:36:02 PM PDT 24
Finished Jun 07 08:36:20 PM PDT 24
Peak memory 218256 kb
Host smart-e6eb2abe-3694-4e2c-ba94-2467a838e8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930871968 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_errors.1930871968
Directory /workspace/38.lc_ctrl_errors/latest

Test location /workspace/coverage/default/38.lc_ctrl_jtag_access.1864256949
Short name T555
Test name
Test status
Simulation time 272486781 ps
CPU time 7.63 seconds
Started Jun 07 08:36:05 PM PDT 24
Finished Jun 07 08:36:16 PM PDT 24
Peak memory 217528 kb
Host smart-2ffc67d4-7d91-46bc-87cd-e52cc4324731
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864256949 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_jtag_access.1864256949
Directory /workspace/38.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/38.lc_ctrl_prog_failure.2350496092
Short name T628
Test name
Test status
Simulation time 347218581 ps
CPU time 6.15 seconds
Started Jun 07 08:36:03 PM PDT 24
Finished Jun 07 08:36:13 PM PDT 24
Peak memory 222720 kb
Host smart-ee921479-c075-4827-b4aa-5472854a8916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350496092 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_prog_failure.2350496092
Directory /workspace/38.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_mubi.2533149072
Short name T209
Test name
Test status
Simulation time 590354253 ps
CPU time 14.35 seconds
Started Jun 07 08:36:05 PM PDT 24
Finished Jun 07 08:36:22 PM PDT 24
Peak memory 226116 kb
Host smart-ab2f06d9-cdfc-4d75-a8e1-bf7dc344a1ef
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533149072 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_mubi.2533149072
Directory /workspace/38.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_digest.2307058407
Short name T97
Test name
Test status
Simulation time 735551122 ps
CPU time 6.67 seconds
Started Jun 07 08:36:04 PM PDT 24
Finished Jun 07 08:36:15 PM PDT 24
Peak memory 218296 kb
Host smart-eec1025b-789f-4f01-b35c-b626e403fc7d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307058407 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_d
igest.2307058407
Directory /workspace/38.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/38.lc_ctrl_sec_token_mux.2265200943
Short name T444
Test name
Test status
Simulation time 336395493 ps
CPU time 8.8 seconds
Started Jun 07 08:36:02 PM PDT 24
Finished Jun 07 08:36:15 PM PDT 24
Peak memory 218124 kb
Host smart-db6b357e-4d45-4d70-bda2-8693a4b1b7f3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265200943 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_sec_token_mux.
2265200943
Directory /workspace/38.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/38.lc_ctrl_security_escalation.507055124
Short name T449
Test name
Test status
Simulation time 274569061 ps
CPU time 8.95 seconds
Started Jun 07 08:36:08 PM PDT 24
Finished Jun 07 08:36:27 PM PDT 24
Peak memory 226108 kb
Host smart-f6f12012-0d35-4619-874a-ec1bd80010eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507055124 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_security_escalation.507055124
Directory /workspace/38.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/38.lc_ctrl_smoke.2799007914
Short name T19
Test name
Test status
Simulation time 39563175 ps
CPU time 3.17 seconds
Started Jun 07 08:36:00 PM PDT 24
Finished Jun 07 08:36:08 PM PDT 24
Peak memory 215012 kb
Host smart-67a14283-3624-4210-8e24-2d4f15c8028a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799007914 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_smoke.2799007914
Directory /workspace/38.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_failure.1001383276
Short name T612
Test name
Test status
Simulation time 175317297 ps
CPU time 20.86 seconds
Started Jun 07 08:36:08 PM PDT 24
Finished Jun 07 08:36:32 PM PDT 24
Peak memory 250888 kb
Host smart-b9bdf6d5-3754-4b53-af35-68e0eeb1cba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001383276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_failure.1001383276
Directory /workspace/38.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/38.lc_ctrl_state_post_trans.1886989554
Short name T174
Test name
Test status
Simulation time 80651593 ps
CPU time 7.91 seconds
Started Jun 07 08:36:06 PM PDT 24
Finished Jun 07 08:36:17 PM PDT 24
Peak memory 251004 kb
Host smart-58cb06de-582d-4747-9876-b0110593ffe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886989554 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_ctrl_state_post_trans.1886989554
Directory /workspace/38.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/38.lc_ctrl_stress_all.3886972225
Short name T379
Test name
Test status
Simulation time 2424900162 ps
CPU time 96.12 seconds
Started Jun 07 08:36:02 PM PDT 24
Finished Jun 07 08:37:42 PM PDT 24
Peak memory 283716 kb
Host smart-983fa9dd-f96e-4f47-a138-2547c077f0be
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886972225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
38.lc_ctrl_stress_all.3886972225
Directory /workspace/38.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.lc_ctrl_volatile_unlock_smoke.2734064213
Short name T603
Test name
Test status
Simulation time 16905612 ps
CPU time 0.85 seconds
Started Jun 07 08:36:05 PM PDT 24
Finished Jun 07 08:36:09 PM PDT 24
Peak memory 211868 kb
Host smart-ae0f515c-1c14-4117-aa5c-c87a0d582985
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734064213 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.lc_c
trl_volatile_unlock_smoke.2734064213
Directory /workspace/38.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_alert_test.67343055
Short name T820
Test name
Test status
Simulation time 14104663 ps
CPU time 0.99 seconds
Started Jun 07 08:36:08 PM PDT 24
Finished Jun 07 08:36:12 PM PDT 24
Peak memory 208940 kb
Host smart-9e761784-284b-4a35-bb7a-86acb73c0058
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67343055 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_alert_test.67343055
Directory /workspace/39.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.lc_ctrl_errors.2265987895
Short name T836
Test name
Test status
Simulation time 518224535 ps
CPU time 14.44 seconds
Started Jun 07 08:36:06 PM PDT 24
Finished Jun 07 08:36:24 PM PDT 24
Peak memory 218176 kb
Host smart-9e0a58bb-87be-40f0-af6b-aea24317bf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265987895 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_errors.2265987895
Directory /workspace/39.lc_ctrl_errors/latest

Test location /workspace/coverage/default/39.lc_ctrl_jtag_access.3721095545
Short name T483
Test name
Test status
Simulation time 2350664813 ps
CPU time 11.84 seconds
Started Jun 07 08:36:07 PM PDT 24
Finished Jun 07 08:36:22 PM PDT 24
Peak memory 217808 kb
Host smart-06637fe2-6f9b-4985-9bbb-4969eb7297d1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721095545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_jtag_access.3721095545
Directory /workspace/39.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/39.lc_ctrl_prog_failure.1404457059
Short name T543
Test name
Test status
Simulation time 25964144 ps
CPU time 2.05 seconds
Started Jun 07 08:36:05 PM PDT 24
Finished Jun 07 08:36:11 PM PDT 24
Peak memory 222044 kb
Host smart-3da0c37f-72f8-43ae-80f8-715f6eaf0713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404457059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_prog_failure.1404457059
Directory /workspace/39.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_mubi.3279860374
Short name T364
Test name
Test status
Simulation time 288681323 ps
CPU time 11.54 seconds
Started Jun 07 08:36:04 PM PDT 24
Finished Jun 07 08:36:19 PM PDT 24
Peak memory 226092 kb
Host smart-ac1ffd9e-4daf-4a19-9fd6-cdc7f64f72e3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279860374 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_mubi.3279860374
Directory /workspace/39.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_digest.4264128380
Short name T423
Test name
Test status
Simulation time 1649834771 ps
CPU time 16.67 seconds
Started Jun 07 08:36:03 PM PDT 24
Finished Jun 07 08:36:24 PM PDT 24
Peak memory 226088 kb
Host smart-68b70e77-1c83-42b4-b87e-5ed8f3cb61af
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264128380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_d
igest.4264128380
Directory /workspace/39.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/39.lc_ctrl_sec_token_mux.459952145
Short name T524
Test name
Test status
Simulation time 836178242 ps
CPU time 8.89 seconds
Started Jun 07 08:36:05 PM PDT 24
Finished Jun 07 08:36:17 PM PDT 24
Peak memory 226096 kb
Host smart-ad05611a-ce5c-4bc1-a7de-05e838cf2bab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459952145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_sec_token_mux.459952145
Directory /workspace/39.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/39.lc_ctrl_security_escalation.3616608292
Short name T316
Test name
Test status
Simulation time 228455234 ps
CPU time 9.24 seconds
Started Jun 07 08:36:06 PM PDT 24
Finished Jun 07 08:36:18 PM PDT 24
Peak memory 225172 kb
Host smart-1b720c8d-7f8c-4870-b845-56961fd38766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616608292 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_security_escalation.3616608292
Directory /workspace/39.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/39.lc_ctrl_smoke.2785364962
Short name T76
Test name
Test status
Simulation time 348431446 ps
CPU time 2.61 seconds
Started Jun 07 08:36:03 PM PDT 24
Finished Jun 07 08:36:09 PM PDT 24
Peak memory 217764 kb
Host smart-bef5c4e4-42ab-461b-b1df-eadc6d653cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785364962 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_smoke.2785364962
Directory /workspace/39.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_failure.88514663
Short name T231
Test name
Test status
Simulation time 301970348 ps
CPU time 27.25 seconds
Started Jun 07 08:36:04 PM PDT 24
Finished Jun 07 08:36:35 PM PDT 24
Peak memory 250892 kb
Host smart-de8536da-33fb-4403-ae64-87cefa9f98b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88514663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_failure.88514663
Directory /workspace/39.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/39.lc_ctrl_state_post_trans.180897122
Short name T632
Test name
Test status
Simulation time 403346064 ps
CPU time 3.73 seconds
Started Jun 07 08:36:07 PM PDT 24
Finished Jun 07 08:36:14 PM PDT 24
Peak memory 222048 kb
Host smart-d491a00d-e751-4620-a2a4-eab43220bece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180897122 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_ctrl_state_post_trans.180897122
Directory /workspace/39.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/39.lc_ctrl_stress_all.4258158114
Short name T721
Test name
Test status
Simulation time 1426125235 ps
CPU time 28.21 seconds
Started Jun 07 08:36:05 PM PDT 24
Finished Jun 07 08:36:37 PM PDT 24
Peak memory 250836 kb
Host smart-0b7bf8cc-1978-44c7-9ec4-c0afbf24cdf1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258158114 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
39.lc_ctrl_stress_all.4258158114
Directory /workspace/39.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.lc_ctrl_volatile_unlock_smoke.1686490691
Short name T549
Test name
Test status
Simulation time 11961398 ps
CPU time 1 seconds
Started Jun 07 08:36:07 PM PDT 24
Finished Jun 07 08:36:11 PM PDT 24
Peak memory 211904 kb
Host smart-d9879760-5ba5-4b4c-985a-795dd026be32
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686490691 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.lc_c
trl_volatile_unlock_smoke.1686490691
Directory /workspace/39.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_alert_test.2780771390
Short name T711
Test name
Test status
Simulation time 73141375 ps
CPU time 1.21 seconds
Started Jun 07 08:34:51 PM PDT 24
Finished Jun 07 08:34:56 PM PDT 24
Peak memory 208984 kb
Host smart-d76f1b69-fff8-4fc0-8b2e-f4914492a9e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780771390 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_alert_test.2780771390
Directory /workspace/4.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.lc_ctrl_claim_transition_if.1159669312
Short name T523
Test name
Test status
Simulation time 12056628 ps
CPU time 0.99 seconds
Started Jun 07 08:34:22 PM PDT 24
Finished Jun 07 08:34:34 PM PDT 24
Peak memory 209024 kb
Host smart-74c74e64-8f28-4740-9d97-89d30433b088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159669312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_claim_transition_if.1159669312
Directory /workspace/4.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/4.lc_ctrl_errors.3757346023
Short name T728
Test name
Test status
Simulation time 5985586704 ps
CPU time 17.95 seconds
Started Jun 07 08:34:44 PM PDT 24
Finished Jun 07 08:35:06 PM PDT 24
Peak memory 219020 kb
Host smart-d6cf4a21-d618-4eba-ae41-a92b38dff8cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3757346023 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_errors.3757346023
Directory /workspace/4.lc_ctrl_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_access.1274707336
Short name T372
Test name
Test status
Simulation time 715217612 ps
CPU time 4.62 seconds
Started Jun 07 08:34:23 PM PDT 24
Finished Jun 07 08:34:38 PM PDT 24
Peak memory 217132 kb
Host smart-1384a2df-1855-4b10-a4e8-bf8b75016488
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274707336 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_access.1274707336
Directory /workspace/4.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_errors.995324184
Short name T556
Test name
Test status
Simulation time 3921656971 ps
CPU time 18.51 seconds
Started Jun 07 08:34:25 PM PDT 24
Finished Jun 07 08:34:54 PM PDT 24
Peak memory 218216 kb
Host smart-0a623896-39b0-4a80-b51f-5e4ac442b87d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995324184 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_err
ors.995324184
Directory /workspace/4.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_priority.3592469172
Short name T295
Test name
Test status
Simulation time 1282964123 ps
CPU time 5.87 seconds
Started Jun 07 08:34:23 PM PDT 24
Finished Jun 07 08:34:39 PM PDT 24
Peak memory 217368 kb
Host smart-2f8b0e93-2962-4a81-a84f-018ba90693ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592469172 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_priority.3
592469172
Directory /workspace/4.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_prog_failure.4286609671
Short name T585
Test name
Test status
Simulation time 63733877 ps
CPU time 2.04 seconds
Started Jun 07 08:34:45 PM PDT 24
Finished Jun 07 08:34:51 PM PDT 24
Peak memory 221760 kb
Host smart-e050bb9d-58fe-4802-b60c-987aa10fc83f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286609671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag
_prog_failure.4286609671
Directory /workspace/4.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_regwen_during_op.924919746
Short name T842
Test name
Test status
Simulation time 3809096009 ps
CPU time 13.87 seconds
Started Jun 07 08:34:51 PM PDT 24
Finished Jun 07 08:35:08 PM PDT 24
Peak memory 217800 kb
Host smart-8334471e-c975-4b32-b444-3570c8c1f67a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924919746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_regwen_during_op.924919746
Directory /workspace/4.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_smoke.3355649325
Short name T487
Test name
Test status
Simulation time 333306935 ps
CPU time 4.6 seconds
Started Jun 07 08:34:47 PM PDT 24
Finished Jun 07 08:34:54 PM PDT 24
Peak memory 217680 kb
Host smart-0183b5ce-8244-4df9-b734-167c220349f9
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355649325 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_smoke.
3355649325
Directory /workspace/4.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_failure.1163536596
Short name T804
Test name
Test status
Simulation time 3180108723 ps
CPU time 56.12 seconds
Started Jun 07 08:34:32 PM PDT 24
Finished Jun 07 08:35:37 PM PDT 24
Peak memory 275456 kb
Host smart-95412a74-700e-490f-b7ba-532f04d7d225
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163536596 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jta
g_state_failure.1163536596
Directory /workspace/4.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_jtag_state_post_trans.184176031
Short name T861
Test name
Test status
Simulation time 4877584140 ps
CPU time 9.66 seconds
Started Jun 07 08:34:22 PM PDT 24
Finished Jun 07 08:34:42 PM PDT 24
Peak memory 224564 kb
Host smart-6805948e-08d8-46fa-bf51-549f3c4a8442
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184176031 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_j
tag_state_post_trans.184176031
Directory /workspace/4.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_prog_failure.3255135438
Short name T525
Test name
Test status
Simulation time 144835373 ps
CPU time 3.48 seconds
Started Jun 07 08:34:43 PM PDT 24
Finished Jun 07 08:34:51 PM PDT 24
Peak memory 222284 kb
Host smart-4e422408-860b-4d0c-acaf-fb502165bd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255135438 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_prog_failure.3255135438
Directory /workspace/4.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_regwen_during_op.3079189273
Short name T180
Test name
Test status
Simulation time 1400899039 ps
CPU time 7.05 seconds
Started Jun 07 08:34:22 PM PDT 24
Finished Jun 07 08:34:40 PM PDT 24
Peak memory 214584 kb
Host smart-d1d643af-bd58-4681-b769-3dcbc5d3d120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079189273 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_regwen_during_op.3079189273
Directory /workspace/4.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_cm.3343096199
Short name T90
Test name
Test status
Simulation time 221349319 ps
CPU time 25.25 seconds
Started Jun 07 08:34:48 PM PDT 24
Finished Jun 07 08:35:16 PM PDT 24
Peak memory 269380 kb
Host smart-2d68a9db-7a12-4a4a-928d-df04014f11fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343096199 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_cm.3343096199
Directory /workspace/4.lc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_mubi.2563818079
Short name T844
Test name
Test status
Simulation time 2727210629 ps
CPU time 16.38 seconds
Started Jun 07 08:34:34 PM PDT 24
Finished Jun 07 08:34:59 PM PDT 24
Peak memory 220124 kb
Host smart-9ffbe97e-e7b6-470d-877d-11aed95933ba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563818079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_mubi.2563818079
Directory /workspace/4.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_digest.1066337731
Short name T242
Test name
Test status
Simulation time 1221539801 ps
CPU time 11.22 seconds
Started Jun 07 08:34:23 PM PDT 24
Finished Jun 07 08:34:45 PM PDT 24
Peak memory 218300 kb
Host smart-80bfbc58-46c7-4b58-9ae9-1eb4a08d9229
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066337731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_di
gest.1066337731
Directory /workspace/4.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/4.lc_ctrl_sec_token_mux.3618571757
Short name T542
Test name
Test status
Simulation time 466305369 ps
CPU time 10.92 seconds
Started Jun 07 08:34:26 PM PDT 24
Finished Jun 07 08:34:47 PM PDT 24
Peak memory 218232 kb
Host smart-08dae02c-64c6-4ec5-990d-e36e2e8b8169
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618571757 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_sec_token_mux.3
618571757
Directory /workspace/4.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/4.lc_ctrl_security_escalation.1597297028
Short name T503
Test name
Test status
Simulation time 510477333 ps
CPU time 11.5 seconds
Started Jun 07 08:34:22 PM PDT 24
Finished Jun 07 08:34:44 PM PDT 24
Peak memory 218296 kb
Host smart-13d0a8a1-0316-4353-bde3-9b098acdedc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597297028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_security_escalation.1597297028
Directory /workspace/4.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/4.lc_ctrl_smoke.407636701
Short name T383
Test name
Test status
Simulation time 367221553 ps
CPU time 2.49 seconds
Started Jun 07 08:34:22 PM PDT 24
Finished Jun 07 08:34:35 PM PDT 24
Peak memory 214632 kb
Host smart-b03e50af-6932-4062-a135-e566b31f2392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407636701 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_smoke.407636701
Directory /workspace/4.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_failure.2579499766
Short name T401
Test name
Test status
Simulation time 634369752 ps
CPU time 15.36 seconds
Started Jun 07 08:34:41 PM PDT 24
Finished Jun 07 08:35:01 PM PDT 24
Peak memory 250828 kb
Host smart-c80744fa-da44-4e98-8271-8b621f09e0f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579499766 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_failure.2579499766
Directory /workspace/4.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/4.lc_ctrl_state_post_trans.1483497146
Short name T699
Test name
Test status
Simulation time 56821355 ps
CPU time 3.42 seconds
Started Jun 07 08:34:34 PM PDT 24
Finished Jun 07 08:34:46 PM PDT 24
Peak memory 226248 kb
Host smart-eb58e409-ef6a-4ca1-8f11-bc9b01c58740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483497146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_state_post_trans.1483497146
Directory /workspace/4.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/4.lc_ctrl_stress_all.3677675920
Short name T428
Test name
Test status
Simulation time 3483464067 ps
CPU time 126.25 seconds
Started Jun 07 08:34:46 PM PDT 24
Finished Jun 07 08:36:56 PM PDT 24
Peak memory 266396 kb
Host smart-f794dae0-734d-4d78-b35a-fae557b3d3da
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677675920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.lc_ctrl_stress_all.3677675920
Directory /workspace/4.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.lc_ctrl_volatile_unlock_smoke.3679396719
Short name T563
Test name
Test status
Simulation time 14223743 ps
CPU time 1.13 seconds
Started Jun 07 08:34:51 PM PDT 24
Finished Jun 07 08:34:55 PM PDT 24
Peak memory 211848 kb
Host smart-d6ee8bb7-1c08-4ea4-89fc-e06594be8531
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679396719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.lc_ct
rl_volatile_unlock_smoke.3679396719
Directory /workspace/4.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_alert_test.1047124855
Short name T243
Test name
Test status
Simulation time 29430124 ps
CPU time 1.01 seconds
Started Jun 07 08:36:11 PM PDT 24
Finished Jun 07 08:36:18 PM PDT 24
Peak memory 209008 kb
Host smart-0c65d250-042e-47d7-9cb9-d779d16e5654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047124855 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_alert_test.1047124855
Directory /workspace/40.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.lc_ctrl_errors.3497070349
Short name T560
Test name
Test status
Simulation time 1171014551 ps
CPU time 14.64 seconds
Started Jun 07 08:36:09 PM PDT 24
Finished Jun 07 08:36:28 PM PDT 24
Peak memory 218256 kb
Host smart-910b4a59-578e-47e3-a489-0ecf4591229b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497070349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_errors.3497070349
Directory /workspace/40.lc_ctrl_errors/latest

Test location /workspace/coverage/default/40.lc_ctrl_jtag_access.2145741075
Short name T581
Test name
Test status
Simulation time 355936479 ps
CPU time 1.06 seconds
Started Jun 07 08:36:09 PM PDT 24
Finished Jun 07 08:36:14 PM PDT 24
Peak memory 217096 kb
Host smart-5ac5b142-733a-49f6-b2bc-3c87b9a94040
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145741075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_jtag_access.2145741075
Directory /workspace/40.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/40.lc_ctrl_prog_failure.2767552108
Short name T429
Test name
Test status
Simulation time 107906096 ps
CPU time 2.98 seconds
Started Jun 07 08:36:08 PM PDT 24
Finished Jun 07 08:36:14 PM PDT 24
Peak memory 218224 kb
Host smart-fa872351-05ae-40ed-8786-2ae76255253c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767552108 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_prog_failure.2767552108
Directory /workspace/40.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_mubi.2587863400
Short name T450
Test name
Test status
Simulation time 757997309 ps
CPU time 13.89 seconds
Started Jun 07 08:36:10 PM PDT 24
Finished Jun 07 08:36:29 PM PDT 24
Peak memory 218960 kb
Host smart-096198fc-9e48-400e-9a56-4d05cef09715
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587863400 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_mubi.2587863400
Directory /workspace/40.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_digest.3164758001
Short name T404
Test name
Test status
Simulation time 2989363416 ps
CPU time 17.2 seconds
Started Jun 07 08:36:10 PM PDT 24
Finished Jun 07 08:36:32 PM PDT 24
Peak memory 219040 kb
Host smart-87652c3d-1b2e-40a8-81d0-a5d9269e3c76
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164758001 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_d
igest.3164758001
Directory /workspace/40.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/40.lc_ctrl_sec_token_mux.2431916852
Short name T568
Test name
Test status
Simulation time 1007416859 ps
CPU time 6.89 seconds
Started Jun 07 08:36:11 PM PDT 24
Finished Jun 07 08:36:24 PM PDT 24
Peak memory 218276 kb
Host smart-b6094d8f-b46f-4baa-9822-da09e5dc6265
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431916852 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_sec_token_mux.
2431916852
Directory /workspace/40.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/40.lc_ctrl_security_escalation.3415685254
Short name T282
Test name
Test status
Simulation time 482800158 ps
CPU time 6.39 seconds
Started Jun 07 08:36:14 PM PDT 24
Finished Jun 07 08:36:26 PM PDT 24
Peak memory 224852 kb
Host smart-196d2fc6-fc80-4674-9fd2-49c1310d87c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415685254 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_security_escalation.3415685254
Directory /workspace/40.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/40.lc_ctrl_smoke.2470793349
Short name T417
Test name
Test status
Simulation time 37805809 ps
CPU time 1.66 seconds
Started Jun 07 08:36:01 PM PDT 24
Finished Jun 07 08:36:07 PM PDT 24
Peak memory 217712 kb
Host smart-3cbfa04d-1237-4c24-90d1-d69b64b25a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470793349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_smoke.2470793349
Directory /workspace/40.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_failure.1083649319
Short name T546
Test name
Test status
Simulation time 387287220 ps
CPU time 21.63 seconds
Started Jun 07 08:36:05 PM PDT 24
Finished Jun 07 08:36:30 PM PDT 24
Peak memory 251000 kb
Host smart-ea6cf210-8923-46af-9219-468f1489a43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083649319 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_failure.1083649319
Directory /workspace/40.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/40.lc_ctrl_state_post_trans.2733745724
Short name T415
Test name
Test status
Simulation time 357447969 ps
CPU time 6.83 seconds
Started Jun 07 08:36:05 PM PDT 24
Finished Jun 07 08:36:15 PM PDT 24
Peak memory 250384 kb
Host smart-4c607ffd-1cbd-42b7-9da2-82bb68a63b47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733745724 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_state_post_trans.2733745724
Directory /workspace/40.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all.2010431480
Short name T616
Test name
Test status
Simulation time 334662307579 ps
CPU time 277.13 seconds
Started Jun 07 08:36:11 PM PDT 24
Finished Jun 07 08:40:54 PM PDT 24
Peak memory 277412 kb
Host smart-5c0a8225-f1b3-4f25-b184-cfabbb517a94
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010431480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
40.lc_ctrl_stress_all.2010431480
Directory /workspace/40.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.lc_ctrl_stress_all_with_rand_reset.1925211847
Short name T117
Test name
Test status
Simulation time 45377651426 ps
CPU time 192.45 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:39:30 PM PDT 24
Peak memory 316624 kb
Host smart-0008889a-a3a5-451c-a900-8460f6e5d2e6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1925211847 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_ctrl_stress_all_with_rand_reset.1925211847
Directory /workspace/40.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.lc_ctrl_volatile_unlock_smoke.2237309035
Short name T308
Test name
Test status
Simulation time 205807512 ps
CPU time 0.94 seconds
Started Jun 07 08:36:04 PM PDT 24
Finished Jun 07 08:36:08 PM PDT 24
Peak memory 211952 kb
Host smart-f484fdd0-635b-4692-b54b-6a360e8be547
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237309035 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.lc_c
trl_volatile_unlock_smoke.2237309035
Directory /workspace/40.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_alert_test.1208847059
Short name T471
Test name
Test status
Simulation time 320306810 ps
CPU time 0.93 seconds
Started Jun 07 08:36:10 PM PDT 24
Finished Jun 07 08:36:16 PM PDT 24
Peak memory 209100 kb
Host smart-7011dac1-f877-4b41-8943-029228890556
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208847059 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_alert_test.1208847059
Directory /workspace/41.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.lc_ctrl_errors.2240245034
Short name T104
Test name
Test status
Simulation time 1418358749 ps
CPU time 13.29 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:31 PM PDT 24
Peak memory 218100 kb
Host smart-8c6a812c-31f3-4a5e-afde-8c2386c972f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240245034 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_errors.2240245034
Directory /workspace/41.lc_ctrl_errors/latest

Test location /workspace/coverage/default/41.lc_ctrl_jtag_access.1550562964
Short name T686
Test name
Test status
Simulation time 3298780627 ps
CPU time 5.12 seconds
Started Jun 07 08:36:09 PM PDT 24
Finished Jun 07 08:36:18 PM PDT 24
Peak memory 217748 kb
Host smart-5165bd36-c344-45c7-ab70-c311bd6ed50d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550562964 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_jtag_access.1550562964
Directory /workspace/41.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/41.lc_ctrl_prog_failure.46217227
Short name T108
Test name
Test status
Simulation time 516468797 ps
CPU time 2.95 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:21 PM PDT 24
Peak memory 218220 kb
Host smart-00e2b60d-17cb-4552-8c19-e09ca5861753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46217227 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_prog_failure.46217227
Directory /workspace/41.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_mubi.3771415697
Short name T671
Test name
Test status
Simulation time 1309051969 ps
CPU time 13.96 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:31 PM PDT 24
Peak memory 219004 kb
Host smart-a395f327-c897-465b-a405-4c2ed86a2929
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771415697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_mubi.3771415697
Directory /workspace/41.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_digest.2649086804
Short name T461
Test name
Test status
Simulation time 489705784 ps
CPU time 10.59 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:28 PM PDT 24
Peak memory 218248 kb
Host smart-039d9c8c-3c60-4b6c-8b74-040d612f8b8a
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649086804 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_d
igest.2649086804
Directory /workspace/41.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/41.lc_ctrl_sec_token_mux.937948533
Short name T615
Test name
Test status
Simulation time 211700790 ps
CPU time 8.8 seconds
Started Jun 07 08:36:13 PM PDT 24
Finished Jun 07 08:36:28 PM PDT 24
Peak memory 218260 kb
Host smart-b7e1a9d9-e506-4e59-8402-8f5d7c3f1f92
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937948533 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_sec_token_mux.937948533
Directory /workspace/41.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/41.lc_ctrl_security_escalation.659077905
Short name T826
Test name
Test status
Simulation time 617748193 ps
CPU time 7.58 seconds
Started Jun 07 08:36:09 PM PDT 24
Finished Jun 07 08:36:20 PM PDT 24
Peak memory 218272 kb
Host smart-8f639345-465e-4ceb-a7d0-8df9d58842dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659077905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_security_escalation.659077905
Directory /workspace/41.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/41.lc_ctrl_smoke.2721939365
Short name T78
Test name
Test status
Simulation time 68374501 ps
CPU time 2.52 seconds
Started Jun 07 08:36:09 PM PDT 24
Finished Jun 07 08:36:16 PM PDT 24
Peak memory 214344 kb
Host smart-ecb4a37d-3da7-458a-909c-89f10e8c8d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721939365 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_smoke.2721939365
Directory /workspace/41.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_failure.3495953954
Short name T323
Test name
Test status
Simulation time 1169389302 ps
CPU time 22.81 seconds
Started Jun 07 08:36:11 PM PDT 24
Finished Jun 07 08:36:39 PM PDT 24
Peak memory 250924 kb
Host smart-df7fc20e-07c5-48b3-a1b6-7780d0a0cf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495953954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_failure.3495953954
Directory /workspace/41.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/41.lc_ctrl_state_post_trans.3706922762
Short name T368
Test name
Test status
Simulation time 196557193 ps
CPU time 10.82 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:28 PM PDT 24
Peak memory 250896 kb
Host smart-93a5fc5c-b7a0-422c-803f-4170cc5de1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706922762 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_ctrl_state_post_trans.3706922762
Directory /workspace/41.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/41.lc_ctrl_stress_all.255452287
Short name T534
Test name
Test status
Simulation time 483176909 ps
CPU time 14.54 seconds
Started Jun 07 08:36:11 PM PDT 24
Finished Jun 07 08:36:31 PM PDT 24
Peak memory 250980 kb
Host smart-a4add43f-9863-44bc-9f88-984816ec0cc8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255452287 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
41.lc_ctrl_stress_all.255452287
Directory /workspace/41.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2756651013
Short name T627
Test name
Test status
Simulation time 31256844 ps
CPU time 0.88 seconds
Started Jun 07 08:36:10 PM PDT 24
Finished Jun 07 08:36:17 PM PDT 24
Peak memory 211880 kb
Host smart-85019c13-99d5-4575-b2ba-f37fe7502c19
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756651013 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.lc_c
trl_volatile_unlock_smoke.2756651013
Directory /workspace/41.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_alert_test.1356633809
Short name T286
Test name
Test status
Simulation time 17576479 ps
CPU time 1.13 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:19 PM PDT 24
Peak memory 208848 kb
Host smart-ab41bbaf-05ab-43ec-b0ee-02db7f8c15e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356633809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_alert_test.1356633809
Directory /workspace/42.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.lc_ctrl_errors.63417424
Short name T779
Test name
Test status
Simulation time 546750496 ps
CPU time 12.09 seconds
Started Jun 07 08:36:11 PM PDT 24
Finished Jun 07 08:36:28 PM PDT 24
Peak memory 218220 kb
Host smart-74a8117f-f1a5-48ec-8228-46bd077c156a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63417424 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_errors.63417424
Directory /workspace/42.lc_ctrl_errors/latest

Test location /workspace/coverage/default/42.lc_ctrl_jtag_access.2101160589
Short name T7
Test name
Test status
Simulation time 130561269 ps
CPU time 1.98 seconds
Started Jun 07 08:36:14 PM PDT 24
Finished Jun 07 08:36:22 PM PDT 24
Peak memory 217124 kb
Host smart-b820ce46-5f51-409e-8672-a864f7b9a9db
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101160589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_jtag_access.2101160589
Directory /workspace/42.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/42.lc_ctrl_prog_failure.453752966
Short name T466
Test name
Test status
Simulation time 45610491 ps
CPU time 2.14 seconds
Started Jun 07 08:36:11 PM PDT 24
Finished Jun 07 08:36:19 PM PDT 24
Peak memory 218232 kb
Host smart-e2ebb6d0-2fce-4927-b689-a5b0894e3e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453752966 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_prog_failure.453752966
Directory /workspace/42.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_digest.1432977340
Short name T586
Test name
Test status
Simulation time 279777292 ps
CPU time 11.86 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:29 PM PDT 24
Peak memory 226048 kb
Host smart-5f8f2f55-b5c5-41f0-9b9b-8cbb9e44c755
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432977340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_d
igest.1432977340
Directory /workspace/42.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/42.lc_ctrl_sec_token_mux.2629337924
Short name T834
Test name
Test status
Simulation time 435767870 ps
CPU time 11.61 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:35 PM PDT 24
Peak memory 218292 kb
Host smart-4fa032e7-e2c4-4535-8f7a-ce2edadfd6f4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629337924 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_sec_token_mux.
2629337924
Directory /workspace/42.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/42.lc_ctrl_security_escalation.1039503956
Short name T60
Test name
Test status
Simulation time 871190893 ps
CPU time 12 seconds
Started Jun 07 08:36:11 PM PDT 24
Finished Jun 07 08:36:28 PM PDT 24
Peak memory 224940 kb
Host smart-443c0411-02d7-4488-9f34-6c7ea6262c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039503956 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_security_escalation.1039503956
Directory /workspace/42.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/42.lc_ctrl_smoke.2908860382
Short name T324
Test name
Test status
Simulation time 67999950 ps
CPU time 2.39 seconds
Started Jun 07 08:36:09 PM PDT 24
Finished Jun 07 08:36:15 PM PDT 24
Peak memory 214392 kb
Host smart-1b08ac8e-3a67-43bb-980d-d6dac6092df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908860382 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_smoke.2908860382
Directory /workspace/42.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_failure.1588213134
Short name T235
Test name
Test status
Simulation time 753460382 ps
CPU time 31.2 seconds
Started Jun 07 08:36:09 PM PDT 24
Finished Jun 07 08:36:45 PM PDT 24
Peak memory 250876 kb
Host smart-686df66a-b52b-41fc-acea-6e106d951a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588213134 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_failure.1588213134
Directory /workspace/42.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/42.lc_ctrl_state_post_trans.2351203622
Short name T456
Test name
Test status
Simulation time 903237705 ps
CPU time 7.62 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:31 PM PDT 24
Peak memory 247332 kb
Host smart-e76333b0-9178-4193-be88-f13759ada008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351203622 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_state_post_trans.2351203622
Directory /workspace/42.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all.1518331965
Short name T811
Test name
Test status
Simulation time 10786910283 ps
CPU time 174.3 seconds
Started Jun 07 08:36:13 PM PDT 24
Finished Jun 07 08:39:13 PM PDT 24
Peak memory 250776 kb
Host smart-f27399b8-1c78-4a23-aa80-bf4c4141dcd2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518331965 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
42.lc_ctrl_stress_all.1518331965
Directory /workspace/42.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.lc_ctrl_stress_all_with_rand_reset.4003341192
Short name T116
Test name
Test status
Simulation time 26529573386 ps
CPU time 696.31 seconds
Started Jun 07 08:36:11 PM PDT 24
Finished Jun 07 08:47:52 PM PDT 24
Peak memory 333152 kb
Host smart-5f883694-6441-4467-92a8-0ac4ca23a964
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=4003341192 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_ctrl_stress_all_with_rand_reset.4003341192
Directory /workspace/42.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.lc_ctrl_volatile_unlock_smoke.3722673111
Short name T349
Test name
Test status
Simulation time 120493838 ps
CPU time 0.93 seconds
Started Jun 07 08:36:10 PM PDT 24
Finished Jun 07 08:36:16 PM PDT 24
Peak memory 212904 kb
Host smart-0614fabc-ae5a-443a-a538-bb2892ea62f8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722673111 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.lc_c
trl_volatile_unlock_smoke.3722673111
Directory /workspace/42.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_alert_test.3686199522
Short name T767
Test name
Test status
Simulation time 26216485 ps
CPU time 1.01 seconds
Started Jun 07 08:36:10 PM PDT 24
Finished Jun 07 08:36:15 PM PDT 24
Peak memory 209008 kb
Host smart-dbc44153-330c-4737-8816-52182345c26f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686199522 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_alert_test.3686199522
Directory /workspace/43.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.lc_ctrl_errors.1026261406
Short name T51
Test name
Test status
Simulation time 1500659766 ps
CPU time 13.41 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:31 PM PDT 24
Peak memory 218148 kb
Host smart-04a096a5-1378-40de-bc39-b2ad5a36dfaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026261406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_errors.1026261406
Directory /workspace/43.lc_ctrl_errors/latest

Test location /workspace/coverage/default/43.lc_ctrl_jtag_access.2127485930
Short name T634
Test name
Test status
Simulation time 5154194436 ps
CPU time 4.73 seconds
Started Jun 07 08:36:11 PM PDT 24
Finished Jun 07 08:36:21 PM PDT 24
Peak memory 217652 kb
Host smart-7c3c8c2c-bd5c-45c9-9b58-304a31e7d27d
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127485930 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_jtag_access.2127485930
Directory /workspace/43.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/43.lc_ctrl_prog_failure.100281168
Short name T554
Test name
Test status
Simulation time 26772733 ps
CPU time 1.9 seconds
Started Jun 07 08:36:11 PM PDT 24
Finished Jun 07 08:36:18 PM PDT 24
Peak memory 218240 kb
Host smart-5fd3361d-7892-42b9-9de8-1eb2ec0bdc88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100281168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_prog_failure.100281168
Directory /workspace/43.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_mubi.2148064091
Short name T347
Test name
Test status
Simulation time 458827123 ps
CPU time 9.68 seconds
Started Jun 07 08:36:10 PM PDT 24
Finished Jun 07 08:36:25 PM PDT 24
Peak memory 226136 kb
Host smart-79e66b88-310b-4f86-8142-b21b9eb6240e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148064091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_mubi.2148064091
Directory /workspace/43.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_digest.91380142
Short name T693
Test name
Test status
Simulation time 869768001 ps
CPU time 16.28 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:33 PM PDT 24
Peak memory 218272 kb
Host smart-89f26137-1dfe-4e96-aa28-03d4c3c2b952
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91380142 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_dig
est_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_dig
est.91380142
Directory /workspace/43.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/43.lc_ctrl_sec_token_mux.901016214
Short name T645
Test name
Test status
Simulation time 3150364800 ps
CPU time 7.37 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:25 PM PDT 24
Peak memory 218312 kb
Host smart-a6f4e776-30b9-4186-8def-02806d205296
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901016214 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_sec_token_mux.901016214
Directory /workspace/43.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/43.lc_ctrl_security_escalation.101407552
Short name T578
Test name
Test status
Simulation time 257920365 ps
CPU time 7.97 seconds
Started Jun 07 08:36:13 PM PDT 24
Finished Jun 07 08:36:26 PM PDT 24
Peak memory 218428 kb
Host smart-7abc6266-79f5-445f-be39-20149633b84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101407552 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_security_escalation.101407552
Directory /workspace/43.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/43.lc_ctrl_smoke.1835477289
Short name T454
Test name
Test status
Simulation time 62618779 ps
CPU time 1.55 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:19 PM PDT 24
Peak memory 217784 kb
Host smart-8599a17e-a96c-45b3-b649-c7cb68772354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835477289 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_smoke.1835477289
Directory /workspace/43.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_failure.3782037531
Short name T448
Test name
Test status
Simulation time 332877722 ps
CPU time 30.16 seconds
Started Jun 07 08:36:10 PM PDT 24
Finished Jun 07 08:36:45 PM PDT 24
Peak memory 250884 kb
Host smart-846b30f8-3938-445e-be03-38544ffde6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782037531 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_failure.3782037531
Directory /workspace/43.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/43.lc_ctrl_state_post_trans.1753475709
Short name T643
Test name
Test status
Simulation time 122026121 ps
CPU time 9.59 seconds
Started Jun 07 08:36:11 PM PDT 24
Finished Jun 07 08:36:25 PM PDT 24
Peak memory 250916 kb
Host smart-0589ad1b-8c82-4080-a171-eef89f56930e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753475709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_ctrl_state_post_trans.1753475709
Directory /workspace/43.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/43.lc_ctrl_stress_all.2146220131
Short name T533
Test name
Test status
Simulation time 15807955363 ps
CPU time 76.37 seconds
Started Jun 07 08:36:08 PM PDT 24
Finished Jun 07 08:37:28 PM PDT 24
Peak memory 220316 kb
Host smart-e08424f5-1332-42be-8b97-418c6f09bf08
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146220131 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
43.lc_ctrl_stress_all.2146220131
Directory /workspace/43.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.lc_ctrl_volatile_unlock_smoke.2603212103
Short name T234
Test name
Test status
Simulation time 13436093 ps
CPU time 0.88 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:19 PM PDT 24
Peak memory 211864 kb
Host smart-88e1ee65-8367-4bfc-8c15-0ea87364876d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603212103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.lc_c
trl_volatile_unlock_smoke.2603212103
Directory /workspace/43.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_alert_test.3495276427
Short name T729
Test name
Test status
Simulation time 66785652 ps
CPU time 0.89 seconds
Started Jun 07 08:36:15 PM PDT 24
Finished Jun 07 08:36:22 PM PDT 24
Peak memory 208996 kb
Host smart-5194ea8e-fc5e-4488-9d97-97d98c849c73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495276427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_alert_test.3495276427
Directory /workspace/44.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.lc_ctrl_errors.3023796853
Short name T50
Test name
Test status
Simulation time 276024888 ps
CPU time 13.87 seconds
Started Jun 07 08:36:13 PM PDT 24
Finished Jun 07 08:36:33 PM PDT 24
Peak memory 218240 kb
Host smart-d2f4e7cd-997d-4f53-b318-7bc1979fc91b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023796853 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_errors.3023796853
Directory /workspace/44.lc_ctrl_errors/latest

Test location /workspace/coverage/default/44.lc_ctrl_jtag_access.3061522415
Short name T473
Test name
Test status
Simulation time 47819176 ps
CPU time 1.14 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:19 PM PDT 24
Peak memory 217084 kb
Host smart-86766547-3162-41db-9968-8f9f65e9aae0
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061522415 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_jtag_access.3061522415
Directory /workspace/44.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/44.lc_ctrl_prog_failure.3600869548
Short name T277
Test name
Test status
Simulation time 124838658 ps
CPU time 3.34 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:21 PM PDT 24
Peak memory 222736 kb
Host smart-44972eba-acb1-4510-b7a0-5457c9e49696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600869548 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_prog_failure.3600869548
Directory /workspace/44.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_mubi.1920247588
Short name T422
Test name
Test status
Simulation time 343188778 ps
CPU time 11.54 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:29 PM PDT 24
Peak memory 218272 kb
Host smart-3c3a7272-e91b-4e4d-9fdc-d0593c42c453
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920247588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_mubi.1920247588
Directory /workspace/44.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_digest.980354234
Short name T562
Test name
Test status
Simulation time 3360780206 ps
CPU time 19.24 seconds
Started Jun 07 08:36:10 PM PDT 24
Finished Jun 07 08:36:34 PM PDT 24
Peak memory 226172 kb
Host smart-650901c3-5379-4c6e-b562-dc8ac81a6fc6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980354234 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_di
gest.980354234
Directory /workspace/44.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/44.lc_ctrl_sec_token_mux.849557439
Short name T484
Test name
Test status
Simulation time 524302164 ps
CPU time 7.24 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:25 PM PDT 24
Peak memory 218260 kb
Host smart-91dae8c0-c8c9-4415-9e56-8da14f5851e2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849557439 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_sec_token_mux.849557439
Directory /workspace/44.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/44.lc_ctrl_smoke.1587671931
Short name T291
Test name
Test status
Simulation time 172878092 ps
CPU time 2.13 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:20 PM PDT 24
Peak memory 214600 kb
Host smart-35b73dd4-9124-48ee-adb0-0f5c5516d673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587671931 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_smoke.1587671931
Directory /workspace/44.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_failure.3678240160
Short name T754
Test name
Test status
Simulation time 339805177 ps
CPU time 22.9 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:41 PM PDT 24
Peak memory 250928 kb
Host smart-0331deff-9e81-47cc-b2b0-110f7f04df81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678240160 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_failure.3678240160
Directory /workspace/44.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/44.lc_ctrl_state_post_trans.3118273355
Short name T369
Test name
Test status
Simulation time 46098936 ps
CPU time 7.64 seconds
Started Jun 07 08:36:11 PM PDT 24
Finished Jun 07 08:36:24 PM PDT 24
Peak memory 250908 kb
Host smart-d266d11c-1de5-4a15-a8b4-4cc3f430c25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118273355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ctrl_state_post_trans.3118273355
Directory /workspace/44.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/44.lc_ctrl_stress_all.2033141795
Short name T644
Test name
Test status
Simulation time 2358543758 ps
CPU time 30.51 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:48 PM PDT 24
Peak memory 226056 kb
Host smart-1da13e7b-53e2-40e3-8e98-ce2a9327daff
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033141795 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
44.lc_ctrl_stress_all.2033141795
Directory /workspace/44.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.lc_ctrl_volatile_unlock_smoke.982880818
Short name T553
Test name
Test status
Simulation time 17350121 ps
CPU time 1.05 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:19 PM PDT 24
Peak memory 212960 kb
Host smart-e6285713-4804-4dab-9895-e0fab3c699dd
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982880818 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.lc_ct
rl_volatile_unlock_smoke.982880818
Directory /workspace/44.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_alert_test.195086519
Short name T260
Test name
Test status
Simulation time 28130239 ps
CPU time 1.14 seconds
Started Jun 07 08:36:14 PM PDT 24
Finished Jun 07 08:36:21 PM PDT 24
Peak memory 208988 kb
Host smart-18defcc5-64aa-4e1f-8d14-f7029d9c7728
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195086519 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_alert_test.195086519
Directory /workspace/45.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.lc_ctrl_errors.1796236834
Short name T698
Test name
Test status
Simulation time 1438209819 ps
CPU time 15.75 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:39 PM PDT 24
Peak memory 218168 kb
Host smart-f05ea6cb-796c-4f4a-885c-4f805d972919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796236834 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_errors.1796236834
Directory /workspace/45.lc_ctrl_errors/latest

Test location /workspace/coverage/default/45.lc_ctrl_jtag_access.1586753239
Short name T858
Test name
Test status
Simulation time 1794598258 ps
CPU time 14.82 seconds
Started Jun 07 08:36:11 PM PDT 24
Finished Jun 07 08:36:31 PM PDT 24
Peak memory 217428 kb
Host smart-2d55b26e-d10d-402e-aec7-7b26d1d47429
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586753239 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_jtag_access.1586753239
Directory /workspace/45.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/45.lc_ctrl_prog_failure.2032520355
Short name T350
Test name
Test status
Simulation time 33770002 ps
CPU time 2.16 seconds
Started Jun 07 08:36:20 PM PDT 24
Finished Jun 07 08:36:28 PM PDT 24
Peak memory 222044 kb
Host smart-dd268f2f-f3b5-4cb0-8848-f1796864b09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032520355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_prog_failure.2032520355
Directory /workspace/45.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_mubi.1434821880
Short name T744
Test name
Test status
Simulation time 1308393976 ps
CPU time 13.43 seconds
Started Jun 07 08:36:11 PM PDT 24
Finished Jun 07 08:36:30 PM PDT 24
Peak memory 218332 kb
Host smart-d242dc8b-d7c5-4bec-b66b-b476521a0839
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434821880 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_mubi.1434821880
Directory /workspace/45.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_digest.3174270151
Short name T249
Test name
Test status
Simulation time 3941262900 ps
CPU time 14.66 seconds
Started Jun 07 08:36:11 PM PDT 24
Finished Jun 07 08:36:31 PM PDT 24
Peak memory 226136 kb
Host smart-82f272a0-a81e-4d61-9f25-605460b0ff25
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174270151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_d
igest.3174270151
Directory /workspace/45.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/45.lc_ctrl_sec_token_mux.42084989
Short name T535
Test name
Test status
Simulation time 197972630 ps
CPU time 7.56 seconds
Started Jun 07 08:36:15 PM PDT 24
Finished Jun 07 08:36:29 PM PDT 24
Peak memory 225016 kb
Host smart-a3795737-79dd-40b5-9aa3-67bae94e35fb
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42084989 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_sec_token_mux.42084989
Directory /workspace/45.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/45.lc_ctrl_security_escalation.4222193988
Short name T801
Test name
Test status
Simulation time 865238791 ps
CPU time 8.7 seconds
Started Jun 07 08:36:14 PM PDT 24
Finished Jun 07 08:36:29 PM PDT 24
Peak memory 224560 kb
Host smart-354fbd9b-8d21-4d04-b655-cf439a7e8173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222193988 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_security_escalation.4222193988
Directory /workspace/45.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/45.lc_ctrl_smoke.3848672147
Short name T646
Test name
Test status
Simulation time 27746715 ps
CPU time 1.84 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:20 PM PDT 24
Peak memory 213996 kb
Host smart-eff76375-8a29-4ad1-8998-397ab4454366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848672147 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_smoke.3848672147
Directory /workspace/45.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_failure.585603367
Short name T596
Test name
Test status
Simulation time 678809838 ps
CPU time 22.31 seconds
Started Jun 07 08:36:16 PM PDT 24
Finished Jun 07 08:36:44 PM PDT 24
Peak memory 250936 kb
Host smart-5454335e-20dd-4c6e-8c4f-f0701c538a7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585603367 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_failure.585603367
Directory /workspace/45.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/45.lc_ctrl_state_post_trans.2870284978
Short name T837
Test name
Test status
Simulation time 83306314 ps
CPU time 7.87 seconds
Started Jun 07 08:36:11 PM PDT 24
Finished Jun 07 08:36:24 PM PDT 24
Peak memory 248376 kb
Host smart-4b5606e1-6e85-4c7f-9acc-2395e477b15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870284978 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ctrl_state_post_trans.2870284978
Directory /workspace/45.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/45.lc_ctrl_stress_all.201997279
Short name T241
Test name
Test status
Simulation time 9682829836 ps
CPU time 144.42 seconds
Started Jun 07 08:36:11 PM PDT 24
Finished Jun 07 08:38:41 PM PDT 24
Peak memory 421652 kb
Host smart-d3768c66-d962-403e-a3a3-5862cb75fc47
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201997279 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
45.lc_ctrl_stress_all.201997279
Directory /workspace/45.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.lc_ctrl_volatile_unlock_smoke.852849944
Short name T538
Test name
Test status
Simulation time 41377585 ps
CPU time 0.85 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:19 PM PDT 24
Peak memory 211864 kb
Host smart-0662a4b3-caa3-4d32-b8c3-79c7cb2834cb
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852849944 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.lc_ct
rl_volatile_unlock_smoke.852849944
Directory /workspace/45.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_alert_test.1501161442
Short name T541
Test name
Test status
Simulation time 16957567 ps
CPU time 0.83 seconds
Started Jun 07 08:36:22 PM PDT 24
Finished Jun 07 08:36:29 PM PDT 24
Peak memory 208912 kb
Host smart-5cb39b00-fcdb-4e9b-854f-7112057f0d5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501161442 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_alert_test.1501161442
Directory /workspace/46.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.lc_ctrl_errors.2084903950
Short name T321
Test name
Test status
Simulation time 212376045 ps
CPU time 7.44 seconds
Started Jun 07 08:36:16 PM PDT 24
Finished Jun 07 08:36:30 PM PDT 24
Peak memory 218236 kb
Host smart-f518af34-9a12-4538-958a-35ae433f90d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084903950 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_errors.2084903950
Directory /workspace/46.lc_ctrl_errors/latest

Test location /workspace/coverage/default/46.lc_ctrl_jtag_access.4206760733
Short name T8
Test name
Test status
Simulation time 1793488468 ps
CPU time 10.41 seconds
Started Jun 07 08:36:16 PM PDT 24
Finished Jun 07 08:36:34 PM PDT 24
Peak memory 217388 kb
Host smart-088005a3-454d-4279-b81d-40c905557429
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206760733 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_jtag_access.4206760733
Directory /workspace/46.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/46.lc_ctrl_prog_failure.3010375706
Short name T246
Test name
Test status
Simulation time 92633035 ps
CPU time 1.38 seconds
Started Jun 07 08:36:14 PM PDT 24
Finished Jun 07 08:36:22 PM PDT 24
Peak memory 218160 kb
Host smart-9c3d63f0-aa6e-4b43-96b9-d29b6ad20cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010375706 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_prog_failure.3010375706
Directory /workspace/46.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_mubi.226687446
Short name T626
Test name
Test status
Simulation time 2112468760 ps
CPU time 13.37 seconds
Started Jun 07 08:36:18 PM PDT 24
Finished Jun 07 08:36:38 PM PDT 24
Peak memory 226032 kb
Host smart-911cbd4c-efe9-4787-8f66-892215541140
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226687446 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_mubi.226687446
Directory /workspace/46.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_digest.309801380
Short name T733
Test name
Test status
Simulation time 514811403 ps
CPU time 14.45 seconds
Started Jun 07 08:36:17 PM PDT 24
Finished Jun 07 08:36:38 PM PDT 24
Peak memory 217840 kb
Host smart-e703a4fa-cfe4-40c4-aebf-12bf51116680
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309801380 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_di
gest.309801380
Directory /workspace/46.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/46.lc_ctrl_sec_token_mux.3915243427
Short name T23
Test name
Test status
Simulation time 3396930251 ps
CPU time 14.45 seconds
Started Jun 07 08:36:16 PM PDT 24
Finished Jun 07 08:36:36 PM PDT 24
Peak memory 218348 kb
Host smart-31cc6789-b4d4-46c4-b341-618b8e0d63a6
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915243427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_sec_token_mux.
3915243427
Directory /workspace/46.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/46.lc_ctrl_security_escalation.3068274480
Short name T203
Test name
Test status
Simulation time 354885218 ps
CPU time 8.11 seconds
Started Jun 07 08:36:14 PM PDT 24
Finished Jun 07 08:36:29 PM PDT 24
Peak memory 218384 kb
Host smart-4ddce712-6a98-4291-81d6-c3a06e7c8d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068274480 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_security_escalation.3068274480
Directory /workspace/46.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/46.lc_ctrl_smoke.607534647
Short name T40
Test name
Test status
Simulation time 51268008 ps
CPU time 2.93 seconds
Started Jun 07 08:36:16 PM PDT 24
Finished Jun 07 08:36:26 PM PDT 24
Peak memory 217852 kb
Host smart-df938c10-213a-4b40-b8fe-ce87fe738ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607534647 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_smoke.607534647
Directory /workspace/46.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_failure.3251403905
Short name T478
Test name
Test status
Simulation time 3061807224 ps
CPU time 21.66 seconds
Started Jun 07 08:36:16 PM PDT 24
Finished Jun 07 08:36:43 PM PDT 24
Peak memory 250860 kb
Host smart-0f95285a-d818-4752-8b55-568bca203dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251403905 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_failure.3251403905
Directory /workspace/46.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/46.lc_ctrl_state_post_trans.483826047
Short name T330
Test name
Test status
Simulation time 190579596 ps
CPU time 6.72 seconds
Started Jun 07 08:36:12 PM PDT 24
Finished Jun 07 08:36:25 PM PDT 24
Peak memory 248508 kb
Host smart-83141594-acfe-49c6-8d43-f4b585dd484e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483826047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_ctrl_state_post_trans.483826047
Directory /workspace/46.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/46.lc_ctrl_stress_all.90337330
Short name T352
Test name
Test status
Simulation time 7034892017 ps
CPU time 74.53 seconds
Started Jun 07 08:36:17 PM PDT 24
Finished Jun 07 08:37:38 PM PDT 24
Peak memory 250740 kb
Host smart-0adcdb2b-90f5-4b6e-9457-f6acb5a8403f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90337330 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4
6.lc_ctrl_stress_all.90337330
Directory /workspace/46.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.lc_ctrl_volatile_unlock_smoke.3611408723
Short name T625
Test name
Test status
Simulation time 19113920 ps
CPU time 0.81 seconds
Started Jun 07 08:36:14 PM PDT 24
Finished Jun 07 08:36:21 PM PDT 24
Peak memory 211744 kb
Host smart-26971af2-d7ac-4d1e-bdfc-299adb0278dc
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611408723 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.lc_c
trl_volatile_unlock_smoke.3611408723
Directory /workspace/46.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_alert_test.1787772033
Short name T679
Test name
Test status
Simulation time 44554762 ps
CPU time 0.93 seconds
Started Jun 07 08:36:18 PM PDT 24
Finished Jun 07 08:36:25 PM PDT 24
Peak memory 209040 kb
Host smart-be49f6ff-d755-4d1c-b7bf-6e40d3cfa108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787772033 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_alert_test.1787772033
Directory /workspace/47.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.lc_ctrl_errors.2390904629
Short name T856
Test name
Test status
Simulation time 414426840 ps
CPU time 18.97 seconds
Started Jun 07 08:36:17 PM PDT 24
Finished Jun 07 08:36:43 PM PDT 24
Peak memory 218228 kb
Host smart-df1d3328-060b-4eb3-93ca-44b7b8d0a62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390904629 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_errors.2390904629
Directory /workspace/47.lc_ctrl_errors/latest

Test location /workspace/coverage/default/47.lc_ctrl_jtag_access.1650554303
Short name T803
Test name
Test status
Simulation time 163503232 ps
CPU time 2.84 seconds
Started Jun 07 08:36:17 PM PDT 24
Finished Jun 07 08:36:26 PM PDT 24
Peak memory 217016 kb
Host smart-091aa0c8-60ab-4c7c-90aa-cad7286fe4cd
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650554303 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_jtag_access.1650554303
Directory /workspace/47.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/47.lc_ctrl_prog_failure.3886729403
Short name T469
Test name
Test status
Simulation time 73816962 ps
CPU time 2.43 seconds
Started Jun 07 08:36:17 PM PDT 24
Finished Jun 07 08:36:26 PM PDT 24
Peak memory 222124 kb
Host smart-07487eb1-33a8-4ffa-aebb-92bcead0b85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886729403 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_prog_failure.3886729403
Directory /workspace/47.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_mubi.3210461168
Short name T101
Test name
Test status
Simulation time 400945945 ps
CPU time 14.44 seconds
Started Jun 07 08:36:24 PM PDT 24
Finished Jun 07 08:36:45 PM PDT 24
Peak memory 218272 kb
Host smart-0e88831f-3a0d-45ca-9996-153077339892
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210461168 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_mubi.3210461168
Directory /workspace/47.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_digest.3166922195
Short name T248
Test name
Test status
Simulation time 227703848 ps
CPU time 8.85 seconds
Started Jun 07 08:36:22 PM PDT 24
Finished Jun 07 08:36:37 PM PDT 24
Peak memory 218256 kb
Host smart-9f255f07-6f28-483a-9067-3d8fabf9e5c3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166922195 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_d
igest.3166922195
Directory /workspace/47.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/47.lc_ctrl_sec_token_mux.1985930951
Short name T702
Test name
Test status
Simulation time 275807568 ps
CPU time 7.14 seconds
Started Jun 07 08:36:19 PM PDT 24
Finished Jun 07 08:36:32 PM PDT 24
Peak memory 226100 kb
Host smart-ed8cc018-3e44-4569-bf64-04f5a0d55219
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985930951 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_sec_token_mux.
1985930951
Directory /workspace/47.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/47.lc_ctrl_security_escalation.3604041091
Short name T601
Test name
Test status
Simulation time 1619445184 ps
CPU time 14.42 seconds
Started Jun 07 08:36:17 PM PDT 24
Finished Jun 07 08:36:38 PM PDT 24
Peak memory 225480 kb
Host smart-bc6b4959-9cf8-4846-9d2a-7d68e63d84b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604041091 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_security_escalation.3604041091
Directory /workspace/47.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/47.lc_ctrl_smoke.3184790491
Short name T71
Test name
Test status
Simulation time 55220963 ps
CPU time 3.18 seconds
Started Jun 07 08:36:17 PM PDT 24
Finished Jun 07 08:36:27 PM PDT 24
Peak memory 214940 kb
Host smart-0e97e050-f54d-4222-bd15-6167b5dcaec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184790491 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_smoke.3184790491
Directory /workspace/47.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_failure.1483305920
Short name T451
Test name
Test status
Simulation time 681732036 ps
CPU time 32.32 seconds
Started Jun 07 08:36:17 PM PDT 24
Finished Jun 07 08:36:56 PM PDT 24
Peak memory 250864 kb
Host smart-4ce8882b-2851-4d8a-8640-bd767df28ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483305920 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_failure.1483305920
Directory /workspace/47.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/47.lc_ctrl_state_post_trans.472354927
Short name T96
Test name
Test status
Simulation time 80203296 ps
CPU time 3.34 seconds
Started Jun 07 08:36:49 PM PDT 24
Finished Jun 07 08:36:57 PM PDT 24
Peak memory 226352 kb
Host smart-a6d31db0-7807-4be3-924b-216e40aba849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472354927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_state_post_trans.472354927
Directory /workspace/47.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all.2135144567
Short name T65
Test name
Test status
Simulation time 39176076966 ps
CPU time 314.68 seconds
Started Jun 07 08:36:23 PM PDT 24
Finished Jun 07 08:41:44 PM PDT 24
Peak memory 283732 kb
Host smart-ccb30faa-c45c-47f8-9959-02742800943f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135144567 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
47.lc_ctrl_stress_all.2135144567
Directory /workspace/47.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.lc_ctrl_stress_all_with_rand_reset.1737893821
Short name T202
Test name
Test status
Simulation time 162487208359 ps
CPU time 546.44 seconds
Started Jun 07 08:36:23 PM PDT 24
Finished Jun 07 08:45:36 PM PDT 24
Peak memory 298704 kb
Host smart-b24f7df1-bfa9-4fb1-a29c-a85f9e856e69
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=1737893821 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_ctrl_stress_all_with_rand_reset.1737893821
Directory /workspace/47.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.lc_ctrl_volatile_unlock_smoke.2652742640
Short name T700
Test name
Test status
Simulation time 52172295 ps
CPU time 1.13 seconds
Started Jun 07 08:36:28 PM PDT 24
Finished Jun 07 08:36:34 PM PDT 24
Peak memory 217776 kb
Host smart-bd5b2295-c143-4ae1-9ec6-154b0c952cb8
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652742640 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.lc_c
trl_volatile_unlock_smoke.2652742640
Directory /workspace/47.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_alert_test.1123825912
Short name T830
Test name
Test status
Simulation time 16770178 ps
CPU time 1.07 seconds
Started Jun 07 08:36:17 PM PDT 24
Finished Jun 07 08:36:25 PM PDT 24
Peak memory 209044 kb
Host smart-8044a6ad-adf0-43ee-ade5-5e08a2d026ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123825912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_alert_test.1123825912
Directory /workspace/48.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.lc_ctrl_errors.207732046
Short name T53
Test name
Test status
Simulation time 2244174543 ps
CPU time 15.15 seconds
Started Jun 07 08:36:35 PM PDT 24
Finished Jun 07 08:36:53 PM PDT 24
Peak memory 218392 kb
Host smart-2bc283ba-8546-4f2d-8f7d-ead15acbaa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207732046 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_errors.207732046
Directory /workspace/48.lc_ctrl_errors/latest

Test location /workspace/coverage/default/48.lc_ctrl_jtag_access.2314525193
Short name T786
Test name
Test status
Simulation time 71006051 ps
CPU time 1.49 seconds
Started Jun 07 08:36:19 PM PDT 24
Finished Jun 07 08:36:27 PM PDT 24
Peak memory 217196 kb
Host smart-8d0b9f54-4bbb-4c9d-a33e-5b16d9c77b81
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314525193 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_jtag_access.2314525193
Directory /workspace/48.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/48.lc_ctrl_prog_failure.3607806063
Short name T848
Test name
Test status
Simulation time 26288496 ps
CPU time 1.36 seconds
Started Jun 07 08:36:18 PM PDT 24
Finished Jun 07 08:36:25 PM PDT 24
Peak memory 218240 kb
Host smart-3cb54f2a-7c9b-40e1-a508-135c3fc245e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607806063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_prog_failure.3607806063
Directory /workspace/48.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_mubi.314385664
Short name T762
Test name
Test status
Simulation time 553413537 ps
CPU time 11.98 seconds
Started Jun 07 08:36:24 PM PDT 24
Finished Jun 07 08:36:42 PM PDT 24
Peak memory 218292 kb
Host smart-ba17432f-f2c8-4680-924f-e6a89c7aa8ab
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314385664 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_mubi.314385664
Directory /workspace/48.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_digest.417616162
Short name T477
Test name
Test status
Simulation time 407794484 ps
CPU time 12.8 seconds
Started Jun 07 08:36:16 PM PDT 24
Finished Jun 07 08:36:35 PM PDT 24
Peak memory 218268 kb
Host smart-ff15621d-36c5-42b7-9ebc-66c145417055
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417616162 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_di
gest.417616162
Directory /workspace/48.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/48.lc_ctrl_sec_token_mux.1107316715
Short name T297
Test name
Test status
Simulation time 5747594626 ps
CPU time 11.17 seconds
Started Jun 07 08:36:23 PM PDT 24
Finished Jun 07 08:36:40 PM PDT 24
Peak memory 218356 kb
Host smart-ef55f179-60d2-416e-8e0d-a25b9cffee5c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107316715 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_sec_token_mux.
1107316715
Directory /workspace/48.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/48.lc_ctrl_security_escalation.3399207209
Short name T447
Test name
Test status
Simulation time 1141011611 ps
CPU time 9.18 seconds
Started Jun 07 08:36:22 PM PDT 24
Finished Jun 07 08:36:38 PM PDT 24
Peak memory 226084 kb
Host smart-7663d3a4-5cca-46f5-9bc8-a443420797a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399207209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_security_escalation.3399207209
Directory /workspace/48.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/48.lc_ctrl_smoke.744230354
Short name T437
Test name
Test status
Simulation time 110551419 ps
CPU time 2.78 seconds
Started Jun 07 08:36:16 PM PDT 24
Finished Jun 07 08:36:26 PM PDT 24
Peak memory 217724 kb
Host smart-acb802c4-cbd7-44ce-be19-ae1f886fe7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744230354 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_smoke.744230354
Directory /workspace/48.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_failure.4185010304
Short name T355
Test name
Test status
Simulation time 236723477 ps
CPU time 32.02 seconds
Started Jun 07 08:36:22 PM PDT 24
Finished Jun 07 08:37:01 PM PDT 24
Peak memory 250920 kb
Host smart-7f288b46-57a4-4a77-983d-a19d64e977bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185010304 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_failure.4185010304
Directory /workspace/48.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/48.lc_ctrl_state_post_trans.1517368075
Short name T772
Test name
Test status
Simulation time 127517380 ps
CPU time 2.88 seconds
Started Jun 07 08:36:18 PM PDT 24
Finished Jun 07 08:36:27 PM PDT 24
Peak memory 218184 kb
Host smart-7926c99c-58f7-4050-b40f-d1b8fd87b186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517368075 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_state_post_trans.1517368075
Directory /workspace/48.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all.3763943604
Short name T514
Test name
Test status
Simulation time 16516300236 ps
CPU time 167.04 seconds
Started Jun 07 08:36:19 PM PDT 24
Finished Jun 07 08:39:12 PM PDT 24
Peak memory 281040 kb
Host smart-169f7c72-6297-4596-a56d-388607ea04e1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763943604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
48.lc_ctrl_stress_all.3763943604
Directory /workspace/48.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.lc_ctrl_stress_all_with_rand_reset.3395181599
Short name T152
Test name
Test status
Simulation time 18942151819 ps
CPU time 636.56 seconds
Started Jun 07 08:36:23 PM PDT 24
Finished Jun 07 08:47:09 PM PDT 24
Peak memory 264700 kb
Host smart-39ddc1de-7c58-48ff-a073-bbb1d382e427
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=3395181599 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_ctrl_stress_all_with_rand_reset.3395181599
Directory /workspace/48.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.lc_ctrl_volatile_unlock_smoke.3599662186
Short name T551
Test name
Test status
Simulation time 21794932 ps
CPU time 0.99 seconds
Started Jun 07 08:36:30 PM PDT 24
Finished Jun 07 08:36:35 PM PDT 24
Peak memory 212952 kb
Host smart-d6ae09f6-53a8-46e5-993e-1f966201164d
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599662186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.lc_c
trl_volatile_unlock_smoke.3599662186
Directory /workspace/48.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_alert_test.3761697021
Short name T730
Test name
Test status
Simulation time 57932302 ps
CPU time 1.04 seconds
Started Jun 07 08:36:30 PM PDT 24
Finished Jun 07 08:36:35 PM PDT 24
Peak memory 209124 kb
Host smart-715d3a9c-66af-4484-af86-a6fceb938603
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761697021 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_alert_test.3761697021
Directory /workspace/49.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.lc_ctrl_errors.2688078271
Short name T752
Test name
Test status
Simulation time 348478145 ps
CPU time 15.33 seconds
Started Jun 07 08:36:30 PM PDT 24
Finished Jun 07 08:36:49 PM PDT 24
Peak memory 218252 kb
Host smart-5ca71508-e780-425d-bce8-87fdc2f607bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688078271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_errors.2688078271
Directory /workspace/49.lc_ctrl_errors/latest

Test location /workspace/coverage/default/49.lc_ctrl_jtag_access.392920987
Short name T695
Test name
Test status
Simulation time 361193241 ps
CPU time 5.4 seconds
Started Jun 07 08:36:25 PM PDT 24
Finished Jun 07 08:36:36 PM PDT 24
Peak memory 217156 kb
Host smart-54ab6b63-e9b3-49af-94f2-8b31eca54632
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392920987 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_jtag_access.392920987
Directory /workspace/49.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/49.lc_ctrl_prog_failure.2456883063
Short name T238
Test name
Test status
Simulation time 48307203 ps
CPU time 2.28 seconds
Started Jun 07 08:36:23 PM PDT 24
Finished Jun 07 08:36:32 PM PDT 24
Peak memory 218220 kb
Host smart-d9333415-79d5-46c2-b3ff-c4d7b991afb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456883063 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_prog_failure.2456883063
Directory /workspace/49.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_mubi.3962871503
Short name T757
Test name
Test status
Simulation time 736662741 ps
CPU time 11.27 seconds
Started Jun 07 08:36:24 PM PDT 24
Finished Jun 07 08:36:41 PM PDT 24
Peak memory 226076 kb
Host smart-b899a35a-e185-43fa-abbb-06bb86d486c1
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962871503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_mubi.3962871503
Directory /workspace/49.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_digest.3921094416
Short name T810
Test name
Test status
Simulation time 283562547 ps
CPU time 10.35 seconds
Started Jun 07 08:36:19 PM PDT 24
Finished Jun 07 08:36:35 PM PDT 24
Peak memory 226120 kb
Host smart-11bc14c8-077e-4d06-b3e5-60f392b1af12
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921094416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_d
igest.3921094416
Directory /workspace/49.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/49.lc_ctrl_sec_token_mux.3043780786
Short name T496
Test name
Test status
Simulation time 560941891 ps
CPU time 10.24 seconds
Started Jun 07 08:36:20 PM PDT 24
Finished Jun 07 08:36:36 PM PDT 24
Peak memory 218288 kb
Host smart-8cdad734-10a2-4ad9-8294-cc79831ef8c8
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043780786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_sec_token_mux.
3043780786
Directory /workspace/49.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/49.lc_ctrl_security_escalation.3686358744
Short name T112
Test name
Test status
Simulation time 814443062 ps
CPU time 6.9 seconds
Started Jun 07 08:36:32 PM PDT 24
Finished Jun 07 08:36:42 PM PDT 24
Peak memory 225268 kb
Host smart-1566dd6b-5e18-4be7-ad9c-aa4c50f81800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686358744 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_security_escalation.3686358744
Directory /workspace/49.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/49.lc_ctrl_smoke.1184454208
Short name T315
Test name
Test status
Simulation time 107612898 ps
CPU time 3.77 seconds
Started Jun 07 08:36:22 PM PDT 24
Finished Jun 07 08:36:32 PM PDT 24
Peak memory 217792 kb
Host smart-569b2df6-7787-4f00-8911-45a219050f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184454208 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_smoke.1184454208
Directory /workspace/49.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_failure.605429707
Short name T410
Test name
Test status
Simulation time 1314408346 ps
CPU time 30.13 seconds
Started Jun 07 08:36:23 PM PDT 24
Finished Jun 07 08:36:59 PM PDT 24
Peak memory 250940 kb
Host smart-98e6a8bf-70fc-44aa-907a-7655c3dc506e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605429707 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_failure.605429707
Directory /workspace/49.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/49.lc_ctrl_state_post_trans.2716485503
Short name T261
Test name
Test status
Simulation time 151864780 ps
CPU time 9.47 seconds
Started Jun 07 08:36:20 PM PDT 24
Finished Jun 07 08:36:36 PM PDT 24
Peak memory 250932 kb
Host smart-8734200e-3fdf-46be-b4bb-5658a124aa9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716485503 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_ctrl_state_post_trans.2716485503
Directory /workspace/49.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/49.lc_ctrl_stress_all.162316006
Short name T85
Test name
Test status
Simulation time 27294799370 ps
CPU time 129.75 seconds
Started Jun 07 08:36:30 PM PDT 24
Finished Jun 07 08:38:44 PM PDT 24
Peak memory 312640 kb
Host smart-e3975b81-a48d-4be8-a24b-4d8ecf62db91
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162316006 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
49.lc_ctrl_stress_all.162316006
Directory /workspace/49.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.lc_ctrl_volatile_unlock_smoke.3442428232
Short name T564
Test name
Test status
Simulation time 96604038 ps
CPU time 0.97 seconds
Started Jun 07 08:36:22 PM PDT 24
Finished Jun 07 08:36:29 PM PDT 24
Peak memory 211908 kb
Host smart-86c682e7-2766-4c3b-a4ee-cd6a50b74d65
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442428232 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.lc_c
trl_volatile_unlock_smoke.3442428232
Directory /workspace/49.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_errors.1435169726
Short name T789
Test name
Test status
Simulation time 255809903 ps
CPU time 10.98 seconds
Started Jun 07 08:34:52 PM PDT 24
Finished Jun 07 08:35:07 PM PDT 24
Peak memory 218260 kb
Host smart-2dcb3327-e705-41dc-afef-4f9f96b3f437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435169726 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_errors.1435169726
Directory /workspace/5.lc_ctrl_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_access.2425927974
Short name T827
Test name
Test status
Simulation time 1733889441 ps
CPU time 5.44 seconds
Started Jun 07 08:34:53 PM PDT 24
Finished Jun 07 08:35:02 PM PDT 24
Peak memory 217444 kb
Host smart-313dbd3d-feaa-414f-be4e-9e706cd61bba
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425927974 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_access.2425927974
Directory /workspace/5.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_errors.1550677525
Short name T99
Test name
Test status
Simulation time 5706139831 ps
CPU time 80 seconds
Started Jun 07 08:34:45 PM PDT 24
Finished Jun 07 08:36:09 PM PDT 24
Peak memory 218952 kb
Host smart-e186da27-571f-4837-9ae8-c302e4bb81f8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550677525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_er
rors.1550677525
Directory /workspace/5.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_priority.356506887
Short name T723
Test name
Test status
Simulation time 303169342 ps
CPU time 2.66 seconds
Started Jun 07 08:34:48 PM PDT 24
Finished Jun 07 08:34:54 PM PDT 24
Peak memory 217780 kb
Host smart-32e35e50-d5e8-47fa-9293-e598a8713a23
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356506887 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_priority.356506887
Directory /workspace/5.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_prog_failure.4284930767
Short name T5
Test name
Test status
Simulation time 138454803 ps
CPU time 5.22 seconds
Started Jun 07 08:34:54 PM PDT 24
Finished Jun 07 08:35:03 PM PDT 24
Peak memory 221944 kb
Host smart-21c2a7e6-f685-4f90-8fd7-c1e29e24fc4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284930767 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag
_prog_failure.4284930767
Directory /workspace/5.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1650965764
Short name T747
Test name
Test status
Simulation time 1182596797 ps
CPU time 23.98 seconds
Started Jun 07 08:34:56 PM PDT 24
Finished Jun 07 08:35:24 PM PDT 24
Peak memory 217780 kb
Host smart-19b9b176-67a5-4077-8a57-4cac42f862b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650965764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_regwen_during_op.1650965764
Directory /workspace/5.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_smoke.3112006170
Short name T392
Test name
Test status
Simulation time 2974126970 ps
CPU time 19.19 seconds
Started Jun 07 08:35:04 PM PDT 24
Finished Jun 07 08:35:33 PM PDT 24
Peak memory 217796 kb
Host smart-0fbd2924-72b4-4ce1-93c7-f55edb73ed1a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112006170 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_smoke.
3112006170
Directory /workspace/5.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_failure.1385155349
Short name T223
Test name
Test status
Simulation time 9692986686 ps
CPU time 67.37 seconds
Started Jun 07 08:34:47 PM PDT 24
Finished Jun 07 08:35:57 PM PDT 24
Peak memory 271536 kb
Host smart-56730d38-7993-4027-a040-8891c55792b8
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1385155349 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jta
g_state_failure.1385155349
Directory /workspace/5.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_jtag_state_post_trans.1061434909
Short name T758
Test name
Test status
Simulation time 2310748588 ps
CPU time 15.33 seconds
Started Jun 07 08:34:55 PM PDT 24
Finished Jun 07 08:35:15 PM PDT 24
Peak memory 250812 kb
Host smart-241f95f8-4faa-4b35-a5b2-5ec3415960b0
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061434909 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_
jtag_state_post_trans.1061434909
Directory /workspace/5.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_prog_failure.3359883376
Short name T755
Test name
Test status
Simulation time 89333663 ps
CPU time 2.4 seconds
Started Jun 07 08:34:56 PM PDT 24
Finished Jun 07 08:35:04 PM PDT 24
Peak memory 222296 kb
Host smart-367b22dd-904f-47dc-a0a5-55210cdb9481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359883376 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_prog_failure.3359883376
Directory /workspace/5.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_regwen_during_op.1005300236
Short name T816
Test name
Test status
Simulation time 2159315771 ps
CPU time 8.13 seconds
Started Jun 07 08:34:47 PM PDT 24
Finished Jun 07 08:34:58 PM PDT 24
Peak memory 217824 kb
Host smart-e4a2261e-55f9-4f49-bb87-5a95f828192d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005300236 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_regwen_during_op.1005300236
Directory /workspace/5.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_mubi.2477365024
Short name T520
Test name
Test status
Simulation time 771225845 ps
CPU time 10.51 seconds
Started Jun 07 08:34:53 PM PDT 24
Finished Jun 07 08:35:09 PM PDT 24
Peak memory 226096 kb
Host smart-b2b0903d-9afd-4a74-9db2-f9a3e3852641
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477365024 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_mubi.2477365024
Directory /workspace/5.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_digest.2649658159
Short name T720
Test name
Test status
Simulation time 1112130950 ps
CPU time 15.71 seconds
Started Jun 07 08:34:52 PM PDT 24
Finished Jun 07 08:35:12 PM PDT 24
Peak memory 226072 kb
Host smart-8f64519c-b913-4c32-97b3-b53b71f50a30
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649658159 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_di
gest.2649658159
Directory /workspace/5.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/5.lc_ctrl_sec_token_mux.3168585749
Short name T571
Test name
Test status
Simulation time 204950819 ps
CPU time 7.12 seconds
Started Jun 07 08:34:51 PM PDT 24
Finished Jun 07 08:35:01 PM PDT 24
Peak memory 226100 kb
Host smart-e1a46dc0-ac26-47f6-85b8-ed985afd2075
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168585749 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_sec_token_mux.3
168585749
Directory /workspace/5.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/5.lc_ctrl_security_escalation.1822777209
Short name T345
Test name
Test status
Simulation time 3311642987 ps
CPU time 7.91 seconds
Started Jun 07 08:34:58 PM PDT 24
Finished Jun 07 08:35:12 PM PDT 24
Peak memory 218352 kb
Host smart-25e22e63-ae10-4080-9540-73b835a507ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822777209 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_security_escalation.1822777209
Directory /workspace/5.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/5.lc_ctrl_smoke.288295535
Short name T425
Test name
Test status
Simulation time 163216526 ps
CPU time 1.97 seconds
Started Jun 07 08:34:51 PM PDT 24
Finished Jun 07 08:34:56 PM PDT 24
Peak memory 214100 kb
Host smart-36e5512c-17c7-498b-8241-989b126defb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288295535 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_smoke.288295535
Directory /workspace/5.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_failure.605705297
Short name T264
Test name
Test status
Simulation time 162047940 ps
CPU time 17.81 seconds
Started Jun 07 08:34:50 PM PDT 24
Finished Jun 07 08:35:10 PM PDT 24
Peak memory 250900 kb
Host smart-a82a317e-956a-45fa-9f34-56dccbcd6a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605705297 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_failure.605705297
Directory /workspace/5.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/5.lc_ctrl_state_post_trans.253021485
Short name T838
Test name
Test status
Simulation time 60254805 ps
CPU time 7.71 seconds
Started Jun 07 08:34:47 PM PDT 24
Finished Jun 07 08:34:58 PM PDT 24
Peak memory 250916 kb
Host smart-0547cc49-2775-4bc1-b26f-5262bfc8c9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253021485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_state_post_trans.253021485
Directory /workspace/5.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all.627567257
Short name T681
Test name
Test status
Simulation time 4728831336 ps
CPU time 64.14 seconds
Started Jun 07 08:34:52 PM PDT 24
Finished Jun 07 08:36:00 PM PDT 24
Peak memory 267320 kb
Host smart-3dc24b23-1ba7-4a4d-9c19-04192e3cbaf2
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627567257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
5.lc_ctrl_stress_all.627567257
Directory /workspace/5.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.24591224
Short name T93
Test name
Test status
Simulation time 21548693115 ps
CPU time 528.65 seconds
Started Jun 07 08:34:50 PM PDT 24
Finished Jun 07 08:43:42 PM PDT 24
Peak memory 316608 kb
Host smart-0dd2e397-2a77-4a68-876f-6fc81b2c41ae
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc
_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see
d=24591224 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_stress_all_with_rand_reset.24591224
Directory /workspace/5.lc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.lc_ctrl_volatile_unlock_smoke.1741355030
Short name T376
Test name
Test status
Simulation time 41280710 ps
CPU time 0.99 seconds
Started Jun 07 08:34:54 PM PDT 24
Finished Jun 07 08:35:00 PM PDT 24
Peak memory 211864 kb
Host smart-18e26443-0e8f-4bd9-b249-4616f2784ec3
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741355030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.lc_ct
rl_volatile_unlock_smoke.1741355030
Directory /workspace/5.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_alert_test.1818032312
Short name T782
Test name
Test status
Simulation time 15055274 ps
CPU time 0.86 seconds
Started Jun 07 08:35:02 PM PDT 24
Finished Jun 07 08:35:10 PM PDT 24
Peak memory 209020 kb
Host smart-4e2e83f5-e2b8-4472-b20e-77ff0362dbb7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818032312 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_alert_test.1818032312
Directory /workspace/6.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.lc_ctrl_claim_transition_if.3450245881
Short name T594
Test name
Test status
Simulation time 20867087 ps
CPU time 0.97 seconds
Started Jun 07 08:34:48 PM PDT 24
Finished Jun 07 08:34:52 PM PDT 24
Peak memory 208988 kb
Host smart-1c247e55-73a1-4024-9a9a-d3f06722def4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450245881 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_claim_transition_if.3450245881
Directory /workspace/6.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/6.lc_ctrl_errors.378700746
Short name T366
Test name
Test status
Simulation time 220539721 ps
CPU time 9.94 seconds
Started Jun 07 08:34:52 PM PDT 24
Finished Jun 07 08:35:06 PM PDT 24
Peak memory 218292 kb
Host smart-7949ca2c-9daf-4572-8b92-16ea5dda8d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378700746 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_errors.378700746
Directory /workspace/6.lc_ctrl_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_access.2470738177
Short name T427
Test name
Test status
Simulation time 71212591 ps
CPU time 2.69 seconds
Started Jun 07 08:34:56 PM PDT 24
Finished Jun 07 08:35:04 PM PDT 24
Peak memory 217080 kb
Host smart-bd1c73c7-d2f2-4aea-87c1-6b4df5f62261
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2470738177 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_access.2470738177
Directory /workspace/6.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_errors.486664595
Short name T47
Test name
Test status
Simulation time 1646029776 ps
CPU time 29.45 seconds
Started Jun 07 08:34:47 PM PDT 24
Finished Jun 07 08:35:20 PM PDT 24
Peak memory 218216 kb
Host smart-99ab7811-4549-40aa-a539-0c54a71c19bb
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486664595 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_err
ors.486664595
Directory /workspace/6.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_priority.1833037340
Short name T559
Test name
Test status
Simulation time 6632810002 ps
CPU time 15.21 seconds
Started Jun 07 08:35:04 PM PDT 24
Finished Jun 07 08:35:29 PM PDT 24
Peak memory 217888 kb
Host smart-95feb9ac-6e9b-49ea-b99b-5067744dd708
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833037340 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_priority.1
833037340
Directory /workspace/6.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_prog_failure.4163064912
Short name T665
Test name
Test status
Simulation time 230929649 ps
CPU time 3.89 seconds
Started Jun 07 08:35:03 PM PDT 24
Finished Jun 07 08:35:16 PM PDT 24
Peak memory 221388 kb
Host smart-65b7390c-9c36-41cf-916c-a312b61bd21f
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4163064912 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag
_prog_failure.4163064912
Directory /workspace/6.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_regwen_during_op.87298954
Short name T685
Test name
Test status
Simulation time 1310837795 ps
CPU time 10.58 seconds
Started Jun 07 08:35:02 PM PDT 24
Finished Jun 07 08:35:19 PM PDT 24
Peak memory 217696 kb
Host smart-0d0f9e74-b07c-4628-a77a-d17d28483c01
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87298954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_r
egwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jt
ag_regwen_during_op.87298954
Directory /workspace/6.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_smoke.3423790456
Short name T77
Test name
Test status
Simulation time 334644752 ps
CPU time 2.65 seconds
Started Jun 07 08:35:04 PM PDT 24
Finished Jun 07 08:35:16 PM PDT 24
Peak memory 217704 kb
Host smart-a9399f92-aa0a-4696-8c75-98c6968b7f7c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423790456 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_smoke.
3423790456
Directory /workspace/6.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_failure.1220040434
Short name T237
Test name
Test status
Simulation time 8957398511 ps
CPU time 76.61 seconds
Started Jun 07 08:35:02 PM PDT 24
Finished Jun 07 08:36:26 PM PDT 24
Peak memory 277376 kb
Host smart-48fb7096-1710-4e70-8d42-1dcd810b0092
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220040434 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jta
g_state_failure.1220040434
Directory /workspace/6.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_jtag_state_post_trans.207798324
Short name T511
Test name
Test status
Simulation time 4073713759 ps
CPU time 20.64 seconds
Started Jun 07 08:34:53 PM PDT 24
Finished Jun 07 08:35:17 PM PDT 24
Peak memory 250896 kb
Host smart-a5638684-36bd-4f69-a433-2960e8cebc55
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207798324 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_j
tag_state_post_trans.207798324
Directory /workspace/6.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_prog_failure.3983108791
Short name T850
Test name
Test status
Simulation time 65907871 ps
CPU time 2.39 seconds
Started Jun 07 08:34:51 PM PDT 24
Finished Jun 07 08:34:57 PM PDT 24
Peak memory 218256 kb
Host smart-10408a1e-41e9-43a2-b872-3827782e3510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983108791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_prog_failure.3983108791
Directory /workspace/6.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_regwen_during_op.1843482683
Short name T86
Test name
Test status
Simulation time 453369734 ps
CPU time 15.12 seconds
Started Jun 07 08:34:50 PM PDT 24
Finished Jun 07 08:35:08 PM PDT 24
Peak memory 217784 kb
Host smart-05435989-5227-4b93-985d-9c9e7785a5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843482683 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_regwen_during_op.1843482683
Directory /workspace/6.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_mubi.623479101
Short name T548
Test name
Test status
Simulation time 369231823 ps
CPU time 12.44 seconds
Started Jun 07 08:34:59 PM PDT 24
Finished Jun 07 08:35:17 PM PDT 24
Peak memory 218324 kb
Host smart-0cc0eeab-fef4-41eb-a6ef-3dc067b425cf
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623479101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_mubi.623479101
Directory /workspace/6.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_digest.4136537667
Short name T357
Test name
Test status
Simulation time 297441348 ps
CPU time 13.61 seconds
Started Jun 07 08:34:49 PM PDT 24
Finished Jun 07 08:35:05 PM PDT 24
Peak memory 218300 kb
Host smart-122bbd7f-adf1-44ed-aa61-d7010771c4a9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136537667 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_di
gest.4136537667
Directory /workspace/6.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/6.lc_ctrl_sec_token_mux.856524941
Short name T736
Test name
Test status
Simulation time 533077620 ps
CPU time 7.02 seconds
Started Jun 07 08:34:59 PM PDT 24
Finished Jun 07 08:35:12 PM PDT 24
Peak memory 218288 kb
Host smart-e69ddf10-95b0-404c-89a3-61f8c13d0f28
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856524941 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_sec_token_mux.856524941
Directory /workspace/6.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/6.lc_ctrl_security_escalation.2124124635
Short name T591
Test name
Test status
Simulation time 910135610 ps
CPU time 9.99 seconds
Started Jun 07 08:35:04 PM PDT 24
Finished Jun 07 08:35:22 PM PDT 24
Peak memory 226052 kb
Host smart-f8ade361-44d0-4e8b-8338-9ca74f31ba0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124124635 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_security_escalation.2124124635
Directory /workspace/6.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/6.lc_ctrl_smoke.1222407719
Short name T683
Test name
Test status
Simulation time 163664979 ps
CPU time 3.19 seconds
Started Jun 07 08:34:49 PM PDT 24
Finished Jun 07 08:34:55 PM PDT 24
Peak memory 214644 kb
Host smart-7e1b3c29-6c07-4fcf-a30c-94302c4ee8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222407719 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_smoke.1222407719
Directory /workspace/6.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_failure.3071694445
Short name T465
Test name
Test status
Simulation time 329209824 ps
CPU time 33.52 seconds
Started Jun 07 08:35:04 PM PDT 24
Finished Jun 07 08:35:46 PM PDT 24
Peak memory 250880 kb
Host smart-bfb13cb7-a1b4-4530-a50c-ae7d48dadcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071694445 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_failure.3071694445
Directory /workspace/6.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/6.lc_ctrl_state_post_trans.2883453146
Short name T734
Test name
Test status
Simulation time 246225256 ps
CPU time 5.58 seconds
Started Jun 07 08:34:51 PM PDT 24
Finished Jun 07 08:35:00 PM PDT 24
Peak memory 246648 kb
Host smart-f6552923-ea09-44b4-86b9-99d0781e5580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883453146 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_state_post_trans.2883453146
Directory /workspace/6.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/6.lc_ctrl_stress_all.870435079
Short name T100
Test name
Test status
Simulation time 7480326081 ps
CPU time 267.98 seconds
Started Jun 07 08:34:58 PM PDT 24
Finished Jun 07 08:39:32 PM PDT 24
Peak memory 250928 kb
Host smart-bd8afc99-f7b2-42d5-bd53-62656d25abb9
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870435079 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_
TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
6.lc_ctrl_stress_all.870435079
Directory /workspace/6.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.lc_ctrl_volatile_unlock_smoke.3791310835
Short name T706
Test name
Test status
Simulation time 14333722 ps
CPU time 0.89 seconds
Started Jun 07 08:35:01 PM PDT 24
Finished Jun 07 08:35:09 PM PDT 24
Peak memory 211912 kb
Host smart-882ef1b0-d240-421f-882d-8243fb790844
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791310835 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.lc_ct
rl_volatile_unlock_smoke.3791310835
Directory /workspace/6.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_alert_test.786368961
Short name T168
Test name
Test status
Simulation time 83825462 ps
CPU time 0.96 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:21 PM PDT 24
Peak memory 208948 kb
Host smart-595e67ea-e8a8-4c5c-95e9-796392120fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786368961 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_alert_test.786368961
Directory /workspace/7.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.lc_ctrl_claim_transition_if.917631225
Short name T614
Test name
Test status
Simulation time 13569659 ps
CPU time 0.85 seconds
Started Jun 07 08:34:54 PM PDT 24
Finished Jun 07 08:34:59 PM PDT 24
Peak memory 208852 kb
Host smart-e316916f-1ff1-4a5e-91eb-50b0ed7aa727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917631225 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_claim_transition_if.917631225
Directory /workspace/7.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/7.lc_ctrl_errors.657990084
Short name T663
Test name
Test status
Simulation time 319092656 ps
CPU time 15.81 seconds
Started Jun 07 08:34:51 PM PDT 24
Finished Jun 07 08:35:11 PM PDT 24
Peak memory 218308 kb
Host smart-5b4faa9a-ef30-4c6b-9abb-7d9d2e3e53d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657990084 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_errors.657990084
Directory /workspace/7.lc_ctrl_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_access.2715390458
Short name T719
Test name
Test status
Simulation time 204830788 ps
CPU time 5.61 seconds
Started Jun 07 08:34:55 PM PDT 24
Finished Jun 07 08:35:05 PM PDT 24
Peak memory 217132 kb
Host smart-da1f5358-e467-49aa-9506-98f141e0fd7f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715390458 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_access.2715390458
Directory /workspace/7.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_errors.3920297305
Short name T250
Test name
Test status
Simulation time 15561381766 ps
CPU time 57.75 seconds
Started Jun 07 08:35:00 PM PDT 24
Finished Jun 07 08:36:04 PM PDT 24
Peak memory 226088 kb
Host smart-e82079e3-8514-4004-a7b1-f7aac80cece5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920297305 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_er
rors.3920297305
Directory /workspace/7.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_priority.724150042
Short name T239
Test name
Test status
Simulation time 2933567629 ps
CPU time 29.53 seconds
Started Jun 07 08:34:51 PM PDT 24
Finished Jun 07 08:35:24 PM PDT 24
Peak memory 217668 kb
Host smart-8d795528-f89f-4a3f-82bc-1c36e40fc897
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724150042 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_priority.724150042
Directory /workspace/7.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_prog_failure.2186599945
Short name T255
Test name
Test status
Simulation time 252194534 ps
CPU time 7.82 seconds
Started Jun 07 08:34:57 PM PDT 24
Finished Jun 07 08:35:10 PM PDT 24
Peak memory 222984 kb
Host smart-a006f0f2-5296-4846-92dd-a359af882072
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186599945 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_prog_failure.2186599945
Directory /workspace/7.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3247791545
Short name T707
Test name
Test status
Simulation time 4125917437 ps
CPU time 34.25 seconds
Started Jun 07 08:35:01 PM PDT 24
Finished Jun 07 08:35:42 PM PDT 24
Peak memory 217768 kb
Host smart-f39fa6bd-1ec4-4db9-a2cc-124dba2e10b5
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247791545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_regwen_during_op.3247791545
Directory /workspace/7.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_smoke.2653076820
Short name T843
Test name
Test status
Simulation time 974119482 ps
CPU time 3.98 seconds
Started Jun 07 08:35:01 PM PDT 24
Finished Jun 07 08:35:12 PM PDT 24
Peak memory 217672 kb
Host smart-80166d27-1d17-4eec-9365-31a33e9f0e07
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653076820 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_smoke.
2653076820
Directory /workspace/7.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_failure.111352809
Short name T367
Test name
Test status
Simulation time 3160877560 ps
CPU time 66.39 seconds
Started Jun 07 08:35:03 PM PDT 24
Finished Jun 07 08:36:17 PM PDT 24
Peak memory 275504 kb
Host smart-1b503903-6f41-44b2-8f69-0ffe7a12cd7e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111352809 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag
_state_failure.111352809
Directory /workspace/7.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_jtag_state_post_trans.2320455530
Short name T641
Test name
Test status
Simulation time 338876301 ps
CPU time 15.84 seconds
Started Jun 07 08:34:53 PM PDT 24
Finished Jun 07 08:35:13 PM PDT 24
Peak memory 250820 kb
Host smart-c8a33801-0392-4fac-88fd-5d807759bf0a
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320455530 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_
jtag_state_post_trans.2320455530
Directory /workspace/7.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_prog_failure.192651869
Short name T726
Test name
Test status
Simulation time 169280430 ps
CPU time 4.28 seconds
Started Jun 07 08:34:48 PM PDT 24
Finished Jun 07 08:34:56 PM PDT 24
Peak memory 222360 kb
Host smart-8158506c-dad4-4535-b45d-bd957f50d9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192651869 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_prog_failure.192651869
Directory /workspace/7.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_regwen_during_op.3736284256
Short name T271
Test name
Test status
Simulation time 1188652828 ps
CPU time 6.67 seconds
Started Jun 07 08:35:04 PM PDT 24
Finished Jun 07 08:35:19 PM PDT 24
Peak memory 217768 kb
Host smart-ff42ff27-8f83-44ac-881e-5fa3b28942bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736284256 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_regwen_during_op.3736284256
Directory /workspace/7.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_mubi.37524402
Short name T306
Test name
Test status
Simulation time 1076821652 ps
CPU time 8.43 seconds
Started Jun 07 08:34:51 PM PDT 24
Finished Jun 07 08:35:03 PM PDT 24
Peak memory 219012 kb
Host smart-7dbc69d8-0147-4792-8c21-45d2814c197e
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37524402 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_mubi.37524402
Directory /workspace/7.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_digest.1635871161
Short name T21
Test name
Test status
Simulation time 265203354 ps
CPU time 10.82 seconds
Started Jun 07 08:34:59 PM PDT 24
Finished Jun 07 08:35:16 PM PDT 24
Peak memory 218256 kb
Host smart-cce39e9f-5208-4b02-9917-a0170922588f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635871161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_di
gest.1635871161
Directory /workspace/7.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/7.lc_ctrl_sec_token_mux.1151135625
Short name T795
Test name
Test status
Simulation time 294684418 ps
CPU time 7.72 seconds
Started Jun 07 08:34:54 PM PDT 24
Finished Jun 07 08:35:06 PM PDT 24
Peak memory 218288 kb
Host smart-6a9a2ea7-0f20-448c-98c5-44ce466cdc71
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151135625 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_sec_token_mux.1
151135625
Directory /workspace/7.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/7.lc_ctrl_smoke.1960086426
Short name T593
Test name
Test status
Simulation time 80280084 ps
CPU time 2.75 seconds
Started Jun 07 08:34:48 PM PDT 24
Finished Jun 07 08:34:53 PM PDT 24
Peak memory 214536 kb
Host smart-3b6058f1-a42c-407a-b3f5-3ddc1b604a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960086426 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_smoke.1960086426
Directory /workspace/7.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_failure.396668575
Short name T158
Test name
Test status
Simulation time 489450998 ps
CPU time 22.9 seconds
Started Jun 07 08:34:59 PM PDT 24
Finished Jun 07 08:35:28 PM PDT 24
Peak memory 250956 kb
Host smart-7408e3f8-e32b-4f27-940f-220dae0cad11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396668575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_failure.396668575
Directory /workspace/7.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/7.lc_ctrl_state_post_trans.3073485028
Short name T254
Test name
Test status
Simulation time 136871902 ps
CPU time 3.63 seconds
Started Jun 07 08:34:54 PM PDT 24
Finished Jun 07 08:35:02 PM PDT 24
Peak memory 218276 kb
Host smart-4e9c87aa-4451-4047-ac38-bb98e0a9a39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073485028 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_state_post_trans.3073485028
Directory /workspace/7.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/7.lc_ctrl_stress_all.7418721
Short name T724
Test name
Test status
Simulation time 29765829231 ps
CPU time 180.02 seconds
Started Jun 07 08:34:56 PM PDT 24
Finished Jun 07 08:38:01 PM PDT 24
Peak memory 421672 kb
Host smart-cfdc20db-c4fb-445a-87a7-8a46d269a44c
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7418721 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TE
ST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
lc_ctrl_stress_all.7418721
Directory /workspace/7.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.lc_ctrl_volatile_unlock_smoke.936184517
Short name T388
Test name
Test status
Simulation time 80165577 ps
CPU time 0.81 seconds
Started Jun 07 08:35:05 PM PDT 24
Finished Jun 07 08:35:15 PM PDT 24
Peak memory 211928 kb
Host smart-caeb396b-1be4-452e-b40c-decdb3e5315c
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=936184517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.lc_ctr
l_volatile_unlock_smoke.936184517
Directory /workspace/7.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_alert_test.3790205257
Short name T799
Test name
Test status
Simulation time 27378325 ps
CPU time 1.05 seconds
Started Jun 07 08:35:02 PM PDT 24
Finished Jun 07 08:35:10 PM PDT 24
Peak memory 209004 kb
Host smart-d220b1b8-fa7c-4cb9-8f7c-6de9d9398866
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790205257 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_alert_test.3790205257
Directory /workspace/8.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.lc_ctrl_claim_transition_if.2022248267
Short name T666
Test name
Test status
Simulation time 10688696 ps
CPU time 0.92 seconds
Started Jun 07 08:35:06 PM PDT 24
Finished Jun 07 08:35:18 PM PDT 24
Peak memory 209004 kb
Host smart-797186f6-9a96-4682-b631-f464a2b048b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022248267 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_claim_transition_if.2022248267
Directory /workspace/8.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/8.lc_ctrl_errors.1593275516
Short name T787
Test name
Test status
Simulation time 1549171944 ps
CPU time 7.61 seconds
Started Jun 07 08:35:05 PM PDT 24
Finished Jun 07 08:35:22 PM PDT 24
Peak memory 218344 kb
Host smart-edf35231-98ce-4094-b5b1-e18994cee02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593275516 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_errors.1593275516
Directory /workspace/8.lc_ctrl_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_access.3481821270
Short name T275
Test name
Test status
Simulation time 207598881 ps
CPU time 1.18 seconds
Started Jun 07 08:34:57 PM PDT 24
Finished Jun 07 08:35:04 PM PDT 24
Peak memory 217076 kb
Host smart-cda411cb-a9a6-4a6e-a40d-72d0d0cb4f75
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481821270 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_access.3481821270
Directory /workspace/8.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_errors.2816598329
Short name T579
Test name
Test status
Simulation time 6010842481 ps
CPU time 46.41 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:36:08 PM PDT 24
Peak memory 218812 kb
Host smart-13ebf7f2-d8ec-45d1-a9c1-8646dbbc127d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816598329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_er
rors.2816598329
Directory /workspace/8.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_priority.2004389103
Short name T852
Test name
Test status
Simulation time 819983599 ps
CPU time 5.64 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:35:27 PM PDT 24
Peak memory 217376 kb
Host smart-6b2b7c8e-f2a5-4f04-888a-819497144a80
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004389103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priori
ty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_priority.2
004389103
Directory /workspace/8.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_prog_failure.3299360497
Short name T847
Test name
Test status
Simulation time 1846280822 ps
CPU time 12.53 seconds
Started Jun 07 08:34:58 PM PDT 24
Finished Jun 07 08:35:16 PM PDT 24
Peak memory 224168 kb
Host smart-47bbab97-1df7-4042-9944-c60acebc18ec
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299360497 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag
_prog_failure.3299360497
Directory /workspace/8.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_regwen_during_op.3419275263
Short name T742
Test name
Test status
Simulation time 3756752537 ps
CPU time 13.29 seconds
Started Jun 07 08:35:09 PM PDT 24
Finished Jun 07 08:35:37 PM PDT 24
Peak memory 217752 kb
Host smart-8957d732-8e25-4707-a769-c592451ab29e
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419275263 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_
jtag_regwen_during_op.3419275263
Directory /workspace/8.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_smoke.2900436207
Short name T82
Test name
Test status
Simulation time 1419543872 ps
CPU time 18.66 seconds
Started Jun 07 08:35:06 PM PDT 24
Finished Jun 07 08:35:35 PM PDT 24
Peak memory 217692 kb
Host smart-cf11d6ae-59e9-4196-8a31-bed962e28b4c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900436207 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_smoke.
2900436207
Directory /workspace/8.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_failure.1937320560
Short name T343
Test name
Test status
Simulation time 5873515475 ps
CPU time 50.99 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:36:10 PM PDT 24
Peak memory 267308 kb
Host smart-888ff8b7-e383-4bdd-bfaf-5dd7ef712302
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937320560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jta
g_state_failure.1937320560
Directory /workspace/8.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_jtag_state_post_trans.421990015
Short name T27
Test name
Test status
Simulation time 1519015952 ps
CPU time 36.44 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:55 PM PDT 24
Peak memory 249884 kb
Host smart-5579afb6-59a0-409c-a050-9b0ea51981c7
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421990015 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_
state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_j
tag_state_post_trans.421990015
Directory /workspace/8.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_prog_failure.4062962886
Short name T109
Test name
Test status
Simulation time 297326436 ps
CPU time 4.05 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:35:25 PM PDT 24
Peak memory 218204 kb
Host smart-b30c57e8-ab5b-4072-95e9-036e3ee2379a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062962886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_prog_failure.4062962886
Directory /workspace/8.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_regwen_during_op.3967005652
Short name T623
Test name
Test status
Simulation time 1498429654 ps
CPU time 8.73 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:29 PM PDT 24
Peak memory 214244 kb
Host smart-edb50266-1dfa-4019-9492-51ae9908c562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967005652 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_regwen_during_op.3967005652
Directory /workspace/8.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_mubi.789406620
Short name T860
Test name
Test status
Simulation time 560662359 ps
CPU time 15.91 seconds
Started Jun 07 08:35:05 PM PDT 24
Finished Jun 07 08:35:32 PM PDT 24
Peak memory 218880 kb
Host smart-79fcc951-daca-479d-942c-3813f30f5690
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789406620 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_mubi.789406620
Directory /workspace/8.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_digest.248338261
Short name T240
Test name
Test status
Simulation time 1287789852 ps
CPU time 13.09 seconds
Started Jun 07 08:35:06 PM PDT 24
Finished Jun 07 08:35:30 PM PDT 24
Peak memory 226136 kb
Host smart-81a169f4-0fdd-41d0-9ddd-cc8ba6d72f60
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248338261 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_di
gest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_dig
est.248338261
Directory /workspace/8.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/8.lc_ctrl_sec_token_mux.493984180
Short name T105
Test name
Test status
Simulation time 223041694 ps
CPU time 8.49 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:35:30 PM PDT 24
Peak memory 218288 kb
Host smart-6ca7e065-3005-42ec-872c-6c1adec35141
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493984180 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mu
x_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_sec_token_mux.493984180
Directory /workspace/8.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/8.lc_ctrl_security_escalation.2900306697
Short name T289
Test name
Test status
Simulation time 1235763284 ps
CPU time 10.86 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:35:36 PM PDT 24
Peak memory 226092 kb
Host smart-389a58b3-f315-45fd-a754-a4adc214345e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900306697 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_security_escalation.2900306697
Directory /workspace/8.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/8.lc_ctrl_smoke.1594801065
Short name T853
Test name
Test status
Simulation time 35034711 ps
CPU time 1.43 seconds
Started Jun 07 08:35:06 PM PDT 24
Finished Jun 07 08:35:18 PM PDT 24
Peak memory 213932 kb
Host smart-5c4b2440-f6bf-44f6-9dc6-28bf5b1433d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594801065 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_smoke.1594801065
Directory /workspace/8.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_failure.101117428
Short name T245
Test name
Test status
Simulation time 232387136 ps
CPU time 26.89 seconds
Started Jun 07 08:35:03 PM PDT 24
Finished Jun 07 08:35:39 PM PDT 24
Peak memory 250896 kb
Host smart-f354a2c4-545f-4801-bcf9-0d40fcfbd438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101117428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_failure.101117428
Directory /workspace/8.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/8.lc_ctrl_state_post_trans.3127678417
Short name T532
Test name
Test status
Simulation time 358022791 ps
CPU time 10.59 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:35:32 PM PDT 24
Peak memory 250900 kb
Host smart-e50ae61a-20a1-46f5-8076-742d6adc31b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127678417 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_state_post_trans.3127678417
Directory /workspace/8.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/8.lc_ctrl_stress_all.18249427
Short name T512
Test name
Test status
Simulation time 1858062210 ps
CPU time 32.53 seconds
Started Jun 07 08:35:12 PM PDT 24
Finished Jun 07 08:35:59 PM PDT 24
Peak memory 220556 kb
Host smart-2396bbdc-f5d3-4d7e-8624-50bddee654aa
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18249427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_T
EST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8
.lc_ctrl_stress_all.18249427
Directory /workspace/8.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.lc_ctrl_volatile_unlock_smoke.1012469623
Short name T274
Test name
Test status
Simulation time 15650175 ps
CPU time 0.92 seconds
Started Jun 07 08:34:59 PM PDT 24
Finished Jun 07 08:35:05 PM PDT 24
Peak memory 212844 kb
Host smart-c46b5f3c-6d31-4d5a-b227-2c2d5e4e4e69
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012469623 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_v
olatile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.lc_ct
rl_volatile_unlock_smoke.1012469623
Directory /workspace/8.lc_ctrl_volatile_unlock_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_alert_test.3532443566
Short name T303
Test name
Test status
Simulation time 60951317 ps
CPU time 1.02 seconds
Started Jun 07 08:35:03 PM PDT 24
Finished Jun 07 08:35:11 PM PDT 24
Peak memory 208956 kb
Host smart-c9aa3fe5-61ed-4560-bd96-a7bb4d533759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532443566 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_alert_test.3532443566
Directory /workspace/9.lc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.lc_ctrl_claim_transition_if.4204383732
Short name T201
Test name
Test status
Simulation time 12128257 ps
CPU time 0.92 seconds
Started Jun 07 08:35:09 PM PDT 24
Finished Jun 07 08:35:23 PM PDT 24
Peak memory 209060 kb
Host smart-650e9287-3c83-46c2-b2f9-034ae616b4c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204383732 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_claim_transition_if.4204383732
Directory /workspace/9.lc_ctrl_claim_transition_if/latest

Test location /workspace/coverage/default/9.lc_ctrl_errors.1066965714
Short name T342
Test name
Test status
Simulation time 782299368 ps
CPU time 11.78 seconds
Started Jun 07 08:34:55 PM PDT 24
Finished Jun 07 08:35:11 PM PDT 24
Peak memory 218368 kb
Host smart-ba5f7ef2-458c-447a-b3d8-82d321e49451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066965714 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_errors.1066965714
Directory /workspace/9.lc_ctrl_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_access.303575621
Short name T817
Test name
Test status
Simulation time 571253697 ps
CPU time 6.24 seconds
Started Jun 07 08:34:55 PM PDT 24
Finished Jun 07 08:35:06 PM PDT 24
Peak memory 217412 kb
Host smart-ab7958f6-8a10-49d8-b47b-9b96d99f9870
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303575621 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_access.303575621
Directory /workspace/9.lc_ctrl_jtag_access/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_errors.3749060186
Short name T309
Test name
Test status
Simulation time 3357907620 ps
CPU time 32.33 seconds
Started Jun 07 08:35:04 PM PDT 24
Finished Jun 07 08:35:45 PM PDT 24
Peak memory 218896 kb
Host smart-0afc3e00-1f55-4d6e-96e2-48d709850f0c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749060186 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_lc_errors_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_er
rors.3749060186
Directory /workspace/9.lc_ctrl_jtag_errors/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_priority.415803485
Short name T659
Test name
Test status
Simulation time 3602623491 ps
CPU time 19.55 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:39 PM PDT 24
Peak memory 217864 kb
Host smart-b9fd22f4-92ab-492e-aaff-ff5ae3fe580f
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415803485 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priorit
y_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_priority.415803485
Directory /workspace/9.lc_ctrl_jtag_priority/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_prog_failure.4029866317
Short name T550
Test name
Test status
Simulation time 625686118 ps
CPU time 3.18 seconds
Started Jun 07 08:35:05 PM PDT 24
Finished Jun 07 08:35:18 PM PDT 24
Peak memory 221780 kb
Host smart-dc7b6554-51b5-49a8-a587-5fd0adeb448d
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029866317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_prog_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag
_prog_failure.4029866317
Directory /workspace/9.lc_ctrl_jtag_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2754177283
Short name T228
Test name
Test status
Simulation time 9047150651 ps
CPU time 10.05 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:35:31 PM PDT 24
Peak memory 217748 kb
Host smart-1cd5c8b8-d1f3-4c33-9586-070468665c67
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754177283 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_regwen_during_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_regwen_during_op.2754177283
Directory /workspace/9.lc_ctrl_jtag_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_smoke.3056516768
Short name T80
Test name
Test status
Simulation time 385698514 ps
CPU time 4.59 seconds
Started Jun 07 08:35:03 PM PDT 24
Finished Jun 07 08:35:16 PM PDT 24
Peak memory 217724 kb
Host smart-4f120a08-4892-40ad-ad6f-c5563937de1b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056516768 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_smoke.
3056516768
Directory /workspace/9.lc_ctrl_jtag_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_failure.3408537406
Short name T298
Test name
Test status
Simulation time 1865051114 ps
CPU time 70.49 seconds
Started Jun 07 08:34:58 PM PDT 24
Finished Jun 07 08:36:14 PM PDT 24
Peak memory 275448 kb
Host smart-cf4e2487-a47f-40c3-bb7f-6eca8033fb1c
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408537406 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_failure_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jta
g_state_failure.3408537406
Directory /workspace/9.lc_ctrl_jtag_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_jtag_state_post_trans.4199439081
Short name T267
Test name
Test status
Simulation time 1039519243 ps
CPU time 22.66 seconds
Started Jun 07 08:34:59 PM PDT 24
Finished Jun 07 08:35:28 PM PDT 24
Peak memory 250840 kb
Host smart-05b28df4-aa79-4882-9607-770a920c2e0b
User root
Command /workspace/default/simv +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d
o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199439081 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl
_state_post_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_
jtag_state_post_trans.4199439081
Directory /workspace/9.lc_ctrl_jtag_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_prog_failure.1957048560
Short name T619
Test name
Test status
Simulation time 228381006 ps
CPU time 3.73 seconds
Started Jun 07 08:35:02 PM PDT 24
Finished Jun 07 08:35:13 PM PDT 24
Peak memory 222504 kb
Host smart-d9ccf6a5-bbbd-47e3-8c14-27f8e338dca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957048560 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_prog_failure.1957048560
Directory /workspace/9.lc_ctrl_prog_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_regwen_during_op.1015300589
Short name T748
Test name
Test status
Simulation time 255585635 ps
CPU time 7.12 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:26 PM PDT 24
Peak memory 214052 kb
Host smart-3df4554a-1d8f-4539-ad5c-bc1111c5e8bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015300589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_regwen_during_op.1015300589
Directory /workspace/9.lc_ctrl_regwen_during_op/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_mubi.3774424410
Short name T464
Test name
Test status
Simulation time 3431334380 ps
CPU time 20.4 seconds
Started Jun 07 08:35:04 PM PDT 24
Finished Jun 07 08:35:34 PM PDT 24
Peak memory 226156 kb
Host smart-ea6b36cf-8293-413b-a1ae-eac3ef6213b4
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774424410 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_mubi.3774424410
Directory /workspace/9.lc_ctrl_sec_mubi/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_digest.2169817556
Short name T761
Test name
Test status
Simulation time 668508774 ps
CPU time 13.7 seconds
Started Jun 07 08:35:02 PM PDT 24
Finished Jun 07 08:35:22 PM PDT 24
Peak memory 218268 kb
Host smart-725f0bc3-0b3c-4c42-abd8-62e97d877937
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169817556 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_d
igest_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_di
gest.2169817556
Directory /workspace/9.lc_ctrl_sec_token_digest/latest

Test location /workspace/coverage/default/9.lc_ctrl_sec_token_mux.2920678575
Short name T857
Test name
Test status
Simulation time 355944240 ps
CPU time 10.07 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:29 PM PDT 24
Peak memory 226084 kb
Host smart-ee63f8e7-1a7a-4e80-92e4-345473cf38a3
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920678575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_m
ux_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_sec_token_mux.2
920678575
Directory /workspace/9.lc_ctrl_sec_token_mux/latest

Test location /workspace/coverage/default/9.lc_ctrl_security_escalation.1391118807
Short name T815
Test name
Test status
Simulation time 1930197047 ps
CPU time 9.08 seconds
Started Jun 07 08:35:01 PM PDT 24
Finished Jun 07 08:35:16 PM PDT 24
Peak memory 218252 kb
Host smart-70ad543d-69ad-4cb2-a349-65d64b03022c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391118807 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_security_escalation.1391118807
Directory /workspace/9.lc_ctrl_security_escalation/latest

Test location /workspace/coverage/default/9.lc_ctrl_smoke.1168751427
Short name T378
Test name
Test status
Simulation time 120121423 ps
CPU time 3.17 seconds
Started Jun 07 08:35:05 PM PDT 24
Finished Jun 07 08:35:19 PM PDT 24
Peak memory 217776 kb
Host smart-c0d75c59-1757-409d-ae88-8a5085eac5d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168751427 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_smoke.1168751427
Directory /workspace/9.lc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_failure.815344266
Short name T435
Test name
Test status
Simulation time 1562462450 ps
CPU time 30.34 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:50 PM PDT 24
Peak memory 250940 kb
Host smart-72040323-4c88-4538-928f-ecde8cdfdd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815344266 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_failure.815344266
Directory /workspace/9.lc_ctrl_state_failure/latest

Test location /workspace/coverage/default/9.lc_ctrl_state_post_trans.1280366311
Short name T714
Test name
Test status
Simulation time 599697697 ps
CPU time 3.25 seconds
Started Jun 07 08:35:02 PM PDT 24
Finished Jun 07 08:35:12 PM PDT 24
Peak memory 218196 kb
Host smart-80152036-ba51-4d5a-b1fa-92f8b15ea711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280366311 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_state_post_trans.1280366311
Directory /workspace/9.lc_ctrl_state_post_trans/latest

Test location /workspace/coverage/default/9.lc_ctrl_stress_all.2320319346
Short name T518
Test name
Test status
Simulation time 2138409634 ps
CPU time 49.88 seconds
Started Jun 07 08:35:08 PM PDT 24
Finished Jun 07 08:36:11 PM PDT 24
Peak memory 250224 kb
Host smart-a02abead-7e64-48bb-ba70-9ed84e0b60f5
User root
Command /workspace/default/simv +create_jtag_riscv_map=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320319346 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM
_TEST_SEQ=lc_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
9.lc_ctrl_stress_all.2320319346
Directory /workspace/9.lc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.lc_ctrl_volatile_unlock_smoke.630136722
Short name T294
Test name
Test status
Simulation time 25971712 ps
CPU time 1.15 seconds
Started Jun 07 08:35:07 PM PDT 24
Finished Jun 07 08:35:21 PM PDT 24
Peak memory 217932 kb
Host smart-b4c73b76-d753-4497-9778-c3abf4f94f92
User root
Command /workspace/default/simv +en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do
/workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630136722 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_vo
latile_unlock_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.lc_ctr
l_volatile_unlock_smoke.630136722
Directory /workspace/9.lc_ctrl_volatile_unlock_smoke/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%