Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	1	63	98.44
Crosses	60	0	60	100.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	0	2	100.00	100	1	1	2
esc_scrap_state1_i_cp	2	0	2	100.00	100	1	1	2
fsm_state_q	15	0	15	100.00	100	1	1	0
fsm_state_q_cp	45	1	44	97.78	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	0	30	100.00	100	1	1	0
scrap_state1_xp	30	0	30	100.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104903598

1

T1

1838

T2

432459

T3

716

auto[1]

1358138

1

T2

1779

T4

297

T5

5233

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

104887534

1

T1

1838

T2

431667

T3

716

auto[1]

1374202

1

T2

2571

T4

99

T5

3852

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	0	15	100.00

Automatically Generated Bins for fsm_state_q

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	7001867	1			T1	93		T2	28298		T3	83
auto[IdleSt]	21663392	1			T1	1745		T2	195846		T3	633
auto[ClkMuxSt]	36684	1			T2	288		T4	5		T5	26
auto[CntIncrSt]	36376	1			T2	288		T4	5		T5	26
auto[CntProgSt]	1851774	1			T2	7122		T4	95		T5	52
auto[TransCheckSt]	28412	1			T2	215		T4	5		T5	6
auto[TokenHashSt]	46002101	1			T2	14334		T4	5186		T5	566
auto[FlashRmaSt]	29592	1			T2	132		T4	18		T5	6
auto[TokenCheck0St]	13021	1			T2	70		T4	5		T5	6
auto[TokenCheck1St]	9587	1			T2	46		T4	5		T5	6
auto[TransProgSt]	481246	1			T2	1736		T4	131		T5	12
auto[PostTransSt]	13154510	1			T2	153152		T4	849		T5	29066
auto[ScrapSt]	124993	1			T22	3		T33	9		T17	5955
auto[EscalateSt]	6260578	1			T2	20448		T4	723		T5	25858
auto[InvalidSt]	9565712	1			T2	12263		T4	314		T5	16187

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	1	44	97.78

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	1891	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
InvalidSt	9565712	1			T2	12263		T4	314		T5	16187
EscalateSt	6260578	1			T2	20448		T4	723		T5	25858
ScrapSt	124993	1			T22	3		T33	9		T17	5955
PostTransSt	13154510	1			T2	153152		T4	849		T5	29066
TransProgSt	481246	1			T2	1736		T4	131		T5	12
TokenCheck1St	9587	1			T2	46		T4	5		T5	6
TokenCheck0St	13021	1			T2	70		T4	5		T5	6
FlashRmaSt	29592	1			T2	132		T4	18		T5	6
TokenHashSt	46002101	1			T2	14334		T4	5186		T5	566
TransCheckSt	28412	1			T2	215		T4	5		T5	6
CntProgSt	1851774	1			T2	7122		T4	95		T5	52
CntIncrSt	36376	1			T2	288		T4	5		T5	26
ClkMuxSt	36684	1			T2	288		T4	5		T5	26
IdleSt	21663392	1			T1	1745		T2	195846		T3	633
ResetSt	7001867	1			T1	93		T2	28298		T3	83
arcs[ResetSt=>IdleSt]	54280	1			T1	1		T2	300		T3	1
arcs[IdleSt=>ScrapSt]	306	1			T22	1		T33	1		T17	6
arcs[IdleSt=>ClkMuxSt]	36445	1			T2	288		T4	5		T5	26
arcs[ClkMuxSt=>CntIncrSt]	36376	1			T2	288		T4	5		T5	26
arcs[CntIncrSt=>PostTransSt]	1964	1			T2	35		T15	11		T16	11
arcs[CntIncrSt=>CntProgSt]	34330	1			T2	253		T4	5		T5	26
arcs[CntProgSt=>PostTransSt]	4763	1			T2	38		T5	20		T11	20
arcs[CntProgSt=>TransCheckSt]	28412	1			T2	215		T4	5		T5	6
arcs[TransCheckSt=>PostTransSt]	3892	1			T2	24		T13	47		T15	9
arcs[TransCheckSt=>TokenHashSt]	24428	1			T2	191		T4	5		T5	6
arcs[TokenHashSt=>PostTransSt]	10657	1			T2	121		T11	6		T12	1
arcs[TokenHashSt=>FlashRmaSt]	13140	1			T2	70		T4	5		T5	6
arcs[FlashRmaSt=>TokenCheck0St]	13021	1			T2	70		T4	5		T5	6
arcs[TokenCheck0St=>PostTransSt]	3399	1			T2	24		T11	18		T13	28
arcs[TokenCheck0St=>TokenCheck1St]	9587	1			T2	46		T4	5		T5	6
arcs[TokenCheck1St=>PostTransSt]	691	1			T13	15		T15	4		T20	6
arcs[TransProgSt=>PostTransSt]	7971	1			T2	46		T4	5		T5	6
arcs[IdleSt=>EscalateSt]	190	1			T22	2		T44	10		T45	6
arcs[ClkMuxSt=>EscalateSt]	69	1			T44	3		T45	4		T46	1
arcs[CntIncrSt=>EscalateSt]	82	1			T22	2		T44	2		T45	1
arcs[CntProgSt=>EscalateSt]	1155	1			T22	9		T44	12		T45	17
arcs[TransCheckSt=>EscalateSt]	92	1			T22	6		T44	5		T46	7
arcs[TokenHashSt=>EscalateSt]	630	1			T22	12		T17	1		T44	15
arcs[FlashRmaSt=>EscalateSt]	119	1			T22	3		T44	3		T45	3
arcs[TokenCheck0St=>EscalateSt]	35	1			T46	1		T47	1		T48	1
arcs[TokenCheck1St=>EscalateSt]	144	1			T22	1		T44	4		T45	3
arcs[TransProgSt=>EscalateSt]	781	1			T22	8		T44	8		T45	14
arcs[PostTransSt=>EscalateSt]	4976	1			T2	38		T5	20		T11	20
arcs[InvalidSt=>EscalateSt]	13377	1			T2	6		T4	4		T5	72

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state0_xp

Bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7001674	1			T1	93		T2	28298		T3	83
auto[0]	auto[IdleSt]	21663265	1			T1	1745		T2	195846		T3	633
auto[0]	auto[ClkMuxSt]	36639	1			T2	288		T4	5		T5	26
auto[0]	auto[CntIncrSt]	36315	1			T2	288		T4	5		T5	26
auto[0]	auto[CntProgSt]	1851005	1			T2	7122		T4	95		T5	52
auto[0]	auto[TransCheckSt]	28354	1			T2	215		T4	5		T5	6
auto[0]	auto[TokenHashSt]	46001673	1			T2	14334		T4	5186		T5	566
auto[0]	auto[FlashRmaSt]	29514	1			T2	132		T4	18		T5	6
auto[0]	auto[TokenCheck0St]	12994	1			T2	70		T4	5		T5	6
auto[0]	auto[TokenCheck1St]	9490	1			T2	46		T4	5		T5	6
auto[0]	auto[TransProgSt]	480720	1			T2	1736		T4	131		T5	12
auto[0]	auto[PostTransSt]	13151997	1			T2	153137		T4	849		T5	29054
auto[0]	auto[ScrapSt]	124958	1			T22	2		T33	9		T17	5955
auto[0]	auto[EscalateSt]	4913963	1			T2	18687		T4	429		T5	20678
auto[0]	auto[InvalidSt]	9559146	1			T2	12260		T4	311		T5	16146
auto[1]	auto[ResetSt]	193	1			T22	2		T44	4		T45	3
auto[1]	auto[IdleSt]	127	1			T22	2		T44	8		T45	3
auto[1]	auto[ClkMuxSt]	45	1			T44	2		T45	1		T46	1
auto[1]	auto[CntIncrSt]	61	1			T22	2		T44	2		T45	1
auto[1]	auto[CntProgSt]	769	1			T22	5		T44	6		T45	14
auto[1]	auto[TransCheckSt]	58	1			T22	3		T44	3		T46	5
auto[1]	auto[TokenHashSt]	428	1			T22	10		T17	1		T44	8
auto[1]	auto[FlashRmaSt]	78	1			T22	2		T44	2		T45	1
auto[1]	auto[TokenCheck0St]	27	1			T46	1		T47	1		T215	1
auto[1]	auto[TokenCheck1St]	97	1			T44	3		T45	3		T46	6
auto[1]	auto[TransProgSt]	526	1			T22	7		T44	7		T45	10
auto[1]	auto[PostTransSt]	2513	1			T2	15		T5	12		T11	10
auto[1]	auto[ScrapSt]	35	1			T22	1		T47	1		T48	1
auto[1]	auto[EscalateSt]	1346615	1			T2	1761		T4	294		T5	5180
auto[1]	auto[InvalidSt]	6566	1			T2	3		T4	3		T5	41

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	0	30	100.00

Automatically Generated Cross Bins for scrap_state1_xp

Bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[ResetSt]	7001698	1			T1	93		T2	28298		T3	83
auto[0]	auto[IdleSt]	21663255	1			T1	1745		T2	195846		T3	633
auto[0]	auto[ClkMuxSt]	36631	1			T2	288		T4	5		T5	26
auto[0]	auto[CntIncrSt]	36320	1			T2	288		T4	5		T5	26
auto[0]	auto[CntProgSt]	1850995	1			T2	7122		T4	95		T5	52
auto[0]	auto[TransCheckSt]	28353	1			T2	215		T4	5		T5	6
auto[0]	auto[TokenHashSt]	46001695	1			T2	14334		T4	5186		T5	566
auto[0]	auto[FlashRmaSt]	29512	1			T2	132		T4	18		T5	6
auto[0]	auto[TokenCheck0St]	12999	1			T2	70		T4	5		T5	6
auto[0]	auto[TokenCheck1St]	9495	1			T2	46		T4	5		T5	6
auto[0]	auto[TransProgSt]	480725	1			T2	1736		T4	131		T5	12
auto[0]	auto[PostTransSt]	13151982	1			T2	153129		T4	849		T5	29058
auto[0]	auto[ScrapSt]	124948	1			T22	3		T33	9		T17	5955
auto[0]	auto[EscalateSt]	4898134	1			T2	17903		T4	625		T5	22045
auto[0]	auto[InvalidSt]	9558901	1			T2	12260		T4	313		T5	16156
auto[1]	auto[ResetSt]	169	1			T22	3		T44	2		T45	1
auto[1]	auto[IdleSt]	137	1			T22	1		T44	7		T45	4
auto[1]	auto[ClkMuxSt]	53	1			T44	3		T45	3		T46	1
auto[1]	auto[CntIncrSt]	56	1			T44	1		T46	4		T47	4
auto[1]	auto[CntProgSt]	779	1			T22	7		T44	10		T45	14
auto[1]	auto[TransCheckSt]	59	1			T22	5		T44	4		T46	4
auto[1]	auto[TokenHashSt]	406	1			T22	6		T44	12		T45	1
auto[1]	auto[FlashRmaSt]	80	1			T22	2		T44	3		T45	3
auto[1]	auto[TokenCheck0St]	22	1			T46	1		T47	1		T48	1
auto[1]	auto[TokenCheck1St]	92	1			T22	1		T44	2		T45	2
auto[1]	auto[TransProgSt]	521	1			T22	5		T44	3		T45	11
auto[1]	auto[PostTransSt]	2528	1			T2	23		T5	8		T11	10
auto[1]	auto[ScrapSt]	45	1			T47	1		T48	1		T216	2
auto[1]	auto[EscalateSt]	1362444	1			T2	2545		T4	98		T5	3813
auto[1]	auto[InvalidSt]	6811	1			T2	3		T4	1		T5	31